From 62a3aa000055efcc86483e8953775943513fe44d Mon Sep 17 00:00:00 2001 From: Sneh Mankad Date: Wed, 10 Jun 2026 11:46:58 +0530 Subject: [PATCH 001/130] pinctrl: qcom: Avoid assigning unused private context in test cases tlmm_test_rising_while_disabled() sets thread_op_remain to 10, but this variable is only used by the threaded IRQ handler to control the number of GPIO pin toggles. Since tlmm_test_rising_while_disabled() does not register a threaded IRQ handler, the assignment is never used. Similarly, tlmm_test_high() and tlmm_test_low() set intr_op_remain to 9, but the variable is used to denote the IRQ handler the number of times GPIO signal has to be toggled from the hard IRQ handler. Since tlmm_test_high() and tlmm_test_low() themselves toggle the signal and do not require the hard IRQ handler to do it, the assignment is never used. Remove the thread_op_remain assignment from tlmm_test_rising_while_disabled() and intr_op_remain assignment from tlmm_test_high() and tlmm_test_low() test cases. This does not cause any change in functionality. Signed-off-by: Sneh Mankad Link: https://patch.msgid.link/20260610-tlmm_test_changes-v2-1-f34536da4717@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski --- drivers/pinctrl/qcom/tlmm-test.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/pinctrl/qcom/tlmm-test.c b/drivers/pinctrl/qcom/tlmm-test.c index 007d6539cece..13c417731be7 100644 --- a/drivers/pinctrl/qcom/tlmm-test.c +++ b/drivers/pinctrl/qcom/tlmm-test.c @@ -273,7 +273,6 @@ static void tlmm_test_low(struct kunit *test) int i; priv->intr_op = TLMM_TEST_COUNT | TLMM_TEST_OUTPUT_HIGH; - atomic_set(&priv->intr_op_remain, 9); tlmm_output_high(); @@ -298,7 +297,6 @@ static void tlmm_test_high(struct kunit *test) int i; priv->intr_op = TLMM_TEST_COUNT | TLMM_TEST_OUTPUT_LOW; - atomic_set(&priv->intr_op_remain, 9); tlmm_output_low(); @@ -521,7 +519,6 @@ static void tlmm_test_rising_while_disabled(struct kunit *test) unsigned int before_edge; priv->intr_op = TLMM_TEST_COUNT; - atomic_set(&priv->thread_op_remain, 10); tlmm_output_low(); From 7b1272d02e65d2d4aeffb0d85b290a8753d24c12 Mon Sep 17 00:00:00 2001 From: Felix Gu Date: Sat, 23 May 2026 18:27:05 +0800 Subject: [PATCH 002/130] pinctrl: imx1: fix device_node leak in dt_is_flat_functions() for_each_child_of_node() holds a reference on the iterator node that must be released on early return. imx1_pinctrl_dt_is_flat_functions() has two early return paths inside the loop that skip this cleanup. Replace both loops with the scoped variant so that the reference is automatically dropped when the iterator goes out of scope. Fixes: 63d2059cd665 ("pinctrl: imx1: Allow parsing DT without function nodes") Signed-off-by: Felix Gu Reviewed-by: Frank Li Signed-off-by: Linus Walleij --- drivers/pinctrl/freescale/pinctrl-imx1-core.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/freescale/pinctrl-imx1-core.c b/drivers/pinctrl/freescale/pinctrl-imx1-core.c index b7bd4ef9c0db..4a6bdaefa42f 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx1-core.c +++ b/drivers/pinctrl/freescale/pinctrl-imx1-core.c @@ -547,14 +547,11 @@ static int imx1_pinctrl_parse_functions(struct device_node *np, */ static bool imx1_pinctrl_dt_is_flat_functions(struct device_node *np) { - struct device_node *function_np; - struct device_node *pinctrl_np; - - for_each_child_of_node(np, function_np) { + for_each_child_of_node_scoped(np, function_np) { if (of_property_present(function_np, "fsl,pins")) return true; - for_each_child_of_node(function_np, pinctrl_np) { + for_each_child_of_node_scoped(function_np, pinctrl_np) { if (of_property_present(pinctrl_np, "fsl,pins")) return false; } From a400058351f4ecb7c6f5609c7fa017f5d7ef9d06 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Tue, 16 Jun 2026 09:37:08 +0200 Subject: [PATCH 003/130] MAINTAINERS: add myself as the maintainer for Qualcomm pin control drivers Linus Walleij expresed the need for a dedicated maintainer for Qualcomm pin control drivers which receive a lot more changes lately. Qualcomm volunteered me for this role so add an entry to MAINTAINERS. Signed-off-by: Bartosz Golaszewski Signed-off-by: Linus Walleij --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 15011f5752a9..1c9a9bbd2564 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22342,6 +22342,13 @@ L: linux-arm-msm@vger.kernel.org S: Maintained F: drivers/firmware/qcom/qcom_qseecom_uefisecapp.c +QUALCOMM PINCTRL DRIVERS +M: Bartosz Golaszewski +L: linux-arm-msm@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/pinctrl/qcom,*.yaml +F: drivers/pinctrl/qcom/ + QUALCOMM RMNET DRIVER M: Subash Abhinov Kasiviswanathan M: Sean Tranchetti From 5a653cedec948423fc8a0180c90b8d05c2239d9d Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Wed, 27 May 2026 13:23:17 -0700 Subject: [PATCH 004/130] pinctrl: renesas: rza2: Embed pins in the priv struct Turn the separately allocated pinctrl_pin_desc array into a flexible array member of struct rza2_pinctrl_priv, annotated with __counted_by(npins). Compute the pin count before allocation so struct_size() can size the combined object, and the two allocations can be collapsed into one. Change npins to unsigned int to avoid potential overflow/underflow errors. Assisted-by: Claude:Opus-4.7 Signed-off-by: Rosen Penev Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260527202317.5347-1-rosenp@gmail.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rza2.c | 26 +++++++++++--------------- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rza2.c b/drivers/pinctrl/renesas/pinctrl-rza2.c index 8618f32ed26a..4cab641c3350 100644 --- a/drivers/pinctrl/renesas/pinctrl-rza2.c +++ b/drivers/pinctrl/renesas/pinctrl-rza2.c @@ -44,12 +44,12 @@ struct rza2_pinctrl_priv { struct device *dev; void __iomem *base; - struct pinctrl_pin_desc *pins; struct pinctrl_desc desc; struct pinctrl_dev *pctl; struct pinctrl_gpio_range gpio_range; - int npins; + unsigned int npins; struct mutex mutex; /* serialize adding groups and functions */ + struct pinctrl_pin_desc pins[] __counted_by(npins); }; #define RZA2_PDR(port) (0x0000 + (port) * 2) /* Direction 16-bit */ @@ -289,21 +289,15 @@ static int rza2_gpio_register(struct rza2_pinctrl_priv *priv) static int rza2_pinctrl_register(struct rza2_pinctrl_priv *priv) { - struct pinctrl_pin_desc *pins; unsigned int i; int ret; - pins = devm_kcalloc(priv->dev, priv->npins, sizeof(*pins), GFP_KERNEL); - if (!pins) - return -ENOMEM; - - priv->pins = pins; - priv->desc.pins = pins; + priv->desc.pins = priv->pins; priv->desc.npins = priv->npins; for (i = 0; i < priv->npins; i++) { - pins[i].number = i; - pins[i].name = rza2_gpio_names[i]; + priv->pins[i].number = i; + priv->pins[i].name = rza2_gpio_names[i]; } ret = devm_pinctrl_register_and_init(priv->dev, &priv->desc, priv, @@ -482,12 +476,17 @@ static const struct pinmux_ops rza2_pinmux_ops = { static int rza2_pinctrl_probe(struct platform_device *pdev) { struct rza2_pinctrl_priv *priv; + unsigned int npins; int ret; - priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + npins = (uintptr_t)of_device_get_match_data(&pdev->dev) * + RZA2_PINS_PER_PORT; + + priv = devm_kzalloc(&pdev->dev, struct_size(priv, pins, npins), GFP_KERNEL); if (!priv) return -ENOMEM; + priv->npins = npins; priv->dev = &pdev->dev; priv->base = devm_platform_ioremap_resource(pdev, 0); @@ -498,9 +497,6 @@ static int rza2_pinctrl_probe(struct platform_device *pdev) platform_set_drvdata(pdev, priv); - priv->npins = (int)(uintptr_t)of_device_get_match_data(&pdev->dev) * - RZA2_PINS_PER_PORT; - priv->desc.name = DRIVER_NAME; priv->desc.pctlops = &rza2_pinctrl_ops; priv->desc.pmxops = &rza2_pinmux_ops; From b8cfe283784b9e7836c1f6a0ca2c60c9494dd36e Mon Sep 17 00:00:00 2001 From: Billy Tsai Date: Tue, 16 Jun 2026 11:30:01 +0800 Subject: [PATCH 005/130] dt-bindings: pinctrl: aspeed,ast2700-soc1: Add JTAGM1TRST group The TRST signal of the JTAG master is optional and may not be wired on every design, but it is only selectable as part of the JTAGM1 group, which forces the D12 ball to be muxed whenever the JTAG master is used. Add a separate JTAGM1TRST group so boards can enable TRST independently of the other JTAG master signals. Signed-off-by: Billy Tsai Acked-by: Conor Dooley Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml index 76944fd14e2c..fe7cef4fef6a 100644 --- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml @@ -356,6 +356,7 @@ patternProperties: - I3C8 - I3C9 - JTAGM1 + - JTAGM1TRST - LPC0 - LPC1 - LTPI From 7a8a6e1cfcb69cdd5b353e6ac222b4294006e108 Mon Sep 17 00:00:00 2001 From: Billy Tsai Date: Tue, 16 Jun 2026 11:30:02 +0800 Subject: [PATCH 006/130] pinctrl: aspeed: Split TRST out of the AST2700 SoC1 JTAGM1 group The JTAGM1 group includes the D12 ball carrying the TRST signal, but TRST is optional for a JTAG master and the ball may be needed for other functions on designs that do not wire it. With TRST embedded in the group, such designs cannot use the JTAG master at all. Move D12 into a new JTAGM1TRST group under the same JTAGM1 function so TRST is muxed only when a board requests it. Boards that do use TRST now need to select both the JTAGM1 and JTAGM1TRST groups. Signed-off-by: Billy Tsai Signed-off-by: Linus Walleij --- drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c index 50027d69c342..f8b4066699ce 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c @@ -1018,7 +1018,8 @@ PIN_GROUP(I3C6, AA22, AB20); PIN_GROUP(I3C7, AF18, AE19); PIN_GROUP(I3C8, AD20, AC20); PIN_GROUP(I3C9, AA21, AB21); -PIN_GROUP(JTAGM1, D12, F10, E11, F11, F13); +PIN_GROUP(JTAGM1, F10, E11, F11, F13); +PIN_GROUP(JTAGM1TRST, D12); PIN_GROUP(LPC0, AF26, AF25, B16, D14, B15, B14, C17, B13, E14, C15); PIN_GROUP(LPC1, C16, C14, C11, D9, F14, D10, C12, C13, AE16, AE17); PIN_GROUP(LTPI, U25, U26, Y26, AA24); @@ -1263,6 +1264,7 @@ static const struct pingroup aspeed_g7_soc1_groups[] = { GROUP(I3C8), GROUP(I3C9), GROUP(JTAGM1), + GROUP(JTAGM1TRST), GROUP(LPC0), GROUP(LPC1), GROUP(LTPI), @@ -1528,7 +1530,7 @@ static const struct aspeed_g7_soc1_function aspeed_g7_soc1_functions[] = { FUNC(I3C7, (1), "I3C7"), FUNC(I3C8, (1), "I3C8"), FUNC(I3C9, (1), "I3C9"), - FUNC(JTAGM1, (1), "JTAGM1"), + FUNC(JTAGM1, (1, 1), "JTAGM1", "JTAGM1TRST"), FUNC(LPC0, (2), "LPC0"), FUNC(LPC1, (2), "LPC1"), FUNC(LTPI, (2), "LTPI"), From 32711f77db0641e57fd96fdc013bf1286b9f2514 Mon Sep 17 00:00:00 2001 From: Daniel McCarthy Date: Thu, 18 Jun 2026 01:04:51 +0300 Subject: [PATCH 007/130] pinctrl: bcm2835: Don't remove an unregistered GPIO chip If the devm_pinctrl_register() function fails, bcm2835_pinctrl_probe() calls gpiochip_remove() before gpiochip_add_data() has registered the GPIO chip. This means that upon failure the gpio_chip.gpiodev is NULL resulting in a null pointer dereference inside the gpiochip_remove() function. Remove the unnecessary function call to gpiochip_remove(). No GPIO cleanup is required because the GPIO chip has not yet been registered. Without this change there is potential for a kernel panic upon registration failure Fixes: 266423e60ea1 ("pinctrl: bcm2835: Change init order for gpio hogs") Signed-off-by: Daniel McCarthy Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/pinctrl-bcm2835.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c index e7b35019a5a7..725e880ae086 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c @@ -1350,7 +1350,6 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) pc->pctl_desc = *pdata->pctl_desc; pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc); if (IS_ERR(pc->pctl_dev)) { - gpiochip_remove(&pc->gpio_chip); return PTR_ERR(pc->pctl_dev); } From 076df055a505aa4ce36b92eba8525fca76c9b213 Mon Sep 17 00:00:00 2001 From: Igor Putko Date: Thu, 18 Jun 2026 18:56:25 +0300 Subject: [PATCH 008/130] gpio: tb10x: use unsigned int instead of bare unsigned Fix the checkpatch.pl warning by using 'unsigned int' instead of the bare use of 'unsigned' for the offset parameter in tb10x_gpio_to_irq(). Signed-off-by: Igor Putko Signed-off-by: Linus Walleij --- drivers/gpio/gpio-tb10x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-tb10x.c b/drivers/gpio/gpio-tb10x.c index 705bfd80a8d0..d30524dbc841 100644 --- a/drivers/gpio/gpio-tb10x.c +++ b/drivers/gpio/gpio-tb10x.c @@ -51,7 +51,7 @@ static inline u32 tb10x_reg_read(struct tb10x_gpio *gpio, unsigned int offs) return ioread32(gpio->base + offs); } -static int tb10x_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +static int tb10x_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) { struct tb10x_gpio *tb10x_gpio = gpiochip_get_data(chip); From a1636f548c497cedf001238c879eae9e271b5809 Mon Sep 17 00:00:00 2001 From: Igor Putko Date: Thu, 18 Jun 2026 18:56:26 +0300 Subject: [PATCH 009/130] gpio: tb10x: remove unnecessary braces Fix the checkpatch.pl warning by removing unnecessary braces from a single-statement if-block in tb10x_gpio_probe(). Signed-off-by: Igor Putko Signed-off-by: Linus Walleij --- drivers/gpio/gpio-tb10x.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpio/gpio-tb10x.c b/drivers/gpio/gpio-tb10x.c index d30524dbc841..7fb8e6223bd1 100644 --- a/drivers/gpio/gpio-tb10x.c +++ b/drivers/gpio/gpio-tb10x.c @@ -167,9 +167,8 @@ static int tb10x_gpio_probe(struct platform_device *pdev) tb10x_gpio->domain = irq_domain_create_linear(dev_fwnode(dev), tb10x_gpio->chip.gc.ngpio, &irq_generic_chip_ops, NULL); - if (!tb10x_gpio->domain) { + if (!tb10x_gpio->domain) return -ENOMEM; - } ret = irq_alloc_domain_generic_chips(tb10x_gpio->domain, tb10x_gpio->chip.gc.ngpio, 1, tb10x_gpio->chip.gc.label, From 32bd01532af59cf0cc6994e2794e0aaa9af5bc8d Mon Sep 17 00:00:00 2001 From: Fenglin Wu Date: Wed, 10 Jun 2026 00:05:46 -0700 Subject: [PATCH 010/130] dt-bindings: pinctrl: qcom,pmic-gpio: Document PMG1110 GPIO support Update the binding documentation to include the compatible string for PMG1110 PMIC which is used on Maili platform. Signed-off-by: Fenglin Wu Reviewed-by: Krzysztof Kozlowski Reviewed-by: Linus Walleij Link: https://patch.msgid.link/20260610-pmg1110-gpio-v1-1-a9c50cd8b5d9@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski --- Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml index b8109e6c2a10..c27e24cb206f 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml @@ -62,6 +62,7 @@ properties: - qcom,pmc8380-gpio - qcom,pmcx0102-gpio - qcom,pmd8028-gpio + - qcom,pmg1110-gpio - qcom,pmh0101-gpio - qcom,pmh0104-gpio - qcom,pmh0110-gpio @@ -155,6 +156,7 @@ allOf: - qcom,pm8450-gpio - qcom,pm8916-gpio - qcom,pmd8028-gpio + - qcom,pmg1110-gpio - qcom,pmk8350-gpio - qcom,pmr735a-gpio - qcom,pmr735b-gpio @@ -496,6 +498,7 @@ $defs: - gpio1-gpio22 for pma8084 - gpio1-gpio14 for pmcx0102 - gpio1-gpio4 for pmd8028 + - gpio1-gpio4 for pmg1110 - gpio1-gpio18 for pmh0101 - gpio1-gpio8 for pmh0104 - gpio1-gpio14 for pmh0110 From 8a762912365d4e7402fb8942934681acd0a3bcd6 Mon Sep 17 00:00:00 2001 From: Fenglin Wu Date: Wed, 10 Jun 2026 00:05:47 -0700 Subject: [PATCH 011/130] pinctrl: qcom: spmi-gpio: Add PMG1110 GPIO support Add PMG1110 GPIO support with its compatible string and match data. Reviewed-by: Konrad Dybcio Signed-off-by: Fenglin Wu Acked-by: Linus Walleij Reviewed-by: Dmitry Baryshkov Reviewed-by: Linus Walleij Link: https://patch.msgid.link/20260610-pmg1110-gpio-v1-2-a9c50cd8b5d9@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski --- drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index cdd61dae74cf..922c27177b5a 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -1262,6 +1262,7 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pmc8380-gpio", .data = (void *) 10 }, { .compatible = "qcom,pmcx0102-gpio", .data = (void *)14 }, { .compatible = "qcom,pmd8028-gpio", .data = (void *) 4 }, + { .compatible = "qcom,pmg1110-gpio", .data = (void *) 4 }, { .compatible = "qcom,pmh0101-gpio", .data = (void *)18 }, { .compatible = "qcom,pmh0104-gpio", .data = (void *)8 }, { .compatible = "qcom,pmh0110-gpio", .data = (void *)14 }, From 72323d7dc5118f5c7c269ff67797d342ed9effc7 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Tue, 23 Jun 2026 14:27:31 +0200 Subject: [PATCH 012/130] pinctrl: qcom: Drop unnecessary bitmap_fill() call Drop an unnecessary bitmap_fill() call from msm_gpio_irq_init_valid_mask(), this is unnecessary because gpiochip_allocate_mask() already does this. Signed-off-by: Hans de Goede Acked-by: Linus Walleij Reviewed-by: Konrad Dybcio Reviewed-by: Mukesh Ojha Link: https://patch.msgid.link/20260623122732.6439-1-johannes.goede@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski --- drivers/pinctrl/qcom/pinctrl-msm.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 11db6564c44d..a035cb6a74fe 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -1035,8 +1035,6 @@ static void msm_gpio_irq_init_valid_mask(struct gpio_chip *gc, const struct msm_pingroup *g; int i; - bitmap_fill(valid_mask, ngpios); - for (i = 0; i < ngpios; i++) { g = &pctrl->soc->groups[i]; From e417d51c7f2ee08361b57a97869a2870bb417782 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Tue, 23 Jun 2026 14:27:32 +0200 Subject: [PATCH 013/130] pinctrl: qcom: Drop unused irq_data argument from msm_gpio_update_dual_edge_pos() The "struct irq_data *d" argument to msm_gpio_update_dual_edge_pos() is unused, drop it. Signed-off-by: Hans de Goede Acked-by: Linus Walleij Reviewed-by: Konrad Dybcio Reviewed-by: Mukesh Ojha Link: https://patch.msgid.link/20260623122732.6439-2-johannes.goede@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski --- drivers/pinctrl/qcom/pinctrl-msm.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index a035cb6a74fe..1055d42381bb 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -810,8 +810,7 @@ static const struct gpio_chip msm_gpio_template = { * Algorithm comes from Google's msmgpio driver. */ static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, - const struct msm_pingroup *g, - struct irq_data *d) + const struct msm_pingroup *g) { int loop_limit = 100; unsigned val, val2, intstat; @@ -1005,7 +1004,7 @@ static void msm_gpio_irq_ack(struct irq_data *d) msm_ack_intr_status(pctrl, g); if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) - msm_gpio_update_dual_edge_pos(pctrl, g, d); + msm_gpio_update_dual_edge_pos(pctrl, g); raw_spin_unlock_irqrestore(&pctrl->lock, flags); } @@ -1175,7 +1174,7 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) msm_ack_intr_status(pctrl, g); if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) - msm_gpio_update_dual_edge_pos(pctrl, g, d); + msm_gpio_update_dual_edge_pos(pctrl, g); raw_spin_unlock_irqrestore(&pctrl->lock, flags); From e95f2b212c4a8ec422b1627e36e951e778809965 Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Mon, 22 Jun 2026 01:35:32 -0700 Subject: [PATCH 014/130] dt-bindings: pinctrl: qcom: Describe Maili TLMM block The Top Level Mode Multiplexer (TLMM) in the Qualcomm Maili SoC provides GPIO and pinctrl functionality for UFS, SDC and 226 GPIO pins. Add a DeviceTree binding to describe the TLMM block on Qualcomm's Maili SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Jingyi Wang Acked-by: Linus Walleij Link: https://patch.msgid.link/20260622-maili-pinctrl-v3-1-9724e1000471@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski --- .../bindings/pinctrl/qcom,maili-tlmm.yaml | 120 ++++++++++++++++++ 1 file changed, 120 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,maili-tlmm.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,maili-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,maili-tlmm.yaml new file mode 100644 index 000000000000..64fe90b2391b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,maili-tlmm.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,maili-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Maili TLMM block + +maintainers: + - Jingyi Wang + +description: + Top Level Mode Multiplexer pin controller in Qualcomm Maili SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,maili-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 113 + + gpio-line-names: + maxItems: 226 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-maili-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-maili-tlmm-state" + additionalProperties: false + +$defs: + qcom-maili-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-9]|22[0-5])$" + - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk, + audio_ref_clk, cam_mclk, cci_async_in, cci_i2c0, cci_i2c1, + cci_i2c2, cci_i2c3, cci_timer, coex_espmi, coex_uart1_rx, + coex_uart1_tx, dbg_out_clk, ddr_bist, ddr_pxi, dp_hot, egpio, + gcc_gp, gnss_adc, host2wlan_sol, host_rst, i2chub0_se0, + i2chub0_se1, i2chub0_se2, i2chub0_se3, i2chub0_se4, i2s0, i2s1, + ibi_i3c, ibi_i3c_qup5_se0, jitter_bist, mdp_esync0, mdp_esync1, + mdp_esync2, mdp_vsync, mdp_vsync_e, mdp_vsync_p, mdp_vsync0_out, + mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out, + modem_pps_in, modem_pps_out, nav_gpio, nav_gpio0, nav_gpio3, + nav_rffe, pcie0_clk_req_n, pcie1_clk_req_n, pcie1_rst_n, + phase_flag, pll_bist_sync, pll_clk_aux, qdss_cti, qlink, qspi, + qspi_clk, qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se3, + qup1_se4, qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1, + qup2_se2, qup2_se3, qup2_se4_01, qup2_se4_23, qup3_se0, + qup3_se1, qup3_se2, qup3_se3, qup3_se4, qup3_se5, qup4_se0, + qup4_se1, qup4_se2, qup4_se3_01, qup4_se3_23, qup4_se3_l3, + qup4_se4_01, qup4_se4_23, qup4_se4_l3, qup5_se0, rng_rosc, + sd_write_protect, sdc2_clk, sdc2_cmd, sdc2_data, sdc2_rclk, + sdc4_clk, sdc4_cmd, sdc4_data, sys_throttle, tb_trig_sdc, + tmess_rng, tsense_clm, tsense_pwm, uim0, uim1, usb0_hs, usb_phy, + vfr, vsense_trigger_mirnat, wcn_sw ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + tlmm: pinctrl@f100000 { + compatible = "qcom,maili-tlmm"; + reg = <0x0f100000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 227>; + interrupt-controller; + #interrupt-cells = <2>; + + qup-uart7-state { + pins = "gpio62", "gpio63"; + function = "qup1_se7"; + }; + }; +... From 251b53103a2e5770658ae106c490cdd2b7512c3a Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Mon, 22 Jun 2026 01:35:33 -0700 Subject: [PATCH 015/130] pinctrl: qcom: Add the tlmm driver for Maili platform Add support for Maili TLMM configuration and control via the pinctrl framework. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Jingyi Wang Acked-by: Linus Walleij Link: https://patch.msgid.link/20260622-maili-pinctrl-v3-2-9724e1000471@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski --- drivers/pinctrl/qcom/Kconfig.msm | 10 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-maili.c | 1625 ++++++++++++++++++++++++++ 3 files changed, 1636 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-maili.c diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfig.msm index 9409e678ec6d..42875457b5fc 100644 --- a/drivers/pinctrl/qcom/Kconfig.msm +++ b/drivers/pinctrl/qcom/Kconfig.msm @@ -153,6 +153,16 @@ config PINCTRL_KAANAPALI Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc Kaanapali platform. +config PINCTRL_MAILI + tristate "Qualcomm Technologies Inc Maili pin controller driver" + depends on ARM64 || COMPILE_TEST + default ARCH_QCOM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Maili platform. + Say Y here to compile statically, or M here to compile it as a module. + If unsure, say N. + config PINCTRL_MSM8226 tristate "Qualcomm 8226 pin controller driver" depends on ARM || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 93cc4e7965ca..43ecd246afe8 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_IPQ6018) += pinctrl-ipq6018.o obj-$(CONFIG_PINCTRL_IPQ9574) += pinctrl-ipq9574.o obj-$(CONFIG_PINCTRL_IPQ9650) += pinctrl-ipq9650.o obj-$(CONFIG_PINCTRL_KAANAPALI) += pinctrl-kaanapali.o +obj-$(CONFIG_PINCTRL_MAILI) += pinctrl-maili.o obj-$(CONFIG_PINCTRL_MSM8226) += pinctrl-msm8226.o obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o diff --git a/drivers/pinctrl/qcom/pinctrl-maili.c b/drivers/pinctrl/qcom/pinctrl-maili.c new file mode 100644 index 000000000000..ffa084cfad64 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-maili.c @@ -0,0 +1,1625 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + msm_mux_##f10, \ + msm_mux_##f11 /* egpio mode */ \ + }, \ + .nfuncs = 12, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_wakeup_present_bit = 6, \ + .intr_wakeup_enable_bit = 7, \ + .intr_target_bit = 8, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, ctl, io) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = io, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc maili_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + PINCTRL_PIN(173, "GPIO_173"), + PINCTRL_PIN(174, "GPIO_174"), + PINCTRL_PIN(175, "GPIO_175"), + PINCTRL_PIN(176, "GPIO_176"), + PINCTRL_PIN(177, "GPIO_177"), + PINCTRL_PIN(178, "GPIO_178"), + PINCTRL_PIN(179, "GPIO_179"), + PINCTRL_PIN(180, "GPIO_180"), + PINCTRL_PIN(181, "GPIO_181"), + PINCTRL_PIN(182, "GPIO_182"), + PINCTRL_PIN(183, "GPIO_183"), + PINCTRL_PIN(184, "GPIO_184"), + PINCTRL_PIN(185, "GPIO_185"), + PINCTRL_PIN(186, "GPIO_186"), + PINCTRL_PIN(187, "GPIO_187"), + PINCTRL_PIN(188, "GPIO_188"), + PINCTRL_PIN(189, "GPIO_189"), + PINCTRL_PIN(190, "GPIO_190"), + PINCTRL_PIN(191, "GPIO_191"), + PINCTRL_PIN(192, "GPIO_192"), + PINCTRL_PIN(193, "GPIO_193"), + PINCTRL_PIN(194, "GPIO_194"), + PINCTRL_PIN(195, "GPIO_195"), + PINCTRL_PIN(196, "GPIO_196"), + PINCTRL_PIN(197, "GPIO_197"), + PINCTRL_PIN(198, "GPIO_198"), + PINCTRL_PIN(199, "GPIO_199"), + PINCTRL_PIN(200, "GPIO_200"), + PINCTRL_PIN(201, "GPIO_201"), + PINCTRL_PIN(202, "GPIO_202"), + PINCTRL_PIN(203, "GPIO_203"), + PINCTRL_PIN(204, "GPIO_204"), + PINCTRL_PIN(205, "GPIO_205"), + PINCTRL_PIN(206, "GPIO_206"), + PINCTRL_PIN(207, "GPIO_207"), + PINCTRL_PIN(208, "GPIO_208"), + PINCTRL_PIN(209, "GPIO_209"), + PINCTRL_PIN(210, "GPIO_210"), + PINCTRL_PIN(211, "GPIO_211"), + PINCTRL_PIN(212, "GPIO_212"), + PINCTRL_PIN(213, "GPIO_213"), + PINCTRL_PIN(214, "GPIO_214"), + PINCTRL_PIN(215, "GPIO_215"), + PINCTRL_PIN(216, "GPIO_216"), + PINCTRL_PIN(217, "GPIO_217"), + PINCTRL_PIN(218, "GPIO_218"), + PINCTRL_PIN(219, "GPIO_219"), + PINCTRL_PIN(220, "GPIO_220"), + PINCTRL_PIN(221, "GPIO_221"), + PINCTRL_PIN(222, "GPIO_222"), + PINCTRL_PIN(223, "GPIO_223"), + PINCTRL_PIN(224, "GPIO_224"), + PINCTRL_PIN(225, "GPIO_225"), + PINCTRL_PIN(226, "UFS_RESET"), + PINCTRL_PIN(227, "SDC2_CLK"), + PINCTRL_PIN(228, "SDC2_CMD"), + PINCTRL_PIN(229, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); +DECLARE_MSM_GPIO_PINS(166); +DECLARE_MSM_GPIO_PINS(167); +DECLARE_MSM_GPIO_PINS(168); +DECLARE_MSM_GPIO_PINS(169); +DECLARE_MSM_GPIO_PINS(170); +DECLARE_MSM_GPIO_PINS(171); +DECLARE_MSM_GPIO_PINS(172); +DECLARE_MSM_GPIO_PINS(173); +DECLARE_MSM_GPIO_PINS(174); +DECLARE_MSM_GPIO_PINS(175); +DECLARE_MSM_GPIO_PINS(176); +DECLARE_MSM_GPIO_PINS(177); +DECLARE_MSM_GPIO_PINS(178); +DECLARE_MSM_GPIO_PINS(179); +DECLARE_MSM_GPIO_PINS(180); +DECLARE_MSM_GPIO_PINS(181); +DECLARE_MSM_GPIO_PINS(182); +DECLARE_MSM_GPIO_PINS(183); +DECLARE_MSM_GPIO_PINS(184); +DECLARE_MSM_GPIO_PINS(185); +DECLARE_MSM_GPIO_PINS(186); +DECLARE_MSM_GPIO_PINS(187); +DECLARE_MSM_GPIO_PINS(188); +DECLARE_MSM_GPIO_PINS(189); +DECLARE_MSM_GPIO_PINS(190); +DECLARE_MSM_GPIO_PINS(191); +DECLARE_MSM_GPIO_PINS(192); +DECLARE_MSM_GPIO_PINS(193); +DECLARE_MSM_GPIO_PINS(194); +DECLARE_MSM_GPIO_PINS(195); +DECLARE_MSM_GPIO_PINS(196); +DECLARE_MSM_GPIO_PINS(197); +DECLARE_MSM_GPIO_PINS(198); +DECLARE_MSM_GPIO_PINS(199); +DECLARE_MSM_GPIO_PINS(200); +DECLARE_MSM_GPIO_PINS(201); +DECLARE_MSM_GPIO_PINS(202); +DECLARE_MSM_GPIO_PINS(203); +DECLARE_MSM_GPIO_PINS(204); +DECLARE_MSM_GPIO_PINS(205); +DECLARE_MSM_GPIO_PINS(206); +DECLARE_MSM_GPIO_PINS(207); +DECLARE_MSM_GPIO_PINS(208); +DECLARE_MSM_GPIO_PINS(209); +DECLARE_MSM_GPIO_PINS(210); +DECLARE_MSM_GPIO_PINS(211); +DECLARE_MSM_GPIO_PINS(212); +DECLARE_MSM_GPIO_PINS(213); +DECLARE_MSM_GPIO_PINS(214); +DECLARE_MSM_GPIO_PINS(215); +DECLARE_MSM_GPIO_PINS(216); +DECLARE_MSM_GPIO_PINS(217); +DECLARE_MSM_GPIO_PINS(218); +DECLARE_MSM_GPIO_PINS(219); +DECLARE_MSM_GPIO_PINS(220); +DECLARE_MSM_GPIO_PINS(221); +DECLARE_MSM_GPIO_PINS(222); +DECLARE_MSM_GPIO_PINS(223); +DECLARE_MSM_GPIO_PINS(224); +DECLARE_MSM_GPIO_PINS(225); + +static const unsigned int ufs_reset_pins[] = { 226 }; +static const unsigned int sdc2_clk_pins[] = { 227 }; +static const unsigned int sdc2_cmd_pins[] = { 228 }; +static const unsigned int sdc2_data_pins[] = { 229 }; + +enum maili_functions { + msm_mux_gpio, + msm_mux_aoss_cti, + msm_mux_atest_char, + msm_mux_atest_usb, + msm_mux_audio_ext_mclk, + msm_mux_audio_ref_clk, + msm_mux_cam_mclk, + msm_mux_cci_async_in, + msm_mux_cci_i2c0, + msm_mux_cci_i2c1, + msm_mux_cci_i2c2, + msm_mux_cci_i2c3, + msm_mux_cci_timer, + msm_mux_coex_espmi, + msm_mux_coex_uart1_rx, + msm_mux_coex_uart1_tx, + msm_mux_dbg_out_clk, + msm_mux_ddr_bist, + msm_mux_ddr_pxi, + msm_mux_dp_hot, + msm_mux_egpio, + msm_mux_gcc_gp, + msm_mux_gnss_adc, + msm_mux_host2wlan_sol, + msm_mux_host_rst, + msm_mux_i2chub0_se0, + msm_mux_i2chub0_se1, + msm_mux_i2chub0_se2, + msm_mux_i2chub0_se3, + msm_mux_i2chub0_se4, + msm_mux_i2s0, + msm_mux_i2s1, + msm_mux_ibi_i3c, + msm_mux_ibi_i3c_qup5_se0, + msm_mux_jitter_bist, + msm_mux_mdp_esync0, + msm_mux_mdp_esync1, + msm_mux_mdp_esync2, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync_e, + msm_mux_mdp_vsync_p, + msm_mux_mdp_vsync0_out, + msm_mux_mdp_vsync1_out, + msm_mux_mdp_vsync2_out, + msm_mux_mdp_vsync3_out, + msm_mux_mdp_vsync5_out, + msm_mux_modem_pps_in, + msm_mux_modem_pps_out, + msm_mux_nav_gpio, + msm_mux_nav_gpio0, + msm_mux_nav_gpio3, + msm_mux_nav_rffe, + msm_mux_pcie0_clk_req_n, + msm_mux_pcie1_clk_req_n, + msm_mux_pcie1_rst_n, + msm_mux_phase_flag, + msm_mux_pll_bist_sync, + msm_mux_pll_clk_aux, + msm_mux_qdss_cti, + msm_mux_qlink, + msm_mux_qspi, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qup1_se0, + msm_mux_qup1_se1, + msm_mux_qup1_se2, + msm_mux_qup1_se3, + msm_mux_qup1_se4, + msm_mux_qup1_se5, + msm_mux_qup1_se6, + msm_mux_qup1_se7, + msm_mux_qup2_se0, + msm_mux_qup2_se1, + msm_mux_qup2_se2, + msm_mux_qup2_se3, + msm_mux_qup2_se4_01, + msm_mux_qup2_se4_23, + msm_mux_qup3_se0, + msm_mux_qup3_se1, + msm_mux_qup3_se2, + msm_mux_qup3_se3, + msm_mux_qup3_se4, + msm_mux_qup3_se5, + msm_mux_qup4_se0, + msm_mux_qup4_se1, + msm_mux_qup4_se2, + msm_mux_qup4_se3_01, + msm_mux_qup4_se3_23, + msm_mux_qup4_se3_l3, + msm_mux_qup4_se4_01, + msm_mux_qup4_se4_23, + msm_mux_qup4_se4_l3, + msm_mux_qup5_se0, + msm_mux_rng_rosc, + msm_mux_sd_write_protect, + msm_mux_sdc2_clk, + msm_mux_sdc2_cmd, + msm_mux_sdc2_data, + msm_mux_sdc2_rclk, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sdc4_data, + msm_mux_sys_throttle, + msm_mux_tb_trig_sdc, + msm_mux_tmess_rng, + msm_mux_tsense_clm, + msm_mux_tsense_pwm, + msm_mux_uim0, + msm_mux_uim1, + msm_mux_usb0_hs, + msm_mux_usb_phy, + msm_mux_vfr, + msm_mux_vsense_trigger_mirnat, + msm_mux_wcn_sw, + msm_mux__, +}; + +static const char *const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", + "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", + "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", + "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", + "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", + "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", + "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", + "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101", + "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", + "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", + "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", + "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", + "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", + "gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137", + "gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143", + "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149", + "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155", + "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161", + "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", "gpio167", + "gpio168", "gpio169", "gpio170", "gpio171", "gpio172", "gpio173", + "gpio174", "gpio175", "gpio176", "gpio177", "gpio178", "gpio179", + "gpio180", "gpio181", "gpio182", "gpio183", "gpio184", "gpio185", + "gpio186", "gpio187", "gpio188", "gpio189", "gpio190", "gpio191", + "gpio192", "gpio193", "gpio194", "gpio195", "gpio196", "gpio197", + "gpio198", "gpio199", "gpio200", "gpio201", "gpio202", "gpio203", + "gpio204", "gpio205", "gpio206", "gpio207", "gpio208", "gpio209", + "gpio210", "gpio211", "gpio212", "gpio213", "gpio214", "gpio215", + "gpio216", "gpio217", "gpio218", "gpio219", "gpio220", "gpio221", + "gpio222", "gpio223", "gpio224", "gpio225", +}; + +static const char *const aoss_cti_groups[] = { + "gpio74", "gpio75", "gpio76", "gpio77", +}; + +static const char *const atest_char_groups[] = { + "gpio126", "gpio127", "gpio128", "gpio129", "gpio133", +}; + +static const char *const atest_usb_groups[] = { + "gpio78", "gpio79", "gpio102", "gpio103", "gpio104", +}; + +static const char *const audio_ext_mclk_groups[] = { + "gpio120", "gpio121", +}; + +static const char *const audio_ref_clk_groups[] = { + "gpio120", +}; + +static const char *const cam_mclk_groups[] = { + "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", +}; + +static const char *const cci_async_in_groups[] = { + "gpio15", "gpio109", "gpio110", +}; + +static const char *const cci_i2c0_groups[] = { + "gpio109", "gpio110", +}; + +static const char *const cci_i2c1_groups[] = { + "gpio111", "gpio112", +}; + +static const char *const cci_i2c2_groups[] = { + "gpio113", "gpio114", +}; + +static const char *const cci_i2c3_groups[] = { + "gpio107", "gpio160", +}; + +static const char *const cci_timer_groups[] = { + "gpio105", "gpio106", "gpio107", "gpio159", "gpio160", +}; + +static const char *const coex_espmi_groups[] = { + "gpio144", "gpio145", +}; + +static const char *const coex_uart1_rx_groups[] = { + "gpio144", +}; + +static const char *const coex_uart1_tx_groups[] = { + "gpio145", +}; + +static const char *const dbg_out_clk_groups[] = { + "gpio82", +}; + +static const char *const ddr_bist_groups[] = { + "gpio40", "gpio41", "gpio44", "gpio45", +}; + +static const char *const ddr_pxi_groups[] = { + "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", +}; + +static const char *const dp_hot_groups[] = { + "gpio47", +}; + +static const char *const egpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio28", "gpio29", "gpio30", "gpio31", + "gpio48", "gpio49", "gpio50", "gpio51", "gpio163", "gpio164", + "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", + "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", + "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182", + "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188", + "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194", + "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200", + "gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206", + "gpio207", "gpio208", "gpio209", "gpio212", "gpio213", "gpio214", + "gpio215", "gpio216", "gpio217", "gpio218", +}; + +static const char *const gcc_gp_groups[] = { + "gpio17", "gpio86", "gpio87", "gpio97", "gpio155", "gpio156", +}; + +static const char *const gnss_adc_groups[] = { + "gpio18", "gpio19", "gpio20", "gpio23", +}; + +static const char *const host2wlan_sol_groups[] = { + "gpio204", +}; + +static const char *const host_rst_groups[] = { + "gpio106", +}; + +static const char *const i2chub0_se0_groups[] = { + "gpio66", "gpio67", +}; + +static const char *const i2chub0_se1_groups[] = { + "gpio78", "gpio79", +}; + +static const char *const i2chub0_se2_groups[] = { + "gpio68", "gpio69", +}; + +static const char *const i2chub0_se3_groups[] = { + "gpio70", "gpio71", +}; + +static const char *const i2chub0_se4_groups[] = { + "gpio72", "gpio73", +}; + +static const char *const i2s0_groups[] = { + "gpio46", "gpio84", "gpio161", "gpio162", +}; + +static const char *const i2s1_groups[] = { + "gpio222", "gpio223", "gpio224", "gpio225", +}; + +static const char *const ibi_i3c_groups[] = { + "gpio0", "gpio1", "gpio4", "gpio5", "gpio8", "gpio9", + "gpio12", "gpio13", "gpio24", "gpio25", "gpio28", "gpio29", + "gpio32", "gpio33", "gpio36", "gpio37", "gpio48", "gpio49", + "gpio60", "gpio61", "gpio64", "gpio65", "gpio85", "gpio89", + "gpio117", "gpio118", +}; + +static const char *const ibi_i3c_qup5_se0_groups[] = { + "gpio8", "gpio9", +}; + +static const char *const jitter_bist_groups[] = { + "gpio73", +}; + +static const char *const mdp_esync0_groups[] = { + "gpio88", "gpio100", +}; + +static const char *const mdp_esync1_groups[] = { + "gpio86", "gpio100", +}; + +static const char *const mdp_esync2_groups[] = { + "gpio87", "gpio97", +}; + +static const char *const mdp_vsync_groups[] = { + "gpio86", "gpio87", "gpio88", "gpio97", +}; + +static const char *const mdp_vsync_e_groups[] = { + "gpio98", +}; + +static const char *const mdp_vsync_p_groups[] = { + "gpio98", +}; + +static const char *const mdp_vsync0_out_groups[] = { + "gpio86", +}; + +static const char *const mdp_vsync1_out_groups[] = { + "gpio86", +}; + +static const char *const mdp_vsync2_out_groups[] = { + "gpio87", +}; + +static const char *const mdp_vsync3_out_groups[] = { + "gpio87", +}; + +static const char *const mdp_vsync5_out_groups[] = { + "gpio87", +}; + +static const char *const modem_pps_in_groups[] = { + "gpio151", +}; + +static const char *const modem_pps_out_groups[] = { + "gpio151", +}; + +static const char *const nav_gpio_groups[] = { + "gpio146", "gpio147", "gpio148", "gpio151", +}; + +static const char *const nav_gpio0_groups[] = { + "gpio150", +}; + +static const char *const nav_gpio3_groups[] = { + "gpio150", +}; + +static const char *const nav_rffe_groups[] = { + "gpio134", "gpio135", "gpio138", "gpio139", +}; + +static const char *const pcie0_clk_req_n_groups[] = { + "gpio103", +}; + +static const char *const pcie1_clk_req_n_groups[] = { + "gpio221", +}; + +static const char *const pcie1_rst_n_groups[] = { + "gpio220", +}; + +static const char *const phase_flag_groups[] = { + "gpio40", "gpio41", "gpio44", "gpio45", "gpio46", "gpio47", "gpio126", + "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", "gpio132", + "gpio133", "gpio161", "gpio162", "gpio169", "gpio170", "gpio171", + "gpio174", "gpio175", "gpio178", "gpio179", "gpio180", "gpio181", + "gpio182", "gpio183", "gpio205", "gpio222", "gpio223", "gpio224", + "gpio225", +}; + +static const char *const pll_bist_sync_groups[] = { + "gpio104", +}; + +static const char *const pll_clk_aux_groups[] = { + "gpio94", +}; + +static const char *const qdss_cti_groups[] = { + "gpio72", "gpio73", "gpio82", "gpio83", "gpio222", "gpio223", + "gpio224", "gpio225", +}; + +static const char *const qlink_groups[] = { + "gpio152", "gpio153", "gpio154", +}; + +static const char *const qspi_groups[] = { + "gpio80", "gpio81", "gpio82", "gpio147", +}; + +static const char *const qspi_clk_groups[] = { + "gpio83", +}; + +static const char *const qspi_cs_groups[] = { + "gpio146", "gpio148", +}; + +static const char *const qup1_se0_groups[] = { + "gpio222", "gpio223", "gpio224", "gpio225", +}; + +static const char *const qup1_se1_groups[] = { + "gpio74", "gpio75", "gpio76", "gpio77", "gpio188", "gpio189", "gpio192", "gpio193", +}; + +static const char *const qup1_se2_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", "gpio130", "gpio131", "gpio132", +}; + +static const char *const qup1_se3_groups[] = { + "gpio44", "gpio45", "gpio46", "gpio47", +}; + +static const char *const qup1_se4_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; + +static const char *const qup1_se5_groups[] = { + "gpio52", "gpio53", "gpio54", "gpio55", +}; + +static const char *const qup1_se6_groups[] = { + "gpio56", "gpio57", "gpio58", "gpio59", +}; + +static const char *const qup1_se7_groups[] = { + "gpio60", "gpio61", "gpio62", "gpio63", +}; + +static const char *const qup2_se0_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char *const qup2_se1_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const char *const qup2_se2_groups[] = { + "gpio117", "gpio118", "gpio119", "gpio120", +}; + +static const char *const qup2_se3_groups[] = { + "gpio97", "gpio122", "gpio123", "gpio124", "gpio125", +}; + +static const char *const qup2_se4_01_groups[] = { + "gpio208", "gpio209", +}; + +static const char *const qup2_se4_23_groups[] = { + "gpio208", "gpio209", +}; + +static const char *const qup3_se0_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio67", "gpio82", "gpio83", +}; + +static const char *const qup3_se1_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio15", +}; + +static const char *const qup3_se2_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; + +static const char *const qup3_se3_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; + +static const char *const qup3_se4_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; + +static const char *const qup3_se5_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", +}; + +static const char *const qup4_se0_groups[] = { + "gpio48", "gpio49", "gpio50", "gpio51", +}; + +static const char *const qup4_se1_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", +}; + +static const char *const qup4_se2_groups[] = { + "gpio32", "gpio33", "gpio34", "gpio35", +}; + +static const char *const qup4_se3_01_groups[] = { + "gpio84", "gpio121", +}; + +static const char *const qup4_se3_23_groups[] = { + "gpio84", "gpio121", +}; + +static const char *const qup4_se3_l3_groups[] = { + "gpio98", +}; + +static const char *const qup4_se4_01_groups[] = { + "gpio161", "gpio162", +}; + +static const char *const qup4_se4_23_groups[] = { + "gpio161", "gpio162", +}; + +static const char *const qup4_se4_l3_groups[] = { + "gpio88", +}; + +static const char *const qup5_se0_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio16", "gpio17", "gpio85", "gpio89", "gpio100", "gpio214", "gpio215", +}; + +static const char *const rng_rosc_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio84", +}; + +static const char *const sd_write_protect_groups[] = { + "gpio85", +}; + +static const char *const sdc2_clk_groups[] = { + "gpio56", +}; + +static const char *const sdc2_cmd_groups[] = { + "gpio57", +}; + +static const char *const sdc2_data_groups[] = { + "gpio74", "gpio75", "gpio76", "gpio77", +}; + +static const char *const sdc2_rclk_groups[] = { + "gpio54", +}; + +static const char *const sdc4_clk_groups[] = { + "gpio83", +}; + +static const char *const sdc4_cmd_groups[] = { + "gpio148", +}; + +static const char *const sdc4_data_groups[] = { + "gpio80", "gpio81", "gpio82", "gpio147", +}; + +static const char *const sys_throttle_groups[] = { + "gpio99", +}; + +static const char *const tb_trig_sdc_groups[] = { + "gpio88", "gpio146", +}; + +static const char *const tmess_rng_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio84", +}; + +static const char *const tsense_clm_groups[] = { + "gpio87", "gpio97", "gpio98", "gpio99", "gpio105", "gpio106", + "gpio159", +}; + +static const char *const tsense_pwm_groups[] = { + "gpio35", "gpio38", "gpio58", "gpio87", "gpio97", "gpio98", "gpio99", +}; + +static const char *const uim0_groups[] = { + "gpio126", "gpio127", "gpio128", "gpio129", +}; + +static const char *const uim1_groups[] = { + "gpio36", "gpio37", "gpio39", "gpio54", "gpio55", "gpio56", "gpio70", + "gpio71", "gpio72", "gpio130", "gpio131", "gpio132", "gpio133", +}; + +static const char *const usb0_hs_groups[] = { + "gpio79", +}; + +static const char *const usb_phy_groups[] = { + "gpio59", "gpio60", +}; + +static const char *const vfr_groups[] = { + "gpio146", "gpio151", +}; + +static const char *const vsense_trigger_mirnat_groups[] = { + "gpio16", +}; + +static const char *const wcn_sw_groups[] = { + "gpio18", "gpio19", "gpio155", "gpio156", +}; + +static const struct pinfunction maili_functions[] = { + MSM_GPIO_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(aoss_cti), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_usb), + MSM_PIN_FUNCTION(audio_ext_mclk), + MSM_PIN_FUNCTION(audio_ref_clk), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async_in), + MSM_PIN_FUNCTION(cci_i2c0), + MSM_PIN_FUNCTION(cci_i2c1), + MSM_PIN_FUNCTION(cci_i2c2), + MSM_PIN_FUNCTION(cci_i2c3), + MSM_PIN_FUNCTION(cci_timer), + MSM_PIN_FUNCTION(coex_espmi), + MSM_PIN_FUNCTION(coex_uart1_rx), + MSM_PIN_FUNCTION(coex_uart1_tx), + MSM_PIN_FUNCTION(dbg_out_clk), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(ddr_pxi), + MSM_PIN_FUNCTION(dp_hot), + MSM_PIN_FUNCTION(egpio), + MSM_PIN_FUNCTION(gcc_gp), + MSM_PIN_FUNCTION(gnss_adc), + MSM_PIN_FUNCTION(host2wlan_sol), + MSM_PIN_FUNCTION(host_rst), + MSM_PIN_FUNCTION(i2chub0_se0), + MSM_PIN_FUNCTION(i2chub0_se1), + MSM_PIN_FUNCTION(i2chub0_se2), + MSM_PIN_FUNCTION(i2chub0_se3), + MSM_PIN_FUNCTION(i2chub0_se4), + MSM_PIN_FUNCTION(i2s0), + MSM_PIN_FUNCTION(i2s1), + MSM_PIN_FUNCTION(ibi_i3c), + MSM_PIN_FUNCTION(ibi_i3c_qup5_se0), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(mdp_esync0), + MSM_PIN_FUNCTION(mdp_esync1), + MSM_PIN_FUNCTION(mdp_esync2), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mdp_vsync_e), + MSM_PIN_FUNCTION(mdp_vsync_p), + MSM_PIN_FUNCTION(mdp_vsync0_out), + MSM_PIN_FUNCTION(mdp_vsync1_out), + MSM_PIN_FUNCTION(mdp_vsync2_out), + MSM_PIN_FUNCTION(mdp_vsync3_out), + MSM_PIN_FUNCTION(mdp_vsync5_out), + MSM_PIN_FUNCTION(modem_pps_in), + MSM_PIN_FUNCTION(modem_pps_out), + MSM_PIN_FUNCTION(nav_gpio), + MSM_PIN_FUNCTION(nav_gpio0), + MSM_PIN_FUNCTION(nav_gpio3), + MSM_PIN_FUNCTION(nav_rffe), + MSM_PIN_FUNCTION(pcie0_clk_req_n), + MSM_PIN_FUNCTION(pcie1_clk_req_n), + MSM_PIN_FUNCTION(pcie1_rst_n), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist_sync), + MSM_PIN_FUNCTION(pll_clk_aux), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qlink), + MSM_PIN_FUNCTION(qspi), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs), + MSM_PIN_FUNCTION(qup1_se0), + MSM_PIN_FUNCTION(qup1_se1), + MSM_PIN_FUNCTION(qup1_se2), + MSM_PIN_FUNCTION(qup1_se3), + MSM_PIN_FUNCTION(qup1_se4), + MSM_PIN_FUNCTION(qup1_se5), + MSM_PIN_FUNCTION(qup1_se6), + MSM_PIN_FUNCTION(qup1_se7), + MSM_PIN_FUNCTION(qup2_se0), + MSM_PIN_FUNCTION(qup2_se1), + MSM_PIN_FUNCTION(qup2_se2), + MSM_PIN_FUNCTION(qup2_se3), + MSM_PIN_FUNCTION(qup2_se4_01), + MSM_PIN_FUNCTION(qup2_se4_23), + MSM_PIN_FUNCTION(qup3_se0), + MSM_PIN_FUNCTION(qup3_se1), + MSM_PIN_FUNCTION(qup3_se2), + MSM_PIN_FUNCTION(qup3_se3), + MSM_PIN_FUNCTION(qup3_se4), + MSM_PIN_FUNCTION(qup3_se5), + MSM_PIN_FUNCTION(qup4_se0), + MSM_PIN_FUNCTION(qup4_se1), + MSM_PIN_FUNCTION(qup4_se2), + MSM_PIN_FUNCTION(qup4_se3_01), + MSM_PIN_FUNCTION(qup4_se3_23), + MSM_PIN_FUNCTION(qup4_se3_l3), + MSM_PIN_FUNCTION(qup4_se4_01), + MSM_PIN_FUNCTION(qup4_se4_23), + MSM_PIN_FUNCTION(qup4_se4_l3), + MSM_PIN_FUNCTION(qup5_se0), + MSM_PIN_FUNCTION(rng_rosc), + MSM_PIN_FUNCTION(sd_write_protect), + MSM_PIN_FUNCTION(sdc2_clk), + MSM_PIN_FUNCTION(sdc2_cmd), + MSM_PIN_FUNCTION(sdc2_data), + MSM_PIN_FUNCTION(sdc2_rclk), + MSM_PIN_FUNCTION(sdc4_clk), + MSM_PIN_FUNCTION(sdc4_cmd), + MSM_PIN_FUNCTION(sdc4_data), + MSM_PIN_FUNCTION(sys_throttle), + MSM_PIN_FUNCTION(tb_trig_sdc), + MSM_PIN_FUNCTION(tmess_rng), + MSM_PIN_FUNCTION(tsense_clm), + MSM_PIN_FUNCTION(tsense_pwm), + MSM_PIN_FUNCTION(uim0), + MSM_PIN_FUNCTION(uim1), + MSM_PIN_FUNCTION(usb0_hs), + MSM_PIN_FUNCTION(usb_phy), + MSM_PIN_FUNCTION(vfr), + MSM_PIN_FUNCTION(vsense_trigger_mirnat), + MSM_PIN_FUNCTION(wcn_sw), +}; + +static const struct msm_pingroup maili_groups[] = { + [0] = PINGROUP(0, qup2_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [1] = PINGROUP(1, qup2_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [2] = PINGROUP(2, qup2_se0, _, _, _, _, _, _, _, _, _, egpio), + [3] = PINGROUP(3, qup2_se0, _, _, _, _, _, _, _, _, _, egpio), + [4] = PINGROUP(4, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [5] = PINGROUP(5, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [6] = PINGROUP(6, qup2_se1, _, _, _, _, _, _, _, _, _, egpio), + [7] = PINGROUP(7, qup2_se1, _, _, _, _, _, _, _, _, _, egpio), + [8] = PINGROUP(8, qup3_se1, ibi_i3c, qup5_se0, ibi_i3c_qup5_se0, _, _, _, _, _, _, _), + [9] = PINGROUP(9, qup3_se1, ibi_i3c, qup5_se0, ibi_i3c_qup5_se0, _, _, _, _, _, _, _), + [10] = PINGROUP(10, qup3_se1, qup5_se0, _, _, _, _, _, _, _, _, _), + [11] = PINGROUP(11, qup3_se1, qup5_se0, _, _, _, _, _, _, _, _, _), + [12] = PINGROUP(12, qup3_se2, ibi_i3c, qup3_se1, qup5_se0, _, _, _, _, _, _, _), + [13] = PINGROUP(13, qup3_se2, ibi_i3c, qup3_se1, qup5_se0, _, _, _, _, _, _, _), + [14] = PINGROUP(14, qup3_se2, qup5_se0, _, _, _, _, _, _, _, _, _), + [15] = PINGROUP(15, qup3_se2, cci_async_in, qup3_se1, _, _, _, _, _, _, _, _), + [16] = PINGROUP(16, qup3_se3, qup5_se0, _, vsense_trigger_mirnat, _, _, _, _, _, _, _), + [17] = PINGROUP(17, qup3_se3, qup5_se0, gcc_gp, _, _, _, _, _, _, _, _), + [18] = PINGROUP(18, wcn_sw, qup3_se3, _, gnss_adc, _, _, _, _, _, _, _), + [19] = PINGROUP(19, wcn_sw, qup3_se3, _, gnss_adc, _, _, _, _, _, _, _), + [20] = PINGROUP(20, qup3_se4, _, gnss_adc, _, _, _, _, _, _, _, _), + [21] = PINGROUP(21, qup3_se4, _, _, _, _, _, _, _, _, _, _), + [22] = PINGROUP(22, qup3_se4, _, _, _, _, _, _, _, _, _, _), + [23] = PINGROUP(23, qup3_se4, _, gnss_adc, _, _, _, _, _, _, _, _), + [24] = PINGROUP(24, qup3_se5, ibi_i3c, _, _, _, _, _, _, _, _, _), + [25] = PINGROUP(25, qup3_se5, ibi_i3c, _, _, _, _, _, _, _, _, _), + [26] = PINGROUP(26, qup3_se5, _, _, _, _, _, _, _, _, _, _), + [27] = PINGROUP(27, qup3_se5, _, _, _, _, _, _, _, _, _, _), + [28] = PINGROUP(28, qup4_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [29] = PINGROUP(29, qup4_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [30] = PINGROUP(30, qup4_se1, _, _, _, _, _, _, _, _, _, egpio), + [31] = PINGROUP(31, qup4_se1, _, _, _, _, _, _, _, _, _, egpio), + [32] = PINGROUP(32, qup4_se2, ibi_i3c, _, _, _, _, _, _, _, _, _), + [33] = PINGROUP(33, qup4_se2, ibi_i3c, _, _, _, _, _, _, _, _, _), + [34] = PINGROUP(34, qup4_se2, _, _, _, _, _, _, _, _, _, _), + [35] = PINGROUP(35, qup4_se2, tsense_pwm, _, _, _, _, _, _, _, _, _), + [36] = PINGROUP(36, qup1_se4, uim1, ibi_i3c, _, _, _, _, _, _, _, _), + [37] = PINGROUP(37, qup1_se4, uim1, ibi_i3c, _, _, _, _, _, _, _, _), + [38] = PINGROUP(38, qup1_se4, tsense_pwm, _, _, _, _, _, _, _, _, _), + [39] = PINGROUP(39, qup1_se4, uim1, _, _, _, _, _, _, _, _, _), + [40] = PINGROUP(40, qup1_se2, ddr_bist, phase_flag, _, _, _, _, _, _, _, _), + [41] = PINGROUP(41, qup1_se2, ddr_bist, phase_flag, _, _, _, _, _, _, _, _), + [42] = PINGROUP(42, qup1_se2, _, _, _, _, _, _, _, _, _, _), + [43] = PINGROUP(43, qup1_se2, _, _, _, _, _, _, _, _, _, _), + [44] = PINGROUP(44, qup1_se3, ddr_bist, phase_flag, _, _, _, _, _, _, _, _), + [45] = PINGROUP(45, qup1_se3, ddr_bist, phase_flag, _, _, _, _, _, _, _, _), + [46] = PINGROUP(46, qup1_se3, i2s0, phase_flag, _, _, _, _, _, _, _, _), + [47] = PINGROUP(47, qup1_se3, dp_hot, phase_flag, _, _, _, _, _, _, _, _), + [48] = PINGROUP(48, qup4_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [49] = PINGROUP(49, qup4_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [50] = PINGROUP(50, qup4_se0, _, _, _, _, _, _, _, _, _, egpio), + [51] = PINGROUP(51, qup4_se0, _, _, _, _, _, _, _, _, _, egpio), + [52] = PINGROUP(52, qup1_se5, _, _, _, _, _, _, _, _, _, _), + [53] = PINGROUP(53, qup1_se5, _, _, _, _, _, _, _, _, _, _), + [54] = PINGROUP(54, qup1_se5, uim1, sdc2_rclk, _, _, _, _, _, _, _, _), + [55] = PINGROUP(55, qup1_se5, uim1, _, _, _, _, _, _, _, _, _), + [56] = PINGROUP(56, qup1_se6, uim1, sdc2_clk, _, _, _, _, _, _, _, _), + [57] = PINGROUP(57, qup1_se6, sdc2_cmd, _, _, _, _, _, _, _, _, _), + [58] = PINGROUP(58, qup1_se6, tsense_pwm, _, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, qup1_se6, usb_phy, _, _, _, _, _, _, _, _, _), + [60] = PINGROUP(60, qup1_se7, usb_phy, ibi_i3c, _, _, _, _, _, _, _, _), + [61] = PINGROUP(61, qup1_se7, ibi_i3c, _, _, _, _, _, _, _, _, _), + [62] = PINGROUP(62, qup1_se7, _, _, _, _, _, _, _, _, _, _), + [63] = PINGROUP(63, qup1_se7, _, _, _, _, _, _, _, _, _, _), + [64] = PINGROUP(64, qup3_se0, rng_rosc, tmess_rng, ibi_i3c, _, _, _, _, _, _, _), + [65] = PINGROUP(65, qup3_se0, rng_rosc, tmess_rng, ibi_i3c, _, _, _, _, _, _, _), + [66] = PINGROUP(66, i2chub0_se0, qup3_se0, rng_rosc, tmess_rng, _, ddr_pxi, _, _, _, _, _), + [67] = PINGROUP(67, i2chub0_se0, qup3_se0, _, ddr_pxi, _, _, _, _, _, _, _), + [68] = PINGROUP(68, i2chub0_se2, _, ddr_pxi, _, _, _, _, _, _, _, _), + [69] = PINGROUP(69, i2chub0_se2, _, ddr_pxi, _, _, _, _, _, _, _, _), + [70] = PINGROUP(70, i2chub0_se3, uim1, _, _, ddr_pxi, _, _, _, _, _, _), + [71] = PINGROUP(71, i2chub0_se3, uim1, _, _, ddr_pxi, _, _, _, _, _, _), + [72] = PINGROUP(72, i2chub0_se4, uim1, qdss_cti, _, ddr_pxi, _, _, _, _, _, _), + [73] = PINGROUP(73, i2chub0_se4, qdss_cti, jitter_bist, ddr_pxi, _, _, _, _, _, _, _), + [74] = PINGROUP(74, qup1_se1, aoss_cti, sdc2_data, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, qup1_se1, aoss_cti, sdc2_data, _, _, _, _, _, _, _, _), + [76] = PINGROUP(76, qup1_se1, aoss_cti, sdc2_data, _, _, _, _, _, _, _, _), + [77] = PINGROUP(77, qup1_se1, aoss_cti, sdc2_data, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, i2chub0_se1, _, atest_usb, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, i2chub0_se1, usb0_hs, _, atest_usb, _, _, _, _, _, _, _), + [80] = PINGROUP(80, sdc4_data, qspi, _, _, _, _, _, _, _, _, _), + [81] = PINGROUP(81, sdc4_data, qspi, _, _, _, _, _, _, _, _, _), + [82] = PINGROUP(82, sdc4_data, qdss_cti, qspi, qup3_se0, dbg_out_clk, _, _, _, _, _, _), + [83] = PINGROUP(83, sdc4_clk, qdss_cti, qspi_clk, qup3_se0, _, _, _, _, _, _, _), + [84] = PINGROUP(84, qup4_se3_01, qup4_se3_23, rng_rosc, tmess_rng, i2s0, _, _, _, _, _, _), + [85] = PINGROUP(85, sd_write_protect, qup5_se0, ibi_i3c, _, _, _, _, _, _, _, _), + [86] = PINGROUP(86, mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, mdp_esync1, gcc_gp, + _, _, _, _, _, _), + [87] = PINGROUP(87, mdp_vsync, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out, mdp_esync2, + gcc_gp, tsense_clm, tsense_pwm, _, _, _), + [88] = PINGROUP(88, mdp_esync0, mdp_vsync, qup4_se4_l3, tb_trig_sdc, _, _, _, _, _, _, _), + [89] = PINGROUP(89, qup5_se0, ibi_i3c, _, _, _, _, _, _, _, _, _), + [90] = PINGROUP(90, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [91] = PINGROUP(91, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [92] = PINGROUP(92, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [93] = PINGROUP(93, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [94] = PINGROUP(94, cam_mclk, pll_clk_aux, _, _, _, _, _, _, _, _, _), + [95] = PINGROUP(95, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [96] = PINGROUP(96, _, _, _, _, _, _, _, _, _, _, _), + [97] = PINGROUP(97, mdp_esync2, qup2_se3, mdp_vsync, gcc_gp, tsense_clm, tsense_pwm, + _, _, _, _, _), + [98] = PINGROUP(98, mdp_vsync_e, qup4_se3_l3, mdp_vsync_p, tsense_clm, tsense_pwm, + _, _, _, _, _, _), + [99] = PINGROUP(99, sys_throttle, tsense_clm, tsense_pwm, _, _, _, _, _, _, _, _), + [100] = PINGROUP(100, mdp_esync1, mdp_esync0, qup5_se0, _, _, _, _, _, _, _, _), + [101] = PINGROUP(101, _, _, _, _, _, _, _, _, _, _, _), + [102] = PINGROUP(102, atest_usb, _, _, _, _, _, _, _, _, _, _), + [103] = PINGROUP(103, pcie0_clk_req_n, atest_usb, _, _, _, _, _, _, _, _, _), + [104] = PINGROUP(104, pll_bist_sync, atest_usb, _, _, _, _, _, _, _, _, _), + [105] = PINGROUP(105, cci_timer, tsense_clm, _, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, host_rst, cci_timer, tsense_clm, _, _, _, _, _, _, _, _), + [107] = PINGROUP(107, cci_i2c3, cci_timer, _, _, _, _, _, _, _, _, _), + [108] = PINGROUP(108, _, _, _, _, _, _, _, _, _, _, _), + [109] = PINGROUP(109, cci_i2c0, cci_async_in, _, _, _, _, _, _, _, _, _), + [110] = PINGROUP(110, cci_i2c0, cci_async_in, _, _, _, _, _, _, _, _, _), + [111] = PINGROUP(111, cci_i2c1, _, _, _, _, _, _, _, _, _, _), + [112] = PINGROUP(112, cci_i2c1, _, _, _, _, _, _, _, _, _, _), + [113] = PINGROUP(113, cci_i2c2, _, _, _, _, _, _, _, _, _, _), + [114] = PINGROUP(114, cci_i2c2, _, _, _, _, _, _, _, _, _, _), + [115] = PINGROUP(115, _, _, _, _, _, _, _, _, _, _, _), + [116] = PINGROUP(116, _, _, _, _, _, _, _, _, _, _, _), + [117] = PINGROUP(117, qup2_se2, ibi_i3c, _, _, _, _, _, _, _, _, _), + [118] = PINGROUP(118, qup2_se2, ibi_i3c, _, _, _, _, _, _, _, _, _), + [119] = PINGROUP(119, qup2_se2, _, _, _, _, _, _, _, _, _, _), + [120] = PINGROUP(120, qup2_se2, audio_ext_mclk, audio_ref_clk, _, _, _, _, _, _, _, _), + [121] = PINGROUP(121, audio_ext_mclk, qup4_se3_01, qup4_se3_23, _, _, _, _, _, _, _, _), + [122] = PINGROUP(122, qup2_se3, _, _, _, _, _, _, _, _, _, _), + [123] = PINGROUP(123, qup2_se3, _, _, _, _, _, _, _, _, _, _), + [124] = PINGROUP(124, qup2_se3, _, _, _, _, _, _, _, _, _, _), + [125] = PINGROUP(125, qup2_se3, _, _, _, _, _, _, _, _, _, _), + [126] = PINGROUP(126, uim0, phase_flag, _, atest_char, _, _, _, _, _, _, _), + [127] = PINGROUP(127, uim0, phase_flag, _, atest_char, _, _, _, _, _, _, _), + [128] = PINGROUP(128, uim0, phase_flag, _, atest_char, _, _, _, _, _, _, _), + [129] = PINGROUP(129, uim0, phase_flag, _, atest_char, _, _, _, _, _, _, _), + [130] = PINGROUP(130, uim1, qup1_se2, _, phase_flag, _, _, _, _, _, _, _), + [131] = PINGROUP(131, uim1, qup1_se2, _, phase_flag, _, _, _, _, _, _, _), + [132] = PINGROUP(132, uim1, qup1_se2, _, phase_flag, _, _, _, _, _, _, _), + [133] = PINGROUP(133, uim1, phase_flag, _, atest_char, _, _, _, _, _, _, _), + [134] = PINGROUP(134, _, _, nav_rffe, _, _, _, _, _, _, _, _), + [135] = PINGROUP(135, _, _, nav_rffe, _, _, _, _, _, _, _, _), + [136] = PINGROUP(136, _, _, _, _, _, _, _, _, _, _, _), + [137] = PINGROUP(137, _, _, _, _, _, _, _, _, _, _, _), + [138] = PINGROUP(138, _, _, nav_rffe, _, _, _, _, _, _, _, _), + [139] = PINGROUP(139, _, _, nav_rffe, _, _, _, _, _, _, _, _), + [140] = PINGROUP(140, _, _, _, _, _, _, _, _, _, _, _), + [141] = PINGROUP(141, _, _, _, _, _, _, _, _, _, _, _), + [142] = PINGROUP(142, _, _, _, _, _, _, _, _, _, _, _), + [143] = PINGROUP(143, _, _, _, _, _, _, _, _, _, _, _), + [144] = PINGROUP(144, coex_uart1_rx, coex_espmi, _, _, _, _, _, _, _, _, _), + [145] = PINGROUP(145, coex_uart1_tx, coex_espmi, _, _, _, _, _, _, _, _, _), + [146] = PINGROUP(146, _, vfr, nav_gpio, tb_trig_sdc, qspi_cs, _, _, _, _, _, _), + [147] = PINGROUP(147, _, nav_gpio, sdc4_data, qspi, _, _, _, _, _, _, _), + [148] = PINGROUP(148, nav_gpio, _, sdc4_cmd, qspi_cs, _, _, _, _, _, _, _), + [149] = PINGROUP(149, _, _, _, _, _, _, _, _, _, _, _), + [150] = PINGROUP(150, nav_gpio0, nav_gpio3, _, _, _, _, _, _, _, _, _), + [151] = PINGROUP(151, nav_gpio, vfr, modem_pps_in, modem_pps_out, _, _, _, _, _, _, _), + [152] = PINGROUP(152, qlink, _, _, _, _, _, _, _, _, _, _), + [153] = PINGROUP(153, qlink, _, _, _, _, _, _, _, _, _, _), + [154] = PINGROUP(154, qlink, _, _, _, _, _, _, _, _, _, _), + [155] = PINGROUP(155, wcn_sw, gcc_gp, _, _, _, _, _, _, _, _, _), + [156] = PINGROUP(156, wcn_sw, gcc_gp, _, _, _, _, _, _, _, _, _), + [157] = PINGROUP(157, _, _, _, _, _, _, _, _, _, _, _), + [158] = PINGROUP(158, _, _, _, _, _, _, _, _, _, _, _), + [159] = PINGROUP(159, cci_timer, tsense_clm, _, _, _, _, _, _, _, _, _), + [160] = PINGROUP(160, cci_timer, cci_i2c3, _, _, _, _, _, _, _, _, _), + [161] = PINGROUP(161, qup4_se4_01, qup4_se4_23, i2s0, phase_flag, _, _, _, _, _, _, _), + [162] = PINGROUP(162, qup4_se4_01, qup4_se4_23, i2s0, phase_flag, _, _, _, _, _, _, _), + [163] = PINGROUP(163, _, _, _, _, _, _, _, _, _, _, egpio), + [164] = PINGROUP(164, _, _, _, _, _, _, _, _, _, _, egpio), + [165] = PINGROUP(165, _, _, _, _, _, _, _, _, _, _, egpio), + [166] = PINGROUP(166, _, _, _, _, _, _, _, _, _, _, egpio), + [167] = PINGROUP(167, _, _, _, _, _, _, _, _, _, _, egpio), + [168] = PINGROUP(168, _, _, _, _, _, _, _, _, _, _, egpio), + [169] = PINGROUP(169, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [170] = PINGROUP(170, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [171] = PINGROUP(171, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [172] = PINGROUP(172, _, _, _, _, _, _, _, _, _, _, egpio), + [173] = PINGROUP(173, _, _, _, _, _, _, _, _, _, _, egpio), + [174] = PINGROUP(174, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [175] = PINGROUP(175, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [176] = PINGROUP(176, _, _, _, _, _, _, _, _, _, _, egpio), + [177] = PINGROUP(177, _, _, _, _, _, _, _, _, _, _, egpio), + [178] = PINGROUP(178, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [179] = PINGROUP(179, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [180] = PINGROUP(180, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [181] = PINGROUP(181, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [182] = PINGROUP(182, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [183] = PINGROUP(183, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [184] = PINGROUP(184, _, _, _, _, _, _, _, _, _, _, egpio), + [185] = PINGROUP(185, _, _, _, _, _, _, _, _, _, _, egpio), + [186] = PINGROUP(186, _, _, _, _, _, _, _, _, _, _, egpio), + [187] = PINGROUP(187, _, _, _, _, _, _, _, _, _, _, egpio), + [188] = PINGROUP(188, qup1_se1, _, _, _, _, _, _, _, _, _, egpio), + [189] = PINGROUP(189, qup1_se1, _, _, _, _, _, _, _, _, _, egpio), + [190] = PINGROUP(190, _, _, _, _, _, _, _, _, _, _, egpio), + [191] = PINGROUP(191, _, _, _, _, _, _, _, _, _, _, egpio), + [192] = PINGROUP(192, qup1_se1, _, _, _, _, _, _, _, _, _, egpio), + [193] = PINGROUP(193, qup1_se1, _, _, _, _, _, _, _, _, _, egpio), + [194] = PINGROUP(194, _, _, _, _, _, _, _, _, _, _, egpio), + [195] = PINGROUP(195, _, _, _, _, _, _, _, _, _, _, egpio), + [196] = PINGROUP(196, _, _, _, _, _, _, _, _, _, _, egpio), + [197] = PINGROUP(197, _, _, _, _, _, _, _, _, _, _, egpio), + [198] = PINGROUP(198, _, _, _, _, _, _, _, _, _, _, egpio), + [199] = PINGROUP(199, _, _, _, _, _, _, _, _, _, _, egpio), + [200] = PINGROUP(200, _, _, _, _, _, _, _, _, _, _, egpio), + [201] = PINGROUP(201, _, _, _, _, _, _, _, _, _, _, egpio), + [202] = PINGROUP(202, _, _, _, _, _, _, _, _, _, _, egpio), + [203] = PINGROUP(203, _, _, _, _, _, _, _, _, _, _, egpio), + [204] = PINGROUP(204, host2wlan_sol, _, _, _, _, _, _, _, _, _, egpio), + [205] = PINGROUP(205, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [206] = PINGROUP(206, _, _, _, _, _, _, _, _, _, _, egpio), + [207] = PINGROUP(207, _, _, _, _, _, _, _, _, _, _, egpio), + [208] = PINGROUP(208, qup2_se4_01, qup2_se4_23, _, _, _, _, _, _, _, _, egpio), + [209] = PINGROUP(209, qup2_se4_01, qup2_se4_23, _, _, _, _, _, _, _, _, egpio), + [210] = PINGROUP(210, _, _, _, _, _, _, _, _, _, _, _), + [211] = PINGROUP(211, _, _, _, _, _, _, _, _, _, _, _), + [212] = PINGROUP(212, _, _, _, _, _, _, _, _, _, _, egpio), + [213] = PINGROUP(213, _, _, _, _, _, _, _, _, _, _, egpio), + [214] = PINGROUP(214, qup5_se0, _, _, _, _, _, _, _, _, _, egpio), + [215] = PINGROUP(215, qup5_se0, _, _, _, _, _, _, _, _, _, egpio), + [216] = PINGROUP(216, _, _, _, _, _, _, _, _, _, _, egpio), + [217] = PINGROUP(217, _, _, _, _, _, _, _, _, _, _, egpio), + [218] = PINGROUP(218, _, _, _, _, _, _, _, _, _, _, egpio), + [219] = PINGROUP(219, _, _, _, _, _, _, _, _, _, _, _), + [220] = PINGROUP(220, pcie1_rst_n, _, _, _, _, _, _, _, _, _, _), + [221] = PINGROUP(221, pcie1_clk_req_n, _, _, _, _, _, _, _, _, _, _), + [222] = PINGROUP(222, qup1_se0, i2s1, qdss_cti, phase_flag, _, _, _, _, _, _, _), + [223] = PINGROUP(223, qup1_se0, i2s1, qdss_cti, phase_flag, _, _, _, _, _, _, _), + [224] = PINGROUP(224, qup1_se0, i2s1, qdss_cti, phase_flag, _, _, _, _, _, _, _), + [225] = PINGROUP(225, qup1_se0, i2s1, qdss_cti, phase_flag, _, _, _, _, _, _, _), + [226] = UFS_RESET(ufs_reset, 0xf1004, 0xf2000), + [227] = SDC_QDSD_PINGROUP(sdc2_clk, 0xe6000, 14, 6), + [228] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xe6000, 11, 3), + [229] = SDC_QDSD_PINGROUP(sdc2_data, 0xe6000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map maili_pdc_map[] = { + { 0, 111 }, { 3, 119 }, { 4, 112 }, { 7, 113 }, { 8, 114 }, { 11, 115 }, + { 12, 121 }, { 15, 137 }, { 16, 122 }, { 17, 147 }, { 18, 149 }, { 19, 118 }, + { 23, 123 }, { 24, 124 }, { 27, 125 }, { 28, 131 }, { 31, 132 }, { 32, 133 }, + { 35, 107 }, { 36, 134 }, { 39, 135 }, { 43, 136 }, { 47, 160 }, { 48, 141 }, + { 51, 120 }, { 55, 110 }, { 57, 142 }, { 58, 143 }, { 59, 144 }, { 60, 145 }, + { 61, 151 }, { 63, 130 }, { 64, 116 }, { 65, 129 }, { 67, 138 }, { 68, 152 }, + { 69, 153 }, { 75, 157 }, { 77, 154 }, { 78, 155 }, { 79, 161 }, { 80, 162 }, + { 81, 163 }, { 82, 164 }, { 83, 171 }, { 84, 140 }, { 85, 165 }, { 86, 166 }, + { 87, 167 }, { 88, 168 }, { 95, 169 }, { 96, 170 }, { 97, 139 }, { 98, 156 }, + { 99, 117 }, { 100, 199 }, { 103, 173 }, { 104, 174 }, { 117, 201 }, { 120, 175 }, + { 123, 176 }, { 125, 177 }, { 129, 159 }, { 133, 106 }, { 144, 178 }, { 146, 179 }, + { 151, 180 }, { 152, 181 }, { 155, 128 }, { 158, 126 }, { 162, 148 }, { 164, 182 }, + { 165, 183 }, { 167, 184 }, { 168, 185 }, { 174, 186 }, { 177, 187 }, { 179, 188 }, + { 183, 189 }, { 184, 190 }, { 185, 191 }, { 186, 158 }, { 188, 150 }, { 202, 108 }, + { 203, 109 }, { 205, 146 }, { 209, 192 }, { 213, 127 }, { 215, 200 }, { 216, 193 }, + { 220, 172 }, { 221, 194 }, { 222, 195 }, { 223, 196 }, { 224, 197 }, { 225, 198 }, +}; + +static const struct msm_pinctrl_soc_data maili_tlmm = { + .pins = maili_pins, + .npins = ARRAY_SIZE(maili_pins), + .functions = maili_functions, + .nfunctions = ARRAY_SIZE(maili_functions), + .groups = maili_groups, + .ngroups = ARRAY_SIZE(maili_groups), + .ngpios = 227, + .wakeirq_map = maili_pdc_map, + .nwakeirq_map = ARRAY_SIZE(maili_pdc_map), + .egpio_func = 11, +}; + +static const struct of_device_id maili_tlmm_of_match[] = { + { .compatible = "qcom,maili-tlmm", }, + {}, +}; +MODULE_DEVICE_TABLE(of, maili_tlmm_of_match); + +static int maili_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &maili_tlmm); +} + +static struct platform_driver maili_tlmm_driver = { + .driver = { + .name = "maili-tlmm", + .of_match_table = maili_tlmm_of_match, + }, + .probe = maili_tlmm_probe, +}; + +static int __init maili_tlmm_init(void) +{ + return platform_driver_register(&maili_tlmm_driver); +} +arch_initcall(maili_tlmm_init); + +static void __exit maili_tlmm_exit(void) +{ + platform_driver_unregister(&maili_tlmm_driver); +} +module_exit(maili_tlmm_exit); + +MODULE_DESCRIPTION("Qualcomm Maili TLMM driver"); +MODULE_LICENSE("GPL"); From 03e661e5f2ba68c629cdf836350324e7630e9a80 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 30 Jun 2026 13:34:15 +0200 Subject: [PATCH 016/130] pinctrl: tb10x: Mark base as __iomem The compile tests are complaining that this is not correctly typed. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202606150641.cbQ05ZMM-lkp@intel.com/ Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-tb10x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-tb10x.c b/drivers/pinctrl/pinctrl-tb10x.c index 3f581404a9b9..b7cbd69dd877 100644 --- a/drivers/pinctrl/pinctrl-tb10x.c +++ b/drivers/pinctrl/pinctrl-tb10x.c @@ -479,7 +479,7 @@ struct tb10x_port { */ struct tb10x_pinctrl { struct pinctrl_dev *pctl; - void *base; + void __iomem *base; const struct tb10x_pinfuncgrp *pingroups; unsigned int pinfuncgrpcnt; unsigned int pinfuncnt; From 0a3ac9e9d20cfb653200bb82fc0c693f55cb2fd8 Mon Sep 17 00:00:00 2001 From: Khristine Andreea Barbulescu Date: Tue, 30 Jun 2026 14:53:58 +0200 Subject: [PATCH 017/130] pinctrl: s32cc: add/fix some comments Add/fix some comments and print statements. Reviewed-by: Linus Walleij Reviewed-by: Bartosz Golaszewski Signed-off-by: Andrei Stefanescu Signed-off-by: Khristine Andreea Barbulescu Reviewed-by: Frank Li Signed-off-by: Linus Walleij --- drivers/pinctrl/nxp/pinctrl-s32cc.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/nxp/pinctrl-s32cc.c b/drivers/pinctrl/nxp/pinctrl-s32cc.c index 56be6e8d624e..a249fd87858d 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32cc.c +++ b/drivers/pinctrl/nxp/pinctrl-s32cc.c @@ -60,6 +60,12 @@ static u32 get_pin_func(u32 pinmux) return pinmux & GENMASK(3, 0); } +/* + * struct s32_pinctrl_mem_region - memory region for a set of SIUL2 registers + * @map: regmap used for this range + * @pin_range: the pins controlled by these registers + * @name: name of the current range + */ struct s32_pinctrl_mem_region { struct regmap *map; const struct s32_pin_range *pin_range; @@ -67,7 +73,7 @@ struct s32_pinctrl_mem_region { }; /* - * Holds pin configuration for GPIO's. + * struct gpio_pin_config - holds pin configuration for GPIO's * @pin_id: Pin ID for this GPIO * @config: Pin settings * @list: Linked list entry for each gpio pin @@ -79,20 +85,22 @@ struct gpio_pin_config { }; /* - * Pad config save/restore for power suspend/resume. + * struct s32_pinctrl_context - pad config save/restore for suspend/resume + * @pads: saved values for the pads */ struct s32_pinctrl_context { unsigned int *pads; }; /* + * struct s32_pinctrl - private driver data * @dev: a pointer back to containing device * @pctl: a pointer to the pinctrl device structure * @regions: reserved memory regions with start/end pin * @info: structure containing information about the pin - * @gpio_configs: Saved configurations for GPIO pins - * @gpiop_configs_lock: lock for the `gpio_configs` list - * @s32_pinctrl_context: Configuration saved over system sleep + * @gpio_configs: saved configurations for GPIO pins + * @gpio_configs_lock: lock for the `gpio_configs` list + * @saved_context: configuration saved over system sleep */ struct s32_pinctrl { struct device *dev; @@ -970,7 +978,7 @@ int s32_pinctrl_probe(struct platform_device *pdev, ipctl); if (IS_ERR(ipctl->pctl)) return dev_err_probe(&pdev->dev, PTR_ERR(ipctl->pctl), - "could not register s32 pinctrl driver\n"); + "Could not register s32 pinctrl driver\n"); #ifdef CONFIG_PM_SLEEP saved_context = &ipctl->saved_context; From e25c57c1426f8d0d17b99fe74d9b6cd4b16cf9b0 Mon Sep 17 00:00:00 2001 From: Khristine Andreea Barbulescu Date: Tue, 30 Jun 2026 14:53:59 +0200 Subject: [PATCH 018/130] pinctrl: s32cc: remove inline specifiers Remove unnecessary inline specifiers from static functions. Reviewed-by: Linus Walleij Reviewed-by: Bartosz Golaszewski Signed-off-by: Andrei Stefanescu Signed-off-by: Khristine Andreea Barbulescu Reviewed-by: Frank Li Tested-by: Enric Balletbo i Serra Signed-off-by: Linus Walleij --- drivers/pinctrl/nxp/pinctrl-s32cc.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/nxp/pinctrl-s32cc.c b/drivers/pinctrl/nxp/pinctrl-s32cc.c index a249fd87858d..db850b7b11e5 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32cc.c +++ b/drivers/pinctrl/nxp/pinctrl-s32cc.c @@ -131,13 +131,13 @@ s32_get_region(struct pinctrl_dev *pctldev, unsigned int pin) return NULL; } -static inline int s32_check_pin(struct pinctrl_dev *pctldev, - unsigned int pin) +static int s32_check_pin(struct pinctrl_dev *pctldev, + unsigned int pin) { return s32_get_region(pctldev, pin) ? 0 : -EINVAL; } -static inline int s32_regmap_read(struct pinctrl_dev *pctldev, +static int s32_regmap_read(struct pinctrl_dev *pctldev, unsigned int pin, unsigned int *val) { struct s32_pinctrl_mem_region *region; @@ -153,7 +153,7 @@ static inline int s32_regmap_read(struct pinctrl_dev *pctldev, return regmap_read(region->map, offset, val); } -static inline int s32_regmap_write(struct pinctrl_dev *pctldev, +static int s32_regmap_write(struct pinctrl_dev *pctldev, unsigned int pin, unsigned int val) { @@ -171,7 +171,7 @@ static inline int s32_regmap_write(struct pinctrl_dev *pctldev, } -static inline int s32_regmap_update(struct pinctrl_dev *pctldev, unsigned int pin, +static int s32_regmap_update(struct pinctrl_dev *pctldev, unsigned int pin, unsigned int mask, unsigned int val) { struct s32_pinctrl_mem_region *region; @@ -484,8 +484,8 @@ static int s32_get_slew_regval(int arg) return -EINVAL; } -static inline void s32_pin_set_pull(enum pin_config_param param, - unsigned int *mask, unsigned int *config) +static void s32_pin_set_pull(enum pin_config_param param, + unsigned int *mask, unsigned int *config) { switch (param) { case PIN_CONFIG_BIAS_DISABLE: From d10d65d6a2fa0b97f67b8c3ee52303e967b2633c Mon Sep 17 00:00:00 2001 From: Andrei Stefanescu Date: Tue, 30 Jun 2026 14:54:00 +0200 Subject: [PATCH 019/130] pinctrl: s32cc: change to "devm_pinctrl_register_and_init" Switch from "devm_pinctrl_register" to "devm_pinctrl_register_and_init" and "pinctrl_enable" since this is the recommended way. Reviewed-by: Linus Walleij Reviewed-by: Frank Li Reviewed-by: Linus Walleij Reviewed-by: Bartosz Golaszewski Signed-off-by: Andrei Stefanescu Signed-off-by: Khristine Andreea Barbulescu Tested-by: Enric Balletbo i Serra Signed-off-by: Linus Walleij --- drivers/pinctrl/nxp/pinctrl-s32cc.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/nxp/pinctrl-s32cc.c b/drivers/pinctrl/nxp/pinctrl-s32cc.c index db850b7b11e5..4b40770a38b7 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32cc.c +++ b/drivers/pinctrl/nxp/pinctrl-s32cc.c @@ -974,10 +974,10 @@ int s32_pinctrl_probe(struct platform_device *pdev, return dev_err_probe(&pdev->dev, ret, "Fail to probe dt properties\n"); - ipctl->pctl = devm_pinctrl_register(&pdev->dev, s32_pinctrl_desc, - ipctl); - if (IS_ERR(ipctl->pctl)) - return dev_err_probe(&pdev->dev, PTR_ERR(ipctl->pctl), + ret = devm_pinctrl_register_and_init(&pdev->dev, s32_pinctrl_desc, + ipctl, &ipctl->pctl); + if (ret) + return dev_err_probe(&pdev->dev, ret, "Could not register s32 pinctrl driver\n"); #ifdef CONFIG_PM_SLEEP @@ -990,7 +990,12 @@ int s32_pinctrl_probe(struct platform_device *pdev, return -ENOMEM; #endif - dev_info(&pdev->dev, "initialized s32 pinctrl driver\n"); + ret = pinctrl_enable(ipctl->pctl); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "Failed to enable pinctrl\n"); + + dev_info(&pdev->dev, "Initialized S32 pinctrl driver\n"); return 0; } From e91152802f0d71c14289b1f86d27ec143c49fbdb Mon Sep 17 00:00:00 2001 From: Khristine Andreea Barbulescu Date: Tue, 30 Jun 2026 14:54:01 +0200 Subject: [PATCH 020/130] dt-bindings: pinctrl: s32g2-siul2: describe GPIO and EIRQ resources Extend the S32G2 SIUL2 pinctrl binding to describe the GPIO data and external interrupt resources present in the same SIUL2 hardware block. Besides the MSCR and IMCR registers used for pin multiplexing and pad configuration, SIUL2 also contains PGPDO and PGPDI registers for GPIO data and EIRQ registers for external interrupt control. Add GPIO controller properties because the SIUL2 block also provides GPIO functionality, and gpio-ranges are needed to describe the mapping between GPIO lines and pin controller pins. Document the interrupt controller properties. The SIUL2 block contains EIRQ hardware as part of the same register space. IRQ support itself will be added in a follow-up patch series. Update the example accordingly to show the complete SIUL2 register layout, including the GPIO data and EIRQ register windows. Reviewed-by: Linus Walleij Reviewed-by: Rob Herring (Arm) Signed-off-by: Khristine Andreea Barbulescu Reviewed-by: Bartosz Golaszewski Signed-off-by: Linus Walleij --- .../pinctrl/nxp,s32g2-siul2-pinctrl.yaml | 90 +++++++++++++++++-- 1 file changed, 84 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml index a24286e4def6..36f2393fa406 100644 --- a/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -# Copyright 2022 NXP +# Copyright 2022, 2026 NXP %YAML 1.2 --- $id: http://devicetree.org/schemas/pinctrl/nxp,s32g2-siul2-pinctrl.yaml# @@ -17,8 +17,10 @@ description: | SIUL2_0 @ 0x4009c000 SIUL2_1 @ 0x44010000 - Every SIUL2 region has multiple register types, and here only MSCR and - IMCR registers need to be revealed for kernel to configure pinmux. + Every SIUL2 region has multiple register types. MSCR and IMCR registers + need to be revealed for kernel to configure pinmux. PGPDO and PGPDI + registers are used for GPIO output/input operations. EIRQ registers + are used for external interrupt configuration. Please note that some register indexes are reserved in S32G2, such as MSCR102-MSCR111, MSCR123-MSCR143, IMCR84-IMCR118 and IMCR398-IMCR429. @@ -29,14 +31,22 @@ properties: - nxp,s32g2-siul2-pinctrl reg: + minItems: 6 description: | - A list of MSCR/IMCR register regions to be reserved. + A list of MSCR/IMCR/PGPDO/PGPDI/EIRQ register regions to be reserved. - MSCR (Multiplexed Signal Configuration Register) An MSCR register can configure the associated pin as either a GPIO pin or a function output pin depends on the selected signal source. - IMCR (Input Multiplexed Signal Configuration Register) An IMCR register can configure the associated pin as function input pin depends on the selected signal source. + - PGPDO (Parallel GPIO Pad Data Out Register) + A PGPDO register is used to set the output value of a GPIO pin. + - PGPDI (Parallel GPIO Pad Data In Register) + A PGPDI register is used to read the input value of a GPIO pin. + - EIRQ (External Interrupt Request) + EIRQ registers are used to configure and manage external interrupts. + items: - description: MSCR registers group 0 in SIUL2_0 - description: MSCR registers group 1 in SIUL2_1 @@ -44,6 +54,28 @@ properties: - description: IMCR registers group 0 in SIUL2_0 - description: IMCR registers group 1 in SIUL2_1 - description: IMCR registers group 2 in SIUL2_1 + - description: PGPDO registers in SIUL2_0 + - description: PGPDI registers in SIUL2_0 + - description: PGPDO registers in SIUL2_1 + - description: PGPDI registers in SIUL2_1 + - description: EIRQ registers in SIUL2_1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + + gpio-ranges: + minItems: 1 + maxItems: 4 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + interrupts: + maxItems: 1 patternProperties: '-pins$': @@ -86,11 +118,38 @@ required: - compatible - reg +oneOf: + - description: Legacy pinctrl-only node + properties: + reg: + maxItems: 6 + + gpio-controller: false + "#gpio-cells": false + gpio-ranges: false + interrupt-controller: false + "#interrupt-cells": false + interrupts: false + + - description: Pinctrl node with GPIO and external interrupt support + required: + - gpio-controller + - "#gpio-cells" + - gpio-ranges + - interrupt-controller + - "#interrupt-cells" + - interrupts + properties: + reg: + minItems: 11 + additionalProperties: false examples: - | - pinctrl@4009c240 { + #include + + pinctrl: pinctrl@4009c240 { compatible = "nxp,s32g2-siul2-pinctrl"; /* MSCR0-MSCR101 registers on siul2_0 */ @@ -104,7 +163,26 @@ examples: /* IMCR119-IMCR397 registers on siul2_1 */ <0x44010c1c 0x45c>, /* IMCR430-IMCR495 registers on siul2_1 */ - <0x440110f8 0x108>; + <0x440110f8 0x108>, + /* PGPDO registers on siul2_0 */ + <0x4009d700 0x10>, + /* PGPDI registers on siul2_0 */ + <0x4009d740 0x10>, + /* PGPDO registers on siul2_1 */ + <0x44011700 0x18>, + /* PGPDI registers on siul2_1 */ + <0x44011740 0x18>, + /* EIRQ registers on siul2_1 */ + <0x44010010 0x34>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 102>, + <&pinctrl 112 112 79>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; llce-can0-pins { llce-can0-grp0 { From 94cb9e8f270797e489633cfa53d2d44afecb8bef Mon Sep 17 00:00:00 2001 From: Andrei Stefanescu Date: Tue, 30 Jun 2026 14:54:02 +0200 Subject: [PATCH 021/130] pinctrl: s32cc: implement GPIO functionality The updated SIUL2 block groups pinctrl, GPIO data access and interrupt control within the same hardware unit. The SIUL2 driver is therefore structured as a monolithic pinctrl/GPIO driver. GPIO data access and direction handling are implemented using the gpio-regmap library backed by a virtual regmap. The virtual regmap translates the gpio-regmap register model to the underlying SIUL2 registers: MSCR for direction, PGPDI for input values and PGPDO for output values. The existing pinctrl GPIO callbacks are used for the request/free path: they switch the pad to GPIO mode on request and restore the previous MSCR configuration when the GPIO is released. This change came as a result of upstream review in the following series: https://lore.kernel.org/linux-gpio/20260120115923.3463866-4-khristineandreea.barbulescu@oss.nxp.com/T/#m543c9edbdde74bdc68b6a2364e8b975356c33043 https://lore.kernel.org/all/20260504131148.3622697-7-khristineandreea.barbulescu@oss.nxp.com/ Support both SIUL2 DT layouts: - legacy pinctrl-only binding - extended pinctrl/GPIO/irqchip binding Reviewed-by: Linus Walleij Signed-off-by: Andrei Stefanescu Signed-off-by: Khristine Andreea Barbulescu Reviewed-by: Bartosz Golaszewski Link: https://lore.kernel.org/linux-gpio/20260120115923.3463866-4-khristineandreea.barbulescu@oss.nxp.com/T/#m543c9edbdde74bdc68b6a2364e8b975356c33043 Link: https://lore.kernel.org/all/20260504131148.3622697-7-khristineandreea.barbulescu@oss.nxp.com/ Signed-off-by: Linus Walleij --- drivers/pinctrl/nxp/Kconfig | 3 +- drivers/pinctrl/nxp/pinctrl-s32.h | 35 +- drivers/pinctrl/nxp/pinctrl-s32cc.c | 721 +++++++++++++++++++++++++--- drivers/pinctrl/nxp/pinctrl-s32g2.c | 47 +- 4 files changed, 727 insertions(+), 79 deletions(-) diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig index abca7ef97003..711c0fe11565 100644 --- a/drivers/pinctrl/nxp/Kconfig +++ b/drivers/pinctrl/nxp/Kconfig @@ -1,10 +1,11 @@ # SPDX-License-Identifier: GPL-2.0-only config PINCTRL_S32CC bool - depends on ARCH_S32 && OF + depends on ARCH_S32 && OF && GPIOLIB select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS select GENERIC_PINCONF + select GPIO_REGMAP select REGMAP_MMIO config PINCTRL_S32G2 diff --git a/drivers/pinctrl/nxp/pinctrl-s32.h b/drivers/pinctrl/nxp/pinctrl-s32.h index 8715befd5f05..028578a090e4 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32.h +++ b/drivers/pinctrl/nxp/pinctrl-s32.h @@ -2,7 +2,7 @@ * * S32 pinmux core definitions * - * Copyright 2016-2020, 2022 NXP + * Copyright 2016-2020, 2022, 2026 NXP * Copyright (C) 2022 SUSE LLC * Copyright 2015-2016 Freescale Semiconductor, Inc. * Copyright (C) 2012 Linaro Ltd. @@ -34,11 +34,42 @@ struct s32_pin_range { unsigned int end; }; +/** + * struct s32_gpio_range - contiguous GPIO pin range within a SIUL2 module + * @gpio_base: first GPIO line offset in the GPIO range + * @pin_base: first pinctrl pin number mapped by this GPIO range + * @gpio_num: number of consecutive GPIO pins in the range + * @sparse: true if the PGPD layout is non-linear (resolved via pad map only); + * pins not found in the pad map are invalid for this range + */ +struct s32_gpio_range { + unsigned int gpio_base; + unsigned int pin_base; + unsigned int gpio_num; + bool sparse; +}; + +/** + * struct s32_gpio_pad_map - mapping between GPIO ranges and PGPD pads + * @gpio_start: first GPIO line offset in the range + * @gpio_end: last GPIO line offset in the range + * @pad: PGPD pad number serving the range + */ +struct s32_gpio_pad_map { + unsigned int gpio_start; + unsigned int gpio_end; + unsigned int pad; +}; + struct s32_pinctrl_soc_data { const struct pinctrl_pin_desc *pins; unsigned int npins; const struct s32_pin_range *mem_pin_ranges; unsigned int mem_regions; + const struct s32_gpio_range *gpio_ranges; + unsigned int num_gpio_ranges; + const struct s32_gpio_pad_map *gpio_pad_maps; + unsigned int num_gpio_pad_maps; }; struct s32_pinctrl_soc_info { @@ -53,6 +84,8 @@ struct s32_pinctrl_soc_info { #define S32_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) #define S32_PIN_RANGE(_start, _end) { .start = _start, .end = _end } +#define S32_GPIO_RANGE(gpio, pin, num) \ + { .gpio_base = gpio, .pin_base = pin, .gpio_num = num } int s32_pinctrl_probe(struct platform_device *pdev, const struct s32_pinctrl_soc_data *soc_data); diff --git a/drivers/pinctrl/nxp/pinctrl-s32cc.c b/drivers/pinctrl/nxp/pinctrl-s32cc.c index 4b40770a38b7..0025add68495 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32cc.c +++ b/drivers/pinctrl/nxp/pinctrl-s32cc.c @@ -2,7 +2,7 @@ /* * Core driver for the S32 CC (Common Chassis) pin controller * - * Copyright 2017-2022,2024-2025 NXP + * Copyright 2017-2022,2024-2026 NXP * Copyright (C) 2022 SUSE LLC * Copyright 2015-2016 Freescale Semiconductor, Inc. */ @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -39,6 +40,40 @@ #define S32_MSCR_ODE BIT(20) #define S32_MSCR_OBE BIT(21) +#define S32_GPIO_OP_SHIFT 16 +#define S32_GPIO_OP_MASK GENMASK(19, 16) + +#define S32_GPIO_OP_DIR 0 /* MSCR direction */ +#define S32_GPIO_OP_DAT BIT(S32_GPIO_OP_SHIFT) /* PGPDI read */ +#define S32_GPIO_OP_SET BIT(S32_GPIO_OP_SHIFT + 1) /* PGPDO write */ + +/* + * [15:12] = GPIO bank / gpio range index + * [11:0] = real register offset or pin id + */ +#define S32_GPIO_BANK_SHIFT 12 +#define S32_GPIO_BANK_MASK GENMASK(15, 12) +#define S32_GPIO_REG_MASK GENMASK(11, 0) + +#define S32_GPIO_ENCODE(bank, off) \ + ((((bank) << S32_GPIO_BANK_SHIFT) & S32_GPIO_BANK_MASK) | \ + ((off) & S32_GPIO_REG_MASK)) + +#define S32_GPIO_DECODE_BANK(reg) \ + (((reg) & S32_GPIO_BANK_MASK) >> S32_GPIO_BANK_SHIFT) + +#define S32_GPIO_DECODE_OFF(reg) \ + ((reg) & S32_GPIO_REG_MASK) + +/* + * PGPDOs are 16bit registers that come in big endian + * order if they are grouped in pairs of two. + * + * For example, the order is PGPDO1, PGPDO0, PGPDO3, PGPDO2... + */ +#define S32_PGPD(N) (((N) ^ 1) * 2) +#define S32_PGPD_SIZE 16 + enum s32_write_type { S32_PINCONF_UPDATE_ONLY, S32_PINCONF_OVERWRITE, @@ -72,6 +107,18 @@ struct s32_pinctrl_mem_region { char name[8]; }; +/* + * struct s32_gpio_regmaps - GPIO register maps for a SIUL2 instance + * @pgpdo: regmap for Parallel GPIO Pad Data Out registers + * @pgpdi: regmap for Parallel GPIO Pad Data In registers + * @range: GPIO range info + */ +struct s32_gpio_regmaps { + struct regmap *pgpdo; + struct regmap *pgpdi; + const struct s32_gpio_range *range; +}; + /* * struct gpio_pin_config - holds pin configuration for GPIO's * @pin_id: Pin ID for this GPIO @@ -98,6 +145,12 @@ struct s32_pinctrl_context { * @pctl: a pointer to the pinctrl device structure * @regions: reserved memory regions with start/end pin * @info: structure containing information about the pin + * @gpio_regmaps: PGPDO/PGPDI regmaps for each SIUL2 module + * @num_gpio_regmaps: number of GPIO regmap entries + * @gpio_regmap: regmap bridging gpio-regmap to SIUL2 registers + * @gpio_rgm: gpio-regmap instance registered for this controller + * @ngpio: total number of GPIO line offsets + * @gpio_names: GPIO line names array passed to gpio-regmap * @gpio_configs: saved configurations for GPIO pins * @gpio_configs_lock: lock for the `gpio_configs` list * @saved_context: configuration saved over system sleep @@ -107,6 +160,12 @@ struct s32_pinctrl { struct pinctrl_dev *pctl; struct s32_pinctrl_mem_region *regions; struct s32_pinctrl_soc_info *info; + struct s32_gpio_regmaps *gpio_regmaps; + unsigned int num_gpio_regmaps; + struct regmap *gpio_regmap; + struct gpio_regmap *gpio_rgm; + unsigned int ngpio; + const char *const *gpio_names; struct list_head gpio_configs; spinlock_t gpio_configs_lock; #ifdef CONFIG_PM_SLEEP @@ -356,6 +415,63 @@ static int s32_pmx_get_funcs_count(struct pinctrl_dev *pctldev) return info->nfunctions; } +static int s32_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + struct gpio_pin_config *gpio_pin __free(kfree) = NULL; + unsigned int config; + int ret; + + ret = s32_regmap_read(pctldev, pin, &config); + if (ret) + return ret; + + gpio_pin = kmalloc_obj(*gpio_pin, GFP_KERNEL); + if (!gpio_pin) + return -ENOMEM; + + gpio_pin->pin_id = pin; + gpio_pin->config = config; + + /* GPIO pin means SSS = 0 */ + ret = s32_regmap_update(pctldev, pin, + S32_MSCR_SSS_MASK | S32_MSCR_IBE, + S32_MSCR_IBE); + if (ret) + return ret; + + scoped_guard(spinlock_irqsave, &ipctl->gpio_configs_lock) + list_add(&no_free_ptr(gpio_pin)->list, &ipctl->gpio_configs); + + return 0; +} + +static void s32_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + struct gpio_pin_config *gpio_pin, *found = NULL; + unsigned long flags; + + spin_lock_irqsave(&ipctl->gpio_configs_lock, flags); + list_for_each_entry(gpio_pin, &ipctl->gpio_configs, list) { + if (gpio_pin->pin_id == pin) { + list_del(&gpio_pin->list); + found = gpio_pin; + break; + } + } + spin_unlock_irqrestore(&ipctl->gpio_configs_lock, flags); + + if (found) { + s32_regmap_write(pctldev, found->pin_id, found->config); + kfree(found); + } +} + static const char *s32_pmx_get_func_name(struct pinctrl_dev *pctldev, unsigned int selector) { @@ -379,67 +495,6 @@ static int s32_pmx_get_groups(struct pinctrl_dev *pctldev, return 0; } -static int s32_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int offset) -{ - struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - struct gpio_pin_config *gpio_pin; - unsigned int config; - unsigned long flags; - int ret; - - ret = s32_regmap_read(pctldev, offset, &config); - if (ret) - return ret; - - /* Save current configuration */ - gpio_pin = kmalloc_obj(*gpio_pin); - if (!gpio_pin) - return -ENOMEM; - - gpio_pin->pin_id = offset; - gpio_pin->config = config; - INIT_LIST_HEAD(&gpio_pin->list); - - spin_lock_irqsave(&ipctl->gpio_configs_lock, flags); - list_add(&gpio_pin->list, &ipctl->gpio_configs); - spin_unlock_irqrestore(&ipctl->gpio_configs_lock, flags); - - /* GPIO pin means SSS = 0 */ - config &= ~S32_MSCR_SSS_MASK; - - return s32_regmap_write(pctldev, offset, config); -} - -static void s32_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int offset) -{ - struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - struct gpio_pin_config *gpio_pin, *tmp; - unsigned long flags; - int ret; - - spin_lock_irqsave(&ipctl->gpio_configs_lock, flags); - - list_for_each_entry_safe(gpio_pin, tmp, &ipctl->gpio_configs, list) { - if (gpio_pin->pin_id == offset) { - ret = s32_regmap_write(pctldev, gpio_pin->pin_id, - gpio_pin->config); - if (ret != 0) - goto unlock; - - list_del(&gpio_pin->list); - kfree(gpio_pin); - break; - } - } - -unlock: - spin_unlock_irqrestore(&ipctl->gpio_configs_lock, flags); -} - static int s32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int offset, @@ -649,9 +704,9 @@ static void s32_pinconf_dbg_show(struct pinctrl_dev *pctldev, ret = s32_regmap_read(pctldev, pin_id, &config); if (ret) - return; - - seq_printf(s, "0x%x", config); + seq_printf(s, "error %d", ret); + else + seq_printf(s, "0x%x", config); } static void s32_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, @@ -669,8 +724,11 @@ static void s32_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, for (i = 0; i < grp->data.npins; i++) { name = pin_get_name(pctldev, grp->data.pins[i]); ret = s32_regmap_read(pctldev, grp->data.pins[i], &config); - if (ret) - return; + if (ret) { + seq_printf(s, "%s: error %d\n", name, ret); + continue; + } + seq_printf(s, "%s: 0x%x\n", name, config); } } @@ -683,6 +741,477 @@ static const struct pinconf_ops s32_pinconf_ops = { .pin_config_group_dbg_show = s32_pinconf_group_dbg_show, }; +static void s32_gpio_free_saved_configs(void *data) +{ + struct s32_pinctrl *ipctl = data; + struct gpio_pin_config *gpio_pin, *tmp; + unsigned long flags; + + spin_lock_irqsave(&ipctl->gpio_configs_lock, flags); + list_for_each_entry_safe(gpio_pin, tmp, &ipctl->gpio_configs, list) { + list_del(&gpio_pin->list); + kfree(gpio_pin); + } + spin_unlock_irqrestore(&ipctl->gpio_configs_lock, flags); +} + +static unsigned int s32_pin2pad(unsigned int pin) +{ + return pin / S32_PGPD_SIZE; +} + +static u16 s32_pin2mask(unsigned int pin) +{ + /* + * From Reference manual : + * PGPDOx[PPDOy] = GPDO(x × 16) + (15 - y)[PDO_(x × 16) + (15 - y)] + */ + return BIT(S32_PGPD_SIZE - 1 - pin % S32_PGPD_SIZE); +} + +static int s32_gpio_get_range(struct s32_pinctrl *ipctl, + unsigned int gpio, + unsigned int *pin, + unsigned int *bank) +{ + const struct s32_pinctrl_soc_data *soc_data = ipctl->info->soc_data; + const struct s32_gpio_range *range; + int i; + + for (i = 0; i < soc_data->num_gpio_ranges; i++) { + range = &soc_data->gpio_ranges[i]; + + if (gpio < range->gpio_base || + gpio >= range->gpio_base + range->gpio_num) + continue; + + if (pin) + *pin = range->pin_base + gpio - range->gpio_base; + + if (bank) + *bank = i; + + return 0; + } + + return -EINVAL; +} + +static int s32_gpio_pad_map_xlate(struct s32_pinctrl *ipctl, + unsigned int gpio, + unsigned int *reg_offset, + u16 *mask) +{ + const struct s32_pinctrl_soc_data *soc_data = ipctl->info->soc_data; + const struct s32_gpio_pad_map *map; + unsigned int bit; + int i; + + if (!soc_data->gpio_pad_maps || !soc_data->num_gpio_pad_maps) + return -EINVAL; + + for (i = 0; i < soc_data->num_gpio_pad_maps; i++) { + map = &soc_data->gpio_pad_maps[i]; + + if (gpio < map->gpio_start || gpio > map->gpio_end) + continue; + + bit = gpio - map->gpio_start; + *mask = BIT(S32_PGPD_SIZE - 1 - bit); + *reg_offset = S32_PGPD(map->pad); + + return 0; + } + + return -EINVAL; +} + +static bool s32_gpio_pin_is_sparse(struct s32_pinctrl *ipctl, unsigned int pin) +{ + const struct s32_pinctrl_soc_data *soc_data = ipctl->info->soc_data; + const struct s32_gpio_range *range; + int i; + + for (i = 0; i < soc_data->num_gpio_ranges; i++) { + range = &soc_data->gpio_ranges[i]; + if (pin >= range->pin_base && + pin < range->pin_base + range->gpio_num) + return range->sparse; + } + + return false; +} + +static int s32_gpio_xlate_pgpd(struct s32_pinctrl *ipctl, + unsigned int pin, + unsigned int *reg_offset, + u16 *mask) +{ + int ret; + + /* + * Try the pad map first. For sparse ranges (SIUL2_1), only pins + * listed in the pad map are valid, return the error directly without + * falling back to the linear layout. + * For linear ranges (SIUL2_0), fall back to the linear pad-to-PGPD + * formula if no pad map entry matches. + */ + ret = s32_gpio_pad_map_xlate(ipctl, pin, reg_offset, mask); + if (ret != -EINVAL) + return ret; + + if (s32_gpio_pin_is_sparse(ipctl, pin)) + return -EINVAL; + + /* Linear layout fallback for non-sparse ranges. */ + *mask = s32_pin2mask(pin); + *reg_offset = S32_PGPD(s32_pin2pad(pin)); + + return 0; +} + +static int s32_gpio_reg_mask_xlate(struct gpio_regmap *gpio, + unsigned int base, unsigned int offset, + unsigned int *reg, unsigned int *mask) +{ + struct s32_pinctrl *ipctl = gpio_regmap_get_drvdata(gpio); + unsigned int pgpd_reg, pin, bank; + u16 pgpd_mask; + int ret; + + ret = s32_gpio_get_range(ipctl, offset, &pin, &bank); + if (ret) + return ret; + + switch (base) { + case S32_GPIO_OP_DIR: + /* + * Direction is controlled through MSCR OBE. + * Encode the real pin id in the virtual register. + */ + *reg = S32_GPIO_OP_DIR | pin; + *mask = S32_MSCR_OBE; + return 0; + + case S32_GPIO_OP_DAT: + case S32_GPIO_OP_SET: + ret = s32_gpio_xlate_pgpd(ipctl, pin, &pgpd_reg, &pgpd_mask); + if (ret) + return ret; + /* + * Encode both the GPIO bank and the real PGPD register offset. + */ + *reg = base | S32_GPIO_ENCODE(bank, pgpd_reg); + *mask = pgpd_mask; + return 0; + default: + return -EINVAL; + } +} + +static int s32_gpio_reg_read(void *context, unsigned int reg, + unsigned int *val) +{ + struct s32_pinctrl *ipctl = context; + unsigned int op = reg & S32_GPIO_OP_MASK; + unsigned int vreg = reg & ~S32_GPIO_OP_MASK; + unsigned int bank; + unsigned int offset; + struct regmap *map; + + switch (op) { + case S32_GPIO_OP_DIR: + /* + * Lower bits contain the real MSCR pin id. + */ + offset = S32_GPIO_DECODE_OFF(vreg); + + return s32_regmap_read(ipctl->pctl, offset, val); + + case S32_GPIO_OP_DAT: + bank = S32_GPIO_DECODE_BANK(vreg); + offset = S32_GPIO_DECODE_OFF(vreg); + + if (bank >= ipctl->num_gpio_regmaps) + return -EINVAL; + + map = ipctl->gpio_regmaps[bank].pgpdi; + if (!map) + return -ENODEV; + + return regmap_read(map, offset, val); + + case S32_GPIO_OP_SET: + /* + * gpio-regmap uses update_bits() for set, so it needs to read + * the output register before writing the updated value. + */ + bank = S32_GPIO_DECODE_BANK(vreg); + offset = S32_GPIO_DECODE_OFF(vreg); + + if (bank >= ipctl->num_gpio_regmaps) + return -EINVAL; + + map = ipctl->gpio_regmaps[bank].pgpdo; + if (!map) + return -ENODEV; + + return regmap_read(map, offset, val); + + default: + return -EINVAL; + } +} + +static int s32_gpio_reg_write(void *context, unsigned int reg, + unsigned int val) +{ + struct s32_pinctrl *ipctl = context; + unsigned int op = reg & S32_GPIO_OP_MASK; + unsigned int vreg = reg & ~S32_GPIO_OP_MASK; + unsigned int bank, offset, config; + struct regmap *map; + + switch (op) { + case S32_GPIO_OP_DIR: + /* + * gpio-regmap sets S32_MSCR_OBE for output and clears it for + * input. Keep IBE enabled for GPIOs in both cases. + */ + offset = S32_GPIO_DECODE_OFF(vreg); + + config = S32_MSCR_IBE; + if (val & S32_MSCR_OBE) + config |= S32_MSCR_OBE; + + return s32_regmap_update(ipctl->pctl, offset, + S32_MSCR_OBE | S32_MSCR_IBE, + config); + + case S32_GPIO_OP_SET: + bank = S32_GPIO_DECODE_BANK(vreg); + offset = S32_GPIO_DECODE_OFF(vreg); + + if (bank >= ipctl->num_gpio_regmaps) + return -EINVAL; + + map = ipctl->gpio_regmaps[bank].pgpdo; + if (!map) + return -ENODEV; + + return regmap_write(map, offset, val); + + default: + return -EINVAL; + } +} + +static const struct regmap_bus s32_gpio_regmap_bus = { + .reg_read = s32_gpio_reg_read, + .reg_write = s32_gpio_reg_write, +}; + +static const struct regmap_config s32_gpio_regmap_config = { + .name = "s32-gpio", + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 1, + .max_register = S32_GPIO_OP_SET | S32_GPIO_BANK_MASK | S32_GPIO_REG_MASK, + .cache_type = REGCACHE_NONE, + .fast_io = true, +}; + +static int s32_gpio_get_ngpio(const struct s32_pinctrl_soc_data *soc_data, + unsigned int *ngpio) +{ + const struct s32_gpio_range *range; + unsigned int end, max = 0; + int i; + + if (!soc_data->gpio_ranges || !soc_data->num_gpio_ranges) + return -EINVAL; + + for (i = 0; i < soc_data->num_gpio_ranges; i++) { + range = &soc_data->gpio_ranges[i]; + + if (!range->gpio_num) + return -EINVAL; + + end = range->gpio_base + range->gpio_num; + + /* + * gpio_ranges must be ordered by gpio_base and must not overlap. + * The GPIO line space size is derived from the highest range end. + */ + if (i > 0 && range->gpio_base < max) + return -EINVAL; + + if (end > max) + max = end; + } + + *ngpio = max; + + return 0; +} + +static int s32_init_gpio_regmap(struct platform_device *pdev, + struct s32_pinctrl *ipctl) +{ + ipctl->gpio_regmap = + devm_regmap_init(&pdev->dev, &s32_gpio_regmap_bus, + ipctl, &s32_gpio_regmap_config); + if (IS_ERR(ipctl->gpio_regmap)) + return dev_err_probe(&pdev->dev, + PTR_ERR(ipctl->gpio_regmap), + "Failed to init GPIO regmap\n"); + + return 0; +} + +static int s32_init_valid_mask(struct gpio_chip *chip, unsigned long *mask, + unsigned int ngpios) +{ + struct gpio_regmap *gpio = gpiochip_get_data(chip); + struct s32_pinctrl *ipctl = gpio_regmap_get_drvdata(gpio); + unsigned int gpio_num, pin, reg_offset; + u16 pgpd_mask; + int ret; + + bitmap_zero(mask, ngpios); + + for (gpio_num = 0; gpio_num < ngpios; gpio_num++) { + ret = s32_gpio_get_range(ipctl, gpio_num, &pin, NULL); + if (ret) + continue; + + ret = s32_gpio_xlate_pgpd(ipctl, pin, ®_offset, &pgpd_mask); + if (ret) + continue; + + bitmap_set(mask, gpio_num, 1); + } + + return 0; +} + +static int s32_gpio_populate_names(struct s32_pinctrl *ipctl) +{ + char **names; + unsigned int gpio; + unsigned int pin; + char port; + int ret; + + names = devm_kcalloc(ipctl->dev, ipctl->ngpio, sizeof(*names), + GFP_KERNEL); + if (!names) + return -ENOMEM; + + for (gpio = 0; gpio < ipctl->ngpio; gpio++) { + ret = s32_gpio_get_range(ipctl, gpio, &pin, NULL); + if (ret) + continue; + + port = 'A' + pin / 16; + + names[gpio] = devm_kasprintf(ipctl->dev, GFP_KERNEL, + "P%c_%02u", port, pin & 0xf); + if (!names[gpio]) + return -ENOMEM; + } + + ipctl->gpio_names = (const char *const *)names; + + return 0; +} + +static int s32_pinctrl_init_gpio_regmaps(struct platform_device *pdev, + struct s32_pinctrl *ipctl) +{ + const struct s32_pinctrl_soc_data *soc_data = ipctl->info->soc_data; + static const struct regmap_config pgpd_config = { + .reg_bits = 32, + .val_bits = 16, + .reg_stride = 2, + }; + struct regmap_config cfg; + struct resource *res; + void __iomem *base; + unsigned int pgpdo_idx, pgpdi_idx; + unsigned int i; + + if (!soc_data->gpio_ranges || !soc_data->num_gpio_ranges) + return 0; + + ipctl->num_gpio_regmaps = soc_data->num_gpio_ranges; + ipctl->gpio_regmaps = devm_kcalloc(&pdev->dev, ipctl->num_gpio_regmaps, + sizeof(*ipctl->gpio_regmaps), + GFP_KERNEL); + if (!ipctl->gpio_regmaps) + return -ENOMEM; + + for (i = 0; i < ipctl->num_gpio_regmaps; i++) { + ipctl->gpio_regmaps[i].range = &soc_data->gpio_ranges[i]; + + /* + * GPIO resources are placed after the pinctrl regions + */ + pgpdo_idx = soc_data->mem_regions + i * 2; + pgpdi_idx = soc_data->mem_regions + i * 2 + 1; + + /* PGPDO */ + res = platform_get_resource(pdev, IORESOURCE_MEM, pgpdo_idx); + if (!res) + return dev_err_probe(&pdev->dev, -ENOENT, + "Missing PGPDO resource %u\n", i); + + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + cfg = pgpd_config; + cfg.name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "pgpdo%u", i); + if (!cfg.name) + return -ENOMEM; + + cfg.max_register = resource_size(res) - cfg.reg_stride; + + ipctl->gpio_regmaps[i].pgpdo = + devm_regmap_init_mmio(&pdev->dev, base, &cfg); + if (IS_ERR(ipctl->gpio_regmaps[i].pgpdo)) + return dev_err_probe(&pdev->dev, + PTR_ERR(ipctl->gpio_regmaps[i].pgpdo), + "Failed to init PGPDO regmap %u\n", i); + + /* PGPDI */ + res = platform_get_resource(pdev, IORESOURCE_MEM, pgpdi_idx); + if (!res) + return dev_err_probe(&pdev->dev, -ENOENT, + "Missing PGPDI resource %u\n", i); + + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + cfg = pgpd_config; + cfg.name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "pgpdi%u", i); + if (!cfg.name) + return -ENOMEM; + + cfg.max_register = resource_size(res) - cfg.reg_stride; + + ipctl->gpio_regmaps[i].pgpdi = + devm_regmap_init_mmio(&pdev->dev, base, &cfg); + if (IS_ERR(ipctl->gpio_regmaps[i].pgpdi)) + return dev_err_probe(&pdev->dev, + PTR_ERR(ipctl->gpio_regmaps[i].pgpdi), + "Failed to init PGPDI regmap %u\n", i); + } + + return 0; +} + #ifdef CONFIG_PM_SLEEP static bool s32_pinctrl_should_save(struct s32_pinctrl *ipctl, unsigned int pin) @@ -709,8 +1238,7 @@ int s32_pinctrl_suspend(struct device *dev) const struct pinctrl_pin_desc *pin; const struct s32_pinctrl_soc_info *info = ipctl->info; struct s32_pinctrl_context *saved_context = &ipctl->saved_context; - int i; - int ret; + int i, ret; unsigned int config; for (i = 0; i < info->soc_data->npins; i++) { @@ -721,7 +1249,7 @@ int s32_pinctrl_suspend(struct device *dev) ret = s32_regmap_read(ipctl->pctl, pin->number, &config); if (ret) - return -EINVAL; + return ret; saved_context->pads[i] = config; } @@ -736,7 +1264,7 @@ int s32_pinctrl_resume(struct device *dev) const struct s32_pinctrl_soc_info *info = ipctl->info; const struct pinctrl_pin_desc *pin; struct s32_pinctrl_context *saved_context = &ipctl->saved_context; - int ret, i; + int i, ret; for (i = 0; i < info->soc_data->npins; i++) { pin = &info->soc_data->pins[i]; @@ -745,7 +1273,7 @@ int s32_pinctrl_resume(struct device *dev) continue; ret = s32_regmap_write(ipctl->pctl, pin->number, - saved_context->pads[i]); + saved_context->pads[i]); if (ret) return ret; } @@ -928,9 +1456,11 @@ int s32_pinctrl_probe(struct platform_device *pdev, #ifdef CONFIG_PM_SLEEP struct s32_pinctrl_context *saved_context; #endif + struct gpio_regmap_config gpio_cfg = {}; struct pinctrl_desc *s32_pinctrl_desc; struct s32_pinctrl_soc_info *info; struct s32_pinctrl *ipctl; + unsigned int ngpio; int ret; if (!soc_data || !soc_data->pins || !soc_data->npins) @@ -956,6 +1486,11 @@ int s32_pinctrl_probe(struct platform_device *pdev, INIT_LIST_HEAD(&ipctl->gpio_configs); spin_lock_init(&ipctl->gpio_configs_lock); + ret = devm_add_action_or_reset(&pdev->dev, + s32_gpio_free_saved_configs, ipctl); + if (ret) + return ret; + s32_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*s32_pinctrl_desc), GFP_KERNEL); if (!s32_pinctrl_desc) @@ -974,6 +1509,11 @@ int s32_pinctrl_probe(struct platform_device *pdev, return dev_err_probe(&pdev->dev, ret, "Fail to probe dt properties\n"); + ret = s32_pinctrl_init_gpio_regmaps(pdev, ipctl); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "Failed to init GPIO regmaps\n"); + ret = devm_pinctrl_register_and_init(&pdev->dev, s32_pinctrl_desc, ipctl, &ipctl->pctl); if (ret) @@ -995,7 +1535,42 @@ int s32_pinctrl_probe(struct platform_device *pdev, return dev_err_probe(&pdev->dev, ret, "Failed to enable pinctrl\n"); - dev_info(&pdev->dev, "Initialized S32 pinctrl driver\n"); + /* Setup GPIO if GPIO ranges are defined */ + if (!soc_data->gpio_ranges || !soc_data->num_gpio_ranges) + return 0; + + ret = s32_gpio_get_ngpio(soc_data, &ngpio); + if (ret) + return dev_err_probe(&pdev->dev, ret, "Invalid GPIO ranges\n"); + + ipctl->ngpio = ngpio; + + ret = s32_gpio_populate_names(ipctl); + if (ret) + return ret; + + ret = s32_init_gpio_regmap(pdev, ipctl); + if (ret) + return ret; + + gpio_cfg.parent = &pdev->dev; + gpio_cfg.fwnode = dev_fwnode(&pdev->dev); + gpio_cfg.label = dev_name(&pdev->dev); + gpio_cfg.regmap = ipctl->gpio_regmap; + gpio_cfg.ngpio = ngpio; + gpio_cfg.names = ipctl->gpio_names; + gpio_cfg.reg_dir_out_base = GPIO_REGMAP_ADDR(S32_GPIO_OP_DIR); + gpio_cfg.reg_dat_base = GPIO_REGMAP_ADDR(S32_GPIO_OP_DAT); + gpio_cfg.reg_set_base = GPIO_REGMAP_ADDR(S32_GPIO_OP_SET); + gpio_cfg.reg_mask_xlate = s32_gpio_reg_mask_xlate; + gpio_cfg.init_valid_mask = s32_init_valid_mask; + gpio_cfg.drvdata = ipctl; + + ipctl->gpio_rgm = devm_gpio_regmap_register(&pdev->dev, &gpio_cfg); + if (IS_ERR(ipctl->gpio_rgm)) + return dev_err_probe(&pdev->dev, + PTR_ERR(ipctl->gpio_rgm), + "Unable to add gpio_regmap chip\n"); return 0; } diff --git a/drivers/pinctrl/nxp/pinctrl-s32g2.c b/drivers/pinctrl/nxp/pinctrl-s32g2.c index c49d28793b69..f9546c67a269 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32g2.c +++ b/drivers/pinctrl/nxp/pinctrl-s32g2.c @@ -3,7 +3,7 @@ * NXP S32G pinctrl driver * * Copyright 2015-2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018, 2020-2022 NXP + * Copyright 2017-2018, 2020-2022, 2025-2026 NXP * Copyright (C) 2022 SUSE LLC */ @@ -773,17 +773,48 @@ static const struct s32_pin_range s32_pin_ranges_siul2[] = { S32_PIN_RANGE(942, 1007), }; -static const struct s32_pinctrl_soc_data s32_pinctrl_data = { +static const struct s32_gpio_range s32_gpio_ranges_siul2[] = { + S32_GPIO_RANGE(0, 0, 102), + /* SIUL2_1: sparse layout, PGPD mapping required for all pins */ + { .gpio_base = 112, .pin_base = 112, .gpio_num = 79, .sparse = true }, +}; + +/* + * SIUL2_1 GPIO ranges mapped to sparse PGPD pads. + * + * SIUL2_1 does not expose GPIO data registers as a linear pad + * sequence. Each entry describes a contiguous GPIO offset range + * and the PGPD pad servicing that range. + */ +static const struct s32_gpio_pad_map s32g_gpio_pad_maps[] = { + { 112, 122, 7 }, /* PH_00 .. PH_10 -> PGPD7 */ + { 144, 159, 9 }, /* PJ_00 .. PJ_15 -> PGPD9 */ + { 160, 175, 10 }, /* PK_00 .. PK_15 -> PGPD10 */ + { 176, 190, 11 }, /* PL_00 .. PL_14 -> PGPD11 */ +}; + +/* Legacy data for old DT bindings without GPIO support */ +static const struct s32_pinctrl_soc_data legacy_s32g_pinctrl_data = { .pins = s32_pinctrl_pads_siul2, .npins = ARRAY_SIZE(s32_pinctrl_pads_siul2), .mem_pin_ranges = s32_pin_ranges_siul2, .mem_regions = ARRAY_SIZE(s32_pin_ranges_siul2), }; +static const struct s32_pinctrl_soc_data s32g_pinctrl_data = { + .pins = s32_pinctrl_pads_siul2, + .npins = ARRAY_SIZE(s32_pinctrl_pads_siul2), + .mem_pin_ranges = s32_pin_ranges_siul2, + .mem_regions = ARRAY_SIZE(s32_pin_ranges_siul2), + .gpio_ranges = s32_gpio_ranges_siul2, + .num_gpio_ranges = ARRAY_SIZE(s32_gpio_ranges_siul2), + .gpio_pad_maps = s32g_gpio_pad_maps, + .num_gpio_pad_maps = ARRAY_SIZE(s32g_gpio_pad_maps), +}; + static const struct of_device_id s32_pinctrl_of_match[] = { { .compatible = "nxp,s32g2-siul2-pinctrl", - .data = &s32_pinctrl_data, }, { /* sentinel */ } }; @@ -792,8 +823,16 @@ MODULE_DEVICE_TABLE(of, s32_pinctrl_of_match); static int s32g_pinctrl_probe(struct platform_device *pdev) { const struct s32_pinctrl_soc_data *soc_data; + struct device_node *np = pdev->dev.of_node; - soc_data = of_device_get_match_data(&pdev->dev); + /* + * Legacy DTs only describe the pinctrl resources. + * New DT changes extend the same node with GPIO resources. + */ + if (of_property_present(np, "gpio-controller")) + soc_data = &s32g_pinctrl_data; + else + soc_data = &legacy_s32g_pinctrl_data; return s32_pinctrl_probe(pdev, soc_data); } From f790ea0b699d95d18572979b1bc1673d8f31eb3c Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 7 Jul 2026 14:51:37 +0530 Subject: [PATCH 022/130] pinctrl: qcom: Acknowledge IRQs for PDC interrupt controller PDC needs to acknowledge incoming GPIO interrupts to clear the latched interrupt status in secondary mode of PDC. For level-triggered IRQs this happens automatically in irq_eoi() but for edge-triggered IRQs this needs to happen as early as possible in the IRQ handler. Implement this by using handle_fasteoi_ack_irq() as IRQ handler in this situation and forward the irq_ack() callback to the parent IRQ chip. Signed-off-by: Stephan Gerhold Signed-off-by: Maulik Shah Link: https://patch.msgid.link/20260707-hamoa_pdc_v3-v4-5-dfd1f4a3ae89@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski --- drivers/pinctrl/qcom/pinctrl-msm.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 1055d42381bb..838969186185 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -994,6 +994,16 @@ static void msm_gpio_irq_ack(struct irq_data *d) if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) msm_gpio_update_dual_edge_parent(d); + + /* + * During early initialization of the IRQ hierarchy, + * irq_ack() is called by __irq_set_handler() before + * the parent IRQ chip has been set up. This is why + * we additionally need to check for d->parent_data->chip. + */ + + if (d->parent_data->chip && d->parent_data->chip->irq_ack) + irq_chip_ack_parent(d); return; } @@ -1064,7 +1074,10 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { clear_bit(d->hwirq, pctrl->dual_edge_irqs); - irq_set_handler_locked(d, handle_fasteoi_irq); + if (type & IRQ_TYPE_LEVEL_MASK) + irq_set_handler_locked(d, handle_fasteoi_irq); + else + irq_set_handler_locked(d, handle_fasteoi_ack_irq); return 0; } From 77fbc756d9cbe53a9496cb2c53ae209d37d5af2d Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Tue, 7 Jul 2026 14:51:38 +0530 Subject: [PATCH 023/130] Revert "pinctrl: qcom: x1e80100: Bypass PDC wakeup parent for now" This reverts commit 602cb14e310a ("pinctrl: qcom: x1e80100: Bypass PDC wakeup parent for now"). PDC interrupts no more break GPIOs PDC irqchip is updated to work for pass through or secondary mode. Update nwakeirq_map to reflect the GPIO to PDC irq map size. Signed-off-by: Maulik Shah Link: https://patch.msgid.link/20260707-hamoa_pdc_v3-v4-6-dfd1f4a3ae89@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski --- drivers/pinctrl/qcom/pinctrl-x1e80100.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-x1e80100.c b/drivers/pinctrl/qcom/pinctrl-x1e80100.c index 8d2b8246170b..e4c0abcd95b9 100644 --- a/drivers/pinctrl/qcom/pinctrl-x1e80100.c +++ b/drivers/pinctrl/qcom/pinctrl-x1e80100.c @@ -1836,9 +1836,7 @@ static const struct msm_pinctrl_soc_data x1e80100_pinctrl = { .ngroups = ARRAY_SIZE(x1e80100_groups), .ngpios = 239, .wakeirq_map = x1e80100_pdc_map, - /* TODO: Enabling PDC currently breaks GPIO interrupts */ - .nwakeirq_map = 0, - /* .nwakeirq_map = ARRAY_SIZE(x1e80100_pdc_map), */ + .nwakeirq_map = ARRAY_SIZE(x1e80100_pdc_map), .egpio_func = 9, }; From ebcba7cd38cd26ab4cfee8ea2eb38aabf1ec51fc Mon Sep 17 00:00:00 2001 From: Gary Wang Date: Mon, 6 Jul 2026 18:36:34 +0800 Subject: [PATCH 024/130] pinctrl: tigerlake: add some pin groups and functions for INTC1055 Add i2c0, i2c1, pwm0, uart1, ssp2 pin groups & functions in tgllp_soc_data for device id INTC1055. The pinctrl-upboard driver set the correct pin function corresponding to these data. Signed-off-by: Gary Wang Acked-by: Linus Walleij Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-tigerlake.c | 32 +++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/pinctrl/intel/pinctrl-tigerlake.c b/drivers/pinctrl/intel/pinctrl-tigerlake.c index ae231f7fba49..0a11b9dac3dd 100644 --- a/drivers/pinctrl/intel/pinctrl-tigerlake.c +++ b/drivers/pinctrl/intel/pinctrl-tigerlake.c @@ -330,6 +330,34 @@ static const struct pinctrl_pin_desc tgllp_pins[] = { PINCTRL_PIN(276, "SPI0_CLK_LOOPBK"), }; +static const unsigned int tgllp_i2c0_pins[] = { 5, 6 }; +static const unsigned int tgllp_i2c1_pins[] = { 7, 8 }; +static const unsigned int tgllp_pwm0_pins[] = { 99 }; +static const unsigned int tgllp_uart1_pins[] = { 85, 86, 87, 88 }; +static const unsigned int tgllp_ssp2_pins[] = { 108, 109, 110, 111 }; + +static const struct intel_pingroup tgllp_groups[] = { + PIN_GROUP("i2c0_grp", tgllp_i2c0_pins, 2), + PIN_GROUP("i2c1_grp", tgllp_i2c1_pins, 2), + PIN_GROUP("pwm0_grp", tgllp_pwm0_pins, 2), + PIN_GROUP("uart1_grp", tgllp_uart1_pins, 2), + PIN_GROUP("ssp2_grp", tgllp_ssp2_pins, 7), +}; + +static const char * const tgllp_i2c0_groups[] = { "i2c0_grp" }; +static const char * const tgllp_i2c1_groups[] = { "i2c1_grp" }; +static const char * const tgllp_pwm0_groups[] = { "pwm0_grp" }; +static const char * const tgllp_uart1_groups[] = { "uart1_grp" }; +static const char * const tgllp_ssp2_groups[] = { "ssp2_grp" }; + +static const struct intel_function tgllp_functions[] = { + FUNCTION("i2c0", tgllp_i2c0_groups), + FUNCTION("i2c1", tgllp_i2c1_groups), + FUNCTION("pwm0", tgllp_pwm0_groups), + FUNCTION("uart1", tgllp_uart1_groups), + FUNCTION("ssp2", tgllp_ssp2_groups), +}; + static const struct intel_padgroup tgllp_community0_gpps[] = { INTEL_GPP(0, 0, 25, 0), /* GPP_B */ INTEL_GPP(1, 26, 41, 32), /* GPP_T */ @@ -367,6 +395,10 @@ static const struct intel_community tgllp_communities[] = { static const struct intel_pinctrl_soc_data tgllp_soc_data = { .pins = tgllp_pins, .npins = ARRAY_SIZE(tgllp_pins), + .groups = tgllp_groups, + .ngroups = ARRAY_SIZE(tgllp_groups), + .functions = tgllp_functions, + .nfunctions = ARRAY_SIZE(tgllp_functions), .communities = tgllp_communities, .ncommunities = ARRAY_SIZE(tgllp_communities), }; From b9949964daa827c05cdce06a765c2e81d1c64d02 Mon Sep 17 00:00:00 2001 From: Gary Wang Date: Mon, 6 Jul 2026 18:36:35 +0800 Subject: [PATCH 025/130] pinctrl: upboard: add device id INTC1055 based UP boards support Add support "UP Xtreme i12" and I2C/PWM/UART/SPI pins mapping data. Signed-off-by: Gary Wang Reviewed-by: Thomas Richard Acked-by: Linus Walleij Acked-by: Mika Westerberg Tested-by: Thomas Richard Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-upboard.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/pinctrl/pinctrl-upboard.c b/drivers/pinctrl/pinctrl-upboard.c index f8c8b9d84990..de1920a3387d 100644 --- a/drivers/pinctrl/pinctrl-upboard.c +++ b/drivers/pinctrl/pinctrl-upboard.c @@ -912,6 +912,19 @@ static const struct upboard_pinctrl_map upboard_pinctrl_map_apl01 = { .nmaps = ARRAY_SIZE(pinctrl_map_apl01), }; +static const struct pinctrl_map pinctrl_map_adl[] = { + PIN_MAP_MUX_GROUP_DEFAULT("upboard-pinctrl", "INTC1055:00", "i2c0_grp", "i2c0"), + PIN_MAP_MUX_GROUP_DEFAULT("upboard-pinctrl", "INTC1055:00", "i2c1_grp", "i2c1"), + PIN_MAP_MUX_GROUP_DEFAULT("upboard-pinctrl", "INTC1055:00", "pwm0_grp", "pwm0"), + PIN_MAP_MUX_GROUP_DEFAULT("upboard-pinctrl", "INTC1055:00", "uart1_grp", "uart1"), + PIN_MAP_MUX_GROUP_DEFAULT("upboard-pinctrl", "INTC1055:00", "ssp2_grp", "ssp2"), +}; + +static const struct upboard_pinctrl_map upboard_pinctrl_map_adl = { + .maps = &pinctrl_map_adl[0], + .nmaps = ARRAY_SIZE(pinctrl_map_adl), +}; + static const struct dmi_system_id dmi_platform_info[] = { { /* UP Squared */ @@ -921,6 +934,14 @@ static const struct dmi_system_id dmi_platform_info[] = { }, .driver_data = (void *)&upboard_pinctrl_map_apl01, }, + { + /* UP Xtreme i12 */ + .matches = { + DMI_EXACT_MATCH(DMI_SYS_VENDOR, "AAEON"), + DMI_EXACT_MATCH(DMI_BOARD_NAME, "UPX-ADLP01"), + }, + .driver_data = (void *)&upboard_pinctrl_map_adl, + }, { } }; From 5fe4b12c087db3e565f53b87f1dafdf2f0d1ee0f Mon Sep 17 00:00:00 2001 From: Pengpeng Hou Date: Sat, 4 Jul 2026 23:22:30 +0800 Subject: [PATCH 026/130] pinctrl: sx150x: add missing MODULE_DEVICE_TABLE() The driver has a match table for the i2c bus wired into its driver structure, but the table is not exported with MODULE_DEVICE_TABLE(). Add the missing MODULE_DEVICE_TABLE() entry so module alias information is generated for automatic module loading. This is a source-level fix. It does not claim dynamic hardware reproduction; the evidence is the driver-owned match table, its use by the driver registration structure, and the missing module alias publication. Signed-off-by: Pengpeng Hou Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-sx150x.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c index b59d913513d5..89fdfa96843f 100644 --- a/drivers/pinctrl/pinctrl-sx150x.c +++ b/drivers/pinctrl/pinctrl-sx150x.c @@ -850,6 +850,7 @@ static const struct i2c_device_id sx150x_id[] = { { .name = "sx1509q", .driver_data = (kernel_ulong_t)&sx1509q_device_data }, { } }; +MODULE_DEVICE_TABLE(i2c, sx150x_id); static const struct of_device_id sx150x_of_match[] = { { .compatible = "semtech,sx1501q", .data = &sx1501q_device_data }, From 81d79de72a32b723ed3f86406eed5a0d0c4abaf2 Mon Sep 17 00:00:00 2001 From: Yuhong Cheng Date: Sun, 5 Jul 2026 15:02:12 +0800 Subject: [PATCH 027/130] docs: driver-api: pin-control: fix spelling of below Fix the spelling of 'bellow' to 'below' in the PM API section. Signed-off-by: Yuhong Cheng Acked-by: Randy Dunlap Signed-off-by: Linus Walleij --- Documentation/driver-api/pin-control.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/driver-api/pin-control.rst b/Documentation/driver-api/pin-control.rst index 1f585ecca63c..80106e44a368 100644 --- a/Documentation/driver-api/pin-control.rst +++ b/Documentation/driver-api/pin-control.rst @@ -1175,7 +1175,7 @@ Possible standard state names are: "default", "init", "sleep" and "idle". selected after the driver probe. - the ``sleep`` and ``idle`` states are for power management and can only - be selected with the PM API bellow. + be selected with the PM API below. PM interfaces ================= From 3f0245e23a176e78f00a760291b8e4f88d01d77e Mon Sep 17 00:00:00 2001 From: Alex Tran Date: Sun, 5 Jul 2026 09:01:04 -0700 Subject: [PATCH 028/130] pinctrl: pinctrl-rp1: Make use of str_hi_lo helper Use the str_hi_lo helper API to print value of a pin for debugging instead of using ternary operator. Signed-off-by: Alex Tran Reviewed-by: Andrea della Porta Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-rp1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-rp1.c b/drivers/pinctrl/pinctrl-rp1.c index fc4ed68ea5ac..dd0e85c2ca33 100644 --- a/drivers/pinctrl/pinctrl-rp1.c +++ b/drivers/pinctrl/pinctrl-rp1.c @@ -1085,7 +1085,7 @@ static void rp1_pctl_pin_dbg_show(struct pinctrl_dev *pctldev, seq_printf(s, "function %s (%s) in %s; irq %d (%s)", rp1_func_names[fsel].name, rp1_func_names[func].name, - value ? "hi" : "lo", + str_hi_lo(value), irq, irq_type_names[pin->irq_type]); } From 4c870bbaba1b011375b1f551c205a8538bf77230 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Wed, 20 May 2026 22:13:17 -0700 Subject: [PATCH 029/130] pinctrl: renesas: gpio: isolate function gpiochip from parent fwnode The sh-pfc driver registers two separate gpiochip instances: one for real GPIOs and another for function GPIOs. Since both share the same parent platform device, gpiolib's fallback logic causes both chips to share the same firmware node (fwnode). This causes ambiguity when using software nodes to describe GPIOs, as gpiolib may apply hogs meant for one chip to the other if they share the same node. Explicitly set gc->fwnode to ERR_PTR(-ENODEV) for the function GPIO chip. This satisfies gpiolib's check for an existing fwnode and prevents it from falling back to the parent device's node, while ensuring that no actual properties or hogs are found on the function chip unless explicitly assigned later. Assisted-by: Gemini:gemini-3.1-pro Signed-off-by: Dmitry Torokhov Acked-by: Bartosz Golaszewski Reviewed-by: Linus Walleij Signed-off-by: Linus Walleij --- drivers/pinctrl/renesas/gpio.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pinctrl/renesas/gpio.c b/drivers/pinctrl/renesas/gpio.c index 2293af642849..4e59dadb7364 100644 --- a/drivers/pinctrl/renesas/gpio.c +++ b/drivers/pinctrl/renesas/gpio.c @@ -278,6 +278,12 @@ static int gpio_function_setup(struct sh_pfc_chip *chip) gc->request = gpio_function_request; + /* + * Explicitly mask the parent's fwnode to prevent gpiolib from + * reusing it for function GPIOs. + */ + gc->fwnode = ERR_PTR(-ENODEV); + gc->label = pfc->info->name; gc->owner = THIS_MODULE; gc->base = pfc->nr_gpio_pins; From 62067bc0a083eb45b9f588745b3846cf366e2d35 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Wed, 20 May 2026 22:13:18 -0700 Subject: [PATCH 030/130] sh: pfc: attach software node to the GPIO chip With commit e5d527be7e69 ("gpio: swnode: don't use the swnode's name as the key for GPIO lookup") gpiolib requires that firmware nodes from the GPIO references to match firmware node in gpiochip structure. Define a software node for the pfc gpiochip so that it can be referenced by boards using static device properties. Signed-off-by: Dmitry Torokhov Reviewed-by: Bartosz Golaszewski Reviewed-by: Linus Walleij Signed-off-by: Linus Walleij --- arch/sh/include/cpu-common/cpu/pfc.h | 3 +++ arch/sh/kernel/cpu/pfc.c | 20 ++++++++++++++------ 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/arch/sh/include/cpu-common/cpu/pfc.h b/arch/sh/include/cpu-common/cpu/pfc.h index 879d2c9da537..d57e38c05bdb 100644 --- a/arch/sh/include/cpu-common/cpu/pfc.h +++ b/arch/sh/include/cpu-common/cpu/pfc.h @@ -11,6 +11,9 @@ #include struct resource; +struct software_node; + +extern const struct software_node pfc_gpiochip_node; int sh_pfc_register(const char *name, struct resource *resource, u32 num_resources); diff --git a/arch/sh/kernel/cpu/pfc.c b/arch/sh/kernel/cpu/pfc.c index 062056ede88d..5a8d804d607b 100644 --- a/arch/sh/kernel/cpu/pfc.c +++ b/arch/sh/kernel/cpu/pfc.c @@ -5,21 +5,29 @@ * Copyright (C) 2012 Renesas Solutions Corp. */ +#include #include #include +#include #include -static struct platform_device sh_pfc_device = { - .id = -1, +const struct software_node pfc_gpiochip_node = { + .name = "sh-pfc", }; int __init sh_pfc_register(const char *name, struct resource *resource, u32 num_resources) { - sh_pfc_device.name = name; - sh_pfc_device.num_resources = num_resources; - sh_pfc_device.resource = resource; + struct platform_device_info pdev_info = { + .name = name, + .id = PLATFORM_DEVID_NONE, + .res = resource, + .num_res = num_resources, + .swnode = &pfc_gpiochip_node, + }; + struct platform_device *pdev; - return platform_device_register(&sh_pfc_device); + pdev = platform_device_register_full(&pdev_info); + return PTR_ERR_OR_ZERO(pdev); } From 6905cdac0e51b067f0060b052724d696b4087f8a Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Wed, 20 May 2026 22:13:19 -0700 Subject: [PATCH 031/130] sh: mach-rsk: rsk7203: use static device properties for LEDs and GPIO buttons Convert the board to use static device properties instead of platform data to describe LEDs and GPIO-connected buttons on the board, so that support for platform data can be removed from gpio-keys and other drivers, unifying their behavior. Signed-off-by: Dmitry Torokhov Reviewed-by: Bartosz Golaszewski Reviewed-by: Linus Walleij Signed-off-by: Linus Walleij --- arch/sh/boards/mach-rsk/devices-rsk7203.c | 221 ++++++++++++++-------- 1 file changed, 142 insertions(+), 79 deletions(-) diff --git a/arch/sh/boards/mach-rsk/devices-rsk7203.c b/arch/sh/boards/mach-rsk/devices-rsk7203.c index e6b05d4588b7..f8760a91e2f1 100644 --- a/arch/sh/boards/mach-rsk/devices-rsk7203.c +++ b/arch/sh/boards/mach-rsk/devices-rsk7203.c @@ -4,17 +4,19 @@ * * Copyright (C) 2008 - 2010 Paul Mundt */ +#include #include #include #include #include #include #include +#include #include -#include -#include +#include +#include #include -#include +#include #include static struct smsc911x_platform_config smsc911x_config = { @@ -37,92 +39,138 @@ static struct resource smsc911x_resources[] = { }, }; -static struct platform_device smsc911x_device = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(smsc911x_resources), - .resource = smsc911x_resources, - .dev = { - .platform_data = &smsc911x_config, +static const struct software_node rsk7203_gpio_leds_node = { + .name = "rsk7203-gpio-leds", +}; + +static const struct software_node rsk7203_green_led_node = { + .name = "green", + .parent = &rsk7203_gpio_leds_node, + .properties = (const struct property_entry[]) { + PROPERTY_ENTRY_STRING("label", "green"), + PROPERTY_ENTRY_GPIO("gpios", &pfc_gpiochip_node, + GPIO_PE10, GPIO_ACTIVE_LOW), + { } }, }; -static struct gpio_led rsk7203_gpio_leds[] = { +static const struct software_node rsk7203_orange_led_node = { + .name = "orange", + .parent = &rsk7203_gpio_leds_node, + .properties = (const struct property_entry[]) { + PROPERTY_ENTRY_STRING("label", "orange"), + PROPERTY_ENTRY_STRING("linux,default-trigger", "nand-disk"), + PROPERTY_ENTRY_GPIO("gpios", &pfc_gpiochip_node, + GPIO_PE12, GPIO_ACTIVE_LOW), + { } + }, +}; + +static const struct software_node rsk7203_red1_led_node = { + .name = "red:timer", + .parent = &rsk7203_gpio_leds_node, + .properties = (const struct property_entry[]) { + PROPERTY_ENTRY_STRING("label", "red:timer"), + PROPERTY_ENTRY_STRING("linux,default-trigger", "timer"), + PROPERTY_ENTRY_GPIO("gpios", &pfc_gpiochip_node, + GPIO_PC14, GPIO_ACTIVE_LOW), + { } + }, +}; + +static const struct software_node rsk7203_red2_led_node = { + .name = "red:heartbeat", + .parent = &rsk7203_gpio_leds_node, + .properties = (const struct property_entry[]) { + PROPERTY_ENTRY_STRING("label", "red:heartbeat"), + PROPERTY_ENTRY_STRING("linux,default-trigger", "heartbeat"), + PROPERTY_ENTRY_GPIO("gpios", &pfc_gpiochip_node, + GPIO_PE11, GPIO_ACTIVE_LOW), + { } + }, +}; + +static const struct software_node rsk7203_gpio_keys_node = { + .name = "rsk7203-gpio-keys", + .properties = (const struct property_entry[]) { + PROPERTY_ENTRY_U32("poll-interval", 50), + { } + }, +}; + +static const struct software_node rsk7203_sw1_key_node = { + .parent = &rsk7203_gpio_keys_node, + .properties = (const struct property_entry[]) { + PROPERTY_ENTRY_U32("linux,code", BTN_0), + PROPERTY_ENTRY_GPIO("gpios", &pfc_gpiochip_node, + GPIO_PB0, GPIO_ACTIVE_LOW), + PROPERTY_ENTRY_STRING("label", "SW1"), + { } + }, +}; + +static const struct software_node rsk7203_sw2_key_node = { + .parent = &rsk7203_gpio_keys_node, + .properties = (const struct property_entry[]) { + PROPERTY_ENTRY_U32("linux,code", BTN_1), + PROPERTY_ENTRY_GPIO("gpios", &pfc_gpiochip_node, + GPIO_PB1, GPIO_ACTIVE_LOW), + PROPERTY_ENTRY_STRING("label", "SW2"), + { } + }, +}; + +static const struct software_node rsk7203_sw3_key_node = { + .parent = &rsk7203_gpio_keys_node, + .properties = (const struct property_entry[]) { + PROPERTY_ENTRY_U32("linux,code", BTN_2), + PROPERTY_ENTRY_GPIO("gpios", &pfc_gpiochip_node, + GPIO_PB2, GPIO_ACTIVE_LOW), + PROPERTY_ENTRY_STRING("label", "SW3"), + { } + }, +}; + +static const struct software_node * const rsk7203_swnodes[] __initconst = { + &rsk7203_gpio_leds_node, + &rsk7203_green_led_node, + &rsk7203_orange_led_node, + &rsk7203_red1_led_node, + &rsk7203_red2_led_node, + &rsk7203_gpio_keys_node, + &rsk7203_sw1_key_node, + &rsk7203_sw2_key_node, + &rsk7203_sw3_key_node, + NULL +}; + +static const struct platform_device_info rsk7203_devices[] __initconst = { { - .name = "green", - .gpio = GPIO_PE10, - .active_low = 1, - }, { - .name = "orange", - .default_trigger = "nand-disk", - .gpio = GPIO_PE12, - .active_low = 1, - }, { - .name = "red:timer", - .default_trigger = "timer", - .gpio = GPIO_PC14, - .active_low = 1, - }, { - .name = "red:heartbeat", - .default_trigger = "heartbeat", - .gpio = GPIO_PE11, - .active_low = 1, + .name = "smsc911x", + .id = PLATFORM_DEVID_NONE, + .res = smsc911x_resources, + .num_res = ARRAY_SIZE(smsc911x_resources), + .data = &smsc911x_config, + .size_data = sizeof(smsc911x_config), }, -}; - -static struct gpio_led_platform_data rsk7203_gpio_leds_info = { - .leds = rsk7203_gpio_leds, - .num_leds = ARRAY_SIZE(rsk7203_gpio_leds), -}; - -static struct platform_device led_device = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &rsk7203_gpio_leds_info, - }, -}; - -static struct gpio_keys_button rsk7203_gpio_keys_table[] = { { - .code = BTN_0, - .gpio = GPIO_PB0, - .active_low = 1, - .desc = "SW1", - }, { - .code = BTN_1, - .gpio = GPIO_PB1, - .active_low = 1, - .desc = "SW2", - }, { - .code = BTN_2, - .gpio = GPIO_PB2, - .active_low = 1, - .desc = "SW3", + .name = "leds-gpio", + .id = PLATFORM_DEVID_NONE, + .swnode = &rsk7203_gpio_leds_node, }, -}; - -static struct gpio_keys_platform_data rsk7203_gpio_keys_info = { - .buttons = rsk7203_gpio_keys_table, - .nbuttons = ARRAY_SIZE(rsk7203_gpio_keys_table), - .poll_interval = 50, /* default to 50ms */ -}; - -static struct platform_device keys_device = { - .name = "gpio-keys-polled", - .dev = { - .platform_data = &rsk7203_gpio_keys_info, + { + .name = "gpio-keys-polled", + .id = PLATFORM_DEVID_NONE, + .swnode = &rsk7203_gpio_keys_node, }, }; -static struct platform_device *rsk7203_devices[] __initdata = { - &smsc911x_device, - &led_device, - &keys_device, -}; - static int __init rsk7203_devices_setup(void) { + struct platform_device *pd; + int error; + int i; + /* Select pins for SCIF0 */ gpio_request(GPIO_FN_TXD0, NULL); gpio_request(GPIO_FN_RXD0, NULL); @@ -131,7 +179,22 @@ static int __init rsk7203_devices_setup(void) __raw_writel(0x36db0400, 0xfffc0008); /* CS1BCR */ gpio_request(GPIO_FN_IRQ0_PB, NULL); - return platform_add_devices(rsk7203_devices, - ARRAY_SIZE(rsk7203_devices)); + error = software_node_register_node_group(rsk7203_swnodes); + if (error) { + pr_err("failed to register software nodes: %d\n", error); + return error; + } + + for (i = 0; i < ARRAY_SIZE(rsk7203_devices); i++) { + pd = platform_device_register_full(&rsk7203_devices[i]); + error = PTR_ERR_OR_ZERO(pd); + if (error) { + pr_err("failed to create platform device %s: %d\n", + rsk7203_devices[i].name, error); + return error; + } + } + + return 0; } device_initcall(rsk7203_devices_setup); From c5b962b6023d3299cc9988e32288d5f2aeb206f1 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Wed, 20 May 2026 22:13:20 -0700 Subject: [PATCH 032/130] pinctrl: renesas: gpio: support software nodes for function GPIOs This patch extends the sh-pfc GPIO driver to support software-node-based configuration for the secondary 'function' GPIO chip. While the primary GPIO chip typically uses the firmware node attached to the parent platform device, the secondary chip should target a specific child node to avoid ambiguity when defining GPIO hogs or properties. Update gpio_function_setup() to look for a child node named 'functions', but only when the parent is a software node. This ensures the behavior is restricted to legacy platforms being migrated to software nodes. Assisted-by: Gemini:gemini-3.1-pro Signed-off-by: Dmitry Torokhov Reviewed-by: Bartosz Golaszewski Reviewed-by: Linus Walleij Signed-off-by: Linus Walleij --- drivers/pinctrl/renesas/gpio.c | 28 +++++++++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/renesas/gpio.c b/drivers/pinctrl/renesas/gpio.c index 4e59dadb7364..b49a3e14da91 100644 --- a/drivers/pinctrl/renesas/gpio.c +++ b/drivers/pinctrl/renesas/gpio.c @@ -271,18 +271,40 @@ static int gpio_function_request(struct gpio_chip *gc, unsigned offset) return ret; } +static void sh_pfc_fwnode_put(void *data) +{ + fwnode_handle_put(data); +} + static int gpio_function_setup(struct sh_pfc_chip *chip) { struct sh_pfc *pfc = chip->pfc; struct gpio_chip *gc = &chip->gpio_chip; + struct fwnode_handle *fwnode = dev_fwnode(pfc->dev); gc->request = gpio_function_request; + if (is_software_node(fwnode)) { + fwnode = fwnode_get_named_child_node(fwnode, "functions"); + if (fwnode) { + int ret; + + ret = devm_add_action_or_reset(pfc->dev, + sh_pfc_fwnode_put, + fwnode); + if (ret) + return ret; + + gc->fwnode = fwnode; + } + } + /* - * Explicitly mask the parent's fwnode to prevent gpiolib from - * reusing it for function GPIOs. + * If we did not find 'functions' node, explicitly mask the parent's + * fwnode to prevent gpiolib from reusing it for function GPIOs. */ - gc->fwnode = ERR_PTR(-ENODEV); + if (!gc->fwnode) + gc->fwnode = ERR_PTR(-ENODEV); gc->label = pfc->info->name; gc->owner = THIS_MODULE; From 106dc49414c47497e9678b1a0a46e161ffeacb5b Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Wed, 20 May 2026 22:13:21 -0700 Subject: [PATCH 033/130] sh: mach-rsk: rsk7203: convert pin configuration to using software nodes Replace legacy gpio_request() calls used to configure function pins (SCIF0 TXD/RXD and LAN9118 IRQ) with software nodes describing GPIO hogs. These hogs are attached to the PFC gpiochip node, allowing the GPIO subsystem to automatically configure these pins when the driver is registered. Assisted-by: Gemini:gemini-3.1-pro Signed-off-by: Dmitry Torokhov Reviewed-by: Bartosz Golaszewski Reviewed-by: Linus Walleij Signed-off-by: Linus Walleij --- arch/sh/boards/mach-rsk/devices-rsk7203.c | 97 ++++++++++++++++++++--- 1 file changed, 85 insertions(+), 12 deletions(-) diff --git a/arch/sh/boards/mach-rsk/devices-rsk7203.c b/arch/sh/boards/mach-rsk/devices-rsk7203.c index f8760a91e2f1..e8a8fc1d2ca9 100644 --- a/arch/sh/boards/mach-rsk/devices-rsk7203.c +++ b/arch/sh/boards/mach-rsk/devices-rsk7203.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -131,6 +130,56 @@ static const struct software_node rsk7203_sw3_key_node = { }, }; +/* The base of the function GPIOs in the flat enum */ +#define SH7203_FN_BASE GPIO_FN_PINT7_PB + +static const struct software_node rsk7203_pfc_functions_node = { + .name = "functions", + .parent = &pfc_gpiochip_node, +}; + +static const struct software_node rsk7203_txd0_hog_node = { + .name = "txd0-hog", + .parent = &rsk7203_pfc_functions_node, + .properties = (const struct property_entry[]) { + PROPERTY_ENTRY_BOOL("gpio-hog"), + PROPERTY_ENTRY_U32_ARRAY("gpios", ((u32[]){ + GPIO_FN_TXD0 - SH7203_FN_BASE, GPIO_ACTIVE_HIGH + })), + PROPERTY_ENTRY_BOOL("input"), + PROPERTY_ENTRY_STRING("line-name", "TXD0"), + { } + }, +}; + +static const struct software_node rsk7203_rxd0_hog_node = { + .name = "rxd0-hog", + .parent = &rsk7203_pfc_functions_node, + .properties = (const struct property_entry[]) { + PROPERTY_ENTRY_BOOL("gpio-hog"), + PROPERTY_ENTRY_U32_ARRAY("gpios", ((u32[]){ + GPIO_FN_RXD0 - SH7203_FN_BASE, GPIO_ACTIVE_HIGH + })), + PROPERTY_ENTRY_BOOL("input"), + PROPERTY_ENTRY_STRING("line-name", "RXD0"), + { } + }, +}; + +static const struct software_node rsk7203_irq0_hog_node = { + .name = "irq0-hog", + .parent = &rsk7203_pfc_functions_node, + .properties = (const struct property_entry[]) { + PROPERTY_ENTRY_BOOL("gpio-hog"), + PROPERTY_ENTRY_U32_ARRAY("gpios", ((u32[]){ + GPIO_FN_IRQ0_PB - SH7203_FN_BASE, GPIO_ACTIVE_HIGH + })), + PROPERTY_ENTRY_BOOL("input"), + PROPERTY_ENTRY_STRING("line-name", "IRQ0_PB"), + { } + }, +}; + static const struct software_node * const rsk7203_swnodes[] __initconst = { &rsk7203_gpio_leds_node, &rsk7203_green_led_node, @@ -141,6 +190,10 @@ static const struct software_node * const rsk7203_swnodes[] __initconst = { &rsk7203_sw1_key_node, &rsk7203_sw2_key_node, &rsk7203_sw3_key_node, + &rsk7203_pfc_functions_node, + &rsk7203_txd0_hog_node, + &rsk7203_rxd0_hog_node, + &rsk7203_irq0_hog_node, NULL }; @@ -165,25 +218,45 @@ static const struct platform_device_info rsk7203_devices[] __initconst = { }, }; +/* + * The pfc-sh7203 device is registered at arch_initcall level, and the + * sh-pfc driver (registered at postcore_initcall level) probes as soon + * as the device is created. + * + * We need to register our software nodes at postcore_initcall level so + * they are already present in the system when the driver probes and + * tries to apply GPIO hogs. + */ +static int __init rsk7203_sw_nodes_setup(void) +{ + int error; + + error = software_node_register(&pfc_gpiochip_node); + if (error && error != -EEXIST) { + pr_err("RSK7203: failed to register PFC software node: %d\n", + error); + return error; + } + + error = software_node_register_node_group(rsk7203_swnodes); + if (error) { + pr_err("RSK7203: failed to register board software nodes: %d\n", + error); + return error; + } + + return 0; +} +postcore_initcall(rsk7203_sw_nodes_setup); + static int __init rsk7203_devices_setup(void) { struct platform_device *pd; int error; int i; - /* Select pins for SCIF0 */ - gpio_request(GPIO_FN_TXD0, NULL); - gpio_request(GPIO_FN_RXD0, NULL); - /* Setup LAN9118: CS1 in 16-bit Big Endian Mode, IRQ0 at Port B */ __raw_writel(0x36db0400, 0xfffc0008); /* CS1BCR */ - gpio_request(GPIO_FN_IRQ0_PB, NULL); - - error = software_node_register_node_group(rsk7203_swnodes); - if (error) { - pr_err("failed to register software nodes: %d\n", error); - return error; - } for (i = 0; i < ARRAY_SIZE(rsk7203_devices); i++) { pd = platform_device_register_full(&rsk7203_devices[i]); From e9c086239fc1923d6ecca9138e4caf94b716ff4a Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Thu, 9 Jul 2026 09:30:53 +0200 Subject: [PATCH 034/130] dt-bindings: pinctrl: apple,pinctrl: Add t6030 and t6031 compatibles The pin controller on Apple silicon M3 Pro, Max and Ultra SoCs is compatible with the t8103 (M1) one. Add "apple,t6030-pinctrl" for M3 Pro and "apple,t6031-pinctrl" for M3 Max and Ultra as per-SoC compatibles. Signed-off-by: Janne Grunau Acked-by: Conor Dooley Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml index 41073176bc69..f08d2c4f5784 100644 --- a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml @@ -20,6 +20,8 @@ properties: - items: - enum: - apple,t6020-pinctrl + - apple,t6030-pinctrl + - apple,t6031-pinctrl - apple,t8122-pinctrl - const: apple,t8103-pinctrl - items: From 8e8bad1e2ab599174c21dd2d0ba6fcf5f82dafa5 Mon Sep 17 00:00:00 2001 From: Alim Akhtar Date: Sat, 27 Jun 2026 22:42:24 +0530 Subject: [PATCH 035/130] dt-bindings: pinctrl: samsung: Add exynos8855-pinctrl compatible Document pin controller support on Exynos8855 SoC. Signed-off-by: Alim Akhtar Reviewed-by: Peter Griffin Link: https://patch.msgid.link/20260627171228.2687857-3-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml index 7b006009ca0e..c4773701c92e 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml @@ -53,6 +53,7 @@ properties: - samsung,exynos7870-pinctrl - samsung,exynos7885-pinctrl - samsung,exynos850-pinctrl + - samsung,exynos8855-pinctrl - samsung,exynos8890-pinctrl - samsung,exynos8895-pinctrl - samsung,exynos9610-pinctrl From 7cd3475913736239696e0111d4d5845d9e0a79b6 Mon Sep 17 00:00:00 2001 From: Alim Akhtar Date: Sat, 27 Jun 2026 22:42:26 +0530 Subject: [PATCH 036/130] dt-bindings: pinctrl: samsung: Add exynos8855-wakeup-eint compatible Add a dedicated compatible for the exynos8855-wakeup-eint node, which is compatible with Exynos7 implementation. Signed-off-by: Alim Akhtar Reviewed-by: Peter Griffin Link: https://patch.msgid.link/20260627171228.2687857-5-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski --- .../bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml index 2b88f25e80a6..802911e23aff 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml @@ -41,6 +41,7 @@ properties: - samsung,exynos7870-wakeup-eint - samsung,exynos7885-wakeup-eint - samsung,exynos850-wakeup-eint + - samsung,exynos8855-wakeup-eint - samsung,exynos8890-wakeup-eint - samsung,exynos8895-wakeup-eint - const: samsung,exynos7-wakeup-eint From d441836c9d704d0f3db5dbf44df87af2ba7a9d26 Mon Sep 17 00:00:00 2001 From: Alim Akhtar Date: Sat, 27 Jun 2026 22:42:25 +0530 Subject: [PATCH 037/130] pinctrl: samsung: Add Exynos8855 pinctrl configuration Add pinctrl configuration for Exynos8855. The bank type macros are reused from EXYNOS850 and GS101 SoC. Signed-off-by: Alim Akhtar Reviewed-by: Peter Griffin Link: https://patch.msgid.link/20260627171228.2687857-4-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski --- .../pinctrl/samsung/pinctrl-exynos-arm64.c | 132 ++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + 3 files changed, 135 insertions(+) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index fe9f92cb037e..1aa977d2a1f8 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -943,6 +943,138 @@ const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = { .num_ctrl = ARRAY_SIZE(exynos850_pin_ctrl), }; +/* pin banks of exynos8855 pin-controller 0 (ALIVE) */ +static const struct samsung_pin_bank_data exynos8855_pin_banks0[] __initconst = { + GS101_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00, 0x00), + GS101_PIN_BANK_EINTW(4, 0x020, "gpa1", 0x04, 0x08), + EXYNOS850_PIN_BANK_EINTN(3, 0x040, "gpq0"), + EXYNOS850_PIN_BANK_EINTN(2, 0x060, "gpq1"), + GS101_PIN_BANK_EINTW(1, 0x080, "gpc0", 0x08, 0x10), + GS101_PIN_BANK_EINTW(1, 0x0a0, "gpc1", 0x0c, 0x14), + GS101_PIN_BANK_EINTW(1, 0x0c0, "gpc2", 0x10, 0x18), + GS101_PIN_BANK_EINTW(1, 0x0e0, "gpc3", 0x14, 0x1c), + GS101_PIN_BANK_EINTW(1, 0x100, "gpc4", 0x18, 0x20), + GS101_PIN_BANK_EINTW(1, 0x120, "gpc5", 0x1c, 0x24), + GS101_PIN_BANK_EINTW(1, 0x140, "gpc6", 0x20, 0x28), + GS101_PIN_BANK_EINTW(1, 0x160, "gpc7", 0x24, 0x2c), + GS101_PIN_BANK_EINTW(1, 0x180, "gpc8", 0x28, 0x30), + GS101_PIN_BANK_EINTW(1, 0x1a0, "gpc9", 0x2c, 0x34), + GS101_PIN_BANK_EINTW(1, 0x1c0, "gpc10", 0x30, 0x38), + GS101_PIN_BANK_EINTW(1, 0x1e0, "gpc11", 0x34, 0x3c), + GS101_PIN_BANK_EINTW(1, 0x200, "gpc12", 0x38, 0x40), + GS101_PIN_BANK_EINTW(1, 0x220, "gpc13", 0x3c, 0x44), + GS101_PIN_BANK_EINTW(1, 0x240, "gpc14", 0x40, 0x48), + GS101_PIN_BANK_EINTW(1, 0x260, "gpj0", 0x44, 0x4c), + GS101_PIN_BANK_EINTW(1, 0x280, "gpj1", 0x48, 0x50), + GS101_PIN_BANK_EINTW(1, 0x2a0, "gpj2", 0x4c, 0x54), +}; + +/* pin banks of exynos8855 pin-controller 1 (CMGP) */ +static const struct samsung_pin_bank_data exynos8855_pin_banks1[] __initconst = { + GS101_PIN_BANK_EINTW(1, 0x00, "gpm0", 0x00, 0x00), + GS101_PIN_BANK_EINTW(1, 0x20, "gpm1", 0x04, 0x04), + GS101_PIN_BANK_EINTW(1, 0x40, "gpm2", 0x08, 0x08), + GS101_PIN_BANK_EINTW(1, 0x60, "gpm3", 0x0c, 0x0c), + GS101_PIN_BANK_EINTW(1, 0x80, "gpm4", 0x10, 0x10), + GS101_PIN_BANK_EINTW(1, 0xa0, "gpm5", 0x14, 0x14), + GS101_PIN_BANK_EINTW(1, 0xc0, "gpm6", 0x18, 0x18), + GS101_PIN_BANK_EINTW(1, 0xe0, "gpm7", 0x1c, 0x1c), + GS101_PIN_BANK_EINTW(1, 0x100, "gpm8", 0x20, 0x20), + GS101_PIN_BANK_EINTW(1, 0x120, "gpm9", 0x24, 0x24), + GS101_PIN_BANK_EINTW(1, 0x140, "gpm10", 0x28, 0x28), + GS101_PIN_BANK_EINTW(1, 0x160, "gpm11", 0x2c, 0x2c), + GS101_PIN_BANK_EINTW(1, 0x180, "gpm12", 0x30, 0x30), + GS101_PIN_BANK_EINTW(1, 0x1a0, "gpm13", 0x34, 0x34), + GS101_PIN_BANK_EINTW(1, 0x1c0, "gpm14", 0x38, 0x38), + GS101_PIN_BANK_EINTW(1, 0x1e0, "gpm15", 0x3c, 0x3c), + GS101_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x40, 0x40), + GS101_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x44, 0x44), + GS101_PIN_BANK_EINTW(1, 0x240, "gpm18", 0x48, 0x48), + GS101_PIN_BANK_EINTW(1, 0x260, "gpm19", 0x4c, 0x4c), + GS101_PIN_BANK_EINTW(1, 0x280, "gpm20", 0x50, 0x50), + GS101_PIN_BANK_EINTW(1, 0x2a0, "gpm21", 0x54, 0x54), +}; + +/* pin banks of exynos8855 pin-controller 2 (HSI UFS) */ +static const struct samsung_pin_bank_data exynos8855_pin_banks2[] __initconst = { + GS101_PIN_BANK_EINTG(2, 0x0, "gpf3", 0x00, 0x00), +}; + +/* pin banks of exynos8855 pin-controller 3 (PERIC) */ +static const struct samsung_pin_bank_data exynos8855_pin_banks3[] __initconst = { + GS101_PIN_BANK_EINTG(8, 0x0, "gpp0", 0x00, 0x00), + GS101_PIN_BANK_EINTG(8, 0x20, "gpp1", 0x04, 0x08), + GS101_PIN_BANK_EINTG(6, 0x40, "gpp2", 0x08, 0x10), + GS101_PIN_BANK_EINTG(4, 0x60, "gpg0", 0x0c, 0x18), + GS101_PIN_BANK_EINTG(3, 0x80, "gpg1", 0x10, 0x1c), + GS101_PIN_BANK_EINTG(6, 0xa0, "gpb0", 0x14, 0x20), + GS101_PIN_BANK_EINTG(4, 0xc0, "gpb1", 0x18, 0x28), +}; + +/* pin banks of exynos8855 pin-controller 4 (PERICMMC) */ +static const struct samsung_pin_bank_data exynos8855_pin_banks4[] __initconst = { + GS101_PIN_BANK_EINTG(7, 0x0, "gpf2", 0x00, 0x00), +}; + +/* pin banks of exynos8855 pin-controller 5 (USI) */ +static const struct samsung_pin_bank_data exynos8855_pin_banks5[] __initconst = { + GS101_PIN_BANK_EINTG(8, 0x00, "gpp3", 0x00, 0x00), + GS101_PIN_BANK_EINTG(2, 0x20, "gpp4", 0x04, 0x08), + GS101_PIN_BANK_EINTG(2, 0x40, "gpg2", 0x08, 0x0c), + GS101_PIN_BANK_EINTG(1, 0x60, "gpg3", 0x0c, 0x10), +}; + +static const struct samsung_pin_ctrl exynos8855_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 ALIVE data */ + .pin_banks = exynos8855_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos8855_pin_banks0), + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = gs101_pinctrl_suspend, + .resume = gs101_pinctrl_resume, + }, { + /* pin-controller instance 1 CMGP data */ + .pin_banks = exynos8855_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos8855_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = gs101_pinctrl_suspend, + .resume = gs101_pinctrl_resume, + }, { + /* pin-controller instance 2 HSI UFS data */ + .pin_banks = exynos8855_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos8855_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = gs101_pinctrl_suspend, + .resume = gs101_pinctrl_resume, + }, { + /* pin-controller instance 3 PERIC data */ + .pin_banks = exynos8855_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos8855_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = gs101_pinctrl_suspend, + .resume = gs101_pinctrl_resume, + }, { + /* pin-controller instance 4 PERICMMC data */ + .pin_banks = exynos8855_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos8855_pin_banks4), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = gs101_pinctrl_suspend, + .resume = gs101_pinctrl_resume, + }, { + /* pin-controller instance 5 USI data */ + .pin_banks = exynos8855_pin_banks5, + .nr_banks = ARRAY_SIZE(exynos8855_pin_banks5), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = gs101_pinctrl_suspend, + .resume = gs101_pinctrl_resume, + }, +}; + +const struct samsung_pinctrl_of_match_data exynos8855_of_data __initconst = { + .ctrl = exynos8855_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos8855_pin_ctrl), +}; + /* pin banks of exynos990 pin-controller 0 (ALIVE) */ static struct samsung_pin_bank_data exynos990_pin_banks0[] = { /* Must start with EINTG banks, ordered by EINT group number. */ diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 5ac6f6b02327..5ecc9ed4c44d 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1500,6 +1500,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = &exynos7885_of_data }, { .compatible = "samsung,exynos850-pinctrl", .data = &exynos850_of_data }, + { .compatible = "samsung,exynos8855-pinctrl", + .data = &exynos8855_of_data }, { .compatible = "samsung,exynos8890-pinctrl", .data = &exynos8890_of_data }, { .compatible = "samsung,exynos8895-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index 937600430a6e..bb02fb49b2af 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -396,6 +396,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7_of_data; extern const struct samsung_pinctrl_of_match_data exynos7870_of_data; extern const struct samsung_pinctrl_of_match_data exynos7885_of_data; extern const struct samsung_pinctrl_of_match_data exynos850_of_data; +extern const struct samsung_pinctrl_of_match_data exynos8855_of_data; extern const struct samsung_pinctrl_of_match_data exynos8890_of_data; extern const struct samsung_pinctrl_of_match_data exynos8895_of_data; extern const struct samsung_pinctrl_of_match_data exynos9610_of_data; From f81bcaae1edde95c684436310edad8cf849f1f1f Mon Sep 17 00:00:00 2001 From: Ravi Hothi Date: Wed, 15 Jul 2026 18:51:49 +0530 Subject: [PATCH 038/130] dt-bindings: pinctrl: qcom,milos-lpass-lpi-pinctrl: Add Eliza pinctrl Document compatible for Qualcomm Eliza SoC LPASS LPI pin controller. Eliza has the same pin mux functions as Milos but uses a different slew rate register layout where the slew rate field is in the same GPIO config register rather than a separate dedicated register. As a result, Eliza only has a single reg entry instead of two. Signed-off-by: Ravi Hothi Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260715132150.1322663-2-ravi.hothi@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski --- .../pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml index 73e84f188591..86c1da0f577c 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml @@ -15,9 +15,12 @@ description: properties: compatible: - const: qcom,milos-lpass-lpi-pinctrl + enum: + - qcom,eliza-lpass-lpi-pinctrl + - qcom,milos-lpass-lpi-pinctrl reg: + minItems: 1 items: - description: LPASS LPI TLMM Control and Status registers - description: LPASS LPI MCC registers @@ -74,6 +77,19 @@ $defs: allOf: - $ref: qcom,lpass-lpi-common.yaml# + - if: + properties: + compatible: + const: qcom,eliza-lpass-lpi-pinctrl + then: + properties: + reg: + maxItems: 1 + else: + properties: + reg: + minItems: 2 + required: - compatible - reg From 82c3edf8701154e2768973ebd4c0d2f3bd29621e Mon Sep 17 00:00:00 2001 From: Ravi Hothi Date: Wed, 15 Jul 2026 18:51:50 +0530 Subject: [PATCH 039/130] pinctrl: qcom: milos-lpass-lpi: Add Eliza LPASS LPI TLMM Eliza SoC has the same LPASS LPI pin mux functions as Milos but the slew rate control is in the same GPIO config register rather than a separate register. Add a new variant data struct with updated slew offsets and LPI_FLAG_SLEW_RATE_SAME_REG flag, reusing the existing pin descriptors and function table from Milos. Signed-off-by: Ravi Hothi Reviewed-by: Konrad Dybcio Link: https://patch.msgid.link/20260715132150.1322663-3-ravi.hothi@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski --- .../pinctrl/qcom/pinctrl-milos-lpass-lpi.c | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c index 72b8ffd97860..cb4934cd6f75 100644 --- a/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c @@ -148,6 +148,33 @@ static const struct lpi_pingroup milos_groups[] = { LPI_PINGROUP(22, LPI_NO_SLEW, i2s3_data, dmic4_data, ext_mclk1_e, _), }; +static const struct lpi_pingroup eliza_groups[] = { + LPI_PINGROUP(0, 11, swr_tx_clk, i2s0_clk, _, _), + LPI_PINGROUP(1, 11, swr_tx_data, i2s0_ws, _, _), + LPI_PINGROUP(2, 11, swr_tx_data, i2s0_data, _, _), + LPI_PINGROUP(3, 11, swr_rx_clk, i2s0_data, _, _), + LPI_PINGROUP(4, 11, swr_rx_data, i2s0_data, _, _), + LPI_PINGROUP(5, 11, swr_rx_data, ext_mclk1_c, i2s0_data, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, ext_mclk1_b, _), + LPI_PINGROUP(10, 11, wsa_swr_clk, i2s2_clk, _, _), + LPI_PINGROUP(11, 11, wsa_swr_data, i2s2_ws, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s2_data, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s2_data, ext_mclk1_a, _), + LPI_PINGROUP(14, 11, swr_tx_data, ext_mclk1_d, _, _), + /* gpio15 - gpio18 do not really exist */ + LPI_PINGROUP(15, 11, _, _, _, _), + LPI_PINGROUP(16, 11, _, _, _, _), + LPI_PINGROUP(17, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(18, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(19, LPI_NO_SLEW, i2s3_clk, slimbus_clk, qca_swr_clk, _), + LPI_PINGROUP(20, LPI_NO_SLEW, i2s3_ws, slimbus_data, qca_swr_data, _), + LPI_PINGROUP(21, LPI_NO_SLEW, i2s3_data, dmic4_clk, _, _), + LPI_PINGROUP(22, LPI_NO_SLEW, i2s3_data, dmic4_data, ext_mclk1_e, _), +}; + static const struct lpi_function milos_functions[] = { LPI_FUNCTION(gpio), LPI_FUNCTION(dmic1_clk), @@ -196,8 +223,21 @@ static const struct lpi_pinctrl_variant_data milos_lpi_data = { .nfunctions = ARRAY_SIZE(milos_functions), }; +static const struct lpi_pinctrl_variant_data eliza_lpi_data = { + .pins = milos_lpi_pins, + .npins = ARRAY_SIZE(milos_lpi_pins), + .groups = eliza_groups, + .ngroups = ARRAY_SIZE(eliza_groups), + .functions = milos_functions, + .nfunctions = ARRAY_SIZE(milos_functions), + .flags = LPI_FLAG_SLEW_RATE_SAME_REG, +}; + static const struct of_device_id lpi_pinctrl_of_match[] = { { + .compatible = "qcom,eliza-lpass-lpi-pinctrl", + .data = &eliza_lpi_data, + }, { .compatible = "qcom,milos-lpass-lpi-pinctrl", .data = &milos_lpi_data, }, From 699fd26ba39c6659b9f5ebbdee9293b9b6936283 Mon Sep 17 00:00:00 2001 From: Pan Chuang Date: Fri, 17 Jul 2026 18:58:45 +0800 Subject: [PATCH 040/130] pinctrl: intel: Remove redundant dev_err_probe() Since commit 55b48e23f5c4 ("genirq/devres: Add error handling in devm_request_*_irq()"), devm_request_irq() automatically logs detailed error messages on failure. Remove the now-redundant driver-specific dev_err_probe() calls. Signed-off-by: Pan Chuang Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-intel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 2e2526e01d58..261ec2ee63ef 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1414,7 +1414,7 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) IRQF_SHARED | IRQF_NO_THREAD, dev_name(pctrl->dev), pctrl); if (ret) - return dev_err_probe(pctrl->dev, ret, "failed to request interrupt\n"); + return ret; /* Setup IRQ chip */ girq = &pctrl->chip.irq; From ba6bf288b44424214ccec19f0f2d6421847b2921 Mon Sep 17 00:00:00 2001 From: Nikolai Burov Date: Mon, 13 Jul 2026 18:06:21 +0300 Subject: [PATCH 041/130] dt-bindings: pinctrl: mediatek: Add MT6858 Add new DT bindings for the pin controller found in the MT6858 (MediaTek Dimensity 7100) SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Nikolai Burov Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Linus Walleij --- .../pinctrl/mediatek,mt6858-pinctrl.yaml | 190 ++++++++++++++++++ 1 file changed, 190 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt6858-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6858-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6858-pinctrl.yaml new file mode 100644 index 000000000000..9b834e87afde --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6858-pinctrl.yaml @@ -0,0 +1,190 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6858-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6858 Pin Controller + +maintainers: + - Nikolai Burov + +description: + The MediaTek's MT6858 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt6858-pinctrl + + reg: + items: + - description: gpio base + - description: lm group IO + - description: rb group IO + - description: bm2 group IO + - description: bm group IO + - description: bm1 group IO + - description: lt group IO + - description: lt1 group IO + - description: rt group IO + - description: rt1 group IO + - description: eint south group IO + - description: eint west group IO + - description: eint east group IO + - description: eint center group IO + + reg-names: + items: + - const: base + - const: lm + - const: rb + - const: bm2 + - const: bm + - const: bm1 + - const: lt + - const: lt1 + - const: rt + - const: rt1 + - const: eint0 + - const: eint1 + - const: eint2 + - const: eint3 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-line-names: true + +# PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^pins': + type: object + $ref: /schemas/pinctrl/pincfg-node.yaml + additionalProperties: false + description: + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + + properties: + pinmux: + description: + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in arch/arm64/boot/dts/mediatek/mt6858-pinfunc.h + for this SoC. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + bias-pull-down: + oneOf: + - type: boolean + description: normal pull down. + - enum: [100, 101, 102, 103] + description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0_ + defines in dt-bindings/pinctrl/mt65xx.h. + - enum: [200, 201, 202, 203] + description: RSEL pull down type. See MTK_PULL_SET_RSEL_ defines + in dt-bindings/pinctrl/mt65xx.h. + + bias-pull-up: + oneOf: + - type: boolean + description: normal pull up. + - enum: [100, 101, 102, 103] + description: PUPD/R1/R0 pull up type. See MTK_PUPD_SET_R1R0_ + defines in dt-bindings/pinctrl/mt65xx.h. + - enum: [200, 201, 202, 203] + description: RSEL pull up type. See MTK_PULL_SET_RSEL_ defines + in dt-bindings/pinctrl/mt65xx.h. + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + #include + #define PINMUX_GPIO149__FUNC_SCL5 (MTK_PIN_NO(149) | 1) + #define PINMUX_GPIO150__FUNC_SDA5 (MTK_PIN_NO(150) | 1) + + pio: pinctrl@10005000 { + compatible = "mediatek,mt6858-pinctrl"; + reg = <0x10005000 0x1000>, + <0x11b20000 0x1000>, + <0x11c10000 0x1000>, + <0x11d10000 0x1000>, + <0x11d30000 0x1000>, + <0x11d40000 0x1000>, + <0x11e20000 0x1000>, + <0x11e30000 0x1000>, + <0x11ed0000 0x1000>, + <0x11ee0000 0x1000>, + <0x11b00000 0x1000>, + <0x11e60000 0x1000>, + <0x11e80000 0x1000>, + <0x1c01e000 0x1000>; + reg-names = "base", "lm", "rb", "bm2", "bm", "bm1", "lt", "lt1", + "rt", "rt1", "eint0", "eint1", "eint2", "eint3"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 197>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + + i2c5-pins { + pins { + pinmux = , + ; + bias-disable; + }; + }; + }; From 449816f1975c43b12b017fa68d732b3fe2f30ee5 Mon Sep 17 00:00:00 2001 From: Nikolai Burov Date: Mon, 13 Jul 2026 18:06:22 +0300 Subject: [PATCH 042/130] pinctrl: mediatek: Add driver for MT6858 Add a pinctrl driver for the MT6858 (MediaTek Dimensity 7100) SoC. Signed-off-by: Nikolai Burov Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/Kconfig | 10 + drivers/pinctrl/mediatek/Makefile | 1 + drivers/pinctrl/mediatek/pinctrl-mt6858.c | 1407 ++++++++++ drivers/pinctrl/mediatek/pinctrl-mtk-mt6858.h | 2378 +++++++++++++++++ 4 files changed, 3796 insertions(+) create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt6858.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt6858.h diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 97980cc28b9c..95c5250150d7 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -166,6 +166,16 @@ config PINCTRL_MT6797 default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_PARIS +config PINCTRL_MT6858 + bool "MediaTek MT6858 pin control" + depends on OF + depends on ARM64 || COMPILE_TEST + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK_PARIS + help + Say yes here to support pin controller and gpio driver + on the MediaTek MT6858 SoC. + config PINCTRL_MT6878 bool "MediaTek MT6878 pin control" depends on OF diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index 6dc17b0c23f9..6ee3833dc6e2 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o obj-$(CONFIG_PINCTRL_MT6779) += pinctrl-mt6779.o obj-$(CONFIG_PINCTRL_MT6795) += pinctrl-mt6795.o obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o +obj-$(CONFIG_PINCTRL_MT6858) += pinctrl-mt6858.o obj-$(CONFIG_PINCTRL_MT6878) += pinctrl-mt6878.o obj-$(CONFIG_PINCTRL_MT6893) += pinctrl-mt6893.o obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6858.c b/drivers/pinctrl/mediatek/pinctrl-mt6858.c new file mode 100644 index 000000000000..07f72d9d531f --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt6858.c @@ -0,0 +1,1407 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025 MediaTek Inc. + * Alice Chao + * Copyright (c) 2026 Jolla Mobile Ltd + * Nikolai Burov + */ + +#include +#include "pinctrl-mtk-mt6858.h" +#include "pinctrl-paris.h" + +/* MT6858 have multiple bases to program pin configuration listed as the below: + * GPIO_BASE: 0x10005000 + * IOCFG_LM_BASE: 0x11B20000 + * IOCFG_RB_BASE: 0x11C10000 + * IOCFG_BM2_BASE: 0x11D10000 + * IOCFG_BM_BASE: 0x11D30000 + * IOCFG_BM1_BASE: 0x11D40000 + * IOCFG_LT_BASE: 0x11E20000 + * IOCFG_LT1_BASE: 0x11E30000 + * IOCFG_RT_BASE: 0x11ED0000 + * IOCFG_RT1_BASE: 0x11EE0000 + * _i_based could be used to indicate what base the pin should be mapped into. + */ + +#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \ + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \ + 32, 0) + +static const struct mtk_pin_field_calc mt6858_pin_mode_range[] = { + /* Pin mode field is 5 bits with 8 bit stride */ + PIN_FIELD(0, 196, 0x0300, 0x10, 0, 8), +}; + +static const struct mtk_pin_field_calc mt6858_pin_dir_range[] = { + PIN_FIELD(0, 196, 0x0000, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6858_pin_di_range[] = { + PIN_FIELD(0, 196, 0x0200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6858_pin_do_range[] = { + PIN_FIELD(0, 196, 0x0100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6858_pin_ies_range[] = { + PIN_FIELD_BASE(0, 0, 8, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(1, 1, 8, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(2, 2, 8, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(3, 3, 8, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(4, 4, 8, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(5, 5, 8, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(6, 6, 8, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(7, 7, 8, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(8, 8, 5, 0x0060, 0x10, 15, 1), + PIN_FIELD_BASE(9, 9, 5, 0x0060, 0x10, 16, 1), + PIN_FIELD_BASE(10, 10, 5, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(11, 11, 5, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(12, 12, 5, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(13, 13, 7, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, 7, 0x0030, 0x10, 1, 1), + PIN_FIELD_BASE(15, 15, 7, 0x0030, 0x10, 2, 1), + PIN_FIELD_BASE(16, 16, 7, 0x0030, 0x10, 3, 1), + PIN_FIELD_BASE(17, 17, 7, 0x0030, 0x10, 4, 1), + PIN_FIELD_BASE(18, 18, 6, 0x0020, 0x10, 0, 1), + PIN_FIELD_BASE(19, 19, 6, 0x0020, 0x10, 1, 1), + PIN_FIELD_BASE(20, 20, 6, 0x0020, 0x10, 2, 1), + PIN_FIELD_BASE(21, 21, 5, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(22, 22, 5, 0x0060, 0x10, 13, 1), + PIN_FIELD_BASE(23, 23, 8, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(24, 24, 5, 0x0060, 0x10, 14, 1), + PIN_FIELD_BASE(25, 25, 2, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(26, 26, 3, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(27, 27, 2, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(28, 28, 2, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(29, 29, 2, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(30, 30, 2, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(31, 31, 2, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(32, 32, 2, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(33, 33, 2, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(34, 34, 2, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(35, 35, 4, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(36, 36, 8, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(37, 37, 8, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, 8, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(39, 39, 8, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(40, 40, 1, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(41, 41, 1, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(42, 42, 1, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(43, 43, 1, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(44, 44, 1, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(45, 45, 5, 0x0060, 0x10, 17, 1), + PIN_FIELD_BASE(46, 46, 5, 0x0060, 0x10, 19, 1), + PIN_FIELD_BASE(47, 47, 5, 0x0060, 0x10, 20, 1), + PIN_FIELD_BASE(48, 48, 5, 0x0060, 0x10, 18, 1), + PIN_FIELD_BASE(49, 49, 4, 0x0050, 0x10, 26, 1), + PIN_FIELD_BASE(50, 50, 4, 0x0050, 0x10, 25, 1), + PIN_FIELD_BASE(51, 51, 1, 0x0050, 0x10, 28, 1), + PIN_FIELD_BASE(52, 52, 1, 0x0050, 0x10, 27, 1), + PIN_FIELD_BASE(53, 53, 5, 0x0060, 0x10, 25, 1), + PIN_FIELD_BASE(54, 54, 5, 0x0060, 0x10, 21, 1), + PIN_FIELD_BASE(55, 55, 5, 0x0060, 0x10, 24, 1), + PIN_FIELD_BASE(56, 56, 5, 0x0060, 0x10, 22, 1), + PIN_FIELD_BASE(57, 57, 5, 0x0060, 0x10, 23, 1), + PIN_FIELD_BASE(58, 58, 3, 0x0060, 0x10, 21, 1), + PIN_FIELD_BASE(59, 59, 3, 0x0060, 0x10, 22, 1), + PIN_FIELD_BASE(60, 60, 3, 0x0060, 0x10, 24, 1), + PIN_FIELD_BASE(61, 61, 3, 0x0060, 0x10, 23, 1), + PIN_FIELD_BASE(62, 62, 8, 0x0060, 0x10, 25, 1), + PIN_FIELD_BASE(63, 63, 8, 0x0060, 0x10, 26, 1), + PIN_FIELD_BASE(64, 64, 8, 0x0060, 0x10, 28, 1), + PIN_FIELD_BASE(65, 65, 8, 0x0060, 0x10, 27, 1), + PIN_FIELD_BASE(66, 66, 1, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(67, 67, 1, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(68, 68, 1, 0x0050, 0x10, 20, 1), + PIN_FIELD_BASE(69, 69, 1, 0x0050, 0x10, 19, 1), + PIN_FIELD_BASE(70, 70, 1, 0x0050, 0x10, 21, 1), + PIN_FIELD_BASE(71, 71, 1, 0x0050, 0x10, 22, 1), + PIN_FIELD_BASE(72, 72, 1, 0x0050, 0x10, 24, 1), + PIN_FIELD_BASE(73, 73, 1, 0x0050, 0x10, 23, 1), + PIN_FIELD_BASE(74, 74, 1, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(75, 75, 1, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(76, 76, 1, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(77, 77, 1, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(78, 78, 3, 0x0060, 0x10, 25, 1), + PIN_FIELD_BASE(79, 79, 3, 0x0060, 0x10, 26, 1), + PIN_FIELD_BASE(80, 80, 3, 0x0060, 0x10, 28, 1), + PIN_FIELD_BASE(81, 81, 3, 0x0060, 0x10, 27, 1), + PIN_FIELD_BASE(82, 82, 8, 0x0060, 0x10, 13, 1), + PIN_FIELD_BASE(83, 83, 8, 0x0060, 0x10, 14, 1), + PIN_FIELD_BASE(84, 84, 8, 0x0060, 0x10, 15, 1), + PIN_FIELD_BASE(85, 85, 8, 0x0060, 0x10, 16, 1), + PIN_FIELD_BASE(86, 86, 8, 0x0060, 0x10, 17, 1), + PIN_FIELD_BASE(87, 87, 8, 0x0060, 0x10, 18, 1), + PIN_FIELD_BASE(88, 88, 4, 0x0050, 0x10, 19, 1), + PIN_FIELD_BASE(89, 89, 4, 0x0050, 0x10, 21, 1), + PIN_FIELD_BASE(90, 90, 4, 0x0050, 0x10, 20, 1), + PIN_FIELD_BASE(91, 91, 4, 0x0050, 0x10, 22, 1), + PIN_FIELD_BASE(92, 92, 4, 0x0050, 0x10, 24, 1), + PIN_FIELD_BASE(93, 93, 4, 0x0050, 0x10, 23, 1), + PIN_FIELD_BASE(94, 94, 4, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(95, 95, 4, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(96, 96, 4, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(97, 97, 4, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(98, 98, 5, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(99, 99, 9, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(100, 100, 9, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(101, 101, 9, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(102, 102, 9, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(103, 103, 9, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(104, 104, 9, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(105, 105, 9, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(106, 106, 5, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(107, 107, 4, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(108, 108, 4, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(109, 109, 5, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(110, 110, 5, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(111, 111, 5, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(112, 112, 5, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(113, 113, 4, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(114, 114, 4, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(115, 115, 5, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, 4, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(117, 117, 4, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(118, 118, 3, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(119, 119, 3, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(120, 120, 3, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(121, 121, 3, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(122, 122, 7, 0x0030, 0x10, 7, 1), + PIN_FIELD_BASE(123, 123, 3, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(124, 124, 1, 0x0050, 0x10, 26, 1), + PIN_FIELD_BASE(125, 125, 7, 0x0030, 0x10, 8, 1), + PIN_FIELD_BASE(126, 126, 2, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(127, 127, 2, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(128, 128, 2, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(129, 129, 2, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(130, 130, 3, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(131, 131, 3, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(132, 132, 3, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(133, 133, 3, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(134, 134, 3, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(135, 135, 8, 0x0060, 0x10, 19, 1), + PIN_FIELD_BASE(136, 136, 8, 0x0060, 0x10, 20, 1), + PIN_FIELD_BASE(137, 137, 7, 0x0030, 0x10, 5, 1), + PIN_FIELD_BASE(138, 138, 7, 0x0030, 0x10, 6, 1), + PIN_FIELD_BASE(139, 139, 3, 0x0060, 0x10, 13, 1), + PIN_FIELD_BASE(140, 140, 3, 0x0060, 0x10, 17, 1), + PIN_FIELD_BASE(141, 141, 3, 0x0060, 0x10, 14, 1), + PIN_FIELD_BASE(142, 142, 3, 0x0060, 0x10, 18, 1), + PIN_FIELD_BASE(143, 143, 3, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(144, 144, 3, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(145, 145, 3, 0x0060, 0x10, 15, 1), + PIN_FIELD_BASE(146, 146, 3, 0x0060, 0x10, 19, 1), + PIN_FIELD_BASE(147, 147, 2, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(148, 148, 2, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(149, 149, 5, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(150, 150, 5, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(151, 151, 3, 0x0060, 0x10, 16, 1), + PIN_FIELD_BASE(152, 152, 3, 0x0060, 0x10, 20, 1), + PIN_FIELD_BASE(153, 153, 2, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(154, 154, 2, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(155, 155, 2, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(156, 156, 2, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(157, 157, 8, 0x0060, 0x10, 21, 1), + PIN_FIELD_BASE(158, 158, 8, 0x0060, 0x10, 23, 1), + PIN_FIELD_BASE(159, 159, 8, 0x0060, 0x10, 22, 1), + PIN_FIELD_BASE(160, 160, 8, 0x0060, 0x10, 24, 1), + PIN_FIELD_BASE(161, 161, 5, 0x0060, 0x10, 26, 1), + PIN_FIELD_BASE(162, 162, 5, 0x0060, 0x10, 28, 1), + PIN_FIELD_BASE(163, 163, 5, 0x0060, 0x10, 27, 1), + PIN_FIELD_BASE(164, 164, 5, 0x0060, 0x10, 29, 1), + PIN_FIELD_BASE(165, 165, 4, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(166, 166, 4, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(167, 167, 4, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(168, 168, 4, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(169, 169, 4, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(170, 170, 4, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(171, 171, 4, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(172, 172, 4, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(173, 173, 1, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(174, 174, 1, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(175, 175, 1, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(176, 176, 1, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(177, 177, 1, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(178, 178, 1, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(179, 179, 1, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(180, 180, 1, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(181, 181, 1, 0x0050, 0x10, 25, 1), + PIN_FIELD_BASE(182, 182, 9, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(183, 183, 9, 0x0040, 0x10, 13, 1), + PIN_FIELD_BASE(184, 184, 9, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(185, 185, 9, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(186, 186, 9, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(187, 187, 9, 0x0040, 0x10, 15, 1), + PIN_FIELD_BASE(188, 188, 9, 0x0040, 0x10, 16, 1), + PIN_FIELD_BASE(189, 189, 9, 0x0040, 0x10, 17, 1), + PIN_FIELD_BASE(190, 190, 9, 0x0040, 0x10, 18, 1), + PIN_FIELD_BASE(191, 191, 9, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(192, 192, 9, 0x0040, 0x10, 14, 1), + PIN_FIELD_BASE(193, 193, 9, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(194, 194, 9, 0x0040, 0x10, 19, 1), + PIN_FIELD_BASE(195, 195, 9, 0x0040, 0x10, 20, 1), + PIN_FIELD_BASE(196, 196, 6, 0x0020, 0x10, 3, 1), +}; + +static const struct mtk_pin_field_calc mt6858_pin_smt_range[] = { + PIN_FIELD_BASE(0, 0, 8, 0x0110, 0x10, 4, 1), + PIN_FIELD_BASE(1, 1, 8, 0x0110, 0x10, 5, 1), + PIN_FIELD_BASE(2, 2, 8, 0x0110, 0x10, 6, 1), + PIN_FIELD_BASE(3, 3, 8, 0x0110, 0x10, 8, 1), + PIN_FIELD_BASE(4, 4, 8, 0x0110, 0x10, 9, 1), + PIN_FIELD_BASE(5, 5, 8, 0x0110, 0x10, 10, 1), + PIN_FIELD_BASE(6, 6, 8, 0x0110, 0x10, 11, 1), + PIN_FIELD_BASE(7, 7, 8, 0x0110, 0x10, 12, 1), + PIN_FIELD_BASE(8, 8, 5, 0x00e0, 0x10, 15, 1), + PIN_FIELD_BASE(9, 9, 5, 0x00e0, 0x10, 16, 1), + PIN_FIELD_BASE(10, 10, 5, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(11, 11, 5, 0x00e0, 0x10, 10, 1), + PIN_FIELD_BASE(12, 12, 5, 0x00e0, 0x10, 11, 1), + PIN_FIELD_BASE(13, 13, 7, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, 7, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(15, 15, 7, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(16, 16, 7, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(17, 17, 7, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(18, 18, 6, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(19, 19, 6, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(20, 20, 6, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(21, 21, 5, 0x00e0, 0x10, 12, 1), + PIN_FIELD_BASE(22, 22, 5, 0x00e0, 0x10, 13, 1), + PIN_FIELD_BASE(23, 23, 8, 0x0110, 0x10, 7, 1), + PIN_FIELD_BASE(24, 24, 5, 0x00e0, 0x10, 14, 1), + PIN_FIELD_BASE(25, 25, 2, 0x00c0, 0x10, 14, 1), + PIN_FIELD_BASE(26, 26, 3, 0x00f0, 0x10, 1, 1), + PIN_FIELD_BASE(27, 27, 2, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(28, 28, 2, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(29, 29, 2, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(30, 30, 2, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(31, 31, 2, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(32, 32, 2, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(33, 33, 2, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(34, 34, 2, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(35, 35, 4, 0x0100, 0x10, 4, 1), + PIN_FIELD_BASE(36, 36, 8, 0x0110, 0x10, 0, 1), + PIN_FIELD_BASE(37, 37, 8, 0x0110, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, 8, 0x0110, 0x10, 2, 1), + PIN_FIELD_BASE(39, 39, 8, 0x0110, 0x10, 3, 1), + PIN_FIELD_BASE(40, 40, 1, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(41, 41, 1, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(42, 42, 1, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(43, 43, 1, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(44, 44, 1, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(45, 45, 5, 0x00e0, 0x10, 17, 1), + PIN_FIELD_BASE(46, 46, 5, 0x00e0, 0x10, 17, 1), + PIN_FIELD_BASE(47, 47, 5, 0x00e0, 0x10, 17, 1), + PIN_FIELD_BASE(48, 48, 5, 0x00e0, 0x10, 17, 1), + PIN_FIELD_BASE(49, 49, 4, 0x0100, 0x10, 18, 1), + PIN_FIELD_BASE(50, 50, 4, 0x0100, 0x10, 17, 1), + PIN_FIELD_BASE(51, 51, 1, 0x00b0, 0x10, 18, 1), + PIN_FIELD_BASE(52, 52, 1, 0x00b0, 0x10, 17, 1), + PIN_FIELD_BASE(53, 53, 5, 0x00e0, 0x10, 22, 1), + PIN_FIELD_BASE(54, 54, 5, 0x00e0, 0x10, 18, 1), + PIN_FIELD_BASE(55, 55, 5, 0x00e0, 0x10, 21, 1), + PIN_FIELD_BASE(56, 56, 5, 0x00e0, 0x10, 19, 1), + PIN_FIELD_BASE(57, 57, 5, 0x00e0, 0x10, 20, 1), + PIN_FIELD_BASE(58, 58, 3, 0x00f0, 0x10, 21, 1), + PIN_FIELD_BASE(59, 59, 3, 0x00f0, 0x10, 22, 1), + PIN_FIELD_BASE(60, 60, 3, 0x00f0, 0x10, 24, 1), + PIN_FIELD_BASE(61, 61, 3, 0x00f0, 0x10, 23, 1), + PIN_FIELD_BASE(62, 62, 8, 0x0110, 0x10, 25, 1), + PIN_FIELD_BASE(63, 63, 8, 0x0110, 0x10, 26, 1), + PIN_FIELD_BASE(64, 64, 8, 0x0110, 0x10, 28, 1), + PIN_FIELD_BASE(65, 65, 8, 0x0110, 0x10, 27, 1), + PIN_FIELD_BASE(66, 66, 1, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(67, 67, 1, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(68, 68, 1, 0x00b0, 0x10, 10, 1), + PIN_FIELD_BASE(69, 69, 1, 0x00b0, 0x10, 9, 1), + PIN_FIELD_BASE(70, 70, 1, 0x00b0, 0x10, 11, 1), + PIN_FIELD_BASE(71, 71, 1, 0x00b0, 0x10, 12, 1), + PIN_FIELD_BASE(72, 72, 1, 0x00b0, 0x10, 14, 1), + PIN_FIELD_BASE(73, 73, 1, 0x00b0, 0x10, 13, 1), + PIN_FIELD_BASE(74, 74, 1, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(75, 75, 1, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(76, 76, 1, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(77, 77, 1, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(78, 78, 3, 0x00f0, 0x10, 25, 1), + PIN_FIELD_BASE(79, 79, 3, 0x00f0, 0x10, 26, 1), + PIN_FIELD_BASE(80, 80, 3, 0x00f0, 0x10, 28, 1), + PIN_FIELD_BASE(81, 81, 3, 0x00f0, 0x10, 27, 1), + PIN_FIELD_BASE(82, 82, 8, 0x0110, 0x10, 13, 1), + PIN_FIELD_BASE(83, 83, 8, 0x0110, 0x10, 14, 1), + PIN_FIELD_BASE(84, 84, 8, 0x0110, 0x10, 15, 1), + PIN_FIELD_BASE(85, 85, 8, 0x0110, 0x10, 16, 1), + PIN_FIELD_BASE(86, 86, 8, 0x0110, 0x10, 17, 1), + PIN_FIELD_BASE(87, 87, 8, 0x0110, 0x10, 18, 1), + PIN_FIELD_BASE(88, 88, 4, 0x0100, 0x10, 15, 1), + PIN_FIELD_BASE(89, 89, 4, 0x0100, 0x10, 15, 1), + PIN_FIELD_BASE(90, 90, 4, 0x0100, 0x10, 15, 1), + PIN_FIELD_BASE(91, 91, 4, 0x0100, 0x10, 16, 1), + PIN_FIELD_BASE(92, 92, 4, 0x0100, 0x10, 16, 1), + PIN_FIELD_BASE(93, 93, 4, 0x0100, 0x10, 16, 1), + PIN_FIELD_BASE(94, 94, 4, 0x0100, 0x10, 7, 1), + PIN_FIELD_BASE(95, 95, 4, 0x0100, 0x10, 8, 1), + PIN_FIELD_BASE(96, 96, 4, 0x0100, 0x10, 6, 1), + PIN_FIELD_BASE(97, 97, 4, 0x0100, 0x10, 9, 1), + PIN_FIELD_BASE(98, 98, 5, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(99, 99, 9, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(100, 100, 9, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(101, 101, 9, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(102, 102, 9, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(103, 103, 9, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(104, 104, 9, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(105, 105, 9, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(106, 106, 5, 0x00e0, 0x10, 0, 1), + PIN_FIELD_BASE(107, 107, 4, 0x0100, 0x10, 0, 1), + PIN_FIELD_BASE(108, 108, 4, 0x0100, 0x10, 1, 1), + PIN_FIELD_BASE(109, 109, 5, 0x00e0, 0x10, 1, 1), + PIN_FIELD_BASE(110, 110, 5, 0x00e0, 0x10, 2, 1), + PIN_FIELD_BASE(111, 111, 5, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(112, 112, 5, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(113, 113, 4, 0x0100, 0x10, 2, 1), + PIN_FIELD_BASE(114, 114, 4, 0x0100, 0x10, 3, 1), + PIN_FIELD_BASE(115, 115, 5, 0x00e0, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, 4, 0x0100, 0x10, 10, 1), + PIN_FIELD_BASE(117, 117, 4, 0x0100, 0x10, 5, 1), + PIN_FIELD_BASE(118, 118, 3, 0x00f0, 0x10, 4, 1), + PIN_FIELD_BASE(119, 119, 3, 0x00f0, 0x10, 0, 1), + PIN_FIELD_BASE(120, 120, 3, 0x00f0, 0x10, 5, 1), + PIN_FIELD_BASE(121, 121, 3, 0x00f0, 0x10, 6, 1), + PIN_FIELD_BASE(122, 122, 7, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(123, 123, 3, 0x00f0, 0x10, 7, 1), + PIN_FIELD_BASE(124, 124, 1, 0x00b0, 0x10, 16, 1), + PIN_FIELD_BASE(125, 125, 7, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(126, 126, 2, 0x00c0, 0x10, 15, 1), + PIN_FIELD_BASE(127, 127, 2, 0x00c0, 0x10, 16, 1), + PIN_FIELD_BASE(128, 128, 2, 0x00c0, 0x10, 17, 1), + PIN_FIELD_BASE(129, 129, 2, 0x00c0, 0x10, 18, 1), + PIN_FIELD_BASE(130, 130, 3, 0x00f0, 0x10, 8, 1), + PIN_FIELD_BASE(131, 131, 3, 0x00f0, 0x10, 9, 1), + PIN_FIELD_BASE(132, 132, 3, 0x00f0, 0x10, 10, 1), + PIN_FIELD_BASE(133, 133, 3, 0x00f0, 0x10, 11, 1), + PIN_FIELD_BASE(134, 134, 3, 0x00f0, 0x10, 12, 1), + PIN_FIELD_BASE(135, 135, 8, 0x0110, 0x10, 19, 1), + PIN_FIELD_BASE(136, 136, 8, 0x0110, 0x10, 20, 1), + PIN_FIELD_BASE(137, 137, 7, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(138, 138, 7, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(139, 139, 3, 0x00f0, 0x10, 13, 1), + PIN_FIELD_BASE(140, 140, 3, 0x00f0, 0x10, 17, 1), + PIN_FIELD_BASE(141, 141, 3, 0x00f0, 0x10, 14, 1), + PIN_FIELD_BASE(142, 142, 3, 0x00f0, 0x10, 18, 1), + PIN_FIELD_BASE(143, 143, 3, 0x00f0, 0x10, 2, 1), + PIN_FIELD_BASE(144, 144, 3, 0x00f0, 0x10, 3, 1), + PIN_FIELD_BASE(145, 145, 3, 0x00f0, 0x10, 15, 1), + PIN_FIELD_BASE(146, 146, 3, 0x00f0, 0x10, 19, 1), + PIN_FIELD_BASE(147, 147, 2, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(148, 148, 2, 0x00c0, 0x10, 11, 1), + PIN_FIELD_BASE(149, 149, 5, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(150, 150, 5, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(151, 151, 3, 0x00f0, 0x10, 16, 1), + PIN_FIELD_BASE(152, 152, 3, 0x00f0, 0x10, 20, 1), + PIN_FIELD_BASE(153, 153, 2, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(154, 154, 2, 0x00c0, 0x10, 12, 1), + PIN_FIELD_BASE(155, 155, 2, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(156, 156, 2, 0x00c0, 0x10, 13, 1), + PIN_FIELD_BASE(157, 157, 8, 0x0110, 0x10, 21, 1), + PIN_FIELD_BASE(158, 158, 8, 0x0110, 0x10, 23, 1), + PIN_FIELD_BASE(159, 159, 8, 0x0110, 0x10, 22, 1), + PIN_FIELD_BASE(160, 160, 8, 0x0110, 0x10, 24, 1), + PIN_FIELD_BASE(161, 161, 5, 0x00e0, 0x10, 23, 1), + PIN_FIELD_BASE(162, 162, 5, 0x00e0, 0x10, 25, 1), + PIN_FIELD_BASE(163, 163, 5, 0x00e0, 0x10, 24, 1), + PIN_FIELD_BASE(164, 164, 5, 0x00e0, 0x10, 26, 1), + PIN_FIELD_BASE(165, 165, 4, 0x0100, 0x10, 11, 1), + PIN_FIELD_BASE(166, 166, 4, 0x0100, 0x10, 11, 1), + PIN_FIELD_BASE(167, 167, 4, 0x0100, 0x10, 12, 1), + PIN_FIELD_BASE(168, 168, 4, 0x0100, 0x10, 12, 1), + PIN_FIELD_BASE(169, 169, 4, 0x0100, 0x10, 13, 1), + PIN_FIELD_BASE(170, 170, 4, 0x0100, 0x10, 13, 1), + PIN_FIELD_BASE(171, 171, 4, 0x0100, 0x10, 14, 1), + PIN_FIELD_BASE(172, 172, 4, 0x0100, 0x10, 14, 1), + PIN_FIELD_BASE(173, 173, 1, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(174, 174, 1, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(175, 175, 1, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(176, 176, 1, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(177, 177, 1, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(178, 178, 1, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(179, 179, 1, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(180, 180, 1, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(181, 181, 1, 0x00b0, 0x10, 15, 1), + PIN_FIELD_BASE(182, 182, 9, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(183, 183, 9, 0x00a0, 0x10, 13, 1), + PIN_FIELD_BASE(184, 184, 9, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(185, 185, 9, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(186, 186, 9, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(187, 187, 9, 0x00a0, 0x10, 15, 1), + PIN_FIELD_BASE(188, 188, 9, 0x00a0, 0x10, 16, 1), + PIN_FIELD_BASE(189, 189, 9, 0x00a0, 0x10, 17, 1), + PIN_FIELD_BASE(190, 190, 9, 0x00a0, 0x10, 18, 1), + PIN_FIELD_BASE(191, 191, 9, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(192, 192, 9, 0x00a0, 0x10, 14, 1), + PIN_FIELD_BASE(193, 193, 9, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(194, 194, 9, 0x00a0, 0x10, 19, 1), + PIN_FIELD_BASE(195, 195, 9, 0x00a0, 0x10, 20, 1), + PIN_FIELD_BASE(196, 196, 6, 0x00c0, 0x10, 3, 1), +}; + +static const struct mtk_pin_field_calc mt6858_pin_pu_range[] = { + PIN_FIELD_BASE(0, 0, 8, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(1, 1, 8, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(2, 2, 8, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(3, 3, 8, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(4, 4, 8, 0x00b0, 0x10, 9, 1), + PIN_FIELD_BASE(5, 5, 8, 0x00b0, 0x10, 10, 1), + PIN_FIELD_BASE(6, 6, 8, 0x00b0, 0x10, 11, 1), + PIN_FIELD_BASE(7, 7, 8, 0x00b0, 0x10, 12, 1), + PIN_FIELD_BASE(8, 8, 5, 0x00a0, 0x10, 15, 1), + PIN_FIELD_BASE(9, 9, 5, 0x00a0, 0x10, 16, 1), + PIN_FIELD_BASE(10, 10, 5, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(11, 11, 5, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(12, 12, 5, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(13, 13, 7, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, 7, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(15, 15, 7, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(16, 16, 7, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(17, 17, 7, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(21, 21, 5, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(22, 22, 5, 0x00a0, 0x10, 13, 1), + PIN_FIELD_BASE(23, 23, 8, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(24, 24, 5, 0x00a0, 0x10, 14, 1), + PIN_FIELD_BASE(25, 25, 2, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(26, 26, 3, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(27, 27, 2, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(28, 28, 2, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(29, 29, 2, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(30, 30, 2, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(31, 31, 2, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(32, 32, 2, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(33, 33, 2, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(34, 34, 2, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(35, 35, 4, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(36, 36, 8, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(37, 37, 8, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, 8, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(39, 39, 8, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(40, 40, 1, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(41, 41, 1, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(42, 42, 1, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(43, 43, 1, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(44, 44, 1, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(45, 45, 5, 0x00a0, 0x10, 17, 1), + PIN_FIELD_BASE(46, 46, 5, 0x00a0, 0x10, 19, 1), + PIN_FIELD_BASE(47, 47, 5, 0x00a0, 0x10, 20, 1), + PIN_FIELD_BASE(48, 48, 5, 0x00a0, 0x10, 18, 1), + PIN_FIELD_BASE(49, 49, 4, 0x00b0, 0x10, 20, 1), + PIN_FIELD_BASE(50, 50, 4, 0x00b0, 0x10, 19, 1), + PIN_FIELD_BASE(51, 51, 1, 0x0090, 0x10, 28, 1), + PIN_FIELD_BASE(52, 52, 1, 0x0090, 0x10, 27, 1), + PIN_FIELD_BASE(53, 53, 5, 0x00a0, 0x10, 25, 1), + PIN_FIELD_BASE(54, 54, 5, 0x00a0, 0x10, 21, 1), + PIN_FIELD_BASE(55, 55, 5, 0x00a0, 0x10, 24, 1), + PIN_FIELD_BASE(56, 56, 5, 0x00a0, 0x10, 22, 1), + PIN_FIELD_BASE(57, 57, 5, 0x00a0, 0x10, 23, 1), + PIN_FIELD_BASE(58, 58, 3, 0x00a0, 0x10, 21, 1), + PIN_FIELD_BASE(59, 59, 3, 0x00a0, 0x10, 22, 1), + PIN_FIELD_BASE(60, 60, 3, 0x00a0, 0x10, 24, 1), + PIN_FIELD_BASE(61, 61, 3, 0x00a0, 0x10, 23, 1), + PIN_FIELD_BASE(62, 62, 8, 0x00b0, 0x10, 19, 1), + PIN_FIELD_BASE(63, 63, 8, 0x00b0, 0x10, 20, 1), + PIN_FIELD_BASE(64, 64, 8, 0x00b0, 0x10, 22, 1), + PIN_FIELD_BASE(65, 65, 8, 0x00b0, 0x10, 21, 1), + PIN_FIELD_BASE(66, 66, 1, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(67, 67, 1, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(68, 68, 1, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(69, 69, 1, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(70, 70, 1, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(71, 71, 1, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(72, 72, 1, 0x0090, 0x10, 24, 1), + PIN_FIELD_BASE(73, 73, 1, 0x0090, 0x10, 23, 1), + PIN_FIELD_BASE(74, 74, 1, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(75, 75, 1, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(76, 76, 1, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(77, 77, 1, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(78, 78, 3, 0x00a0, 0x10, 25, 1), + PIN_FIELD_BASE(79, 79, 3, 0x00a0, 0x10, 26, 1), + PIN_FIELD_BASE(80, 80, 3, 0x00a0, 0x10, 28, 1), + PIN_FIELD_BASE(81, 81, 3, 0x00a0, 0x10, 27, 1), + PIN_FIELD_BASE(94, 94, 4, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(95, 95, 4, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(96, 96, 4, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(97, 97, 4, 0x00b0, 0x10, 9, 1), + PIN_FIELD_BASE(98, 98, 5, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(99, 99, 9, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(100, 100, 9, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(101, 101, 9, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(102, 102, 9, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(103, 103, 9, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(104, 104, 9, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(105, 105, 9, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(106, 106, 5, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(107, 107, 4, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(108, 108, 4, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(109, 109, 5, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(110, 110, 5, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(111, 111, 5, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(112, 112, 5, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(113, 113, 4, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(114, 114, 4, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(115, 115, 5, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, 4, 0x00b0, 0x10, 10, 1), + PIN_FIELD_BASE(117, 117, 4, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(118, 118, 3, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(119, 119, 3, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(120, 120, 3, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(121, 121, 3, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(122, 122, 7, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(123, 123, 3, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(124, 124, 1, 0x0090, 0x10, 26, 1), + PIN_FIELD_BASE(125, 125, 7, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(126, 126, 2, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(127, 127, 2, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(128, 128, 2, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(129, 129, 2, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(130, 130, 3, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(131, 131, 3, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(132, 132, 3, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(133, 133, 3, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(134, 134, 3, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(135, 135, 8, 0x00b0, 0x10, 13, 1), + PIN_FIELD_BASE(136, 136, 8, 0x00b0, 0x10, 14, 1), + PIN_FIELD_BASE(137, 137, 7, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(138, 138, 7, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(139, 139, 3, 0x00a0, 0x10, 13, 1), + PIN_FIELD_BASE(140, 140, 3, 0x00a0, 0x10, 17, 1), + PIN_FIELD_BASE(141, 141, 3, 0x00a0, 0x10, 14, 1), + PIN_FIELD_BASE(142, 142, 3, 0x00a0, 0x10, 18, 1), + PIN_FIELD_BASE(143, 143, 3, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(144, 144, 3, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(145, 145, 3, 0x00a0, 0x10, 15, 1), + PIN_FIELD_BASE(146, 146, 3, 0x00a0, 0x10, 19, 1), + PIN_FIELD_BASE(147, 147, 2, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(148, 148, 2, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(149, 149, 5, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(150, 150, 5, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(151, 151, 3, 0x00a0, 0x10, 16, 1), + PIN_FIELD_BASE(152, 152, 3, 0x00a0, 0x10, 20, 1), + PIN_FIELD_BASE(153, 153, 2, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(154, 154, 2, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(155, 155, 2, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(156, 156, 2, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(157, 157, 8, 0x00b0, 0x10, 15, 1), + PIN_FIELD_BASE(158, 158, 8, 0x00b0, 0x10, 17, 1), + PIN_FIELD_BASE(159, 159, 8, 0x00b0, 0x10, 16, 1), + PIN_FIELD_BASE(160, 160, 8, 0x00b0, 0x10, 18, 1), + PIN_FIELD_BASE(161, 161, 5, 0x00a0, 0x10, 26, 1), + PIN_FIELD_BASE(162, 162, 5, 0x00a0, 0x10, 28, 1), + PIN_FIELD_BASE(163, 163, 5, 0x00a0, 0x10, 27, 1), + PIN_FIELD_BASE(164, 164, 5, 0x00a0, 0x10, 29, 1), + PIN_FIELD_BASE(165, 165, 4, 0x00b0, 0x10, 11, 1), + PIN_FIELD_BASE(166, 166, 4, 0x00b0, 0x10, 12, 1), + PIN_FIELD_BASE(167, 167, 4, 0x00b0, 0x10, 13, 1), + PIN_FIELD_BASE(168, 168, 4, 0x00b0, 0x10, 14, 1), + PIN_FIELD_BASE(169, 169, 4, 0x00b0, 0x10, 15, 1), + PIN_FIELD_BASE(170, 170, 4, 0x00b0, 0x10, 16, 1), + PIN_FIELD_BASE(171, 171, 4, 0x00b0, 0x10, 17, 1), + PIN_FIELD_BASE(172, 172, 4, 0x00b0, 0x10, 18, 1), + PIN_FIELD_BASE(173, 173, 1, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(174, 174, 1, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(175, 175, 1, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(176, 176, 1, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(177, 177, 1, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(178, 178, 1, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(179, 179, 1, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(180, 180, 1, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(181, 181, 1, 0x0090, 0x10, 25, 1), + PIN_FIELD_BASE(182, 182, 9, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(183, 183, 9, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(184, 184, 9, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(185, 185, 9, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(186, 186, 9, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(187, 187, 9, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(188, 188, 9, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(189, 189, 9, 0x0080, 0x10, 17, 1), + PIN_FIELD_BASE(190, 190, 9, 0x0080, 0x10, 18, 1), + PIN_FIELD_BASE(191, 191, 9, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(192, 192, 9, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(193, 193, 9, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(194, 194, 9, 0x0080, 0x10, 19, 1), + PIN_FIELD_BASE(195, 195, 9, 0x0080, 0x10, 20, 1), + PIN_FIELD_BASE(196, 196, 6, 0x0080, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6858_pin_pd_range[] = { + PIN_FIELD_BASE(0, 0, 8, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(1, 1, 8, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(2, 2, 8, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(3, 3, 8, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(4, 4, 8, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(5, 5, 8, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(6, 6, 8, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(7, 7, 8, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(8, 8, 5, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(9, 9, 5, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(10, 10, 5, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(11, 11, 5, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(12, 12, 5, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(13, 13, 7, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, 7, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(15, 15, 7, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(16, 16, 7, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(17, 17, 7, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(21, 21, 5, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(22, 22, 5, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(23, 23, 8, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(24, 24, 5, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(25, 25, 2, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(26, 26, 3, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(27, 27, 2, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(28, 28, 2, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(29, 29, 2, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(30, 30, 2, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(31, 31, 2, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(32, 32, 2, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(33, 33, 2, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(34, 34, 2, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(35, 35, 4, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(36, 36, 8, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(37, 37, 8, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, 8, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(39, 39, 8, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(40, 40, 1, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(41, 41, 1, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(42, 42, 1, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(43, 43, 1, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(44, 44, 1, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(45, 45, 5, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(46, 46, 5, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(47, 47, 5, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(48, 48, 5, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(49, 49, 4, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(50, 50, 4, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(51, 51, 1, 0x0080, 0x10, 28, 1), + PIN_FIELD_BASE(52, 52, 1, 0x0080, 0x10, 27, 1), + PIN_FIELD_BASE(53, 53, 5, 0x0090, 0x10, 25, 1), + PIN_FIELD_BASE(54, 54, 5, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(55, 55, 5, 0x0090, 0x10, 24, 1), + PIN_FIELD_BASE(56, 56, 5, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(57, 57, 5, 0x0090, 0x10, 23, 1), + PIN_FIELD_BASE(58, 58, 3, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(59, 59, 3, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(60, 60, 3, 0x0090, 0x10, 24, 1), + PIN_FIELD_BASE(61, 61, 3, 0x0090, 0x10, 23, 1), + PIN_FIELD_BASE(62, 62, 8, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(63, 63, 8, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(64, 64, 8, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(65, 65, 8, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(66, 66, 1, 0x0080, 0x10, 17, 1), + PIN_FIELD_BASE(67, 67, 1, 0x0080, 0x10, 18, 1), + PIN_FIELD_BASE(68, 68, 1, 0x0080, 0x10, 20, 1), + PIN_FIELD_BASE(69, 69, 1, 0x0080, 0x10, 19, 1), + PIN_FIELD_BASE(70, 70, 1, 0x0080, 0x10, 21, 1), + PIN_FIELD_BASE(71, 71, 1, 0x0080, 0x10, 22, 1), + PIN_FIELD_BASE(72, 72, 1, 0x0080, 0x10, 24, 1), + PIN_FIELD_BASE(73, 73, 1, 0x0080, 0x10, 23, 1), + PIN_FIELD_BASE(74, 74, 1, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(75, 75, 1, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(76, 76, 1, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(77, 77, 1, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(78, 78, 3, 0x0090, 0x10, 25, 1), + PIN_FIELD_BASE(79, 79, 3, 0x0090, 0x10, 26, 1), + PIN_FIELD_BASE(80, 80, 3, 0x0090, 0x10, 28, 1), + PIN_FIELD_BASE(81, 81, 3, 0x0090, 0x10, 27, 1), + PIN_FIELD_BASE(94, 94, 4, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(95, 95, 4, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(96, 96, 4, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(97, 97, 4, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(98, 98, 5, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(99, 99, 9, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(100, 100, 9, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(101, 101, 9, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(102, 102, 9, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(103, 103, 9, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(104, 104, 9, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(105, 105, 9, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(106, 106, 5, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(107, 107, 4, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(108, 108, 4, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(109, 109, 5, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(110, 110, 5, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(111, 111, 5, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(112, 112, 5, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(113, 113, 4, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(114, 114, 4, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(115, 115, 5, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, 4, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(117, 117, 4, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(118, 118, 3, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(119, 119, 3, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(120, 120, 3, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(121, 121, 3, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(122, 122, 7, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(123, 123, 3, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(124, 124, 1, 0x0080, 0x10, 26, 1), + PIN_FIELD_BASE(125, 125, 7, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(126, 126, 2, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(127, 127, 2, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(128, 128, 2, 0x0080, 0x10, 17, 1), + PIN_FIELD_BASE(129, 129, 2, 0x0080, 0x10, 18, 1), + PIN_FIELD_BASE(130, 130, 3, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(131, 131, 3, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(132, 132, 3, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(133, 133, 3, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(134, 134, 3, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(135, 135, 8, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(136, 136, 8, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(137, 137, 7, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(138, 138, 7, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(139, 139, 3, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(140, 140, 3, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(141, 141, 3, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(142, 142, 3, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(143, 143, 3, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(144, 144, 3, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(145, 145, 3, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(146, 146, 3, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(147, 147, 2, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(148, 148, 2, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(149, 149, 5, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(150, 150, 5, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(151, 151, 3, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(152, 152, 3, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(153, 153, 2, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(154, 154, 2, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(155, 155, 2, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(156, 156, 2, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(157, 157, 8, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(158, 158, 8, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(159, 159, 8, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(160, 160, 8, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(161, 161, 5, 0x0090, 0x10, 26, 1), + PIN_FIELD_BASE(162, 162, 5, 0x0090, 0x10, 28, 1), + PIN_FIELD_BASE(163, 163, 5, 0x0090, 0x10, 27, 1), + PIN_FIELD_BASE(164, 164, 5, 0x0090, 0x10, 29, 1), + PIN_FIELD_BASE(165, 165, 4, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(166, 166, 4, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(167, 167, 4, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(168, 168, 4, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(169, 169, 4, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(170, 170, 4, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(171, 171, 4, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(172, 172, 4, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(173, 173, 1, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(174, 174, 1, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(175, 175, 1, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(176, 176, 1, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(177, 177, 1, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(178, 178, 1, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(179, 179, 1, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(180, 180, 1, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(181, 181, 1, 0x0080, 0x10, 25, 1), + PIN_FIELD_BASE(182, 182, 9, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(183, 183, 9, 0x0070, 0x10, 13, 1), + PIN_FIELD_BASE(184, 184, 9, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(185, 185, 9, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(186, 186, 9, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(187, 187, 9, 0x0070, 0x10, 15, 1), + PIN_FIELD_BASE(188, 188, 9, 0x0070, 0x10, 16, 1), + PIN_FIELD_BASE(189, 189, 9, 0x0070, 0x10, 17, 1), + PIN_FIELD_BASE(190, 190, 9, 0x0070, 0x10, 18, 1), + PIN_FIELD_BASE(191, 191, 9, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(192, 192, 9, 0x0070, 0x10, 14, 1), + PIN_FIELD_BASE(193, 193, 9, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(194, 194, 9, 0x0070, 0x10, 19, 1), + PIN_FIELD_BASE(195, 195, 9, 0x0070, 0x10, 20, 1), + PIN_FIELD_BASE(196, 196, 6, 0x0060, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6858_pin_pupd_range[] = { + PIN_FIELD_BASE(18, 18, 6, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(19, 19, 6, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(20, 20, 6, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(82, 82, 8, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(83, 83, 8, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(84, 84, 8, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(85, 85, 8, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(86, 86, 8, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(87, 87, 8, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(88, 88, 4, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(89, 89, 4, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(90, 90, 4, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(91, 91, 4, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(92, 92, 4, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(93, 93, 4, 0x00a0, 0x10, 4, 1), +}; + +static const struct mtk_pin_field_calc mt6858_pin_r0_range[] = { + PIN_FIELD_BASE(18, 18, 6, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(19, 19, 6, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(20, 20, 6, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(82, 82, 8, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(83, 83, 8, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(84, 84, 8, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(85, 85, 8, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(86, 86, 8, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(87, 87, 8, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(88, 88, 4, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(89, 89, 4, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(90, 90, 4, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(91, 91, 4, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(92, 92, 4, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(93, 93, 4, 0x00c0, 0x10, 4, 1), +}; + +static const struct mtk_pin_field_calc mt6858_pin_r1_range[] = { + PIN_FIELD_BASE(18, 18, 6, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(19, 19, 6, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(20, 20, 6, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(82, 82, 8, 0x00d0, 0x10, 0, 1), + PIN_FIELD_BASE(83, 83, 8, 0x00d0, 0x10, 1, 1), + PIN_FIELD_BASE(84, 84, 8, 0x00d0, 0x10, 2, 1), + PIN_FIELD_BASE(85, 85, 8, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(86, 86, 8, 0x00d0, 0x10, 4, 1), + PIN_FIELD_BASE(87, 87, 8, 0x00d0, 0x10, 5, 1), + PIN_FIELD_BASE(88, 88, 4, 0x00d0, 0x10, 0, 1), + PIN_FIELD_BASE(89, 89, 4, 0x00d0, 0x10, 2, 1), + PIN_FIELD_BASE(90, 90, 4, 0x00d0, 0x10, 1, 1), + PIN_FIELD_BASE(91, 91, 4, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(92, 92, 4, 0x00d0, 0x10, 5, 1), + PIN_FIELD_BASE(93, 93, 4, 0x00d0, 0x10, 4, 1), +}; + +static const struct mtk_pin_field_calc mt6858_pin_drv_range[] = { + PIN_FIELD_BASE(0, 0, 8, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(1, 1, 8, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(2, 2, 8, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(3, 3, 8, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(4, 4, 8, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(5, 5, 8, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(6, 6, 8, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(7, 7, 8, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(8, 8, 5, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(9, 9, 5, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(10, 10, 5, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(11, 11, 5, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(12, 12, 5, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(13, 13, 7, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(14, 14, 7, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(15, 15, 7, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(16, 16, 7, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(17, 17, 7, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(18, 18, 6, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(19, 19, 6, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(20, 20, 6, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(21, 21, 5, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(22, 22, 5, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(23, 23, 8, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(24, 24, 5, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(25, 25, 2, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(26, 26, 3, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(27, 27, 2, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(28, 28, 2, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(29, 29, 2, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(30, 30, 2, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(31, 31, 2, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(32, 32, 2, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(33, 33, 2, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(34, 34, 2, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(35, 35, 4, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(36, 36, 8, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(37, 37, 8, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(38, 38, 8, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(39, 39, 8, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(40, 40, 1, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(41, 41, 1, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(42, 42, 1, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(43, 43, 1, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(44, 44, 1, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(45, 45, 5, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(46, 46, 5, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(47, 47, 5, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(48, 48, 5, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(49, 49, 4, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(50, 50, 4, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(51, 51, 1, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(52, 52, 1, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(53, 53, 5, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(54, 54, 5, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(55, 55, 5, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(56, 56, 5, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(57, 57, 5, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(58, 58, 3, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(59, 59, 3, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(60, 60, 3, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(61, 61, 3, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(62, 62, 8, 0x0020, 0x10, 15, 3), + PIN_FIELD_BASE(63, 63, 8, 0x0020, 0x10, 18, 3), + PIN_FIELD_BASE(64, 64, 8, 0x0020, 0x10, 24, 3), + PIN_FIELD_BASE(65, 65, 8, 0x0020, 0x10, 21, 3), + PIN_FIELD_BASE(66, 66, 1, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(67, 67, 1, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(68, 68, 1, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(69, 69, 1, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(70, 70, 1, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(71, 71, 1, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(72, 72, 1, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(73, 73, 1, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(74, 74, 1, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(75, 75, 1, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(76, 76, 1, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(77, 77, 1, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(78, 78, 3, 0x0020, 0x10, 15, 3), + PIN_FIELD_BASE(79, 79, 3, 0x0020, 0x10, 18, 3), + PIN_FIELD_BASE(80, 80, 3, 0x0020, 0x10, 24, 3), + PIN_FIELD_BASE(81, 81, 3, 0x0020, 0x10, 21, 3), + PIN_FIELD_BASE(82, 82, 8, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(83, 83, 8, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(84, 84, 8, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(85, 85, 8, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(86, 86, 8, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(87, 87, 8, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(88, 88, 4, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(89, 89, 4, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(90, 90, 4, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(91, 91, 4, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(92, 92, 4, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(93, 93, 4, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(94, 94, 4, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(95, 95, 4, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(96, 96, 4, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(97, 97, 4, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(98, 98, 5, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(99, 99, 9, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(100, 100, 9, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(101, 101, 9, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(102, 102, 9, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(103, 103, 9, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(104, 104, 9, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(105, 105, 9, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(106, 106, 5, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(107, 107, 4, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(108, 108, 4, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(109, 109, 5, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(110, 110, 5, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(111, 111, 5, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(112, 112, 5, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(113, 113, 4, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(114, 114, 4, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(115, 115, 5, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(116, 116, 4, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(117, 117, 4, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(118, 118, 3, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(119, 119, 3, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(120, 120, 3, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(121, 121, 3, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(122, 122, 7, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(123, 123, 3, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(124, 124, 1, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(125, 125, 7, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(126, 126, 2, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(127, 127, 2, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(128, 128, 2, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(129, 129, 2, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(130, 130, 3, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(131, 131, 3, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(132, 132, 3, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(133, 133, 3, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(134, 134, 3, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(135, 135, 8, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(136, 136, 8, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(137, 137, 7, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(138, 138, 7, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(139, 139, 3, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(140, 140, 3, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(141, 141, 3, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(142, 142, 3, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(143, 143, 3, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(144, 144, 3, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(145, 145, 3, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(146, 146, 3, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(147, 147, 2, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(148, 148, 2, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(149, 149, 5, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(150, 150, 5, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(151, 151, 3, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(152, 152, 3, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(153, 153, 2, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(154, 154, 2, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(155, 155, 2, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(156, 156, 2, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(157, 157, 8, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(158, 158, 8, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(159, 159, 8, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(160, 160, 8, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(161, 161, 5, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(162, 162, 5, 0x0020, 0x10, 15, 3), + PIN_FIELD_BASE(163, 163, 5, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(164, 164, 5, 0x0020, 0x10, 18, 3), + PIN_FIELD_BASE(165, 165, 4, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(166, 166, 4, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(167, 167, 4, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(168, 168, 4, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(169, 169, 4, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(170, 170, 4, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(171, 171, 4, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(172, 172, 4, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(173, 173, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(174, 174, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(175, 175, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(176, 176, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(177, 177, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(178, 178, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(179, 179, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(180, 180, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(181, 181, 1, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(182, 182, 9, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(183, 183, 9, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(184, 184, 9, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(185, 185, 9, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(186, 186, 9, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(187, 187, 9, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(188, 188, 9, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(189, 189, 9, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(190, 190, 9, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(191, 191, 9, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(192, 192, 9, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(193, 193, 9, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(194, 194, 9, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(195, 195, 9, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(196, 196, 6, 0x0000, 0x10, 9, 3), +}; + +static const struct mtk_pin_field_calc mt6858_pin_drv_adv_range[] = { + PIN_FIELD_BASE(36, 36, 8, 0x0030, 0x10, 0, 5), + PIN_FIELD_BASE(37, 37, 8, 0x0030, 0x10, 5, 5), + PIN_FIELD_BASE(38, 38, 8, 0x0030, 0x10, 10, 5), + PIN_FIELD_BASE(39, 39, 8, 0x0030, 0x10, 15, 5), + PIN_FIELD_BASE(126, 126, 2, 0x0020, 0x10, 18, 5), + PIN_FIELD_BASE(127, 127, 2, 0x0020, 0x10, 23, 5), + PIN_FIELD_BASE(128, 128, 2, 0x0030, 0x10, 0, 5), + PIN_FIELD_BASE(129, 129, 2, 0x0030, 0x10, 5, 5), + PIN_FIELD_BASE(139, 139, 3, 0x0030, 0x10, 6, 3), + PIN_FIELD_BASE(140, 140, 3, 0x0030, 0x10, 18, 3), + PIN_FIELD_BASE(141, 141, 3, 0x0030, 0x10, 9, 3), + PIN_FIELD_BASE(142, 142, 3, 0x0030, 0x10, 21, 3), + PIN_FIELD_BASE(143, 143, 3, 0x0030, 0x10, 0, 3), + PIN_FIELD_BASE(144, 144, 3, 0x0030, 0x10, 3, 3), + PIN_FIELD_BASE(145, 145, 3, 0x0030, 0x10, 12, 3), + PIN_FIELD_BASE(146, 146, 3, 0x0030, 0x10, 24, 3), + PIN_FIELD_BASE(147, 147, 2, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(148, 148, 2, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(149, 149, 5, 0x0030, 0x10, 0, 3), + PIN_FIELD_BASE(150, 150, 5, 0x0030, 0x10, 3, 3), + PIN_FIELD_BASE(151, 151, 3, 0x0030, 0x10, 15, 3), + PIN_FIELD_BASE(152, 152, 3, 0x0030, 0x10, 27, 3), + PIN_FIELD_BASE(153, 153, 2, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(154, 154, 2, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(155, 155, 2, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(156, 156, 2, 0x0020, 0x10, 15, 3), + PIN_FIELD_BASE(157, 157, 8, 0x0030, 0x10, 20, 3), + PIN_FIELD_BASE(158, 158, 8, 0x0030, 0x10, 26, 3), + PIN_FIELD_BASE(159, 159, 8, 0x0030, 0x10, 23, 3), + PIN_FIELD_BASE(160, 160, 8, 0x0030, 0x10, 29, 3), + PIN_FIELD_BASE(161, 161, 5, 0x0030, 0x10, 6, 3), + PIN_FIELD_BASE(162, 162, 5, 0x0030, 0x10, 12, 3), + PIN_FIELD_BASE(163, 163, 5, 0x0030, 0x10, 9, 3), + PIN_FIELD_BASE(164, 164, 5, 0x0030, 0x10, 15, 3), +}; + +static const struct mtk_pin_field_calc mt6858_pin_rsel_range[] = { + PIN_FIELD_BASE(139, 139, 3, 0x00e0, 0x10, 6, 3), + PIN_FIELD_BASE(140, 140, 3, 0x00e0, 0x10, 18, 3), + PIN_FIELD_BASE(141, 141, 3, 0x00e0, 0x10, 9, 3), + PIN_FIELD_BASE(142, 142, 3, 0x00e0, 0x10, 21, 3), + PIN_FIELD_BASE(143, 143, 3, 0x00e0, 0x10, 0, 3), + PIN_FIELD_BASE(144, 144, 3, 0x00e0, 0x10, 3, 3), + PIN_FIELD_BASE(145, 145, 3, 0x00e0, 0x10, 12, 3), + PIN_FIELD_BASE(146, 146, 3, 0x00e0, 0x10, 24, 3), + PIN_FIELD_BASE(147, 147, 2, 0x00b0, 0x10, 0, 3), + PIN_FIELD_BASE(148, 148, 2, 0x00b0, 0x10, 9, 3), + PIN_FIELD_BASE(149, 149, 5, 0x00d0, 0x10, 0, 3), + PIN_FIELD_BASE(150, 150, 5, 0x00d0, 0x10, 3, 3), + PIN_FIELD_BASE(151, 151, 3, 0x00e0, 0x10, 15, 3), + PIN_FIELD_BASE(152, 152, 3, 0x00e0, 0x10, 27, 3), + PIN_FIELD_BASE(153, 153, 2, 0x00b0, 0x10, 3, 3), + PIN_FIELD_BASE(154, 154, 2, 0x00b0, 0x10, 12, 3), + PIN_FIELD_BASE(155, 155, 2, 0x00b0, 0x10, 6, 3), + PIN_FIELD_BASE(156, 156, 2, 0x00b0, 0x10, 15, 3), + PIN_FIELD_BASE(157, 157, 8, 0x0100, 0x10, 0, 3), + PIN_FIELD_BASE(158, 158, 8, 0x0100, 0x10, 6, 3), + PIN_FIELD_BASE(159, 159, 8, 0x0100, 0x10, 3, 3), + PIN_FIELD_BASE(160, 160, 8, 0x0100, 0x10, 9, 3), + PIN_FIELD_BASE(161, 161, 5, 0x00d0, 0x10, 6, 3), + PIN_FIELD_BASE(162, 162, 5, 0x00d0, 0x10, 12, 3), + PIN_FIELD_BASE(163, 163, 5, 0x00d0, 0x10, 9, 3), + PIN_FIELD_BASE(164, 164, 5, 0x00d0, 0x10, 15, 3), +}; + +static const unsigned int mt6858_pull_type[] = { + MTK_PULL_PU_PD_TYPE, /* 0 */ + MTK_PULL_PU_PD_TYPE, /* 1 */ + MTK_PULL_PU_PD_TYPE, /* 2 */ + MTK_PULL_PU_PD_TYPE, /* 3 */ + MTK_PULL_PU_PD_TYPE, /* 4 */ + MTK_PULL_PU_PD_TYPE, /* 5 */ + MTK_PULL_PU_PD_TYPE, /* 6 */ + MTK_PULL_PU_PD_TYPE, /* 7 */ + MTK_PULL_PU_PD_TYPE, /* 8 */ + MTK_PULL_PU_PD_TYPE, /* 9 */ + MTK_PULL_PU_PD_TYPE, /* 10 */ + MTK_PULL_PU_PD_TYPE, /* 11 */ + MTK_PULL_PU_PD_TYPE, /* 12 */ + MTK_PULL_PU_PD_TYPE, /* 13 */ + MTK_PULL_PU_PD_TYPE, /* 14 */ + MTK_PULL_PU_PD_TYPE, /* 15 */ + MTK_PULL_PU_PD_TYPE, /* 16 */ + MTK_PULL_PU_PD_TYPE, /* 17 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 18 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 19 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 20 */ + MTK_PULL_PU_PD_TYPE, /* 21 */ + MTK_PULL_PU_PD_TYPE, /* 22 */ + MTK_PULL_PU_PD_TYPE, /* 23 */ + MTK_PULL_PU_PD_TYPE, /* 24 */ + MTK_PULL_PU_PD_TYPE, /* 25 */ + MTK_PULL_PU_PD_TYPE, /* 26 */ + MTK_PULL_PU_PD_TYPE, /* 27 */ + MTK_PULL_PU_PD_TYPE, /* 28 */ + MTK_PULL_PU_PD_TYPE, /* 29 */ + MTK_PULL_PU_PD_TYPE, /* 30 */ + MTK_PULL_PU_PD_TYPE, /* 31 */ + MTK_PULL_PU_PD_TYPE, /* 32 */ + MTK_PULL_PU_PD_TYPE, /* 33 */ + MTK_PULL_PU_PD_TYPE, /* 34 */ + MTK_PULL_PU_PD_TYPE, /* 35 */ + MTK_PULL_PU_PD_TYPE, /* 36 */ + MTK_PULL_PU_PD_TYPE, /* 37 */ + MTK_PULL_PU_PD_TYPE, /* 38 */ + MTK_PULL_PU_PD_TYPE, /* 39 */ + MTK_PULL_PU_PD_TYPE, /* 40 */ + MTK_PULL_PU_PD_TYPE, /* 41 */ + MTK_PULL_PU_PD_TYPE, /* 42 */ + MTK_PULL_PU_PD_TYPE, /* 43 */ + MTK_PULL_PU_PD_TYPE, /* 44 */ + MTK_PULL_PU_PD_TYPE, /* 45 */ + MTK_PULL_PU_PD_TYPE, /* 46 */ + MTK_PULL_PU_PD_TYPE, /* 47 */ + MTK_PULL_PU_PD_TYPE, /* 48 */ + MTK_PULL_PU_PD_TYPE, /* 49 */ + MTK_PULL_PU_PD_TYPE, /* 50 */ + MTK_PULL_PU_PD_TYPE, /* 51 */ + MTK_PULL_PU_PD_TYPE, /* 52 */ + MTK_PULL_PU_PD_TYPE, /* 53 */ + MTK_PULL_PU_PD_TYPE, /* 54 */ + MTK_PULL_PU_PD_TYPE, /* 55 */ + MTK_PULL_PU_PD_TYPE, /* 56 */ + MTK_PULL_PU_PD_TYPE, /* 57 */ + MTK_PULL_PU_PD_TYPE, /* 58 */ + MTK_PULL_PU_PD_TYPE, /* 59 */ + MTK_PULL_PU_PD_TYPE, /* 60 */ + MTK_PULL_PU_PD_TYPE, /* 61 */ + MTK_PULL_PU_PD_TYPE, /* 62 */ + MTK_PULL_PU_PD_TYPE, /* 63 */ + MTK_PULL_PU_PD_TYPE, /* 64 */ + MTK_PULL_PU_PD_TYPE, /* 65 */ + MTK_PULL_PU_PD_TYPE, /* 66 */ + MTK_PULL_PU_PD_TYPE, /* 67 */ + MTK_PULL_PU_PD_TYPE, /* 68 */ + MTK_PULL_PU_PD_TYPE, /* 69 */ + MTK_PULL_PU_PD_TYPE, /* 70 */ + MTK_PULL_PU_PD_TYPE, /* 71 */ + MTK_PULL_PU_PD_TYPE, /* 72 */ + MTK_PULL_PU_PD_TYPE, /* 73 */ + MTK_PULL_PU_PD_TYPE, /* 74 */ + MTK_PULL_PU_PD_TYPE, /* 75 */ + MTK_PULL_PU_PD_TYPE, /* 76 */ + MTK_PULL_PU_PD_TYPE, /* 77 */ + MTK_PULL_PU_PD_TYPE, /* 78 */ + MTK_PULL_PU_PD_TYPE, /* 79 */ + MTK_PULL_PU_PD_TYPE, /* 80 */ + MTK_PULL_PU_PD_TYPE, /* 81 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 82 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 83 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 84 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 85 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 86 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 87 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 88 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 89 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 90 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 91 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 92 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 93 */ + MTK_PULL_PU_PD_TYPE, /* 94 */ + MTK_PULL_PU_PD_TYPE, /* 95 */ + MTK_PULL_PU_PD_TYPE, /* 96 */ + MTK_PULL_PU_PD_TYPE, /* 97 */ + MTK_PULL_PU_PD_TYPE, /* 98 */ + MTK_PULL_PU_PD_TYPE, /* 99 */ + MTK_PULL_PU_PD_TYPE, /* 100 */ + MTK_PULL_PU_PD_TYPE, /* 101 */ + MTK_PULL_PU_PD_TYPE, /* 102 */ + MTK_PULL_PU_PD_TYPE, /* 103 */ + MTK_PULL_PU_PD_TYPE, /* 104 */ + MTK_PULL_PU_PD_TYPE, /* 105 */ + MTK_PULL_PU_PD_TYPE, /* 106 */ + MTK_PULL_PU_PD_TYPE, /* 107 */ + MTK_PULL_PU_PD_TYPE, /* 108 */ + MTK_PULL_PU_PD_TYPE, /* 109 */ + MTK_PULL_PU_PD_TYPE, /* 110 */ + MTK_PULL_PU_PD_TYPE, /* 111 */ + MTK_PULL_PU_PD_TYPE, /* 112 */ + MTK_PULL_PU_PD_TYPE, /* 113 */ + MTK_PULL_PU_PD_TYPE, /* 114 */ + MTK_PULL_PU_PD_TYPE, /* 115 */ + MTK_PULL_PU_PD_TYPE, /* 116 */ + MTK_PULL_PU_PD_TYPE, /* 117 */ + MTK_PULL_PU_PD_TYPE, /* 118 */ + MTK_PULL_PU_PD_TYPE, /* 119 */ + MTK_PULL_PU_PD_TYPE, /* 120 */ + MTK_PULL_PU_PD_TYPE, /* 121 */ + MTK_PULL_PU_PD_TYPE, /* 122 */ + MTK_PULL_PU_PD_TYPE, /* 123 */ + MTK_PULL_PU_PD_TYPE, /* 124 */ + MTK_PULL_PU_PD_TYPE, /* 125 */ + MTK_PULL_PU_PD_TYPE, /* 126 */ + MTK_PULL_PU_PD_TYPE, /* 127 */ + MTK_PULL_PU_PD_TYPE, /* 128 */ + MTK_PULL_PU_PD_TYPE, /* 129 */ + MTK_PULL_PU_PD_TYPE, /* 130 */ + MTK_PULL_PU_PD_TYPE, /* 131 */ + MTK_PULL_PU_PD_TYPE, /* 132 */ + MTK_PULL_PU_PD_TYPE, /* 133 */ + MTK_PULL_PU_PD_TYPE, /* 134 */ + MTK_PULL_PU_PD_TYPE, /* 135 */ + MTK_PULL_PU_PD_TYPE, /* 136 */ + MTK_PULL_PU_PD_TYPE, /* 137 */ + MTK_PULL_PU_PD_TYPE, /* 138 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 139 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 140 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 141 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 142 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 143 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 144 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 145 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 146 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 147 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 148 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 149 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 150 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 151 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 152 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 153 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 154 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 155 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 156 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 157 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 158 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 159 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 160 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 161 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 162 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 163 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 164 */ + MTK_PULL_PU_PD_TYPE, /* 165 */ + MTK_PULL_PU_PD_TYPE, /* 166 */ + MTK_PULL_PU_PD_TYPE, /* 167 */ + MTK_PULL_PU_PD_TYPE, /* 168 */ + MTK_PULL_PU_PD_TYPE, /* 169 */ + MTK_PULL_PU_PD_TYPE, /* 170 */ + MTK_PULL_PU_PD_TYPE, /* 171 */ + MTK_PULL_PU_PD_TYPE, /* 172 */ + MTK_PULL_PU_PD_TYPE, /* 173 */ + MTK_PULL_PU_PD_TYPE, /* 174 */ + MTK_PULL_PU_PD_TYPE, /* 175 */ + MTK_PULL_PU_PD_TYPE, /* 176 */ + MTK_PULL_PU_PD_TYPE, /* 177 */ + MTK_PULL_PU_PD_TYPE, /* 178 */ + MTK_PULL_PU_PD_TYPE, /* 179 */ + MTK_PULL_PU_PD_TYPE, /* 180 */ + MTK_PULL_PU_PD_TYPE, /* 181 */ + MTK_PULL_PU_PD_TYPE, /* 182 */ + MTK_PULL_PU_PD_TYPE, /* 183 */ + MTK_PULL_PU_PD_TYPE, /* 184 */ + MTK_PULL_PU_PD_TYPE, /* 185 */ + MTK_PULL_PU_PD_TYPE, /* 186 */ + MTK_PULL_PU_PD_TYPE, /* 187 */ + MTK_PULL_PU_PD_TYPE, /* 188 */ + MTK_PULL_PU_PD_TYPE, /* 189 */ + MTK_PULL_PU_PD_TYPE, /* 190 */ + MTK_PULL_PU_PD_TYPE, /* 191 */ + MTK_PULL_PU_PD_TYPE, /* 192 */ + MTK_PULL_PU_PD_TYPE, /* 193 */ + MTK_PULL_PU_PD_TYPE, /* 194 */ + MTK_PULL_PU_PD_TYPE, /* 195 */ + MTK_PULL_PU_PD_TYPE, /* 196 */ +}; + +static const struct mtk_pin_reg_calc mt6858_reg_cals[PINCTRL_PIN_REG_MAX] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6858_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6858_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6858_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6858_pin_do_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt6858_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt6858_pin_ies_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt6858_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt6858_pin_pd_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt6858_pin_drv_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt6858_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt6858_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt6858_pin_r1_range), + [PINCTRL_PIN_REG_DRV_ADV] = MTK_RANGE(mt6858_pin_drv_adv_range), + [PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt6858_pin_rsel_range), +}; + +static const char * const mt6858_pinctrl_register_base_names[] = { + "base", "lm", "rb", "bm2", "bm", "bm1", "lt", "lt1", "rt", "rt1", +}; + +static const struct mtk_eint_hw mt6858_eint_hw = { + .port_mask = 0xf, + .ports = 3, + .ap_num = 217, + .db_cnt = 36, + .db_time = debounce_time_mt6878, +}; + +static const struct mtk_pin_soc mt6858_data = { + .reg_cal = mt6858_reg_cals, + .pins = mtk_pins_mt6858, + .npins = ARRAY_SIZE(mtk_pins_mt6858), + .ngrps = ARRAY_SIZE(mtk_pins_mt6858), + .eint_hw = &mt6858_eint_hw, + .eint_pin = eint_pins_mt6858, + .nfuncs = 16, + .gpio_m = 0, + .base_names = mt6858_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt6858_pinctrl_register_base_names), + .pull_type = mt6858_pull_type, + .bias_set_combo = mtk_pinconf_bias_set_combo, + .bias_get_combo = mtk_pinconf_bias_get_combo, + .drive_set = mtk_pinconf_drive_set_rev1, + .drive_get = mtk_pinconf_drive_get_rev1, + .adv_drive_get = mtk_pinconf_adv_drive_get_raw, + .adv_drive_set = mtk_pinconf_adv_drive_set_raw, +}; + +static const struct of_device_id mt6858_pinctrl_of_match[] = { + { .compatible = "mediatek,mt6858-pinctrl", .data = &mt6858_data }, + { /* sentinel */ } +}; + +static struct platform_driver mt6858_pinctrl_driver = { + .driver = { + .name = "mt6858-pinctrl", + .of_match_table = mt6858_pinctrl_of_match, + .pm = pm_sleep_ptr(&mtk_paris_pinctrl_pm_ops), + }, + .probe = mtk_paris_pinctrl_probe, +}; + +static int __init mt6858_pinctrl_init(void) +{ + return platform_driver_register(&mt6858_pinctrl_driver); +} +arch_initcall(mt6858_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT6858 Pinctrl Driver"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6858.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6858.h new file mode 100644 index 000000000000..208db809717f --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6858.h @@ -0,0 +1,2378 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2025 MediaTek Inc. + * Alice Chao + * Copyright (c) 2026 Jolla Mobile Ltd + * Nikolai Burov + */ + +#ifndef __PINCTRL_MTK_MT6858_H +#define __PINCTRL_MTK_MT6858_H + +#include "pinctrl-paris.h" + +#define EINT_INVALID_BASE 0xff + +#define MTK_PIN_VEINT(_number) \ + MTK_PIN( \ + _number, "veint" #_number, \ + MTK_EINT_FUNCTION(0, _number), \ + DRV_GRP4, \ + MTK_FUNCTION(0, NULL) \ + ) + +static const struct mtk_pin_desc mtk_pins_mt6858[] = { + MTK_PIN( + 0, "GPIO0", + MTK_EINT_FUNCTION(0, 0), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO0"), + MTK_FUNCTION(1, "TP_GPIO0_AO"), + MTK_FUNCTION(3, "MD_INT0"), + MTK_FUNCTION(5, "SCP_SCL4"), + MTK_FUNCTION(7, "DBG_MON_A0"), + MTK_FUNCTION(8, "IOBIST0") + ), + MTK_PIN( + 1, "GPIO1", + MTK_EINT_FUNCTION(0, 1), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO1"), + MTK_FUNCTION(1, "TP_GPIO1_AO"), + MTK_FUNCTION(2, "SRCLKENA2"), + MTK_FUNCTION(3, "MD_INT3"), + MTK_FUNCTION(4, "SCP_DMIC_CLK"), + MTK_FUNCTION(5, "DMIC_CLK"), + MTK_FUNCTION(6, "SCP_SCL5"), + MTK_FUNCTION(7, "DBG_MON_A1"), + MTK_FUNCTION(8, "IOBIST1") + ), + MTK_PIN( + 2, "GPIO2", + MTK_EINT_FUNCTION(0, 2), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO2"), + MTK_FUNCTION(1, "TP_GPIO2_AO"), + MTK_FUNCTION(3, "MD_INT4"), + MTK_FUNCTION(4, "SCP_DMIC_DAT"), + MTK_FUNCTION(5, "DMIC_DAT"), + MTK_FUNCTION(6, "SCP_SDA5"), + MTK_FUNCTION(7, "DBG_MON_A2"), + MTK_FUNCTION(8, "IOBIST2") + ), + MTK_PIN( + 3, "GPIO3", + MTK_EINT_FUNCTION(0, 3), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO3"), + MTK_FUNCTION(1, "TP_GPIO3_AO"), + MTK_FUNCTION(2, "SPI7_CLK"), + MTK_FUNCTION(3, "TP_UTXD2_VLP"), + MTK_FUNCTION(4, "SSPM_UTXD_AO_VLP"), + MTK_FUNCTION(5, "MD_MCIF_UTXD0"), + MTK_FUNCTION(8, "IOBIST3") + ), + MTK_PIN( + 4, "GPIO4", + MTK_EINT_FUNCTION(0, 4), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO4"), + MTK_FUNCTION(1, "TP_GPIO4_AO"), + MTK_FUNCTION(2, "SPI7_CSB"), + MTK_FUNCTION(3, "TP_URXD2_VLP"), + MTK_FUNCTION(4, "SSPM_URXD_AO_VLP"), + MTK_FUNCTION(5, "MD_MCIF_URXD0"), + MTK_FUNCTION(8, "IOBIST4") + ), + MTK_PIN( + 5, "GPIO5", + MTK_EINT_FUNCTION(0, 5), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO5"), + MTK_FUNCTION(1, "TP_GPIO5_AO"), + MTK_FUNCTION(2, "SPI7_MO"), + MTK_FUNCTION(8, "IOBIST5") + ), + MTK_PIN( + 6, "GPIO6", + MTK_EINT_FUNCTION(0, 6), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO6"), + MTK_FUNCTION(1, "TP_GPIO6_AO"), + MTK_FUNCTION(2, "SPI7_MI"), + MTK_FUNCTION(3, "GPS_PPS"), + MTK_FUNCTION(4, "MD32_0_GPIO0"), + MTK_FUNCTION(8, "IOBIST6") + ), + MTK_PIN( + 7, "GPIO7", + MTK_EINT_FUNCTION(0, 7), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO7"), + MTK_FUNCTION(1, "TP_GPIO7_AO"), + MTK_FUNCTION(2, "SRCLKENA1"), + MTK_FUNCTION(3, "PWM_1"), + MTK_FUNCTION(4, "MD32_1_GPIO0"), + MTK_FUNCTION(5, "SCP_SDA4"), + MTK_FUNCTION(6, "MD_INT4"), + MTK_FUNCTION(8, "IOBIST7") + ), + MTK_PIN( + 8, "GPIO8", + MTK_EINT_FUNCTION(0, 8), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO8"), + MTK_FUNCTION(1, "SSPM_JTAG_TRSTN_VCORE"), + MTK_FUNCTION(2, "SCP_JTAG0_TRSTN_VCORE"), + MTK_FUNCTION(6, "CONN_BGF_MCU_TRST_B"), + MTK_FUNCTION(8, "IOBIST8") + ), + MTK_PIN( + 9, "GPIO9", + MTK_EINT_FUNCTION(0, 9), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO9"), + MTK_FUNCTION(1, "SSPM_JTAG_TCK_VCORE"), + MTK_FUNCTION(2, "SCP_JTAG0_TCK_VCORE"), + MTK_FUNCTION(6, "CONN_BGF_MCU_TCK"), + MTK_FUNCTION(8, "IOBIST9") + ), + MTK_PIN( + 10, "GPIO10", + MTK_EINT_FUNCTION(0, 10), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO10"), + MTK_FUNCTION(1, "SSPM_JTAG_TMS_VCORE"), + MTK_FUNCTION(2, "SCP_JTAG0_TMS_VCORE"), + MTK_FUNCTION(6, "CONN_BGF_MCU_TMS"), + MTK_FUNCTION(8, "IOBIST10") + ), + MTK_PIN( + 11, "GPIO11", + MTK_EINT_FUNCTION(0, 11), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO11"), + MTK_FUNCTION(1, "SSPM_JTAG_TDI_VCORE"), + MTK_FUNCTION(2, "SCP_JTAG0_TDI_VCORE"), + MTK_FUNCTION(6, "CONN_BGF_MCU_TDI"), + MTK_FUNCTION(8, "IOBIST11") + ), + MTK_PIN( + 12, "GPIO12", + MTK_EINT_FUNCTION(0, 12), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO12"), + MTK_FUNCTION(1, "SSPM_JTAG_TDO_VCORE"), + MTK_FUNCTION(2, "SCP_JTAG0_TDO_VCORE"), + MTK_FUNCTION(6, "CONN_BGF_MCU_TDO"), + MTK_FUNCTION(8, "IOBIST12") + ), + MTK_PIN( + 13, "GPIO13", + MTK_EINT_FUNCTION(0, 13), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO13"), + MTK_FUNCTION(1, "TP_GPIO8_AO"), + MTK_FUNCTION(2, "HFRP_JTAG0_TRSTN"), + MTK_FUNCTION(3, "MFG_EB_JTAG_TRSTN"), + MTK_FUNCTION(4, "SSPM_JTAG_TRSTN_VLP"), + MTK_FUNCTION(5, "SPM_JTAG_TRSTN_VLP"), + MTK_FUNCTION(6, "SCP_JTAG0_TRSTN_VLP"), + MTK_FUNCTION(7, "IO_JTAG_TRSTN"), + MTK_FUNCTION(8, "IOBIST13") + ), + MTK_PIN( + 14, "GPIO14", + MTK_EINT_FUNCTION(0, 14), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO14"), + MTK_FUNCTION(1, "TP_GPIO9_AO"), + MTK_FUNCTION(2, "HFRP_JTAG0_TCK"), + MTK_FUNCTION(3, "MFG_EB_JTAG_TCK"), + MTK_FUNCTION(4, "SSPM_JTAG_TCK_VLP"), + MTK_FUNCTION(5, "SPM_JTAG_TCK_VLP"), + MTK_FUNCTION(6, "SCP_JTAG0_TCK_VLP"), + MTK_FUNCTION(7, "IO_JTAG_TCK"), + MTK_FUNCTION(8, "IOBIST14") + ), + MTK_PIN( + 15, "GPIO15", + MTK_EINT_FUNCTION(0, 15), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO15"), + MTK_FUNCTION(1, "TP_GPIO10_AO"), + MTK_FUNCTION(2, "HFRP_JTAG0_TMS"), + MTK_FUNCTION(3, "MFG_EB_JTAG_TMS"), + MTK_FUNCTION(4, "SSPM_JTAG_TMS_VLP"), + MTK_FUNCTION(5, "SPM_JTAG_TMS_VLP"), + MTK_FUNCTION(6, "SCP_JTAG0_TMS_VLP"), + MTK_FUNCTION(7, "IO_JTAG_TMS"), + MTK_FUNCTION(8, "IOBIST15") + ), + MTK_PIN( + 16, "GPIO16", + MTK_EINT_FUNCTION(0, 16), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO16"), + MTK_FUNCTION(1, "TP_GPIO11_AO"), + MTK_FUNCTION(2, "HFRP_JTAG0_TDI"), + MTK_FUNCTION(3, "MFG_EB_JTAG_TDI"), + MTK_FUNCTION(4, "SSPM_JTAG_TDI_VLP"), + MTK_FUNCTION(5, "SPM_JTAG_TDI_VLP"), + MTK_FUNCTION(6, "SCP_JTAG0_TDI_VLP"), + MTK_FUNCTION(7, "IO_JTAG_TDI"), + MTK_FUNCTION(8, "IOBIST16") + ), + MTK_PIN( + 17, "GPIO17", + MTK_EINT_FUNCTION(0, 17), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO17"), + MTK_FUNCTION(1, "TP_GPIO12_AO"), + MTK_FUNCTION(2, "HFRP_JTAG0_TDO"), + MTK_FUNCTION(3, "MFG_EB_JTAG_TDO"), + MTK_FUNCTION(4, "SSPM_JTAG_TDO_VLP"), + MTK_FUNCTION(5, "SPM_JTAG_TDO_VLP"), + MTK_FUNCTION(6, "SCP_JTAG0_TDO_VLP"), + MTK_FUNCTION(7, "IO_JTAG_TDO"), + MTK_FUNCTION(8, "IOBIST17") + ), + MTK_PIN( + 18, "GPIO18", + MTK_EINT_FUNCTION(0, 18), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO18"), + MTK_FUNCTION(1, "MD1_SIM2_SRST"), + MTK_FUNCTION(2, "MD1_SIM1_SRST"), + MTK_FUNCTION(5, "IDDIG"), + MTK_FUNCTION(6, "TSFDC_EN"), + MTK_FUNCTION(8, "IOBIST18") + ), + MTK_PIN( + 19, "GPIO19", + MTK_EINT_FUNCTION(0, 19), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO19"), + MTK_FUNCTION(1, "MD1_SIM2_SCLK"), + MTK_FUNCTION(2, "MD1_SIM1_SCLK"), + MTK_FUNCTION(3, "TP_UTXD2_VCORE"), + MTK_FUNCTION(4, "SSPM_UTXD_AO_VCORE"), + MTK_FUNCTION(5, "MD32_1_TXD"), + MTK_FUNCTION(6, "UTXD2"), + MTK_FUNCTION(8, "IOBIST19") + ), + MTK_PIN( + 20, "GPIO20", + MTK_EINT_FUNCTION(0, 20), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO20"), + MTK_FUNCTION(1, "MD1_SIM2_SIO"), + MTK_FUNCTION(2, "MD1_SIM1_SIO"), + MTK_FUNCTION(3, "TP_URXD2_VCORE"), + MTK_FUNCTION(4, "SSPM_URXD_AO_VCORE"), + MTK_FUNCTION(5, "MD32_1_RXD"), + MTK_FUNCTION(6, "URXD2"), + MTK_FUNCTION(8, "IOBIST20") + ), + MTK_PIN( + 21, "GPIO21", + MTK_EINT_FUNCTION(0, 21), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO21"), + MTK_FUNCTION(1, "KPROW1"), + MTK_FUNCTION(2, "CONN_WIFI_TXD"), + MTK_FUNCTION(3, "CONN_BT_TXD"), + MTK_FUNCTION(4, "HFRP_UTXD1"), + MTK_FUNCTION(5, "TP_UTXD1_VCORE"), + MTK_FUNCTION(6, "CONN_BGF_UART0_TXD"), + MTK_FUNCTION(7, "MD_UTXD1"), + MTK_FUNCTION(8, "IOBIST21") + ), + MTK_PIN( + 22, "GPIO22", + MTK_EINT_FUNCTION(0, 22), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO22"), + MTK_FUNCTION(1, "KPCOL1"), + MTK_FUNCTION(3, "PMSR_SMAP"), + MTK_FUNCTION(4, "HFRP_URXD1"), + MTK_FUNCTION(5, "TP_URXD1_VCORE"), + MTK_FUNCTION(6, "CONN_BGF_UART0_RXD"), + MTK_FUNCTION(7, "MD_URXD1"), + MTK_FUNCTION(8, "IOBIST22") + ), + MTK_PIN( + 23, "GPIO23", + MTK_EINT_FUNCTION(0, 23), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO23"), + MTK_FUNCTION(3, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(5, "USB_DRVVBUS"), + MTK_FUNCTION(7, "DBG_MON_A6"), + MTK_FUNCTION(8, "IOBIST23") + ), + MTK_PIN( + 24, "GPIO24", + MTK_EINT_FUNCTION(0, 24), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO24"), + MTK_FUNCTION(1, "KPROW0"), + MTK_FUNCTION(2, "I2SIN2_MCK"), + MTK_FUNCTION(5, "USB_DRVVBUS"), + MTK_FUNCTION(7, "DBG_MON_B0"), + MTK_FUNCTION(8, "IOBIST24") + ), + MTK_PIN( + 25, "GPIO25", + MTK_EINT_FUNCTION(0, 25), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO25"), + MTK_FUNCTION(4, "PWM_3"), + MTK_FUNCTION(7, "DBG_MON_A8"), + MTK_FUNCTION(8, "IOBIST25") + ), + MTK_PIN( + 26, "GPIO26", + MTK_EINT_FUNCTION(0, 26), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO26"), + MTK_FUNCTION(1, "CMFLASH0"), + MTK_FUNCTION(2, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(3, "MD32_0_GPIO0"), + MTK_FUNCTION(4, "PWM_0"), + MTK_FUNCTION(5, "VBUSVALID"), + MTK_FUNCTION(8, "IOBIST26") + ), + MTK_PIN( + 27, "GPIO27", + MTK_EINT_FUNCTION(0, 27), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO27"), + MTK_FUNCTION(1, "CMFLASH1"), + MTK_FUNCTION(6, "DAP_SONIC_SWCK"), + MTK_FUNCTION(7, "DBG_MON_A10"), + MTK_FUNCTION(8, "IOBIST27") + ), + MTK_PIN( + 28, "GPIO28", + MTK_EINT_FUNCTION(0, 28), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO28"), + MTK_FUNCTION(1, "CMFLASH2"), + MTK_FUNCTION(4, "GPS_PPS"), + MTK_FUNCTION(6, "DAP_SONIC_SWD"), + MTK_FUNCTION(7, "DBG_MON_A11"), + MTK_FUNCTION(8, "IOBIST28") + ), + MTK_PIN( + 29, "GPIO29", + MTK_EINT_FUNCTION(0, 29), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO29"), + MTK_FUNCTION(1, "CMFLASH3"), + MTK_FUNCTION(3, "SCL10"), + MTK_FUNCTION(6, "DAP_MD32_SWCK"), + MTK_FUNCTION(7, "DBG_MON_A12"), + MTK_FUNCTION(8, "IOBIST29") + ), + MTK_PIN( + 30, "GPIO30", + MTK_EINT_FUNCTION(0, 30), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO30"), + MTK_FUNCTION(3, "SDA10"), + MTK_FUNCTION(6, "DAP_MD32_SWD"), + MTK_FUNCTION(7, "DBG_MON_A13"), + MTK_FUNCTION(8, "IOBIST30") + ), + MTK_PIN( + 31, "GPIO31", + MTK_EINT_FUNCTION(0, 31), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO31"), + MTK_FUNCTION(1, "CMVREF0"), + MTK_FUNCTION(3, "SCL12"), + MTK_FUNCTION(7, "DBG_MON_A14"), + MTK_FUNCTION(8, "IOBIST31") + ), + MTK_PIN( + 32, "GPIO32", + MTK_EINT_FUNCTION(0, 32), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO32"), + MTK_FUNCTION(1, "CMVREF1"), + MTK_FUNCTION(3, "SDA12"), + MTK_FUNCTION(7, "DBG_MON_A15"), + MTK_FUNCTION(8, "IOBIST32") + ), + MTK_PIN( + 33, "GPIO33", + MTK_EINT_FUNCTION(0, 33), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO33"), + MTK_FUNCTION(1, "CMVREF2"), + MTK_FUNCTION(3, "USB_DRVVBUS"), + MTK_FUNCTION(7, "DBG_MON_A16"), + MTK_FUNCTION(8, "IOBIST33") + ), + MTK_PIN( + 34, "GPIO34", + MTK_EINT_FUNCTION(0, 34), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO34"), + MTK_FUNCTION(1, "CMVREF3"), + MTK_FUNCTION(3, "VBUSVALID"), + MTK_FUNCTION(7, "DBG_MON_A17"), + MTK_FUNCTION(8, "IOBIST34") + ), + MTK_PIN( + 35, "GPIO35", + MTK_EINT_FUNCTION(0, 35), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO35"), + MTK_FUNCTION(1, "CMVREF4"), + MTK_FUNCTION(3, "IDDIG"), + MTK_FUNCTION(7, "DBG_MON_A18"), + MTK_FUNCTION(8, "IOBIST35") + ), + MTK_PIN( + 36, "GPIO36", + MTK_EINT_FUNCTION(0, 36), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO36"), + MTK_FUNCTION(1, "CMMCLK0"), + MTK_FUNCTION(2, "CLKM0"), + MTK_FUNCTION(7, "DBG_MON_A19"), + MTK_FUNCTION(8, "IOBIST36") + ), + MTK_PIN( + 37, "GPIO37", + MTK_EINT_FUNCTION(0, 37), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO37"), + MTK_FUNCTION(1, "CMMCLK1"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(4, "MD32_1_GPIO0"), + MTK_FUNCTION(7, "DBG_MON_A20"), + MTK_FUNCTION(8, "IOBIST37") + ), + MTK_PIN( + 38, "GPIO38", + MTK_EINT_FUNCTION(0, 38), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO38"), + MTK_FUNCTION(1, "CMMCLK2"), + MTK_FUNCTION(2, "CLKM2"), + MTK_FUNCTION(7, "DBG_MON_A21"), + MTK_FUNCTION(8, "IOBIST38") + ), + MTK_PIN( + 39, "GPIO39", + MTK_EINT_FUNCTION(0, 39), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO39"), + MTK_FUNCTION(1, "CMMCLK3"), + MTK_FUNCTION(2, "CLKM3"), + MTK_FUNCTION(7, "DBG_MON_A22"), + MTK_FUNCTION(8, "IOBIST39") + ), + MTK_PIN( + 40, "GPIO40", + MTK_EINT_FUNCTION(0, 40), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO40"), + MTK_FUNCTION(1, "I2SIN1_MCK"), + MTK_FUNCTION(2, "IDDIG"), + MTK_FUNCTION(3, "IRRX_IN"), + MTK_FUNCTION(4, "GPS_PPS"), + MTK_FUNCTION(6, "ANT_SEL8"), + MTK_FUNCTION(8, "IOBIST40") + ), + MTK_PIN( + 41, "GPIO41", + MTK_EINT_FUNCTION(0, 41), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO41"), + MTK_FUNCTION(1, "I2SIN1_BCK"), + MTK_FUNCTION(4, "CONN_WF_MCU_AICE_TMSC"), + MTK_FUNCTION(6, "ANT_SEL9"), + MTK_FUNCTION(8, "IOBIST41") + ), + MTK_PIN( + 42, "GPIO42", + MTK_EINT_FUNCTION(0, 42), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO42"), + MTK_FUNCTION(1, "I2SIN1_LRCK"), + MTK_FUNCTION(4, "CONN_WF_MCU_AICE_TCKC"), + MTK_FUNCTION(6, "ANT_SEL10"), + MTK_FUNCTION(8, "IOBIST42") + ), + MTK_PIN( + 43, "GPIO43", + MTK_EINT_FUNCTION(0, 43), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO43"), + MTK_FUNCTION(1, "I2SOUT1_DO"), + MTK_FUNCTION(4, "CONN_BGF_MCU_AICE_TMSC"), + MTK_FUNCTION(6, "ANT_SEL11"), + MTK_FUNCTION(8, "IOBIST43") + ), + MTK_PIN( + 44, "GPIO44", + MTK_EINT_FUNCTION(0, 44), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO44"), + MTK_FUNCTION(1, "I2SIN1_DI"), + MTK_FUNCTION(4, "CONN_BGF_MCU_AICE_TCKC"), + MTK_FUNCTION(6, "ANT_SEL12"), + MTK_FUNCTION(8, "IOBIST44") + ), + MTK_PIN( + 45, "GPIO45", + MTK_EINT_FUNCTION(0, 45), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO45"), + MTK_FUNCTION(1, "I2SIN2_BCK"), + MTK_FUNCTION(2, "SCL11"), + MTK_FUNCTION(3, "BPI_BUS10"), + MTK_FUNCTION(4, "MD_UCTS0"), + MTK_FUNCTION(5, "TP_UCTS1_VCORE"), + MTK_FUNCTION(6, "HFRP_UCTS1"), + MTK_FUNCTION(7, "DBG_MON_B1"), + MTK_FUNCTION(8, "IOBIST45") + ), + MTK_PIN( + 46, "GPIO46", + MTK_EINT_FUNCTION(0, 46), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO46"), + MTK_FUNCTION(1, "I2SIN2_LRCK"), + MTK_FUNCTION(2, "SDA11"), + MTK_FUNCTION(3, "BPI_BUS11"), + MTK_FUNCTION(4, "MD_URTS0"), + MTK_FUNCTION(5, "TP_URTS1_VCORE"), + MTK_FUNCTION(6, "HFRP_URTS1"), + MTK_FUNCTION(7, "DBG_MON_B2"), + MTK_FUNCTION(8, "IOBIST46") + ), + MTK_PIN( + 47, "GPIO47", + MTK_EINT_FUNCTION(0, 47), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO47"), + MTK_FUNCTION(1, "I2SOUT2_DO"), + MTK_FUNCTION(2, "SCL1"), + MTK_FUNCTION(3, "BPI_BUS12"), + MTK_FUNCTION(4, "MD_UCTS1"), + MTK_FUNCTION(5, "TP_UCTS2_VCORE"), + MTK_FUNCTION(6, "UCTS2"), + MTK_FUNCTION(7, "DBG_MON_B3"), + MTK_FUNCTION(8, "IOBIST47") + ), + MTK_PIN( + 48, "GPIO48", + MTK_EINT_FUNCTION(0, 48), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO48"), + MTK_FUNCTION(1, "I2SIN2_DI"), + MTK_FUNCTION(2, "SDA1"), + MTK_FUNCTION(3, "BPI_BUS13"), + MTK_FUNCTION(4, "MD_URTS1"), + MTK_FUNCTION(5, "TP_URTS2_VCORE"), + MTK_FUNCTION(6, "URTS2"), + MTK_FUNCTION(7, "DBG_MON_B4"), + MTK_FUNCTION(8, "IOBIST48") + ), + MTK_PIN( + 49, "GPIO49", + MTK_EINT_FUNCTION(0, 49), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO49"), + MTK_FUNCTION(1, "UTXD0"), + MTK_FUNCTION(2, "MBISTREADEN_TRIGGER"), + MTK_FUNCTION(3, "MD_UTXD1"), + MTK_FUNCTION(4, "HFRP_UTXD1"), + MTK_FUNCTION(5, "MD32_0_TXD"), + MTK_FUNCTION(6, "PTA_TXD"), + MTK_FUNCTION(8, "IOBIST49") + ), + MTK_PIN( + 50, "GPIO50", + MTK_EINT_FUNCTION(0, 50), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO50"), + MTK_FUNCTION(1, "URXD0"), + MTK_FUNCTION(2, "MBISTWRITEEN_TRIGGER"), + MTK_FUNCTION(3, "MD_URXD1"), + MTK_FUNCTION(4, "HFRP_URXD1"), + MTK_FUNCTION(5, "MD32_0_RXD"), + MTK_FUNCTION(6, "PTA_RXD"), + MTK_FUNCTION(8, "IOBIST50") + ), + MTK_PIN( + 51, "GPIO51", + MTK_EINT_FUNCTION(0, 51), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO51"), + MTK_FUNCTION(1, "UTXD1"), + MTK_FUNCTION(2, "TP_UTXD1_VLP"), + MTK_FUNCTION(3, "TP_UTXD2_VLP"), + MTK_FUNCTION(4, "CONN_BGF_UART0_TXD"), + MTK_FUNCTION(5, "SSPM_UTXD_AO_VLP"), + MTK_FUNCTION(6, "MD_MCIF_UTXD0"), + MTK_FUNCTION(7, "MD_UTXD0"), + MTK_FUNCTION(8, "IOBIST51") + ), + MTK_PIN( + 52, "GPIO52", + MTK_EINT_FUNCTION(0, 52), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO52"), + MTK_FUNCTION(1, "URXD1"), + MTK_FUNCTION(2, "TP_URXD1_VLP"), + MTK_FUNCTION(3, "TP_URXD2_VLP"), + MTK_FUNCTION(4, "CONN_BGF_UART0_RXD"), + MTK_FUNCTION(5, "SSPM_URXD_AO_VLP"), + MTK_FUNCTION(6, "MD_MCIF_URXD0"), + MTK_FUNCTION(7, "MD_URXD0"), + MTK_FUNCTION(8, "IOBIST52") + ), + MTK_PIN( + 53, "GPIO53", + MTK_EINT_FUNCTION(0, 53), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO53"), + MTK_FUNCTION(1, "JTRSTN_SEL1_VCORE"), + MTK_FUNCTION(2, "SPM_JTAG_TRSTN_VCORE"), + MTK_FUNCTION(8, "IOBIST53") + ), + MTK_PIN( + 54, "GPIO54", + MTK_EINT_FUNCTION(0, 54), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO54"), + MTK_FUNCTION(1, "JTCK_SEL1_VCORE"), + MTK_FUNCTION(2, "SPM_JTAG_TCK_VCORE"), + MTK_FUNCTION(8, "IOBIST54") + ), + MTK_PIN( + 55, "GPIO55", + MTK_EINT_FUNCTION(0, 55), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO55"), + MTK_FUNCTION(1, "JTMS_SEL1_VCORE"), + MTK_FUNCTION(2, "SPM_JTAG_TMS_VCORE"), + MTK_FUNCTION(8, "IOBIST55") + ), + MTK_PIN( + 56, "GPIO56", + MTK_EINT_FUNCTION(0, 56), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO56"), + MTK_FUNCTION(1, "JTDI_SEL1_VCORE"), + MTK_FUNCTION(2, "SPM_JTAG_TDI_VCORE"), + MTK_FUNCTION(8, "IOBIST56") + ), + MTK_PIN( + 57, "GPIO57", + MTK_EINT_FUNCTION(0, 57), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO57"), + MTK_FUNCTION(1, "JTDO_SEL1_VCORE"), + MTK_FUNCTION(2, "SPM_JTAG_TDO_VCORE"), + MTK_FUNCTION(8, "IOBIST57") + ), + MTK_PIN( + 58, "GPIO58", + MTK_EINT_FUNCTION(0, 58), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO58"), + MTK_FUNCTION(1, "SPI4_CLK"), + MTK_FUNCTION(2, "MD_UTXD0"), + MTK_FUNCTION(3, "UTXD2"), + MTK_FUNCTION(4, "TP_UTXD1_VCORE"), + MTK_FUNCTION(5, "MBISTREADEN_TRIGGER"), + MTK_FUNCTION(6, "EXTIF0_ACT"), + MTK_FUNCTION(7, "DAP_SONIC_SWCK"), + MTK_FUNCTION(8, "IOBIST58") + ), + MTK_PIN( + 59, "GPIO59", + MTK_EINT_FUNCTION(0, 59), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO59"), + MTK_FUNCTION(1, "SPI4_CSB"), + MTK_FUNCTION(2, "MD_URXD0"), + MTK_FUNCTION(3, "URXD2"), + MTK_FUNCTION(4, "TP_URXD1_VCORE"), + MTK_FUNCTION(5, "MBISTWRITEEN_TRIGGER"), + MTK_FUNCTION(6, "EXTIF0_PRI"), + MTK_FUNCTION(7, "DAP_SONIC_SWD"), + MTK_FUNCTION(8, "IOBIST59") + ), + MTK_PIN( + 60, "GPIO60", + MTK_EINT_FUNCTION(0, 60), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO60"), + MTK_FUNCTION(1, "SPI4_MO"), + MTK_FUNCTION(6, "EXTIF0_GNT_B"), + MTK_FUNCTION(7, "DAP_MD32_SWCK"), + MTK_FUNCTION(8, "IOBIST60") + ), + MTK_PIN( + 61, "GPIO61", + MTK_EINT_FUNCTION(0, 61), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO61"), + MTK_FUNCTION(1, "SPI4_MI"), + MTK_FUNCTION(7, "DAP_MD32_SWD"), + MTK_FUNCTION(8, "IOBIST61") + ), + MTK_PIN( + 62, "GPIO62", + MTK_EINT_FUNCTION(0, 62), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO62"), + MTK_FUNCTION(1, "SCP_SPI1_CK"), + MTK_FUNCTION(2, "SPI1_CLK"), + MTK_FUNCTION(3, "TP_UTXD1_VLP"), + MTK_FUNCTION(5, "TP_GPIO0_AO"), + MTK_FUNCTION(6, "UTXD0"), + MTK_FUNCTION(7, "DBG_MON_A25"), + MTK_FUNCTION(8, "IOBIST62") + ), + MTK_PIN( + 63, "GPIO63", + MTK_EINT_FUNCTION(0, 63), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO63"), + MTK_FUNCTION(1, "SCP_SPI1_CS"), + MTK_FUNCTION(2, "SPI1_CSB"), + MTK_FUNCTION(3, "TP_URXD1_VLP"), + MTK_FUNCTION(5, "TP_GPIO1_AO"), + MTK_FUNCTION(6, "URXD0"), + MTK_FUNCTION(7, "DBG_MON_A26"), + MTK_FUNCTION(8, "IOBIST63") + ), + MTK_PIN( + 64, "GPIO64", + MTK_EINT_FUNCTION(0, 64), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO64"), + MTK_FUNCTION(1, "SCP_SPI1_MO"), + MTK_FUNCTION(2, "SPI1_MO"), + MTK_FUNCTION(5, "TP_GPIO2_AO"), + MTK_FUNCTION(7, "DBG_MON_A9"), + MTK_FUNCTION(8, "IOBIST64") + ), + MTK_PIN( + 65, "GPIO65", + MTK_EINT_FUNCTION(0, 65), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO65"), + MTK_FUNCTION(1, "SCP_SPI1_MI"), + MTK_FUNCTION(2, "SPI1_MI"), + MTK_FUNCTION(5, "TP_GPIO3_AO"), + MTK_FUNCTION(8, "IOBIST65") + ), + MTK_PIN( + 66, "GPIO66", + MTK_EINT_FUNCTION(0, 66), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO66"), + MTK_FUNCTION(1, "SCP_SPI2_CK"), + MTK_FUNCTION(2, "SPI2_CLK"), + MTK_FUNCTION(5, "TP_GPIO4_AO"), + MTK_FUNCTION(6, "UTXD1"), + MTK_FUNCTION(7, "DBG_MON_B13"), + MTK_FUNCTION(8, "IOBIST66") + ), + MTK_PIN( + 67, "GPIO67", + MTK_EINT_FUNCTION(0, 67), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO67"), + MTK_FUNCTION(1, "SCP_SPI2_CS"), + MTK_FUNCTION(2, "SPI2_CSB"), + MTK_FUNCTION(5, "TP_GPIO5_AO"), + MTK_FUNCTION(6, "URXD1"), + MTK_FUNCTION(7, "DBG_MON_B14"), + MTK_FUNCTION(8, "IOBIST67") + ), + MTK_PIN( + 68, "GPIO68", + MTK_EINT_FUNCTION(0, 68), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO68"), + MTK_FUNCTION(1, "SCP_SPI2_MO"), + MTK_FUNCTION(2, "SPI2_MO"), + MTK_FUNCTION(5, "TP_GPIO6_AO"), + MTK_FUNCTION(7, "DBG_MON_B15"), + MTK_FUNCTION(8, "IOBIST68") + ), + MTK_PIN( + 69, "GPIO69", + MTK_EINT_FUNCTION(0, 69), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO69"), + MTK_FUNCTION(1, "SCP_SPI2_MI"), + MTK_FUNCTION(2, "SPI2_MI"), + MTK_FUNCTION(5, "TP_GPIO7_AO"), + MTK_FUNCTION(7, "DBG_MON_B16"), + MTK_FUNCTION(8, "IOBIST69") + ), + MTK_PIN( + 70, "GPIO70", + MTK_EINT_FUNCTION(0, 70), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO70"), + MTK_FUNCTION(1, "SCP_SPI3_CK"), + MTK_FUNCTION(2, "SPI3_CLK"), + MTK_FUNCTION(3, "MD_INT4"), + MTK_FUNCTION(5, "TP_GPIO8_AO"), + MTK_FUNCTION(7, "DBG_MON_B17"), + MTK_FUNCTION(8, "IOBIST70") + ), + MTK_PIN( + 71, "GPIO71", + MTK_EINT_FUNCTION(0, 71), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO71"), + MTK_FUNCTION(1, "SCP_SPI3_CS"), + MTK_FUNCTION(2, "SPI3_CSB"), + MTK_FUNCTION(3, "MD_INT3"), + MTK_FUNCTION(5, "TP_GPIO9_AO"), + MTK_FUNCTION(7, "DBG_MON_B18"), + MTK_FUNCTION(8, "IOBIST71") + ), + MTK_PIN( + 72, "GPIO72", + MTK_EINT_FUNCTION(0, 72), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO72"), + MTK_FUNCTION(1, "SCP_SPI3_MO"), + MTK_FUNCTION(2, "SPI3_MO"), + MTK_FUNCTION(5, "TP_GPIO10_AO"), + MTK_FUNCTION(7, "DBG_MON_B19"), + MTK_FUNCTION(8, "IOBIST72") + ), + MTK_PIN( + 73, "GPIO73", + MTK_EINT_FUNCTION(0, 73), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO73"), + MTK_FUNCTION(1, "SCP_SPI3_MI"), + MTK_FUNCTION(2, "SPI3_MI"), + MTK_FUNCTION(5, "TP_GPIO11_AO"), + MTK_FUNCTION(7, "DBG_MON_B20"), + MTK_FUNCTION(8, "IOBIST73") + ), + MTK_PIN( + 74, "GPIO74", + MTK_EINT_FUNCTION(0, 74), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO74"), + MTK_FUNCTION(1, "SCP_SPI0_CK"), + MTK_FUNCTION(2, "SPI0_CLK"), + MTK_FUNCTION(3, "MD_INT0"), + MTK_FUNCTION(4, "BPI_BUS14"), + MTK_FUNCTION(5, "TP_GPIO12_AO"), + MTK_FUNCTION(7, "DBG_MON_B5"), + MTK_FUNCTION(8, "IOBIST74") + ), + MTK_PIN( + 75, "GPIO75", + MTK_EINT_FUNCTION(0, 75), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO75"), + MTK_FUNCTION(1, "SCP_SPI0_CS"), + MTK_FUNCTION(2, "SPI0_CSB"), + MTK_FUNCTION(4, "BPI_BUS15"), + MTK_FUNCTION(5, "TP_GPIO13_AO"), + MTK_FUNCTION(7, "DBG_MON_B6"), + MTK_FUNCTION(8, "IOBIST75") + ), + MTK_PIN( + 76, "GPIO76", + MTK_EINT_FUNCTION(0, 76), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO76"), + MTK_FUNCTION(1, "SCP_SPI0_MO"), + MTK_FUNCTION(2, "SPI0_MO"), + MTK_FUNCTION(4, "BPI_BUS16"), + MTK_FUNCTION(5, "TP_GPIO14_AO"), + MTK_FUNCTION(7, "DBG_MON_B7"), + MTK_FUNCTION(8, "IOBIST76") + ), + MTK_PIN( + 77, "GPIO77", + MTK_EINT_FUNCTION(0, 77), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO77"), + MTK_FUNCTION(1, "SCP_SPI0_MI"), + MTK_FUNCTION(2, "SPI0_MI"), + MTK_FUNCTION(4, "BPI_BUS17"), + MTK_FUNCTION(5, "TP_GPIO15_AO"), + MTK_FUNCTION(7, "DBG_MON_B8"), + MTK_FUNCTION(8, "IOBIST77") + ), + MTK_PIN( + 78, "GPIO78", + MTK_EINT_FUNCTION(0, 78), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO78"), + MTK_FUNCTION(1, "SPI5_CLK"), + MTK_FUNCTION(2, "MD32_0_TXD"), + MTK_FUNCTION(3, "PTA_TXD"), + MTK_FUNCTION(4, "TP_UTXD2_VCORE"), + MTK_FUNCTION(5, "SSPM_UTXD_AO_VCORE"), + MTK_FUNCTION(6, "UTXD2"), + MTK_FUNCTION(7, "DBG_MON_B21"), + MTK_FUNCTION(8, "IOBIST78") + ), + MTK_PIN( + 79, "GPIO79", + MTK_EINT_FUNCTION(0, 79), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO79"), + MTK_FUNCTION(1, "SPI5_CSB"), + MTK_FUNCTION(2, "MD32_0_RXD"), + MTK_FUNCTION(3, "PTA_RXD"), + MTK_FUNCTION(4, "TP_URXD2_VCORE"), + MTK_FUNCTION(5, "SSPM_URXD_AO_VCORE"), + MTK_FUNCTION(6, "URXD2"), + MTK_FUNCTION(7, "DBG_MON_B22"), + MTK_FUNCTION(8, "IOBIST79") + ), + MTK_PIN( + 80, "GPIO80", + MTK_EINT_FUNCTION(0, 80), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO80"), + MTK_FUNCTION(1, "SPI5_MO"), + MTK_FUNCTION(7, "DBG_MON_B23"), + MTK_FUNCTION(8, "IOBIST80") + ), + MTK_PIN( + 81, "GPIO81", + MTK_EINT_FUNCTION(0, 81), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO81"), + MTK_FUNCTION(1, "SPI5_MI"), + MTK_FUNCTION(7, "DBG_MON_B24"), + MTK_FUNCTION(8, "IOBIST81") + ), + MTK_PIN( + 82, "GPIO82", + MTK_EINT_FUNCTION(0, 82), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO82"), + MTK_FUNCTION(1, "MSDC1_CLK"), + MTK_FUNCTION(2, "MFG_EB_JTAG_TCK"), + MTK_FUNCTION(3, "UDI_TCK"), + MTK_FUNCTION(4, "CONN_DSP_JCK"), + MTK_FUNCTION(8, "IOBIST82") + ), + MTK_PIN( + 83, "GPIO83", + MTK_EINT_FUNCTION(0, 83), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO83"), + MTK_FUNCTION(1, "MSDC1_CMD"), + MTK_FUNCTION(2, "MFG_EB_JTAG_TMS"), + MTK_FUNCTION(3, "UDI_TMS"), + MTK_FUNCTION(4, "CONN_DSP_JMS"), + MTK_FUNCTION(6, "TSFDC_VCO_RST"), + MTK_FUNCTION(8, "IOBIST83") + ), + MTK_PIN( + 84, "GPIO84", + MTK_EINT_FUNCTION(0, 84), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO84"), + MTK_FUNCTION(1, "MSDC1_DAT0"), + MTK_FUNCTION(2, "MFG_EB_JTAG_TDI"), + MTK_FUNCTION(3, "UDI_TDI"), + MTK_FUNCTION(4, "CONN_DSP_JDI"), + MTK_FUNCTION(6, "TSFDC_TSSEL2"), + MTK_FUNCTION(8, "IOBIST84") + ), + MTK_PIN( + 85, "GPIO85", + MTK_EINT_FUNCTION(0, 85), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO85"), + MTK_FUNCTION(1, "MSDC1_DAT1"), + MTK_FUNCTION(2, "MFG_EB_JTAG_TDO"), + MTK_FUNCTION(3, "UDI_TDO"), + MTK_FUNCTION(4, "CONN_DSP_JDO"), + MTK_FUNCTION(6, "TSFDC_TSSEL1"), + MTK_FUNCTION(8, "IOBIST85") + ), + MTK_PIN( + 86, "GPIO86", + MTK_EINT_FUNCTION(0, 86), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO86"), + MTK_FUNCTION(1, "MSDC1_DAT2"), + MTK_FUNCTION(2, "MFG_EB_JTAG_TRSTN"), + MTK_FUNCTION(3, "UDI_NTRST"), + MTK_FUNCTION(6, "TSFDC_TSSEL0"), + MTK_FUNCTION(8, "IOBIST86") + ), + MTK_PIN( + 87, "GPIO87", + MTK_EINT_FUNCTION(0, 87), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO87"), + MTK_FUNCTION(1, "MSDC1_DAT3"), + MTK_FUNCTION(2, "IRRX_IN"), + MTK_FUNCTION(4, "CONN_DSP_JINTP"), + MTK_FUNCTION(6, "TSFDC_RCK_SELB"), + MTK_FUNCTION(8, "IOBIST87") + ), + MTK_PIN( + 88, "GPIO88", + MTK_EINT_FUNCTION(0, 88), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO88"), + MTK_FUNCTION(1, "MD1_SIM1_SCLK"), + MTK_FUNCTION(2, "MD1_SIM2_SCLK"), + MTK_FUNCTION(4, "CONN_DSP_L5_JINTP"), + MTK_FUNCTION(6, "TSFDC_26M"), + MTK_FUNCTION(8, "IOBIST88") + ), + MTK_PIN( + 89, "GPIO89", + MTK_EINT_FUNCTION(0, 89), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO89"), + MTK_FUNCTION(1, "MD1_SIM1_SRST"), + MTK_FUNCTION(2, "MD1_SIM2_SRST"), + MTK_FUNCTION(3, "SPM_JTAG_TRSTN_VCORE"), + MTK_FUNCTION(5, "MCUPM_JTAG_TRSTN"), + MTK_FUNCTION(6, "TSFDC_SDO"), + MTK_FUNCTION(8, "IOBIST89") + ), + MTK_PIN( + 90, "GPIO90", + MTK_EINT_FUNCTION(0, 90), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO90"), + MTK_FUNCTION(1, "MD1_SIM1_SIO"), + MTK_FUNCTION(2, "MD1_SIM2_SIO"), + MTK_FUNCTION(3, "SPM_JTAG_TCK_VCORE"), + MTK_FUNCTION(4, "CONN_DSP_L5_JCK"), + MTK_FUNCTION(5, "MCUPM_JTAG_TCK"), + MTK_FUNCTION(6, "TSFDC_FOUT"), + MTK_FUNCTION(8, "IOBIST90") + ), + MTK_PIN( + 91, "GPIO91", + MTK_EINT_FUNCTION(0, 91), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO91"), + MTK_FUNCTION(1, "MD1_SIM2_SCLK"), + MTK_FUNCTION(2, "MD1_SIM1_SCLK"), + MTK_FUNCTION(3, "SPM_JTAG_TMS_VCORE"), + MTK_FUNCTION(4, "CONN_DSP_L5_JMS"), + MTK_FUNCTION(5, "MCUPM_JTAG_TMS"), + MTK_FUNCTION(6, "TSFDC_SCK"), + MTK_FUNCTION(8, "IOBIST91") + ), + MTK_PIN( + 92, "GPIO92", + MTK_EINT_FUNCTION(0, 92), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO92"), + MTK_FUNCTION(1, "MD1_SIM2_SRST"), + MTK_FUNCTION(2, "MD1_SIM1_SRST"), + MTK_FUNCTION(3, "SPM_JTAG_TDI_VCORE"), + MTK_FUNCTION(4, "CONN_DSP_L5_JDI"), + MTK_FUNCTION(5, "MCUPM_JTAG_TDI"), + MTK_FUNCTION(6, "TSFDC_SDI"), + MTK_FUNCTION(8, "IOBIST92") + ), + MTK_PIN( + 93, "GPIO93", + MTK_EINT_FUNCTION(0, 93), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO93"), + MTK_FUNCTION(1, "MD1_SIM2_SIO"), + MTK_FUNCTION(2, "MD1_SIM1_SIO"), + MTK_FUNCTION(3, "SPM_JTAG_TDO_VCORE"), + MTK_FUNCTION(4, "CONN_DSP_L5_JDO"), + MTK_FUNCTION(5, "MCUPM_JTAG_TDO"), + MTK_FUNCTION(6, "TSFDC_SCF"), + MTK_FUNCTION(8, "IOBIST93") + ), + MTK_PIN( + 94, "GPIO94", + MTK_EINT_FUNCTION(0, 94), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO94"), + MTK_FUNCTION(1, "MD_INT1_C2K_UIM0_HOT_PLUG"), + MTK_FUNCTION(2, "MD_INT2_C2K_UIM1_HOT_PLUG"), + MTK_FUNCTION(3, "SRCLKENAI0"), + MTK_FUNCTION(6, "MD_MCIF_UTXD0"), + MTK_FUNCTION(8, "IOBIST94") + ), + MTK_PIN( + 95, "GPIO95", + MTK_EINT_FUNCTION(0, 95), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO95"), + MTK_FUNCTION(1, "MD_INT2_C2K_UIM1_HOT_PLUG"), + MTK_FUNCTION(2, "MD_INT1_C2K_UIM0_HOT_PLUG"), + MTK_FUNCTION(3, "SRCLKENAI1"), + MTK_FUNCTION(4, "SRCLKENA1"), + MTK_FUNCTION(6, "MD_MCIF_URXD0"), + MTK_FUNCTION(8, "IOBIST95") + ), + MTK_PIN( + 96, "GPIO96", + MTK_EINT_FUNCTION(0, 96), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO96"), + MTK_FUNCTION(1, "DSI_TE"), + MTK_FUNCTION(7, "DBG_MON_B25"), + MTK_FUNCTION(8, "IOBIST96") + ), + MTK_PIN( + 97, "GPIO97", + MTK_EINT_FUNCTION(0, 97), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO97"), + MTK_FUNCTION(1, "LCM_RST"), + MTK_FUNCTION(7, "DBG_MON_B26"), + MTK_FUNCTION(8, "IOBIST97") + ), + MTK_PIN( + 98, "GPIO98", + MTK_EINT_FUNCTION(0, 98), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO98"), + MTK_FUNCTION(1, "DISP_PWM"), + MTK_FUNCTION(2, "PWM_2"), + MTK_FUNCTION(7, "DBG_MON_B27"), + MTK_FUNCTION(8, "IOBIST98") + ), + MTK_PIN( + 99, "GPIO99", + MTK_EINT_FUNCTION(0, 99), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO99"), + MTK_FUNCTION(1, "ANT_SEL0"), + MTK_FUNCTION(2, "CONN_BPI_BUS17_ANT0"), + MTK_FUNCTION(3, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(4, "EXT_FRAME_SYNC"), + MTK_FUNCTION(5, "SCL6"), + MTK_FUNCTION(8, "IOBIST99") + ), + MTK_PIN( + 100, "GPIO100", + MTK_EINT_FUNCTION(0, 100), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO100"), + MTK_FUNCTION(1, "ANT_SEL1"), + MTK_FUNCTION(2, "CONN_BPI_BUS18_ANT1"), + MTK_FUNCTION(3, "GPS_L5_ELNA_EN"), + MTK_FUNCTION(4, "AGPS_SYNC"), + MTK_FUNCTION(5, "SDA6"), + MTK_FUNCTION(8, "IOBIST100") + ), + MTK_PIN( + 101, "GPIO101", + MTK_EINT_FUNCTION(0, 101), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO101"), + MTK_FUNCTION(1, "ANT_SEL2"), + MTK_FUNCTION(2, "CONN_BPI_BUS19_ANT2"), + MTK_FUNCTION(3, "UDI_NTRST"), + MTK_FUNCTION(4, "CONN_WF_MCU_TRST_B"), + MTK_FUNCTION(8, "IOBIST101") + ), + MTK_PIN( + 102, "GPIO102", + MTK_EINT_FUNCTION(0, 102), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO102"), + MTK_FUNCTION(1, "ANT_SEL3"), + MTK_FUNCTION(2, "CONN_BPI_BUS20_ANT3"), + MTK_FUNCTION(3, "UDI_TCK"), + MTK_FUNCTION(4, "CONN_WF_MCU_TCK"), + MTK_FUNCTION(8, "IOBIST102") + ), + MTK_PIN( + 103, "GPIO103", + MTK_EINT_FUNCTION(0, 103), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO103"), + MTK_FUNCTION(1, "ANT_SEL4"), + MTK_FUNCTION(2, "CONN_BPI_BUS21_ANT4"), + MTK_FUNCTION(3, "UDI_TMS"), + MTK_FUNCTION(4, "CONN_WF_MCU_TMS"), + MTK_FUNCTION(8, "IOBIST103") + ), + MTK_PIN( + 104, "GPIO104", + MTK_EINT_FUNCTION(0, 104), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO104"), + MTK_FUNCTION(1, "ANT_SEL5"), + MTK_FUNCTION(2, "CONN_BPI_BUS16_OLAT5"), + MTK_FUNCTION(3, "UDI_TDI"), + MTK_FUNCTION(4, "CONN_WF_MCU_TDI"), + MTK_FUNCTION(8, "IOBIST104") + ), + MTK_PIN( + 105, "GPIO105", + MTK_EINT_FUNCTION(0, 105), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO105"), + MTK_FUNCTION(1, "ANT_SEL6"), + MTK_FUNCTION(2, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(3, "UDI_TDO"), + MTK_FUNCTION(4, "CONN_WF_MCU_TDO"), + MTK_FUNCTION(8, "IOBIST105") + ), + MTK_PIN( + 106, "GPIO106", + MTK_EINT_FUNCTION(0, 106), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO106"), + MTK_FUNCTION(1, "BPI_BUS0"), + MTK_FUNCTION(2, "CONN_BPI_BUS10"), + MTK_FUNCTION(4, "MFG_TSFDC_EN"), + MTK_FUNCTION(5, "I2SOUT4_DATA0"), + MTK_FUNCTION(6, "ANT_SEL7"), + MTK_FUNCTION(8, "IOBIST106") + ), + MTK_PIN( + 107, "GPIO107", + MTK_EINT_FUNCTION(0, 107), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO107"), + MTK_FUNCTION(1, "BPI_BUS1"), + MTK_FUNCTION(2, "CONN_BPI_BUS11_OLAT0"), + MTK_FUNCTION(4, "MFG_TSFDC_VCO_RST"), + MTK_FUNCTION(5, "I2SOUT4_DATA1"), + MTK_FUNCTION(6, "ANT_SEL8"), + MTK_FUNCTION(8, "IOBIST107") + ), + MTK_PIN( + 108, "GPIO108", + MTK_EINT_FUNCTION(0, 108), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO108"), + MTK_FUNCTION(1, "BPI_BUS2"), + MTK_FUNCTION(2, "CONN_BPI_BUS12_OLAT1"), + MTK_FUNCTION(3, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(4, "MFG_TSFDC_TSSEL2"), + MTK_FUNCTION(5, "I2SOUT4_DATA2"), + MTK_FUNCTION(6, "ANT_SEL9"), + MTK_FUNCTION(8, "IOBIST108") + ), + MTK_PIN( + 109, "GPIO109", + MTK_EINT_FUNCTION(0, 109), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO109"), + MTK_FUNCTION(1, "BPI_BUS3"), + MTK_FUNCTION(2, "CONN_BPI_BUS13_OLAT2"), + MTK_FUNCTION(4, "MFG_TSFDC_TSSEL1"), + MTK_FUNCTION(5, "I2SOUT4_DATA3"), + MTK_FUNCTION(6, "ANT_SEL10"), + MTK_FUNCTION(8, "IOBIST109") + ), + MTK_PIN( + 110, "GPIO110", + MTK_EINT_FUNCTION(0, 110), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO110"), + MTK_FUNCTION(1, "BPI_BUS4"), + MTK_FUNCTION(2, "CONN_BPI_BUS14_OLAT3"), + MTK_FUNCTION(3, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(4, "MFG_TSFDC_TSSEL0"), + MTK_FUNCTION(5, "I2SIN4_BCK"), + MTK_FUNCTION(6, "ANT_SEL11"), + MTK_FUNCTION(8, "IOBIST110") + ), + MTK_PIN( + 111, "GPIO111", + MTK_EINT_FUNCTION(0, 111), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO111"), + MTK_FUNCTION(1, "BPI_BUS5"), + MTK_FUNCTION(2, "CONN_BPI_BUS15_OLAT4"), + MTK_FUNCTION(3, "GPS_L5_ELNA_EN"), + MTK_FUNCTION(4, "MFG_TSFDC_RCK_SELB"), + MTK_FUNCTION(5, "I2SIN4_DATA0"), + MTK_FUNCTION(6, "ANT_SEL12"), + MTK_FUNCTION(8, "IOBIST111") + ), + MTK_PIN( + 112, "GPIO112", + MTK_EINT_FUNCTION(0, 112), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO112"), + MTK_FUNCTION(1, "BPI_BUS6"), + MTK_FUNCTION(2, "CONN_BPI_BUS6"), + MTK_FUNCTION(3, "MIPI3_D_SDATA"), + MTK_FUNCTION(4, "MFG_TSFDC_SDO"), + MTK_FUNCTION(5, "I2SIN4_DATA1"), + MTK_FUNCTION(6, "ANT_SEL13"), + MTK_FUNCTION(8, "IOBIST112") + ), + MTK_PIN( + 113, "GPIO113", + MTK_EINT_FUNCTION(0, 113), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO113"), + MTK_FUNCTION(1, "BPI_BUS7"), + MTK_FUNCTION(2, "CONN_BPI_BUS7"), + MTK_FUNCTION(3, "MIPI3_D_SCLK"), + MTK_FUNCTION(4, "MFG_TSFDC_FOUT"), + MTK_FUNCTION(5, "I2SIN4_DATA2"), + MTK_FUNCTION(6, "ANT_SEL14"), + MTK_FUNCTION(8, "IOBIST113") + ), + MTK_PIN( + 114, "GPIO114", + MTK_EINT_FUNCTION(0, 114), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO114"), + MTK_FUNCTION(1, "BPI_BUS8"), + MTK_FUNCTION(2, "CONN_BPI_BUS8"), + MTK_FUNCTION(3, "MIPI4_D_SDATA"), + MTK_FUNCTION(4, "SCL9"), + MTK_FUNCTION(5, "I2SIN4_DATA3"), + MTK_FUNCTION(6, "ANT_SEL15"), + MTK_FUNCTION(8, "IOBIST114") + ), + MTK_PIN( + 115, "GPIO115", + MTK_EINT_FUNCTION(0, 115), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO115"), + MTK_FUNCTION(1, "BPI_BUS9"), + MTK_FUNCTION(2, "CONN_BPI_BUS9"), + MTK_FUNCTION(3, "MIPI4_D_SCLK"), + MTK_FUNCTION(4, "SDA9"), + MTK_FUNCTION(5, "I2SIN4_LRCK"), + MTK_FUNCTION(6, "ANT_SEL16"), + MTK_FUNCTION(8, "IOBIST115") + ), + MTK_PIN( + 116, "GPIO116", + MTK_EINT_FUNCTION(0, 116), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO116"), + MTK_FUNCTION(1, "MD_UCNT_A_TGL"), + MTK_FUNCTION(8, "IOBIST116") + ), + MTK_PIN( + 117, "GPIO117", + MTK_EINT_FUNCTION(0, 117), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO117"), + MTK_FUNCTION(1, "DIGRF_IRQ"), + MTK_FUNCTION(8, "IOBIST117") + ), + MTK_PIN( + 118, "GPIO118", + MTK_EINT_FUNCTION(0, 118), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO118"), + MTK_FUNCTION(8, "IOBIST118") + ), + MTK_PIN( + 119, "GPIO119", + MTK_EINT_FUNCTION(0, 119), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO119"), + MTK_FUNCTION(1, "AP_GOOD"), + MTK_FUNCTION(3, "CONN_WIFI_TXD"), + MTK_FUNCTION(4, "GPS_PPS"), + MTK_FUNCTION(5, "PMSR_SMAP"), + MTK_FUNCTION(6, "AGPS_SYNC"), + MTK_FUNCTION(8, "IOBIST119") + ), + MTK_PIN( + 120, "GPIO120", + MTK_EINT_FUNCTION(0, 120), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO120"), + MTK_FUNCTION(1, "KPCOL0_VLP"), + MTK_FUNCTION(8, "IOBIST120") + ), + MTK_PIN( + 121, "GPIO121", + MTK_EINT_FUNCTION(0, 121), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO121"), + MTK_FUNCTION(1, "SRCLKENAI0"), + MTK_FUNCTION(2, "SRCLKENAI1"), + MTK_FUNCTION(8, "IOBIST121") + ), + MTK_PIN( + 122, "GPIO122", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO122"), + MTK_FUNCTION(1, "WATCHDOG"), + MTK_FUNCTION(8, "IOBIST122") + ), + MTK_PIN( + 123, "GPIO123", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO123"), + MTK_FUNCTION(8, "IOBIST123") + ), + MTK_PIN( + 124, "GPIO124", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO124"), + MTK_FUNCTION(1, "SRCLKENA0"), + MTK_FUNCTION(8, "IOBIST124") + ), + MTK_PIN( + 125, "GPIO125", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO125"), + MTK_FUNCTION(1, "RTC32K_CK"), + MTK_FUNCTION(8, "IOBIST125") + ), + MTK_PIN( + 126, "GPIO126", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO126"), + MTK_FUNCTION(1, "SPMI_M_SCL"), + MTK_FUNCTION(8, "IOBIST126") + ), + MTK_PIN( + 127, "GPIO127", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO127"), + MTK_FUNCTION(1, "SPMI_M_SDA"), + MTK_FUNCTION(8, "IOBIST127") + ), + MTK_PIN( + 128, "GPIO128", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO128"), + MTK_FUNCTION(1, "SPMI_P_SCL"), + MTK_FUNCTION(8, "IOBIST128") + ), + MTK_PIN( + 129, "GPIO129", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO129"), + MTK_FUNCTION(1, "SPMI_P_SDA"), + MTK_FUNCTION(8, "IOBIST129") + ), + MTK_PIN( + 130, "GPIO130", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO130"), + MTK_FUNCTION(3, "BPI_BUS13"), + MTK_FUNCTION(8, "IOBIST130") + ), + MTK_PIN( + 131, "GPIO131", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO131"), + MTK_FUNCTION(1, "SPI6_CLK"), + MTK_FUNCTION(2, "KPROW2"), + MTK_FUNCTION(3, "BPI_BUS14"), + MTK_FUNCTION(4, "CONN_BT_TXD"), + MTK_FUNCTION(5, "MD32_1_TXD"), + MTK_FUNCTION(6, "PTA_TXD"), + MTK_FUNCTION(8, "IOBIST131") + ), + MTK_PIN( + 132, "GPIO132", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO132"), + MTK_FUNCTION(1, "SPI6_CSB"), + MTK_FUNCTION(2, "KPCOL2"), + MTK_FUNCTION(3, "BPI_BUS15"), + MTK_FUNCTION(5, "MD32_1_RXD"), + MTK_FUNCTION(6, "PTA_RXD"), + MTK_FUNCTION(8, "IOBIST132") + ), + MTK_PIN( + 133, "GPIO133", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO133"), + MTK_FUNCTION(1, "SPI6_MO"), + MTK_FUNCTION(2, "CLKM0"), + MTK_FUNCTION(3, "BPI_BUS16"), + MTK_FUNCTION(4, "CMFLASH2"), + MTK_FUNCTION(8, "IOBIST133") + ), + MTK_PIN( + 134, "GPIO134", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO134"), + MTK_FUNCTION(1, "SPI6_MI"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(3, "BPI_BUS17"), + MTK_FUNCTION(4, "CMFLASH3"), + MTK_FUNCTION(8, "IOBIST134") + ), + MTK_PIN( + 135, "GPIO135", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO135"), + MTK_FUNCTION(1, "SCP_SCL1"), + MTK_FUNCTION(2, "CLKM2"), + MTK_FUNCTION(3, "SCP_DMIC_CLK"), + MTK_FUNCTION(4, "DMIC_CLK"), + MTK_FUNCTION(5, "TP_GPIO13_AO"), + MTK_FUNCTION(7, "DBG_MON_A23"), + MTK_FUNCTION(8, "IOBIST135") + ), + MTK_PIN( + 136, "GPIO136", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO136"), + MTK_FUNCTION(1, "SCP_SDA1"), + MTK_FUNCTION(2, "CLKM3"), + MTK_FUNCTION(3, "SCP_DMIC_DAT"), + MTK_FUNCTION(4, "DMIC_DAT"), + MTK_FUNCTION(5, "TP_GPIO14_AO"), + MTK_FUNCTION(7, "DBG_MON_A24"), + MTK_FUNCTION(8, "IOBIST136") + ), + MTK_PIN( + 137, "GPIO137", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO137"), + MTK_FUNCTION(2, "IRRX_IN"), + MTK_FUNCTION(3, "MD_INT0"), + MTK_FUNCTION(4, "SPMI_M_TRIG_FLAG"), + MTK_FUNCTION(5, "TP_GPIO15_AO"), + MTK_FUNCTION(6, "UFS_MPHY_SCL"), + MTK_FUNCTION(8, "IOBIST137") + ), + MTK_PIN( + 138, "GPIO138", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO138"), + MTK_FUNCTION(2, "PWM_VLP"), + MTK_FUNCTION(3, "MD_INT3"), + MTK_FUNCTION(5, "TP_GPIO0_AO"), + MTK_FUNCTION(6, "UFS_MPHY_SDA"), + MTK_FUNCTION(8, "IOBIST138") + ), + MTK_PIN( + 139, "GPIO139", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO139"), + MTK_FUNCTION(1, "SCL0"), + MTK_FUNCTION(4, "BPI_BUS18"), + MTK_FUNCTION(7, "DBG_MON_B28"), + MTK_FUNCTION(8, "IOBIST139") + ), + MTK_PIN( + 140, "GPIO140", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO140"), + MTK_FUNCTION(1, "SDA0"), + MTK_FUNCTION(4, "BPI_BUS19"), + MTK_FUNCTION(7, "DBG_MON_B29"), + MTK_FUNCTION(8, "IOBIST140") + ), + MTK_PIN( + 141, "GPIO141", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO141"), + MTK_FUNCTION(1, "SCL1"), + MTK_FUNCTION(2, "SCL9"), + MTK_FUNCTION(4, "BPI_BUS20"), + MTK_FUNCTION(7, "DBG_MON_B30"), + MTK_FUNCTION(8, "IOBIST141") + ), + MTK_PIN( + 142, "GPIO142", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO142"), + MTK_FUNCTION(1, "SDA1"), + MTK_FUNCTION(2, "SDA9"), + MTK_FUNCTION(4, "BPI_BUS21"), + MTK_FUNCTION(7, "DBG_MON_B31"), + MTK_FUNCTION(8, "IOBIST142") + ), + MTK_PIN( + 143, "GPIO143", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO143"), + MTK_FUNCTION(1, "SCL2"), + MTK_FUNCTION(7, "DBG_MON_B9"), + MTK_FUNCTION(8, "IOBIST143") + ), + MTK_PIN( + 144, "GPIO144", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO144"), + MTK_FUNCTION(1, "SDA2"), + MTK_FUNCTION(7, "DBG_MON_B10"), + MTK_FUNCTION(8, "IOBIST144") + ), + MTK_PIN( + 145, "GPIO145", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO145"), + MTK_FUNCTION(1, "SCL3"), + MTK_FUNCTION(3, "DMIC1_CLK"), + MTK_FUNCTION(7, "DBG_MON_B11"), + MTK_FUNCTION(8, "IOBIST145") + ), + MTK_PIN( + 146, "GPIO146", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO146"), + MTK_FUNCTION(1, "SDA3"), + MTK_FUNCTION(3, "DMIC1_DAT"), + MTK_FUNCTION(7, "DBG_MON_B12"), + MTK_FUNCTION(8, "IOBIST146") + ), + MTK_PIN( + 147, "GPIO147", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO147"), + MTK_FUNCTION(1, "SCL4"), + MTK_FUNCTION(7, "DBG_MON_A31"), + MTK_FUNCTION(8, "IOBIST147") + ), + MTK_PIN( + 148, "GPIO148", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO148"), + MTK_FUNCTION(1, "SDA4"), + MTK_FUNCTION(7, "DBG_MON_A7"), + MTK_FUNCTION(8, "IOBIST148") + ), + MTK_PIN( + 149, "GPIO149", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO149"), + MTK_FUNCTION(1, "SCL5"), + MTK_FUNCTION(8, "IOBIST149") + ), + MTK_PIN( + 150, "GPIO150", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO150"), + MTK_FUNCTION(1, "SDA5"), + MTK_FUNCTION(8, "IOBIST150") + ), + MTK_PIN( + 151, "GPIO151", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO151"), + MTK_FUNCTION(1, "SCL6"), + MTK_FUNCTION(2, "SCL11"), + MTK_FUNCTION(8, "IOBIST151") + ), + MTK_PIN( + 152, "GPIO152", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO152"), + MTK_FUNCTION(1, "SDA6"), + MTK_FUNCTION(2, "SDA11"), + MTK_FUNCTION(8, "IOBIST152") + ), + MTK_PIN( + 153, "GPIO153", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO153"), + MTK_FUNCTION(1, "SCL7"), + MTK_FUNCTION(7, "DBG_MON_A3"), + MTK_FUNCTION(8, "IOBIST153") + ), + MTK_PIN( + 154, "GPIO154", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO154"), + MTK_FUNCTION(1, "SDA7"), + MTK_FUNCTION(7, "DBG_MON_A4"), + MTK_FUNCTION(8, "IOBIST154") + ), + MTK_PIN( + 155, "GPIO155", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO155"), + MTK_FUNCTION(1, "SCL8"), + MTK_FUNCTION(7, "DBG_MON_A5"), + MTK_FUNCTION(8, "IOBIST155") + ), + MTK_PIN( + 156, "GPIO156", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO156"), + MTK_FUNCTION(1, "SDA8"), + MTK_FUNCTION(8, "IOBIST156") + ), + MTK_PIN( + 157, "GPIO157", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO157"), + MTK_FUNCTION(1, "SCP_SCL0"), + MTK_FUNCTION(3, "SCP_SCL5"), + MTK_FUNCTION(4, "TP_UCTS1_VLP"), + MTK_FUNCTION(5, "TP_GPIO0_AO"), + MTK_FUNCTION(7, "DBG_MON_A27"), + MTK_FUNCTION(8, "IOBIST157") + ), + MTK_PIN( + 158, "GPIO158", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO158"), + MTK_FUNCTION(1, "SCP_SDA0"), + MTK_FUNCTION(3, "SCP_SDA5"), + MTK_FUNCTION(4, "TP_URTS1_VLP"), + MTK_FUNCTION(5, "TP_GPIO1_AO"), + MTK_FUNCTION(7, "DBG_MON_A28"), + MTK_FUNCTION(8, "IOBIST158") + ), + MTK_PIN( + 159, "GPIO159", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO159"), + MTK_FUNCTION(1, "SCP_SCL1"), + MTK_FUNCTION(3, "SCP_SCL4"), + MTK_FUNCTION(4, "TP_UCTS2_VLP"), + MTK_FUNCTION(5, "TP_GPIO2_AO"), + MTK_FUNCTION(7, "DBG_MON_A29"), + MTK_FUNCTION(8, "IOBIST159") + ), + MTK_PIN( + 160, "GPIO160", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO160"), + MTK_FUNCTION(1, "SCP_SDA1"), + MTK_FUNCTION(3, "SCP_SDA4"), + MTK_FUNCTION(4, "TP_URTS2_VLP"), + MTK_FUNCTION(5, "TP_GPIO3_AO"), + MTK_FUNCTION(7, "DBG_MON_A30"), + MTK_FUNCTION(8, "IOBIST160") + ), + MTK_PIN( + 161, "GPIO161", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO161"), + MTK_FUNCTION(1, "SCP_SCL2"), + MTK_FUNCTION(2, "SCL10"), + MTK_FUNCTION(3, "SCP_DMIC_CLK"), + MTK_FUNCTION(4, "DMIC_CLK"), + MTK_FUNCTION(5, "TP_GPIO4_AO"), + MTK_FUNCTION(6, "EXTIF0_PRI"), + MTK_FUNCTION(8, "IOBIST161") + ), + MTK_PIN( + 162, "GPIO162", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO162"), + MTK_FUNCTION(1, "SCP_SDA2"), + MTK_FUNCTION(2, "SDA10"), + MTK_FUNCTION(3, "SCP_DMIC_DAT"), + MTK_FUNCTION(4, "DMIC_DAT"), + MTK_FUNCTION(5, "TP_GPIO5_AO"), + MTK_FUNCTION(6, "EXTIF0_GNT_B"), + MTK_FUNCTION(8, "IOBIST162") + ), + MTK_PIN( + 163, "GPIO163", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO163"), + MTK_FUNCTION(1, "SCP_SCL3"), + MTK_FUNCTION(2, "SCL12"), + MTK_FUNCTION(5, "TP_GPIO6_AO"), + MTK_FUNCTION(7, "MBISTREADEN_TRIGGER"), + MTK_FUNCTION(8, "IOBIST163") + ), + MTK_PIN( + 164, "GPIO164", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO164"), + MTK_FUNCTION(1, "SCP_SDA3"), + MTK_FUNCTION(2, "SDA12"), + MTK_FUNCTION(5, "TP_GPIO7_AO"), + MTK_FUNCTION(7, "MBISTWRITEEN_TRIGGER"), + MTK_FUNCTION(8, "IOBIST164") + ), + MTK_PIN( + 165, "GPIO165", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO165"), + MTK_FUNCTION(1, "MIPI0_D_SCLK"), + MTK_FUNCTION(2, "CONN_MIPI0_SCLK"), + MTK_FUNCTION(3, "BPI_BUS18"), + MTK_FUNCTION(6, "ANT_SEL17"), + MTK_FUNCTION(8, "IOBIST165") + ), + MTK_PIN( + 166, "GPIO166", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO166"), + MTK_FUNCTION(1, "MIPI0_D_SDATA"), + MTK_FUNCTION(2, "CONN_MIPI0_SDATA"), + MTK_FUNCTION(3, "BPI_BUS19"), + MTK_FUNCTION(6, "ANT_SEL18"), + MTK_FUNCTION(8, "IOBIST166") + ), + MTK_PIN( + 167, "GPIO167", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO167"), + MTK_FUNCTION(1, "MIPI1_D_SCLK"), + MTK_FUNCTION(2, "CONN_MIPI1_SCLK"), + MTK_FUNCTION(3, "BPI_BUS20"), + MTK_FUNCTION(6, "ANT_SEL19"), + MTK_FUNCTION(8, "IOBIST167") + ), + MTK_PIN( + 168, "GPIO168", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO168"), + MTK_FUNCTION(1, "MIPI1_D_SDATA"), + MTK_FUNCTION(2, "CONN_MIPI1_SDATA"), + MTK_FUNCTION(3, "BPI_BUS21"), + MTK_FUNCTION(6, "ANT_SEL20"), + MTK_FUNCTION(8, "IOBIST168") + ), + MTK_PIN( + 169, "GPIO169", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO169"), + MTK_FUNCTION(1, "MIPI2_D_SCLK"), + MTK_FUNCTION(3, "BPI_BUS10"), + MTK_FUNCTION(6, "MD_GPS_L1_BLANK"), + MTK_FUNCTION(8, "IOBIST169") + ), + MTK_PIN( + 170, "GPIO170", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO170"), + MTK_FUNCTION(1, "MIPI2_D_SDATA"), + MTK_FUNCTION(3, "BPI_BUS11"), + MTK_FUNCTION(6, "MD_GPS_L5_BLANK"), + MTK_FUNCTION(8, "IOBIST170") + ), + MTK_PIN( + 171, "GPIO171", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO171"), + MTK_FUNCTION(1, "MIPI_M_SCLK"), + MTK_FUNCTION(8, "IOBIST171") + ), + MTK_PIN( + 172, "GPIO172", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO172"), + MTK_FUNCTION(1, "MIPI_M_SDATA"), + MTK_FUNCTION(8, "IOBIST172") + ), + MTK_PIN( + 173, "GPIO173", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO173"), + MTK_FUNCTION(1, "AUD_CLK_MOSI"), + MTK_FUNCTION(3, "AUD_CLK_MOSI"), + MTK_FUNCTION(8, "IOBIST173") + ), + MTK_PIN( + 174, "GPIO174", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO174"), + MTK_FUNCTION(1, "AUD_SYNC_MOSI"), + MTK_FUNCTION(8, "IOBIST174") + ), + MTK_PIN( + 175, "GPIO175", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO175"), + MTK_FUNCTION(1, "AUD_DAT_MOSI0"), + MTK_FUNCTION(3, "AUD_DAT_MOSI0"), + MTK_FUNCTION(8, "IOBIST175") + ), + MTK_PIN( + 176, "GPIO176", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO176"), + MTK_FUNCTION(1, "AUD_DAT_MOSI1"), + MTK_FUNCTION(3, "AUD_DAT_MOSI1"), + MTK_FUNCTION(8, "IOBIST176") + ), + MTK_PIN( + 177, "GPIO177", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO177"), + MTK_FUNCTION(1, "AUD_NLE_MOSI0"), + MTK_FUNCTION(2, "AUD_SYNC_MISO"), + MTK_FUNCTION(8, "IOBIST177") + ), + MTK_PIN( + 178, "GPIO178", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO178"), + MTK_FUNCTION(1, "AUD_NLE_MOSI1"), + MTK_FUNCTION(2, "AUD_CLK_MISO"), + MTK_FUNCTION(3, "AUD_CLK_MISO"), + MTK_FUNCTION(8, "IOBIST178") + ), + MTK_PIN( + 179, "GPIO179", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO179"), + MTK_FUNCTION(1, "AUD_DAT_MISO0"), + MTK_FUNCTION(2, "VOW_DAT_MISO"), + MTK_FUNCTION(3, "AUD_DAT_MISO0"), + MTK_FUNCTION(8, "IOBIST179") + ), + MTK_PIN( + 180, "GPIO180", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO180"), + MTK_FUNCTION(1, "AUD_DAT_MISO1"), + MTK_FUNCTION(2, "VOW_CLK_MISO"), + MTK_FUNCTION(3, "AUD_DAT_MISO1"), + MTK_FUNCTION(8, "IOBIST180") + ), + MTK_PIN( + 181, "GPIO181", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO181"), + MTK_FUNCTION(1, "SCP_VREQ_VAO"), + MTK_FUNCTION(8, "IOBIST181") + ), + MTK_PIN( + 182, "GPIO182", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO182"), + MTK_FUNCTION(1, "CONN_TOP_CLK"), + MTK_FUNCTION(8, "IOBIST182") + ), + MTK_PIN( + 183, "GPIO183", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO183"), + MTK_FUNCTION(1, "CONN_TOP_DATA"), + MTK_FUNCTION(8, "IOBIST183") + ), + MTK_PIN( + 184, "GPIO184", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO184"), + MTK_FUNCTION(1, "CONN_BT_CLK"), + MTK_FUNCTION(8, "IOBIST184") + ), + MTK_PIN( + 185, "GPIO185", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO185"), + MTK_FUNCTION(1, "CONN_BT_DATA"), + MTK_FUNCTION(8, "IOBIST185") + ), + MTK_PIN( + 186, "GPIO186", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO186"), + MTK_FUNCTION(1, "CONN_HRST_B"), + MTK_FUNCTION(8, "IOBIST186") + ), + MTK_PIN( + 187, "GPIO187", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO187"), + MTK_FUNCTION(1, "CONN_WB_PTA"), + MTK_FUNCTION(8, "IOBIST187") + ), + MTK_PIN( + 188, "GPIO188", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO188"), + MTK_FUNCTION(1, "CONN_WF_CTRL0"), + MTK_FUNCTION(8, "IOBIST188") + ), + MTK_PIN( + 189, "GPIO189", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO189"), + MTK_FUNCTION(1, "CONN_WF_CTRL1"), + MTK_FUNCTION(8, "IOBIST189") + ), + MTK_PIN( + 190, "GPIO190", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO190"), + MTK_FUNCTION(1, "CONN_WF_CTRL2"), + MTK_FUNCTION(8, "IOBIST190") + ), + MTK_PIN( + 191, "GPIO191", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO191"), + MTK_FUNCTION(1, "CONN_TOP_CLK_2"), + MTK_FUNCTION(8, "IOBIST191") + ), + MTK_PIN( + 192, "GPIO192", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO192"), + MTK_FUNCTION(1, "CONN_TOP_DATA_2"), + MTK_FUNCTION(8, "IOBIST192") + ), + MTK_PIN( + 193, "GPIO193", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO193"), + MTK_FUNCTION(1, "CONN_HRST_B_2"), + MTK_FUNCTION(8, "IOBIST193") + ), + MTK_PIN( + 194, "GPIO194", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO194"), + MTK_FUNCTION(1, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(2, "MD_GPS_L1_BLANK"), + MTK_FUNCTION(8, "IOBIST194") + ), + MTK_PIN( + 195, "GPIO195", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO195"), + MTK_FUNCTION(1, "GPS_L5_ELNA_EN"), + MTK_FUNCTION(2, "MD_GPS_L5_BLANK"), + MTK_FUNCTION(3, "ANT_SEL21"), + MTK_FUNCTION(5, "SPMI_P_TRIG_FLAG"), + MTK_FUNCTION(8, "IOBIST195") + ), + MTK_PIN( + 196, "GPIO196", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO196"), + MTK_FUNCTION(1, "PAD_RESET_DRAM_0"), + MTK_FUNCTION(8, "IOBIST196") + ), + MTK_PIN_VEINT(197), + MTK_PIN_VEINT(198), + MTK_PIN_VEINT(199), + MTK_PIN_VEINT(200), + MTK_PIN_VEINT(201), + MTK_PIN_VEINT(202), + MTK_PIN_VEINT(203), + MTK_PIN_VEINT(204), + MTK_PIN_VEINT(205), + MTK_PIN_VEINT(206), + MTK_PIN_VEINT(207), + MTK_PIN_VEINT(208), + MTK_PIN_VEINT(209), + MTK_PIN_VEINT(210), + MTK_PIN_VEINT(211), + MTK_PIN_VEINT(212), + MTK_PIN_VEINT(213), + MTK_PIN_VEINT(214), + MTK_PIN_VEINT(215), + MTK_PIN_VEINT(216), +}; + +static struct mtk_eint_pin eint_pins_mt6858[] = { + MTK_EINT_PIN(0, 2, 0, 1), + MTK_EINT_PIN(1, 2, 1, 1), + MTK_EINT_PIN(2, 2, 2, 1), + MTK_EINT_PIN(3, 2, 3, 1), + MTK_EINT_PIN(4, 2, 4, 1), + MTK_EINT_PIN(5, 2, 5, 1), + MTK_EINT_PIN(6, 2, 6, 1), + MTK_EINT_PIN(7, 2, 7, 1), + MTK_EINT_PIN(8, 0, 0, 1), + MTK_EINT_PIN(9, 0, 1, 1), + MTK_EINT_PIN(10, 0, 2, 1), + MTK_EINT_PIN(11, 0, 3, 1), + MTK_EINT_PIN(12, 0, 4, 1), + MTK_EINT_PIN(13, 1, 0, 1), + MTK_EINT_PIN(14, 1, 1, 1), + MTK_EINT_PIN(15, 1, 2, 1), + MTK_EINT_PIN(16, 1, 3, 1), + MTK_EINT_PIN(17, 1, 4, 1), + MTK_EINT_PIN(18, 1, 5, 1), + MTK_EINT_PIN(19, 1, 6, 1), + MTK_EINT_PIN(20, 1, 7, 1), + MTK_EINT_PIN(21, 0, 5, 1), + MTK_EINT_PIN(22, 0, 6, 1), + MTK_EINT_PIN(23, 2, 8, 1), + MTK_EINT_PIN(24, 0, 7, 1), + MTK_EINT_PIN(25, 2, 18, 0), + MTK_EINT_PIN(26, 0, 8, 1), + MTK_EINT_PIN(27, 2, 9, 1), + MTK_EINT_PIN(28, 2, 10, 1), + MTK_EINT_PIN(29, 2, 11, 1), + MTK_EINT_PIN(30, 2, 12, 1), + MTK_EINT_PIN(31, 2, 13, 1), + MTK_EINT_PIN(32, 2, 14, 1), + MTK_EINT_PIN(33, 2, 15, 1), + MTK_EINT_PIN(34, 2, 16, 1), + MTK_EINT_PIN(35, 0, 9, 1), + MTK_EINT_PIN(36, 2, 17, 1), + MTK_EINT_PIN(37, 2, 19, 0), + MTK_EINT_PIN(38, 2, 20, 0), + MTK_EINT_PIN(39, 2, 21, 0), + MTK_EINT_PIN(40, 0, 10, 0), + MTK_EINT_PIN(41, 0, 11, 0), + MTK_EINT_PIN(42, 0, 12, 0), + MTK_EINT_PIN(43, 0, 13, 0), + MTK_EINT_PIN(44, 0, 14, 0), + MTK_EINT_PIN(45, 0, 15, 0), + MTK_EINT_PIN(46, 0, 16, 0), + MTK_EINT_PIN(47, 0, 17, 0), + MTK_EINT_PIN(48, 0, 18, 0), + MTK_EINT_PIN(49, 0, 19, 0), + MTK_EINT_PIN(50, 0, 20, 0), + MTK_EINT_PIN(51, 0, 21, 0), + MTK_EINT_PIN(52, 0, 22, 0), + MTK_EINT_PIN(53, 0, 23, 0), + MTK_EINT_PIN(54, 0, 24, 0), + MTK_EINT_PIN(55, 0, 25, 0), + MTK_EINT_PIN(56, 0, 26, 0), + MTK_EINT_PIN(57, 0, 27, 0), + MTK_EINT_PIN(58, 0, 28, 0), + MTK_EINT_PIN(59, 0, 29, 0), + MTK_EINT_PIN(60, 0, 30, 0), + MTK_EINT_PIN(61, 0, 31, 0), + MTK_EINT_PIN(62, 2, 22, 0), + MTK_EINT_PIN(63, 2, 23, 0), + MTK_EINT_PIN(64, 2, 24, 0), + MTK_EINT_PIN(65, 2, 25, 0), + MTK_EINT_PIN(66, 0, 32, 0), + MTK_EINT_PIN(67, 0, 33, 0), + MTK_EINT_PIN(68, 0, 34, 0), + MTK_EINT_PIN(69, 0, 35, 0), + MTK_EINT_PIN(70, 0, 36, 0), + MTK_EINT_PIN(71, 0, 37, 0), + MTK_EINT_PIN(72, 0, 38, 0), + MTK_EINT_PIN(73, 0, 39, 0), + MTK_EINT_PIN(74, 0, 40, 0), + MTK_EINT_PIN(75, 0, 41, 0), + MTK_EINT_PIN(76, 0, 42, 0), + MTK_EINT_PIN(77, 0, 43, 0), + MTK_EINT_PIN(78, 0, 44, 0), + MTK_EINT_PIN(79, 0, 45, 0), + MTK_EINT_PIN(80, 0, 46, 0), + MTK_EINT_PIN(81, 0, 47, 0), + MTK_EINT_PIN(82, 2, 26, 0), + MTK_EINT_PIN(83, 2, 27, 0), + MTK_EINT_PIN(84, 2, 28, 0), + MTK_EINT_PIN(85, 2, 29, 0), + MTK_EINT_PIN(86, 2, 30, 0), + MTK_EINT_PIN(87, 2, 31, 0), + MTK_EINT_PIN(88, 0, 48, 0), + MTK_EINT_PIN(89, 0, 49, 0), + MTK_EINT_PIN(90, 0, 50, 0), + MTK_EINT_PIN(91, 0, 51, 0), + MTK_EINT_PIN(92, 0, 52, 0), + MTK_EINT_PIN(93, 0, 53, 0), + MTK_EINT_PIN(94, 0, 54, 0), + MTK_EINT_PIN(95, 0, 55, 0), + MTK_EINT_PIN(96, 0, 56, 0), + MTK_EINT_PIN(97, 0, 57, 0), + MTK_EINT_PIN(98, 0, 58, 0), + MTK_EINT_PIN(99, 2, 32, 0), + MTK_EINT_PIN(100, 2, 33, 0), + MTK_EINT_PIN(101, 2, 34, 0), + MTK_EINT_PIN(102, 2, 35, 0), + MTK_EINT_PIN(103, 2, 36, 0), + MTK_EINT_PIN(104, 2, 37, 0), + MTK_EINT_PIN(105, 2, 38, 0), + MTK_EINT_PIN(106, 0, 59, 0), + MTK_EINT_PIN(107, 0, 60, 0), + MTK_EINT_PIN(108, 0, 61, 0), + MTK_EINT_PIN(109, 0, 62, 0), + MTK_EINT_PIN(110, 0, 63, 0), + MTK_EINT_PIN(111, 0, 64, 0), + MTK_EINT_PIN(112, 0, 65, 0), + MTK_EINT_PIN(113, 0, 66, 0), + MTK_EINT_PIN(114, 0, 67, 0), + MTK_EINT_PIN(115, 0, 68, 0), + MTK_EINT_PIN(116, 0, 69, 0), + MTK_EINT_PIN(117, 0, 70, 0), + MTK_EINT_PIN(118, 0, 71, 0), + MTK_EINT_PIN(119, 0, 72, 0), + MTK_EINT_PIN(120, 0, 73, 0), + MTK_EINT_PIN(121, 0, 74, 0), + MTK_EINT_PIN(122, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(123, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(124, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(125, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(126, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(127, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(128, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(129, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(130, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(131, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(132, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(133, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(134, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(135, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(136, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(137, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(138, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(139, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(140, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(141, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(142, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(143, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(144, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(145, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(146, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(147, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(148, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(149, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(150, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(151, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(152, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(153, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(154, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(155, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(156, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(157, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(158, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(159, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(160, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(161, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(162, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(163, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(164, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(165, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(166, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(167, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(168, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(169, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(170, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(171, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(172, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(173, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(174, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(175, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(176, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(177, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(178, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(179, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(180, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(181, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(182, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(183, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(184, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(185, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(186, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(187, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(188, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(189, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(190, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(191, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(192, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(193, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(194, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(195, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(196, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(197, 3, 0, 0), + MTK_EINT_PIN(198, 3, 1, 0), + MTK_EINT_PIN(199, 3, 2, 0), + MTK_EINT_PIN(200, 3, 3, 0), + MTK_EINT_PIN(201, 3, 4, 0), + MTK_EINT_PIN(202, 3, 5, 0), + MTK_EINT_PIN(203, 3, 6, 0), + MTK_EINT_PIN(204, 3, 7, 0), + MTK_EINT_PIN(205, 3, 8, 0), + MTK_EINT_PIN(206, 3, 9, 0), + MTK_EINT_PIN(207, 3, 10, 0), + MTK_EINT_PIN(208, 3, 11, 0), + MTK_EINT_PIN(209, 3, 12, 0), + MTK_EINT_PIN(210, 3, 13, 0), + MTK_EINT_PIN(211, 3, 14, 0), + MTK_EINT_PIN(212, 3, 15, 0), + MTK_EINT_PIN(213, 3, 16, 0), + MTK_EINT_PIN(214, 3, 17, 0), + MTK_EINT_PIN(215, 3, 18, 0), + MTK_EINT_PIN(216, 3, 19, 0), +}; + +#endif /* __PINCTRL_MTK_MT6858_H */ From c65c3afedaf60731c994a2567cce06b07abaff9b Mon Sep 17 00:00:00 2001 From: Nikolai Burov Date: Mon, 13 Jul 2026 18:06:23 +0300 Subject: [PATCH 043/130] arm64: dts: mediatek: mt6858: Add pinmux macro header file Add a header file providing macros needed for specifying MT6858 pin functions in device tree files. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nikolai Burov Signed-off-by: Linus Walleij --- arch/arm64/boot/dts/mediatek/mt6858-pinfunc.h | 1335 +++++++++++++++++ 1 file changed, 1335 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt6858-pinfunc.h diff --git a/arch/arm64/boot/dts/mediatek/mt6858-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt6858-pinfunc.h new file mode 100644 index 000000000000..a229b2578a16 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6858-pinfunc.h @@ -0,0 +1,1335 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Alice Chao + */ + +#ifndef __MT6858_PINFUNC_H +#define __MT6858_PINFUNC_H + +#include + +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 1) +#define PINMUX_GPIO0__FUNC_MD_INT0 (MTK_PIN_NO(0) | 3) +#define PINMUX_GPIO0__FUNC_SCP_SCL4 (MTK_PIN_NO(0) | 5) +#define PINMUX_GPIO0__FUNC_DBG_MON_A0 (MTK_PIN_NO(0) | 7) +#define PINMUX_GPIO0__FUNC_IOBIST0 (MTK_PIN_NO(0) | 8) + +#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 1) +#define PINMUX_GPIO1__FUNC_SRCLKENA2 (MTK_PIN_NO(1) | 2) +#define PINMUX_GPIO1__FUNC_MD_INT3 (MTK_PIN_NO(1) | 3) +#define PINMUX_GPIO1__FUNC_SCP_DMIC_CLK (MTK_PIN_NO(1) | 4) +#define PINMUX_GPIO1__FUNC_DMIC_CLK (MTK_PIN_NO(1) | 5) +#define PINMUX_GPIO1__FUNC_SCP_SCL5 (MTK_PIN_NO(1) | 6) +#define PINMUX_GPIO1__FUNC_DBG_MON_A1 (MTK_PIN_NO(1) | 7) +#define PINMUX_GPIO1__FUNC_IOBIST1 (MTK_PIN_NO(1) | 8) + +#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 1) +#define PINMUX_GPIO2__FUNC_MD_INT4 (MTK_PIN_NO(2) | 3) +#define PINMUX_GPIO2__FUNC_SCP_DMIC_DAT (MTK_PIN_NO(2) | 4) +#define PINMUX_GPIO2__FUNC_DMIC_DAT (MTK_PIN_NO(2) | 5) +#define PINMUX_GPIO2__FUNC_SCP_SDA5 (MTK_PIN_NO(2) | 6) +#define PINMUX_GPIO2__FUNC_DBG_MON_A2 (MTK_PIN_NO(2) | 7) +#define PINMUX_GPIO2__FUNC_IOBIST2 (MTK_PIN_NO(2) | 8) + +#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 1) +#define PINMUX_GPIO3__FUNC_SPI7_CLK (MTK_PIN_NO(3) | 2) +#define PINMUX_GPIO3__FUNC_TP_UTXD2_VLP (MTK_PIN_NO(3) | 3) +#define PINMUX_GPIO3__FUNC_SSPM_UTXD_AO_VLP (MTK_PIN_NO(3) | 4) +#define PINMUX_GPIO3__FUNC_MD_MCIF_UTXD0 (MTK_PIN_NO(3) | 5) +#define PINMUX_GPIO3__FUNC_IOBIST3 (MTK_PIN_NO(3) | 8) + +#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 1) +#define PINMUX_GPIO4__FUNC_SPI7_CSB (MTK_PIN_NO(4) | 2) +#define PINMUX_GPIO4__FUNC_TP_URXD2_VLP (MTK_PIN_NO(4) | 3) +#define PINMUX_GPIO4__FUNC_SSPM_URXD_AO_VLP (MTK_PIN_NO(4) | 4) +#define PINMUX_GPIO4__FUNC_MD_MCIF_URXD0 (MTK_PIN_NO(4) | 5) +#define PINMUX_GPIO4__FUNC_IOBIST4 (MTK_PIN_NO(4) | 8) + +#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 1) +#define PINMUX_GPIO5__FUNC_SPI7_MO (MTK_PIN_NO(5) | 2) +#define PINMUX_GPIO5__FUNC_IOBIST5 (MTK_PIN_NO(5) | 8) + +#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 1) +#define PINMUX_GPIO6__FUNC_SPI7_MI (MTK_PIN_NO(6) | 2) +#define PINMUX_GPIO6__FUNC_GPS_PPS (MTK_PIN_NO(6) | 3) +#define PINMUX_GPIO6__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(6) | 4) +#define PINMUX_GPIO6__FUNC_IOBIST6 (MTK_PIN_NO(6) | 8) + +#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 1) +#define PINMUX_GPIO7__FUNC_SRCLKENA1 (MTK_PIN_NO(7) | 2) +#define PINMUX_GPIO7__FUNC_PWM_1 (MTK_PIN_NO(7) | 3) +#define PINMUX_GPIO7__FUNC_MD32_1_GPIO0 (MTK_PIN_NO(7) | 4) +#define PINMUX_GPIO7__FUNC_SCP_SDA4 (MTK_PIN_NO(7) | 5) +#define PINMUX_GPIO7__FUNC_MD_INT4 (MTK_PIN_NO(7) | 6) +#define PINMUX_GPIO7__FUNC_IOBIST7 (MTK_PIN_NO(7) | 8) + +#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define PINMUX_GPIO8__FUNC_SSPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(8) | 1) +#define PINMUX_GPIO8__FUNC_SCP_JTAG0_TRSTN_VCORE (MTK_PIN_NO(8) | 2) +#define PINMUX_GPIO8__FUNC_CONN_BGF_MCU_TRST_B (MTK_PIN_NO(8) | 6) +#define PINMUX_GPIO8__FUNC_IOBIST8 (MTK_PIN_NO(8) | 8) + +#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define PINMUX_GPIO9__FUNC_SSPM_JTAG_TCK_VCORE (MTK_PIN_NO(9) | 1) +#define PINMUX_GPIO9__FUNC_SCP_JTAG0_TCK_VCORE (MTK_PIN_NO(9) | 2) +#define PINMUX_GPIO9__FUNC_CONN_BGF_MCU_TCK (MTK_PIN_NO(9) | 6) +#define PINMUX_GPIO9__FUNC_IOBIST9 (MTK_PIN_NO(9) | 8) + +#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define PINMUX_GPIO10__FUNC_SSPM_JTAG_TMS_VCORE (MTK_PIN_NO(10) | 1) +#define PINMUX_GPIO10__FUNC_SCP_JTAG0_TMS_VCORE (MTK_PIN_NO(10) | 2) +#define PINMUX_GPIO10__FUNC_CONN_BGF_MCU_TMS (MTK_PIN_NO(10) | 6) +#define PINMUX_GPIO10__FUNC_IOBIST10 (MTK_PIN_NO(10) | 8) + +#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define PINMUX_GPIO11__FUNC_SSPM_JTAG_TDI_VCORE (MTK_PIN_NO(11) | 1) +#define PINMUX_GPIO11__FUNC_SCP_JTAG0_TDI_VCORE (MTK_PIN_NO(11) | 2) +#define PINMUX_GPIO11__FUNC_CONN_BGF_MCU_TDI (MTK_PIN_NO(11) | 6) +#define PINMUX_GPIO11__FUNC_IOBIST11 (MTK_PIN_NO(11) | 8) + +#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define PINMUX_GPIO12__FUNC_SSPM_JTAG_TDO_VCORE (MTK_PIN_NO(12) | 1) +#define PINMUX_GPIO12__FUNC_SCP_JTAG0_TDO_VCORE (MTK_PIN_NO(12) | 2) +#define PINMUX_GPIO12__FUNC_CONN_BGF_MCU_TDO (MTK_PIN_NO(12) | 6) +#define PINMUX_GPIO12__FUNC_IOBIST12 (MTK_PIN_NO(12) | 8) + +#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define PINMUX_GPIO13__FUNC_TP_GPIO8_AO (MTK_PIN_NO(13) | 1) +#define PINMUX_GPIO13__FUNC_HFRP_JTAG0_TRSTN (MTK_PIN_NO(13) | 2) +#define PINMUX_GPIO13__FUNC_MFG_EB_JTAG_TRSTN (MTK_PIN_NO(13) | 3) +#define PINMUX_GPIO13__FUNC_SSPM_JTAG_TRSTN_VLP (MTK_PIN_NO(13) | 4) +#define PINMUX_GPIO13__FUNC_SPM_JTAG_TRSTN_VLP (MTK_PIN_NO(13) | 5) +#define PINMUX_GPIO13__FUNC_SCP_JTAG0_TRSTN_VLP (MTK_PIN_NO(13) | 6) +#define PINMUX_GPIO13__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(13) | 7) +#define PINMUX_GPIO13__FUNC_IOBIST13 (MTK_PIN_NO(13) | 8) + +#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define PINMUX_GPIO14__FUNC_TP_GPIO9_AO (MTK_PIN_NO(14) | 1) +#define PINMUX_GPIO14__FUNC_HFRP_JTAG0_TCK (MTK_PIN_NO(14) | 2) +#define PINMUX_GPIO14__FUNC_MFG_EB_JTAG_TCK (MTK_PIN_NO(14) | 3) +#define PINMUX_GPIO14__FUNC_SSPM_JTAG_TCK_VLP (MTK_PIN_NO(14) | 4) +#define PINMUX_GPIO14__FUNC_SPM_JTAG_TCK_VLP (MTK_PIN_NO(14) | 5) +#define PINMUX_GPIO14__FUNC_SCP_JTAG0_TCK_VLP (MTK_PIN_NO(14) | 6) +#define PINMUX_GPIO14__FUNC_IO_JTAG_TCK (MTK_PIN_NO(14) | 7) +#define PINMUX_GPIO14__FUNC_IOBIST14 (MTK_PIN_NO(14) | 8) + +#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define PINMUX_GPIO15__FUNC_TP_GPIO10_AO (MTK_PIN_NO(15) | 1) +#define PINMUX_GPIO15__FUNC_HFRP_JTAG0_TMS (MTK_PIN_NO(15) | 2) +#define PINMUX_GPIO15__FUNC_MFG_EB_JTAG_TMS (MTK_PIN_NO(15) | 3) +#define PINMUX_GPIO15__FUNC_SSPM_JTAG_TMS_VLP (MTK_PIN_NO(15) | 4) +#define PINMUX_GPIO15__FUNC_SPM_JTAG_TMS_VLP (MTK_PIN_NO(15) | 5) +#define PINMUX_GPIO15__FUNC_SCP_JTAG0_TMS_VLP (MTK_PIN_NO(15) | 6) +#define PINMUX_GPIO15__FUNC_IO_JTAG_TMS (MTK_PIN_NO(15) | 7) +#define PINMUX_GPIO15__FUNC_IOBIST15 (MTK_PIN_NO(15) | 8) + +#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define PINMUX_GPIO16__FUNC_TP_GPIO11_AO (MTK_PIN_NO(16) | 1) +#define PINMUX_GPIO16__FUNC_HFRP_JTAG0_TDI (MTK_PIN_NO(16) | 2) +#define PINMUX_GPIO16__FUNC_MFG_EB_JTAG_TDI (MTK_PIN_NO(16) | 3) +#define PINMUX_GPIO16__FUNC_SSPM_JTAG_TDI_VLP (MTK_PIN_NO(16) | 4) +#define PINMUX_GPIO16__FUNC_SPM_JTAG_TDI_VLP (MTK_PIN_NO(16) | 5) +#define PINMUX_GPIO16__FUNC_SCP_JTAG0_TDI_VLP (MTK_PIN_NO(16) | 6) +#define PINMUX_GPIO16__FUNC_IO_JTAG_TDI (MTK_PIN_NO(16) | 7) +#define PINMUX_GPIO16__FUNC_IOBIST16 (MTK_PIN_NO(16) | 8) + +#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define PINMUX_GPIO17__FUNC_TP_GPIO12_AO (MTK_PIN_NO(17) | 1) +#define PINMUX_GPIO17__FUNC_HFRP_JTAG0_TDO (MTK_PIN_NO(17) | 2) +#define PINMUX_GPIO17__FUNC_MFG_EB_JTAG_TDO (MTK_PIN_NO(17) | 3) +#define PINMUX_GPIO17__FUNC_SSPM_JTAG_TDO_VLP (MTK_PIN_NO(17) | 4) +#define PINMUX_GPIO17__FUNC_SPM_JTAG_TDO_VLP (MTK_PIN_NO(17) | 5) +#define PINMUX_GPIO17__FUNC_SCP_JTAG0_TDO_VLP (MTK_PIN_NO(17) | 6) +#define PINMUX_GPIO17__FUNC_IO_JTAG_TDO (MTK_PIN_NO(17) | 7) +#define PINMUX_GPIO17__FUNC_IOBIST17 (MTK_PIN_NO(17) | 8) + +#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define PINMUX_GPIO18__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(18) | 1) +#define PINMUX_GPIO18__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(18) | 2) +#define PINMUX_GPIO18__FUNC_IDDIG (MTK_PIN_NO(18) | 5) +#define PINMUX_GPIO18__FUNC_TSFDC_EN (MTK_PIN_NO(18) | 6) +#define PINMUX_GPIO18__FUNC_IOBIST18 (MTK_PIN_NO(18) | 8) + +#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define PINMUX_GPIO19__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(19) | 1) +#define PINMUX_GPIO19__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(19) | 2) +#define PINMUX_GPIO19__FUNC_TP_UTXD2_VCORE (MTK_PIN_NO(19) | 3) +#define PINMUX_GPIO19__FUNC_SSPM_UTXD_AO_VCORE (MTK_PIN_NO(19) | 4) +#define PINMUX_GPIO19__FUNC_MD32_1_TXD (MTK_PIN_NO(19) | 5) +#define PINMUX_GPIO19__FUNC_UTXD2 (MTK_PIN_NO(19) | 6) +#define PINMUX_GPIO19__FUNC_IOBIST19 (MTK_PIN_NO(19) | 8) + +#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define PINMUX_GPIO20__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(20) | 1) +#define PINMUX_GPIO20__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(20) | 2) +#define PINMUX_GPIO20__FUNC_TP_URXD2_VCORE (MTK_PIN_NO(20) | 3) +#define PINMUX_GPIO20__FUNC_SSPM_URXD_AO_VCORE (MTK_PIN_NO(20) | 4) +#define PINMUX_GPIO20__FUNC_MD32_1_RXD (MTK_PIN_NO(20) | 5) +#define PINMUX_GPIO20__FUNC_URXD2 (MTK_PIN_NO(20) | 6) +#define PINMUX_GPIO20__FUNC_IOBIST20 (MTK_PIN_NO(20) | 8) + +#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define PINMUX_GPIO21__FUNC_KPROW1 (MTK_PIN_NO(21) | 1) +#define PINMUX_GPIO21__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(21) | 2) +#define PINMUX_GPIO21__FUNC_CONN_BT_TXD (MTK_PIN_NO(21) | 3) +#define PINMUX_GPIO21__FUNC_HFRP_UTXD1 (MTK_PIN_NO(21) | 4) +#define PINMUX_GPIO21__FUNC_TP_UTXD1_VCORE (MTK_PIN_NO(21) | 5) +#define PINMUX_GPIO21__FUNC_CONN_BGF_UART0_TXD (MTK_PIN_NO(21) | 6) +#define PINMUX_GPIO21__FUNC_MD_UTXD1 (MTK_PIN_NO(21) | 7) +#define PINMUX_GPIO21__FUNC_IOBIST21 (MTK_PIN_NO(21) | 8) + +#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define PINMUX_GPIO22__FUNC_KPCOL1 (MTK_PIN_NO(22) | 1) +#define PINMUX_GPIO22__FUNC_PMSR_SMAP (MTK_PIN_NO(22) | 3) +#define PINMUX_GPIO22__FUNC_HFRP_URXD1 (MTK_PIN_NO(22) | 4) +#define PINMUX_GPIO22__FUNC_TP_URXD1_VCORE (MTK_PIN_NO(22) | 5) +#define PINMUX_GPIO22__FUNC_CONN_BGF_UART0_RXD (MTK_PIN_NO(22) | 6) +#define PINMUX_GPIO22__FUNC_MD_URXD1 (MTK_PIN_NO(22) | 7) +#define PINMUX_GPIO22__FUNC_IOBIST22 (MTK_PIN_NO(22) | 8) + +#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define PINMUX_GPIO23__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(23) | 3) +#define PINMUX_GPIO23__FUNC_USB_DRVVBUS (MTK_PIN_NO(23) | 5) +#define PINMUX_GPIO23__FUNC_DBG_MON_A6 (MTK_PIN_NO(23) | 7) +#define PINMUX_GPIO23__FUNC_IOBIST23 (MTK_PIN_NO(23) | 8) + +#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define PINMUX_GPIO24__FUNC_KPROW0 (MTK_PIN_NO(24) | 1) +#define PINMUX_GPIO24__FUNC_I2SIN2_MCK (MTK_PIN_NO(24) | 2) +#define PINMUX_GPIO24__FUNC_USB_DRVVBUS (MTK_PIN_NO(24) | 5) +#define PINMUX_GPIO24__FUNC_DBG_MON_B0 (MTK_PIN_NO(24) | 7) +#define PINMUX_GPIO24__FUNC_IOBIST24 (MTK_PIN_NO(24) | 8) + +#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define PINMUX_GPIO25__FUNC_PWM_3 (MTK_PIN_NO(25) | 4) +#define PINMUX_GPIO25__FUNC_DBG_MON_A8 (MTK_PIN_NO(25) | 7) +#define PINMUX_GPIO25__FUNC_IOBIST25 (MTK_PIN_NO(25) | 8) + +#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define PINMUX_GPIO26__FUNC_CMFLASH0 (MTK_PIN_NO(26) | 1) +#define PINMUX_GPIO26__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(26) | 2) +#define PINMUX_GPIO26__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(26) | 3) +#define PINMUX_GPIO26__FUNC_PWM_0 (MTK_PIN_NO(26) | 4) +#define PINMUX_GPIO26__FUNC_VBUSVALID (MTK_PIN_NO(26) | 5) +#define PINMUX_GPIO26__FUNC_IOBIST26 (MTK_PIN_NO(26) | 8) + +#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define PINMUX_GPIO27__FUNC_CMFLASH1 (MTK_PIN_NO(27) | 1) +#define PINMUX_GPIO27__FUNC_DAP_SONIC_SWCK (MTK_PIN_NO(27) | 6) +#define PINMUX_GPIO27__FUNC_DBG_MON_A10 (MTK_PIN_NO(27) | 7) +#define PINMUX_GPIO27__FUNC_IOBIST27 (MTK_PIN_NO(27) | 8) + +#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define PINMUX_GPIO28__FUNC_CMFLASH2 (MTK_PIN_NO(28) | 1) +#define PINMUX_GPIO28__FUNC_GPS_PPS (MTK_PIN_NO(28) | 4) +#define PINMUX_GPIO28__FUNC_DAP_SONIC_SWD (MTK_PIN_NO(28) | 6) +#define PINMUX_GPIO28__FUNC_DBG_MON_A11 (MTK_PIN_NO(28) | 7) +#define PINMUX_GPIO28__FUNC_IOBIST28 (MTK_PIN_NO(28) | 8) + +#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define PINMUX_GPIO29__FUNC_CMFLASH3 (MTK_PIN_NO(29) | 1) +#define PINMUX_GPIO29__FUNC_SCL10 (MTK_PIN_NO(29) | 3) +#define PINMUX_GPIO29__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(29) | 6) +#define PINMUX_GPIO29__FUNC_DBG_MON_A12 (MTK_PIN_NO(29) | 7) +#define PINMUX_GPIO29__FUNC_IOBIST29 (MTK_PIN_NO(29) | 8) + +#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define PINMUX_GPIO30__FUNC_SDA10 (MTK_PIN_NO(30) | 3) +#define PINMUX_GPIO30__FUNC_DAP_MD32_SWD (MTK_PIN_NO(30) | 6) +#define PINMUX_GPIO30__FUNC_DBG_MON_A13 (MTK_PIN_NO(30) | 7) +#define PINMUX_GPIO30__FUNC_IOBIST30 (MTK_PIN_NO(30) | 8) + +#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define PINMUX_GPIO31__FUNC_CMVREF0 (MTK_PIN_NO(31) | 1) +#define PINMUX_GPIO31__FUNC_SCL12 (MTK_PIN_NO(31) | 3) +#define PINMUX_GPIO31__FUNC_DBG_MON_A14 (MTK_PIN_NO(31) | 7) +#define PINMUX_GPIO31__FUNC_IOBIST31 (MTK_PIN_NO(31) | 8) + +#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define PINMUX_GPIO32__FUNC_CMVREF1 (MTK_PIN_NO(32) | 1) +#define PINMUX_GPIO32__FUNC_SDA12 (MTK_PIN_NO(32) | 3) +#define PINMUX_GPIO32__FUNC_DBG_MON_A15 (MTK_PIN_NO(32) | 7) +#define PINMUX_GPIO32__FUNC_IOBIST32 (MTK_PIN_NO(32) | 8) + +#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define PINMUX_GPIO33__FUNC_CMVREF2 (MTK_PIN_NO(33) | 1) +#define PINMUX_GPIO33__FUNC_USB_DRVVBUS (MTK_PIN_NO(33) | 3) +#define PINMUX_GPIO33__FUNC_DBG_MON_A16 (MTK_PIN_NO(33) | 7) +#define PINMUX_GPIO33__FUNC_IOBIST33 (MTK_PIN_NO(33) | 8) + +#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define PINMUX_GPIO34__FUNC_CMVREF3 (MTK_PIN_NO(34) | 1) +#define PINMUX_GPIO34__FUNC_VBUSVALID (MTK_PIN_NO(34) | 3) +#define PINMUX_GPIO34__FUNC_DBG_MON_A17 (MTK_PIN_NO(34) | 7) +#define PINMUX_GPIO34__FUNC_IOBIST34 (MTK_PIN_NO(34) | 8) + +#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define PINMUX_GPIO35__FUNC_CMVREF4 (MTK_PIN_NO(35) | 1) +#define PINMUX_GPIO35__FUNC_IDDIG (MTK_PIN_NO(35) | 3) +#define PINMUX_GPIO35__FUNC_DBG_MON_A18 (MTK_PIN_NO(35) | 7) +#define PINMUX_GPIO35__FUNC_IOBIST35 (MTK_PIN_NO(35) | 8) + +#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define PINMUX_GPIO36__FUNC_CMMCLK0 (MTK_PIN_NO(36) | 1) +#define PINMUX_GPIO36__FUNC_CLKM0 (MTK_PIN_NO(36) | 2) +#define PINMUX_GPIO36__FUNC_DBG_MON_A19 (MTK_PIN_NO(36) | 7) +#define PINMUX_GPIO36__FUNC_IOBIST36 (MTK_PIN_NO(36) | 8) + +#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define PINMUX_GPIO37__FUNC_CMMCLK1 (MTK_PIN_NO(37) | 1) +#define PINMUX_GPIO37__FUNC_CLKM1 (MTK_PIN_NO(37) | 2) +#define PINMUX_GPIO37__FUNC_MD32_1_GPIO0 (MTK_PIN_NO(37) | 4) +#define PINMUX_GPIO37__FUNC_DBG_MON_A20 (MTK_PIN_NO(37) | 7) +#define PINMUX_GPIO37__FUNC_IOBIST37 (MTK_PIN_NO(37) | 8) + +#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define PINMUX_GPIO38__FUNC_CMMCLK2 (MTK_PIN_NO(38) | 1) +#define PINMUX_GPIO38__FUNC_CLKM2 (MTK_PIN_NO(38) | 2) +#define PINMUX_GPIO38__FUNC_DBG_MON_A21 (MTK_PIN_NO(38) | 7) +#define PINMUX_GPIO38__FUNC_IOBIST38 (MTK_PIN_NO(38) | 8) + +#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define PINMUX_GPIO39__FUNC_CMMCLK3 (MTK_PIN_NO(39) | 1) +#define PINMUX_GPIO39__FUNC_CLKM3 (MTK_PIN_NO(39) | 2) +#define PINMUX_GPIO39__FUNC_DBG_MON_A22 (MTK_PIN_NO(39) | 7) +#define PINMUX_GPIO39__FUNC_IOBIST39 (MTK_PIN_NO(39) | 8) + +#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define PINMUX_GPIO40__FUNC_I2SIN1_MCK (MTK_PIN_NO(40) | 1) +#define PINMUX_GPIO40__FUNC_IDDIG (MTK_PIN_NO(40) | 2) +#define PINMUX_GPIO40__FUNC_IRRX_IN (MTK_PIN_NO(40) | 3) +#define PINMUX_GPIO40__FUNC_GPS_PPS (MTK_PIN_NO(40) | 4) +#define PINMUX_GPIO40__FUNC_ANT_SEL8 (MTK_PIN_NO(40) | 6) +#define PINMUX_GPIO40__FUNC_IOBIST40 (MTK_PIN_NO(40) | 8) + +#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define PINMUX_GPIO41__FUNC_I2SIN1_BCK (MTK_PIN_NO(41) | 1) +#define PINMUX_GPIO41__FUNC_CONN_WF_MCU_AICE_TMSC (MTK_PIN_NO(41) | 4) +#define PINMUX_GPIO41__FUNC_ANT_SEL9 (MTK_PIN_NO(41) | 6) +#define PINMUX_GPIO41__FUNC_IOBIST41 (MTK_PIN_NO(41) | 8) + +#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define PINMUX_GPIO42__FUNC_I2SIN1_LRCK (MTK_PIN_NO(42) | 1) +#define PINMUX_GPIO42__FUNC_CONN_WF_MCU_AICE_TCKC (MTK_PIN_NO(42) | 4) +#define PINMUX_GPIO42__FUNC_ANT_SEL10 (MTK_PIN_NO(42) | 6) +#define PINMUX_GPIO42__FUNC_IOBIST42 (MTK_PIN_NO(42) | 8) + +#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define PINMUX_GPIO43__FUNC_I2SOUT1_DO (MTK_PIN_NO(43) | 1) +#define PINMUX_GPIO43__FUNC_CONN_BGF_MCU_AICE_TMSC (MTK_PIN_NO(43) | 4) +#define PINMUX_GPIO43__FUNC_ANT_SEL11 (MTK_PIN_NO(43) | 6) +#define PINMUX_GPIO43__FUNC_IOBIST43 (MTK_PIN_NO(43) | 8) + +#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define PINMUX_GPIO44__FUNC_I2SIN1_DI (MTK_PIN_NO(44) | 1) +#define PINMUX_GPIO44__FUNC_CONN_BGF_MCU_AICE_TCKC (MTK_PIN_NO(44) | 4) +#define PINMUX_GPIO44__FUNC_ANT_SEL12 (MTK_PIN_NO(44) | 6) +#define PINMUX_GPIO44__FUNC_IOBIST44 (MTK_PIN_NO(44) | 8) + +#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define PINMUX_GPIO45__FUNC_I2SIN2_BCK (MTK_PIN_NO(45) | 1) +#define PINMUX_GPIO45__FUNC_SCL11 (MTK_PIN_NO(45) | 2) +#define PINMUX_GPIO45__FUNC_BPI_BUS10 (MTK_PIN_NO(45) | 3) +#define PINMUX_GPIO45__FUNC_MD_UCTS0 (MTK_PIN_NO(45) | 4) +#define PINMUX_GPIO45__FUNC_TP_UCTS1_VCORE (MTK_PIN_NO(45) | 5) +#define PINMUX_GPIO45__FUNC_HFRP_UCTS1 (MTK_PIN_NO(45) | 6) +#define PINMUX_GPIO45__FUNC_DBG_MON_B1 (MTK_PIN_NO(45) | 7) +#define PINMUX_GPIO45__FUNC_IOBIST45 (MTK_PIN_NO(45) | 8) + +#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define PINMUX_GPIO46__FUNC_I2SIN2_LRCK (MTK_PIN_NO(46) | 1) +#define PINMUX_GPIO46__FUNC_SDA11 (MTK_PIN_NO(46) | 2) +#define PINMUX_GPIO46__FUNC_BPI_BUS11 (MTK_PIN_NO(46) | 3) +#define PINMUX_GPIO46__FUNC_MD_URTS0 (MTK_PIN_NO(46) | 4) +#define PINMUX_GPIO46__FUNC_TP_URTS1_VCORE (MTK_PIN_NO(46) | 5) +#define PINMUX_GPIO46__FUNC_HFRP_URTS1 (MTK_PIN_NO(46) | 6) +#define PINMUX_GPIO46__FUNC_DBG_MON_B2 (MTK_PIN_NO(46) | 7) +#define PINMUX_GPIO46__FUNC_IOBIST46 (MTK_PIN_NO(46) | 8) + +#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define PINMUX_GPIO47__FUNC_I2SOUT2_DO (MTK_PIN_NO(47) | 1) +#define PINMUX_GPIO47__FUNC_SCL1 (MTK_PIN_NO(47) | 2) +#define PINMUX_GPIO47__FUNC_BPI_BUS12 (MTK_PIN_NO(47) | 3) +#define PINMUX_GPIO47__FUNC_MD_UCTS1 (MTK_PIN_NO(47) | 4) +#define PINMUX_GPIO47__FUNC_TP_UCTS2_VCORE (MTK_PIN_NO(47) | 5) +#define PINMUX_GPIO47__FUNC_UCTS2 (MTK_PIN_NO(47) | 6) +#define PINMUX_GPIO47__FUNC_DBG_MON_B3 (MTK_PIN_NO(47) | 7) +#define PINMUX_GPIO47__FUNC_IOBIST47 (MTK_PIN_NO(47) | 8) + +#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define PINMUX_GPIO48__FUNC_I2SIN2_DI (MTK_PIN_NO(48) | 1) +#define PINMUX_GPIO48__FUNC_SDA1 (MTK_PIN_NO(48) | 2) +#define PINMUX_GPIO48__FUNC_BPI_BUS13 (MTK_PIN_NO(48) | 3) +#define PINMUX_GPIO48__FUNC_MD_URTS1 (MTK_PIN_NO(48) | 4) +#define PINMUX_GPIO48__FUNC_TP_URTS2_VCORE (MTK_PIN_NO(48) | 5) +#define PINMUX_GPIO48__FUNC_URTS2 (MTK_PIN_NO(48) | 6) +#define PINMUX_GPIO48__FUNC_DBG_MON_B4 (MTK_PIN_NO(48) | 7) +#define PINMUX_GPIO48__FUNC_IOBIST48 (MTK_PIN_NO(48) | 8) + +#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define PINMUX_GPIO49__FUNC_UTXD0 (MTK_PIN_NO(49) | 1) +#define PINMUX_GPIO49__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(49) | 2) +#define PINMUX_GPIO49__FUNC_MD_UTXD1 (MTK_PIN_NO(49) | 3) +#define PINMUX_GPIO49__FUNC_HFRP_UTXD1 (MTK_PIN_NO(49) | 4) +#define PINMUX_GPIO49__FUNC_MD32_0_TXD (MTK_PIN_NO(49) | 5) +#define PINMUX_GPIO49__FUNC_PTA_TXD (MTK_PIN_NO(49) | 6) +#define PINMUX_GPIO49__FUNC_IOBIST49 (MTK_PIN_NO(49) | 8) + +#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define PINMUX_GPIO50__FUNC_URXD0 (MTK_PIN_NO(50) | 1) +#define PINMUX_GPIO50__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(50) | 2) +#define PINMUX_GPIO50__FUNC_MD_URXD1 (MTK_PIN_NO(50) | 3) +#define PINMUX_GPIO50__FUNC_HFRP_URXD1 (MTK_PIN_NO(50) | 4) +#define PINMUX_GPIO50__FUNC_MD32_0_RXD (MTK_PIN_NO(50) | 5) +#define PINMUX_GPIO50__FUNC_PTA_RXD (MTK_PIN_NO(50) | 6) +#define PINMUX_GPIO50__FUNC_IOBIST50 (MTK_PIN_NO(50) | 8) + +#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define PINMUX_GPIO51__FUNC_UTXD1 (MTK_PIN_NO(51) | 1) +#define PINMUX_GPIO51__FUNC_TP_UTXD1_VLP (MTK_PIN_NO(51) | 2) +#define PINMUX_GPIO51__FUNC_TP_UTXD2_VLP (MTK_PIN_NO(51) | 3) +#define PINMUX_GPIO51__FUNC_CONN_BGF_UART0_TXD (MTK_PIN_NO(51) | 4) +#define PINMUX_GPIO51__FUNC_SSPM_UTXD_AO_VLP (MTK_PIN_NO(51) | 5) +#define PINMUX_GPIO51__FUNC_MD_MCIF_UTXD0 (MTK_PIN_NO(51) | 6) +#define PINMUX_GPIO51__FUNC_MD_UTXD0 (MTK_PIN_NO(51) | 7) +#define PINMUX_GPIO51__FUNC_IOBIST51 (MTK_PIN_NO(51) | 8) + +#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define PINMUX_GPIO52__FUNC_URXD1 (MTK_PIN_NO(52) | 1) +#define PINMUX_GPIO52__FUNC_TP_URXD1_VLP (MTK_PIN_NO(52) | 2) +#define PINMUX_GPIO52__FUNC_TP_URXD2_VLP (MTK_PIN_NO(52) | 3) +#define PINMUX_GPIO52__FUNC_CONN_BGF_UART0_RXD (MTK_PIN_NO(52) | 4) +#define PINMUX_GPIO52__FUNC_SSPM_URXD_AO_VLP (MTK_PIN_NO(52) | 5) +#define PINMUX_GPIO52__FUNC_MD_MCIF_URXD0 (MTK_PIN_NO(52) | 6) +#define PINMUX_GPIO52__FUNC_MD_URXD0 (MTK_PIN_NO(52) | 7) +#define PINMUX_GPIO52__FUNC_IOBIST52 (MTK_PIN_NO(52) | 8) + +#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define PINMUX_GPIO53__FUNC_JTRSTN_SEL1_VCORE (MTK_PIN_NO(53) | 1) +#define PINMUX_GPIO53__FUNC_SPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(53) | 2) +#define PINMUX_GPIO53__FUNC_IOBIST53 (MTK_PIN_NO(53) | 8) + +#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define PINMUX_GPIO54__FUNC_JTCK_SEL1_VCORE (MTK_PIN_NO(54) | 1) +#define PINMUX_GPIO54__FUNC_SPM_JTAG_TCK_VCORE (MTK_PIN_NO(54) | 2) +#define PINMUX_GPIO54__FUNC_IOBIST54 (MTK_PIN_NO(54) | 8) + +#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define PINMUX_GPIO55__FUNC_JTMS_SEL1_VCORE (MTK_PIN_NO(55) | 1) +#define PINMUX_GPIO55__FUNC_SPM_JTAG_TMS_VCORE (MTK_PIN_NO(55) | 2) +#define PINMUX_GPIO55__FUNC_IOBIST55 (MTK_PIN_NO(55) | 8) + +#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define PINMUX_GPIO56__FUNC_JTDI_SEL1_VCORE (MTK_PIN_NO(56) | 1) +#define PINMUX_GPIO56__FUNC_SPM_JTAG_TDI_VCORE (MTK_PIN_NO(56) | 2) +#define PINMUX_GPIO56__FUNC_IOBIST56 (MTK_PIN_NO(56) | 8) + +#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define PINMUX_GPIO57__FUNC_JTDO_SEL1_VCORE (MTK_PIN_NO(57) | 1) +#define PINMUX_GPIO57__FUNC_SPM_JTAG_TDO_VCORE (MTK_PIN_NO(57) | 2) +#define PINMUX_GPIO57__FUNC_IOBIST57 (MTK_PIN_NO(57) | 8) + +#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define PINMUX_GPIO58__FUNC_SPI4_CLK (MTK_PIN_NO(58) | 1) +#define PINMUX_GPIO58__FUNC_MD_UTXD0 (MTK_PIN_NO(58) | 2) +#define PINMUX_GPIO58__FUNC_UTXD2 (MTK_PIN_NO(58) | 3) +#define PINMUX_GPIO58__FUNC_TP_UTXD1_VCORE (MTK_PIN_NO(58) | 4) +#define PINMUX_GPIO58__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(58) | 5) +#define PINMUX_GPIO58__FUNC_EXTIF0_ACT (MTK_PIN_NO(58) | 6) +#define PINMUX_GPIO58__FUNC_DAP_SONIC_SWCK (MTK_PIN_NO(58) | 7) +#define PINMUX_GPIO58__FUNC_IOBIST58 (MTK_PIN_NO(58) | 8) + +#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define PINMUX_GPIO59__FUNC_SPI4_CSB (MTK_PIN_NO(59) | 1) +#define PINMUX_GPIO59__FUNC_MD_URXD0 (MTK_PIN_NO(59) | 2) +#define PINMUX_GPIO59__FUNC_URXD2 (MTK_PIN_NO(59) | 3) +#define PINMUX_GPIO59__FUNC_TP_URXD1_VCORE (MTK_PIN_NO(59) | 4) +#define PINMUX_GPIO59__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(59) | 5) +#define PINMUX_GPIO59__FUNC_EXTIF0_PRI (MTK_PIN_NO(59) | 6) +#define PINMUX_GPIO59__FUNC_DAP_SONIC_SWD (MTK_PIN_NO(59) | 7) +#define PINMUX_GPIO59__FUNC_IOBIST59 (MTK_PIN_NO(59) | 8) + +#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define PINMUX_GPIO60__FUNC_SPI4_MO (MTK_PIN_NO(60) | 1) +#define PINMUX_GPIO60__FUNC_EXTIF0_GNT_B (MTK_PIN_NO(60) | 6) +#define PINMUX_GPIO60__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(60) | 7) +#define PINMUX_GPIO60__FUNC_IOBIST60 (MTK_PIN_NO(60) | 8) + +#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define PINMUX_GPIO61__FUNC_SPI4_MI (MTK_PIN_NO(61) | 1) +#define PINMUX_GPIO61__FUNC_DAP_MD32_SWD (MTK_PIN_NO(61) | 7) +#define PINMUX_GPIO61__FUNC_IOBIST61 (MTK_PIN_NO(61) | 8) + +#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define PINMUX_GPIO62__FUNC_SCP_SPI1_CK (MTK_PIN_NO(62) | 1) +#define PINMUX_GPIO62__FUNC_SPI1_CLK (MTK_PIN_NO(62) | 2) +#define PINMUX_GPIO62__FUNC_TP_UTXD1_VLP (MTK_PIN_NO(62) | 3) +#define PINMUX_GPIO62__FUNC_TP_GPIO0_AO (MTK_PIN_NO(62) | 5) +#define PINMUX_GPIO62__FUNC_UTXD0 (MTK_PIN_NO(62) | 6) +#define PINMUX_GPIO62__FUNC_DBG_MON_A25 (MTK_PIN_NO(62) | 7) +#define PINMUX_GPIO62__FUNC_IOBIST62 (MTK_PIN_NO(62) | 8) + +#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define PINMUX_GPIO63__FUNC_SCP_SPI1_CS (MTK_PIN_NO(63) | 1) +#define PINMUX_GPIO63__FUNC_SPI1_CSB (MTK_PIN_NO(63) | 2) +#define PINMUX_GPIO63__FUNC_TP_URXD1_VLP (MTK_PIN_NO(63) | 3) +#define PINMUX_GPIO63__FUNC_TP_GPIO1_AO (MTK_PIN_NO(63) | 5) +#define PINMUX_GPIO63__FUNC_URXD0 (MTK_PIN_NO(63) | 6) +#define PINMUX_GPIO63__FUNC_DBG_MON_A26 (MTK_PIN_NO(63) | 7) +#define PINMUX_GPIO63__FUNC_IOBIST63 (MTK_PIN_NO(63) | 8) + +#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define PINMUX_GPIO64__FUNC_SCP_SPI1_MO (MTK_PIN_NO(64) | 1) +#define PINMUX_GPIO64__FUNC_SPI1_MO (MTK_PIN_NO(64) | 2) +#define PINMUX_GPIO64__FUNC_TP_GPIO2_AO (MTK_PIN_NO(64) | 5) +#define PINMUX_GPIO64__FUNC_DBG_MON_A9 (MTK_PIN_NO(64) | 7) +#define PINMUX_GPIO64__FUNC_IOBIST64 (MTK_PIN_NO(64) | 8) + +#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define PINMUX_GPIO65__FUNC_SCP_SPI1_MI (MTK_PIN_NO(65) | 1) +#define PINMUX_GPIO65__FUNC_SPI1_MI (MTK_PIN_NO(65) | 2) +#define PINMUX_GPIO65__FUNC_TP_GPIO3_AO (MTK_PIN_NO(65) | 5) +#define PINMUX_GPIO65__FUNC_IOBIST65 (MTK_PIN_NO(65) | 8) + +#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define PINMUX_GPIO66__FUNC_SCP_SPI2_CK (MTK_PIN_NO(66) | 1) +#define PINMUX_GPIO66__FUNC_SPI2_CLK (MTK_PIN_NO(66) | 2) +#define PINMUX_GPIO66__FUNC_TP_GPIO4_AO (MTK_PIN_NO(66) | 5) +#define PINMUX_GPIO66__FUNC_UTXD1 (MTK_PIN_NO(66) | 6) +#define PINMUX_GPIO66__FUNC_DBG_MON_B13 (MTK_PIN_NO(66) | 7) +#define PINMUX_GPIO66__FUNC_IOBIST66 (MTK_PIN_NO(66) | 8) + +#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define PINMUX_GPIO67__FUNC_SCP_SPI2_CS (MTK_PIN_NO(67) | 1) +#define PINMUX_GPIO67__FUNC_SPI2_CSB (MTK_PIN_NO(67) | 2) +#define PINMUX_GPIO67__FUNC_TP_GPIO5_AO (MTK_PIN_NO(67) | 5) +#define PINMUX_GPIO67__FUNC_URXD1 (MTK_PIN_NO(67) | 6) +#define PINMUX_GPIO67__FUNC_DBG_MON_B14 (MTK_PIN_NO(67) | 7) +#define PINMUX_GPIO67__FUNC_IOBIST67 (MTK_PIN_NO(67) | 8) + +#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define PINMUX_GPIO68__FUNC_SCP_SPI2_MO (MTK_PIN_NO(68) | 1) +#define PINMUX_GPIO68__FUNC_SPI2_MO (MTK_PIN_NO(68) | 2) +#define PINMUX_GPIO68__FUNC_TP_GPIO6_AO (MTK_PIN_NO(68) | 5) +#define PINMUX_GPIO68__FUNC_DBG_MON_B15 (MTK_PIN_NO(68) | 7) +#define PINMUX_GPIO68__FUNC_IOBIST68 (MTK_PIN_NO(68) | 8) + +#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define PINMUX_GPIO69__FUNC_SCP_SPI2_MI (MTK_PIN_NO(69) | 1) +#define PINMUX_GPIO69__FUNC_SPI2_MI (MTK_PIN_NO(69) | 2) +#define PINMUX_GPIO69__FUNC_TP_GPIO7_AO (MTK_PIN_NO(69) | 5) +#define PINMUX_GPIO69__FUNC_DBG_MON_B16 (MTK_PIN_NO(69) | 7) +#define PINMUX_GPIO69__FUNC_IOBIST69 (MTK_PIN_NO(69) | 8) + +#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define PINMUX_GPIO70__FUNC_SCP_SPI3_CK (MTK_PIN_NO(70) | 1) +#define PINMUX_GPIO70__FUNC_SPI3_CLK (MTK_PIN_NO(70) | 2) +#define PINMUX_GPIO70__FUNC_MD_INT4 (MTK_PIN_NO(70) | 3) +#define PINMUX_GPIO70__FUNC_TP_GPIO8_AO (MTK_PIN_NO(70) | 5) +#define PINMUX_GPIO70__FUNC_DBG_MON_B17 (MTK_PIN_NO(70) | 7) +#define PINMUX_GPIO70__FUNC_IOBIST70 (MTK_PIN_NO(70) | 8) + +#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define PINMUX_GPIO71__FUNC_SCP_SPI3_CS (MTK_PIN_NO(71) | 1) +#define PINMUX_GPIO71__FUNC_SPI3_CSB (MTK_PIN_NO(71) | 2) +#define PINMUX_GPIO71__FUNC_MD_INT3 (MTK_PIN_NO(71) | 3) +#define PINMUX_GPIO71__FUNC_TP_GPIO9_AO (MTK_PIN_NO(71) | 5) +#define PINMUX_GPIO71__FUNC_DBG_MON_B18 (MTK_PIN_NO(71) | 7) +#define PINMUX_GPIO71__FUNC_IOBIST71 (MTK_PIN_NO(71) | 8) + +#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define PINMUX_GPIO72__FUNC_SCP_SPI3_MO (MTK_PIN_NO(72) | 1) +#define PINMUX_GPIO72__FUNC_SPI3_MO (MTK_PIN_NO(72) | 2) +#define PINMUX_GPIO72__FUNC_TP_GPIO10_AO (MTK_PIN_NO(72) | 5) +#define PINMUX_GPIO72__FUNC_DBG_MON_B19 (MTK_PIN_NO(72) | 7) +#define PINMUX_GPIO72__FUNC_IOBIST72 (MTK_PIN_NO(72) | 8) + +#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define PINMUX_GPIO73__FUNC_SCP_SPI3_MI (MTK_PIN_NO(73) | 1) +#define PINMUX_GPIO73__FUNC_SPI3_MI (MTK_PIN_NO(73) | 2) +#define PINMUX_GPIO73__FUNC_TP_GPIO11_AO (MTK_PIN_NO(73) | 5) +#define PINMUX_GPIO73__FUNC_DBG_MON_B20 (MTK_PIN_NO(73) | 7) +#define PINMUX_GPIO73__FUNC_IOBIST73 (MTK_PIN_NO(73) | 8) + +#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define PINMUX_GPIO74__FUNC_SCP_SPI0_CK (MTK_PIN_NO(74) | 1) +#define PINMUX_GPIO74__FUNC_SPI0_CLK (MTK_PIN_NO(74) | 2) +#define PINMUX_GPIO74__FUNC_MD_INT0 (MTK_PIN_NO(74) | 3) +#define PINMUX_GPIO74__FUNC_BPI_BUS14 (MTK_PIN_NO(74) | 4) +#define PINMUX_GPIO74__FUNC_TP_GPIO12_AO (MTK_PIN_NO(74) | 5) +#define PINMUX_GPIO74__FUNC_DBG_MON_B5 (MTK_PIN_NO(74) | 7) +#define PINMUX_GPIO74__FUNC_IOBIST74 (MTK_PIN_NO(74) | 8) + +#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define PINMUX_GPIO75__FUNC_SCP_SPI0_CS (MTK_PIN_NO(75) | 1) +#define PINMUX_GPIO75__FUNC_SPI0_CSB (MTK_PIN_NO(75) | 2) +#define PINMUX_GPIO75__FUNC_BPI_BUS15 (MTK_PIN_NO(75) | 4) +#define PINMUX_GPIO75__FUNC_TP_GPIO13_AO (MTK_PIN_NO(75) | 5) +#define PINMUX_GPIO75__FUNC_DBG_MON_B6 (MTK_PIN_NO(75) | 7) +#define PINMUX_GPIO75__FUNC_IOBIST75 (MTK_PIN_NO(75) | 8) + +#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define PINMUX_GPIO76__FUNC_SCP_SPI0_MO (MTK_PIN_NO(76) | 1) +#define PINMUX_GPIO76__FUNC_SPI0_MO (MTK_PIN_NO(76) | 2) +#define PINMUX_GPIO76__FUNC_BPI_BUS16 (MTK_PIN_NO(76) | 4) +#define PINMUX_GPIO76__FUNC_TP_GPIO14_AO (MTK_PIN_NO(76) | 5) +#define PINMUX_GPIO76__FUNC_DBG_MON_B7 (MTK_PIN_NO(76) | 7) +#define PINMUX_GPIO76__FUNC_IOBIST76 (MTK_PIN_NO(76) | 8) + +#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define PINMUX_GPIO77__FUNC_SCP_SPI0_MI (MTK_PIN_NO(77) | 1) +#define PINMUX_GPIO77__FUNC_SPI0_MI (MTK_PIN_NO(77) | 2) +#define PINMUX_GPIO77__FUNC_BPI_BUS17 (MTK_PIN_NO(77) | 4) +#define PINMUX_GPIO77__FUNC_TP_GPIO15_AO (MTK_PIN_NO(77) | 5) +#define PINMUX_GPIO77__FUNC_DBG_MON_B8 (MTK_PIN_NO(77) | 7) +#define PINMUX_GPIO77__FUNC_IOBIST77 (MTK_PIN_NO(77) | 8) + +#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define PINMUX_GPIO78__FUNC_SPI5_CLK (MTK_PIN_NO(78) | 1) +#define PINMUX_GPIO78__FUNC_MD32_0_TXD (MTK_PIN_NO(78) | 2) +#define PINMUX_GPIO78__FUNC_PTA_TXD (MTK_PIN_NO(78) | 3) +#define PINMUX_GPIO78__FUNC_TP_UTXD2_VCORE (MTK_PIN_NO(78) | 4) +#define PINMUX_GPIO78__FUNC_SSPM_UTXD_AO_VCORE (MTK_PIN_NO(78) | 5) +#define PINMUX_GPIO78__FUNC_UTXD2 (MTK_PIN_NO(78) | 6) +#define PINMUX_GPIO78__FUNC_DBG_MON_B21 (MTK_PIN_NO(78) | 7) +#define PINMUX_GPIO78__FUNC_IOBIST78 (MTK_PIN_NO(78) | 8) + +#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define PINMUX_GPIO79__FUNC_SPI5_CSB (MTK_PIN_NO(79) | 1) +#define PINMUX_GPIO79__FUNC_MD32_0_RXD (MTK_PIN_NO(79) | 2) +#define PINMUX_GPIO79__FUNC_PTA_RXD (MTK_PIN_NO(79) | 3) +#define PINMUX_GPIO79__FUNC_TP_URXD2_VCORE (MTK_PIN_NO(79) | 4) +#define PINMUX_GPIO79__FUNC_SSPM_URXD_AO_VCORE (MTK_PIN_NO(79) | 5) +#define PINMUX_GPIO79__FUNC_URXD2 (MTK_PIN_NO(79) | 6) +#define PINMUX_GPIO79__FUNC_DBG_MON_B22 (MTK_PIN_NO(79) | 7) +#define PINMUX_GPIO79__FUNC_IOBIST79 (MTK_PIN_NO(79) | 8) + +#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define PINMUX_GPIO80__FUNC_SPI5_MO (MTK_PIN_NO(80) | 1) +#define PINMUX_GPIO80__FUNC_DBG_MON_B23 (MTK_PIN_NO(80) | 7) +#define PINMUX_GPIO80__FUNC_IOBIST80 (MTK_PIN_NO(80) | 8) + +#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define PINMUX_GPIO81__FUNC_SPI5_MI (MTK_PIN_NO(81) | 1) +#define PINMUX_GPIO81__FUNC_DBG_MON_B24 (MTK_PIN_NO(81) | 7) +#define PINMUX_GPIO81__FUNC_IOBIST81 (MTK_PIN_NO(81) | 8) + +#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define PINMUX_GPIO82__FUNC_MSDC1_CLK (MTK_PIN_NO(82) | 1) +#define PINMUX_GPIO82__FUNC_MFG_EB_JTAG_TCK (MTK_PIN_NO(82) | 2) +#define PINMUX_GPIO82__FUNC_UDI_TCK (MTK_PIN_NO(82) | 3) +#define PINMUX_GPIO82__FUNC_CONN_DSP_JCK (MTK_PIN_NO(82) | 4) +#define PINMUX_GPIO82__FUNC_IOBIST82 (MTK_PIN_NO(82) | 8) + +#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define PINMUX_GPIO83__FUNC_MSDC1_CMD (MTK_PIN_NO(83) | 1) +#define PINMUX_GPIO83__FUNC_MFG_EB_JTAG_TMS (MTK_PIN_NO(83) | 2) +#define PINMUX_GPIO83__FUNC_UDI_TMS (MTK_PIN_NO(83) | 3) +#define PINMUX_GPIO83__FUNC_CONN_DSP_JMS (MTK_PIN_NO(83) | 4) +#define PINMUX_GPIO83__FUNC_TSFDC_VCO_RST (MTK_PIN_NO(83) | 6) +#define PINMUX_GPIO83__FUNC_IOBIST83 (MTK_PIN_NO(83) | 8) + +#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define PINMUX_GPIO84__FUNC_MSDC1_DAT0 (MTK_PIN_NO(84) | 1) +#define PINMUX_GPIO84__FUNC_MFG_EB_JTAG_TDI (MTK_PIN_NO(84) | 2) +#define PINMUX_GPIO84__FUNC_UDI_TDI (MTK_PIN_NO(84) | 3) +#define PINMUX_GPIO84__FUNC_CONN_DSP_JDI (MTK_PIN_NO(84) | 4) +#define PINMUX_GPIO84__FUNC_TSFDC_TSSEL2 (MTK_PIN_NO(84) | 6) +#define PINMUX_GPIO84__FUNC_IOBIST84 (MTK_PIN_NO(84) | 8) + +#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define PINMUX_GPIO85__FUNC_MSDC1_DAT1 (MTK_PIN_NO(85) | 1) +#define PINMUX_GPIO85__FUNC_MFG_EB_JTAG_TDO (MTK_PIN_NO(85) | 2) +#define PINMUX_GPIO85__FUNC_UDI_TDO (MTK_PIN_NO(85) | 3) +#define PINMUX_GPIO85__FUNC_CONN_DSP_JDO (MTK_PIN_NO(85) | 4) +#define PINMUX_GPIO85__FUNC_TSFDC_TSSEL1 (MTK_PIN_NO(85) | 6) +#define PINMUX_GPIO85__FUNC_IOBIST85 (MTK_PIN_NO(85) | 8) + +#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define PINMUX_GPIO86__FUNC_MSDC1_DAT2 (MTK_PIN_NO(86) | 1) +#define PINMUX_GPIO86__FUNC_MFG_EB_JTAG_TRSTN (MTK_PIN_NO(86) | 2) +#define PINMUX_GPIO86__FUNC_UDI_NTRST (MTK_PIN_NO(86) | 3) +#define PINMUX_GPIO86__FUNC_TSFDC_TSSEL0 (MTK_PIN_NO(86) | 6) +#define PINMUX_GPIO86__FUNC_IOBIST86 (MTK_PIN_NO(86) | 8) + +#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define PINMUX_GPIO87__FUNC_MSDC1_DAT3 (MTK_PIN_NO(87) | 1) +#define PINMUX_GPIO87__FUNC_IRRX_IN (MTK_PIN_NO(87) | 2) +#define PINMUX_GPIO87__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(87) | 4) +#define PINMUX_GPIO87__FUNC_TSFDC_RCK_SELB (MTK_PIN_NO(87) | 6) +#define PINMUX_GPIO87__FUNC_IOBIST87 (MTK_PIN_NO(87) | 8) + +#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define PINMUX_GPIO88__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(88) | 1) +#define PINMUX_GPIO88__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(88) | 2) +#define PINMUX_GPIO88__FUNC_CONN_DSP_L5_JINTP (MTK_PIN_NO(88) | 4) +#define PINMUX_GPIO88__FUNC_TSFDC_26M (MTK_PIN_NO(88) | 6) +#define PINMUX_GPIO88__FUNC_IOBIST88 (MTK_PIN_NO(88) | 8) + +#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define PINMUX_GPIO89__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(89) | 1) +#define PINMUX_GPIO89__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(89) | 2) +#define PINMUX_GPIO89__FUNC_SPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(89) | 3) +#define PINMUX_GPIO89__FUNC_MCUPM_JTAG_TRSTN (MTK_PIN_NO(89) | 5) +#define PINMUX_GPIO89__FUNC_TSFDC_SDO (MTK_PIN_NO(89) | 6) +#define PINMUX_GPIO89__FUNC_IOBIST89 (MTK_PIN_NO(89) | 8) + +#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define PINMUX_GPIO90__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(90) | 1) +#define PINMUX_GPIO90__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(90) | 2) +#define PINMUX_GPIO90__FUNC_SPM_JTAG_TCK_VCORE (MTK_PIN_NO(90) | 3) +#define PINMUX_GPIO90__FUNC_CONN_DSP_L5_JCK (MTK_PIN_NO(90) | 4) +#define PINMUX_GPIO90__FUNC_MCUPM_JTAG_TCK (MTK_PIN_NO(90) | 5) +#define PINMUX_GPIO90__FUNC_TSFDC_FOUT (MTK_PIN_NO(90) | 6) +#define PINMUX_GPIO90__FUNC_IOBIST90 (MTK_PIN_NO(90) | 8) + +#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define PINMUX_GPIO91__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(91) | 1) +#define PINMUX_GPIO91__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(91) | 2) +#define PINMUX_GPIO91__FUNC_SPM_JTAG_TMS_VCORE (MTK_PIN_NO(91) | 3) +#define PINMUX_GPIO91__FUNC_CONN_DSP_L5_JMS (MTK_PIN_NO(91) | 4) +#define PINMUX_GPIO91__FUNC_MCUPM_JTAG_TMS (MTK_PIN_NO(91) | 5) +#define PINMUX_GPIO91__FUNC_TSFDC_SCK (MTK_PIN_NO(91) | 6) +#define PINMUX_GPIO91__FUNC_IOBIST91 (MTK_PIN_NO(91) | 8) + +#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define PINMUX_GPIO92__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(92) | 1) +#define PINMUX_GPIO92__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(92) | 2) +#define PINMUX_GPIO92__FUNC_SPM_JTAG_TDI_VCORE (MTK_PIN_NO(92) | 3) +#define PINMUX_GPIO92__FUNC_CONN_DSP_L5_JDI (MTK_PIN_NO(92) | 4) +#define PINMUX_GPIO92__FUNC_MCUPM_JTAG_TDI (MTK_PIN_NO(92) | 5) +#define PINMUX_GPIO92__FUNC_TSFDC_SDI (MTK_PIN_NO(92) | 6) +#define PINMUX_GPIO92__FUNC_IOBIST92 (MTK_PIN_NO(92) | 8) + +#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define PINMUX_GPIO93__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(93) | 1) +#define PINMUX_GPIO93__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(93) | 2) +#define PINMUX_GPIO93__FUNC_SPM_JTAG_TDO_VCORE (MTK_PIN_NO(93) | 3) +#define PINMUX_GPIO93__FUNC_CONN_DSP_L5_JDO (MTK_PIN_NO(93) | 4) +#define PINMUX_GPIO93__FUNC_MCUPM_JTAG_TDO (MTK_PIN_NO(93) | 5) +#define PINMUX_GPIO93__FUNC_TSFDC_SCF (MTK_PIN_NO(93) | 6) +#define PINMUX_GPIO93__FUNC_IOBIST93 (MTK_PIN_NO(93) | 8) + +#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define PINMUX_GPIO94__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(94) | 1) +#define PINMUX_GPIO94__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(94) | 2) +#define PINMUX_GPIO94__FUNC_SRCLKENAI0 (MTK_PIN_NO(94) | 3) +#define PINMUX_GPIO94__FUNC_MD_MCIF_UTXD0 (MTK_PIN_NO(94) | 6) +#define PINMUX_GPIO94__FUNC_IOBIST94 (MTK_PIN_NO(94) | 8) + +#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define PINMUX_GPIO95__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(95) | 1) +#define PINMUX_GPIO95__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(95) | 2) +#define PINMUX_GPIO95__FUNC_SRCLKENAI1 (MTK_PIN_NO(95) | 3) +#define PINMUX_GPIO95__FUNC_SRCLKENA1 (MTK_PIN_NO(95) | 4) +#define PINMUX_GPIO95__FUNC_MD_MCIF_URXD0 (MTK_PIN_NO(95) | 6) +#define PINMUX_GPIO95__FUNC_IOBIST95 (MTK_PIN_NO(95) | 8) + +#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define PINMUX_GPIO96__FUNC_DSI_TE (MTK_PIN_NO(96) | 1) +#define PINMUX_GPIO96__FUNC_DBG_MON_B25 (MTK_PIN_NO(96) | 7) +#define PINMUX_GPIO96__FUNC_IOBIST96 (MTK_PIN_NO(96) | 8) + +#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define PINMUX_GPIO97__FUNC_LCM_RST (MTK_PIN_NO(97) | 1) +#define PINMUX_GPIO97__FUNC_DBG_MON_B26 (MTK_PIN_NO(97) | 7) +#define PINMUX_GPIO97__FUNC_IOBIST97 (MTK_PIN_NO(97) | 8) + +#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define PINMUX_GPIO98__FUNC_DISP_PWM (MTK_PIN_NO(98) | 1) +#define PINMUX_GPIO98__FUNC_PWM_2 (MTK_PIN_NO(98) | 2) +#define PINMUX_GPIO98__FUNC_DBG_MON_B27 (MTK_PIN_NO(98) | 7) +#define PINMUX_GPIO98__FUNC_IOBIST98 (MTK_PIN_NO(98) | 8) + +#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define PINMUX_GPIO99__FUNC_ANT_SEL0 (MTK_PIN_NO(99) | 1) +#define PINMUX_GPIO99__FUNC_CONN_BPI_BUS17_ANT0 (MTK_PIN_NO(99) | 2) +#define PINMUX_GPIO99__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(99) | 3) +#define PINMUX_GPIO99__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(99) | 4) +#define PINMUX_GPIO99__FUNC_SCL6 (MTK_PIN_NO(99) | 5) +#define PINMUX_GPIO99__FUNC_IOBIST99 (MTK_PIN_NO(99) | 8) + +#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define PINMUX_GPIO100__FUNC_ANT_SEL1 (MTK_PIN_NO(100) | 1) +#define PINMUX_GPIO100__FUNC_CONN_BPI_BUS18_ANT1 (MTK_PIN_NO(100) | 2) +#define PINMUX_GPIO100__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(100) | 3) +#define PINMUX_GPIO100__FUNC_AGPS_SYNC (MTK_PIN_NO(100) | 4) +#define PINMUX_GPIO100__FUNC_SDA6 (MTK_PIN_NO(100) | 5) +#define PINMUX_GPIO100__FUNC_IOBIST100 (MTK_PIN_NO(100) | 8) + +#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define PINMUX_GPIO101__FUNC_ANT_SEL2 (MTK_PIN_NO(101) | 1) +#define PINMUX_GPIO101__FUNC_CONN_BPI_BUS19_ANT2 (MTK_PIN_NO(101) | 2) +#define PINMUX_GPIO101__FUNC_UDI_NTRST (MTK_PIN_NO(101) | 3) +#define PINMUX_GPIO101__FUNC_CONN_WF_MCU_TRST_B (MTK_PIN_NO(101) | 4) +#define PINMUX_GPIO101__FUNC_IOBIST101 (MTK_PIN_NO(101) | 8) + +#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define PINMUX_GPIO102__FUNC_ANT_SEL3 (MTK_PIN_NO(102) | 1) +#define PINMUX_GPIO102__FUNC_CONN_BPI_BUS20_ANT3 (MTK_PIN_NO(102) | 2) +#define PINMUX_GPIO102__FUNC_UDI_TCK (MTK_PIN_NO(102) | 3) +#define PINMUX_GPIO102__FUNC_CONN_WF_MCU_TCK (MTK_PIN_NO(102) | 4) +#define PINMUX_GPIO102__FUNC_IOBIST102 (MTK_PIN_NO(102) | 8) + +#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define PINMUX_GPIO103__FUNC_ANT_SEL4 (MTK_PIN_NO(103) | 1) +#define PINMUX_GPIO103__FUNC_CONN_BPI_BUS21_ANT4 (MTK_PIN_NO(103) | 2) +#define PINMUX_GPIO103__FUNC_UDI_TMS (MTK_PIN_NO(103) | 3) +#define PINMUX_GPIO103__FUNC_CONN_WF_MCU_TMS (MTK_PIN_NO(103) | 4) +#define PINMUX_GPIO103__FUNC_IOBIST103 (MTK_PIN_NO(103) | 8) + +#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define PINMUX_GPIO104__FUNC_ANT_SEL5 (MTK_PIN_NO(104) | 1) +#define PINMUX_GPIO104__FUNC_CONN_BPI_BUS16_OLAT5 (MTK_PIN_NO(104) | 2) +#define PINMUX_GPIO104__FUNC_UDI_TDI (MTK_PIN_NO(104) | 3) +#define PINMUX_GPIO104__FUNC_CONN_WF_MCU_TDI (MTK_PIN_NO(104) | 4) +#define PINMUX_GPIO104__FUNC_IOBIST104 (MTK_PIN_NO(104) | 8) + +#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define PINMUX_GPIO105__FUNC_ANT_SEL6 (MTK_PIN_NO(105) | 1) +#define PINMUX_GPIO105__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(105) | 2) +#define PINMUX_GPIO105__FUNC_UDI_TDO (MTK_PIN_NO(105) | 3) +#define PINMUX_GPIO105__FUNC_CONN_WF_MCU_TDO (MTK_PIN_NO(105) | 4) +#define PINMUX_GPIO105__FUNC_IOBIST105 (MTK_PIN_NO(105) | 8) + +#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define PINMUX_GPIO106__FUNC_BPI_BUS0 (MTK_PIN_NO(106) | 1) +#define PINMUX_GPIO106__FUNC_CONN_BPI_BUS10 (MTK_PIN_NO(106) | 2) +#define PINMUX_GPIO106__FUNC_MFG_TSFDC_EN (MTK_PIN_NO(106) | 4) +#define PINMUX_GPIO106__FUNC_I2SOUT4_DATA0 (MTK_PIN_NO(106) | 5) +#define PINMUX_GPIO106__FUNC_ANT_SEL7 (MTK_PIN_NO(106) | 6) +#define PINMUX_GPIO106__FUNC_IOBIST106 (MTK_PIN_NO(106) | 8) + +#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define PINMUX_GPIO107__FUNC_BPI_BUS1 (MTK_PIN_NO(107) | 1) +#define PINMUX_GPIO107__FUNC_CONN_BPI_BUS11_OLAT0 (MTK_PIN_NO(107) | 2) +#define PINMUX_GPIO107__FUNC_MFG_TSFDC_VCO_RST (MTK_PIN_NO(107) | 4) +#define PINMUX_GPIO107__FUNC_I2SOUT4_DATA1 (MTK_PIN_NO(107) | 5) +#define PINMUX_GPIO107__FUNC_ANT_SEL8 (MTK_PIN_NO(107) | 6) +#define PINMUX_GPIO107__FUNC_IOBIST107 (MTK_PIN_NO(107) | 8) + +#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define PINMUX_GPIO108__FUNC_BPI_BUS2 (MTK_PIN_NO(108) | 1) +#define PINMUX_GPIO108__FUNC_CONN_BPI_BUS12_OLAT1 (MTK_PIN_NO(108) | 2) +#define PINMUX_GPIO108__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(108) | 3) +#define PINMUX_GPIO108__FUNC_MFG_TSFDC_TSSEL2 (MTK_PIN_NO(108) | 4) +#define PINMUX_GPIO108__FUNC_I2SOUT4_DATA2 (MTK_PIN_NO(108) | 5) +#define PINMUX_GPIO108__FUNC_ANT_SEL9 (MTK_PIN_NO(108) | 6) +#define PINMUX_GPIO108__FUNC_IOBIST108 (MTK_PIN_NO(108) | 8) + +#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define PINMUX_GPIO109__FUNC_BPI_BUS3 (MTK_PIN_NO(109) | 1) +#define PINMUX_GPIO109__FUNC_CONN_BPI_BUS13_OLAT2 (MTK_PIN_NO(109) | 2) +#define PINMUX_GPIO109__FUNC_MFG_TSFDC_TSSEL1 (MTK_PIN_NO(109) | 4) +#define PINMUX_GPIO109__FUNC_I2SOUT4_DATA3 (MTK_PIN_NO(109) | 5) +#define PINMUX_GPIO109__FUNC_ANT_SEL10 (MTK_PIN_NO(109) | 6) +#define PINMUX_GPIO109__FUNC_IOBIST109 (MTK_PIN_NO(109) | 8) + +#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define PINMUX_GPIO110__FUNC_BPI_BUS4 (MTK_PIN_NO(110) | 1) +#define PINMUX_GPIO110__FUNC_CONN_BPI_BUS14_OLAT3 (MTK_PIN_NO(110) | 2) +#define PINMUX_GPIO110__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(110) | 3) +#define PINMUX_GPIO110__FUNC_MFG_TSFDC_TSSEL0 (MTK_PIN_NO(110) | 4) +#define PINMUX_GPIO110__FUNC_I2SIN4_BCK (MTK_PIN_NO(110) | 5) +#define PINMUX_GPIO110__FUNC_ANT_SEL11 (MTK_PIN_NO(110) | 6) +#define PINMUX_GPIO110__FUNC_IOBIST110 (MTK_PIN_NO(110) | 8) + +#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define PINMUX_GPIO111__FUNC_BPI_BUS5 (MTK_PIN_NO(111) | 1) +#define PINMUX_GPIO111__FUNC_CONN_BPI_BUS15_OLAT4 (MTK_PIN_NO(111) | 2) +#define PINMUX_GPIO111__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(111) | 3) +#define PINMUX_GPIO111__FUNC_MFG_TSFDC_RCK_SELB (MTK_PIN_NO(111) | 4) +#define PINMUX_GPIO111__FUNC_I2SIN4_DATA0 (MTK_PIN_NO(111) | 5) +#define PINMUX_GPIO111__FUNC_ANT_SEL12 (MTK_PIN_NO(111) | 6) +#define PINMUX_GPIO111__FUNC_IOBIST111 (MTK_PIN_NO(111) | 8) + +#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define PINMUX_GPIO112__FUNC_BPI_BUS6 (MTK_PIN_NO(112) | 1) +#define PINMUX_GPIO112__FUNC_CONN_BPI_BUS6 (MTK_PIN_NO(112) | 2) +#define PINMUX_GPIO112__FUNC_MIPI3_D_SDATA (MTK_PIN_NO(112) | 3) +#define PINMUX_GPIO112__FUNC_MFG_TSFDC_SDO (MTK_PIN_NO(112) | 4) +#define PINMUX_GPIO112__FUNC_I2SIN4_DATA1 (MTK_PIN_NO(112) | 5) +#define PINMUX_GPIO112__FUNC_ANT_SEL13 (MTK_PIN_NO(112) | 6) +#define PINMUX_GPIO112__FUNC_IOBIST112 (MTK_PIN_NO(112) | 8) + +#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define PINMUX_GPIO113__FUNC_BPI_BUS7 (MTK_PIN_NO(113) | 1) +#define PINMUX_GPIO113__FUNC_CONN_BPI_BUS7 (MTK_PIN_NO(113) | 2) +#define PINMUX_GPIO113__FUNC_MIPI3_D_SCLK (MTK_PIN_NO(113) | 3) +#define PINMUX_GPIO113__FUNC_MFG_TSFDC_FOUT (MTK_PIN_NO(113) | 4) +#define PINMUX_GPIO113__FUNC_I2SIN4_DATA2 (MTK_PIN_NO(113) | 5) +#define PINMUX_GPIO113__FUNC_ANT_SEL14 (MTK_PIN_NO(113) | 6) +#define PINMUX_GPIO113__FUNC_IOBIST113 (MTK_PIN_NO(113) | 8) + +#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define PINMUX_GPIO114__FUNC_BPI_BUS8 (MTK_PIN_NO(114) | 1) +#define PINMUX_GPIO114__FUNC_CONN_BPI_BUS8 (MTK_PIN_NO(114) | 2) +#define PINMUX_GPIO114__FUNC_MIPI4_D_SDATA (MTK_PIN_NO(114) | 3) +#define PINMUX_GPIO114__FUNC_SCL9 (MTK_PIN_NO(114) | 4) +#define PINMUX_GPIO114__FUNC_I2SIN4_DATA3 (MTK_PIN_NO(114) | 5) +#define PINMUX_GPIO114__FUNC_ANT_SEL15 (MTK_PIN_NO(114) | 6) +#define PINMUX_GPIO114__FUNC_IOBIST114 (MTK_PIN_NO(114) | 8) + +#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define PINMUX_GPIO115__FUNC_BPI_BUS9 (MTK_PIN_NO(115) | 1) +#define PINMUX_GPIO115__FUNC_CONN_BPI_BUS9 (MTK_PIN_NO(115) | 2) +#define PINMUX_GPIO115__FUNC_MIPI4_D_SCLK (MTK_PIN_NO(115) | 3) +#define PINMUX_GPIO115__FUNC_SDA9 (MTK_PIN_NO(115) | 4) +#define PINMUX_GPIO115__FUNC_I2SIN4_LRCK (MTK_PIN_NO(115) | 5) +#define PINMUX_GPIO115__FUNC_ANT_SEL16 (MTK_PIN_NO(115) | 6) +#define PINMUX_GPIO115__FUNC_IOBIST115 (MTK_PIN_NO(115) | 8) + +#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define PINMUX_GPIO116__FUNC_MD_UCNT_A_TGL (MTK_PIN_NO(116) | 1) +#define PINMUX_GPIO116__FUNC_IOBIST116 (MTK_PIN_NO(116) | 8) + +#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define PINMUX_GPIO117__FUNC_DIGRF_IRQ (MTK_PIN_NO(117) | 1) +#define PINMUX_GPIO117__FUNC_IOBIST117 (MTK_PIN_NO(117) | 8) + +#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define PINMUX_GPIO118__FUNC_IOBIST118 (MTK_PIN_NO(118) | 8) + +#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define PINMUX_GPIO119__FUNC_AP_GOOD (MTK_PIN_NO(119) | 1) +#define PINMUX_GPIO119__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(119) | 3) +#define PINMUX_GPIO119__FUNC_GPS_PPS (MTK_PIN_NO(119) | 4) +#define PINMUX_GPIO119__FUNC_PMSR_SMAP (MTK_PIN_NO(119) | 5) +#define PINMUX_GPIO119__FUNC_AGPS_SYNC (MTK_PIN_NO(119) | 6) +#define PINMUX_GPIO119__FUNC_IOBIST119 (MTK_PIN_NO(119) | 8) + +#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define PINMUX_GPIO120__FUNC_KPCOL0_VLP (MTK_PIN_NO(120) | 1) +#define PINMUX_GPIO120__FUNC_IOBIST120 (MTK_PIN_NO(120) | 8) + +#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define PINMUX_GPIO121__FUNC_SRCLKENAI0 (MTK_PIN_NO(121) | 1) +#define PINMUX_GPIO121__FUNC_SRCLKENAI1 (MTK_PIN_NO(121) | 2) +#define PINMUX_GPIO121__FUNC_IOBIST121 (MTK_PIN_NO(121) | 8) + +#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define PINMUX_GPIO122__FUNC_WATCHDOG (MTK_PIN_NO(122) | 1) +#define PINMUX_GPIO122__FUNC_IOBIST122 (MTK_PIN_NO(122) | 8) + +#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define PINMUX_GPIO123__FUNC_IOBIST123 (MTK_PIN_NO(123) | 8) + +#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define PINMUX_GPIO124__FUNC_SRCLKENA0 (MTK_PIN_NO(124) | 1) +#define PINMUX_GPIO124__FUNC_IOBIST124 (MTK_PIN_NO(124) | 8) + +#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define PINMUX_GPIO125__FUNC_RTC32K_CK (MTK_PIN_NO(125) | 1) +#define PINMUX_GPIO125__FUNC_IOBIST125 (MTK_PIN_NO(125) | 8) + +#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define PINMUX_GPIO126__FUNC_SPMI_M_SCL (MTK_PIN_NO(126) | 1) +#define PINMUX_GPIO126__FUNC_IOBIST126 (MTK_PIN_NO(126) | 8) + +#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define PINMUX_GPIO127__FUNC_SPMI_M_SDA (MTK_PIN_NO(127) | 1) +#define PINMUX_GPIO127__FUNC_IOBIST127 (MTK_PIN_NO(127) | 8) + +#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define PINMUX_GPIO128__FUNC_SPMI_P_SCL (MTK_PIN_NO(128) | 1) +#define PINMUX_GPIO128__FUNC_IOBIST128 (MTK_PIN_NO(128) | 8) + +#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define PINMUX_GPIO129__FUNC_SPMI_P_SDA (MTK_PIN_NO(129) | 1) +#define PINMUX_GPIO129__FUNC_IOBIST129 (MTK_PIN_NO(129) | 8) + +#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define PINMUX_GPIO130__FUNC_BPI_BUS13 (MTK_PIN_NO(130) | 3) +#define PINMUX_GPIO130__FUNC_IOBIST130 (MTK_PIN_NO(130) | 8) + +#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define PINMUX_GPIO131__FUNC_SPI6_CLK (MTK_PIN_NO(131) | 1) +#define PINMUX_GPIO131__FUNC_KPROW2 (MTK_PIN_NO(131) | 2) +#define PINMUX_GPIO131__FUNC_BPI_BUS14 (MTK_PIN_NO(131) | 3) +#define PINMUX_GPIO131__FUNC_CONN_BT_TXD (MTK_PIN_NO(131) | 4) +#define PINMUX_GPIO131__FUNC_MD32_1_TXD (MTK_PIN_NO(131) | 5) +#define PINMUX_GPIO131__FUNC_PTA_TXD (MTK_PIN_NO(131) | 6) +#define PINMUX_GPIO131__FUNC_IOBIST131 (MTK_PIN_NO(131) | 8) + +#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define PINMUX_GPIO132__FUNC_SPI6_CSB (MTK_PIN_NO(132) | 1) +#define PINMUX_GPIO132__FUNC_KPCOL2 (MTK_PIN_NO(132) | 2) +#define PINMUX_GPIO132__FUNC_BPI_BUS15 (MTK_PIN_NO(132) | 3) +#define PINMUX_GPIO132__FUNC_MD32_1_RXD (MTK_PIN_NO(132) | 5) +#define PINMUX_GPIO132__FUNC_PTA_RXD (MTK_PIN_NO(132) | 6) +#define PINMUX_GPIO132__FUNC_IOBIST132 (MTK_PIN_NO(132) | 8) + +#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define PINMUX_GPIO133__FUNC_SPI6_MO (MTK_PIN_NO(133) | 1) +#define PINMUX_GPIO133__FUNC_CLKM0 (MTK_PIN_NO(133) | 2) +#define PINMUX_GPIO133__FUNC_BPI_BUS16 (MTK_PIN_NO(133) | 3) +#define PINMUX_GPIO133__FUNC_CMFLASH2 (MTK_PIN_NO(133) | 4) +#define PINMUX_GPIO133__FUNC_IOBIST133 (MTK_PIN_NO(133) | 8) + +#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define PINMUX_GPIO134__FUNC_SPI6_MI (MTK_PIN_NO(134) | 1) +#define PINMUX_GPIO134__FUNC_CLKM1 (MTK_PIN_NO(134) | 2) +#define PINMUX_GPIO134__FUNC_BPI_BUS17 (MTK_PIN_NO(134) | 3) +#define PINMUX_GPIO134__FUNC_CMFLASH3 (MTK_PIN_NO(134) | 4) +#define PINMUX_GPIO134__FUNC_IOBIST134 (MTK_PIN_NO(134) | 8) + +#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define PINMUX_GPIO135__FUNC_SCP_SCL1 (MTK_PIN_NO(135) | 1) +#define PINMUX_GPIO135__FUNC_CLKM2 (MTK_PIN_NO(135) | 2) +#define PINMUX_GPIO135__FUNC_SCP_DMIC_CLK (MTK_PIN_NO(135) | 3) +#define PINMUX_GPIO135__FUNC_DMIC_CLK (MTK_PIN_NO(135) | 4) +#define PINMUX_GPIO135__FUNC_TP_GPIO13_AO (MTK_PIN_NO(135) | 5) +#define PINMUX_GPIO135__FUNC_DBG_MON_A23 (MTK_PIN_NO(135) | 7) +#define PINMUX_GPIO135__FUNC_IOBIST135 (MTK_PIN_NO(135) | 8) + +#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define PINMUX_GPIO136__FUNC_SCP_SDA1 (MTK_PIN_NO(136) | 1) +#define PINMUX_GPIO136__FUNC_CLKM3 (MTK_PIN_NO(136) | 2) +#define PINMUX_GPIO136__FUNC_SCP_DMIC_DAT (MTK_PIN_NO(136) | 3) +#define PINMUX_GPIO136__FUNC_DMIC_DAT (MTK_PIN_NO(136) | 4) +#define PINMUX_GPIO136__FUNC_TP_GPIO14_AO (MTK_PIN_NO(136) | 5) +#define PINMUX_GPIO136__FUNC_DBG_MON_A24 (MTK_PIN_NO(136) | 7) +#define PINMUX_GPIO136__FUNC_IOBIST136 (MTK_PIN_NO(136) | 8) + +#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define PINMUX_GPIO137__FUNC_IRRX_IN (MTK_PIN_NO(137) | 2) +#define PINMUX_GPIO137__FUNC_MD_INT0 (MTK_PIN_NO(137) | 3) +#define PINMUX_GPIO137__FUNC_SPMI_M_TRIG_FLAG (MTK_PIN_NO(137) | 4) +#define PINMUX_GPIO137__FUNC_TP_GPIO15_AO (MTK_PIN_NO(137) | 5) +#define PINMUX_GPIO137__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(137) | 6) +#define PINMUX_GPIO137__FUNC_IOBIST137 (MTK_PIN_NO(137) | 8) + +#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define PINMUX_GPIO138__FUNC_PWM_VLP (MTK_PIN_NO(138) | 2) +#define PINMUX_GPIO138__FUNC_MD_INT3 (MTK_PIN_NO(138) | 3) +#define PINMUX_GPIO138__FUNC_TP_GPIO0_AO (MTK_PIN_NO(138) | 5) +#define PINMUX_GPIO138__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(138) | 6) +#define PINMUX_GPIO138__FUNC_IOBIST138 (MTK_PIN_NO(138) | 8) + +#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define PINMUX_GPIO139__FUNC_SCL0 (MTK_PIN_NO(139) | 1) +#define PINMUX_GPIO139__FUNC_BPI_BUS18 (MTK_PIN_NO(139) | 4) +#define PINMUX_GPIO139__FUNC_DBG_MON_B28 (MTK_PIN_NO(139) | 7) +#define PINMUX_GPIO139__FUNC_IOBIST139 (MTK_PIN_NO(139) | 8) + +#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define PINMUX_GPIO140__FUNC_SDA0 (MTK_PIN_NO(140) | 1) +#define PINMUX_GPIO140__FUNC_BPI_BUS19 (MTK_PIN_NO(140) | 4) +#define PINMUX_GPIO140__FUNC_DBG_MON_B29 (MTK_PIN_NO(140) | 7) +#define PINMUX_GPIO140__FUNC_IOBIST140 (MTK_PIN_NO(140) | 8) + +#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define PINMUX_GPIO141__FUNC_SCL1 (MTK_PIN_NO(141) | 1) +#define PINMUX_GPIO141__FUNC_SCL9 (MTK_PIN_NO(141) | 2) +#define PINMUX_GPIO141__FUNC_BPI_BUS20 (MTK_PIN_NO(141) | 4) +#define PINMUX_GPIO141__FUNC_DBG_MON_B30 (MTK_PIN_NO(141) | 7) +#define PINMUX_GPIO141__FUNC_IOBIST141 (MTK_PIN_NO(141) | 8) + +#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define PINMUX_GPIO142__FUNC_SDA1 (MTK_PIN_NO(142) | 1) +#define PINMUX_GPIO142__FUNC_SDA9 (MTK_PIN_NO(142) | 2) +#define PINMUX_GPIO142__FUNC_BPI_BUS21 (MTK_PIN_NO(142) | 4) +#define PINMUX_GPIO142__FUNC_DBG_MON_B31 (MTK_PIN_NO(142) | 7) +#define PINMUX_GPIO142__FUNC_IOBIST142 (MTK_PIN_NO(142) | 8) + +#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define PINMUX_GPIO143__FUNC_SCL2 (MTK_PIN_NO(143) | 1) +#define PINMUX_GPIO143__FUNC_DBG_MON_B9 (MTK_PIN_NO(143) | 7) +#define PINMUX_GPIO143__FUNC_IOBIST143 (MTK_PIN_NO(143) | 8) + +#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define PINMUX_GPIO144__FUNC_SDA2 (MTK_PIN_NO(144) | 1) +#define PINMUX_GPIO144__FUNC_DBG_MON_B10 (MTK_PIN_NO(144) | 7) +#define PINMUX_GPIO144__FUNC_IOBIST144 (MTK_PIN_NO(144) | 8) + +#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +#define PINMUX_GPIO145__FUNC_SCL3 (MTK_PIN_NO(145) | 1) +#define PINMUX_GPIO145__FUNC_DMIC1_CLK (MTK_PIN_NO(145) | 3) +#define PINMUX_GPIO145__FUNC_DBG_MON_B11 (MTK_PIN_NO(145) | 7) +#define PINMUX_GPIO145__FUNC_IOBIST145 (MTK_PIN_NO(145) | 8) + +#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +#define PINMUX_GPIO146__FUNC_SDA3 (MTK_PIN_NO(146) | 1) +#define PINMUX_GPIO146__FUNC_DMIC1_DAT (MTK_PIN_NO(146) | 3) +#define PINMUX_GPIO146__FUNC_DBG_MON_B12 (MTK_PIN_NO(146) | 7) +#define PINMUX_GPIO146__FUNC_IOBIST146 (MTK_PIN_NO(146) | 8) + +#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +#define PINMUX_GPIO147__FUNC_SCL4 (MTK_PIN_NO(147) | 1) +#define PINMUX_GPIO147__FUNC_DBG_MON_A31 (MTK_PIN_NO(147) | 7) +#define PINMUX_GPIO147__FUNC_IOBIST147 (MTK_PIN_NO(147) | 8) + +#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +#define PINMUX_GPIO148__FUNC_SDA4 (MTK_PIN_NO(148) | 1) +#define PINMUX_GPIO148__FUNC_DBG_MON_A7 (MTK_PIN_NO(148) | 7) +#define PINMUX_GPIO148__FUNC_IOBIST148 (MTK_PIN_NO(148) | 8) + +#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +#define PINMUX_GPIO149__FUNC_SCL5 (MTK_PIN_NO(149) | 1) +#define PINMUX_GPIO149__FUNC_IOBIST149 (MTK_PIN_NO(149) | 8) + +#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +#define PINMUX_GPIO150__FUNC_SDA5 (MTK_PIN_NO(150) | 1) +#define PINMUX_GPIO150__FUNC_IOBIST150 (MTK_PIN_NO(150) | 8) + +#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +#define PINMUX_GPIO151__FUNC_SCL6 (MTK_PIN_NO(151) | 1) +#define PINMUX_GPIO151__FUNC_SCL11 (MTK_PIN_NO(151) | 2) +#define PINMUX_GPIO151__FUNC_IOBIST151 (MTK_PIN_NO(151) | 8) + +#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +#define PINMUX_GPIO152__FUNC_SDA6 (MTK_PIN_NO(152) | 1) +#define PINMUX_GPIO152__FUNC_SDA11 (MTK_PIN_NO(152) | 2) +#define PINMUX_GPIO152__FUNC_IOBIST152 (MTK_PIN_NO(152) | 8) + +#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +#define PINMUX_GPIO153__FUNC_SCL7 (MTK_PIN_NO(153) | 1) +#define PINMUX_GPIO153__FUNC_DBG_MON_A3 (MTK_PIN_NO(153) | 7) +#define PINMUX_GPIO153__FUNC_IOBIST153 (MTK_PIN_NO(153) | 8) + +#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +#define PINMUX_GPIO154__FUNC_SDA7 (MTK_PIN_NO(154) | 1) +#define PINMUX_GPIO154__FUNC_DBG_MON_A4 (MTK_PIN_NO(154) | 7) +#define PINMUX_GPIO154__FUNC_IOBIST154 (MTK_PIN_NO(154) | 8) + +#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +#define PINMUX_GPIO155__FUNC_SCL8 (MTK_PIN_NO(155) | 1) +#define PINMUX_GPIO155__FUNC_DBG_MON_A5 (MTK_PIN_NO(155) | 7) +#define PINMUX_GPIO155__FUNC_IOBIST155 (MTK_PIN_NO(155) | 8) + +#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +#define PINMUX_GPIO156__FUNC_SDA8 (MTK_PIN_NO(156) | 1) +#define PINMUX_GPIO156__FUNC_IOBIST156 (MTK_PIN_NO(156) | 8) + +#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +#define PINMUX_GPIO157__FUNC_SCP_SCL0 (MTK_PIN_NO(157) | 1) +#define PINMUX_GPIO157__FUNC_SCP_SCL5 (MTK_PIN_NO(157) | 3) +#define PINMUX_GPIO157__FUNC_TP_UCTS1_VLP (MTK_PIN_NO(157) | 4) +#define PINMUX_GPIO157__FUNC_TP_GPIO0_AO (MTK_PIN_NO(157) | 5) +#define PINMUX_GPIO157__FUNC_DBG_MON_A27 (MTK_PIN_NO(157) | 7) +#define PINMUX_GPIO157__FUNC_IOBIST157 (MTK_PIN_NO(157) | 8) + +#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +#define PINMUX_GPIO158__FUNC_SCP_SDA0 (MTK_PIN_NO(158) | 1) +#define PINMUX_GPIO158__FUNC_SCP_SDA5 (MTK_PIN_NO(158) | 3) +#define PINMUX_GPIO158__FUNC_TP_URTS1_VLP (MTK_PIN_NO(158) | 4) +#define PINMUX_GPIO158__FUNC_TP_GPIO1_AO (MTK_PIN_NO(158) | 5) +#define PINMUX_GPIO158__FUNC_DBG_MON_A28 (MTK_PIN_NO(158) | 7) +#define PINMUX_GPIO158__FUNC_IOBIST158 (MTK_PIN_NO(158) | 8) + +#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +#define PINMUX_GPIO159__FUNC_SCP_SCL1 (MTK_PIN_NO(159) | 1) +#define PINMUX_GPIO159__FUNC_SCP_SCL4 (MTK_PIN_NO(159) | 3) +#define PINMUX_GPIO159__FUNC_TP_UCTS2_VLP (MTK_PIN_NO(159) | 4) +#define PINMUX_GPIO159__FUNC_TP_GPIO2_AO (MTK_PIN_NO(159) | 5) +#define PINMUX_GPIO159__FUNC_DBG_MON_A29 (MTK_PIN_NO(159) | 7) +#define PINMUX_GPIO159__FUNC_IOBIST159 (MTK_PIN_NO(159) | 8) + +#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +#define PINMUX_GPIO160__FUNC_SCP_SDA1 (MTK_PIN_NO(160) | 1) +#define PINMUX_GPIO160__FUNC_SCP_SDA4 (MTK_PIN_NO(160) | 3) +#define PINMUX_GPIO160__FUNC_TP_URTS2_VLP (MTK_PIN_NO(160) | 4) +#define PINMUX_GPIO160__FUNC_TP_GPIO3_AO (MTK_PIN_NO(160) | 5) +#define PINMUX_GPIO160__FUNC_DBG_MON_A30 (MTK_PIN_NO(160) | 7) +#define PINMUX_GPIO160__FUNC_IOBIST160 (MTK_PIN_NO(160) | 8) + +#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +#define PINMUX_GPIO161__FUNC_SCP_SCL2 (MTK_PIN_NO(161) | 1) +#define PINMUX_GPIO161__FUNC_SCL10 (MTK_PIN_NO(161) | 2) +#define PINMUX_GPIO161__FUNC_SCP_DMIC_CLK (MTK_PIN_NO(161) | 3) +#define PINMUX_GPIO161__FUNC_DMIC_CLK (MTK_PIN_NO(161) | 4) +#define PINMUX_GPIO161__FUNC_TP_GPIO4_AO (MTK_PIN_NO(161) | 5) +#define PINMUX_GPIO161__FUNC_EXTIF0_PRI (MTK_PIN_NO(161) | 6) +#define PINMUX_GPIO161__FUNC_IOBIST161 (MTK_PIN_NO(161) | 8) + +#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +#define PINMUX_GPIO162__FUNC_SCP_SDA2 (MTK_PIN_NO(162) | 1) +#define PINMUX_GPIO162__FUNC_SDA10 (MTK_PIN_NO(162) | 2) +#define PINMUX_GPIO162__FUNC_SCP_DMIC_DAT (MTK_PIN_NO(162) | 3) +#define PINMUX_GPIO162__FUNC_DMIC_DAT (MTK_PIN_NO(162) | 4) +#define PINMUX_GPIO162__FUNC_TP_GPIO5_AO (MTK_PIN_NO(162) | 5) +#define PINMUX_GPIO162__FUNC_EXTIF0_GNT_B (MTK_PIN_NO(162) | 6) +#define PINMUX_GPIO162__FUNC_IOBIST162 (MTK_PIN_NO(162) | 8) + +#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) +#define PINMUX_GPIO163__FUNC_SCP_SCL3 (MTK_PIN_NO(163) | 1) +#define PINMUX_GPIO163__FUNC_SCL12 (MTK_PIN_NO(163) | 2) +#define PINMUX_GPIO163__FUNC_TP_GPIO6_AO (MTK_PIN_NO(163) | 5) +#define PINMUX_GPIO163__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(163) | 7) +#define PINMUX_GPIO163__FUNC_IOBIST163 (MTK_PIN_NO(163) | 8) + +#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) +#define PINMUX_GPIO164__FUNC_SCP_SDA3 (MTK_PIN_NO(164) | 1) +#define PINMUX_GPIO164__FUNC_SDA12 (MTK_PIN_NO(164) | 2) +#define PINMUX_GPIO164__FUNC_TP_GPIO7_AO (MTK_PIN_NO(164) | 5) +#define PINMUX_GPIO164__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(164) | 7) +#define PINMUX_GPIO164__FUNC_IOBIST164 (MTK_PIN_NO(164) | 8) + +#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) +#define PINMUX_GPIO165__FUNC_MIPI0_D_SCLK (MTK_PIN_NO(165) | 1) +#define PINMUX_GPIO165__FUNC_CONN_MIPI0_SCLK (MTK_PIN_NO(165) | 2) +#define PINMUX_GPIO165__FUNC_BPI_BUS18 (MTK_PIN_NO(165) | 3) +#define PINMUX_GPIO165__FUNC_ANT_SEL17 (MTK_PIN_NO(165) | 6) +#define PINMUX_GPIO165__FUNC_IOBIST165 (MTK_PIN_NO(165) | 8) + +#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) +#define PINMUX_GPIO166__FUNC_MIPI0_D_SDATA (MTK_PIN_NO(166) | 1) +#define PINMUX_GPIO166__FUNC_CONN_MIPI0_SDATA (MTK_PIN_NO(166) | 2) +#define PINMUX_GPIO166__FUNC_BPI_BUS19 (MTK_PIN_NO(166) | 3) +#define PINMUX_GPIO166__FUNC_ANT_SEL18 (MTK_PIN_NO(166) | 6) +#define PINMUX_GPIO166__FUNC_IOBIST166 (MTK_PIN_NO(166) | 8) + +#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) +#define PINMUX_GPIO167__FUNC_MIPI1_D_SCLK (MTK_PIN_NO(167) | 1) +#define PINMUX_GPIO167__FUNC_CONN_MIPI1_SCLK (MTK_PIN_NO(167) | 2) +#define PINMUX_GPIO167__FUNC_BPI_BUS20 (MTK_PIN_NO(167) | 3) +#define PINMUX_GPIO167__FUNC_ANT_SEL19 (MTK_PIN_NO(167) | 6) +#define PINMUX_GPIO167__FUNC_IOBIST167 (MTK_PIN_NO(167) | 8) + +#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) +#define PINMUX_GPIO168__FUNC_MIPI1_D_SDATA (MTK_PIN_NO(168) | 1) +#define PINMUX_GPIO168__FUNC_CONN_MIPI1_SDATA (MTK_PIN_NO(168) | 2) +#define PINMUX_GPIO168__FUNC_BPI_BUS21 (MTK_PIN_NO(168) | 3) +#define PINMUX_GPIO168__FUNC_ANT_SEL20 (MTK_PIN_NO(168) | 6) +#define PINMUX_GPIO168__FUNC_IOBIST168 (MTK_PIN_NO(168) | 8) + +#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) +#define PINMUX_GPIO169__FUNC_MIPI2_D_SCLK (MTK_PIN_NO(169) | 1) +#define PINMUX_GPIO169__FUNC_BPI_BUS10 (MTK_PIN_NO(169) | 3) +#define PINMUX_GPIO169__FUNC_MD_GPS_L1_BLANK (MTK_PIN_NO(169) | 6) +#define PINMUX_GPIO169__FUNC_IOBIST169 (MTK_PIN_NO(169) | 8) + +#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) +#define PINMUX_GPIO170__FUNC_MIPI2_D_SDATA (MTK_PIN_NO(170) | 1) +#define PINMUX_GPIO170__FUNC_BPI_BUS11 (MTK_PIN_NO(170) | 3) +#define PINMUX_GPIO170__FUNC_MD_GPS_L5_BLANK (MTK_PIN_NO(170) | 6) +#define PINMUX_GPIO170__FUNC_IOBIST170 (MTK_PIN_NO(170) | 8) + +#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) +#define PINMUX_GPIO171__FUNC_MIPI_M_SCLK (MTK_PIN_NO(171) | 1) +#define PINMUX_GPIO171__FUNC_IOBIST171 (MTK_PIN_NO(171) | 8) + +#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) +#define PINMUX_GPIO172__FUNC_MIPI_M_SDATA (MTK_PIN_NO(172) | 1) +#define PINMUX_GPIO172__FUNC_IOBIST172 (MTK_PIN_NO(172) | 8) + +#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) +#define PINMUX_GPIO173__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(173) | 1) +#define PINMUX_GPIO173__FUNC_AUD_CLK_MOSI_A (MTK_PIN_NO(173) | 3) +#define PINMUX_GPIO173__FUNC_IOBIST173 (MTK_PIN_NO(173) | 8) + +#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) +#define PINMUX_GPIO174__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(174) | 1) +#define PINMUX_GPIO174__FUNC_IOBIST174 (MTK_PIN_NO(174) | 8) + +#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) +#define PINMUX_GPIO175__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(175) | 1) +#define PINMUX_GPIO175__FUNC_AUD_DAT_MOSI0_A (MTK_PIN_NO(175) | 3) +#define PINMUX_GPIO175__FUNC_IOBIST175 (MTK_PIN_NO(175) | 8) + +#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) +#define PINMUX_GPIO176__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(176) | 1) +#define PINMUX_GPIO176__FUNC_AUD_DAT_MOSI1_A (MTK_PIN_NO(176) | 3) +#define PINMUX_GPIO176__FUNC_IOBIST176 (MTK_PIN_NO(176) | 8) + +#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) +#define PINMUX_GPIO177__FUNC_AUD_NLE_MOSI0 (MTK_PIN_NO(177) | 1) +#define PINMUX_GPIO177__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(177) | 2) +#define PINMUX_GPIO177__FUNC_IOBIST177 (MTK_PIN_NO(177) | 8) + +#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) +#define PINMUX_GPIO178__FUNC_AUD_NLE_MOSI1 (MTK_PIN_NO(178) | 1) +#define PINMUX_GPIO178__FUNC_AUD_CLK_MISO (MTK_PIN_NO(178) | 2) +#define PINMUX_GPIO178__FUNC_AUD_CLK_MISO_A (MTK_PIN_NO(178) | 3) +#define PINMUX_GPIO178__FUNC_IOBIST178 (MTK_PIN_NO(178) | 8) + +#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) +#define PINMUX_GPIO179__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(179) | 1) +#define PINMUX_GPIO179__FUNC_VOW_DAT_MISO (MTK_PIN_NO(179) | 2) +#define PINMUX_GPIO179__FUNC_AUD_DAT_MISO0_A (MTK_PIN_NO(179) | 3) +#define PINMUX_GPIO179__FUNC_IOBIST179 (MTK_PIN_NO(179) | 8) + +#define PINMUX_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) +#define PINMUX_GPIO180__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(180) | 1) +#define PINMUX_GPIO180__FUNC_VOW_CLK_MISO (MTK_PIN_NO(180) | 2) +#define PINMUX_GPIO180__FUNC_AUD_DAT_MISO1_A (MTK_PIN_NO(180) | 3) +#define PINMUX_GPIO180__FUNC_IOBIST180 (MTK_PIN_NO(180) | 8) + +#define PINMUX_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) +#define PINMUX_GPIO181__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(181) | 1) +#define PINMUX_GPIO181__FUNC_IOBIST181 (MTK_PIN_NO(181) | 8) + +#define PINMUX_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) +#define PINMUX_GPIO182__FUNC_CONN_TOP_CLK (MTK_PIN_NO(182) | 1) +#define PINMUX_GPIO182__FUNC_IOBIST182 (MTK_PIN_NO(182) | 8) + +#define PINMUX_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) +#define PINMUX_GPIO183__FUNC_CONN_TOP_DATA (MTK_PIN_NO(183) | 1) +#define PINMUX_GPIO183__FUNC_IOBIST183 (MTK_PIN_NO(183) | 8) + +#define PINMUX_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) +#define PINMUX_GPIO184__FUNC_CONN_BT_CLK (MTK_PIN_NO(184) | 1) +#define PINMUX_GPIO184__FUNC_IOBIST184 (MTK_PIN_NO(184) | 8) + +#define PINMUX_GPIO185__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) +#define PINMUX_GPIO185__FUNC_CONN_BT_DATA (MTK_PIN_NO(185) | 1) +#define PINMUX_GPIO185__FUNC_IOBIST185 (MTK_PIN_NO(185) | 8) + +#define PINMUX_GPIO186__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) +#define PINMUX_GPIO186__FUNC_CONN_HRST_B (MTK_PIN_NO(186) | 1) +#define PINMUX_GPIO186__FUNC_IOBIST186 (MTK_PIN_NO(186) | 8) + +#define PINMUX_GPIO187__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) +#define PINMUX_GPIO187__FUNC_CONN_WB_PTA (MTK_PIN_NO(187) | 1) +#define PINMUX_GPIO187__FUNC_IOBIST187 (MTK_PIN_NO(187) | 8) + +#define PINMUX_GPIO188__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) +#define PINMUX_GPIO188__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(188) | 1) +#define PINMUX_GPIO188__FUNC_IOBIST188 (MTK_PIN_NO(188) | 8) + +#define PINMUX_GPIO189__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) +#define PINMUX_GPIO189__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(189) | 1) +#define PINMUX_GPIO189__FUNC_IOBIST189 (MTK_PIN_NO(189) | 8) + +#define PINMUX_GPIO190__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) +#define PINMUX_GPIO190__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(190) | 1) +#define PINMUX_GPIO190__FUNC_IOBIST190 (MTK_PIN_NO(190) | 8) + +#define PINMUX_GPIO191__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) +#define PINMUX_GPIO191__FUNC_CONN_TOP_CLK_2 (MTK_PIN_NO(191) | 1) +#define PINMUX_GPIO191__FUNC_IOBIST191 (MTK_PIN_NO(191) | 8) + +#define PINMUX_GPIO192__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) +#define PINMUX_GPIO192__FUNC_CONN_TOP_DATA_2 (MTK_PIN_NO(192) | 1) +#define PINMUX_GPIO192__FUNC_IOBIST192 (MTK_PIN_NO(192) | 8) + +#define PINMUX_GPIO193__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) +#define PINMUX_GPIO193__FUNC_CONN_HRST_B_2 (MTK_PIN_NO(193) | 1) +#define PINMUX_GPIO193__FUNC_IOBIST193 (MTK_PIN_NO(193) | 8) + +#define PINMUX_GPIO194__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) +#define PINMUX_GPIO194__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(194) | 1) +#define PINMUX_GPIO194__FUNC_MD_GPS_L1_BLANK (MTK_PIN_NO(194) | 2) +#define PINMUX_GPIO194__FUNC_IOBIST194 (MTK_PIN_NO(194) | 8) + +#define PINMUX_GPIO195__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) +#define PINMUX_GPIO195__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(195) | 1) +#define PINMUX_GPIO195__FUNC_MD_GPS_L5_BLANK (MTK_PIN_NO(195) | 2) +#define PINMUX_GPIO195__FUNC_ANT_SEL21 (MTK_PIN_NO(195) | 3) +#define PINMUX_GPIO195__FUNC_SPMI_P_TRIG_FLAG (MTK_PIN_NO(195) | 5) +#define PINMUX_GPIO195__FUNC_IOBIST195 (MTK_PIN_NO(195) | 8) + +#define PINMUX_GPIO196__FUNC_GPIO196 (MTK_PIN_NO(196) | 0) +#define PINMUX_GPIO196__FUNC_PAD_RESET_DRAM_0 (MTK_PIN_NO(196) | 1) +#define PINMUX_GPIO196__FUNC_IOBIST196 (MTK_PIN_NO(196) | 8) + +#endif /* __6858_PINFUNC_H */ From 39a5c6017e949cb32608f4fd7f98cbf599fd6b5b Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Wed, 15 Jul 2026 15:29:16 +0300 Subject: [PATCH 044/130] pinctrl: npcm8xx: drop RTS/CTS pins from bmcuart1 The bmcuart1 group currently claims BU1_RTS and BU1_CTS in addition to TXD and RXD. That prevents boards from using the modem-control pins independently through the dedicated nbu1crts function. Limit bmcuart1 to the TXD/RXD pair and let users opt into BU1_RTS and BU1_CTS explicitly through the nbu1crts group when those signals are needed. Signed-off-by: Tomer Maimon Signed-off-by: Linus Walleij --- drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c index 0aae1a253459..c859dca4b973 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c @@ -538,7 +538,7 @@ static const int wdog2_pins[] = { 219 }; static const int bmcuart0a_pins[] = { 41, 42 }; static const int bmcuart0b_pins[] = { 48, 49 }; -static const int bmcuart1_pins[] = { 43, 44, 62, 63 }; +static const int bmcuart1_pins[] = { 43, 63 }; static const int scipme_pins[] = { 169 }; static const int smi_pins[] = { 170 }; From c6ccdc305589dd7c7976116e0870a23f291c5fa9 Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Wed, 15 Jul 2026 15:29:17 +0300 Subject: [PATCH 045/130] pinctrl: npcm8xx: enable RMII outputs from RMII groups NPCM8xx uses GCR_INTCR4 bits to release the R1, R2 and RMII3 transmit outputs from Hi-Z. Those bits need to follow the mandatory r1, r2 and rmii3 pin groups. The R1_OEn, R2_OEn and R3_OEn side groups are optional and should not be required just to enable RMII transmit outputs. Program the INTCR4 bits when the corresponding RMII groups are selected and clear them again when those pins switch back to GPIO or another shared function. Signed-off-by: Tomer Maimon Signed-off-by: Linus Walleij --- drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 61 +++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c index c859dca4b973..1d5b3c648109 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c @@ -26,6 +26,7 @@ #define NPCM8XX_GCR_SRCNT 0x068 #define NPCM8XX_GCR_FLOCKR1 0x074 #define NPCM8XX_GCR_DSCNT 0x078 +#define NPCM8XX_GCR_INTCR4 0x0c0 #define NPCM8XX_GCR_I2CSEGSEL 0x0e0 #define NPCM8XX_GCR_MFSEL1 0x260 #define NPCM8XX_GCR_MFSEL2 0x264 @@ -78,6 +79,9 @@ #define NPCM8XX_GPIO_PER_BANK 32 #define NPCM8XX_GPIO_BANK_NUM 8 #define NPCM8XX_GCR_NONE 0 +#define NPCM8XX_INTCR4_R1_RMII_EN BIT(12) +#define NPCM8XX_INTCR4_R2_RMII_EN BIT(13) +#define NPCM8XX_INTCR4_RMII3_EN BIT(14) #define NPCM8XX_DEBOUNCE_MAX 4 #define NPCM8XX_DEBOUNCE_NSEC 40 @@ -1796,6 +1800,61 @@ static const struct pinctrl_pin_desc npcm8xx_pins[] = { PINCTRL_PIN(251, "JM2/CP1_GPIO"), }; +static u32 npcm8xx_rmii_output_enable_mask(unsigned int pin) +{ + switch (pin) { + case 178: + case 179: + case 180: + case 181: + case 182: + case 193: + case 201: + return NPCM8XX_INTCR4_R1_RMII_EN; + case 84: + case 85: + case 86: + case 87: + case 88: + case 89: + case 200: + return NPCM8XX_INTCR4_R2_RMII_EN; + case 110: + case 111: + case 209: + case 210: + case 211: + case 214: + case 215: + return NPCM8XX_INTCR4_RMII3_EN; + default: + return 0; + } +} + +static void npcm8xx_set_rmii_output_enable(struct regmap *gcr_regmap, + const unsigned int *pin, + int pin_number, int mode) +{ + u32 mask = 0; + u32 val = 0; + u32 bit; + int i; + + for (i = 0; i < pin_number; i++) { + bit = npcm8xx_rmii_output_enable_mask(pin[i]); + mask |= bit; + + if ((mode == fn_r1 && bit == NPCM8XX_INTCR4_R1_RMII_EN) || + (mode == fn_r2 && bit == NPCM8XX_INTCR4_R2_RMII_EN) || + (mode == fn_rmii3 && bit == NPCM8XX_INTCR4_RMII3_EN)) + val |= bit; + } + + if (mask) + regmap_update_bits(gcr_regmap, NPCM8XX_GCR_INTCR4, mask, val); +} + /* Enable mode in pin group */ static void npcm8xx_setfunc(struct regmap *gcr_regmap, const unsigned int *pin, int pin_number, int mode) @@ -1834,6 +1893,8 @@ static void npcm8xx_setfunc(struct regmap *gcr_regmap, const unsigned int *pin, BIT(cfg->bit4) : 0); } } + + npcm8xx_set_rmii_output_enable(gcr_regmap, pin, pin_number, mode); } static int npcm8xx_get_slew_rate(struct npcm8xx_gpio *bank, From dc0e211e1adc246976517cbd00b34831be962183 Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Wed, 15 Jul 2026 15:29:18 +0300 Subject: [PATCH 046/130] pinctrl: npcm8xx: support RG2 drive strength selection RG2 pins 110-113 and 208-209 do not use the per-bank ODSC bit that the driver relies on for the rest of the drive-strength handling. Their strength is encoded in GCR_DSCNT[7:6] and supports four values: 8, 12, 16 and 24mA. Mark those pins as a dedicated drive-strength class and translate the pinconf get/set operations to the shared GCR_DSCNT field so the full hardware range becomes available. Signed-off-by: Tomer Maimon Signed-off-by: Linus Walleij --- drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 75 ++++++++++++++++++++--- 1 file changed, 67 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c index 1d5b3c648109..8d7dfb326b9e 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c @@ -82,6 +82,8 @@ #define NPCM8XX_INTCR4_R1_RMII_EN BIT(12) #define NPCM8XX_INTCR4_R2_RMII_EN BIT(13) #define NPCM8XX_INTCR4_RMII3_EN BIT(14) +#define NPCM8XX_GCR_DSCNT_RG2DS_SHIFT 6 +#define NPCM8XX_GCR_DSCNT_RG2DS_MASK GENMASK(7, 6) #define NPCM8XX_DEBOUNCE_MAX 4 #define NPCM8XX_DEBOUNCE_NSEC 40 @@ -1287,6 +1289,7 @@ static struct pinfunction npcm8xx_funcs[] = { #define DRIVE_STRENGTH_LO_SHIFT 8 #define DRIVE_STRENGTH_HI_SHIFT 12 #define DRIVE_STRENGTH_MASK GENMASK(15, 8) +#define DSTR_RG2 BIT(16) #define DSTR(lo, hi) (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \ ((hi) << DRIVE_STRENGTH_HI_SHIFT)) @@ -1419,10 +1422,10 @@ static const struct npcm8xx_pincfg pincfg[] = { NPCM8XX_PINCFG(107, i3c5, MFSEL3, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), NPCM8XX_PINCFG(108, sg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), NPCM8XX_PINCFG(109, sg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), - NPCM8XX_PINCFG(110, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, SLEW), - NPCM8XX_PINCFG(111, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, SLEW), - NPCM8XX_PINCFG(112, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), - NPCM8XX_PINCFG(113, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(110, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR_RG2 | SLEW), + NPCM8XX_PINCFG(111, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR_RG2 | SLEW), + NPCM8XX_PINCFG(112, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR_RG2 | SLEW), + NPCM8XX_PINCFG(113, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR_RG2 | SLEW), NPCM8XX_PINCFG(114, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), NPCM8XX_PINCFG(115, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), NPCM8XX_PINCFG(116, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), @@ -1513,8 +1516,8 @@ static const struct npcm8xx_pincfg pincfg[] = { NPCM8XX_PINCFG(201, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), NPCM8XX_PINCFG(202, smb0c, I2CSEGSEL, 1, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), NPCM8XX_PINCFG(203, faninx, MFSEL3, 3, spi1cs0, MFSEL3, 4, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), - NPCM8XX_PINCFG(208, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), /* DSCNT */ - NPCM8XX_PINCFG(209, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, SLEW), /* DSCNT */ + NPCM8XX_PINCFG(208, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR_RG2 | SLEW), + NPCM8XX_PINCFG(209, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR_RG2 | SLEW), NPCM8XX_PINCFG(210, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), NPCM8XX_PINCFG(211, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), NPCM8XX_PINCFG(212, rg2, MFSEL4, 24, ddr, MFSEL3, 26, r3rxer, MFSEL6, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), @@ -1954,6 +1957,56 @@ static int npcm8xx_set_slew_rate(struct npcm8xx_gpio *bank, return 0; } +static int npcm8xx_get_rg2_drive_strength(struct npcm8xx_pinctrl *npcm) +{ + u32 val; + int ret; + + ret = regmap_read(npcm->gcr_regmap, NPCM8XX_GCR_DSCNT, &val); + if (ret) + return ret; + + switch ((val & NPCM8XX_GCR_DSCNT_RG2DS_MASK) >> + NPCM8XX_GCR_DSCNT_RG2DS_SHIFT) { + case 0: + return 8; + case 1: + return 12; + case 2: + return 16; + case 3: + return 24; + default: + return -EINVAL; + } +} + +static int npcm8xx_set_rg2_drive_strength(struct npcm8xx_pinctrl *npcm, int nval) +{ + u32 val; + + switch (nval) { + case 8: + val = 0; + break; + case 12: + val = 1; + break; + case 16: + val = 2; + break; + case 24: + val = 3; + break; + default: + return -EOPNOTSUPP; + } + + return regmap_update_bits(npcm->gcr_regmap, NPCM8XX_GCR_DSCNT, + NPCM8XX_GCR_DSCNT_RG2DS_MASK, + val << NPCM8XX_GCR_DSCNT_RG2DS_SHIFT); +} + static int npcm8xx_get_drive_strength(struct pinctrl_dev *pctldev, unsigned int pin) { @@ -1962,10 +2015,13 @@ static int npcm8xx_get_drive_strength(struct pinctrl_dev *pctldev, &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; int gpio = pin % bank->chip.gc.ngpio; unsigned long pinmask = BIT(gpio); - int flg, val; - u32 ds = 0; + int flg, ds; + u32 val; flg = pincfg[pin].flag; + if (flg & DSTR_RG2) + return npcm8xx_get_rg2_drive_strength(npcm); + if (!(flg & DRIVE_STRENGTH_MASK)) return -EINVAL; @@ -1984,6 +2040,9 @@ static int npcm8xx_set_drive_strength(struct npcm8xx_pinctrl *npcm, int gpio = BIT(pin % bank->chip.gc.ngpio); int v; + if (pincfg[pin].flag & DSTR_RG2) + return npcm8xx_set_rg2_drive_strength(npcm, nval); + v = pincfg[pin].flag & DRIVE_STRENGTH_MASK; if (DSLO(v) == nval) From cd39cce4cfd499f555eb8b8252636609c3468f57 Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Wed, 15 Jul 2026 15:29:19 +0300 Subject: [PATCH 047/130] pinctrl: npcm8xx: clear pending GPIO events during init A bank may retain pending event status across resets of the GPIO block. If probe leaves the old state in place, the chained IRQ handler can see spurious events as soon as the irqchip is registered. Disable event generation and clear EVST before wiring each GPIO bank into gpiolib so the driver starts from a known state. Signed-off-by: Tomer Maimon Signed-off-by: Linus Walleij --- drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c index 8d7dfb326b9e..5dcb01923162 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c @@ -2471,6 +2471,9 @@ static int npcm8xx_gpio_fw(struct npcm8xx_pinctrl *pctrl) if (ret < 0) return dev_err_probe(dev, ret, "Failed to retrieve IRQ for bank %u\n", id); + iowrite32(0, pctrl->gpio_bank[id].base + NPCM8XX_GP_N_EVEN); + iowrite32(0xffffffff, pctrl->gpio_bank[id].base + NPCM8XX_GP_N_EVST); + pctrl->gpio_bank[id].irq = ret; pctrl->gpio_bank[id].irq_chip = npcmgpio_irqchip; pctrl->gpio_bank[id].irqbase = id * NPCM8XX_GPIO_PER_BANK; From 565d368597da793df314060468766456d04b5237 Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Wed, 15 Jul 2026 15:29:20 +0300 Subject: [PATCH 048/130] pinctrl: npcm8xx: rename GPIO7 IOX2 signal to DO The pin description for GPIO7 spells the IOX2 output signal as D0. The datasheet names that signal IOX2_DO, matching the rest of the IOX naming scheme. Rename the pin description accordingly. Signed-off-by: Tomer Maimon Signed-off-by: Linus Walleij --- drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c index 5dcb01923162..1c95d7cbd546 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c @@ -1567,7 +1567,7 @@ static const struct pinctrl_pin_desc npcm8xx_pins[] = { PINCTRL_PIN(4, "GPIO4/IOX2_DI/SMB1D_SDA"), PINCTRL_PIN(5, "GPIO5/IOX2_LD/SMB1D_SCL"), PINCTRL_PIN(6, "GPIO6/IOX2_CK/SMB2D_SDA"), - PINCTRL_PIN(7, "GPIO7/IOX2_D0/SMB2D_SCL"), + PINCTRL_PIN(7, "GPIO7/IOX2_DO/SMB2D_SCL"), PINCTRL_PIN(8, "GPIO8/LKGPO1/TP_GPIO0"), PINCTRL_PIN(9, "GPIO9/LKGPO2/TP_GPIO1"), PINCTRL_PIN(10, "GPIO10/IOXH_LD/SMB6D_SCL/SMB16_SCL"), From b8edfde12e355030e708394c0fa11632559c7ac5 Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Wed, 15 Jul 2026 15:29:21 +0300 Subject: [PATCH 049/130] pinctrl: npcm8xx: move GPIO IRQ setup into request_resources npcmgpio_irq_startup() calls pinctrl_gpio_direction_input(), which may sleep while taking the pinctrl core mutex. That makes IRQ startup trip lockdep when CONFIG_PROVE_LOCKING is enabled. Move the direction change into irq_request_resources() and keep startup limited to the ack and unmask operations that are safe in atomic context. Signed-off-by: Tomer Maimon Signed-off-by: Linus Walleij --- drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 29 ++++++++++++++++++----- 1 file changed, 23 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c index 1c95d7cbd546..e21ccdb5d1f8 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c @@ -297,17 +297,33 @@ static void npcmgpio_irq_unmask(struct irq_data *d) static unsigned int npcmgpio_irq_startup(struct irq_data *d) { - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - unsigned int gpio = irqd_to_hwirq(d); - - /* active-high, input, clear interrupt, enable interrupt */ - npcmgpio_direction_input(gc, gpio); npcmgpio_irq_ack(d); npcmgpio_irq_unmask(d); return 0; } +static int npcmgpio_irq_request_resources(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + unsigned int gpio = irqd_to_hwirq(d); + int ret; + + ret = npcmgpio_direction_input(gc, gpio); + if (ret) + return ret; + + return gpiochip_reqres_irq(gc, gpio); +} + +static void npcmgpio_irq_release_resources(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + unsigned int gpio = irqd_to_hwirq(d); + + gpiochip_relres_irq(gc, gpio); +} + static struct irq_chip npcmgpio_irqchip = { .name = "NPCM8XX-GPIO-IRQ", .irq_ack = npcmgpio_irq_ack, @@ -315,8 +331,9 @@ static struct irq_chip npcmgpio_irqchip = { .irq_mask = npcmgpio_irq_mask, .irq_set_type = npcmgpio_set_irq_type, .irq_startup = npcmgpio_irq_startup, + .irq_request_resources = npcmgpio_irq_request_resources, + .irq_release_resources = npcmgpio_irq_release_resources, .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE, - GPIOCHIP_IRQ_RESOURCE_HELPERS, }; static const int gpi36_pins[] = { 36 }; From e74ff540a7480a3ebe752b72858bbc1c15ede6dc Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Wed, 15 Jul 2026 15:29:22 +0300 Subject: [PATCH 050/130] pinctrl: npcm8xx: correct JM1 and SMB7 pin flags Pins 136-140 and 142 are currently advertised as having both drive- strength and slew-rate controls, while pins 141 and 143 expose no slew control at all. According to the hardware description, those pins only support slew-rate configuration. Update the pin flags accordingly so pinconf exposes the capabilities that the hardware actually implements. Signed-off-by: Tomer Maimon Signed-off-by: Linus Walleij --- drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c index e21ccdb5d1f8..f94494b672ee 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c @@ -1465,14 +1465,14 @@ static const struct npcm8xx_pincfg pincfg[] = { NPCM8XX_PINCFG(133, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), NPCM8XX_PINCFG(134, smb11, MFSEL4, 14, smb23b, MFSEL6, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), NPCM8XX_PINCFG(135, smb11, MFSEL4, 14, smb23b, MFSEL6, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), - NPCM8XX_PINCFG(136, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), - NPCM8XX_PINCFG(137, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), - NPCM8XX_PINCFG(138, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), - NPCM8XX_PINCFG(139, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), - NPCM8XX_PINCFG(140, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), - NPCM8XX_PINCFG(141, smb7b, I2CSEGSEL, 27, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), - NPCM8XX_PINCFG(142, smb7d, I2CSEGSEL, 29, tp_smb1, MFSEL7, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), - NPCM8XX_PINCFG(143, smb7d, I2CSEGSEL, 29, tp_smb1, MFSEL7, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(136, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(137, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(138, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(139, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(140, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(141, smb7b, I2CSEGSEL, 27, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(142, smb7d, I2CSEGSEL, 29, tp_smb1, MFSEL7, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(143, smb7d, I2CSEGSEL, 29, tp_smb1, MFSEL7, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), NPCM8XX_PINCFG(144, pwm4, MFSEL2, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), NPCM8XX_PINCFG(145, pwm5, MFSEL2, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), NPCM8XX_PINCFG(146, pwm6, MFSEL2, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), From 602ee6c9447e4382c7e145b26a1c940813f2a144 Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Wed, 15 Jul 2026 15:29:23 +0300 Subject: [PATCH 051/130] pinctrl: npcm8xx: fix debounce register selection Each DBNCS register programs debounce source selection for 16 GPIOs. The current offset calculation advances the register address every four GPIOs, so offsets 4-15 and 20-31 end up touching the wrong selector register. Advance the DBNCS offset per 16 GPIOs so each line uses the debounce selector bank that matches the hardware layout. Signed-off-by: Tomer Maimon Signed-off-by: Linus Walleij --- drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c index f94494b672ee..f9107f81906b 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c @@ -2211,7 +2211,8 @@ static const struct pinmux_ops npcm8xx_pinmux_ops = { static int debounce_timing_setting(struct npcm8xx_gpio *bank, u32 gpio, u32 nanosecs) { - void __iomem *DBNCS_offset = bank->base + NPCM8XX_GP_N_DBNCS0 + (gpio / 4); + void __iomem *DBNCS_offset = bank->base + NPCM8XX_GP_N_DBNCS0 + + (gpio / 16) * 4; int gpio_debounce = (gpio % 16) * 2, debounce_select, i; u32 dbncp_val, dbncp_val_mod; From 15532f9cbb713255805ca78442f6e6e43f4b2adf Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 15 Jul 2026 15:35:45 -0400 Subject: [PATCH 052/130] pinctrl: pinctrl-generic-mux: use mux_state_try_select() Use mux_state_try_select() instead of mux_state_select() so that the consumer driver does not block during probe when the mux state has already been selected. mux_state_try_select() returns -EBUSY if the requested state is already selected, allowing the driver to handle the condition without waiting. Signed-off-by: Frank Li Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-generic-mux.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-generic-mux.c b/drivers/pinctrl/pinctrl-generic-mux.c index da5a5ec01583..202b72351efb 100644 --- a/drivers/pinctrl/pinctrl-generic-mux.c +++ b/drivers/pinctrl/pinctrl-generic-mux.c @@ -93,7 +93,7 @@ static int mux_pinmux_set_mux(struct pinctrl_dev *pctldev, function = pinmux_generic_get_function(pctldev, func_selector); func = function->data; - ret = mux_state_select(func->mux_state); + ret = mux_state_try_select(func->mux_state); if (ret) return ret; From 46840fa8c9f53b9c90db4b4be2b808bbc626cde2 Mon Sep 17 00:00:00 2001 From: Julian Braha Date: Thu, 16 Jul 2026 04:34:41 +0100 Subject: [PATCH 053/130] pinctrl: fix unmet dependencies from missing GPIOLIB These 4 options, PINCTRL_PIC32, PINCTRL_PIC32, PINCTRL_IPROC_GPIO, and PINCTRL_NSP_GPIO all select GPIOLIB_IRQCHIP without ensuring GPIOLIB is enabled, causing unmet dependencies, such as: WARNING: unmet direct dependencies detected for GPIOLIB_IRQCHIP Depends on [n]: GPIOLIB [=n] Selected by [y]: - PINCTRL_PIC32 [=y] && PINCTRL [=y] && OF [=y] && (MACH_PIC32 || COMPILE_TEST [=y]) Similar options in this subsystem select GPIOLIB, so let's do the same here. These unmet dependency bugs were found by kconfirm, a static analysis tool for Kconfig. Fixes: 2ba384e6c381 ("pinctrl: pinctrl-pic32: Add PIC32 pin control driver") Fixes: 1490d9f841b1 ("pinctrl: Add STMFX GPIO expander Pinctrl/GPIO driver") Fixes: b64333ce769c ("pinctrl: cygnus: add gpio/pinconf driver") Fixes: 8bfcbbbcabe0 ("pinctrl: nsp: add gpio-a driver support for Broadcom NSP SoC") Signed-off-by: Julian Braha Reviewed-by: Arnd Bergmann Acked-by: Arnd Bergmann Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 2 ++ drivers/pinctrl/bcm/Kconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index c2cdd7b2c49b..ddc60562b770 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -486,6 +486,7 @@ config PINCTRL_PIC32 depends on MACH_PIC32 || COMPILE_TEST select PINMUX select GENERIC_PINCONF + select GPIOLIB select GPIOLIB_IRQCHIP help This is the pin controller and gpio driver for Microchip PIC32 @@ -562,6 +563,7 @@ config PINCTRL_STMFX depends on I2C depends on HAS_IOMEM select GENERIC_PINCONF + select GPIOLIB select GPIOLIB_IRQCHIP select MFD_STMFX help diff --git a/drivers/pinctrl/bcm/Kconfig b/drivers/pinctrl/bcm/Kconfig index 206f3f1249cf..19d22e7fd11e 100644 --- a/drivers/pinctrl/bcm/Kconfig +++ b/drivers/pinctrl/bcm/Kconfig @@ -121,6 +121,7 @@ source "drivers/pinctrl/bcm/Kconfig.stb" config PINCTRL_IPROC_GPIO bool "Broadcom iProc GPIO (with PINCONF) driver" depends on ARCH_BCM_IPROC || COMPILE_TEST + select GPIOLIB select GPIOLIB_IRQCHIP select PINCONF select GENERIC_PINCONF @@ -186,6 +187,7 @@ config PINCTRL_NS config PINCTRL_NSP_GPIO bool "Broadcom NSP GPIO (with PINCONF) driver" depends on ARCH_BCM_NSP || COMPILE_TEST + select GPIOLIB select GPIOLIB_IRQCHIP select PINCONF select GENERIC_PINCONF From 0e5d8cf3f71a542762ed3eaef677258c87492dfa Mon Sep 17 00:00:00 2001 From: Hugo VALTIER Date: Fri, 17 Jul 2026 09:59:14 +0200 Subject: [PATCH 054/130] pinctrl: rockchip: constify mux recalced and route data arrays The mux_recalced_data and mux_route_data arrays are never modified after initialization. Mark them const so they can be placed in read-only memory. Also constify the corresponding struct fields in rockchip_pin_ctrl and local pointer variables. This is inspired by review comments on Dmitry Yashin's earlier RK3308B series [1]. [1] https://lore.kernel.org/all/20240515121634.23945-1-dmt.yashin@gmail.com/ Signed-off-by: Hugo VALTIER Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-rockchip.c | 34 +++++++++++++++--------------- drivers/pinctrl/pinctrl-rockchip.h | 4 ++-- 2 files changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 7e0fcd45fd26..849e72f1832c 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -483,7 +483,7 @@ static struct rockchip_mux_recalced_data rv1103b_mux_recalced_data[] = { }, }; -static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { +static const struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { { .num = 1, .pin = 0, @@ -547,7 +547,7 @@ static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { }, }; -static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = { +static const struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = { { .num = 0, .pin = 20, @@ -578,7 +578,7 @@ static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = { }, }; -static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { +static const struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { { .num = 2, .pin = 20, @@ -612,7 +612,7 @@ static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { }, }; -static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { +static const struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { { /* gpio1b6_sel */ .num = 1, @@ -721,7 +721,7 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { }, }; -static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { +static const struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { { /* gpio2_b7_sel */ .num = 2, @@ -793,7 +793,7 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, { struct rockchip_pinctrl *info = bank->drvdata; struct rockchip_pin_ctrl *ctrl = info->ctrl; - struct rockchip_mux_recalced_data *data; + const struct rockchip_mux_recalced_data *data; int i; for (i = 0; i < ctrl->niomux_recalced; i++) { @@ -811,7 +811,7 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, *bit = data->bit; } -static struct rockchip_mux_route_data px30_mux_route_data[] = { +static const struct rockchip_mux_route_data px30_mux_route_data[] = { RK_MUXROUTE_SAME(2, RK_PB4, 1, 0x184, BIT(16 + 7)), /* cif-d0m0 */ RK_MUXROUTE_SAME(3, RK_PA1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d0m1 */ RK_MUXROUTE_SAME(2, RK_PB6, 1, 0x184, BIT(16 + 7)), /* cif-d1m0 */ @@ -862,7 +862,7 @@ static struct rockchip_mux_route_data px30_mux_route_data[] = { RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rtsm1 */ }; -static struct rockchip_mux_route_data rv1126_mux_route_data[] = { +static const struct rockchip_mux_route_data rv1126_mux_route_data[] = { RK_MUXROUTE_GRF(3, RK_PD2, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */ RK_MUXROUTE_GRF(3, RK_PB0, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */ @@ -959,7 +959,7 @@ static struct rockchip_mux_route_data rv1126_mux_route_data[] = { RK_MUXROUTE_PMU(1, RK_PD0, 5, 0x0118, WRITE_MASK_VAL(2, 2, 1)), /* UART1_TX_M1 */ }; -static struct rockchip_mux_route_data rk3128_mux_route_data[] = { +static const struct rockchip_mux_route_data rk3128_mux_route_data[] = { RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */ RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */ RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */ @@ -969,12 +969,12 @@ static struct rockchip_mux_route_data rk3128_mux_route_data[] = { RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */ }; -static struct rockchip_mux_route_data rk3188_mux_route_data[] = { +static const struct rockchip_mux_route_data rk3188_mux_route_data[] = { RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */ RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */ }; -static struct rockchip_mux_route_data rk3228_mux_route_data[] = { +static const struct rockchip_mux_route_data rk3228_mux_route_data[] = { RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */ RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */ RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */ @@ -995,12 +995,12 @@ static struct rockchip_mux_route_data rk3228_mux_route_data[] = { RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */ }; -static struct rockchip_mux_route_data rk3288_mux_route_data[] = { +static const struct rockchip_mux_route_data rk3288_mux_route_data[] = { RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */ RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */ }; -static struct rockchip_mux_route_data rk3308_mux_route_data[] = { +static const struct rockchip_mux_route_data rk3308_mux_route_data[] = { RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */ RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */ RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */ @@ -1016,7 +1016,7 @@ static struct rockchip_mux_route_data rk3308_mux_route_data[] = { RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */ }; -static struct rockchip_mux_route_data rk3328_mux_route_data[] = { +static const struct rockchip_mux_route_data rk3328_mux_route_data[] = { RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */ RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */ RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */ @@ -1031,7 +1031,7 @@ static struct rockchip_mux_route_data rk3328_mux_route_data[] = { RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */ }; -static struct rockchip_mux_route_data rk3399_mux_route_data[] = { +static const struct rockchip_mux_route_data rk3399_mux_route_data[] = { RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */ RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */ RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */ @@ -1039,7 +1039,7 @@ static struct rockchip_mux_route_data rk3399_mux_route_data[] = { RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */ }; -static struct rockchip_mux_route_data rk3568_mux_route_data[] = { +static const struct rockchip_mux_route_data rk3568_mux_route_data[] = { RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */ RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */ RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */ @@ -1140,7 +1140,7 @@ static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, { struct rockchip_pinctrl *info = bank->drvdata; struct rockchip_pin_ctrl *ctrl = info->ctrl; - struct rockchip_mux_route_data *data; + const struct rockchip_mux_route_data *data; int i; for (i = 0; i < ctrl->niomux_routes; i++) { diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h index bb0e803e3b8a..dd07a16f615c 100644 --- a/drivers/pinctrl/pinctrl-rockchip.h +++ b/drivers/pinctrl/pinctrl-rockchip.h @@ -400,9 +400,9 @@ struct rockchip_pin_ctrl { int pmu_mux_offset; int grf_drv_offset; int pmu_drv_offset; - struct rockchip_mux_recalced_data *iomux_recalced; + const struct rockchip_mux_recalced_data *iomux_recalced; u32 niomux_recalced; - struct rockchip_mux_route_data *iomux_routes; + const struct rockchip_mux_route_data *iomux_routes; u32 niomux_routes; int (*pull_calc_reg)(struct rockchip_pin_bank *bank, From 83a9c8385ff10775958188c8f2a115c71c45b7ef Mon Sep 17 00:00:00 2001 From: Hugo VALTIER Date: Fri, 17 Jul 2026 09:59:15 +0200 Subject: [PATCH 055/130] pinctrl: rockchip: extract iomux_recalced_routes_init() Extract the per-bank recalced_mask and route_mask computation out of rockchip_pinctrl_get_soc_data() into a separate function and call it from rockchip_pinctrl_probe(). This allows SoC-specific init code to swap the mux tables before the masks are computed. No functional change intended. Signed-off-by: Hugo VALTIER Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-rockchip.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 849e72f1832c..549834501e7f 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -4370,7 +4370,18 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( bank_pins += 8; } + } + return ctrl; +} + +static void iomux_recalced_routes_init(struct rockchip_pinctrl *info) +{ + struct rockchip_pin_ctrl *ctrl = info->ctrl; + struct rockchip_pin_bank *bank = ctrl->pin_banks; + int i, j; + + for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { /* calculate the per-bank recalced_mask */ for (j = 0; j < ctrl->niomux_recalced; j++) { int pin = 0; @@ -4391,8 +4402,6 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( } } } - - return ctrl; } #define RK3288_GRF_GPIO6C_IOMUX 0x64 @@ -4505,6 +4514,8 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) /* try to find the optional reference to the ioc1 syscon */ info->regmap_ioc1 = syscon_regmap_lookup_by_phandle_optional(np, "rockchip,ioc1"); + iomux_recalced_routes_init(info); + ret = rockchip_pinctrl_register(pdev, info); if (ret) return ret; From 6f00e157a1d24d8e4df09d5f71f2cabb505d066b Mon Sep 17 00:00:00 2001 From: Hugo VALTIER Date: Fri, 17 Jul 2026 09:59:16 +0200 Subject: [PATCH 056/130] pinctrl: rockchip: add support for RK3308B SoC The RK3308B is a revision of the RK3308 including different iomux register layout. Several pins (GPIO2_A2, GPIO2_A3, GPIO2_C0, GPIO3_B2, GPIO3_B3) have 3-bit mux fields in new GRF registers (SOC_CON13 at 0x608 and SOC_CON15 at 0x610) that override the standard 2-bit fields. I believe the bootloader sets the sel_src_ctrl bits to activate these new registers, which causes the kernel's writes to the old 2-bit iomux registers to be silently ignored. Without this patch, SPI1, I2C3, and other peripherals that depend on these pins are completely non-functional on my RK3308B boards. Detect the SoC variant at runtime by reading the chip_id register at GRF offset 0x800 (0xcea = RK3308, 0x3308/0x3308c = RK3308B), as requested by reviewers of the earlier series. When RK3308B is detected, swap in the correct mux_recalced and mux_route tables and write the sel_src_ctrl bits to ensure the 3-bit mux registers are active. This is a rework of Dmitry Yashin's series [1] which used a separate device tree compatible string ("rockchip,rk3308b-pinctrl") to distinguish the variants. Reviewers Luca Ceresoli and Heiko Stuebner agreed that runtime detection was preferable since boards are manufactured with both RK3308 and RK3308B using the same device tree. Jonas Karlman implemented runtime detection based on the GRF_CHIP_ID register [2]. Reviewers asked for more changes (constifying some arrays), but the series was never resubmitted and was dropped. I run this patch on my Rock Pi S boards, the newer ones I've got in 2024 use the RK3308B. And thanks to runtime detection we should still be compatible with older devices (but I couldn't test on RK3308 as I don't have any). [1] https://lore.kernel.org/all/20240515121634.23945-1-dmt.yashin@gmail.com/ [2] https://lore.kernel.org/all/20240604141020.21725-1-dmt.yashin@gmail.com/ Signed-off-by: Hugo VALTIER Tested-by: Dmitry Yashin Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-rockchip.c | 217 +++++++++++++++++++++++++++++ drivers/pinctrl/pinctrl-rockchip.h | 1 + 2 files changed, 218 insertions(+) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 549834501e7f..e90e13c5d7f2 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -721,6 +721,115 @@ static const struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { }, }; +static const struct rockchip_mux_recalced_data rk3308b_mux_recalced_data[] = { + { + /* gpio1b6_sel */ + .num = 1, + .pin = 14, + .reg = 0x28, + .bit = 12, + .mask = 0xf + }, { + /* gpio1b7_sel */ + .num = 1, + .pin = 15, + .reg = 0x2c, + .bit = 0, + .mask = 0x3 + }, { + /* gpio1c2_sel */ + .num = 1, + .pin = 18, + .reg = 0x30, + .bit = 4, + .mask = 0xf + }, { + /* gpio1c3_sel */ + .num = 1, + .pin = 19, + .reg = 0x30, + .bit = 8, + .mask = 0xf + }, { + /* gpio1c4_sel */ + .num = 1, + .pin = 20, + .reg = 0x30, + .bit = 12, + .mask = 0xf + }, { + /* gpio1c5_sel */ + .num = 1, + .pin = 21, + .reg = 0x34, + .bit = 0, + .mask = 0xf + }, { + /* gpio1c6_sel */ + .num = 1, + .pin = 22, + .reg = 0x34, + .bit = 4, + .mask = 0xf + }, { + /* gpio1c7_sel */ + .num = 1, + .pin = 23, + .reg = 0x34, + .bit = 8, + .mask = 0xf + }, { + /* gpio2a2_sel_plus */ + .num = 2, + .pin = 2, + .reg = 0x608, + .bit = 0, + .mask = 0x7 + }, { + /* gpio2a3_sel_plus */ + .num = 2, + .pin = 3, + .reg = 0x608, + .bit = 4, + .mask = 0x7 + }, { + /* gpio2c0_sel_plus */ + .num = 2, + .pin = 16, + .reg = 0x610, + .bit = 8, + .mask = 0x7 + }, { + /* gpio3b2_sel_plus */ + .num = 3, + .pin = 10, + .reg = 0x610, + .bit = 0, + .mask = 0x7 + }, { + /* gpio3b3_sel_plus */ + .num = 3, + .pin = 11, + .reg = 0x610, + .bit = 4, + .mask = 0x7 + }, { + /* gpio3b4_sel */ + .num = 3, + .pin = 12, + .reg = 0x68, + .bit = 8, + .mask = 0xf + }, { + /* gpio3b5_sel */ + .num = 3, + .pin = 13, + .reg = 0x68, + .bit = 12, + .mask = 0xf + }, +}; + static const struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { { /* gpio2_b7_sel */ @@ -1016,6 +1125,35 @@ static const struct rockchip_mux_route_data rk3308_mux_route_data[] = { RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */ }; +static const struct rockchip_mux_route_data rk3308b_mux_route_data[] = { + RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */ + RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */ + RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */ + RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */ + RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(8)), /* i2c3_sdam1 */ + RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(9)), /* i2c3_sdam2 */ + RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */ + RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */ + RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */ + RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */ + RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */ + RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */ + RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */ + RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */ + RK_MUXROUTE_SAME(3, RK_PB2, 3, 0x314, BIT(16 + 9)), /* spi1_miso */ + RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x314, BIT(16 + 9) | BIT(9)), /* spi1_miso_m1 */ + RK_MUXROUTE_SAME(0, RK_PB3, 3, 0x314, BIT(16 + 10) | BIT(16 + 11)), /* owire_m0 */ + RK_MUXROUTE_SAME(1, RK_PC6, 7, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* owire_m1 */ + RK_MUXROUTE_SAME(2, RK_PA2, 5, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* owire_m2 */ + RK_MUXROUTE_SAME(0, RK_PB3, 2, 0x314, BIT(16 + 12) | BIT(16 + 13)), /* can_rxd_m0 */ + RK_MUXROUTE_SAME(1, RK_PC6, 5, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* can_rxd_m1 */ + RK_MUXROUTE_SAME(2, RK_PA2, 4, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* can_rxd_m2 */ + RK_MUXROUTE_SAME(1, RK_PC4, 3, 0x314, BIT(16 + 14)), /* mac_rxd0_m0 */ + RK_MUXROUTE_SAME(4, RK_PA2, 2, 0x314, BIT(16 + 14) | BIT(14)), /* mac_rxd0_m1 */ + RK_MUXROUTE_SAME(3, RK_PB4, 4, 0x314, BIT(16 + 15)), /* uart3_rx */ + RK_MUXROUTE_SAME(0, RK_PC1, 3, 0x314, BIT(16 + 15) | BIT(15)), /* uart3_rx_m1 */ +}; + static const struct rockchip_mux_route_data rk3328_mux_route_data[] = { RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */ RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */ @@ -3486,6 +3624,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) case RK3188: case RK3288: case RK3308: + case RK3308B: case RK3328: case RK3368: case RK3399: @@ -3552,6 +3691,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, case RK3188: case RK3288: case RK3308: + case RK3308B: case RK3328: case RK3368: case RK3399: @@ -3848,6 +3988,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, case RK3188: case RK3288: case RK3308: + case RK3308B: case RK3328: case RK3368: case RK3399: @@ -4452,6 +4593,76 @@ static int __maybe_unused rockchip_pinctrl_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend, rockchip_pinctrl_resume); +#define RK3308B_GRF_SOC_CON13 0x608 +#define RK3308B_GRF_SOC_CON15 0x610 + +/* RK3308B_GRF_SOC_CON13 */ +#define RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL (BIT(16 + 10) | BIT(10)) +#define RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) +#define RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) + +/* RK3308B_GRF_SOC_CON15 */ +#define RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL (BIT(16 + 11) | BIT(11)) +#define RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) +#define RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) + +/* + * RK3308B has 3-bit gpio##_sel_plus iomuxes over some 2-bit old ones. + * Enable them by setting the gpio##_sel_src_ctrl registers. + */ +static int rk3308b_soc_sel_src_init(struct rockchip_pinctrl *info) +{ + int ret; + + ret = regmap_write(info->regmap_base, RK3308B_GRF_SOC_CON13, + RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL | + RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL | + RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL); + if (ret) + return ret; + + return regmap_write(info->regmap_base, RK3308B_GRF_SOC_CON15, + RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL | + RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL | + RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL); +} + +#define RK3308_GRF_CHIP_ID 0x800 + +static int rk3308_soc_data_init(struct rockchip_pinctrl *info) +{ + struct rockchip_pin_ctrl *ctrl = info->ctrl; + unsigned int chip_id; + int ret; + + ret = regmap_read(info->regmap_base, RK3308_GRF_CHIP_ID, &chip_id); + if (ret) + return ret; + + switch (chip_id) { + case 0xcea: + /* Original RK3308, no changes needed */ + break; + case 0x3308: + case 0x3308c: + ctrl->type = RK3308B; + ctrl->iomux_recalced = rk3308b_mux_recalced_data; + ctrl->niomux_recalced = ARRAY_SIZE(rk3308b_mux_recalced_data); + ctrl->iomux_routes = rk3308b_mux_route_data; + ctrl->niomux_routes = ARRAY_SIZE(rk3308b_mux_route_data); + + ret = rk3308b_soc_sel_src_init(info); + if (ret) + return ret; + break; + default: + return dev_err_probe(info->dev, -EINVAL, + "Unknown RK3308 chip_id: 0x%x\n", chip_id); + } + + return 0; +} + static int rockchip_pinctrl_probe(struct platform_device *pdev) { struct rockchip_pinctrl *info; @@ -4514,6 +4725,12 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) /* try to find the optional reference to the ioc1 syscon */ info->regmap_ioc1 = syscon_regmap_lookup_by_phandle_optional(np, "rockchip,ioc1"); + if (ctrl->type == RK3308) { + ret = rk3308_soc_data_init(info); + if (ret) + return ret; + } + iomux_recalced_routes_init(info); ret = rockchip_pinctrl_register(pdev, info); diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h index dd07a16f615c..914582c87dd8 100644 --- a/drivers/pinctrl/pinctrl-rockchip.h +++ b/drivers/pinctrl/pinctrl-rockchip.h @@ -194,6 +194,7 @@ enum rockchip_pinctrl_type { RK3188, RK3288, RK3308, + RK3308B, RK3328, RK3368, RK3399, From cd6c277c70d8f471ae9242c89a5ae4a48abc9bc4 Mon Sep 17 00:00:00 2001 From: Pan Chuang Date: Fri, 17 Jul 2026 18:58:43 +0800 Subject: [PATCH 057/130] pinctrl: airoha: Remove redundant dev_err() Since commit 55b48e23f5c4 ("genirq/devres: Add error handling in devm_request_*_irq()"), devm_request_irq() automatically logs detailed error messages on failure. Remove the now-redundant driver-specific dev_err() calls. Signed-off-by: Pan Chuang Acked-by: Lorenzo Bianconi Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/pinctrl-airoha.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c index 04b4424c688b..abfb018f207e 100644 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c @@ -2519,10 +2519,8 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl, err = devm_request_irq(dev, irq, airoha_irq_handler, IRQF_SHARED, dev_name(dev), pinctrl); - if (err) { - dev_err(dev, "error requesting irq %d: %d\n", irq, err); + if (err) return err; - } return devm_gpiochip_add_data(dev, gc, pinctrl); } From ee88f84f95661e07c263893e7fa8f90185d14f93 Mon Sep 17 00:00:00 2001 From: Pan Chuang Date: Fri, 17 Jul 2026 18:58:44 +0800 Subject: [PATCH 058/130] pinctrl: bcm: Remove redundant dev_err() Since commit 55b48e23f5c4 ("genirq/devres: Add error handling in devm_request_*_irq()"), devm_request_irq() automatically logs detailed error messages on failure. Remove the now-redundant driver-specific dev_err() calls. Signed-off-by: Pan Chuang Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/pinctrl-nsp-gpio.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c index b425ecacd1b0..1fbb101386a3 100644 --- a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c @@ -671,11 +671,8 @@ static int nsp_gpio_probe(struct platform_device *pdev) /* Install ISR for this GPIO controller. */ ret = devm_request_irq(dev, irq, nsp_gpio_irq_handler, IRQF_SHARED, "gpio-a", &chip->gc); - if (ret) { - dev_err(&pdev->dev, "Unable to request IRQ%d: %d\n", - irq, ret); + if (ret) return ret; - } girq = &chip->gc.irq; gpio_irq_chip_set_chip(girq, &nsp_gpio_irq_chip); From 17015f70fbce923ed5eb0850b5d9b66f2f77316f Mon Sep 17 00:00:00 2001 From: Pan Chuang Date: Fri, 17 Jul 2026 18:58:46 +0800 Subject: [PATCH 059/130] pinctrl: Remove redundant dev_err()/dev_err_probe() Since commit 55b48e23f5c4 ("genirq/devres: Add error handling in devm_request_*_irq()"), devm_request_threaded_irq() automatically logs detailed error messages on failure. Remove the now-redundant driver-specific dev_err() and dev_err_probe() calls. Signed-off-by: Pan Chuang Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-aw9523.c | 2 +- drivers/pinctrl/pinctrl-mcp23s08.c | 5 +---- drivers/pinctrl/pinctrl-stmfx.c | 4 +--- 3 files changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/pinctrl-aw9523.c b/drivers/pinctrl/pinctrl-aw9523.c index bc94003512cf..a13b1cdb78ea 100644 --- a/drivers/pinctrl/pinctrl-aw9523.c +++ b/drivers/pinctrl/pinctrl-aw9523.c @@ -817,7 +817,7 @@ static int aw9523_init_irq(struct aw9523 *awi, int irq) ret = devm_request_threaded_irq(dev, irq, NULL, aw9523_irq_thread_func, IRQF_ONESHOT, dev_name(dev), awi); if (ret) - return dev_err_probe(dev, ret, "Failed to request irq %d\n", irq); + return ret; girq = &awi->gpio.irq; gpio_irq_chip_set_chip(girq, &aw9523_irq_chip); diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c index b89b3169e8be..139b7536d67d 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08.c +++ b/drivers/pinctrl/pinctrl-mcp23s08.c @@ -560,11 +560,8 @@ static int mcp23s08_irq_setup(struct mcp23s08 *mcp) err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL, mcp23s08_irq, irqflags, dev_name(chip->parent), mcp); - if (err != 0) { - dev_err(chip->parent, "unable to request IRQ#%d: %d\n", - mcp->irq, err); + if (err) return err; - } return 0; } diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c index 03ee13844b50..935cace7f645 100644 --- a/drivers/pinctrl/pinctrl-stmfx.c +++ b/drivers/pinctrl/pinctrl-stmfx.c @@ -727,10 +727,8 @@ static int stmfx_pinctrl_probe(struct platform_device *pdev) stmfx_pinctrl_irq_thread_fn, IRQF_ONESHOT, dev_name(pctl->dev), pctl); - if (ret) { - dev_err(pctl->dev, "cannot request irq%d\n", irq); + if (ret) return ret; - } dev_info(pctl->dev, "%ld GPIOs available\n", hweight_long(pctl->gpio_valid_mask)); From 6f93039161bc00bf9942313be7e8a0e01652d995 Mon Sep 17 00:00:00 2001 From: Chen-Yu Yeh Date: Fri, 10 Jul 2026 03:39:27 +0800 Subject: [PATCH 060/130] dt-bindings: pinctrl: mt7622: allow gpio-hogs Commit 6e3b067d3c5e ("arm64: dts: mediatek: mt7622: Align GPIO hog name with bindings") renamed the asm_sel GPIO hog to asm-sel-hog to follow the GPIO hog naming convention, but the mt7622 pinctrl binding only allows child nodes matching '-pins(-[a-z]+)?$', causing a dtbs_check warning: mt7622-bananapi-bpi-r64.dtb: pinctrl@10211000 (mediatek,mt7622-pinctrl): 'asm-sel-hog' does not match any of the regexes: '-pins(-[a-z]+)?$', '^pinctrl-[0-9]+$' Allow gpio-hog nodes in the pinctrl node, following the same pattern as commit 9322da935c9a ("dt-bindings: pinctrl: mt7988: allow gpio-hogs"). Signed-off-by: Chen-Yu Yeh Reviewed-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml index 6b925c5099cc..021307b6d801 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml @@ -65,6 +65,11 @@ then: - "#interrupt-cells" patternProperties: + "-hog(-[0-9]+)?$": + type: object + required: + - gpio-hog + '-pins(-[a-z]+)?$': type: object additionalProperties: false From a2fd5a9f09587eddf4d96c7b46541359985c6ea8 Mon Sep 17 00:00:00 2001 From: Julian Braha Date: Wed, 22 Jul 2026 22:33:14 +0100 Subject: [PATCH 061/130] pinctrl: s32cc: fix unmet dependency for PINCTRL_S32CC Currently, PINCTRL_S32G2 selects PINCTRL_S32CC which needs GPIOLIB, without selecting or depending on GPIOLIB. However, other similar options in this subsystem actually select GPIOLIB instead of depending, so I think we can do the same here. This unmet dependency was found by kconfirm, a static analysis tool for Kconfig. Fixes: 94cb9e8f2707 ("pinctrl: s32cc: implement GPIO functionality") Signed-off-by: Julian Braha Acked-by: Arnd Bergmann Signed-off-by: Linus Walleij --- drivers/pinctrl/nxp/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig index 711c0fe11565..fab725f250ab 100644 --- a/drivers/pinctrl/nxp/Kconfig +++ b/drivers/pinctrl/nxp/Kconfig @@ -1,10 +1,11 @@ # SPDX-License-Identifier: GPL-2.0-only config PINCTRL_S32CC bool - depends on ARCH_S32 && OF && GPIOLIB + depends on ARCH_S32 && OF select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS select GENERIC_PINCONF + select GPIOLIB select GPIO_REGMAP select REGMAP_MMIO From 9c650317ba553d297f3fc5f0ae40ec53d86f9dab Mon Sep 17 00:00:00 2001 From: Justin Yeh Date: Thu, 23 Jul 2026 11:58:12 +0800 Subject: [PATCH 062/130] pinctrl: mediatek: use devm_gpiochip_add_data() for GPIO chip The gpio_chip is allocated with device-managed memory but registered with the non-managed gpiochip_add_data(). This was harmless while the drivers were built-in, but once they can be built as modules and unbound/rmmod'd, devm frees the gpio_chip's memory while it is still registered, causing a use-after-free. Register it with devm_gpiochip_add_data() so it shares the same device-managed lifecycle, which also lets the manual gpiochip_remove() error paths go away. Fixes: a6df410d420a ("pinctrl: mediatek: Add Pinctrl/GPIO driver for mt8135.") Fixes: 805250982bb5 ("pinctrl: mediatek: add pinctrl-paris that implements the vendor dt-bindings") Fixes: e78d57b2f87c ("pinctrl: mediatek: add pinctrl-moore that implements the generic pinctrl dt-bindings") Signed-off-by: Justin Yeh Reviewed-by: Chen-Yu Tsai Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-moore.c | 6 ++---- drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 14 ++++---------- drivers/pinctrl/mediatek/pinctrl-paris.c | 2 +- 3 files changed, 7 insertions(+), 15 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c b/drivers/pinctrl/mediatek/pinctrl-moore.c index 17e30f83dc19..38f15dbe9a28 100644 --- a/drivers/pinctrl/mediatek/pinctrl-moore.c +++ b/drivers/pinctrl/mediatek/pinctrl-moore.c @@ -594,7 +594,7 @@ static int mtk_build_gpiochip(struct mtk_pinctrl *hw) chip->base = -1; chip->ngpio = hw->soc->npins; - ret = gpiochip_add_data(chip, hw); + ret = devm_gpiochip_add_data(hw->dev, chip, hw); if (ret < 0) return ret; @@ -608,10 +608,8 @@ static int mtk_build_gpiochip(struct mtk_pinctrl *hw) if (!of_property_present(hw->dev->of_node, "gpio-ranges")) { ret = gpiochip_add_pin_range(chip, dev_name(hw->dev), 0, 0, chip->ngpio); - if (ret < 0) { - gpiochip_remove(chip); + if (ret < 0) return ret; - } } return 0; diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index dd2c8aa03938..791eddd7a2c6 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -1130,30 +1130,24 @@ int mtk_pctrl_init(struct platform_device *pdev, pctl->chip->parent = &pdev->dev; pctl->chip->base = -1; - ret = gpiochip_add_data(pctl->chip, pctl); + ret = devm_gpiochip_add_data(&pdev->dev, pctl->chip, pctl); if (ret) return -EINVAL; /* Register the GPIO to pin mappings. */ ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), 0, 0, pctl->devdata->npins); - if (ret) { - ret = -EINVAL; - goto chip_error; - } + if (ret) + return -EINVAL; /* Only initialize EINT if we have EINT pins */ if (data->eint_hw.ap_num > 0) { ret = mtk_eint_init(pctl, pdev); if (ret) - goto chip_error; + return ret; } return 0; - -chip_error: - gpiochip_remove(pctl->chip); - return ret; } int mtk_pctrl_common_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c index 23f04b24fd65..09098b68f725 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -957,7 +957,7 @@ static int mtk_build_gpiochip(struct mtk_pinctrl *hw) chip->base = -1; chip->ngpio = hw->soc->npins; - ret = gpiochip_add_data(chip, hw); + ret = devm_gpiochip_add_data(hw->dev, chip, hw); if (ret < 0) return ret; From 88292b7103d260e3e606eb3bb2794060a5fde48e Mon Sep 17 00:00:00 2001 From: Justin Yeh Date: Thu, 23 Jul 2026 11:58:13 +0800 Subject: [PATCH 063/130] pinctrl: mediatek: free EINT resources on unbind mtk_eint_do_init() creates an IRQ domain, populates it with a mapping for every EINT line and installs a chained handler on the parent interrupt, but none of these are ever released. This was harmless while the drivers were built-in, but now that they can be built as modules and unbound/rmmod'd it leaves behind a dangling IRQ domain, interrupt mappings whose chip data points at freed memory, and a chained handler that keeps firing into that freed data. The plain allocations in mtk_eint_do_init() already use the device-managed devm_*() helpers, so tear the remaining resources down the same way: register a devm action that detaches the chained handler, waits for any in-flight handler to finish, disposes of the per-line mappings and removes the IRQ domain. This mirrors the device-managed lifecycle adopted for the GPIO chip and keeps the whole EINT setup self-cleaning on unbind. Fixes: e46df235b4e6 ("pinctrl: mediatek: refactor EINT related code for all MediaTek pinctrl can fit") Signed-off-by: Justin Yeh Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/mtk-eint.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/mediatek/mtk-eint.c b/drivers/pinctrl/mediatek/mtk-eint.c index 47ac92ea98c2..8b022545a3e9 100644 --- a/drivers/pinctrl/mediatek/mtk-eint.c +++ b/drivers/pinctrl/mediatek/mtk-eint.c @@ -12,8 +12,10 @@ */ #include +#include #include #include +#include #include #include #include @@ -509,6 +511,27 @@ int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n) } EXPORT_SYMBOL_GPL(mtk_eint_find_irq); +static void mtk_eint_teardown(void *data) +{ + struct mtk_eint *eint = data; + unsigned int i, virq; + + /* Detach the demux handler so it can no longer reference freed data. */ + irq_set_chained_handler_and_data(eint->irq, NULL, NULL); + + /* Wait for any in-flight handler to finish before tearing down. */ + synchronize_irq(eint->irq); + + /* Dispose of all child mappings before the domain is removed. */ + for (i = 0; i < eint->hw->ap_num; i++) { + virq = irq_find_mapping(eint->domain, i); + if (virq) + irq_dispose_mapping(virq); + } + + irq_domain_remove(eint->domain); +} + int mtk_eint_do_init(struct mtk_eint *eint, struct mtk_eint_pin *eint_pin) { unsigned int size, i, port, virq, inst = 0; @@ -601,7 +624,7 @@ int mtk_eint_do_init(struct mtk_eint *eint, struct mtk_eint_pin *eint_pin) irq_set_chained_handler_and_data(eint->irq, mtk_eint_irq_handler, eint); - return 0; + return devm_add_action_or_reset(eint->dev, mtk_eint_teardown, eint); err_eint: for (i = 0; i < eint->nbase; i++) { From dab3c7afde6c6572ea71d4ea7f9f6050b576cc53 Mon Sep 17 00:00:00 2001 From: Justin Yeh Date: Thu, 23 Jul 2026 11:58:14 +0800 Subject: [PATCH 064/130] pinctrl: mediatek: allow common drivers to be built as modules The MediaTek SoC pinctrl drivers link against the shared implementations in pinctrl-mtk-common.c (v1), pinctrl-moore.c and pinctrl-mtmips.c. These were built-in only: their Kconfig symbols were bool, they did not export their entry points and they carried no MODULE_LICENSE(). To let the individual SoC drivers be built as loadable modules (required for Android GKI + vendor_dlkm, where vendor drivers must live outside the GKI vmlinux), the shared code they depend on has to be modular too. Otherwise selecting a SoC driver as =m forces the common symbol to =y and the resulting module fails to link against the unexported common entry points. Convert PINCTRL_MTK, PINCTRL_MTK_MOORE and PINCTRL_MTK_MTMIPS to tristate, export the entry points used by the SoC drivers, and add MODULE_DESCRIPTION()/MODULE_LICENSE() to the three common files. The v2 common code (PINCTRL_MTK_V2) is already modular, but mtk_rmw() was never exported. It is called directly by SoC drivers such as mt7623, so export it as well to keep those drivers linking once they are modular. Rather than exporting these shared symbols into the global namespace, export them in the "MTK_PINCTRL" symbol namespace with EXPORT_SYMBOL_NS_GPL() so they are only visible to drivers that opt in. Each SoC driver that uses them therefore declares MODULE_IMPORT_NS("MTK_PINCTRL"). Signed-off-by: Justin Yeh Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/Kconfig | 6 +++--- drivers/pinctrl/mediatek/pinctrl-moore.c | 5 +++++ drivers/pinctrl/mediatek/pinctrl-mt2701.c | 2 ++ drivers/pinctrl/mediatek/pinctrl-mt2712.c | 2 ++ drivers/pinctrl/mediatek/pinctrl-mt6397.c | 2 ++ drivers/pinctrl/mediatek/pinctrl-mt7620.c | 2 ++ drivers/pinctrl/mediatek/pinctrl-mt7621.c | 2 ++ drivers/pinctrl/mediatek/pinctrl-mt7622.c | 2 ++ drivers/pinctrl/mediatek/pinctrl-mt7623.c | 2 ++ drivers/pinctrl/mediatek/pinctrl-mt7629.c | 2 ++ drivers/pinctrl/mediatek/pinctrl-mt76x8.c | 2 ++ drivers/pinctrl/mediatek/pinctrl-mt7981.c | 2 ++ drivers/pinctrl/mediatek/pinctrl-mt7986.c | 2 ++ drivers/pinctrl/mediatek/pinctrl-mt7988.c | 2 ++ drivers/pinctrl/mediatek/pinctrl-mt8127.c | 2 ++ drivers/pinctrl/mediatek/pinctrl-mt8135.c | 2 ++ drivers/pinctrl/mediatek/pinctrl-mt8167.c | 2 ++ drivers/pinctrl/mediatek/pinctrl-mt8173.c | 2 ++ drivers/pinctrl/mediatek/pinctrl-mt8365.c | 1 + drivers/pinctrl/mediatek/pinctrl-mt8516.c | 2 ++ drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 1 + drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 8 ++++++++ drivers/pinctrl/mediatek/pinctrl-mtmips.c | 4 ++++ drivers/pinctrl/mediatek/pinctrl-rt2880.c | 2 ++ drivers/pinctrl/mediatek/pinctrl-rt305x.c | 2 ++ drivers/pinctrl/mediatek/pinctrl-rt3883.c | 2 ++ 26 files changed, 62 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 95c5250150d7..ae0d10ae9022 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -11,7 +11,7 @@ config EINT_MTK default PINCTRL_MTK_PARIS config PINCTRL_MTK - bool + tristate depends on OF select PINMUX select GENERIC_PINCONF @@ -22,13 +22,13 @@ config PINCTRL_MTK_V2 tristate config PINCTRL_MTK_MTMIPS - bool + tristate depends on RALINK select PINMUX select GENERIC_PINCONF config PINCTRL_MTK_MOORE - bool + tristate depends on OF select GENERIC_PINCONF select GENERIC_PINCTRL_GROUPS diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c b/drivers/pinctrl/mediatek/pinctrl-moore.c index 38f15dbe9a28..fdfbe007b84f 100644 --- a/drivers/pinctrl/mediatek/pinctrl-moore.c +++ b/drivers/pinctrl/mediatek/pinctrl-moore.c @@ -10,6 +10,7 @@ #include #include +#include #include @@ -743,3 +744,7 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev, return 0; } +EXPORT_SYMBOL_NS_GPL(mtk_moore_pinctrl_probe, "MTK_PINCTRL"); + +MODULE_DESCRIPTION("MediaTek Pinctrl Common Driver V2 Moore"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2701.c b/drivers/pinctrl/mediatek/pinctrl-mt2701.c index 6b1c7122b0fb..d262f810e40b 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt2701.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c @@ -542,3 +542,5 @@ static int __init mtk_pinctrl_init(void) return platform_driver_register(&mtk_pinctrl_driver); } arch_initcall(mtk_pinctrl_init); + +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2712.c b/drivers/pinctrl/mediatek/pinctrl-mt2712.c index bb7394ae252b..aa8f9650c157 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt2712.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c @@ -591,3 +591,5 @@ static int __init mtk_pinctrl_init(void) } arch_initcall(mtk_pinctrl_init); + +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6397.c b/drivers/pinctrl/mediatek/pinctrl-mt6397.c index 03d0f65d7bcc..be691edf3e65 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6397.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6397.c @@ -59,3 +59,5 @@ static struct platform_driver mtk_pinctrl_driver = { }; builtin_platform_driver(mtk_pinctrl_driver); + +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7620.c b/drivers/pinctrl/mediatek/pinctrl-mt7620.c index d2624b9b5bc4..e5d368530247 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7620.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7620.c @@ -135,3 +135,5 @@ static int __init mt7620_pinctrl_init(void) return platform_driver_register(&mt7620_pinctrl_driver); } core_initcall_sync(mt7620_pinctrl_init); + +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7621.c b/drivers/pinctrl/mediatek/pinctrl-mt7621.c index b18c1a47bbeb..b337936e5c18 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7621.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7621.c @@ -115,3 +115,5 @@ static int __init mt7621_pinctrl_init(void) return platform_driver_register(&mt7621_pinctrl_driver); } core_initcall_sync(mt7621_pinctrl_init); + +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7622.c b/drivers/pinctrl/mediatek/pinctrl-mt7622.c index d5777889448a..38830f6dc5fd 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7622.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c @@ -893,3 +893,5 @@ static int __init mt7622_pinctrl_init(void) return platform_driver_register(&mt7622_pinctrl_driver); } arch_initcall(mt7622_pinctrl_init); + +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7623.c b/drivers/pinctrl/mediatek/pinctrl-mt7623.c index 69c06c2c0e21..a36124036daa 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7623.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c @@ -1440,3 +1440,5 @@ static int __init mtk_pinctrl_init(void) return platform_driver_register(&mtk_pinctrl_driver); } arch_initcall(mtk_pinctrl_init); + +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7629.c b/drivers/pinctrl/mediatek/pinctrl-mt7629.c index cc0694881ac9..57868f73fce2 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7629.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c @@ -449,3 +449,5 @@ static int __init mt7629_pinctrl_init(void) return platform_driver_register(&mt7629_pinctrl_driver); } arch_initcall(mt7629_pinctrl_init); + +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt76x8.c b/drivers/pinctrl/mediatek/pinctrl-mt76x8.c index 2bc8d4409ca2..9c064bf94935 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt76x8.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt76x8.c @@ -247,3 +247,5 @@ static int __init mt76x8_pinctrl_init(void) return platform_driver_register(&mt76x8_pinctrl_driver); } core_initcall_sync(mt76x8_pinctrl_init); + +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7981.c b/drivers/pinctrl/mediatek/pinctrl-mt7981.c index 22c8f2480346..69b16b01b4b3 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c @@ -1058,3 +1058,5 @@ static int __init mt7981_pinctrl_init(void) return platform_driver_register(&mt7981_pinctrl_driver); } arch_initcall(mt7981_pinctrl_init); + +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7986.c b/drivers/pinctrl/mediatek/pinctrl-mt7986.c index 5dda4b7467fd..ca468115765b 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c @@ -1009,3 +1009,5 @@ static int __init mt7986b_pinctrl_init(void) arch_initcall(mt7986a_pinctrl_init); arch_initcall(mt7986b_pinctrl_init); + +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7988.c b/drivers/pinctrl/mediatek/pinctrl-mt7988.c index fd3a7ff0a04d..d90456c55c0b 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7988.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7988.c @@ -1544,3 +1544,5 @@ static int __init mt7988_pinctrl_init(void) return platform_driver_register(&mt7988_pinctrl_driver); } arch_initcall(mt7988_pinctrl_init); + +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8127.c b/drivers/pinctrl/mediatek/pinctrl-mt8127.c index f5030a9ea40b..34d840c1cc6a 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8127.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8127.c @@ -307,3 +307,5 @@ static int __init mtk_pinctrl_init(void) return platform_driver_register(&mtk_pinctrl_driver); } arch_initcall(mtk_pinctrl_init); + +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8135.c b/drivers/pinctrl/mediatek/pinctrl-mt8135.c index 77c6ac464e86..635048f9d1f2 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8135.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c @@ -336,3 +336,5 @@ static int __init mtk_pinctrl_init(void) return platform_driver_register(&mtk_pinctrl_driver); } arch_initcall(mtk_pinctrl_init); + +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8167.c b/drivers/pinctrl/mediatek/pinctrl-mt8167.c index c812d614e9d4..3bd8288795e4 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8167.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8167.c @@ -343,3 +343,5 @@ static int __init mtk_pinctrl_init(void) return platform_driver_register(&mtk_pinctrl_driver); } arch_initcall(mtk_pinctrl_init); + +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/drivers/pinctrl/mediatek/pinctrl-mt8173.c index b214deeafbf1..20dd324eb152 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c @@ -356,3 +356,5 @@ static int __init mtk_pinctrl_init(void) return platform_driver_register(&mtk_pinctrl_driver); } arch_initcall(mtk_pinctrl_init); + +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8365.c b/drivers/pinctrl/mediatek/pinctrl-mt8365.c index c20b9e2e02dd..73849ae569c9 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c @@ -495,3 +495,4 @@ arch_initcall(mtk_pinctrl_init); MODULE_DESCRIPTION("MediaTek MT8365 Pinctrl Driver"); MODULE_AUTHOR("Zhiyong Tao "); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8516.c b/drivers/pinctrl/mediatek/pinctrl-mt8516.c index 68d6638e7f4b..62084d0cc4c9 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8516.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c @@ -343,3 +343,5 @@ static int __init mtk_pinctrl_init(void) return platform_driver_register(&mtk_pinctrl_driver); } arch_initcall(mtk_pinctrl_init); + +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c index 4918d38abfc2..802f780120bf 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c @@ -69,6 +69,7 @@ void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set) spin_unlock_irqrestore(&pctl->lock, flags); } +EXPORT_SYMBOL_NS_GPL(mtk_rmw, "MTK_PINCTRL"); static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 791eddd7a2c6..1a977acd6883 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -190,6 +191,7 @@ int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap, regmap_write(regmap, reg_addr, bit); return 0; } +EXPORT_SYMBOL_NS_GPL(mtk_pconf_spec_set_ies_smt_range, "MTK_PINCTRL"); static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin( struct mtk_pinctrl *pctl, unsigned long pin) { @@ -297,6 +299,7 @@ int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, return 0; } +EXPORT_SYMBOL_NS_GPL(mtk_pctrl_spec_pull_set_samereg, "MTK_PINCTRL"); static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl, unsigned int pin, bool enable, bool isup, unsigned int arg) @@ -1149,6 +1152,7 @@ int mtk_pctrl_init(struct platform_device *pdev, return 0; } +EXPORT_SYMBOL_NS_GPL(mtk_pctrl_init, "MTK_PINCTRL"); int mtk_pctrl_common_probe(struct platform_device *pdev) { @@ -1160,3 +1164,7 @@ int mtk_pctrl_common_probe(struct platform_device *pdev) return mtk_pctrl_init(pdev, data, NULL); } +EXPORT_SYMBOL_NS_GPL(mtk_pctrl_common_probe, "MTK_PINCTRL"); + +MODULE_DESCRIPTION("MediaTek Pinctrl Common Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtmips.c b/drivers/pinctrl/mediatek/pinctrl-mtmips.c index efd77b6c56a1..b2d7a79ff9cc 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtmips.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtmips.c @@ -349,3 +349,7 @@ int mtmips_pinctrl_init(struct platform_device *pdev, return PTR_ERR_OR_ZERO(dev); } +EXPORT_SYMBOL_NS_GPL(mtmips_pinctrl_init, "MTK_PINCTRL"); + +MODULE_DESCRIPTION("MediaTek MIPS Pinctrl Common Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-rt2880.c b/drivers/pinctrl/mediatek/pinctrl-rt2880.c index e0366721a515..a9c4acdc6766 100644 --- a/drivers/pinctrl/mediatek/pinctrl-rt2880.c +++ b/drivers/pinctrl/mediatek/pinctrl-rt2880.c @@ -59,3 +59,5 @@ static int __init rt2880_pinctrl_init(void) return platform_driver_register(&rt2880_pinctrl_driver); } core_initcall_sync(rt2880_pinctrl_init); + +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-rt305x.c b/drivers/pinctrl/mediatek/pinctrl-rt305x.c index 77bd4d1f6122..93788ec49ed0 100644 --- a/drivers/pinctrl/mediatek/pinctrl-rt305x.c +++ b/drivers/pinctrl/mediatek/pinctrl-rt305x.c @@ -138,3 +138,5 @@ static int __init rt305x_pinctrl_init(void) return platform_driver_register(&rt305x_pinctrl_driver); } core_initcall_sync(rt305x_pinctrl_init); + +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-rt3883.c b/drivers/pinctrl/mediatek/pinctrl-rt3883.c index eeaf344c3647..afe705a0ddf6 100644 --- a/drivers/pinctrl/mediatek/pinctrl-rt3883.c +++ b/drivers/pinctrl/mediatek/pinctrl-rt3883.c @@ -106,3 +106,5 @@ static int __init rt3883_pinctrl_init(void) return platform_driver_register(&rt3883_pinctrl_driver); } core_initcall_sync(rt3883_pinctrl_init); + +MODULE_IMPORT_NS("MTK_PINCTRL"); From e3b4295e0d72186d8c929052fef8ce83ddb20aec Mon Sep 17 00:00:00 2001 From: Justin Yeh Date: Thu, 23 Jul 2026 11:58:15 +0800 Subject: [PATCH 065/130] pinctrl: mediatek: mt7986: register both platform drivers from a single initcall The MT7986 driver registers two separate platform drivers (mt7986a and mt7986b) and used to call arch_initcall() twice, once for each. This is fine while the driver is built-in, but a single translation unit can only provide one module_init(). Since arch_initcall() expands to module_init() when built as a module, having two of them would break the module build with a redefinition of init_module()/__inittest(). Fold both platform drivers into a single driver array and register them from one initcall using platform_register_drivers(), matching the shape of the other MediaTek pinctrl SoC drivers. platform_register_drivers() also rolls back the first registration if the second one fails. No functional change for built-in builds; this is a preparatory cleanup for enabling module builds. Signed-off-by: Justin Yeh Reviewed-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-mt7986.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7986.c b/drivers/pinctrl/mediatek/pinctrl-mt7986.c index ca468115765b..d7c7591ed231 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c @@ -997,17 +997,16 @@ static struct platform_driver mt7986b_pinctrl_driver = { .probe = mt7986b_pinctrl_probe, }; -static int __init mt7986a_pinctrl_init(void) -{ - return platform_driver_register(&mt7986a_pinctrl_driver); -} +static struct platform_driver * const mt7986_pinctrl_drivers[] = { + &mt7986a_pinctrl_driver, + &mt7986b_pinctrl_driver, +}; -static int __init mt7986b_pinctrl_init(void) +static int __init mt7986_pinctrl_init(void) { - return platform_driver_register(&mt7986b_pinctrl_driver); + return platform_register_drivers(mt7986_pinctrl_drivers, + ARRAY_SIZE(mt7986_pinctrl_drivers)); } - -arch_initcall(mt7986a_pinctrl_init); -arch_initcall(mt7986b_pinctrl_init); +arch_initcall(mt7986_pinctrl_init); MODULE_IMPORT_NS("MTK_PINCTRL"); From 5f30668104fe7ed2959ffeb67459a0288022b50e Mon Sep 17 00:00:00 2001 From: Justin Yeh Date: Thu, 23 Jul 2026 11:58:16 +0800 Subject: [PATCH 066/130] pinctrl: mediatek: enable module build support for all SoC drivers Convert the Kconfig option of every MediaTek pinctrl SoC driver from bool to tristate and add MODULE_DESCRIPTION()/MODULE_LICENSE() so that they can be built as loadable kernel modules. This is required for Android GKI + vendor_dlkm deployments, where vendor-specific drivers must be kept separate from the GKI vmlinux and loaded as modules from the vendor partition. Signed-off-by: Justin Yeh Reviewed-by: AngeloGioacchino Del Regno [linusw@kernel.org: Rebased and added MT6858] Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/Kconfig | 66 +++++++++++------------ drivers/pinctrl/mediatek/pinctrl-mt2701.c | 2 + drivers/pinctrl/mediatek/pinctrl-mt2712.c | 2 + drivers/pinctrl/mediatek/pinctrl-mt6397.c | 3 ++ drivers/pinctrl/mediatek/pinctrl-mt6795.c | 4 ++ drivers/pinctrl/mediatek/pinctrl-mt6797.c | 4 ++ drivers/pinctrl/mediatek/pinctrl-mt6858.c | 2 + drivers/pinctrl/mediatek/pinctrl-mt6878.c | 2 + drivers/pinctrl/mediatek/pinctrl-mt6893.c | 2 + drivers/pinctrl/mediatek/pinctrl-mt7620.c | 2 + drivers/pinctrl/mediatek/pinctrl-mt7621.c | 2 + drivers/pinctrl/mediatek/pinctrl-mt7622.c | 3 ++ drivers/pinctrl/mediatek/pinctrl-mt7623.c | 3 ++ drivers/pinctrl/mediatek/pinctrl-mt7629.c | 3 ++ drivers/pinctrl/mediatek/pinctrl-mt76x8.c | 2 + drivers/pinctrl/mediatek/pinctrl-mt7981.c | 3 ++ drivers/pinctrl/mediatek/pinctrl-mt7986.c | 4 ++ drivers/pinctrl/mediatek/pinctrl-mt7988.c | 3 ++ drivers/pinctrl/mediatek/pinctrl-mt8127.c | 3 ++ drivers/pinctrl/mediatek/pinctrl-mt8135.c | 3 ++ drivers/pinctrl/mediatek/pinctrl-mt8167.c | 2 + drivers/pinctrl/mediatek/pinctrl-mt8173.c | 3 ++ drivers/pinctrl/mediatek/pinctrl-mt8183.c | 4 ++ drivers/pinctrl/mediatek/pinctrl-mt8186.c | 4 ++ drivers/pinctrl/mediatek/pinctrl-mt8188.c | 2 + drivers/pinctrl/mediatek/pinctrl-mt8189.c | 2 + drivers/pinctrl/mediatek/pinctrl-mt8192.c | 2 + drivers/pinctrl/mediatek/pinctrl-mt8195.c | 4 ++ drivers/pinctrl/mediatek/pinctrl-mt8196.c | 2 + drivers/pinctrl/mediatek/pinctrl-mt8365.c | 2 + drivers/pinctrl/mediatek/pinctrl-mt8516.c | 2 + drivers/pinctrl/mediatek/pinctrl-rt2880.c | 2 + drivers/pinctrl/mediatek/pinctrl-rt305x.c | 2 + drivers/pinctrl/mediatek/pinctrl-rt3883.c | 2 + 34 files changed, 120 insertions(+), 33 deletions(-) diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index ae0d10ae9022..30ef3dc5dfb1 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -48,42 +48,42 @@ config PINCTRL_MTK_PARIS # For MIPS SoCs config PINCTRL_MT7620 - bool "MediaTek MT7620 pin control" + tristate "MediaTek MT7620 pin control" depends on SOC_MT7620 || COMPILE_TEST depends on RALINK default SOC_MT7620 select PINCTRL_MTK_MTMIPS config PINCTRL_MT7621 - bool "MediaTek MT7621 pin control" + tristate "MediaTek MT7621 pin control" depends on SOC_MT7621 || COMPILE_TEST depends on RALINK default SOC_MT7621 select PINCTRL_MTK_MTMIPS config PINCTRL_MT76X8 - bool "MediaTek MT76X8 pin control" + tristate "MediaTek MT76X8 pin control" depends on SOC_MT7620 || COMPILE_TEST depends on RALINK default SOC_MT7620 select PINCTRL_MTK_MTMIPS config PINCTRL_RT2880 - bool "Ralink RT2880 pin control" + tristate "Ralink RT2880 pin control" depends on SOC_RT288X || COMPILE_TEST depends on RALINK default SOC_RT288X select PINCTRL_MTK_MTMIPS config PINCTRL_RT305X - bool "Ralink RT305X pin control" + tristate "Ralink RT305X pin control" depends on SOC_RT305X || COMPILE_TEST depends on RALINK default SOC_RT305X select PINCTRL_MTK_MTMIPS config PINCTRL_RT3883 - bool "Ralink RT3883 pin control" + tristate "Ralink RT3883 pin control" depends on SOC_RT3883 || COMPILE_TEST depends on RALINK default SOC_RT3883 @@ -91,35 +91,35 @@ config PINCTRL_RT3883 # For ARMv7 SoCs config PINCTRL_MT2701 - bool "MediaTek MT2701 pin control" + tristate "MediaTek MT2701 pin control" depends on MACH_MT7623 || MACH_MT2701 || COMPILE_TEST depends on OF default MACH_MT2701 select PINCTRL_MTK config PINCTRL_MT7623 - bool "MediaTek MT7623 pin control with generic binding" + tristate "MediaTek MT7623 pin control with generic binding" depends on MACH_MT7623 || COMPILE_TEST depends on OF default MACH_MT7623 select PINCTRL_MTK_MOORE config PINCTRL_MT7629 - bool "MediaTek MT7629 pin control" + tristate "MediaTek MT7629 pin control" depends on MACH_MT7629 || COMPILE_TEST depends on OF default MACH_MT7629 select PINCTRL_MTK_MOORE config PINCTRL_MT8135 - bool "MediaTek MT8135 pin control" + tristate "MediaTek MT8135 pin control" depends on MACH_MT8135 || COMPILE_TEST depends on OF default MACH_MT8135 select PINCTRL_MTK config PINCTRL_MT8127 - bool "MediaTek MT8127 pin control" + tristate "MediaTek MT8127 pin control" depends on MACH_MT8127 || COMPILE_TEST depends on OF default MACH_MT8127 @@ -127,7 +127,7 @@ config PINCTRL_MT8127 # For ARMv8 SoCs config PINCTRL_MT2712 - bool "MediaTek MT2712 pin control" + tristate "MediaTek MT2712 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK @@ -153,21 +153,21 @@ config PINCTRL_MT6779 map specific eint which doesn't have real gpio pin. config PINCTRL_MT6795 - bool "MediaTek MT6795 pin control" + tristate "MediaTek MT6795 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_PARIS config PINCTRL_MT6797 - bool "MediaTek MT6797 pin control" + tristate "MediaTek MT6797 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_PARIS config PINCTRL_MT6858 - bool "MediaTek MT6858 pin control" + tristate "MediaTek MT6858 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK @@ -177,7 +177,7 @@ config PINCTRL_MT6858 on the MediaTek MT6858 SoC. config PINCTRL_MT6878 - bool "MediaTek MT6878 pin control" + tristate "MediaTek MT6878 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK @@ -187,7 +187,7 @@ config PINCTRL_MT6878 on the MediaTek MT6878 SoC. config PINCTRL_MT6893 - bool "MediaTek Dimensity MT6893 pin control" + tristate "MediaTek Dimensity MT6893 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK @@ -197,63 +197,63 @@ config PINCTRL_MT6893 on the MediaTek Dimensity 1200 MT6893 Smartphone SoC. config PINCTRL_MT7622 - bool "MediaTek MT7622 pin control" + tristate "MediaTek MT7622 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_MOORE config PINCTRL_MT7981 - bool "MediaTek MT7981 pin control" + tristate "MediaTek MT7981 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_MOORE config PINCTRL_MT7986 - bool "MediaTek MT7986 pin control" + tristate "MediaTek MT7986 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_MOORE config PINCTRL_MT7988 - bool "Mediatek MT7988 pin control" + tristate "Mediatek MT7988 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_MOORE config PINCTRL_MT8167 - bool "MediaTek MT8167 pin control" + tristate "MediaTek MT8167 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK config PINCTRL_MT8173 - bool "MediaTek MT8173 pin control" + tristate "MediaTek MT8173 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK config PINCTRL_MT8183 - bool "MediaTek MT8183 pin control" + tristate "MediaTek MT8183 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_PARIS config PINCTRL_MT8186 - bool "MediaTek MT8186 pin control" + tristate "MediaTek MT8186 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_PARIS config PINCTRL_MT8188 - bool "MediaTek MT8188 pin control" + tristate "MediaTek MT8188 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK @@ -265,7 +265,7 @@ config PINCTRL_MT8188 map specific eint which doesn't have real gpio pin. config PINCTRL_MT8189 - bool "MediaTek MT8189 pin control" + tristate "MediaTek MT8189 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK @@ -277,21 +277,21 @@ config PINCTRL_MT8189 map specific eint which doesn't have real gpio pin. config PINCTRL_MT8192 - bool "MediaTek MT8192 pin control" + tristate "MediaTek MT8192 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_PARIS config PINCTRL_MT8195 - bool "MediaTek MT8195 pin control" + tristate "MediaTek MT8195 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_PARIS config PINCTRL_MT8196 - bool "MediaTek MT8196 pin control" + tristate "MediaTek MT8196 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK @@ -303,14 +303,14 @@ config PINCTRL_MT8196 map specific eint which doesn't have real gpio pin. config PINCTRL_MT8365 - bool "MediaTek MT8365 pin control" + tristate "MediaTek MT8365 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK config PINCTRL_MT8516 - bool "MediaTek MT8516 pin control" + tristate "MediaTek MT8516 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK @@ -318,7 +318,7 @@ config PINCTRL_MT8516 # For PMIC config PINCTRL_MT6397 - bool "MediaTek MT6397 pin control" + tristate "MediaTek MT6397 pin control" depends on MFD_MT6397 || COMPILE_TEST depends on OF default MFD_MT6397 diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2701.c b/drivers/pinctrl/mediatek/pinctrl-mt2701.c index d262f810e40b..9e04f5b7cbba 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt2701.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c @@ -543,4 +543,6 @@ static int __init mtk_pinctrl_init(void) } arch_initcall(mtk_pinctrl_init); +MODULE_DESCRIPTION("MediaTek MT2701 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2712.c b/drivers/pinctrl/mediatek/pinctrl-mt2712.c index aa8f9650c157..c7df168c314d 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt2712.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c @@ -592,4 +592,6 @@ static int __init mtk_pinctrl_init(void) arch_initcall(mtk_pinctrl_init); +MODULE_DESCRIPTION("MediaTek MT2712 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6397.c b/drivers/pinctrl/mediatek/pinctrl-mt6397.c index be691edf3e65..13cee2a209c2 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6397.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6397.c @@ -49,6 +49,7 @@ static const struct of_device_id mt6397_pctrl_match[] = { { .compatible = "mediatek,mt6397-pinctrl", }, { } }; +MODULE_DEVICE_TABLE(of, mt6397_pctrl_match); static struct platform_driver mtk_pinctrl_driver = { .probe = mt6397_pinctrl_probe, @@ -60,4 +61,6 @@ static struct platform_driver mtk_pinctrl_driver = { builtin_platform_driver(mtk_pinctrl_driver); +MODULE_DESCRIPTION("MediaTek MT6397 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6795.c b/drivers/pinctrl/mediatek/pinctrl-mt6795.c index ee3ae3d2fa7e..82df5cafc3d3 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6795.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6795.c @@ -607,6 +607,7 @@ static const struct of_device_id mt6795_pctrl_match[] = { { .compatible = "mediatek,mt6795-pinctrl", .data = &mt6795_data }, { } }; +MODULE_DEVICE_TABLE(of, mt6795_pctrl_match); static struct platform_driver mt6795_pinctrl_driver = { .driver = { @@ -622,3 +623,6 @@ static int __init mtk_pinctrl_init(void) return platform_driver_register(&mt6795_pinctrl_driver); } arch_initcall(mtk_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT6795 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6797.c b/drivers/pinctrl/mediatek/pinctrl-mt6797.c index 53f240491259..6d4a5b16035f 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6797.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6797.c @@ -61,6 +61,7 @@ static const struct of_device_id mt6797_pinctrl_of_match[] = { { .compatible = "mediatek,mt6797-pinctrl", .data = &mt6797_data }, { } }; +MODULE_DEVICE_TABLE(of, mt6797_pinctrl_of_match); static struct platform_driver mt6797_pinctrl_driver = { .driver = { @@ -75,3 +76,6 @@ static int __init mt6797_pinctrl_init(void) return platform_driver_register(&mt6797_pinctrl_driver); } arch_initcall(mt6797_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT6797 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6858.c b/drivers/pinctrl/mediatek/pinctrl-mt6858.c index 07f72d9d531f..996b826e00d0 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6858.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6858.c @@ -1388,6 +1388,7 @@ static const struct of_device_id mt6858_pinctrl_of_match[] = { { .compatible = "mediatek,mt6858-pinctrl", .data = &mt6858_data }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, mt6858_pinctrl_of_match); static struct platform_driver mt6858_pinctrl_driver = { .driver = { @@ -1405,3 +1406,4 @@ static int __init mt6858_pinctrl_init(void) arch_initcall(mt6858_pinctrl_init); MODULE_DESCRIPTION("MediaTek MT6858 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6878.c b/drivers/pinctrl/mediatek/pinctrl-mt6878.c index b59ae089128a..7b5a15f4aba1 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6878.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6878.c @@ -1459,6 +1459,7 @@ static const struct of_device_id mt6878_pinctrl_of_match[] = { { .compatible = "mediatek,mt6878-pinctrl", .data = &mt6878_data }, { } }; +MODULE_DEVICE_TABLE(of, mt6878_pinctrl_of_match); static struct platform_driver mt6878_pinctrl_driver = { .driver = { @@ -1476,3 +1477,4 @@ static int __init mt6878_pinctrl_init(void) arch_initcall(mt6878_pinctrl_init); MODULE_DESCRIPTION("MediaTek MT6878 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6893.c b/drivers/pinctrl/mediatek/pinctrl-mt6893.c index 468ce0109b07..5ff1e7722889 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6893.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6893.c @@ -859,6 +859,7 @@ static const struct of_device_id mt6893_pinctrl_of_match[] = { { .compatible = "mediatek,mt6893-pinctrl", .data = &mt6893_data }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, mt6893_pinctrl_of_match); static struct platform_driver mt6893_pinctrl_driver = { .driver = { @@ -877,3 +878,4 @@ static int __init mt6893_pinctrl_init(void) arch_initcall(mt6893_pinctrl_init); MODULE_DESCRIPTION("MediaTek MT6893 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7620.c b/drivers/pinctrl/mediatek/pinctrl-mt7620.c index e5d368530247..7bfa6a8a3ce3 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7620.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7620.c @@ -136,4 +136,6 @@ static int __init mt7620_pinctrl_init(void) } core_initcall_sync(mt7620_pinctrl_init); +MODULE_DESCRIPTION("MediaTek MT7620 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7621.c b/drivers/pinctrl/mediatek/pinctrl-mt7621.c index b337936e5c18..5a893d8505a3 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7621.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7621.c @@ -116,4 +116,6 @@ static int __init mt7621_pinctrl_init(void) } core_initcall_sync(mt7621_pinctrl_init); +MODULE_DESCRIPTION("MediaTek MT7621 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7622.c b/drivers/pinctrl/mediatek/pinctrl-mt7622.c index 38830f6dc5fd..36a9a9f302ca 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7622.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c @@ -874,6 +874,7 @@ static const struct of_device_id mt7622_pinctrl_of_match[] = { { .compatible = "mediatek,mt7622-pinctrl", }, { } }; +MODULE_DEVICE_TABLE(of, mt7622_pinctrl_of_match); static int mt7622_pinctrl_probe(struct platform_device *pdev) { @@ -894,4 +895,6 @@ static int __init mt7622_pinctrl_init(void) } arch_initcall(mt7622_pinctrl_init); +MODULE_DESCRIPTION("MediaTek MT7622 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7623.c b/drivers/pinctrl/mediatek/pinctrl-mt7623.c index a36124036daa..26fa489db13c 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7623.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c @@ -1413,6 +1413,7 @@ static const struct of_device_id mt7623_pctrl_match[] = { { .compatible = "mediatek,mt7623-moore-pinctrl", }, {} }; +MODULE_DEVICE_TABLE(of, mt7623_pctrl_match); static int mt7623_pinctrl_probe(struct platform_device *pdev) { @@ -1441,4 +1442,6 @@ static int __init mtk_pinctrl_init(void) } arch_initcall(mtk_pinctrl_init); +MODULE_DESCRIPTION("MediaTek MT7623 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7629.c b/drivers/pinctrl/mediatek/pinctrl-mt7629.c index 57868f73fce2..385d66b8e3fb 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7629.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c @@ -430,6 +430,7 @@ static const struct of_device_id mt7629_pinctrl_of_match[] = { { .compatible = "mediatek,mt7629-pinctrl", }, {} }; +MODULE_DEVICE_TABLE(of, mt7629_pinctrl_of_match); static int mt7629_pinctrl_probe(struct platform_device *pdev) { @@ -450,4 +451,6 @@ static int __init mt7629_pinctrl_init(void) } arch_initcall(mt7629_pinctrl_init); +MODULE_DESCRIPTION("MediaTek MT7629 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt76x8.c b/drivers/pinctrl/mediatek/pinctrl-mt76x8.c index 9c064bf94935..336d4e36e884 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt76x8.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt76x8.c @@ -248,4 +248,6 @@ static int __init mt76x8_pinctrl_init(void) } core_initcall_sync(mt76x8_pinctrl_init); +MODULE_DESCRIPTION("MediaTek MT76X8 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7981.c b/drivers/pinctrl/mediatek/pinctrl-mt7981.c index 69b16b01b4b3..2325cc8b9345 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c @@ -1039,6 +1039,7 @@ static const struct of_device_id mt7981_pinctrl_of_match[] = { { .compatible = "mediatek,mt7981-pinctrl", }, {} }; +MODULE_DEVICE_TABLE(of, mt7981_pinctrl_of_match); static int mt7981_pinctrl_probe(struct platform_device *pdev) { @@ -1059,4 +1060,6 @@ static int __init mt7981_pinctrl_init(void) } arch_initcall(mt7981_pinctrl_init); +MODULE_DESCRIPTION("MediaTek MT7981 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7986.c b/drivers/pinctrl/mediatek/pinctrl-mt7986.c index d7c7591ed231..6cbf90879eb5 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c @@ -965,11 +965,13 @@ static const struct of_device_id mt7986a_pinctrl_of_match[] = { {.compatible = "mediatek,mt7986a-pinctrl",}, {} }; +MODULE_DEVICE_TABLE(of, mt7986a_pinctrl_of_match); static const struct of_device_id mt7986b_pinctrl_of_match[] = { {.compatible = "mediatek,mt7986b-pinctrl",}, {} }; +MODULE_DEVICE_TABLE(of, mt7986b_pinctrl_of_match); static int mt7986a_pinctrl_probe(struct platform_device *pdev) { @@ -1009,4 +1011,6 @@ static int __init mt7986_pinctrl_init(void) } arch_initcall(mt7986_pinctrl_init); +MODULE_DESCRIPTION("MediaTek MT7986 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7988.c b/drivers/pinctrl/mediatek/pinctrl-mt7988.c index d90456c55c0b..14b5f4b695a2 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7988.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7988.c @@ -1525,6 +1525,7 @@ static const struct of_device_id mt7988_pinctrl_of_match[] = { { .compatible = "mediatek,mt7988-pinctrl" }, {} }; +MODULE_DEVICE_TABLE(of, mt7988_pinctrl_of_match); static int mt7988_pinctrl_probe(struct platform_device *pdev) { @@ -1545,4 +1546,6 @@ static int __init mt7988_pinctrl_init(void) } arch_initcall(mt7988_pinctrl_init); +MODULE_DESCRIPTION("MediaTek MT7988 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8127.c b/drivers/pinctrl/mediatek/pinctrl-mt8127.c index 34d840c1cc6a..296eed43c10a 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8127.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8127.c @@ -293,6 +293,7 @@ static const struct of_device_id mt8127_pctrl_match[] = { { .compatible = "mediatek,mt8127-pinctrl", .data = &mt8127_pinctrl_data }, { } }; +MODULE_DEVICE_TABLE(of, mt8127_pctrl_match); static struct platform_driver mtk_pinctrl_driver = { .probe = mtk_pctrl_common_probe, @@ -308,4 +309,6 @@ static int __init mtk_pinctrl_init(void) } arch_initcall(mtk_pinctrl_init); +MODULE_DESCRIPTION("MediaTek MT8127 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8135.c b/drivers/pinctrl/mediatek/pinctrl-mt8135.c index 635048f9d1f2..713b362832db 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8135.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c @@ -322,6 +322,7 @@ static const struct of_device_id mt8135_pctrl_match[] = { { .compatible = "mediatek,mt8135-pinctrl", .data = &mt8135_pinctrl_data }, { } }; +MODULE_DEVICE_TABLE(of, mt8135_pctrl_match); static struct platform_driver mtk_pinctrl_driver = { .probe = mtk_pctrl_common_probe, @@ -337,4 +338,6 @@ static int __init mtk_pinctrl_init(void) } arch_initcall(mtk_pinctrl_init); +MODULE_DESCRIPTION("MediaTek MT8135 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8167.c b/drivers/pinctrl/mediatek/pinctrl-mt8167.c index 3bd8288795e4..cc45b0954009 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8167.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8167.c @@ -344,4 +344,6 @@ static int __init mtk_pinctrl_init(void) } arch_initcall(mtk_pinctrl_init); +MODULE_DESCRIPTION("MediaTek MT8167 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/drivers/pinctrl/mediatek/pinctrl-mt8173.c index 20dd324eb152..fbb92a1b9d2c 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c @@ -341,6 +341,7 @@ static const struct of_device_id mt8173_pctrl_match[] = { }, { } }; +MODULE_DEVICE_TABLE(of, mt8173_pctrl_match); static struct platform_driver mtk_pinctrl_driver = { .probe = mt8173_pinctrl_probe, @@ -357,4 +358,6 @@ static int __init mtk_pinctrl_init(void) } arch_initcall(mtk_pinctrl_init); +MODULE_DESCRIPTION("MediaTek MT8173 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8183.c b/drivers/pinctrl/mediatek/pinctrl-mt8183.c index 93e482c6b5fd..edc68f998d8c 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8183.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8183.c @@ -571,6 +571,7 @@ static const struct of_device_id mt8183_pinctrl_of_match[] = { { .compatible = "mediatek,mt8183-pinctrl", .data = &mt8183_data }, { } }; +MODULE_DEVICE_TABLE(of, mt8183_pinctrl_of_match); static struct platform_driver mt8183_pinctrl_driver = { .driver = { @@ -586,3 +587,6 @@ static int __init mt8183_pinctrl_init(void) return platform_driver_register(&mt8183_pinctrl_driver); } arch_initcall(mt8183_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT8183 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8186.c b/drivers/pinctrl/mediatek/pinctrl-mt8186.c index dd19e74856a9..d4817838c531 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8186.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8186.c @@ -1249,6 +1249,7 @@ static const struct of_device_id mt8186_pinctrl_of_match[] = { { .compatible = "mediatek,mt8186-pinctrl", .data = &mt8186_data }, { } }; +MODULE_DEVICE_TABLE(of, mt8186_pinctrl_of_match); static struct platform_driver mt8186_pinctrl_driver = { .driver = { @@ -1265,3 +1266,6 @@ static int __init mt8186_pinctrl_init(void) } arch_initcall(mt8186_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT8186 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8188.c b/drivers/pinctrl/mediatek/pinctrl-mt8188.c index 3975e99d9cf4..35dde16ab449 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8188.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8188.c @@ -1653,6 +1653,7 @@ static const struct of_device_id mt8188_pinctrl_of_match[] = { { .compatible = "mediatek,mt8188-pinctrl", .data = &mt8188_data }, { } }; +MODULE_DEVICE_TABLE(of, mt8188_pinctrl_of_match); static struct platform_driver mt8188_pinctrl_driver = { .driver = { @@ -1671,3 +1672,4 @@ static int __init mt8188_pinctrl_init(void) arch_initcall(mt8188_pinctrl_init); MODULE_DESCRIPTION("MediaTek MT8188 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8189.c b/drivers/pinctrl/mediatek/pinctrl-mt8189.c index cd4cdff309a1..1b1f9b4b6ad1 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8189.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8189.c @@ -1679,6 +1679,7 @@ static const struct of_device_id mt8189_pinctrl_of_match[] = { { .compatible = "mediatek,mt8189-pinctrl", .data = &mt8189_data }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, mt8189_pinctrl_of_match); static struct platform_driver mt8189_pinctrl_driver = { .driver = { @@ -1696,3 +1697,4 @@ static int __init mt8189_pinctrl_init(void) arch_initcall(mt8189_pinctrl_init); MODULE_DESCRIPTION("MediaTek MT8189 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8192.c b/drivers/pinctrl/mediatek/pinctrl-mt8192.c index 3f8a9dbcb704..b2ae3a62418d 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8192.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8192.c @@ -1414,6 +1414,7 @@ static const struct of_device_id mt8192_pinctrl_of_match[] = { { .compatible = "mediatek,mt8192-pinctrl", .data = &mt8192_data }, { } }; +MODULE_DEVICE_TABLE(of, mt8192_pinctrl_of_match); static struct platform_driver mt8192_pinctrl_driver = { .driver = { @@ -1431,3 +1432,4 @@ static int __init mt8192_pinctrl_init(void) arch_initcall(mt8192_pinctrl_init); MODULE_DESCRIPTION("MediaTek MT8192 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8195.c b/drivers/pinctrl/mediatek/pinctrl-mt8195.c index 83345c52b2fa..3a9912c0c095 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8195.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8195.c @@ -963,6 +963,7 @@ static const struct of_device_id mt8195_pinctrl_of_match[] = { { .compatible = "mediatek,mt8195-pinctrl", .data = &mt8195_data }, { } }; +MODULE_DEVICE_TABLE(of, mt8195_pinctrl_of_match); static struct platform_driver mt8195_pinctrl_driver = { .driver = { @@ -978,3 +979,6 @@ static int __init mt8195_pinctrl_init(void) return platform_driver_register(&mt8195_pinctrl_driver); } arch_initcall(mt8195_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT8195 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8196.c b/drivers/pinctrl/mediatek/pinctrl-mt8196.c index dec957c1724b..2e36bf3c45eb 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8196.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8196.c @@ -1839,6 +1839,7 @@ static const struct of_device_id mt8196_pinctrl_of_match[] = { { .compatible = "mediatek,mt8196-pinctrl", .data = &mt8196_data }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, mt8196_pinctrl_of_match); static struct platform_driver mt8196_pinctrl_driver = { .driver = { @@ -1856,3 +1857,4 @@ static int __init mt8196_pinctrl_init(void) arch_initcall(mt8196_pinctrl_init); MODULE_DESCRIPTION("MediaTek MT8196 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8365.c b/drivers/pinctrl/mediatek/pinctrl-mt8365.c index 73849ae569c9..564227f7ca2d 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c @@ -477,6 +477,7 @@ static const struct of_device_id mt8365_pctrl_match[] = { { .compatible = "mediatek,mt8365-pinctrl", .data = &mt8365_pinctrl_data }, {} }; +MODULE_DEVICE_TABLE(of, mt8365_pctrl_match); static struct platform_driver mtk_pinctrl_driver = { .probe = mtk_pctrl_common_probe, @@ -494,5 +495,6 @@ static int __init mtk_pinctrl_init(void) arch_initcall(mtk_pinctrl_init); MODULE_DESCRIPTION("MediaTek MT8365 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); MODULE_AUTHOR("Zhiyong Tao "); MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8516.c b/drivers/pinctrl/mediatek/pinctrl-mt8516.c index 62084d0cc4c9..d4f0a0bc5438 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8516.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c @@ -344,4 +344,6 @@ static int __init mtk_pinctrl_init(void) } arch_initcall(mtk_pinctrl_init); +MODULE_DESCRIPTION("MediaTek MT8516 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-rt2880.c b/drivers/pinctrl/mediatek/pinctrl-rt2880.c index a9c4acdc6766..e7099325c5ef 100644 --- a/drivers/pinctrl/mediatek/pinctrl-rt2880.c +++ b/drivers/pinctrl/mediatek/pinctrl-rt2880.c @@ -60,4 +60,6 @@ static int __init rt2880_pinctrl_init(void) } core_initcall_sync(rt2880_pinctrl_init); +MODULE_DESCRIPTION("MediaTek RT2880 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-rt305x.c b/drivers/pinctrl/mediatek/pinctrl-rt305x.c index 93788ec49ed0..fa6407e86f79 100644 --- a/drivers/pinctrl/mediatek/pinctrl-rt305x.c +++ b/drivers/pinctrl/mediatek/pinctrl-rt305x.c @@ -139,4 +139,6 @@ static int __init rt305x_pinctrl_init(void) } core_initcall_sync(rt305x_pinctrl_init); +MODULE_DESCRIPTION("MediaTek RT305X Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-rt3883.c b/drivers/pinctrl/mediatek/pinctrl-rt3883.c index afe705a0ddf6..838bf811cd0c 100644 --- a/drivers/pinctrl/mediatek/pinctrl-rt3883.c +++ b/drivers/pinctrl/mediatek/pinctrl-rt3883.c @@ -107,4 +107,6 @@ static int __init rt3883_pinctrl_init(void) } core_initcall_sync(rt3883_pinctrl_init); +MODULE_DESCRIPTION("MediaTek RT3883 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); MODULE_IMPORT_NS("MTK_PINCTRL"); From ee59788040d6f50123f6b83421131f5c8899c456 Mon Sep 17 00:00:00 2001 From: Sang-Heon Jeon Date: Fri, 24 Jul 2026 03:45:26 +0900 Subject: [PATCH 067/130] pinctrl: mediatek: remove conditional return with no effect Both branches of the check return the same value, so the check has no effect. Remove it and return the value directly. This is the result of running the Coccinelle script from scripts/coccinelle/misc/cond_return_no_effect.cocci. Signed-off-by: Sang-Heon Jeon Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c index 802f780120bf..faa6dbf0f635 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c @@ -1243,11 +1243,7 @@ int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw, if (err) return err; - err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, e1); - if (err) - return err; - - return err; + return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, e1); } EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_set); From 1860fb0be224dec0e4d170f46d1cbbc77e25e09e Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Fri, 24 Apr 2026 12:01:24 +0530 Subject: [PATCH 068/130] pinctrl: qcom: Add irq_get/set_irqchip_state() for msm gpio irqchip MPM irqchip monitors the interrupts during SoC sleep state and after wakeup replays the edge interrupt by making it pending at respective irqchip by invoking irq_set_irqchip_state() API. The msm gpio irqchip however do not implement this function making it impossible to replay the gpio interrupt on any MPM irqchip based SoC. Add the missing irq_get/set_irqchip_state() APIs. Implement only IRQCHIP_STATE_PENDING case which MPM irqchip uses. Signed-off-by: Maulik Shah Signed-off-by: Sneh Mankad Acked-by: Linus Walleij Reviewed-by: Navya Malempati Link: https://patch.msgid.link/20260424-pinctrl_irqchip_states-v1-1-85286f078916@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski --- drivers/pinctrl/qcom/pinctrl-msm.c | 39 ++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 838969186185..3cb48ba31b78 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -1313,6 +1313,43 @@ static int msm_gpio_irq_set_affinity(struct irq_data *d, return -EINVAL; } +static int msm_gpio_irq_set_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, bool val) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; + + if (which != IRQCHIP_STATE_PENDING) + return -EINVAL; + + if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) + return -EINVAL; + + msm_writel_intr_status(val, pctrl, g); + + return 0; +} + +static int msm_gpio_irq_get_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, bool *val) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; + + if (which != IRQCHIP_STATE_PENDING) + return -EINVAL; + + if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) + return -EINVAL; + + g = &pctrl->soc->groups[d->hwirq]; + *val = msm_readl_intr_status(pctrl, g); + + return 0; +} + static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); @@ -1401,6 +1438,8 @@ static const struct irq_chip msm_gpio_irq_chip = { .irq_request_resources = msm_gpio_irq_reqres, .irq_release_resources = msm_gpio_irq_relres, .irq_set_affinity = msm_gpio_irq_set_affinity, + .irq_set_irqchip_state = msm_gpio_irq_set_irqchip_state, + .irq_get_irqchip_state = msm_gpio_irq_get_irqchip_state, .irq_set_vcpu_affinity = msm_gpio_irq_set_vcpu_affinity, .flags = (IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SET_TYPE_MASKED | From 1e7b04c12c077e8829991833a9aa2cb3bdacab61 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Tue, 28 Jul 2026 16:33:08 +0530 Subject: [PATCH 069/130] pinctrl: qcom: shikra: Fix intr_target_width for summary interrupt routing The intr_target_width field sets the mask width used when writing target processor into interrupt config register and deciding which processor receives summary interrupt for a given GPIO. Without it, pinctrl driver defaults to a 3-bit mask. On Shikra, this field is 4 bits wide, which could corrupt adjacent bits and mis-route interrupts. Set intr_target_width = 4 to match the hardware. Fixes: 9db68ec534c5 ("pinctrl: qcom: Add Shikra pinctrl driver") Signed-off-by: Komal Bajaj Reviewed-by: Konrad Dybcio Link: https://patch.msgid.link/20260728-shikra-pinctrl-intr-width-v1-1-46583734d808@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski --- drivers/pinctrl/qcom/pinctrl-shikra.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/qcom/pinctrl-shikra.c b/drivers/pinctrl/qcom/pinctrl-shikra.c index 0fc98369948c..55aec2f675e6 100644 --- a/drivers/pinctrl/qcom/pinctrl-shikra.c +++ b/drivers/pinctrl/qcom/pinctrl-shikra.c @@ -44,6 +44,7 @@ .intr_status_bit = 0, \ .intr_wakeup_enable_bit = 7, \ .intr_wakeup_present_bit = 6, \ + .intr_target_width = 4, \ .intr_target_bit = 8, \ .intr_target_kpss_val = 3, \ .intr_raw_status_bit = 4, \ From 04b3818c3bbc3f68b6e856f87dca752af2cc34ee Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 1 Aug 2026 00:06:02 +0200 Subject: [PATCH 070/130] Revert "pinctrl: s32cc: implement GPIO functionality" This reverts commit 94cb9e8f270797e489633cfa53d2d44afecb8bef. This collides with orthogonal changes in the GPIO tree, we need to rebase it and apply it to the GPIO tree instead. Signed-off-by: Linus Walleij --- drivers/pinctrl/nxp/Kconfig | 2 - drivers/pinctrl/nxp/pinctrl-s32.h | 35 +- drivers/pinctrl/nxp/pinctrl-s32cc.c | 721 +++------------------------- drivers/pinctrl/nxp/pinctrl-s32g2.c | 47 +- 4 files changed, 78 insertions(+), 727 deletions(-) diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig index fab725f250ab..abca7ef97003 100644 --- a/drivers/pinctrl/nxp/Kconfig +++ b/drivers/pinctrl/nxp/Kconfig @@ -5,8 +5,6 @@ config PINCTRL_S32CC select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS select GENERIC_PINCONF - select GPIOLIB - select GPIO_REGMAP select REGMAP_MMIO config PINCTRL_S32G2 diff --git a/drivers/pinctrl/nxp/pinctrl-s32.h b/drivers/pinctrl/nxp/pinctrl-s32.h index 028578a090e4..8715befd5f05 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32.h +++ b/drivers/pinctrl/nxp/pinctrl-s32.h @@ -2,7 +2,7 @@ * * S32 pinmux core definitions * - * Copyright 2016-2020, 2022, 2026 NXP + * Copyright 2016-2020, 2022 NXP * Copyright (C) 2022 SUSE LLC * Copyright 2015-2016 Freescale Semiconductor, Inc. * Copyright (C) 2012 Linaro Ltd. @@ -34,42 +34,11 @@ struct s32_pin_range { unsigned int end; }; -/** - * struct s32_gpio_range - contiguous GPIO pin range within a SIUL2 module - * @gpio_base: first GPIO line offset in the GPIO range - * @pin_base: first pinctrl pin number mapped by this GPIO range - * @gpio_num: number of consecutive GPIO pins in the range - * @sparse: true if the PGPD layout is non-linear (resolved via pad map only); - * pins not found in the pad map are invalid for this range - */ -struct s32_gpio_range { - unsigned int gpio_base; - unsigned int pin_base; - unsigned int gpio_num; - bool sparse; -}; - -/** - * struct s32_gpio_pad_map - mapping between GPIO ranges and PGPD pads - * @gpio_start: first GPIO line offset in the range - * @gpio_end: last GPIO line offset in the range - * @pad: PGPD pad number serving the range - */ -struct s32_gpio_pad_map { - unsigned int gpio_start; - unsigned int gpio_end; - unsigned int pad; -}; - struct s32_pinctrl_soc_data { const struct pinctrl_pin_desc *pins; unsigned int npins; const struct s32_pin_range *mem_pin_ranges; unsigned int mem_regions; - const struct s32_gpio_range *gpio_ranges; - unsigned int num_gpio_ranges; - const struct s32_gpio_pad_map *gpio_pad_maps; - unsigned int num_gpio_pad_maps; }; struct s32_pinctrl_soc_info { @@ -84,8 +53,6 @@ struct s32_pinctrl_soc_info { #define S32_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) #define S32_PIN_RANGE(_start, _end) { .start = _start, .end = _end } -#define S32_GPIO_RANGE(gpio, pin, num) \ - { .gpio_base = gpio, .pin_base = pin, .gpio_num = num } int s32_pinctrl_probe(struct platform_device *pdev, const struct s32_pinctrl_soc_data *soc_data); diff --git a/drivers/pinctrl/nxp/pinctrl-s32cc.c b/drivers/pinctrl/nxp/pinctrl-s32cc.c index 0025add68495..4b40770a38b7 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32cc.c +++ b/drivers/pinctrl/nxp/pinctrl-s32cc.c @@ -2,7 +2,7 @@ /* * Core driver for the S32 CC (Common Chassis) pin controller * - * Copyright 2017-2022,2024-2026 NXP + * Copyright 2017-2022,2024-2025 NXP * Copyright (C) 2022 SUSE LLC * Copyright 2015-2016 Freescale Semiconductor, Inc. */ @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -40,40 +39,6 @@ #define S32_MSCR_ODE BIT(20) #define S32_MSCR_OBE BIT(21) -#define S32_GPIO_OP_SHIFT 16 -#define S32_GPIO_OP_MASK GENMASK(19, 16) - -#define S32_GPIO_OP_DIR 0 /* MSCR direction */ -#define S32_GPIO_OP_DAT BIT(S32_GPIO_OP_SHIFT) /* PGPDI read */ -#define S32_GPIO_OP_SET BIT(S32_GPIO_OP_SHIFT + 1) /* PGPDO write */ - -/* - * [15:12] = GPIO bank / gpio range index - * [11:0] = real register offset or pin id - */ -#define S32_GPIO_BANK_SHIFT 12 -#define S32_GPIO_BANK_MASK GENMASK(15, 12) -#define S32_GPIO_REG_MASK GENMASK(11, 0) - -#define S32_GPIO_ENCODE(bank, off) \ - ((((bank) << S32_GPIO_BANK_SHIFT) & S32_GPIO_BANK_MASK) | \ - ((off) & S32_GPIO_REG_MASK)) - -#define S32_GPIO_DECODE_BANK(reg) \ - (((reg) & S32_GPIO_BANK_MASK) >> S32_GPIO_BANK_SHIFT) - -#define S32_GPIO_DECODE_OFF(reg) \ - ((reg) & S32_GPIO_REG_MASK) - -/* - * PGPDOs are 16bit registers that come in big endian - * order if they are grouped in pairs of two. - * - * For example, the order is PGPDO1, PGPDO0, PGPDO3, PGPDO2... - */ -#define S32_PGPD(N) (((N) ^ 1) * 2) -#define S32_PGPD_SIZE 16 - enum s32_write_type { S32_PINCONF_UPDATE_ONLY, S32_PINCONF_OVERWRITE, @@ -107,18 +72,6 @@ struct s32_pinctrl_mem_region { char name[8]; }; -/* - * struct s32_gpio_regmaps - GPIO register maps for a SIUL2 instance - * @pgpdo: regmap for Parallel GPIO Pad Data Out registers - * @pgpdi: regmap for Parallel GPIO Pad Data In registers - * @range: GPIO range info - */ -struct s32_gpio_regmaps { - struct regmap *pgpdo; - struct regmap *pgpdi; - const struct s32_gpio_range *range; -}; - /* * struct gpio_pin_config - holds pin configuration for GPIO's * @pin_id: Pin ID for this GPIO @@ -145,12 +98,6 @@ struct s32_pinctrl_context { * @pctl: a pointer to the pinctrl device structure * @regions: reserved memory regions with start/end pin * @info: structure containing information about the pin - * @gpio_regmaps: PGPDO/PGPDI regmaps for each SIUL2 module - * @num_gpio_regmaps: number of GPIO regmap entries - * @gpio_regmap: regmap bridging gpio-regmap to SIUL2 registers - * @gpio_rgm: gpio-regmap instance registered for this controller - * @ngpio: total number of GPIO line offsets - * @gpio_names: GPIO line names array passed to gpio-regmap * @gpio_configs: saved configurations for GPIO pins * @gpio_configs_lock: lock for the `gpio_configs` list * @saved_context: configuration saved over system sleep @@ -160,12 +107,6 @@ struct s32_pinctrl { struct pinctrl_dev *pctl; struct s32_pinctrl_mem_region *regions; struct s32_pinctrl_soc_info *info; - struct s32_gpio_regmaps *gpio_regmaps; - unsigned int num_gpio_regmaps; - struct regmap *gpio_regmap; - struct gpio_regmap *gpio_rgm; - unsigned int ngpio; - const char *const *gpio_names; struct list_head gpio_configs; spinlock_t gpio_configs_lock; #ifdef CONFIG_PM_SLEEP @@ -415,63 +356,6 @@ static int s32_pmx_get_funcs_count(struct pinctrl_dev *pctldev) return info->nfunctions; } -static int s32_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int pin) -{ - struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - struct gpio_pin_config *gpio_pin __free(kfree) = NULL; - unsigned int config; - int ret; - - ret = s32_regmap_read(pctldev, pin, &config); - if (ret) - return ret; - - gpio_pin = kmalloc_obj(*gpio_pin, GFP_KERNEL); - if (!gpio_pin) - return -ENOMEM; - - gpio_pin->pin_id = pin; - gpio_pin->config = config; - - /* GPIO pin means SSS = 0 */ - ret = s32_regmap_update(pctldev, pin, - S32_MSCR_SSS_MASK | S32_MSCR_IBE, - S32_MSCR_IBE); - if (ret) - return ret; - - scoped_guard(spinlock_irqsave, &ipctl->gpio_configs_lock) - list_add(&no_free_ptr(gpio_pin)->list, &ipctl->gpio_configs); - - return 0; -} - -static void s32_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int pin) -{ - struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - struct gpio_pin_config *gpio_pin, *found = NULL; - unsigned long flags; - - spin_lock_irqsave(&ipctl->gpio_configs_lock, flags); - list_for_each_entry(gpio_pin, &ipctl->gpio_configs, list) { - if (gpio_pin->pin_id == pin) { - list_del(&gpio_pin->list); - found = gpio_pin; - break; - } - } - spin_unlock_irqrestore(&ipctl->gpio_configs_lock, flags); - - if (found) { - s32_regmap_write(pctldev, found->pin_id, found->config); - kfree(found); - } -} - static const char *s32_pmx_get_func_name(struct pinctrl_dev *pctldev, unsigned int selector) { @@ -495,6 +379,67 @@ static int s32_pmx_get_groups(struct pinctrl_dev *pctldev, return 0; } +static int s32_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + struct gpio_pin_config *gpio_pin; + unsigned int config; + unsigned long flags; + int ret; + + ret = s32_regmap_read(pctldev, offset, &config); + if (ret) + return ret; + + /* Save current configuration */ + gpio_pin = kmalloc_obj(*gpio_pin); + if (!gpio_pin) + return -ENOMEM; + + gpio_pin->pin_id = offset; + gpio_pin->config = config; + INIT_LIST_HEAD(&gpio_pin->list); + + spin_lock_irqsave(&ipctl->gpio_configs_lock, flags); + list_add(&gpio_pin->list, &ipctl->gpio_configs); + spin_unlock_irqrestore(&ipctl->gpio_configs_lock, flags); + + /* GPIO pin means SSS = 0 */ + config &= ~S32_MSCR_SSS_MASK; + + return s32_regmap_write(pctldev, offset, config); +} + +static void s32_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + struct gpio_pin_config *gpio_pin, *tmp; + unsigned long flags; + int ret; + + spin_lock_irqsave(&ipctl->gpio_configs_lock, flags); + + list_for_each_entry_safe(gpio_pin, tmp, &ipctl->gpio_configs, list) { + if (gpio_pin->pin_id == offset) { + ret = s32_regmap_write(pctldev, gpio_pin->pin_id, + gpio_pin->config); + if (ret != 0) + goto unlock; + + list_del(&gpio_pin->list); + kfree(gpio_pin); + break; + } + } + +unlock: + spin_unlock_irqrestore(&ipctl->gpio_configs_lock, flags); +} + static int s32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int offset, @@ -704,9 +649,9 @@ static void s32_pinconf_dbg_show(struct pinctrl_dev *pctldev, ret = s32_regmap_read(pctldev, pin_id, &config); if (ret) - seq_printf(s, "error %d", ret); - else - seq_printf(s, "0x%x", config); + return; + + seq_printf(s, "0x%x", config); } static void s32_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, @@ -724,11 +669,8 @@ static void s32_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, for (i = 0; i < grp->data.npins; i++) { name = pin_get_name(pctldev, grp->data.pins[i]); ret = s32_regmap_read(pctldev, grp->data.pins[i], &config); - if (ret) { - seq_printf(s, "%s: error %d\n", name, ret); - continue; - } - + if (ret) + return; seq_printf(s, "%s: 0x%x\n", name, config); } } @@ -741,477 +683,6 @@ static const struct pinconf_ops s32_pinconf_ops = { .pin_config_group_dbg_show = s32_pinconf_group_dbg_show, }; -static void s32_gpio_free_saved_configs(void *data) -{ - struct s32_pinctrl *ipctl = data; - struct gpio_pin_config *gpio_pin, *tmp; - unsigned long flags; - - spin_lock_irqsave(&ipctl->gpio_configs_lock, flags); - list_for_each_entry_safe(gpio_pin, tmp, &ipctl->gpio_configs, list) { - list_del(&gpio_pin->list); - kfree(gpio_pin); - } - spin_unlock_irqrestore(&ipctl->gpio_configs_lock, flags); -} - -static unsigned int s32_pin2pad(unsigned int pin) -{ - return pin / S32_PGPD_SIZE; -} - -static u16 s32_pin2mask(unsigned int pin) -{ - /* - * From Reference manual : - * PGPDOx[PPDOy] = GPDO(x × 16) + (15 - y)[PDO_(x × 16) + (15 - y)] - */ - return BIT(S32_PGPD_SIZE - 1 - pin % S32_PGPD_SIZE); -} - -static int s32_gpio_get_range(struct s32_pinctrl *ipctl, - unsigned int gpio, - unsigned int *pin, - unsigned int *bank) -{ - const struct s32_pinctrl_soc_data *soc_data = ipctl->info->soc_data; - const struct s32_gpio_range *range; - int i; - - for (i = 0; i < soc_data->num_gpio_ranges; i++) { - range = &soc_data->gpio_ranges[i]; - - if (gpio < range->gpio_base || - gpio >= range->gpio_base + range->gpio_num) - continue; - - if (pin) - *pin = range->pin_base + gpio - range->gpio_base; - - if (bank) - *bank = i; - - return 0; - } - - return -EINVAL; -} - -static int s32_gpio_pad_map_xlate(struct s32_pinctrl *ipctl, - unsigned int gpio, - unsigned int *reg_offset, - u16 *mask) -{ - const struct s32_pinctrl_soc_data *soc_data = ipctl->info->soc_data; - const struct s32_gpio_pad_map *map; - unsigned int bit; - int i; - - if (!soc_data->gpio_pad_maps || !soc_data->num_gpio_pad_maps) - return -EINVAL; - - for (i = 0; i < soc_data->num_gpio_pad_maps; i++) { - map = &soc_data->gpio_pad_maps[i]; - - if (gpio < map->gpio_start || gpio > map->gpio_end) - continue; - - bit = gpio - map->gpio_start; - *mask = BIT(S32_PGPD_SIZE - 1 - bit); - *reg_offset = S32_PGPD(map->pad); - - return 0; - } - - return -EINVAL; -} - -static bool s32_gpio_pin_is_sparse(struct s32_pinctrl *ipctl, unsigned int pin) -{ - const struct s32_pinctrl_soc_data *soc_data = ipctl->info->soc_data; - const struct s32_gpio_range *range; - int i; - - for (i = 0; i < soc_data->num_gpio_ranges; i++) { - range = &soc_data->gpio_ranges[i]; - if (pin >= range->pin_base && - pin < range->pin_base + range->gpio_num) - return range->sparse; - } - - return false; -} - -static int s32_gpio_xlate_pgpd(struct s32_pinctrl *ipctl, - unsigned int pin, - unsigned int *reg_offset, - u16 *mask) -{ - int ret; - - /* - * Try the pad map first. For sparse ranges (SIUL2_1), only pins - * listed in the pad map are valid, return the error directly without - * falling back to the linear layout. - * For linear ranges (SIUL2_0), fall back to the linear pad-to-PGPD - * formula if no pad map entry matches. - */ - ret = s32_gpio_pad_map_xlate(ipctl, pin, reg_offset, mask); - if (ret != -EINVAL) - return ret; - - if (s32_gpio_pin_is_sparse(ipctl, pin)) - return -EINVAL; - - /* Linear layout fallback for non-sparse ranges. */ - *mask = s32_pin2mask(pin); - *reg_offset = S32_PGPD(s32_pin2pad(pin)); - - return 0; -} - -static int s32_gpio_reg_mask_xlate(struct gpio_regmap *gpio, - unsigned int base, unsigned int offset, - unsigned int *reg, unsigned int *mask) -{ - struct s32_pinctrl *ipctl = gpio_regmap_get_drvdata(gpio); - unsigned int pgpd_reg, pin, bank; - u16 pgpd_mask; - int ret; - - ret = s32_gpio_get_range(ipctl, offset, &pin, &bank); - if (ret) - return ret; - - switch (base) { - case S32_GPIO_OP_DIR: - /* - * Direction is controlled through MSCR OBE. - * Encode the real pin id in the virtual register. - */ - *reg = S32_GPIO_OP_DIR | pin; - *mask = S32_MSCR_OBE; - return 0; - - case S32_GPIO_OP_DAT: - case S32_GPIO_OP_SET: - ret = s32_gpio_xlate_pgpd(ipctl, pin, &pgpd_reg, &pgpd_mask); - if (ret) - return ret; - /* - * Encode both the GPIO bank and the real PGPD register offset. - */ - *reg = base | S32_GPIO_ENCODE(bank, pgpd_reg); - *mask = pgpd_mask; - return 0; - default: - return -EINVAL; - } -} - -static int s32_gpio_reg_read(void *context, unsigned int reg, - unsigned int *val) -{ - struct s32_pinctrl *ipctl = context; - unsigned int op = reg & S32_GPIO_OP_MASK; - unsigned int vreg = reg & ~S32_GPIO_OP_MASK; - unsigned int bank; - unsigned int offset; - struct regmap *map; - - switch (op) { - case S32_GPIO_OP_DIR: - /* - * Lower bits contain the real MSCR pin id. - */ - offset = S32_GPIO_DECODE_OFF(vreg); - - return s32_regmap_read(ipctl->pctl, offset, val); - - case S32_GPIO_OP_DAT: - bank = S32_GPIO_DECODE_BANK(vreg); - offset = S32_GPIO_DECODE_OFF(vreg); - - if (bank >= ipctl->num_gpio_regmaps) - return -EINVAL; - - map = ipctl->gpio_regmaps[bank].pgpdi; - if (!map) - return -ENODEV; - - return regmap_read(map, offset, val); - - case S32_GPIO_OP_SET: - /* - * gpio-regmap uses update_bits() for set, so it needs to read - * the output register before writing the updated value. - */ - bank = S32_GPIO_DECODE_BANK(vreg); - offset = S32_GPIO_DECODE_OFF(vreg); - - if (bank >= ipctl->num_gpio_regmaps) - return -EINVAL; - - map = ipctl->gpio_regmaps[bank].pgpdo; - if (!map) - return -ENODEV; - - return regmap_read(map, offset, val); - - default: - return -EINVAL; - } -} - -static int s32_gpio_reg_write(void *context, unsigned int reg, - unsigned int val) -{ - struct s32_pinctrl *ipctl = context; - unsigned int op = reg & S32_GPIO_OP_MASK; - unsigned int vreg = reg & ~S32_GPIO_OP_MASK; - unsigned int bank, offset, config; - struct regmap *map; - - switch (op) { - case S32_GPIO_OP_DIR: - /* - * gpio-regmap sets S32_MSCR_OBE for output and clears it for - * input. Keep IBE enabled for GPIOs in both cases. - */ - offset = S32_GPIO_DECODE_OFF(vreg); - - config = S32_MSCR_IBE; - if (val & S32_MSCR_OBE) - config |= S32_MSCR_OBE; - - return s32_regmap_update(ipctl->pctl, offset, - S32_MSCR_OBE | S32_MSCR_IBE, - config); - - case S32_GPIO_OP_SET: - bank = S32_GPIO_DECODE_BANK(vreg); - offset = S32_GPIO_DECODE_OFF(vreg); - - if (bank >= ipctl->num_gpio_regmaps) - return -EINVAL; - - map = ipctl->gpio_regmaps[bank].pgpdo; - if (!map) - return -ENODEV; - - return regmap_write(map, offset, val); - - default: - return -EINVAL; - } -} - -static const struct regmap_bus s32_gpio_regmap_bus = { - .reg_read = s32_gpio_reg_read, - .reg_write = s32_gpio_reg_write, -}; - -static const struct regmap_config s32_gpio_regmap_config = { - .name = "s32-gpio", - .reg_bits = 32, - .val_bits = 32, - .reg_stride = 1, - .max_register = S32_GPIO_OP_SET | S32_GPIO_BANK_MASK | S32_GPIO_REG_MASK, - .cache_type = REGCACHE_NONE, - .fast_io = true, -}; - -static int s32_gpio_get_ngpio(const struct s32_pinctrl_soc_data *soc_data, - unsigned int *ngpio) -{ - const struct s32_gpio_range *range; - unsigned int end, max = 0; - int i; - - if (!soc_data->gpio_ranges || !soc_data->num_gpio_ranges) - return -EINVAL; - - for (i = 0; i < soc_data->num_gpio_ranges; i++) { - range = &soc_data->gpio_ranges[i]; - - if (!range->gpio_num) - return -EINVAL; - - end = range->gpio_base + range->gpio_num; - - /* - * gpio_ranges must be ordered by gpio_base and must not overlap. - * The GPIO line space size is derived from the highest range end. - */ - if (i > 0 && range->gpio_base < max) - return -EINVAL; - - if (end > max) - max = end; - } - - *ngpio = max; - - return 0; -} - -static int s32_init_gpio_regmap(struct platform_device *pdev, - struct s32_pinctrl *ipctl) -{ - ipctl->gpio_regmap = - devm_regmap_init(&pdev->dev, &s32_gpio_regmap_bus, - ipctl, &s32_gpio_regmap_config); - if (IS_ERR(ipctl->gpio_regmap)) - return dev_err_probe(&pdev->dev, - PTR_ERR(ipctl->gpio_regmap), - "Failed to init GPIO regmap\n"); - - return 0; -} - -static int s32_init_valid_mask(struct gpio_chip *chip, unsigned long *mask, - unsigned int ngpios) -{ - struct gpio_regmap *gpio = gpiochip_get_data(chip); - struct s32_pinctrl *ipctl = gpio_regmap_get_drvdata(gpio); - unsigned int gpio_num, pin, reg_offset; - u16 pgpd_mask; - int ret; - - bitmap_zero(mask, ngpios); - - for (gpio_num = 0; gpio_num < ngpios; gpio_num++) { - ret = s32_gpio_get_range(ipctl, gpio_num, &pin, NULL); - if (ret) - continue; - - ret = s32_gpio_xlate_pgpd(ipctl, pin, ®_offset, &pgpd_mask); - if (ret) - continue; - - bitmap_set(mask, gpio_num, 1); - } - - return 0; -} - -static int s32_gpio_populate_names(struct s32_pinctrl *ipctl) -{ - char **names; - unsigned int gpio; - unsigned int pin; - char port; - int ret; - - names = devm_kcalloc(ipctl->dev, ipctl->ngpio, sizeof(*names), - GFP_KERNEL); - if (!names) - return -ENOMEM; - - for (gpio = 0; gpio < ipctl->ngpio; gpio++) { - ret = s32_gpio_get_range(ipctl, gpio, &pin, NULL); - if (ret) - continue; - - port = 'A' + pin / 16; - - names[gpio] = devm_kasprintf(ipctl->dev, GFP_KERNEL, - "P%c_%02u", port, pin & 0xf); - if (!names[gpio]) - return -ENOMEM; - } - - ipctl->gpio_names = (const char *const *)names; - - return 0; -} - -static int s32_pinctrl_init_gpio_regmaps(struct platform_device *pdev, - struct s32_pinctrl *ipctl) -{ - const struct s32_pinctrl_soc_data *soc_data = ipctl->info->soc_data; - static const struct regmap_config pgpd_config = { - .reg_bits = 32, - .val_bits = 16, - .reg_stride = 2, - }; - struct regmap_config cfg; - struct resource *res; - void __iomem *base; - unsigned int pgpdo_idx, pgpdi_idx; - unsigned int i; - - if (!soc_data->gpio_ranges || !soc_data->num_gpio_ranges) - return 0; - - ipctl->num_gpio_regmaps = soc_data->num_gpio_ranges; - ipctl->gpio_regmaps = devm_kcalloc(&pdev->dev, ipctl->num_gpio_regmaps, - sizeof(*ipctl->gpio_regmaps), - GFP_KERNEL); - if (!ipctl->gpio_regmaps) - return -ENOMEM; - - for (i = 0; i < ipctl->num_gpio_regmaps; i++) { - ipctl->gpio_regmaps[i].range = &soc_data->gpio_ranges[i]; - - /* - * GPIO resources are placed after the pinctrl regions - */ - pgpdo_idx = soc_data->mem_regions + i * 2; - pgpdi_idx = soc_data->mem_regions + i * 2 + 1; - - /* PGPDO */ - res = platform_get_resource(pdev, IORESOURCE_MEM, pgpdo_idx); - if (!res) - return dev_err_probe(&pdev->dev, -ENOENT, - "Missing PGPDO resource %u\n", i); - - base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(base)) - return PTR_ERR(base); - - cfg = pgpd_config; - cfg.name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "pgpdo%u", i); - if (!cfg.name) - return -ENOMEM; - - cfg.max_register = resource_size(res) - cfg.reg_stride; - - ipctl->gpio_regmaps[i].pgpdo = - devm_regmap_init_mmio(&pdev->dev, base, &cfg); - if (IS_ERR(ipctl->gpio_regmaps[i].pgpdo)) - return dev_err_probe(&pdev->dev, - PTR_ERR(ipctl->gpio_regmaps[i].pgpdo), - "Failed to init PGPDO regmap %u\n", i); - - /* PGPDI */ - res = platform_get_resource(pdev, IORESOURCE_MEM, pgpdi_idx); - if (!res) - return dev_err_probe(&pdev->dev, -ENOENT, - "Missing PGPDI resource %u\n", i); - - base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(base)) - return PTR_ERR(base); - - cfg = pgpd_config; - cfg.name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "pgpdi%u", i); - if (!cfg.name) - return -ENOMEM; - - cfg.max_register = resource_size(res) - cfg.reg_stride; - - ipctl->gpio_regmaps[i].pgpdi = - devm_regmap_init_mmio(&pdev->dev, base, &cfg); - if (IS_ERR(ipctl->gpio_regmaps[i].pgpdi)) - return dev_err_probe(&pdev->dev, - PTR_ERR(ipctl->gpio_regmaps[i].pgpdi), - "Failed to init PGPDI regmap %u\n", i); - } - - return 0; -} - #ifdef CONFIG_PM_SLEEP static bool s32_pinctrl_should_save(struct s32_pinctrl *ipctl, unsigned int pin) @@ -1238,7 +709,8 @@ int s32_pinctrl_suspend(struct device *dev) const struct pinctrl_pin_desc *pin; const struct s32_pinctrl_soc_info *info = ipctl->info; struct s32_pinctrl_context *saved_context = &ipctl->saved_context; - int i, ret; + int i; + int ret; unsigned int config; for (i = 0; i < info->soc_data->npins; i++) { @@ -1249,7 +721,7 @@ int s32_pinctrl_suspend(struct device *dev) ret = s32_regmap_read(ipctl->pctl, pin->number, &config); if (ret) - return ret; + return -EINVAL; saved_context->pads[i] = config; } @@ -1264,7 +736,7 @@ int s32_pinctrl_resume(struct device *dev) const struct s32_pinctrl_soc_info *info = ipctl->info; const struct pinctrl_pin_desc *pin; struct s32_pinctrl_context *saved_context = &ipctl->saved_context; - int i, ret; + int ret, i; for (i = 0; i < info->soc_data->npins; i++) { pin = &info->soc_data->pins[i]; @@ -1273,7 +745,7 @@ int s32_pinctrl_resume(struct device *dev) continue; ret = s32_regmap_write(ipctl->pctl, pin->number, - saved_context->pads[i]); + saved_context->pads[i]); if (ret) return ret; } @@ -1456,11 +928,9 @@ int s32_pinctrl_probe(struct platform_device *pdev, #ifdef CONFIG_PM_SLEEP struct s32_pinctrl_context *saved_context; #endif - struct gpio_regmap_config gpio_cfg = {}; struct pinctrl_desc *s32_pinctrl_desc; struct s32_pinctrl_soc_info *info; struct s32_pinctrl *ipctl; - unsigned int ngpio; int ret; if (!soc_data || !soc_data->pins || !soc_data->npins) @@ -1486,11 +956,6 @@ int s32_pinctrl_probe(struct platform_device *pdev, INIT_LIST_HEAD(&ipctl->gpio_configs); spin_lock_init(&ipctl->gpio_configs_lock); - ret = devm_add_action_or_reset(&pdev->dev, - s32_gpio_free_saved_configs, ipctl); - if (ret) - return ret; - s32_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*s32_pinctrl_desc), GFP_KERNEL); if (!s32_pinctrl_desc) @@ -1509,11 +974,6 @@ int s32_pinctrl_probe(struct platform_device *pdev, return dev_err_probe(&pdev->dev, ret, "Fail to probe dt properties\n"); - ret = s32_pinctrl_init_gpio_regmaps(pdev, ipctl); - if (ret) - return dev_err_probe(&pdev->dev, ret, - "Failed to init GPIO regmaps\n"); - ret = devm_pinctrl_register_and_init(&pdev->dev, s32_pinctrl_desc, ipctl, &ipctl->pctl); if (ret) @@ -1535,42 +995,7 @@ int s32_pinctrl_probe(struct platform_device *pdev, return dev_err_probe(&pdev->dev, ret, "Failed to enable pinctrl\n"); - /* Setup GPIO if GPIO ranges are defined */ - if (!soc_data->gpio_ranges || !soc_data->num_gpio_ranges) - return 0; - - ret = s32_gpio_get_ngpio(soc_data, &ngpio); - if (ret) - return dev_err_probe(&pdev->dev, ret, "Invalid GPIO ranges\n"); - - ipctl->ngpio = ngpio; - - ret = s32_gpio_populate_names(ipctl); - if (ret) - return ret; - - ret = s32_init_gpio_regmap(pdev, ipctl); - if (ret) - return ret; - - gpio_cfg.parent = &pdev->dev; - gpio_cfg.fwnode = dev_fwnode(&pdev->dev); - gpio_cfg.label = dev_name(&pdev->dev); - gpio_cfg.regmap = ipctl->gpio_regmap; - gpio_cfg.ngpio = ngpio; - gpio_cfg.names = ipctl->gpio_names; - gpio_cfg.reg_dir_out_base = GPIO_REGMAP_ADDR(S32_GPIO_OP_DIR); - gpio_cfg.reg_dat_base = GPIO_REGMAP_ADDR(S32_GPIO_OP_DAT); - gpio_cfg.reg_set_base = GPIO_REGMAP_ADDR(S32_GPIO_OP_SET); - gpio_cfg.reg_mask_xlate = s32_gpio_reg_mask_xlate; - gpio_cfg.init_valid_mask = s32_init_valid_mask; - gpio_cfg.drvdata = ipctl; - - ipctl->gpio_rgm = devm_gpio_regmap_register(&pdev->dev, &gpio_cfg); - if (IS_ERR(ipctl->gpio_rgm)) - return dev_err_probe(&pdev->dev, - PTR_ERR(ipctl->gpio_rgm), - "Unable to add gpio_regmap chip\n"); + dev_info(&pdev->dev, "Initialized S32 pinctrl driver\n"); return 0; } diff --git a/drivers/pinctrl/nxp/pinctrl-s32g2.c b/drivers/pinctrl/nxp/pinctrl-s32g2.c index f9546c67a269..c49d28793b69 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32g2.c +++ b/drivers/pinctrl/nxp/pinctrl-s32g2.c @@ -3,7 +3,7 @@ * NXP S32G pinctrl driver * * Copyright 2015-2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018, 2020-2022, 2025-2026 NXP + * Copyright 2017-2018, 2020-2022 NXP * Copyright (C) 2022 SUSE LLC */ @@ -773,48 +773,17 @@ static const struct s32_pin_range s32_pin_ranges_siul2[] = { S32_PIN_RANGE(942, 1007), }; -static const struct s32_gpio_range s32_gpio_ranges_siul2[] = { - S32_GPIO_RANGE(0, 0, 102), - /* SIUL2_1: sparse layout, PGPD mapping required for all pins */ - { .gpio_base = 112, .pin_base = 112, .gpio_num = 79, .sparse = true }, -}; - -/* - * SIUL2_1 GPIO ranges mapped to sparse PGPD pads. - * - * SIUL2_1 does not expose GPIO data registers as a linear pad - * sequence. Each entry describes a contiguous GPIO offset range - * and the PGPD pad servicing that range. - */ -static const struct s32_gpio_pad_map s32g_gpio_pad_maps[] = { - { 112, 122, 7 }, /* PH_00 .. PH_10 -> PGPD7 */ - { 144, 159, 9 }, /* PJ_00 .. PJ_15 -> PGPD9 */ - { 160, 175, 10 }, /* PK_00 .. PK_15 -> PGPD10 */ - { 176, 190, 11 }, /* PL_00 .. PL_14 -> PGPD11 */ -}; - -/* Legacy data for old DT bindings without GPIO support */ -static const struct s32_pinctrl_soc_data legacy_s32g_pinctrl_data = { +static const struct s32_pinctrl_soc_data s32_pinctrl_data = { .pins = s32_pinctrl_pads_siul2, .npins = ARRAY_SIZE(s32_pinctrl_pads_siul2), .mem_pin_ranges = s32_pin_ranges_siul2, .mem_regions = ARRAY_SIZE(s32_pin_ranges_siul2), }; -static const struct s32_pinctrl_soc_data s32g_pinctrl_data = { - .pins = s32_pinctrl_pads_siul2, - .npins = ARRAY_SIZE(s32_pinctrl_pads_siul2), - .mem_pin_ranges = s32_pin_ranges_siul2, - .mem_regions = ARRAY_SIZE(s32_pin_ranges_siul2), - .gpio_ranges = s32_gpio_ranges_siul2, - .num_gpio_ranges = ARRAY_SIZE(s32_gpio_ranges_siul2), - .gpio_pad_maps = s32g_gpio_pad_maps, - .num_gpio_pad_maps = ARRAY_SIZE(s32g_gpio_pad_maps), -}; - static const struct of_device_id s32_pinctrl_of_match[] = { { .compatible = "nxp,s32g2-siul2-pinctrl", + .data = &s32_pinctrl_data, }, { /* sentinel */ } }; @@ -823,16 +792,8 @@ MODULE_DEVICE_TABLE(of, s32_pinctrl_of_match); static int s32g_pinctrl_probe(struct platform_device *pdev) { const struct s32_pinctrl_soc_data *soc_data; - struct device_node *np = pdev->dev.of_node; - /* - * Legacy DTs only describe the pinctrl resources. - * New DT changes extend the same node with GPIO resources. - */ - if (of_property_present(np, "gpio-controller")) - soc_data = &s32g_pinctrl_data; - else - soc_data = &legacy_s32g_pinctrl_data; + soc_data = of_device_get_match_data(&pdev->dev); return s32_pinctrl_probe(pdev, soc_data); } From f9af1329b98a478f4bba605ec6db429ef0e38d54 Mon Sep 17 00:00:00 2001 From: Yulin Lu Date: Tue, 28 Jul 2026 15:29:06 +0800 Subject: [PATCH 071/130] pinctrl: eswin: Fix Handling of PIN_CONFIG_PERSIST_STATE The EIC7700 pinctrl driver does not handle PIN_CONFIG_PERSIST_STATE specifically, and returns -EOPNOTSUPP from the default case. Since all pins on the EIC7700 SoC are persistent over suspend, the correct behaviour is to accept this parameter and return success. Add an explicit case for PIN_CONFIG_PERSIST_STATE that returns 0 to prevent errors when this parameter is set. Signed-off-by: Yulin Lu Fixes: 5b797bcc00ef ("pinctrl: eswin: Add EIC7700 pinctrl driver") Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-eic7700.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pinctrl/pinctrl-eic7700.c b/drivers/pinctrl/pinctrl-eic7700.c index ffcd0ec5c2dc..1e72931feca5 100644 --- a/drivers/pinctrl/pinctrl-eic7700.c +++ b/drivers/pinctrl/pinctrl-eic7700.c @@ -423,6 +423,9 @@ static int eic7700_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin, else value &= ~EIC7700_ST; break; + /* All pins are persistent over suspend */ + case PIN_CONFIG_PERSIST_STATE: + return 0; default: return -EOPNOTSUPP; } From 17007cd700601777d9ee203a13d97e64ece3a10f Mon Sep 17 00:00:00 2001 From: Surendra Singh Chouhan Date: Wed, 29 Jul 2026 13:24:37 +0530 Subject: [PATCH 072/130] pinctrl: generic: free maps on pinctrl_generic_to_map() failure pinctrl_generic_to_map() parses DT configuration and allocates pinctrl maps via pinctrl_utils_reserve_map(). If subsequent steps (such as pinctrl_utils_add_map_mux(), pinctrl_generic_add_group(), pinconf_generic_parse_dt_config(), or pinctrl_utils_add_map_configs()) return an error, *maps may contain partially allocated map entries. Returning the error directly without freeing *maps leaks the allocated mapping memory across all drivers that rely on pinctrl_generic_to_map(). Fix this by calling pinctrl_utils_free_map() and resetting *maps, *num_maps, and *num_reserved_maps in the error path of pinctrl_generic_to_map(). Fixes: aaaf31be0426 ("pinctrl: extract pinctrl_generic_to_map() from pinctrl_generic_pins_function_dt_node_to_map()") Signed-off-by: Surendra Singh Chouhan Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-generic.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/pinctrl-generic.c b/drivers/pinctrl/pinctrl-generic.c index 9759b0186bcc..fd6bdb74028a 100644 --- a/drivers/pinctrl/pinctrl-generic.c +++ b/drivers/pinctrl/pinctrl-generic.c @@ -42,33 +42,44 @@ int pinctrl_generic_to_map(struct pinctrl_dev *pctldev, struct device_node *pare ret = pinctrl_utils_add_map_mux(pctldev, maps, num_reserved_maps, num_maps, group_name, parent->name); if (ret < 0) - return ret; + goto err_free_map; ret = pinctrl_generic_add_group(pctldev, group_name, pins, npins, data); - if (ret < 0) - return dev_err_probe(dev, ret, "failed to add group %s: %d\n", + if (ret < 0) { + dev_err_probe(dev, ret, "failed to add group %s: %d\n", group_name, ret); + goto err_free_map; + } ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &num_configs); - if (ret) - return dev_err_probe(dev, ret, "failed to parse pin config of group %s\n", + if (ret) { + dev_err_probe(dev, ret, "failed to parse pin config of group %s\n", group_name); + goto err_free_map; + } if (num_configs == 0) return 0; ret = pinctrl_utils_reserve_map(pctldev, maps, num_reserved_maps, num_maps, reserve); if (ret) - return ret; + goto err_free_map; ret = pinctrl_utils_add_map_configs(pctldev, maps, num_reserved_maps, num_maps, group_name, configs, num_configs, PIN_MAP_TYPE_CONFIGS_GROUP); kfree(configs); if (ret) - return ret; + goto err_free_map; return 0; + +err_free_map: + pinctrl_utils_free_map(pctldev, *maps, *num_maps); + *maps = NULL; + *num_maps = 0; + *num_reserved_maps = 0; + return ret; }; EXPORT_SYMBOL_GPL(pinctrl_generic_to_map); From 41c59b22370d2e1785e0e80f8ad7bd9946a1ca82 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Wed, 29 Jul 2026 02:26:42 -0700 Subject: [PATCH 073/130] pinctrl: spacemit: validate pins in pinconf callbacks Pin 0 is a valid pin ID, but spacemit_pinconf_get() rejects it by testing the numeric ID rather than the result of the descriptor lookup. It also fails to reject nonzero IDs absent from the SoC pin table before computing their register addresses. Check the descriptor and use its pin ID for the register lookup. spacemit_pinconf_group_set() validates only the first group member when generating the configuration. If a later member is invalid, spacemit_pin_set_config() returns -EINVAL, but the callback ignores it and reports success after partially updating the group. Validate every group member before writing any registers so malformed groups fail without being partially applied. Fixes: a83c29e1d145 ("pinctrl: spacemit: add support for SpacemiT K1 SoC") Signed-off-by: Troy Mitchell Reviewed-by: Yixun Lan Signed-off-by: Linus Walleij --- drivers/pinctrl/spacemit/pinctrl-k1.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c index f0b5ebd9e223..c3a7538783b8 100644 --- a/drivers/pinctrl/spacemit/pinctrl-k1.c +++ b/drivers/pinctrl/spacemit/pinctrl-k1.c @@ -503,13 +503,14 @@ static int spacemit_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config) { struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); int param = pinconf_to_config_param(*config); u32 value, arg = 0; - if (!pin) + if (!spin) return -EINVAL; - value = readl(spacemit_pin_to_reg(pctrl, pin)); + value = readl(spacemit_pin_to_reg(pctrl, spin->pin)); switch (param) { case PIN_CONFIG_SLEW_RATE: @@ -689,6 +690,11 @@ static int spacemit_pinconf_group_set(struct pinctrl_dev *pctldev, if (ret) return ret; + for (i = 0; i < group->grp.npins; i++) { + if (!spacemit_get_pin(pctrl, group->grp.pins[i])) + return -EINVAL; + } + for (i = 0; i < group->grp.npins; i++) spacemit_pin_set_config(pctrl, group->grp.pins[i], value); From dbbb19b8e412fb815d9eadceb1c0ce40083a5504 Mon Sep 17 00:00:00 2001 From: Tsz Shan Chan Date: Fri, 31 Jul 2026 17:18:45 +1000 Subject: [PATCH 074/130] pinctrl: sx150x: allow build when I2C is a module PINCTRL_SX150X currently depends on I2C=y. This prevents the driver from being built when I2C is configured as module. Change the Kconfig dependency to just I2C so sx150x can be built as a module when I2C is also a module. Signed-off-by: Tsz Shan Chan Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index ddc60562b770..fdcd0ea34d6f 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -575,7 +575,7 @@ config PINCTRL_STMFX config PINCTRL_SX150X tristate "Semtech SX150x I2C GPIO expander pinctrl driver" - depends on I2C=y + depends on I2C select PINMUX select PINCONF select GENERIC_PINCONF From c04957d2fc45af6f637cb21b21a15e05aa8bddfc Mon Sep 17 00:00:00 2001 From: Tsz Shan Chan Date: Wed, 5 Aug 2026 15:55:15 +1000 Subject: [PATCH 075/130] pinctrl: sx150x: Return IRQ_NONE if no pending irq The driver currently reads the interrupt source register, writes the value back to clear it, and always returns IRQ_HANDLED. When the IRQ is shared, the handler should not claim interrupts that are not from this device. Check for zero interrupt source first. It no interrupt is pending, return IRQ_NONE and skip the register write. Signed-off-by: Tsz Shan Chan Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-sx150x.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c index 89fdfa96843f..3c1309e8a844 100644 --- a/drivers/pinctrl/pinctrl-sx150x.c +++ b/drivers/pinctrl/pinctrl-sx150x.c @@ -550,6 +550,9 @@ static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id) if (err < 0) return IRQ_NONE; + if (!val) + return IRQ_NONE; + err = regmap_write(pctl->regmap, pctl->data->reg_irq_src, val); if (err < 0) return IRQ_NONE; From d4f32b8b8a3bcc7c07603b097d16320015af8e3c Mon Sep 17 00:00:00 2001 From: Tsz Shan Chan Date: Wed, 5 Aug 2026 15:55:16 +1000 Subject: [PATCH 076/130] pinctrl: sx150x: get parent IRQ trigger type from firmware The driver currently hardcodes the parent interrupt trigger type to IRQF_TRIGGER_FALLING. Use the trigger type configured by firmware instead. If no trigger type is specified, fall back to IRQF_TRIGGER_FALLING to maintain current behaviour. Support IRQF_TRIGGER_FALLING and IRQF_TRIGGER_LOW, which match the sx150x open drain active low interrupt output. Reject unsupported trigger types. Signed-off-by: Tsz Shan Chan Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-sx150x.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c index 3c1309e8a844..5eb6cc476eb3 100644 --- a/drivers/pinctrl/pinctrl-sx150x.c +++ b/drivers/pinctrl/pinctrl-sx150x.c @@ -1126,6 +1126,7 @@ static int sx150x_probe(struct i2c_client *client) I2C_FUNC_SMBUS_WRITE_WORD_DATA; struct device *dev = &client->dev; struct sx150x_pinctrl *pctl; + u32 irq_type; int ret; if (!i2c_check_functionality(client->adapter, i2c_funcs)) @@ -1225,10 +1226,24 @@ static int sx150x_probe(struct i2c_client *client) girq->handler = handle_bad_irq; girq->threaded = true; + irq_type = irq_get_trigger_type(client->irq); + switch (irq_type) { + case IRQF_TRIGGER_FALLING: + case IRQF_TRIGGER_LOW: + break; + case IRQF_TRIGGER_NONE: + irq_type = IRQF_TRIGGER_FALLING; + break; + default: + return dev_err_probe(dev, -EINVAL, + "unsupported irq trigger type %x\n", + irq_type); + } + ret = devm_request_threaded_irq(dev, client->irq, NULL, sx150x_irq_thread_fn, IRQF_ONESHOT | IRQF_SHARED | - IRQF_TRIGGER_FALLING, + irq_type, client->name, pctl); if (ret < 0) return ret; From aef612f013de95bfe01b9b4c3a3231c4327cd3ab Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Sun, 2 Aug 2026 19:35:43 +0530 Subject: [PATCH 077/130] pinctrl: Use IRQ trigger mask helpers Use IRQ_TYPE_LEVEL_MASK and IRQ_TYPE_EDGE_BOTH instead of open-coded trigger type combinations in irqchip callbacks. No functional change intended. Assisted-by: Claude:claude-sonnet-5 Signed-off-by: Maulik Shah Acked-by: Viresh Kumar Signed-off-by: Linus Walleij --- drivers/pinctrl/actions/pinctrl-owl.c | 2 +- drivers/pinctrl/airoha/pinctrl-airoha.c | 2 +- drivers/pinctrl/bcm/pinctrl-nsp-gpio.c | 4 ++-- drivers/pinctrl/mediatek/mtk-eint.c | 2 +- drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c | 5 ++--- drivers/pinctrl/pinctrl-ocelot.c | 2 +- drivers/pinctrl/pinctrl-sx150x.c | 2 +- drivers/pinctrl/qcom/pinctrl-msm.c | 4 ++-- drivers/pinctrl/spear/pinctrl-plgpio.c | 2 +- 9 files changed, 12 insertions(+), 13 deletions(-) diff --git a/drivers/pinctrl/actions/pinctrl-owl.c b/drivers/pinctrl/actions/pinctrl-owl.c index 1f0ef4727ba7..9f5637756bd3 100644 --- a/drivers/pinctrl/actions/pinctrl-owl.c +++ b/drivers/pinctrl/actions/pinctrl-owl.c @@ -824,7 +824,7 @@ static int owl_gpio_irq_set_type(struct irq_data *data, unsigned int type) struct gpio_chip *gc = irq_data_get_irq_chip_data(data); struct owl_pinctrl *pctrl = gpiochip_get_data(gc); - if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) + if (type & IRQ_TYPE_LEVEL_MASK) irq_set_handler_locked(data, handle_level_irq); else irq_set_handler_locked(data, handle_edge_irq); diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c index abfb018f207e..90372827639d 100644 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c @@ -2435,7 +2435,7 @@ static int airoha_irq_type(struct irq_data *data, unsigned int type) if (gpiochip->irq_type[data->hwirq]) return 0; - type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; + type = IRQ_TYPE_EDGE_BOTH; } gpiochip->irq_type[data->hwirq] = type & IRQ_TYPE_SENSE_MASK; diff --git a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c index 1fbb101386a3..83fcc80d5967 100644 --- a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c @@ -159,7 +159,7 @@ static void nsp_gpio_irq_ack(struct irq_data *d) u32 trigger_type; trigger_type = irq_get_trigger_type(d->irq); - if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) + if (trigger_type & IRQ_TYPE_EDGE_BOTH) writel(val, chip->base + NSP_GPIO_EVENT); } @@ -177,7 +177,7 @@ static void nsp_gpio_irq_set_mask(struct irq_data *d, bool unmask) u32 trigger_type; trigger_type = irq_get_trigger_type(d->irq); - if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) + if (trigger_type & IRQ_TYPE_EDGE_BOTH) nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_MASK, gpio, unmask); else nsp_set_bit(chip, REG, NSP_GPIO_INT_MASK, gpio, unmask); diff --git a/drivers/pinctrl/mediatek/mtk-eint.c b/drivers/pinctrl/mediatek/mtk-eint.c index 8b022545a3e9..827231dc0d24 100644 --- a/drivers/pinctrl/mediatek/mtk-eint.c +++ b/drivers/pinctrl/mediatek/mtk-eint.c @@ -216,7 +216,7 @@ static int mtk_eint_set_type(struct irq_data *d, unsigned int type) writel(mask, reg); } - if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { + if (type & IRQ_TYPE_EDGE_BOTH) { reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_clr); writel(mask, reg); } else { diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c index 13ed87d5d30c..f42d45373aad 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c @@ -260,11 +260,10 @@ static int npcmgpio_set_irq_type(struct irq_data *d, unsigned int type) return -EINVAL; } - if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { + if (type & IRQ_TYPE_LEVEL_MASK) { npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_EVTYP, gpio); irq_set_handler_locked(d, handle_level_irq); - } else if (type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_EDGE_RISING - | IRQ_TYPE_EDGE_FALLING)) { + } else if (type & IRQ_TYPE_EDGE_BOTH) { npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_EVTYP, gpio); irq_set_handler_locked(d, handle_edge_irq); } diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index 0fe0527863b8..58d3cde9f964 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -2317,7 +2317,7 @@ static const struct irq_chip ocelot_irqchip = { static int ocelot_irq_set_type(struct irq_data *data, unsigned int type) { - if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) + if (type & IRQ_TYPE_LEVEL_MASK) irq_set_chip_handler_name_locked(data, &ocelot_level_irqchip, handle_level_irq, NULL); if (type & IRQ_TYPE_EDGE_BOTH) diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c index 5eb6cc476eb3..04a0e6269e5b 100644 --- a/drivers/pinctrl/pinctrl-sx150x.c +++ b/drivers/pinctrl/pinctrl-sx150x.c @@ -525,7 +525,7 @@ static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type) struct sx150x_pinctrl *pctl = gpiochip_get_data(gc); unsigned int n, val = 0; - if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) + if (flow_type & IRQ_TYPE_LEVEL_MASK) return -EINVAL; n = irqd_to_hwirq(d); diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 11db6564c44d..d747ef618941 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -1181,9 +1181,9 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) raw_spin_unlock_irqrestore(&pctrl->lock, flags); - if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) + if (type & IRQ_TYPE_LEVEL_MASK) irq_set_handler_locked(d, handle_level_irq); - else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) + else if (type & IRQ_TYPE_EDGE_BOTH) irq_set_handler_locked(d, handle_edge_irq); return 0; diff --git a/drivers/pinctrl/spear/pinctrl-plgpio.c b/drivers/pinctrl/spear/pinctrl-plgpio.c index 1ec22010a3f9..5fcbea32089d 100644 --- a/drivers/pinctrl/spear/pinctrl-plgpio.c +++ b/drivers/pinctrl/spear/pinctrl-plgpio.c @@ -339,7 +339,7 @@ static int plgpio_irq_set_type(struct irq_data *d, unsigned trigger) if (plgpio->regs.eit == -1) supported_type = IRQ_TYPE_LEVEL_HIGH; else - supported_type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; + supported_type = IRQ_TYPE_EDGE_BOTH; if (!(trigger & supported_type)) return -EINVAL; From 77abd038eaf3a852477daf5c5c4e3cc63fb1399b Mon Sep 17 00:00:00 2001 From: Prathamesh Shete Date: Mon, 27 Jul 2026 14:11:20 +0000 Subject: [PATCH 078/130] dt-bindings: pinctrl: tegra264: fix DAP2 DIN/DOUT pin names The DAP2_DIN and DAP2_DOUT pins were listed with swapped ball suffixes: DAP2_DIN as PV7 and DAP2_DOUT as PW0. On silicon DAP2_DIN is on ball PW0 and DAP2_DOUT is on ball PV7. Correct the pin and drive group names to dap2_din_pw0 and dap2_dout_pv7. Fixes: 30a9d5162f25 ("dt-bindings: pinctrl: Document Tegra264 pin controllers") Signed-off-by: Prathamesh Shete Reviewed-by: Jon Hunter Acked-by: Thierry Reding Acked-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- .../bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml index c40409d3263c..01db762e82bc 100644 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml @@ -44,7 +44,7 @@ patternProperties: soc_gpio173_pu3, soc_gpio174_pu4, soc_gpio175_pu5, soc_gpio176_pu6, soc_gpio177_pu7, soc_gpio178_pv0, pwm10_pv1, uart4_tx_pv2, uart4_rx_pv3, uart4_rts_n_pv4, - uart4_cts_n_pv5, dap2_clk_pv6, dap2_din_pv7, dap2_dout_pw0, + uart4_cts_n_pv5, dap2_clk_pv6, dap2_din_pw0, dap2_dout_pv7, dap2_fs_pw1, gen1_i2c_scl_pw2, gen1_i2c_sda_pw3, gen0_i2c_scl_pw4, gen0_i2c_sda_pw5, pwr_i2c_scl_pw6, pwr_i2c_sda_pw7, soc_gpio138_pp0, soc_gpio139_pp1, @@ -111,8 +111,8 @@ patternProperties: drive_soc_gpio351_ps1, drive_gen0_i2c_scl_pw4, drive_gen0_i2c_sda_pw5, drive_gen1_i2c_scl_pw2, drive_gen1_i2c_sda_pw3, drive_dap2_fs_pw1, - drive_dap2_clk_pv6, drive_dap2_din_pv7, - drive_dap2_dout_pw0, drive_pwm10_pv1, + drive_dap2_clk_pv6, drive_dap2_din_pw0, + drive_dap2_dout_pv7, drive_pwm10_pv1, drive_soc_gpio170_pu0, drive_soc_gpio171_pu1, drive_soc_gpio172_pu2, drive_soc_gpio173_pu3, drive_soc_gpio174_pu4, drive_soc_gpio175_pu5, From 27e5b8efc25b9238865288b7091ae6915c2f7c14 Mon Sep 17 00:00:00 2001 From: Prathamesh Shete Date: Mon, 27 Jul 2026 14:11:21 +0000 Subject: [PATCH 079/130] pinctrl: tegra264: fix DAP2 DIN/DOUT pin assignment The dap2_din and dap2_dout pin groups were given swapped ball suffixes: DAP2_DIN was described as ball PV7 and DAP2_DOUT as ball PW0. On silicon DAP2_DIN is on ball PW0 (mux register 0x6050, drive register 0x6054) and DAP2_DOUT is on ball PV7 (mux register 0x6058, drive register 0x605c), as reflected by the board pinmux. Because the ball suffixes were swapped, the groups were also assigned the wrong primary mux functions (dap2_din -> I2S2_SDATA_OUT and dap2_dout -> I2S2_SDATA_IN), routing the I2S2 data-in and data-out signals to the wrong pins and breaking DAP2 audio. Rename the groups to dap2_din_pw0 and dap2_dout_pv7 and give each pad its correct function (dap2_din_pw0 -> I2S2_SDATA_IN, dap2_dout_pv7 -> I2S2_SDATA_OUT). The register offsets are already correct and are left unchanged. This matches the board pinmux. Fixes: c98506206912 ("pinctrl: tegra: Add Tegra264 pinmux driver") Signed-off-by: Prathamesh Shete Reviewed-by: Jon Hunter Tested-by: Jon Hunter Acked-by: Thierry Reding Signed-off-by: Linus Walleij --- drivers/pinctrl/tegra/pinctrl-tegra264.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/tegra/pinctrl-tegra264.c b/drivers/pinctrl/tegra/pinctrl-tegra264.c index 5a0c91aaba3a..97a7d9db378e 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra264.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra264.c @@ -97,8 +97,8 @@ enum { TEGRA_PIN_UART4_RTS_N_PV4, TEGRA_PIN_UART4_CTS_N_PV5, TEGRA_PIN_DAP2_CLK_PV6, - TEGRA_PIN_DAP2_DIN_PV7, - TEGRA_PIN_DAP2_DOUT_PW0, + TEGRA_PIN_DAP2_DIN_PW0, + TEGRA_PIN_DAP2_DOUT_PV7, TEGRA_PIN_DAP2_FS_PW1, TEGRA_PIN_GEN1_I2C_SCL_PW2, TEGRA_PIN_GEN1_I2C_SDA_PW3, @@ -330,8 +330,8 @@ static const struct pinctrl_pin_desc tegra264_main_pins[] = { PINCTRL_PIN(TEGRA_PIN_UART4_RTS_N_PV4, "UART4_RTS_N_PV4"), PINCTRL_PIN(TEGRA_PIN_UART4_CTS_N_PV5, "UART4_CTS_N_PV5"), PINCTRL_PIN(TEGRA_PIN_DAP2_CLK_PV6, "DAP2_CLK_PV6"), - PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PV7, "DAP2_DIN_PV7"), - PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PW0, "DAP2_DOUT_PW0"), + PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PW0, "DAP2_DIN_PW0"), + PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PV7, "DAP2_DOUT_PV7"), PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PW1, "DAP2_FS_PW1"), PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PW2, "GEN1_I2C_SCL_PW2"), PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PW3, "GEN1_I2C_SDA_PW3"), @@ -828,12 +828,12 @@ static const unsigned int dap2_clk_pv6_pins[] = { TEGRA_PIN_DAP2_CLK_PV6, }; -static const unsigned int dap2_din_pv7_pins[] = { - TEGRA_PIN_DAP2_DIN_PV7, +static const unsigned int dap2_din_pw0_pins[] = { + TEGRA_PIN_DAP2_DIN_PW0, }; -static const unsigned int dap2_dout_pw0_pins[] = { - TEGRA_PIN_DAP2_DOUT_PW0, +static const unsigned int dap2_dout_pv7_pins[] = { + TEGRA_PIN_DAP2_DOUT_PV7, }; static const unsigned int dap2_fs_pw1_pins[] = { @@ -1835,8 +1835,8 @@ static const char * const tegra264_functions[] = { #define drive_gen1_i2c_sda_pw3 DRV_PINGROUP_ENTRY_Y(0x601c, 12, 4, 20, 4, -1, -1, -1, -1, 0) #define drive_dap2_fs_pw1 DRV_PINGROUP_ENTRY_Y(0x6044, 12, 4, 20, 4, -1, -1, -1, -1, 0) #define drive_dap2_clk_pv6 DRV_PINGROUP_ENTRY_Y(0x604c, 12, 4, 20, 4, -1, -1, -1, -1, 0) -#define drive_dap2_din_pv7 DRV_PINGROUP_ENTRY_Y(0x6054, 12, 4, 20, 4, -1, -1, -1, -1, 0) -#define drive_dap2_dout_pw0 DRV_PINGROUP_ENTRY_Y(0x605c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_dap2_din_pw0 DRV_PINGROUP_ENTRY_Y(0x6054, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_dap2_dout_pv7 DRV_PINGROUP_ENTRY_Y(0x605c, 12, 4, 20, 4, -1, -1, -1, -1, 0) #define drive_pwm10_pv1 DRV_PINGROUP_ENTRY_Y(0x6064, 12, 4, 20, 4, -1, -1, -1, -1, 0) #define drive_soc_gpio170_pu0 DRV_PINGROUP_ENTRY_Y(0x606c, 12, 4, 20, 4, -1, -1, -1, -1, 0) #define drive_soc_gpio171_pu1 DRV_PINGROUP_ENTRY_Y(0x6074, 12, 4, 20, 4, -1, -1, -1, -1, 0) @@ -2052,8 +2052,8 @@ static const struct tegra_pingroup tegra264_main_groups[] = { PINGROUP(gen1_i2c_sda_pw3, I2C1_DAT, RSVD1, RSVD2, RSVD3, 0x6018, 0, Y, 5, 7, 6, 8, -1, 10, 11), PINGROUP(dap2_fs_pw1, I2S2_LRCK, RSVD1, RSVD2, RSVD3, 0x6040, 0, Y, 5, 7, 6, 8, -1, 10, 11), PINGROUP(dap2_clk_pv6, I2S2_SCLK, RSVD1, RSVD2, RSVD3, 0x6048, 0, Y, 5, 7, 6, 8, -1, 10, 11), - PINGROUP(dap2_din_pv7, I2S2_SDATA_OUT, RSVD1, RSVD2, RSVD3, 0x6050, 0, Y, 5, 7, 6, 8, -1, 10, 11), - PINGROUP(dap2_dout_pw0, I2S2_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x6058, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(dap2_din_pw0, I2S2_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x6050, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(dap2_dout_pv7, I2S2_SDATA_OUT, RSVD1, RSVD2, RSVD3, 0x6058, 0, Y, 5, 7, 6, 8, -1, 10, 11), PINGROUP(pwm10_pv1, GP_PWM10, SDMMC1_CD, I2S7_LRCK, RSVD3, 0x6060, 0, Y, 5, 7, 6, 8, -1, 10, 11), PINGROUP(soc_gpio170_pu0, RSVD0, I2S7_SDATA_IN, CCLA_LA_TRIGGER_MUX, RSVD3, 0x6068, 0, Y, 5, 7, 6, 8, -1, 10, 11), PINGROUP(soc_gpio171_pu1, RSVD0, SPI4_SCK, RSVD2, RSVD3, 0x6070, 0, Y, 5, 7, 6, 8, -1, 10, 11), From 5b695c191cc85f0fd62eec885b55d01468dc9f2c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 3 Aug 2026 08:10:23 -0600 Subject: [PATCH 080/130] pinctrl: rockchip: Reset the pin count when recalculating SoC data rockchip_pinctrl_get_soc_data() mutates the static per-SoC data. The iomux and drive offsets are recalculated idempotently, since a rerun anchors at the values calculated before, but the total pin count only accumulates: each run adds every bank's pins again. When the probe is deferred and runs a second time, nr_pins doubles and every bank's pin_base shifts, so later pin lookups resolve to the wrong bank and the wrong registers. Reset the pin count at the start of the calculation, so that a rerun produces the same values. This is verified on a Luckfox Pico Mini B (RV1103, with the pending RV1106 series applied) by forcing the probe to defer once: without this patch the second probe calculates nr_pins=304 instead of 152 and no GPIO bank comes up; with it the recalculation matches the first run and all banks work. Fixes: d3e5116119bd ("pinctrl: add pinctrl driver for Rockchip SoCs") Link: https://sashiko.dev/#/patchset/20260729132736.3807082-1-sjg@chromium.org?part=4 Assisted-by: Claude:claude-opus-5 Signed-off-by: Simon Glass Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-rockchip.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index e90e13c5d7f2..dbbbfdc73848 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -4437,6 +4437,16 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( pmu_offs = ctrl->pmu_mux_offset; drv_pmu_offs = ctrl->pmu_drv_offset; drv_grf_offs = ctrl->grf_drv_offset; + + /* + * This function mutates the static per-SoC data. Most of it is + * idempotent: recalculated iomux and drv offsets anchor at the + * values calculated by a previous run. The pin count is not, so + * reset it here; otherwise it accumulates when the probe runs + * again after a probe deferral, shifting every bank's pin_base. + */ + ctrl->nr_pins = 0; + bank = ctrl->pin_banks; for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { int bank_pins = 0; From 35ff52e54b38b01914be62ece27899665a46af56 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 3 Aug 2026 08:10:24 -0600 Subject: [PATCH 081/130] pinctrl: rockchip: Restrict the RV1103B 2-bit drive type to bank 2 The RV1103B override in rockchip_get_drive_perpin() forces the 2-bit level drive type for every pin above 11, but only bank 2 has the 2-bit fields; banks 0 and 1 use the 8-bit level type for all pins, as the corresponding check in rockchip_set_drive_perpin() shows. Today this is harmless, since neither level type is decoded in the get function and both paths fail with -EINVAL. It becomes an active problem once decoding is added, as the pins of banks 0 and 1 would be truncated to 2-bit values. Add the missing bank check, matching the set path. Fixes: 6d3ea3120eaa ("pinctrl: rockchip: Add RV1103B pinctrl support") Link: https://sashiko.dev/#/patchset/20260729132736.3807082-1-sjg@chromium.org?part=1 Assisted-by: Claude:claude-opus-5 Signed-off-by: Simon Glass Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-rockchip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index dbbbfdc73848..8c7e410ec9d1 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -3350,7 +3350,7 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, u8 bit; int drv_type = bank->drv[pin_num / 8].drv_type; - if (ctrl->type == RV1103B && pin_num >= 12) + if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) drv_type = DRV_TYPE_IO_LEVEL_2_BIT; ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); From 7716c99fa74a54ae460e52b5d0d5cfebb5d710dc Mon Sep 17 00:00:00 2001 From: Bhargav Joshi Date: Wed, 22 Jul 2026 22:15:54 +0530 Subject: [PATCH 082/130] dt-bindings: pinctrl: ti,dra7-iodelay: Convert to DT schema Convert TI IODELAY controller from text to DT schema. Document child properties missing from text bindings for proper validation. Signed-off-by: Bhargav Joshi Reviewed-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- .../bindings/pinctrl/ti,dra7-iodelay.yaml | 83 +++++++++++++++++++ .../bindings/pinctrl/ti,iodelay.txt | 47 ----------- 2 files changed, 83 insertions(+), 47 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/ti,dra7-iodelay.yaml delete mode 100644 Documentation/devicetree/bindings/pinctrl/ti,iodelay.txt diff --git a/Documentation/devicetree/bindings/pinctrl/ti,dra7-iodelay.yaml b/Documentation/devicetree/bindings/pinctrl/ti,dra7-iodelay.yaml new file mode 100644 index 000000000000..a798552c1ac2 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ti,dra7-iodelay.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ti,dra7-iodelay.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Pin configuration for TI IODELAY controller + +maintainers: + - Nishanth Menon + - Bhargav Joshi + +description: + TI dra7 based SoCs such as am57xx have a controller for setting the IO delay + for each pin. For most part the IO delay values are programmed by the + bootloader, but some pins need to be configured dynamically by the kernel such + as the MMC pins. + +properties: + compatible: + const: ti,dra7-iodelay + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + '#pinctrl-cells': + const: 2 + +patternProperties: + ^.*_conf$: + type: object + additionalProperties: false + + properties: + pinctrl-pin-array: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + An array of 32-bit integers defining the pin delay configuration. + + required: + - pinctrl-pin-array + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + - '#pinctrl-cells' + +additionalProperties: false + +examples: + - | + #include + + padconf@4844a000 { + compatible = "ti,dra7-iodelay"; + reg = <0x4844a000 0x0d1c>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <2>; + + mmc2_iodelay_3v3_conf { + pinctrl-pin-array = < + 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */ + 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */ + 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */ + 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */ + 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */ + 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */ + 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ + 0x1ec A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */ + 0x1f8 A_DELAY_PS(120) G_DELAY_PS(180) /* CFG_GPMC_A27_IN */ + 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ + >; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/ti,iodelay.txt b/Documentation/devicetree/bindings/pinctrl/ti,iodelay.txt deleted file mode 100644 index c3ed1232b6a3..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/ti,iodelay.txt +++ /dev/null @@ -1,47 +0,0 @@ -* Pin configuration for TI IODELAY controller - -TI dra7 based SoCs such as am57xx have a controller for setting the IO delay -for each pin. For most part the IO delay values are programmed by the bootloader, -but some pins need to be configured dynamically by the kernel such as the -MMC pins. - -Required Properties: - - - compatible: Must be "ti,dra7-iodelay" - - reg: Base address and length of the memory resource used - - #address-cells: Number of address cells - - #size-cells: Size of cells - - #pinctrl-cells: Number of pinctrl cells, must be 2. See also - Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - -Example -------- - -In the SoC specific dtsi file: - - dra7_iodelay_core: padconf@4844a000 { - compatible = "ti,dra7-iodelay"; - reg = <0x4844a000 0x0d1c>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <2>; - }; - -In board-specific file: - -&dra7_iodelay_core { - mmc2_iodelay_3v3_conf: mmc2_iodelay_3v3_conf { - pinctrl-pin-array = < - 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */ - 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */ - 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */ - 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */ - 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */ - 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */ - 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ - 0x1ec A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */ - 0x1f8 A_DELAY_PS(120) G_DELAY_PS(180) /* CFG_GPMC_A27_IN */ - 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ - >; - }; -}; From acb4f82a54a3b4465aee7556c7c41704fc2b0fc8 Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:05:39 +0300 Subject: [PATCH 083/130] dt-bindings: pinctrl: airoha: en7581: fix misprint in i2s function name Due to misprint i2s pin-function is missed, instead i2c pin-function defined twice. The second of them operates with i2s pin-group. Let's fix the typo so that the i2s function is defined correctly. Fixes: d0c15cb96b74 ("dt-bindings: pinctrl: airoha: Add EN7581 pinctrl") Signed-off-by: Mikhail Kshevetskiy Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml index 21fd4f1ba78b..0c5a7eb6d563 100644 --- a/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml @@ -166,7 +166,7 @@ patternProperties: - if: properties: function: - const: i2c + const: i2s then: properties: groups: From 282f2cee8a3f407d5fa4eb1dc56393f68abaa5f7 Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:05:40 +0300 Subject: [PATCH 084/130] dt-bindings: pinctrl: airoha: an7583: fix device tree binding schema An7583 device tree binding schema was more or less blinly copied from corresponding en7581 schema. As result it's not correct. There are following issues: * i2s pin-function is not really defined for an7583 * i2s pin-function by mistake was replaced by i2c pin-function in the functions/groups checks * pcm_spi pin-function defined for less number of pin-groups * pwm pin-function should have more pin-groups elements * unexisting pins was defined Fix an7583 schema, so it matches actual pinctrl driver. Fixes: e6e47d31d3f8 ("dt-bindings: pinctrl: airoha: Document AN7583 Pin Controller") Signed-off-by: Mikhail Kshevetskiy Reviewed-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- .../pinctrl/airoha,an7583-pinctrl.yaml | 37 +++++++------------ 1 file changed, 14 insertions(+), 23 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml index 79910214d9b5..f52802a3ad79 100644 --- a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml @@ -61,7 +61,7 @@ patternProperties: description: A string containing the name of the function to mux to the group. enum: [pon, tod_1pps, sipo, mdio, uart, i2c, jtag, pcm, spi, - pcm_spi, i2s, emmc, pnand, pcie_reset, pwm, phy1_led0, + pcm_spi, emmc, pnand, pcie_reset, pwm, phy1_led0, phy2_led0, phy3_led0, phy4_led0, phy1_led1, phy2_led1, phy3_led1, phy4_led1] @@ -159,17 +159,8 @@ patternProperties: properties: groups: items: - enum: [pcm_spi, pcm_spi_int, pcm_spi_rst, pcm_spi_cs1, - pcm_spi_cs2, pcm_spi_cs3, pcm_spi_cs4] - maxItems: 7 - - if: - properties: - function: - const: i2c - then: - properties: - groups: - enum: [i2s] + enum: [pcm_spi, pcm_spi_rst, pcm_spi_cs1] + maxItems: 3 - if: properties: function: @@ -207,7 +198,8 @@ patternProperties: gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, gpio26, gpio27, gpio28, gpio29, gpio30, gpio31, gpio36, gpio37, gpio38, gpio39, gpio40, gpio41, - gpio42, gpio43, gpio44, gpio45, gpio46, gpio47] + gpio42, gpio43, gpio44, gpio45, gpio46, gpio47, + gpio48] - if: properties: function: @@ -288,17 +280,16 @@ patternProperties: description: An array of strings. Each string contains the name of a pin. items: - enum: [uart1_txd, uart1_rxd, i2c_scl, i2c_sda, spi_cs0, spi_clk, - spi_mosi, spi_miso, gpio0, gpio1, gpio2, gpio3, gpio4, - gpio5, gpio6, gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, - gpio13, gpio14, gpio15, gpio16, gpio17, gpio18, gpio19, - gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, gpio26, - gpio27, gpio28, gpio29, gpio30, gpio31, gpio32, gpio33, - gpio34, gpio35, gpio36, gpio37, gpio38, gpio39, gpio40, - gpio41, gpio42, gpio43, gpio44, gpio45, gpio46, - pcie_reset0, pcie_reset1, pcie_reset2] + enum: [gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, + gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio14, + gpio15, gpio16, gpio17, gpio18, gpio19, gpio20, gpio21, + gpio22, gpio23, gpio24, gpio25, gpio26, gpio27, gpio28, + gpio29, gpio30, gpio31, gpio32, gpio33, gpio34, gpio35, + gpio36, gpio37, gpio38, i2c0_scl, i2c0_sda, i2c1_scl, + i2c1_sda, spi_clk, spi_cs, spi_mosi, spi_miso, uart_txd, + uart_rxd, pcie_reset0, pcie_reset1, mdc_0, mdio_0] minItems: 1 - maxItems: 58 + maxItems: 53 bias-disable: true From a8454680a6ce75fbbd8086bcb654eacf7897bc0f Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:05:41 +0300 Subject: [PATCH 085/130] pinctrl: airoha: fix mdio bitfield names Fix misprint in mdio bitfield name of GPIO_2ND_I2C_MODE register. While at it also fix an7583 mdio. It should use an7583 specific mdio bitfield. Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC") Signed-off-by: Mikhail Kshevetskiy Acked-by: Lorenzo Bianconi Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/pinctrl-airoha.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c index 90372827639d..4462d0c7c491 100644 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c @@ -49,7 +49,7 @@ /* MUX */ #define REG_GPIO_2ND_I2C_MODE 0x0214 -#define GPIO_MDC_IO_MASTER_MODE_MODE BIT(14) +#define GPIO_MDC_IO_MASTER_MODE_MASK BIT(14) #define GPIO_I2C_MASTER_MODE_MODE BIT(13) #define GPIO_I2S_MODE_MASK BIT(12) #define GPIO_I2C_SLAVE_MODE_MODE BIT(11) @@ -66,6 +66,7 @@ #define GPIO_2ND_I2C_MODE_MASK BIT(0) #define REG_GPIO_SPI_CS1_MODE 0x0218 +#define AN7583_GPIO_MDC_IO_MASTER_MODE_MASK BIT(22) #define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21) #define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20) #define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19) @@ -1026,8 +1027,8 @@ static const struct airoha_pinctrl_func_group mdio_func_group[] = { .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_2ND_I2C_MODE, - GPIO_MDC_IO_MASTER_MODE_MODE, - GPIO_MDC_IO_MASTER_MODE_MODE + GPIO_MDC_IO_MASTER_MODE_MASK, + GPIO_MDC_IO_MASTER_MODE_MASK }, .regmap[1] = { AIROHA_FUNC_MUX, @@ -1051,8 +1052,8 @@ static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE, - GPIO_MDC_IO_MASTER_MODE_MODE, - GPIO_MDC_IO_MASTER_MODE_MODE + AN7583_GPIO_MDC_IO_MASTER_MODE_MASK, + AN7583_GPIO_MDC_IO_MASTER_MODE_MASK }, .regmap_size = 2, }, From 65ce9d5d781f872596194771d62ad6e1260fcf4f Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:05:42 +0300 Subject: [PATCH 086/130] pinctrl: airoha: an7581: fix pinconf of i2c_scl/i2c_sda pins Pinconfs of i2c_sda/i2c_scl pins are swapped, this needs to be fixed. Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC") Signed-off-by: Mikhail Kshevetskiy Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/pinctrl-airoha.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c index 4462d0c7c491..d18387c8bb27 100644 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c @@ -1844,8 +1844,8 @@ static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = { static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = { PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), - PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), - PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), + PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), @@ -1961,8 +1961,8 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = { static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = { PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), - PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), - PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), + PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), @@ -2078,8 +2078,8 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = { static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = { PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), - PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), - PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), + PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), @@ -2195,8 +2195,8 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = { static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = { PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), - PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), - PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), + PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), From d560e28bdca824781898023496658404df01be9f Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:05:43 +0300 Subject: [PATCH 087/130] pinctrl: airoha: an7583: fix I2C0_SDA_PD register bit order I2C1_SCL_PD and RG_I2C1_SDA_PD bits are swapped, fix it. Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs") Signed-off-by: Mikhail Kshevetskiy Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/pinctrl-airoha.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c index d18387c8bb27..501d88369b86 100644 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c @@ -185,8 +185,8 @@ #define I2C_SDA_PU_MASK BIT(0) #define REG_I2C_SDA_PD 0x0048 -#define AN7583_I2C1_SDA_PD_MASK BIT(16) -#define AN7583_I2C1_SCL_PD_MASK BIT(15) +#define AN7583_I2C1_SCL_PD_MASK BIT(16) +#define AN7583_I2C1_SDA_PD_MASK BIT(15) #define SPI_MISO_PD_MASK BIT(14) #define SPI_MOSI_PD_MASK BIT(13) #define SPI_CLK_PD_MASK BIT(12) From fdce588071f06638bdc91c01ace0822f39336ea3 Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:05:44 +0300 Subject: [PATCH 088/130] dt-bindings: pinctrl: airoha: en7581: allow configuration of pcie_reset pins as gpio or pwm In the an7581 case * gpio47 and pcie_reset0 shares the same pin, * gpio48 and pcie_reset1 shares the same pin, * gpio49 and pcie_reset2 shares the same pin. Let's define a way to configure these pins as gpio or pwm. Also add gpio-range property in the dts example. Signed-off-by: Mikhail Kshevetskiy Signed-off-by: Linus Walleij --- .../bindings/pinctrl/airoha,en7581-pinctrl.yaml | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml index 0c5a7eb6d563..0cf1826c691f 100644 --- a/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml @@ -61,7 +61,7 @@ patternProperties: description: A string containing the name of the function to mux to the group. enum: [pon, tod_1pps, sipo, mdio, uart, i2c, jtag, pcm, spi, - pcm_spi, i2s, emmc, pnand, pcie_reset, pwm, phy1_led0, + pcm_spi, i2s, emmc, pnand, gpio, pcie_reset, pwm, phy1_led0, phy2_led0, phy3_led0, phy4_led0, phy1_led1, phy2_led1, phy3_led1, phy4_led1] @@ -187,6 +187,14 @@ patternProperties: properties: groups: enum: [pnand] + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [gpio47, gpio48, gpio49] - if: properties: function: @@ -208,7 +216,8 @@ patternProperties: gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, gpio26, gpio27, gpio28, gpio29, gpio30, gpio31, gpio36, gpio37, gpio38, gpio39, gpio40, gpio41, - gpio42, gpio43, gpio44, gpio45, gpio46, gpio47] + gpio42, gpio43, gpio44, gpio45, gpio46, gpio47, + gpio48, gpio49] - if: properties: function: @@ -347,6 +356,8 @@ examples: interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&pinctrl 0 13 50>; + pcie1-rst-pins { conf { pins = "pcie_reset1"; From 739bc85aed14b739dca5b7aff4241b778af80220 Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:05:45 +0300 Subject: [PATCH 089/130] pinctrl: airoha: an7581: fix mux/conf of pcie_reset pins In the an7581 case * gpio47 and pcie_reset0 shares pin 60, * gpio48 and pcie_reset1 shares pin 61, * gpio49 and pcie_reset2 shares pin 62. but current driver treat them as pins 61--63. This is wrong. Also current an7581 pinmux implementation have following issues: * current pcie_reset pin function actually sets corresponding pins as gpios. * there is no proper way to set pcie_reset pins as gpios. * there is no way to set pcie_reset pins as pwm. This patch fixes above issues. WARNING: There is a contradiction in the Airoha documentation. AN7581 programming guide claims: - gpio44 and pcie_reset0 shares the same pin - gpio45 and pcie_reset1 shares the same pin - gpio46 and pcie_reset2 shares the same pin While AN7581 datasheet claims: - gpio47 and pcie_reset0 shares the same pin - gpio48 and pcie_reset1 shares the same pin - gpio49 and pcie_reset2 shares the same pin The datasheet should be considered as a more reliable source. Thanks to Benjamin Larsson for clarification. Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC") Signed-off-by: Mikhail Kshevetskiy Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/pinctrl-airoha.c | 122 +++++++++++++++++++----- 1 file changed, 97 insertions(+), 25 deletions(-) diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c index 501d88369b86..b73659e4fdee 100644 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c @@ -470,9 +470,9 @@ static struct pinctrl_pin_desc en7581_pinctrl_pins[] = { PINCTRL_PIN(57, "gpio44"), PINCTRL_PIN(58, "gpio45"), PINCTRL_PIN(59, "gpio46"), - PINCTRL_PIN(61, "pcie_reset0"), - PINCTRL_PIN(62, "pcie_reset1"), - PINCTRL_PIN(63, "pcie_reset2"), + PINCTRL_PIN(60, "pcie_reset0"), + PINCTRL_PIN(61, "pcie_reset1"), + PINCTRL_PIN(62, "pcie_reset2"), }; static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 }; @@ -555,9 +555,12 @@ static const int en7581_gpio43_pins[] = { 56 }; static const int en7581_gpio44_pins[] = { 57 }; static const int en7581_gpio45_pins[] = { 58 }; static const int en7581_gpio46_pins[] = { 59 }; -static const int en7581_pcie_reset0_pins[] = { 61 }; -static const int en7581_pcie_reset1_pins[] = { 62 }; -static const int en7581_pcie_reset2_pins[] = { 63 }; +static const int en7581_gpio47_pins[] = { 60 }; +static const int en7581_gpio48_pins[] = { 61 }; +static const int en7581_gpio49_pins[] = { 62 }; +static const int en7581_pcie_reset0_pins[] = { 60 }; +static const int en7581_pcie_reset1_pins[] = { 61 }; +static const int en7581_pcie_reset2_pins[] = { 62 }; static const struct pingroup en7581_pinctrl_groups[] = { PINCTRL_PIN_GROUP("pon", en7581_pon), @@ -640,6 +643,9 @@ static const struct pingroup en7581_pinctrl_groups[] = { PINCTRL_PIN_GROUP("gpio44", en7581_gpio44), PINCTRL_PIN_GROUP("gpio45", en7581_gpio45), PINCTRL_PIN_GROUP("gpio46", en7581_gpio46), + PINCTRL_PIN_GROUP("gpio47", en7581_gpio47), + PINCTRL_PIN_GROUP("gpio48", en7581_gpio48), + PINCTRL_PIN_GROUP("gpio49", en7581_gpio49), PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0), PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1), PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2), @@ -883,6 +889,7 @@ static const char *const an7583_pcm_spi_groups[] = { "pcm_spi", static const char *const i2s_groups[] = { "i2s" }; static const char *const emmc_groups[] = { "emmc" }; static const char *const pnand_groups[] = { "pnand" }; +static const char *const gpio_groups[] = { "gpio47", "gpio48", "gpio49" }; static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1", "pcie_reset2" }; static const char *const an7583_pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1" }; @@ -907,7 +914,8 @@ static const char *const pwm_groups[] = { "gpio0", "gpio1", "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", - "gpio46" }; + "gpio46", "gpio47", + "gpio48", "gpio49" }; static const char *const an7583_pwm_groups[] = { "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", @@ -1406,6 +1414,45 @@ static const struct airoha_pinctrl_func_group pnand_func_group[] = { }, }; +#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + 0 \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (smux_val), \ + (smux_val) \ + }, \ + .regmap_size = 2, \ + } + +static const struct airoha_pinctrl_func_group gpio_func_group[] = { + AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG, + GPIO_PCIE_RESET0_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG, + GPIO_PCIE_RESET1_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG, + GPIO_PCIE_RESET2_MASK), +}; + static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = { { .name = "pcie_reset0", @@ -1413,7 +1460,7 @@ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE, GPIO_PCIE_RESET0_MASK, - GPIO_PCIE_RESET0_MASK + 0 }, .regmap_size = 1, }, { @@ -1422,7 +1469,7 @@ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE, GPIO_PCIE_RESET1_MASK, - GPIO_PCIE_RESET1_MASK + 0 }, .regmap_size = 1, }, { @@ -1431,7 +1478,7 @@ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE, GPIO_PCIE_RESET2_MASK, - GPIO_PCIE_RESET2_MASK + 0 }, .regmap_size = 1, }, @@ -1484,6 +1531,24 @@ static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = { .regmap_size = 1, \ } \ +#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (smux_val), \ + (smux_val) \ + }, \ + .regmap_size = 2, \ + } + static const struct airoha_pinctrl_func_group pwm_func_group[] = { AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), @@ -1528,6 +1593,12 @@ static const struct airoha_pinctrl_func_group pwm_func_group[] = { AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG), AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG), AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG, + GPIO_PCIE_RESET0_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG, + GPIO_PCIE_RESET1_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG, + GPIO_PCIE_RESET2_MASK), }; static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = { @@ -1804,6 +1875,7 @@ static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = { PINCTRL_FUNC_DESC("i2s", i2s), PINCTRL_FUNC_DESC("emmc", emmc), PINCTRL_FUNC_DESC("pnand", pnand), + PINCTRL_FUNC_DESC("gpio", gpio), PINCTRL_FUNC_DESC("pcie_reset", pcie_reset), PINCTRL_FUNC_DESC("pwm", pwm), PINCTRL_FUNC_DESC("phy1_led0", phy1_led0), @@ -1897,9 +1969,9 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = { PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)), PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)), PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)), - PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), - PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), - PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK), + PINCTRL_CONF_DESC(60, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), + PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), + PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK), }; static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = { @@ -2014,9 +2086,9 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = { PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)), PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)), PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)), - PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), - PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), - PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK), + PINCTRL_CONF_DESC(60, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), + PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), + PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK), }; static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = { @@ -2131,9 +2203,9 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = { PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)), PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)), PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)), - PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), - PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), - PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK), + PINCTRL_CONF_DESC(60, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), + PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), + PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK), }; static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = { @@ -2248,9 +2320,9 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = { PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)), PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)), PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)), - PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), - PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), - PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK), + PINCTRL_CONF_DESC(60, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), + PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), + PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK), }; static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = { @@ -2310,9 +2382,9 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = { }; static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = { - PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), - PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), - PINCTRL_CONF_DESC(63, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK), + PINCTRL_CONF_DESC(60, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), + PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), + PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK), }; static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = { From da64ec8b4d3f6d3c2f61590b1264f8901bc37d45 Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:05:46 +0300 Subject: [PATCH 090/130] dt-bindings: pinctrl: airoha: an7583: allow configuration of non-gpio default pins as gpio and pwm Some AN7583 pins have non-gpio default settings. This patch provides a way to configure such pins as GPIO or PWM. Also add gpio-range property in the dts example. Please note that gpio52 pin can't be configured as PWM pin. Signed-off-by: Mikhail Kshevetskiy Reviewed-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- .../bindings/pinctrl/airoha,an7583-pinctrl.yaml | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml index f52802a3ad79..3e680c997fe2 100644 --- a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml @@ -61,7 +61,7 @@ patternProperties: description: A string containing the name of the function to mux to the group. enum: [pon, tod_1pps, sipo, mdio, uart, i2c, jtag, pcm, spi, - pcm_spi, emmc, pnand, pcie_reset, pwm, phy1_led0, + pcm_spi, emmc, pnand, gpio, pcie_reset, pwm, phy1_led0, phy2_led0, phy3_led0, phy4_led0, phy1_led1, phy2_led1, phy3_led1, phy4_led1] @@ -177,6 +177,16 @@ patternProperties: properties: groups: enum: [pnand] + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [gpio39, gpio40, gpio41, gpio42, gpio43, gpio44, + gpio45, gpio46, gpio47, gpio48, gpio49, gpio50, + gpio51, gpio52] - if: properties: function: @@ -199,7 +209,7 @@ patternProperties: gpio26, gpio27, gpio28, gpio29, gpio30, gpio31, gpio36, gpio37, gpio38, gpio39, gpio40, gpio41, gpio42, gpio43, gpio44, gpio45, gpio46, gpio47, - gpio48] + gpio48, gpio49, gpio50, gpio51] - if: properties: function: @@ -337,6 +347,8 @@ examples: interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&pinctrl 0 2 53>; + pcie1-rst-pins { conf { pins = "pcie_reset1"; From aaa41d8010c04635e035a9d334885b07edc8af21 Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:05:47 +0300 Subject: [PATCH 091/130] pinctrl: airoha: an7583: fix muxing of non-gpio default pins Current an7583 pinmux implementation have following issues: * pins 51 and 52 can't be set as pcie_reset, current pcie_reset code will sets pins to gpio mode instead. * there is no proper way to set pins 41--54 to gpio mode. * pins 41--53 can't be actually set as pwm pins. These pins must be muxed to gpio mode as well. This patch fixes above issues. Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs") Signed-off-by: Mikhail Kshevetskiy Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/pinctrl-airoha.c | 99 +++++++++++++++++++++---- 1 file changed, 86 insertions(+), 13 deletions(-) diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c index b73659e4fdee..5012c21c9c32 100644 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c @@ -85,6 +85,18 @@ #define GPIO_SPI_CS1_MODE_MASK BIT(0) #define REG_GPIO_PON_MODE 0x021c +#define AN7583_MDIO_0_GPIO_MODE_MASK BIT(26) +#define AN7583_MDC_0_GPIO_MODE_MASK BIT(25) +#define AN7583_UART_RXD_GPIO_MODE_MASK BIT(24) +#define AN7583_UART_TXD_GPIO_MODE_MASK BIT(23) +#define AN7583_SPI_MISO_GPIO_MODE_MASK BIT(22) +#define AN7583_SPI_MOSI_GPIO_MODE_MASK BIT(21) +#define AN7583_SPI_CS_GPIO_MODE_MASK BIT(20) +#define AN7583_SPI_CLK_GPIO_MODE_MASK BIT(19) +#define AN7583_I2C1_SDA_GPIO_MODE_MASK BIT(18) +#define AN7583_I2C1_SCL_GPIO_MODE_MASK BIT(17) +#define AN7583_I2C0_SDA_GPIO_MODE_MASK BIT(16) +#define AN7583_I2C0_SCL_GPIO_MODE_MASK BIT(15) #define GPIO_PARALLEL_NAND_MODE_MASK BIT(14) #define GPIO_SGMII_MDIO_MODE_MASK BIT(13) #define GPIO_PCIE_RESET2_MASK BIT(12) @@ -783,6 +795,10 @@ static const int an7583_gpio45_pins[] = { 47 }; static const int an7583_gpio46_pins[] = { 48 }; static const int an7583_gpio47_pins[] = { 49 }; static const int an7583_gpio48_pins[] = { 50 }; +static const int an7583_gpio49_pins[] = { 51 }; +static const int an7583_gpio50_pins[] = { 52 }; +static const int an7583_gpio51_pins[] = { 53 }; +static const int an7583_gpio52_pins[] = { 54 }; static const int an7583_pcie_reset0_pins[] = { 51 }; static const int an7583_pcie_reset1_pins[] = { 52 }; @@ -863,6 +879,10 @@ static const struct pingroup an7583_pinctrl_groups[] = { PINCTRL_PIN_GROUP("gpio46", an7583_gpio46), PINCTRL_PIN_GROUP("gpio47", an7583_gpio47), PINCTRL_PIN_GROUP("gpio48", an7583_gpio48), + PINCTRL_PIN_GROUP("gpio49", an7583_gpio49), + PINCTRL_PIN_GROUP("gpio50", an7583_gpio50), + PINCTRL_PIN_GROUP("gpio51", an7583_gpio51), + PINCTRL_PIN_GROUP("gpio52", an7583_gpio52), PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0), PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1), }; @@ -892,6 +912,11 @@ static const char *const pnand_groups[] = { "pnand" }; static const char *const gpio_groups[] = { "gpio47", "gpio48", "gpio49" }; static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1", "pcie_reset2" }; +static const char *const an7583_gpio_groups[] = { "gpio39", "gpio40", "gpio41", + "gpio42", "gpio43", "gpio44", + "gpio45", "gpio46", "gpio47", + "gpio48", "gpio49", "gpio50", + "gpio51", "gpio52" }; static const char *const an7583_pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1" }; static const char *const pwm_groups[] = { "gpio0", "gpio1", "gpio2", "gpio3", @@ -938,7 +963,8 @@ static const char *const an7583_pwm_groups[] = { "gpio0", "gpio1", "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", - "gpio48" }; + "gpio48", "gpio49", + "gpio50", "gpio51" }; static const char *const phy1_led0_groups[] = { "gpio33", "gpio34", "gpio35", "gpio42" }; static const char *const phy2_led0_groups[] = { "gpio33", "gpio34", @@ -1484,6 +1510,36 @@ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = { }, }; +static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = { + AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG, + AN7583_I2C0_SCL_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG, + AN7583_I2C0_SDA_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG, + AN7583_I2C1_SCL_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG, + AN7583_I2C1_SDA_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG, + AN7583_SPI_CLK_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG, + AN7583_SPI_CS_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG, + AN7583_SPI_MOSI_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG, + AN7583_SPI_MISO_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG, + AN7583_UART_TXD_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG, + AN7583_UART_RXD_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG, + GPIO_PCIE_RESET0_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG, + GPIO_PCIE_RESET1_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG, + AN7583_MDC_0_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK), +}; + static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = { { .name = "pcie_reset0", @@ -1491,7 +1547,7 @@ static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE, GPIO_PCIE_RESET0_MASK, - GPIO_PCIE_RESET0_MASK + 0 }, .regmap_size = 1, }, { @@ -1500,7 +1556,7 @@ static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE, GPIO_PCIE_RESET1_MASK, - GPIO_PCIE_RESET1_MASK + 0 }, .regmap_size = 1, }, @@ -1637,16 +1693,32 @@ static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = { AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG), AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG), AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio47", GPIO47_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio48", GPIO48_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG, + AN7583_I2C0_SCL_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG, + AN7583_I2C0_SDA_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG, + AN7583_I2C1_SCL_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG, + AN7583_I2C1_SDA_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG, + AN7583_SPI_CLK_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG, + AN7583_SPI_CS_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG, + AN7583_SPI_MOSI_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG, + AN7583_SPI_MISO_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG, + AN7583_UART_TXD_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG, + AN7583_UART_RXD_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG, + GPIO_PCIE_RESET0_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG, + GPIO_PCIE_RESET1_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG, + AN7583_MDC_0_GPIO_MODE_MASK), }; #define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ @@ -1901,6 +1973,7 @@ static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = { PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi), PINCTRL_FUNC_DESC("emmc", emmc), PINCTRL_FUNC_DESC("pnand", pnand), + PINCTRL_FUNC_DESC("gpio", an7583_gpio), PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset), PINCTRL_FUNC_DESC("pwm", an7583_pwm), PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0), From bf76a61cf93de4df641b564082e48d2396f5ecc1 Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck Date: Fri, 7 Aug 2026 01:05:48 +0300 Subject: [PATCH 092/130] pinctrl: airoha: fix I2C1 pin mux config for AN7581 The pin mux on GPIOs 1 and 2 on AN7581 supports I2C in master and slave mode. When selecting I2C the according bits (bit 13 for master, bit 11 for slave) must be set in REG_GPIO_2ND_I2C_MODE. Fix the i2c1 pin group to set bits 0 and 13 to set I2C1 master mode by default. Signed-off-by: Daniel Schwierzeck Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/pinctrl-airoha.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c index 5012c21c9c32..1e913c6a31ff 100644 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c @@ -1158,8 +1158,8 @@ static const struct airoha_pinctrl_func_group i2c_func_group[] = { .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_2ND_I2C_MODE, - GPIO_2ND_I2C_MODE_MASK, - GPIO_2ND_I2C_MODE_MASK + GPIO_2ND_I2C_MODE_MASK | GPIO_I2C_MASTER_MODE_MODE, + GPIO_2ND_I2C_MODE_MASK | GPIO_I2C_MASTER_MODE_MODE, }, .regmap_size = 1, }, From bc662fe067d232b11d84a1feb1f67b4e2c6b5bd7 Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:05:49 +0300 Subject: [PATCH 093/130] dt-bindings: pinctrl: airoha: an7583: add i2c0 group for i2c function add mux to force enable i2c0 bus. Signed-off-by: Mikhail Kshevetskiy Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml index 3e680c997fe2..24f1ac60eea8 100644 --- a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml @@ -124,7 +124,7 @@ patternProperties: then: properties: groups: - enum: [i2c1] + enum: [i2c0, i2c1] - if: properties: function: From 0562b05f4ac71cc32fce361425c01a6acecec1a0 Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck Date: Fri, 7 Aug 2026 01:05:50 +0300 Subject: [PATCH 094/130] pinctrl: airoha: fix I2C pin mux config for AN7583 On AN7583 both I2C busses have a pin sharing with GPIO. Also the pin mux setting is done in REG_GPIO_PON_MODE instead of REG_GPIO_2ND_I2C_MODE. Add dedicated I2C pin groups and function groups for AN7583. The new groups must support i2c0 and i2c1. Signed-off-by: Daniel Schwierzeck Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/pinctrl-airoha.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c index 1e913c6a31ff..2288b1e911b4 100644 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c @@ -896,6 +896,7 @@ static const char *const uart_groups[] = { "uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts", "uart4", "uart5" }; static const char *const i2c_groups[] = { "i2c1" }; +static const char *const an7583_i2c_groups[] = { "i2c0", "i2c1" }; static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" }; static const char *const pcm_groups[] = { "pcm1", "pcm2" }; static const char *const spi_groups[] = { "spi_quad", "spi_cs1" }; @@ -1165,6 +1166,28 @@ static const struct airoha_pinctrl_func_group i2c_func_group[] = { }, }; +static const struct airoha_pinctrl_func_group an7583_i2c_func_group[] = { + { + .name = "i2c0", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + AN7583_I2C0_SCL_GPIO_MODE_MASK | AN7583_I2C0_SDA_GPIO_MODE_MASK, + 0 + }, + .regmap_size = 1, + }, { + .name = "i2c1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + AN7583_I2C1_SCL_GPIO_MODE_MASK | AN7583_I2C1_SDA_GPIO_MODE_MASK, + 0 + }, + .regmap_size = 1, + }, +}; + static const struct airoha_pinctrl_func_group jtag_func_group[] = { { .name = "jtag_udi", @@ -1966,7 +1989,7 @@ static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = { PINCTRL_FUNC_DESC("sipo", sipo), PINCTRL_FUNC_DESC("mdio", an7583_mdio), PINCTRL_FUNC_DESC("uart", uart), - PINCTRL_FUNC_DESC("i2c", i2c), + PINCTRL_FUNC_DESC("i2c", an7583_i2c), PINCTRL_FUNC_DESC("jtag", jtag), PINCTRL_FUNC_DESC("pcm", pcm), PINCTRL_FUNC_DESC("spi", spi), From 239fd71600c5a5ed27980a7d0275706c94eb28bd Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck Date: Fri, 7 Aug 2026 01:05:51 +0300 Subject: [PATCH 095/130] pinctrl: airoha: fix AN7583 MDIO pin mux config an7583_mdio_pins[] pointed at pins 43/44 (I2C1_SDA/I2C1_SCL) instead of pins 53/54 (MDC_0/MDIO_0 respectively GPIO 51/52). Also the MDIO function group wrote GPIO_SGMII_MDIO_MODE_MASK (bit 13 of REG_GPIO_PON_MODE, an unrelated SGMII MDIO mode) and GPIO_MDC_IO_MASTER_MODE_MODE (BIT(14), an EN7581 specific bit from REG_GPIO_2ND_I2C_MODE). Fix both by setting an7583_mdio_pins[] to { 53, 54 } and rewriting the function group to clear AN7583_MDC_0_GPIO_MODE_MASK (bit 25) and AN7583_MDIO_0_GPIO_MODE_MASK (bit 26) of REG_GPIO_PON_MODE. Both bits are cleared by the hwinit at probe. Signed-off-by: Daniel Schwierzeck Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/pinctrl-airoha.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c index 2288b1e911b4..16484e9f12a9 100644 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c @@ -724,7 +724,8 @@ static const int an7583_pon_tod_1pps_pins[] = { 32 }; static const int an7583_gsw_tod_1pps_pins[] = { 32 }; static const int an7583_sipo_pins[] = { 34, 35 }; static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 }; -static const int an7583_mdio_pins[] = { 43, 44 }; +static const int an7583_mdio_pins[] = { 53, 54 }; +static const int an7583_mdio1_pins[] = { 43, 44 }; static const int an7583_uart2_pins[] = { 34, 35 }; static const int an7583_uart2_cts_rts_pins[] = { 32, 33 }; static const int an7583_hsuart_pins[] = { 30, 31 }; @@ -809,6 +810,7 @@ static const struct pingroup an7583_pinctrl_groups[] = { PINCTRL_PIN_GROUP("sipo", an7583_sipo), PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk), PINCTRL_PIN_GROUP("mdio", an7583_mdio), + PINCTRL_PIN_GROUP("mdio1", an7583_mdio1), PINCTRL_PIN_GROUP("uart2", an7583_uart2), PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts), PINCTRL_PIN_GROUP("hsuart", an7583_hsuart), @@ -1081,16 +1083,10 @@ static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = { .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE, - GPIO_SGMII_MDIO_MODE_MASK, - GPIO_SGMII_MDIO_MODE_MASK + AN7583_MDC_0_GPIO_MODE_MASK | AN7583_MDIO_0_GPIO_MODE_MASK, + 0 }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - AN7583_GPIO_MDC_IO_MASTER_MODE_MASK, - AN7583_GPIO_MDC_IO_MASTER_MODE_MASK - }, - .regmap_size = 2, + .regmap_size = 1, }, }; From ccc41d25590645096bdbf420b43e7c22627b3f59 Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:05:52 +0300 Subject: [PATCH 096/130] pinctrl: airoha: an7583: fix spi group pins pcm pins were used insted of spi pins. This patch fixes an issue. Thanks to Daniel Schwierzeck for noticing it. Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs") Signed-off-by: Mikhail Kshevetskiy Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/pinctrl-airoha.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c index 16484e9f12a9..6f6822fce7aa 100644 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c @@ -739,7 +739,7 @@ static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 }; static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 }; static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 }; static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 }; -static const int an7583_spi_pins[] = { 28, 29, 30, 31 }; +static const int an7583_spi_pins[] = { 45, 46, 47, 48 }; static const int an7583_spi_quad_pins[] = { 25, 26 }; static const int an7583_spi_cs1_pins[] = { 27 }; static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 }; From d6392502a9e6b11c3a93eb4c987672a8c638d749 Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:05:53 +0300 Subject: [PATCH 097/130] pinctrl: airoha: add missed get_direction() function for gpio_chip This patch adds missed get_direction() function for gpio_chip. Also it reimplements pinconf's get_direction() function using newly defined function. Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC") Signed-off-by: Mikhail Kshevetskiy Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/pinctrl-airoha.c | 50 +++++++++++++++++-------- 1 file changed, 34 insertions(+), 16 deletions(-) diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c index 6f6822fce7aa..fe4a94fbd5ae 100644 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c @@ -2523,6 +2523,22 @@ static int airoha_gpio_get(struct gpio_chip *chip, unsigned int gpio) return err ? err : !!(val & BIT(pin)); } +static int airoha_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) +{ + struct airoha_pinctrl *pinctrl = gpiochip_get_data(chip); + u32 val, mask; + u8 index; + int err; + + index = gpio / AIROHA_REG_GPIOCTRL_NUM_PIN; + err = regmap_read(pinctrl->regmap, pinctrl->gpiochip.dir[index], &val); + if (err) + return err; + + mask = BIT(2 * (gpio % AIROHA_REG_GPIOCTRL_NUM_PIN)); + return val & mask ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; +} + static int airoha_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio, int value) { @@ -2656,19 +2672,13 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl, struct device *dev = &pdev->dev; int irq, err; - chip->data = gpio_data_regs; - chip->dir = gpio_dir_regs; - chip->out = gpio_out_regs; - chip->status = irq_status_regs; - chip->level = irq_level_regs; - chip->edge = irq_edge_regs; - gc->parent = dev; gc->label = dev_name(dev); gc->request = gpiochip_generic_request; gc->free = gpiochip_generic_free; gc->direction_input = pinctrl_gpio_direction_input; gc->direction_output = airoha_gpio_direction_output; + gc->get_direction = airoha_gpio_get_direction; gc->set = airoha_gpio_set; gc->get = airoha_gpio_get; gc->base = -1; @@ -2876,21 +2886,18 @@ static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl, static int airoha_pinconf_get_direction(struct pinctrl_dev *pctrl_dev, u32 p) { struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); - u32 val, mask; - int err, pin; - u8 index; + int ret, pin; pin = airoha_convert_pin_to_reg_offset(pctrl_dev, NULL, p); if (pin < 0) return pin; - index = pin / AIROHA_REG_GPIOCTRL_NUM_PIN; - err = regmap_read(pinctrl->regmap, pinctrl->gpiochip.dir[index], &val); - if (err) - return err; + ret = airoha_gpio_get_direction(&pinctrl->gpiochip.chip, pin); + if (ret < 0) + return ret; - mask = BIT(2 * (pin % AIROHA_REG_GPIOCTRL_NUM_PIN)); - return val & mask ? PIN_CONFIG_OUTPUT_ENABLE : PIN_CONFIG_INPUT_ENABLE; + return ret == GPIO_LINE_DIRECTION_OUT ? + PIN_CONFIG_OUTPUT_ENABLE : PIN_CONFIG_INPUT_ENABLE; } static int airoha_pinconf_get(struct pinctrl_dev *pctrl_dev, @@ -3136,6 +3143,17 @@ static int airoha_pinctrl_probe(struct platform_device *pdev) pinctrl->desc.pins = data->pins; pinctrl->desc.npins = data->num_pins; + /* + * some pinctrl operations (ex: get_direction) might use gpio registers + * before gpio chip abstraction will be completely initialized. + */ + pinctrl->gpiochip.data = gpio_data_regs; + pinctrl->gpiochip.dir = gpio_dir_regs; + pinctrl->gpiochip.out = gpio_out_regs; + pinctrl->gpiochip.status = irq_status_regs; + pinctrl->gpiochip.level = irq_level_regs; + pinctrl->gpiochip.edge = irq_edge_regs; + err = devm_pinctrl_register_and_init(dev, &pinctrl->desc, pinctrl, &pinctrl->ctrl); if (err) From 62b1dd7eeaca17dd57404a19df86a095d2419e08 Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:05:54 +0300 Subject: [PATCH 098/130] pinctrl: airoha: add set_direction() helper for gpio_chip The patch creates set_direction() helper for gpio_chip abstraction. It also implements/reimplements some function using newly defined helper. This is cosmetic patch used to place gpio_chip specific code together. No functional changes. Signed-off-by: Mikhail Kshevetskiy Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/pinctrl-airoha.c | 52 ++++++++++++++++--------- 1 file changed, 34 insertions(+), 18 deletions(-) diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c index fe4a94fbd5ae..11db612731df 100644 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c @@ -2539,12 +2539,42 @@ static int airoha_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) return val & mask ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; } +static int airoha_gpio_set_direction(struct gpio_chip *chip, unsigned int gpio, + bool input) +{ + struct airoha_pinctrl *pinctrl = gpiochip_get_data(chip); + u32 mask, index; + int err; + + /* set output enable */ + mask = BIT(gpio % AIROHA_PIN_BANK_SIZE); + index = gpio / AIROHA_PIN_BANK_SIZE; + err = regmap_update_bits(pinctrl->regmap, pinctrl->gpiochip.out[index], + mask, !input ? mask : 0); + if (err) + return err; + + /* set direction */ + mask = BIT(2 * (gpio % AIROHA_REG_GPIOCTRL_NUM_PIN)); + index = gpio / AIROHA_REG_GPIOCTRL_NUM_PIN; + + return regmap_update_bits(pinctrl->regmap, + pinctrl->gpiochip.dir[index], mask, + !input ? mask : 0); +} + +static int airoha_gpio_direction_input(struct gpio_chip *chip, + unsigned int gpio) +{ + return airoha_gpio_set_direction(chip, gpio, true); +} + static int airoha_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio, int value) { int err; - err = pinctrl_gpio_direction_output(chip, gpio); + err = airoha_gpio_set_direction(chip, gpio, false); if (err) return err; @@ -2676,7 +2706,7 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl, gc->label = dev_name(dev); gc->request = gpiochip_generic_request; gc->free = gpiochip_generic_free; - gc->direction_input = pinctrl_gpio_direction_input; + gc->direction_input = airoha_gpio_direction_input; gc->direction_output = airoha_gpio_direction_output; gc->get_direction = airoha_gpio_get_direction; gc->set = airoha_gpio_set; @@ -2759,27 +2789,13 @@ static int airoha_pinmux_set_direction(struct pinctrl_dev *pctrl_dev, unsigned int p, bool input) { struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); - u32 mask, index; - int err, pin; + int pin; pin = airoha_convert_pin_to_reg_offset(pctrl_dev, range, p); if (pin < 0) return pin; - /* set output enable */ - mask = BIT(pin % AIROHA_PIN_BANK_SIZE); - index = pin / AIROHA_PIN_BANK_SIZE; - err = regmap_update_bits(pinctrl->regmap, pinctrl->gpiochip.out[index], - mask, !input ? mask : 0); - if (err) - return err; - - /* set direction */ - mask = BIT(2 * (pin % AIROHA_REG_GPIOCTRL_NUM_PIN)); - index = pin / AIROHA_REG_GPIOCTRL_NUM_PIN; - return regmap_update_bits(pinctrl->regmap, - pinctrl->gpiochip.dir[index], mask, - !input ? mask : 0); + return airoha_gpio_set_direction(&pinctrl->gpiochip.chip, pin, input); } static const struct pinmux_ops airoha_pmxops = { From 0d3b5e7b84da3d25f824e205c3f4451df63e2be7 Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:05:55 +0300 Subject: [PATCH 099/130] pinctrl: airoha: minor improvements Changes: * use field_get() macro instead of direct bit operations * improve error handling Signed-off-by: Mikhail Kshevetskiy Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/pinctrl-airoha.c | 56 +++++++++++++++++++------ 1 file changed, 43 insertions(+), 13 deletions(-) diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c index 11db612731df..924ebe083106 100644 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c @@ -2840,7 +2840,7 @@ static int airoha_pinctrl_get_conf(struct airoha_pinctrl *pinctrl, if (regmap_read(pinctrl->chip_scu, reg->offset, val)) return -EINVAL; - *val = (*val & reg->mask) >> __ffs(reg->mask); + *val = field_get(reg->mask, *val); return 0; } @@ -2862,7 +2862,7 @@ static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl, if (regmap_update_bits(pinctrl->chip_scu, reg->offset, reg->mask, - val << __ffs(reg->mask))) + field_prep(reg->mask, val))) return -EINVAL; return 0; @@ -2994,7 +2994,7 @@ static int airoha_pinconf_set(struct pinctrl_dev *pctrl_dev, unsigned int num_configs) { struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); - int i; + int i, err; for (i = 0; i < num_configs; i++) { u32 param = pinconf_to_config_param(configs[i]); @@ -3002,16 +3002,35 @@ static int airoha_pinconf_set(struct pinctrl_dev *pctrl_dev, switch (param) { case PIN_CONFIG_BIAS_DISABLE: - airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 0); - airoha_pinctrl_set_pullup_conf(pinctrl, pin, 0); + err = airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 0); + if (err) + return err; + + err = airoha_pinctrl_set_pullup_conf(pinctrl, pin, 0); + if (err) + return err; + break; + case PIN_CONFIG_BIAS_PULL_UP: - airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 0); - airoha_pinctrl_set_pullup_conf(pinctrl, pin, 1); + err = airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 0); + if (err) + return err; + + err = airoha_pinctrl_set_pullup_conf(pinctrl, pin, 1); + if (err) + return err; + break; case PIN_CONFIG_BIAS_PULL_DOWN: - airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 1); - airoha_pinctrl_set_pullup_conf(pinctrl, pin, 0); + err = airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 1); + if (err) + return err; + + err = airoha_pinctrl_set_pullup_conf(pinctrl, pin, 0); + if (err) + return err; + break; case PIN_CONFIG_DRIVE_STRENGTH: { u32 e2 = 0, e4 = 0; @@ -3033,18 +3052,29 @@ static int airoha_pinconf_set(struct pinctrl_dev *pctrl_dev, return -EINVAL; } - airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, e2); - airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, e4); + err = airoha_pinctrl_set_drive_e2_conf(pinctrl, + pin, e2); + if (err) + return err; + + err = airoha_pinctrl_set_drive_e4_conf(pinctrl, + pin, e4); + if (err) + return err; + break; } case PIN_CONFIG_DRIVE_OPEN_DRAIN: - airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, !!arg); + err = airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, + pin, !!arg); + if (err) + return err; + break; case PIN_CONFIG_OUTPUT_ENABLE: case PIN_CONFIG_INPUT_ENABLE: case PIN_CONFIG_LEVEL: { bool input = param == PIN_CONFIG_INPUT_ENABLE; - int err; err = airoha_pinmux_set_direction(pctrl_dev, NULL, pin, input); From b8dd30554847bde27e8a4584dd447c1c3ac585ce Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:05:56 +0300 Subject: [PATCH 100/130] pinctrl: airoha: fix getting gpiochip/pinctrl pointers in the IRQ handling code airoha_irq_unmask(), airoha_irq_mask(), airoha_irq_type() functions impements brain damaged logic to retrieve gpiochip and pinctrl pointers. Details: gpiochip = irq_data_get_irq_chip_data(data); will initialize gpiochip variable with data->chip_data value. This value initialized inside gpiochip_irq_map() function static int gpiochip_irq_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) { struct gpio_chip *gc = d->host_data; ... irq_set_chip_data(irq, gc); ... } Thus gpiochip variable of 'struct airoha_pinctrl_gpiochip *' type will be initialized with a pointer to a variable of 'struct gpio_chip' type. Luckily, gpio_chip is the first element of airoha_pinctrl_gpiochip, so gpiochip pointer will get a correct value. This patch implements correct logic of getting gpiochip and pinctrl pointers. Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC") Signed-off-by: Mikhail Kshevetskiy Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/pinctrl-airoha.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c index 924ebe083106..0cadbc04cb58 100644 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c @@ -2584,18 +2584,17 @@ static int airoha_gpio_direction_output(struct gpio_chip *chip, /* irq callbacks */ static void airoha_irq_unmask(struct irq_data *data) { + struct gpio_chip *gc = irq_data_get_irq_chip_data(data); + struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc); + struct airoha_pinctrl_gpiochip *gpiochip = &pinctrl->gpiochip; u8 offset = data->hwirq % AIROHA_REG_GPIOCTRL_NUM_PIN; u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN; u32 mask = GENMASK(2 * offset + 1, 2 * offset); - struct airoha_pinctrl_gpiochip *gpiochip; - struct airoha_pinctrl *pinctrl; u32 val = BIT(2 * offset); - gpiochip = irq_data_get_irq_chip_data(data); if (WARN_ON_ONCE(data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))) return; - pinctrl = container_of(gpiochip, struct airoha_pinctrl, gpiochip); switch (gpiochip->irq_type[data->hwirq]) { case IRQ_TYPE_LEVEL_LOW: val = val << 1; @@ -2621,14 +2620,12 @@ static void airoha_irq_unmask(struct irq_data *data) static void airoha_irq_mask(struct irq_data *data) { + struct gpio_chip *gc = irq_data_get_irq_chip_data(data); + struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc); + struct airoha_pinctrl_gpiochip *gpiochip = &pinctrl->gpiochip; u8 offset = data->hwirq % AIROHA_REG_GPIOCTRL_NUM_PIN; u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN; u32 mask = GENMASK(2 * offset + 1, 2 * offset); - struct airoha_pinctrl_gpiochip *gpiochip; - struct airoha_pinctrl *pinctrl; - - gpiochip = irq_data_get_irq_chip_data(data); - pinctrl = container_of(gpiochip, struct airoha_pinctrl, gpiochip); regmap_clear_bits(pinctrl->regmap, gpiochip->level[index], mask); regmap_clear_bits(pinctrl->regmap, gpiochip->edge[index], mask); @@ -2636,9 +2633,10 @@ static void airoha_irq_mask(struct irq_data *data) static int airoha_irq_type(struct irq_data *data, unsigned int type) { - struct airoha_pinctrl_gpiochip *gpiochip; + struct gpio_chip *gc = irq_data_get_irq_chip_data(data); + struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc); + struct airoha_pinctrl_gpiochip *gpiochip = &pinctrl->gpiochip; - gpiochip = irq_data_get_irq_chip_data(data); if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type)) return -EINVAL; From a02fa031b9520e46e98bff17e12b472eba770670 Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:05:57 +0300 Subject: [PATCH 101/130] pinctrl: airoha: add missed IRQ resource helpers Without hooking .irq_request_resources, gpiolib cannot set GPIOD_FLAG_USED_AS_IRQ. This breaks pin direction locking and can allow userspace or another driver to reconfigure an active IRQ pin as an output Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC") Signed-off-by: Mikhail Kshevetskiy Acked-by: Lorenzo Bianconi Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/pinctrl-airoha.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c index 0cadbc04cb58..899299adfd57 100644 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c @@ -2689,6 +2689,7 @@ static const struct irq_chip airoha_gpio_irq_chip = { .irq_mask_ack = airoha_irq_mask, .irq_set_type = airoha_irq_type, .flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, }; static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl, From 20b996280640f492ebdd41c2d2c991801df75e61 Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:05:58 +0300 Subject: [PATCH 102/130] pinctrl: airoha: fix IRQ mask/unmask code When using IRQCHIP_IMMUTABLE, airoha_irq_unmask() must manually call gpiochip_enable_irq() and airoha_irq_mask() must call gpiochip_disable_irq(). Without these calls, gpiolib never sets the GPIOD_FLAG_IRQ_IS_ENABLED bit. Because this bit is missing, gpiod_direction_output() will not realize the pin is actively used as an interrupt. Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC") Signed-off-by: Mikhail Kshevetskiy Acked-by: Lorenzo Bianconi Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/pinctrl-airoha.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c index 899299adfd57..2e2870005bad 100644 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c @@ -2595,6 +2595,7 @@ static void airoha_irq_unmask(struct irq_data *data) if (WARN_ON_ONCE(data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))) return; + gpiochip_enable_irq(gc, irqd_to_hwirq(data)); switch (gpiochip->irq_type[data->hwirq]) { case IRQ_TYPE_LEVEL_LOW: val = val << 1; @@ -2629,6 +2630,7 @@ static void airoha_irq_mask(struct irq_data *data) regmap_clear_bits(pinctrl->regmap, gpiochip->level[index], mask); regmap_clear_bits(pinctrl->regmap, gpiochip->edge[index], mask); + gpiochip_disable_irq(gc, irqd_to_hwirq(data)); } static int airoha_irq_type(struct irq_data *data, unsigned int type) From 3de4686cdf0ccf6d78ca96ccaea621cbcf69fc3a Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:05:59 +0300 Subject: [PATCH 103/130] pinctrl: airoha: fix edge-triggered interrupts handling Edge-triggered interrupts are handled incorrectly because of * no irq_ack() handler was defined, * no handle_level_irq() handler was used, This patch probably fixes an issue Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC") Signed-off-by: Mikhail Kshevetskiy Acked-by: Lorenzo Bianconi Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/pinctrl-airoha.c | 37 ++++++++++++++++++++++--- 1 file changed, 33 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c index 2e2870005bad..7003359debaf 100644 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c @@ -2628,11 +2628,28 @@ static void airoha_irq_mask(struct irq_data *data) u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN; u32 mask = GENMASK(2 * offset + 1, 2 * offset); + if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type)) + return; + regmap_clear_bits(pinctrl->regmap, gpiochip->level[index], mask); regmap_clear_bits(pinctrl->regmap, gpiochip->edge[index], mask); gpiochip_disable_irq(gc, irqd_to_hwirq(data)); } +static void airoha_irq_ack(struct irq_data *data) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(data); + struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc); + struct airoha_pinctrl_gpiochip *gpiochip = &pinctrl->gpiochip; + u8 offset = data->hwirq % AIROHA_PIN_BANK_SIZE; + u8 index = data->hwirq / AIROHA_PIN_BANK_SIZE; + + if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type)) + return; + + regmap_write(pinctrl->regmap, gpiochip->status[index], BIT(offset)); +} + static int airoha_irq_type(struct irq_data *data, unsigned int type) { struct gpio_chip *gc = irq_data_get_irq_chip_data(data); @@ -2642,13 +2659,26 @@ static int airoha_irq_type(struct irq_data *data, unsigned int type) if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type)) return -EINVAL; + if (type == IRQ_TYPE_NONE) { + gpiochip->irq_type[data->hwirq] = IRQ_TYPE_NONE; + irq_set_handler_locked(data, handle_bad_irq); + + return 0; + } + if (type == IRQ_TYPE_PROBE) { if (gpiochip->irq_type[data->hwirq]) return 0; type = IRQ_TYPE_EDGE_BOTH; } + gpiochip->irq_type[data->hwirq] = type & IRQ_TYPE_SENSE_MASK; + if (type & IRQ_TYPE_EDGE_BOTH) + irq_set_handler_locked(data, handle_edge_irq); + else + irq_set_handler_locked(data, handle_level_irq); + return 0; } @@ -2673,8 +2703,7 @@ static irqreturn_t airoha_irq_handler(int irq, void *data) for_each_set_bit(irq, &status, AIROHA_PIN_BANK_SIZE) { u32 offset = irq + i * AIROHA_PIN_BANK_SIZE; - generic_handle_irq(irq_find_mapping(girq->domain, - offset)); + generic_handle_domain_irq(girq->domain, offset); regmap_write(pinctrl->regmap, pinctrl->gpiochip.status[i], BIT(irq)); } @@ -2688,7 +2717,7 @@ static const struct irq_chip airoha_gpio_irq_chip = { .name = "airoha-gpio-irq", .irq_unmask = airoha_irq_unmask, .irq_mask = airoha_irq_mask, - .irq_mask_ack = airoha_irq_mask, + .irq_ack = airoha_irq_ack, .irq_set_type = airoha_irq_type, .flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE, GPIOCHIP_IRQ_RESOURCE_HELPERS, @@ -2716,7 +2745,7 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl, gc->ngpio = AIROHA_NUM_PINS; girq->default_type = IRQ_TYPE_NONE; - girq->handler = handle_simple_irq; + girq->handler = handle_bad_irq; gpio_irq_chip_set_chip(girq, &airoha_gpio_irq_chip); irq = platform_get_irq(pdev, 0); From ad1a8fd4854953c5b0770b057f99de06183ad1ee Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:06:00 +0300 Subject: [PATCH 104/130] pinctrl: airoha: remove not needed irq_type[] array irq_type[] array inside airoha_pinctrl_gpiochip structure is not actually necessary. Use trigger type from 'struct irq_data' instead. Signed-off-by: Mikhail Kshevetskiy Acked-by: Lorenzo Bianconi Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/pinctrl-airoha.c | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c index 7003359debaf..5ac82dc7f955 100644 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c @@ -383,8 +383,6 @@ struct airoha_pinctrl_gpiochip { const u32 *status; const u32 *level; const u32 *edge; - - u32 irq_type[AIROHA_NUM_PINS]; }; struct airoha_pinctrl_confs_info { @@ -2592,11 +2590,11 @@ static void airoha_irq_unmask(struct irq_data *data) u32 mask = GENMASK(2 * offset + 1, 2 * offset); u32 val = BIT(2 * offset); - if (WARN_ON_ONCE(data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))) + if (WARN_ON_ONCE(data->hwirq >= AIROHA_NUM_PINS)) return; gpiochip_enable_irq(gc, irqd_to_hwirq(data)); - switch (gpiochip->irq_type[data->hwirq]) { + switch (irqd_get_trigger_type(data)) { case IRQ_TYPE_LEVEL_LOW: val = val << 1; fallthrough; @@ -2628,7 +2626,7 @@ static void airoha_irq_mask(struct irq_data *data) u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN; u32 mask = GENMASK(2 * offset + 1, 2 * offset); - if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type)) + if (data->hwirq >= AIROHA_NUM_PINS) return; regmap_clear_bits(pinctrl->regmap, gpiochip->level[index], mask); @@ -2644,7 +2642,7 @@ static void airoha_irq_ack(struct irq_data *data) u8 offset = data->hwirq % AIROHA_PIN_BANK_SIZE; u8 index = data->hwirq / AIROHA_PIN_BANK_SIZE; - if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type)) + if (data->hwirq >= AIROHA_NUM_PINS) return; regmap_write(pinctrl->regmap, gpiochip->status[index], BIT(offset)); @@ -2652,28 +2650,24 @@ static void airoha_irq_ack(struct irq_data *data) static int airoha_irq_type(struct irq_data *data, unsigned int type) { - struct gpio_chip *gc = irq_data_get_irq_chip_data(data); - struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc); - struct airoha_pinctrl_gpiochip *gpiochip = &pinctrl->gpiochip; - - if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type)) + if (data->hwirq >= AIROHA_NUM_PINS) return -EINVAL; if (type == IRQ_TYPE_NONE) { - gpiochip->irq_type[data->hwirq] = IRQ_TYPE_NONE; + irqd_set_trigger_type(data, type); irq_set_handler_locked(data, handle_bad_irq); return 0; } if (type == IRQ_TYPE_PROBE) { - if (gpiochip->irq_type[data->hwirq]) + if (irqd_get_trigger_type(data)) return 0; type = IRQ_TYPE_EDGE_BOTH; } - gpiochip->irq_type[data->hwirq] = type & IRQ_TYPE_SENSE_MASK; + irqd_set_trigger_type(data, type); if (type & IRQ_TYPE_EDGE_BOTH) irq_set_handler_locked(data, handle_edge_irq); else From e3a62553d40468f20ea1b87b5b97b7af8afbcf20 Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:06:01 +0300 Subject: [PATCH 105/130] pinctrl: airoha: statically allocate gpio regs structure just a small refactoring to collect all gpio register information in the one statically allocated structure. Signed-off-by: Mikhail Kshevetskiy Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/pinctrl-airoha.c | 92 ++++++++++++------------- 1 file changed, 46 insertions(+), 46 deletions(-) diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c index 5ac82dc7f955..165ba662dfc5 100644 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c @@ -303,6 +303,17 @@ #define AIROHA_PIN_BANK_SIZE (AIROHA_NUM_PINS / 2) #define AIROHA_REG_GPIOCTRL_NUM_PIN (AIROHA_NUM_PINS / 4) +struct airoha_gpiochip_regs { + /* gpio */ + const u32 *data; + const u32 *dir; + const u32 *out; + /* irq */ + const u32 *status; + const u32 *level; + const u32 *edge; +}; + static const u32 gpio_data_regs[] = { REG_GPIO_DATA, REG_GPIO_DATA1 @@ -339,6 +350,15 @@ static const u32 irq_edge_regs[] = { REG_GPIO_INT_EDGE3 }; +static struct airoha_gpiochip_regs airoha_gpiochip_regs = { + .data = gpio_data_regs, + .dir = gpio_dir_regs, + .out = gpio_out_regs, + .status = irq_status_regs, + .level = irq_level_regs, + .edge = irq_edge_regs, +}; + struct airoha_pinctrl_reg { u32 offset; u32 mask; @@ -372,19 +392,6 @@ struct airoha_pinctrl_conf { struct airoha_pinctrl_reg reg; }; -struct airoha_pinctrl_gpiochip { - struct gpio_chip chip; - - /* gpio */ - const u32 *data; - const u32 *dir; - const u32 *out; - /* irq */ - const u32 *status; - const u32 *level; - const u32 *edge; -}; - struct airoha_pinctrl_confs_info { const struct airoha_pinctrl_conf *confs; unsigned int num_confs; @@ -411,7 +418,8 @@ struct airoha_pinctrl { struct regmap *chip_scu; struct regmap *regmap; - struct airoha_pinctrl_gpiochip gpiochip; + struct gpio_chip gpiochip; + struct airoha_gpiochip_regs *gpio_regs; }; struct airoha_pinctrl_match_data { @@ -2504,7 +2512,7 @@ static int airoha_gpio_set(struct gpio_chip *chip, unsigned int gpio, u8 index = gpio / AIROHA_PIN_BANK_SIZE; return regmap_update_bits(pinctrl->regmap, - pinctrl->gpiochip.data[index], + pinctrl->gpio_regs->data[index], BIT(offset), value ? BIT(offset) : 0); } @@ -2516,7 +2524,7 @@ static int airoha_gpio_get(struct gpio_chip *chip, unsigned int gpio) int err; err = regmap_read(pinctrl->regmap, - pinctrl->gpiochip.data[index], &val); + pinctrl->gpio_regs->data[index], &val); return err ? err : !!(val & BIT(pin)); } @@ -2529,7 +2537,8 @@ static int airoha_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) int err; index = gpio / AIROHA_REG_GPIOCTRL_NUM_PIN; - err = regmap_read(pinctrl->regmap, pinctrl->gpiochip.dir[index], &val); + err = regmap_read(pinctrl->regmap, + pinctrl->gpio_regs->dir[index], &val); if (err) return err; @@ -2547,7 +2556,8 @@ static int airoha_gpio_set_direction(struct gpio_chip *chip, unsigned int gpio, /* set output enable */ mask = BIT(gpio % AIROHA_PIN_BANK_SIZE); index = gpio / AIROHA_PIN_BANK_SIZE; - err = regmap_update_bits(pinctrl->regmap, pinctrl->gpiochip.out[index], + err = regmap_update_bits(pinctrl->regmap, + pinctrl->gpio_regs->out[index], mask, !input ? mask : 0); if (err) return err; @@ -2557,7 +2567,7 @@ static int airoha_gpio_set_direction(struct gpio_chip *chip, unsigned int gpio, index = gpio / AIROHA_REG_GPIOCTRL_NUM_PIN; return regmap_update_bits(pinctrl->regmap, - pinctrl->gpiochip.dir[index], mask, + pinctrl->gpio_regs->dir[index], mask, !input ? mask : 0); } @@ -2584,7 +2594,7 @@ static void airoha_irq_unmask(struct irq_data *data) { struct gpio_chip *gc = irq_data_get_irq_chip_data(data); struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc); - struct airoha_pinctrl_gpiochip *gpiochip = &pinctrl->gpiochip; + struct airoha_gpiochip_regs *gpio_regs = pinctrl->gpio_regs; u8 offset = data->hwirq % AIROHA_REG_GPIOCTRL_NUM_PIN; u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN; u32 mask = GENMASK(2 * offset + 1, 2 * offset); @@ -2599,18 +2609,18 @@ static void airoha_irq_unmask(struct irq_data *data) val = val << 1; fallthrough; case IRQ_TYPE_LEVEL_HIGH: - regmap_update_bits(pinctrl->regmap, gpiochip->level[index], + regmap_update_bits(pinctrl->regmap, gpio_regs->level[index], mask, val); break; case IRQ_TYPE_EDGE_FALLING: val = val << 1; fallthrough; case IRQ_TYPE_EDGE_RISING: - regmap_update_bits(pinctrl->regmap, gpiochip->edge[index], + regmap_update_bits(pinctrl->regmap, gpio_regs->edge[index], mask, val); break; case IRQ_TYPE_EDGE_BOTH: - regmap_set_bits(pinctrl->regmap, gpiochip->edge[index], mask); + regmap_set_bits(pinctrl->regmap, gpio_regs->edge[index], mask); break; default: break; @@ -2621,7 +2631,7 @@ static void airoha_irq_mask(struct irq_data *data) { struct gpio_chip *gc = irq_data_get_irq_chip_data(data); struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc); - struct airoha_pinctrl_gpiochip *gpiochip = &pinctrl->gpiochip; + struct airoha_gpiochip_regs *gpio_regs = pinctrl->gpio_regs; u8 offset = data->hwirq % AIROHA_REG_GPIOCTRL_NUM_PIN; u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN; u32 mask = GENMASK(2 * offset + 1, 2 * offset); @@ -2629,8 +2639,8 @@ static void airoha_irq_mask(struct irq_data *data) if (data->hwirq >= AIROHA_NUM_PINS) return; - regmap_clear_bits(pinctrl->regmap, gpiochip->level[index], mask); - regmap_clear_bits(pinctrl->regmap, gpiochip->edge[index], mask); + regmap_clear_bits(pinctrl->regmap, gpio_regs->level[index], mask); + regmap_clear_bits(pinctrl->regmap, gpio_regs->edge[index], mask); gpiochip_disable_irq(gc, irqd_to_hwirq(data)); } @@ -2638,14 +2648,14 @@ static void airoha_irq_ack(struct irq_data *data) { struct gpio_chip *gc = irq_data_get_irq_chip_data(data); struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc); - struct airoha_pinctrl_gpiochip *gpiochip = &pinctrl->gpiochip; + struct airoha_gpiochip_regs *gpio_regs = pinctrl->gpio_regs; u8 offset = data->hwirq % AIROHA_PIN_BANK_SIZE; u8 index = data->hwirq / AIROHA_PIN_BANK_SIZE; if (data->hwirq >= AIROHA_NUM_PINS) return; - regmap_write(pinctrl->regmap, gpiochip->status[index], BIT(offset)); + regmap_write(pinctrl->regmap, gpio_regs->status[index], BIT(offset)); } static int airoha_irq_type(struct irq_data *data, unsigned int type) @@ -2684,12 +2694,12 @@ static irqreturn_t airoha_irq_handler(int irq, void *data) int i; for (i = 0; i < ARRAY_SIZE(irq_status_regs); i++) { - struct gpio_irq_chip *girq = &pinctrl->gpiochip.chip.irq; + struct gpio_irq_chip *girq = &pinctrl->gpiochip.irq; u32 regmap; unsigned long status; int irq; - if (regmap_read(pinctrl->regmap, pinctrl->gpiochip.status[i], + if (regmap_read(pinctrl->regmap, pinctrl->gpio_regs->status[i], ®map)) continue; @@ -2699,7 +2709,7 @@ static irqreturn_t airoha_irq_handler(int irq, void *data) generic_handle_domain_irq(girq->domain, offset); regmap_write(pinctrl->regmap, - pinctrl->gpiochip.status[i], BIT(irq)); + pinctrl->gpio_regs->status[i], BIT(irq)); } handled |= !!status; } @@ -2720,8 +2730,7 @@ static const struct irq_chip airoha_gpio_irq_chip = { static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl, struct platform_device *pdev) { - struct airoha_pinctrl_gpiochip *chip = &pinctrl->gpiochip; - struct gpio_chip *gc = &chip->chip; + struct gpio_chip *gc = &pinctrl->gpiochip; struct gpio_irq_chip *girq = &gc->irq; struct device *dev = &pdev->dev; int irq, err; @@ -2819,7 +2828,7 @@ static int airoha_pinmux_set_direction(struct pinctrl_dev *pctrl_dev, if (pin < 0) return pin; - return airoha_gpio_set_direction(&pinctrl->gpiochip.chip, pin, input); + return airoha_gpio_set_direction(&pinctrl->gpiochip, pin, input); } static const struct pinmux_ops airoha_pmxops = { @@ -2932,7 +2941,7 @@ static int airoha_pinconf_get_direction(struct pinctrl_dev *pctrl_dev, u32 p) if (pin < 0) return pin; - ret = airoha_gpio_get_direction(&pinctrl->gpiochip.chip, pin); + ret = airoha_gpio_get_direction(&pinctrl->gpiochip, pin); if (ret < 0) return ret; @@ -3010,7 +3019,7 @@ static int airoha_pinconf_set_pin_value(struct pinctrl_dev *pctrl_dev, if (pin < 0) return pin; - return airoha_gpio_set(&pinctrl->gpiochip.chip, pin, value); + return airoha_gpio_set(&pinctrl->gpiochip, pin, value); } static int airoha_pinconf_set(struct pinctrl_dev *pctrl_dev, @@ -3213,16 +3222,7 @@ static int airoha_pinctrl_probe(struct platform_device *pdev) pinctrl->desc.pins = data->pins; pinctrl->desc.npins = data->num_pins; - /* - * some pinctrl operations (ex: get_direction) might use gpio registers - * before gpio chip abstraction will be completely initialized. - */ - pinctrl->gpiochip.data = gpio_data_regs; - pinctrl->gpiochip.dir = gpio_dir_regs; - pinctrl->gpiochip.out = gpio_out_regs; - pinctrl->gpiochip.status = irq_status_regs; - pinctrl->gpiochip.level = irq_level_regs; - pinctrl->gpiochip.edge = irq_edge_regs; + pinctrl->gpio_regs = &airoha_gpiochip_regs; err = devm_pinctrl_register_and_init(dev, &pinctrl->desc, pinctrl, &pinctrl->ctrl); From 3f263f763699a38dac39cafe0e08e7d09a6ac48d Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:06:02 +0300 Subject: [PATCH 106/130] pinctrl: airoha: move common definitions to the separate header Let's move the SoC independent definitions and declarations of structures required for Airoha SoC-specific pinctrl drivers to a common header. Later we'll have several SoC-specific drivers, so this step is necessary. We will not move to the common header file other register addresses, register bitfields definitions and macroses that use SoC specific information. We will keep SoC specific definitions inside SoC specific files. No functional changes. Signed-off-by: Mikhail Kshevetskiy Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/airoha-common.h | 142 ++++++++ drivers/pinctrl/airoha/pinctrl-airoha.c | 411 ++++++++---------------- 2 files changed, 283 insertions(+), 270 deletions(-) create mode 100644 drivers/pinctrl/airoha/airoha-common.h diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoha/airoha-common.h new file mode 100644 index 000000000000..bffeea34c5a7 --- /dev/null +++ b/drivers/pinctrl/airoha/airoha-common.h @@ -0,0 +1,142 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Author: Lorenzo Bianconi + * Author: Benjamin Larsson + * Author: Markus Gothe + */ + +#ifndef __AIROHA_COMMON_HEADER__ +#define __AIROHA_COMMON_HEADER__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../core.h" +#include "../pinconf.h" +#include "../pinmux.h" + +#define AIROHA_NUM_PINS 64 +#define AIROHA_PIN_BANK_SIZE (AIROHA_NUM_PINS / 2) +#define AIROHA_REG_GPIOCTRL_NUM_PIN (AIROHA_NUM_PINS / 4) + +#define PINCTRL_PIN_GROUP(id, table) \ + PINCTRL_PINGROUP(id, table##_pins, ARRAY_SIZE(table##_pins)) + +#define PINCTRL_FUNC_DESC(id, table) \ + { \ + .desc = PINCTRL_PINFUNCTION(id, table##_groups, \ + ARRAY_SIZE(table##_groups)),\ + .groups = table##_func_group, \ + .group_size = ARRAY_SIZE(table##_func_group), \ + } + +#define PINCTRL_CONF_DESC(p, offset, mask) \ + { \ + .pin = p, \ + .reg = { offset, mask }, \ + } + +struct airoha_pinctrl_reg { + u32 offset; + u32 mask; +}; + +enum airoha_pinctrl_mux_func { + AIROHA_FUNC_MUX, + AIROHA_FUNC_PWM_MUX, + AIROHA_FUNC_PWM_EXT_MUX, +}; + +struct airoha_pinctrl_func_group { + const char *name; + struct { + enum airoha_pinctrl_mux_func mux; + u32 offset; + u32 mask; + u32 val; + } regmap[2]; + int regmap_size; +}; + +struct airoha_pinctrl_func { + const struct pinfunction desc; + const struct airoha_pinctrl_func_group *groups; + u8 group_size; +}; + +struct airoha_pinctrl_conf { + u32 pin; + struct airoha_pinctrl_reg reg; +}; + +struct airoha_gpiochip_regs { + /* gpio */ + const u32 *data; + const u32 *dir; + const u32 *out; + /* irq */ + const u32 *status; + const u32 *level; + const u32 *edge; +}; + +struct airoha_pinctrl_confs_info { + const struct airoha_pinctrl_conf *confs; + unsigned int num_confs; +}; + +enum airoha_pinctrl_confs_type { + AIROHA_PINCTRL_CONFS_PULLUP, + AIROHA_PINCTRL_CONFS_PULLDOWN, + AIROHA_PINCTRL_CONFS_DRIVE_E2, + AIROHA_PINCTRL_CONFS_DRIVE_E4, + AIROHA_PINCTRL_CONFS_PCIE_RST_OD, + + AIROHA_PINCTRL_CONFS_MAX, +}; + +struct airoha_pinctrl { + struct pinctrl_dev *ctrl; + + struct pinctrl_desc desc; + const struct pingroup *grps; + const struct airoha_pinctrl_func *funcs; + const struct airoha_pinctrl_confs_info *confs_info; + + struct regmap *chip_scu; + struct regmap *regmap; + + struct gpio_chip gpiochip; + struct airoha_gpiochip_regs *gpio_regs; +}; + +struct airoha_pinctrl_match_data { + const struct pinctrl_pin_desc *pins; + const unsigned int num_pins; + const struct pingroup *grps; + const unsigned int num_grps; + const struct airoha_pinctrl_func *funcs; + const unsigned int num_funcs; + const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX]; +}; + +#endif diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c index 165ba662dfc5..3df4b344068b 100644 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c @@ -5,47 +5,7 @@ * Author: Markus Gothe */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../core.h" -#include "../pinconf.h" -#include "../pinmux.h" - -#define PINCTRL_PIN_GROUP(id, table) \ - PINCTRL_PINGROUP(id, table##_pins, ARRAY_SIZE(table##_pins)) - -#define PINCTRL_FUNC_DESC(id, table) \ - { \ - .desc = PINCTRL_PINFUNCTION(id, table##_groups, \ - ARRAY_SIZE(table##_groups)),\ - .groups = table##_func_group, \ - .group_size = ARRAY_SIZE(table##_func_group), \ - } - -#define PINCTRL_CONF_DESC(p, offset, mask) \ - { \ - .pin = p, \ - .reg = { offset, mask }, \ - } +#include "airoha-common.h" /* MUX */ #define REG_GPIO_2ND_I2C_MODE 0x0214 @@ -231,6 +191,8 @@ #define REG_GPIO_INT_LEVEL 0x0010 #define REG_GPIO_OE 0x0014 #define REG_GPIO_CTRL1 0x0020 +#define REG_GPIO_CTRL2 0x0060 +#define REG_GPIO_CTRL3 0x0064 /* PWM MODE CONF */ #define REG_GPIO_FLASH_MODE_CFG 0x0034 @@ -251,9 +213,6 @@ #define GPIO1_FLASH_MODE_CFG BIT(1) #define GPIO0_FLASH_MODE_CFG BIT(0) -#define REG_GPIO_CTRL2 0x0060 -#define REG_GPIO_CTRL3 0x0064 - /* PWM MODE CONF EXT */ #define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068 #define GPIO51_FLASH_MODE_CFG BIT(31) @@ -299,20 +258,145 @@ #define REG_GPIO_INT_LEVEL2 0x0090 #define REG_GPIO_INT_LEVEL3 0x0094 -#define AIROHA_NUM_PINS 64 -#define AIROHA_PIN_BANK_SIZE (AIROHA_NUM_PINS / 2) -#define AIROHA_REG_GPIOCTRL_NUM_PIN (AIROHA_NUM_PINS / 4) +#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } -struct airoha_gpiochip_regs { - /* gpio */ - const u32 *data; - const u32 *dir; - const u32 *out; - /* irq */ - const u32 *status; - const u32 *level; - const u32 *edge; -}; +#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + 0 \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (smux_val), \ + (smux_val) \ + }, \ + .regmap_size = 2, \ + } + +/* PWM */ +#define AIROHA_PINCTRL_PWM(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_MUX, \ + REG_GPIO_FLASH_MODE_CFG, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (smux_val), \ + (smux_val) \ + }, \ + .regmap_size = 2, \ + } + +#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_2ND_I2C_MODE, \ + (mux_val), \ + (mux_val), \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_LAN_LED0_MAPPING, \ + (map_mask), \ + (map_val), \ + }, \ + .regmap_size = 2, \ + } + +#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_2ND_I2C_MODE, \ + (mux_val), \ + (mux_val), \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_LAN_LED1_MAPPING, \ + (map_mask), \ + (map_val), \ + }, \ + .regmap_size = 2, \ + } + +#define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val) \ + airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \ + (pin), (val)) +#define airoha_pinctrl_get_pulldown_conf(pinctrl, pin, val) \ + airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \ + (pin), (val)) +#define airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, val) \ + airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \ + (pin), (val)) +#define airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, val) \ + airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \ + (pin), (val)) +#define airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, val) \ + airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \ + (pin), (val)) +#define airoha_pinctrl_set_pullup_conf(pinctrl, pin, val) \ + airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \ + (pin), (val)) +#define airoha_pinctrl_set_pulldown_conf(pinctrl, pin, val) \ + airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \ + (pin), (val)) +#define airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, val) \ + airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \ + (pin), (val)) +#define airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, val) \ + airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \ + (pin), (val)) +#define airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, val) \ + airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \ + (pin), (val)) static const u32 gpio_data_regs[] = { REG_GPIO_DATA, @@ -359,79 +443,6 @@ static struct airoha_gpiochip_regs airoha_gpiochip_regs = { .edge = irq_edge_regs, }; -struct airoha_pinctrl_reg { - u32 offset; - u32 mask; -}; - -enum airoha_pinctrl_mux_func { - AIROHA_FUNC_MUX, - AIROHA_FUNC_PWM_MUX, - AIROHA_FUNC_PWM_EXT_MUX, -}; - -struct airoha_pinctrl_func_group { - const char *name; - struct { - enum airoha_pinctrl_mux_func mux; - u32 offset; - u32 mask; - u32 val; - } regmap[2]; - int regmap_size; -}; - -struct airoha_pinctrl_func { - const struct pinfunction desc; - const struct airoha_pinctrl_func_group *groups; - u8 group_size; -}; - -struct airoha_pinctrl_conf { - u32 pin; - struct airoha_pinctrl_reg reg; -}; - -struct airoha_pinctrl_confs_info { - const struct airoha_pinctrl_conf *confs; - unsigned int num_confs; -}; - -enum airoha_pinctrl_confs_type { - AIROHA_PINCTRL_CONFS_PULLUP, - AIROHA_PINCTRL_CONFS_PULLDOWN, - AIROHA_PINCTRL_CONFS_DRIVE_E2, - AIROHA_PINCTRL_CONFS_DRIVE_E4, - AIROHA_PINCTRL_CONFS_PCIE_RST_OD, - - AIROHA_PINCTRL_CONFS_MAX, -}; - -struct airoha_pinctrl { - struct pinctrl_dev *ctrl; - - struct pinctrl_desc desc; - const struct pingroup *grps; - const struct airoha_pinctrl_func *funcs; - const struct airoha_pinctrl_confs_info *confs_info; - - struct regmap *chip_scu; - struct regmap *regmap; - - struct gpio_chip gpiochip; - struct airoha_gpiochip_regs *gpio_regs; -}; - -struct airoha_pinctrl_match_data { - const struct pinctrl_pin_desc *pins; - const unsigned int num_pins; - const struct pingroup *grps; - const unsigned int num_grps; - const struct airoha_pinctrl_func *funcs; - const unsigned int num_funcs; - const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX]; -}; - static struct pinctrl_pin_desc en7581_pinctrl_pins[] = { PINCTRL_PIN(0, "uart1_txd"), PINCTRL_PIN(1, "uart1_rxd"), @@ -1465,36 +1476,6 @@ static const struct airoha_pinctrl_func_group pnand_func_group[] = { }, }; -#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \ - { \ - .name = (gpio), \ - .regmap[0] = { \ - AIROHA_FUNC_MUX, \ - REG_GPIO_PON_MODE, \ - (mux_val), \ - (mux_val) \ - }, \ - .regmap_size = 1, \ - } - -#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \ - { \ - .name = (gpio), \ - .regmap[0] = { \ - AIROHA_FUNC_PWM_EXT_MUX, \ - REG_GPIO_FLASH_MODE_CFG_EXT, \ - (mux_val), \ - 0 \ - }, \ - .regmap[1] = { \ - AIROHA_FUNC_MUX, \ - REG_GPIO_PON_MODE, \ - (smux_val), \ - (smux_val) \ - }, \ - .regmap_size = 2, \ - } - static const struct airoha_pinctrl_func_group gpio_func_group[] = { AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG, GPIO_PCIE_RESET0_MASK), @@ -1587,49 +1568,6 @@ static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = { }, }; -/* PWM */ -#define AIROHA_PINCTRL_PWM(gpio, mux_val) \ - { \ - .name = (gpio), \ - .regmap[0] = { \ - AIROHA_FUNC_PWM_MUX, \ - REG_GPIO_FLASH_MODE_CFG, \ - (mux_val), \ - (mux_val) \ - }, \ - .regmap_size = 1, \ - } \ - -#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \ - { \ - .name = (gpio), \ - .regmap[0] = { \ - AIROHA_FUNC_PWM_EXT_MUX, \ - REG_GPIO_FLASH_MODE_CFG_EXT, \ - (mux_val), \ - (mux_val) \ - }, \ - .regmap_size = 1, \ - } \ - -#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \ - { \ - .name = (gpio), \ - .regmap[0] = { \ - AIROHA_FUNC_PWM_EXT_MUX, \ - REG_GPIO_FLASH_MODE_CFG_EXT, \ - (mux_val), \ - (mux_val) \ - }, \ - .regmap[1] = { \ - AIROHA_FUNC_MUX, \ - REG_GPIO_PON_MODE, \ - (smux_val), \ - (smux_val) \ - }, \ - .regmap_size = 2, \ - } - static const struct airoha_pinctrl_func_group pwm_func_group[] = { AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), @@ -1746,42 +1684,6 @@ static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = { AN7583_MDC_0_GPIO_MODE_MASK), }; -#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ - { \ - .name = (gpio), \ - .regmap[0] = { \ - AIROHA_FUNC_MUX, \ - REG_GPIO_2ND_I2C_MODE, \ - (mux_val), \ - (mux_val), \ - }, \ - .regmap[1] = { \ - AIROHA_FUNC_MUX, \ - REG_LAN_LED0_MAPPING, \ - (map_mask), \ - (map_val), \ - }, \ - .regmap_size = 2, \ - } - -#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \ - { \ - .name = (gpio), \ - .regmap[0] = { \ - AIROHA_FUNC_MUX, \ - REG_GPIO_2ND_I2C_MODE, \ - (mux_val), \ - (mux_val), \ - }, \ - .regmap[1] = { \ - AIROHA_FUNC_MUX, \ - REG_LAN_LED1_MAPPING, \ - (map_mask), \ - (map_val), \ - }, \ - .regmap_size = 2, \ - } - static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = { AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), @@ -2901,37 +2803,6 @@ static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl, return 0; } -#define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val) \ - airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \ - (pin), (val)) -#define airoha_pinctrl_get_pulldown_conf(pinctrl, pin, val) \ - airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \ - (pin), (val)) -#define airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, val) \ - airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \ - (pin), (val)) -#define airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, val) \ - airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \ - (pin), (val)) -#define airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, val) \ - airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \ - (pin), (val)) -#define airoha_pinctrl_set_pullup_conf(pinctrl, pin, val) \ - airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \ - (pin), (val)) -#define airoha_pinctrl_set_pulldown_conf(pinctrl, pin, val) \ - airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \ - (pin), (val)) -#define airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, val) \ - airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \ - (pin), (val)) -#define airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, val) \ - airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \ - (pin), (val)) -#define airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, val) \ - airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \ - (pin), (val)) - static int airoha_pinconf_get_direction(struct pinctrl_dev *pctrl_dev, u32 p) { struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); From 900b49e603f267ecdd1e8d22b48a0eec5cc56775 Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:06:03 +0300 Subject: [PATCH 107/130] pinctrl: airoha: split driver on shared code and SoC specific drivers Split combined an7581/an7583 source file on a * shared pinctrl code (pinctrl-airoha.c) * an7581 specific pinctrl driver (pinctrl-an7581.c) * an7583 specific pinctrl driver (pinctrl-an7583.c) Ininialization code was adapted a bit to work properly for shared and SoC specific cases. Signed-off-by: Mikhail Kshevetskiy Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/Kconfig | 24 +- drivers/pinctrl/airoha/Makefile | 5 + drivers/pinctrl/airoha/airoha-common.h | 4 + drivers/pinctrl/airoha/pinctrl-airoha.c | 2378 +---------------------- drivers/pinctrl/airoha/pinctrl-an7581.c | 1486 ++++++++++++++ drivers/pinctrl/airoha/pinctrl-an7583.c | 1476 ++++++++++++++ 6 files changed, 2999 insertions(+), 2374 deletions(-) create mode 100644 drivers/pinctrl/airoha/pinctrl-an7581.c create mode 100644 drivers/pinctrl/airoha/pinctrl-an7583.c diff --git a/drivers/pinctrl/airoha/Kconfig b/drivers/pinctrl/airoha/Kconfig index 03adaeae8fc3..dae6608bc72d 100644 --- a/drivers/pinctrl/airoha/Kconfig +++ b/drivers/pinctrl/airoha/Kconfig @@ -3,9 +3,9 @@ menu "Airoha pinctrl drivers" depends on ARCH_AIROHA || COMPILE_TEST config PINCTRL_AIROHA - tristate "Airoha EN7581 pin control" + tristate "Airoha pin control" depends on OF - depends on ARM64 || COMPILE_TEST + depends on ARCH_AIROHA || COMPILE_TEST select PINMUX select GENERIC_PINCONF select GENERIC_PINCTRL_GROUPS @@ -13,8 +13,26 @@ config PINCTRL_AIROHA select GPIOLIB select GPIOLIB_IRQCHIP select REGMAP_MMIO + imply PINCTRL_AIROHA_AN7581 + imply PINCTRL_AIROHA_AN7583 + help + Shared pin controller and gpio driver code for different + Airoha SoCs. + +config PINCTRL_AIROHA_AN7581 + tristate "AN7581 pinctrl" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_AIROHA help Say yes here to support pin controller and gpio driver - on Airoha EN7581 SoC. + on Airoha AN7581, AN7566, AN7551 and other compatible SoCs. + +config PINCTRL_AIROHA_AN7583 + tristate "AN7583 pinctrl" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_AIROHA + help + Say yes here to support pin controller and gpio driver + on Airoha AN7583, AN7553, AN7567 and other compatible SoCs. endmenu diff --git a/drivers/pinctrl/airoha/Makefile b/drivers/pinctrl/airoha/Makefile index a25b744dd7a8..cfd68c45ae0f 100644 --- a/drivers/pinctrl/airoha/Makefile +++ b/drivers/pinctrl/airoha/Makefile @@ -1,3 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 +# shared code obj-$(CONFIG_PINCTRL_AIROHA) += pinctrl-airoha.o + +# SoC drivers +obj-$(CONFIG_PINCTRL_AIROHA_AN7581) += pinctrl-an7581.o +obj-$(CONFIG_PINCTRL_AIROHA_AN7583) += pinctrl-an7583.o diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoha/airoha-common.h index bffeea34c5a7..e6b60c8f9fa7 100644 --- a/drivers/pinctrl/airoha/airoha-common.h +++ b/drivers/pinctrl/airoha/airoha-common.h @@ -130,6 +130,8 @@ struct airoha_pinctrl { }; struct airoha_pinctrl_match_data { + const char *pinctrl_name; + struct module *pinctrl_owner; const struct pinctrl_pin_desc *pins; const unsigned int num_pins; const struct pingroup *grps; @@ -139,4 +141,6 @@ struct airoha_pinctrl_match_data { const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX]; }; +int airoha_pinctrl_probe(struct platform_device *pdev); + #endif diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c index 3df4b344068b..7f6c6279f7f8 100644 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c @@ -7,182 +7,6 @@ #include "airoha-common.h" -/* MUX */ -#define REG_GPIO_2ND_I2C_MODE 0x0214 -#define GPIO_MDC_IO_MASTER_MODE_MASK BIT(14) -#define GPIO_I2C_MASTER_MODE_MODE BIT(13) -#define GPIO_I2S_MODE_MASK BIT(12) -#define GPIO_I2C_SLAVE_MODE_MODE BIT(11) -#define GPIO_LAN3_LED1_MODE_MASK BIT(10) -#define GPIO_LAN3_LED0_MODE_MASK BIT(9) -#define GPIO_LAN2_LED1_MODE_MASK BIT(8) -#define GPIO_LAN2_LED0_MODE_MASK BIT(7) -#define GPIO_LAN1_LED1_MODE_MASK BIT(6) -#define GPIO_LAN1_LED0_MODE_MASK BIT(5) -#define GPIO_LAN0_LED1_MODE_MASK BIT(4) -#define GPIO_LAN0_LED0_MODE_MASK BIT(3) -#define PON_TOD_1PPS_MODE_MASK BIT(2) -#define GSW_TOD_1PPS_MODE_MASK BIT(1) -#define GPIO_2ND_I2C_MODE_MASK BIT(0) - -#define REG_GPIO_SPI_CS1_MODE 0x0218 -#define AN7583_GPIO_MDC_IO_MASTER_MODE_MASK BIT(22) -#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21) -#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20) -#define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19) -#define GPIO_PCM_SPI_CS2_MODE_P128_MASK BIT(18) -#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK BIT(18) -#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17) -#define GPIO_PCM_SPI_MODE_MASK BIT(16) -#define GPIO_PCM2_MODE_MASK BIT(13) -#define GPIO_PCM1_MODE_MASK BIT(12) -#define GPIO_PCM_INT_MODE_MASK BIT(9) -#define GPIO_PCM_RESET_MODE_MASK BIT(8) -#define GPIO_SPI_QUAD_MODE_MASK BIT(4) -#define GPIO_SPI_CS4_MODE_MASK BIT(3) -#define GPIO_SPI_CS3_MODE_MASK BIT(2) -#define GPIO_SPI_CS2_MODE_MASK BIT(1) -#define GPIO_SPI_CS1_MODE_MASK BIT(0) - -#define REG_GPIO_PON_MODE 0x021c -#define AN7583_MDIO_0_GPIO_MODE_MASK BIT(26) -#define AN7583_MDC_0_GPIO_MODE_MASK BIT(25) -#define AN7583_UART_RXD_GPIO_MODE_MASK BIT(24) -#define AN7583_UART_TXD_GPIO_MODE_MASK BIT(23) -#define AN7583_SPI_MISO_GPIO_MODE_MASK BIT(22) -#define AN7583_SPI_MOSI_GPIO_MODE_MASK BIT(21) -#define AN7583_SPI_CS_GPIO_MODE_MASK BIT(20) -#define AN7583_SPI_CLK_GPIO_MODE_MASK BIT(19) -#define AN7583_I2C1_SDA_GPIO_MODE_MASK BIT(18) -#define AN7583_I2C1_SCL_GPIO_MODE_MASK BIT(17) -#define AN7583_I2C0_SDA_GPIO_MODE_MASK BIT(16) -#define AN7583_I2C0_SCL_GPIO_MODE_MASK BIT(15) -#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14) -#define GPIO_SGMII_MDIO_MODE_MASK BIT(13) -#define GPIO_PCIE_RESET2_MASK BIT(12) -#define SIPO_RCLK_MODE_MASK BIT(11) -#define GPIO_PCIE_RESET1_MASK BIT(10) -#define GPIO_PCIE_RESET0_MASK BIT(9) -#define GPIO_UART5_MODE_MASK BIT(8) -#define GPIO_UART4_MODE_MASK BIT(7) -#define GPIO_HSUART_CTS_RTS_MODE_MASK BIT(6) -#define GPIO_HSUART_MODE_MASK BIT(5) -#define GPIO_UART2_CTS_RTS_MODE_MASK BIT(4) -#define GPIO_UART2_MODE_MASK BIT(3) -#define GPIO_SIPO_MODE_MASK BIT(2) -#define GPIO_EMMC_MODE_MASK BIT(1) -#define GPIO_PON_MODE_MASK BIT(0) - -#define REG_NPU_UART_EN 0x0224 -#define JTAG_UDI_EN_MASK BIT(4) -#define JTAG_DFD_EN_MASK BIT(3) - -#define REG_FORCE_GPIO_EN 0x0228 -#define FORCE_GPIO_EN(n) BIT(n) - -/* LED MAP */ -#define REG_LAN_LED0_MAPPING 0x027c -#define REG_LAN_LED1_MAPPING 0x0280 - -#define LAN4_LED_MAPPING_MASK GENMASK(18, 16) -#define LAN4_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n)) - -#define LAN3_LED_MAPPING_MASK GENMASK(14, 12) -#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n)) - -#define LAN2_LED_MAPPING_MASK GENMASK(10, 8) -#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n)) - -#define LAN1_LED_MAPPING_MASK GENMASK(6, 4) -#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n)) - -#define LAN0_LED_MAPPING_MASK GENMASK(2, 0) -#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n)) - -/* CONF */ -#define REG_I2C_SDA_E2 0x001c -#define AN7583_I2C1_SCL_E2_MASK BIT(16) -#define AN7583_I2C1_SDA_E2_MASK BIT(15) -#define SPI_MISO_E2_MASK BIT(14) -#define SPI_MOSI_E2_MASK BIT(13) -#define SPI_CLK_E2_MASK BIT(12) -#define SPI_CS0_E2_MASK BIT(11) -#define PCIE2_RESET_E2_MASK BIT(10) -#define PCIE1_RESET_E2_MASK BIT(9) -#define PCIE0_RESET_E2_MASK BIT(8) -#define AN7583_MDIO_0_E2_MASK BIT(5) -#define AN7583_MDC_0_E2_MASK BIT(4) -#define UART1_RXD_E2_MASK BIT(3) -#define UART1_TXD_E2_MASK BIT(2) -#define I2C_SCL_E2_MASK BIT(1) -#define I2C_SDA_E2_MASK BIT(0) - -#define REG_I2C_SDA_E4 0x0020 -#define AN7583_I2C1_SCL_E4_MASK BIT(16) -#define AN7583_I2C1_SDA_E4_MASK BIT(15) -#define SPI_MISO_E4_MASK BIT(14) -#define SPI_MOSI_E4_MASK BIT(13) -#define SPI_CLK_E4_MASK BIT(12) -#define SPI_CS0_E4_MASK BIT(11) -#define PCIE2_RESET_E4_MASK BIT(10) -#define PCIE1_RESET_E4_MASK BIT(9) -#define PCIE0_RESET_E4_MASK BIT(8) -#define AN7583_MDIO_0_E4_MASK BIT(5) -#define AN7583_MDC_0_E4_MASK BIT(4) -#define UART1_RXD_E4_MASK BIT(3) -#define UART1_TXD_E4_MASK BIT(2) -#define I2C_SCL_E4_MASK BIT(1) -#define I2C_SDA_E4_MASK BIT(0) - -#define REG_GPIO_L_E2 0x0024 -#define REG_GPIO_L_E4 0x0028 -#define REG_GPIO_H_E2 0x002c -#define REG_GPIO_H_E4 0x0030 - -#define REG_I2C_SDA_PU 0x0044 -#define AN7583_I2C1_SCL_PU_MASK BIT(16) -#define AN7583_I2C1_SDA_PU_MASK BIT(15) -#define SPI_MISO_PU_MASK BIT(14) -#define SPI_MOSI_PU_MASK BIT(13) -#define SPI_CLK_PU_MASK BIT(12) -#define SPI_CS0_PU_MASK BIT(11) -#define PCIE2_RESET_PU_MASK BIT(10) -#define PCIE1_RESET_PU_MASK BIT(9) -#define PCIE0_RESET_PU_MASK BIT(8) -#define AN7583_MDIO_0_PU_MASK BIT(5) -#define AN7583_MDC_0_PU_MASK BIT(4) -#define UART1_RXD_PU_MASK BIT(3) -#define UART1_TXD_PU_MASK BIT(2) -#define I2C_SCL_PU_MASK BIT(1) -#define I2C_SDA_PU_MASK BIT(0) - -#define REG_I2C_SDA_PD 0x0048 -#define AN7583_I2C1_SCL_PD_MASK BIT(16) -#define AN7583_I2C1_SDA_PD_MASK BIT(15) -#define SPI_MISO_PD_MASK BIT(14) -#define SPI_MOSI_PD_MASK BIT(13) -#define SPI_CLK_PD_MASK BIT(12) -#define SPI_CS0_PD_MASK BIT(11) -#define PCIE2_RESET_PD_MASK BIT(10) -#define PCIE1_RESET_PD_MASK BIT(9) -#define PCIE0_RESET_PD_MASK BIT(8) -#define AN7583_MDIO_0_PD_MASK BIT(5) -#define AN7583_MDC_0_PD_MASK BIT(4) -#define UART1_RXD_PD_MASK BIT(3) -#define UART1_TXD_PD_MASK BIT(2) -#define I2C_SCL_PD_MASK BIT(1) -#define I2C_SDA_PD_MASK BIT(0) - -#define REG_GPIO_L_PU 0x004c -#define REG_GPIO_L_PD 0x0050 -#define REG_GPIO_H_PU 0x0054 -#define REG_GPIO_H_PD 0x0058 - -#define REG_PCIE_RESET_OD 0x018c -#define PCIE2_RESET_OD_MASK BIT(2) -#define PCIE1_RESET_OD_MASK BIT(1) -#define PCIE0_RESET_OD_MASK BIT(0) - /* GPIOs */ #define REG_GPIO_CTRL 0x0000 #define REG_GPIO_DATA 0x0004 @@ -193,61 +17,6 @@ #define REG_GPIO_CTRL1 0x0020 #define REG_GPIO_CTRL2 0x0060 #define REG_GPIO_CTRL3 0x0064 - -/* PWM MODE CONF */ -#define REG_GPIO_FLASH_MODE_CFG 0x0034 -#define GPIO15_FLASH_MODE_CFG BIT(15) -#define GPIO14_FLASH_MODE_CFG BIT(14) -#define GPIO13_FLASH_MODE_CFG BIT(13) -#define GPIO12_FLASH_MODE_CFG BIT(12) -#define GPIO11_FLASH_MODE_CFG BIT(11) -#define GPIO10_FLASH_MODE_CFG BIT(10) -#define GPIO9_FLASH_MODE_CFG BIT(9) -#define GPIO8_FLASH_MODE_CFG BIT(8) -#define GPIO7_FLASH_MODE_CFG BIT(7) -#define GPIO6_FLASH_MODE_CFG BIT(6) -#define GPIO5_FLASH_MODE_CFG BIT(5) -#define GPIO4_FLASH_MODE_CFG BIT(4) -#define GPIO3_FLASH_MODE_CFG BIT(3) -#define GPIO2_FLASH_MODE_CFG BIT(2) -#define GPIO1_FLASH_MODE_CFG BIT(1) -#define GPIO0_FLASH_MODE_CFG BIT(0) - -/* PWM MODE CONF EXT */ -#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068 -#define GPIO51_FLASH_MODE_CFG BIT(31) -#define GPIO50_FLASH_MODE_CFG BIT(30) -#define GPIO49_FLASH_MODE_CFG BIT(29) -#define GPIO48_FLASH_MODE_CFG BIT(28) -#define GPIO47_FLASH_MODE_CFG BIT(27) -#define GPIO46_FLASH_MODE_CFG BIT(26) -#define GPIO45_FLASH_MODE_CFG BIT(25) -#define GPIO44_FLASH_MODE_CFG BIT(24) -#define GPIO43_FLASH_MODE_CFG BIT(23) -#define GPIO42_FLASH_MODE_CFG BIT(22) -#define GPIO41_FLASH_MODE_CFG BIT(21) -#define GPIO40_FLASH_MODE_CFG BIT(20) -#define GPIO39_FLASH_MODE_CFG BIT(19) -#define GPIO38_FLASH_MODE_CFG BIT(18) -#define GPIO37_FLASH_MODE_CFG BIT(17) -#define GPIO36_FLASH_MODE_CFG BIT(16) -#define GPIO31_FLASH_MODE_CFG BIT(15) -#define GPIO30_FLASH_MODE_CFG BIT(14) -#define GPIO29_FLASH_MODE_CFG BIT(13) -#define GPIO28_FLASH_MODE_CFG BIT(12) -#define GPIO27_FLASH_MODE_CFG BIT(11) -#define GPIO26_FLASH_MODE_CFG BIT(10) -#define GPIO25_FLASH_MODE_CFG BIT(9) -#define GPIO24_FLASH_MODE_CFG BIT(8) -#define GPIO23_FLASH_MODE_CFG BIT(7) -#define GPIO22_FLASH_MODE_CFG BIT(6) -#define GPIO21_FLASH_MODE_CFG BIT(5) -#define GPIO20_FLASH_MODE_CFG BIT(4) -#define GPIO19_FLASH_MODE_CFG BIT(3) -#define GPIO18_FLASH_MODE_CFG BIT(2) -#define GPIO17_FLASH_MODE_CFG BIT(1) -#define GPIO16_FLASH_MODE_CFG BIT(0) - #define REG_GPIO_DATA1 0x0070 #define REG_GPIO_OE1 0x0078 #define REG_GPIO_INT1 0x007c @@ -258,115 +27,6 @@ #define REG_GPIO_INT_LEVEL2 0x0090 #define REG_GPIO_INT_LEVEL3 0x0094 -#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \ - { \ - .name = (gpio), \ - .regmap[0] = { \ - AIROHA_FUNC_MUX, \ - REG_GPIO_PON_MODE, \ - (mux_val), \ - (mux_val) \ - }, \ - .regmap_size = 1, \ - } - -#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \ - { \ - .name = (gpio), \ - .regmap[0] = { \ - AIROHA_FUNC_PWM_EXT_MUX, \ - REG_GPIO_FLASH_MODE_CFG_EXT, \ - (mux_val), \ - 0 \ - }, \ - .regmap[1] = { \ - AIROHA_FUNC_MUX, \ - REG_GPIO_PON_MODE, \ - (smux_val), \ - (smux_val) \ - }, \ - .regmap_size = 2, \ - } - -/* PWM */ -#define AIROHA_PINCTRL_PWM(gpio, mux_val) \ - { \ - .name = (gpio), \ - .regmap[0] = { \ - AIROHA_FUNC_PWM_MUX, \ - REG_GPIO_FLASH_MODE_CFG, \ - (mux_val), \ - (mux_val) \ - }, \ - .regmap_size = 1, \ - } - -#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \ - { \ - .name = (gpio), \ - .regmap[0] = { \ - AIROHA_FUNC_PWM_EXT_MUX, \ - REG_GPIO_FLASH_MODE_CFG_EXT, \ - (mux_val), \ - (mux_val) \ - }, \ - .regmap_size = 1, \ - } - -#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \ - { \ - .name = (gpio), \ - .regmap[0] = { \ - AIROHA_FUNC_PWM_EXT_MUX, \ - REG_GPIO_FLASH_MODE_CFG_EXT, \ - (mux_val), \ - (mux_val) \ - }, \ - .regmap[1] = { \ - AIROHA_FUNC_MUX, \ - REG_GPIO_PON_MODE, \ - (smux_val), \ - (smux_val) \ - }, \ - .regmap_size = 2, \ - } - -#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ - { \ - .name = (gpio), \ - .regmap[0] = { \ - AIROHA_FUNC_MUX, \ - REG_GPIO_2ND_I2C_MODE, \ - (mux_val), \ - (mux_val), \ - }, \ - .regmap[1] = { \ - AIROHA_FUNC_MUX, \ - REG_LAN_LED0_MAPPING, \ - (map_mask), \ - (map_val), \ - }, \ - .regmap_size = 2, \ - } - -#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \ - { \ - .name = (gpio), \ - .regmap[0] = { \ - AIROHA_FUNC_MUX, \ - REG_GPIO_2ND_I2C_MODE, \ - (mux_val), \ - (mux_val), \ - }, \ - .regmap[1] = { \ - AIROHA_FUNC_MUX, \ - REG_LAN_LED1_MAPPING, \ - (map_mask), \ - (map_val), \ - }, \ - .regmap_size = 2, \ - } - #define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val) \ airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \ (pin), (val)) @@ -443,1955 +103,6 @@ static struct airoha_gpiochip_regs airoha_gpiochip_regs = { .edge = irq_edge_regs, }; -static struct pinctrl_pin_desc en7581_pinctrl_pins[] = { - PINCTRL_PIN(0, "uart1_txd"), - PINCTRL_PIN(1, "uart1_rxd"), - PINCTRL_PIN(2, "i2c_scl"), - PINCTRL_PIN(3, "i2c_sda"), - PINCTRL_PIN(4, "spi_cs0"), - PINCTRL_PIN(5, "spi_clk"), - PINCTRL_PIN(6, "spi_mosi"), - PINCTRL_PIN(7, "spi_miso"), - PINCTRL_PIN(13, "gpio0"), - PINCTRL_PIN(14, "gpio1"), - PINCTRL_PIN(15, "gpio2"), - PINCTRL_PIN(16, "gpio3"), - PINCTRL_PIN(17, "gpio4"), - PINCTRL_PIN(18, "gpio5"), - PINCTRL_PIN(19, "gpio6"), - PINCTRL_PIN(20, "gpio7"), - PINCTRL_PIN(21, "gpio8"), - PINCTRL_PIN(22, "gpio9"), - PINCTRL_PIN(23, "gpio10"), - PINCTRL_PIN(24, "gpio11"), - PINCTRL_PIN(25, "gpio12"), - PINCTRL_PIN(26, "gpio13"), - PINCTRL_PIN(27, "gpio14"), - PINCTRL_PIN(28, "gpio15"), - PINCTRL_PIN(29, "gpio16"), - PINCTRL_PIN(30, "gpio17"), - PINCTRL_PIN(31, "gpio18"), - PINCTRL_PIN(32, "gpio19"), - PINCTRL_PIN(33, "gpio20"), - PINCTRL_PIN(34, "gpio21"), - PINCTRL_PIN(35, "gpio22"), - PINCTRL_PIN(36, "gpio23"), - PINCTRL_PIN(37, "gpio24"), - PINCTRL_PIN(38, "gpio25"), - PINCTRL_PIN(39, "gpio26"), - PINCTRL_PIN(40, "gpio27"), - PINCTRL_PIN(41, "gpio28"), - PINCTRL_PIN(42, "gpio29"), - PINCTRL_PIN(43, "gpio30"), - PINCTRL_PIN(44, "gpio31"), - PINCTRL_PIN(45, "gpio32"), - PINCTRL_PIN(46, "gpio33"), - PINCTRL_PIN(47, "gpio34"), - PINCTRL_PIN(48, "gpio35"), - PINCTRL_PIN(49, "gpio36"), - PINCTRL_PIN(50, "gpio37"), - PINCTRL_PIN(51, "gpio38"), - PINCTRL_PIN(52, "gpio39"), - PINCTRL_PIN(53, "gpio40"), - PINCTRL_PIN(54, "gpio41"), - PINCTRL_PIN(55, "gpio42"), - PINCTRL_PIN(56, "gpio43"), - PINCTRL_PIN(57, "gpio44"), - PINCTRL_PIN(58, "gpio45"), - PINCTRL_PIN(59, "gpio46"), - PINCTRL_PIN(60, "pcie_reset0"), - PINCTRL_PIN(61, "pcie_reset1"), - PINCTRL_PIN(62, "pcie_reset2"), -}; - -static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 }; -static const int en7581_pon_tod_1pps_pins[] = { 46 }; -static const int en7581_gsw_tod_1pps_pins[] = { 46 }; -static const int en7581_sipo_pins[] = { 16, 17 }; -static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 }; -static const int en7581_mdio_pins[] = { 14, 15 }; -static const int en7581_uart2_pins[] = { 48, 55 }; -static const int en7581_uart2_cts_rts_pins[] = { 46, 47 }; -static const int en7581_hsuart_pins[] = { 28, 29 }; -static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 }; -static const int en7581_uart4_pins[] = { 38, 39 }; -static const int en7581_uart5_pins[] = { 18, 19 }; -static const int en7581_i2c0_pins[] = { 2, 3 }; -static const int en7581_i2c1_pins[] = { 14, 15 }; -static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 }; -static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 }; -static const int en7581_i2s_pins[] = { 26, 27, 28, 29 }; -static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 }; -static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 }; -static const int en7581_spi_quad_pins[] = { 32, 33 }; -static const int en7581_spi_pins[] = { 4, 5, 6, 7 }; -static const int en7581_spi_cs1_pins[] = { 34 }; -static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 }; -static const int en7581_pcm_spi_int_pins[] = { 14 }; -static const int en7581_pcm_spi_rst_pins[] = { 15 }; -static const int en7581_pcm_spi_cs1_pins[] = { 43 }; -static const int en7581_pcm_spi_cs2_pins[] = { 40 }; -static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 }; -static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 }; -static const int en7581_pcm_spi_cs3_pins[] = { 41 }; -static const int en7581_pcm_spi_cs4_pins[] = { 42 }; -static const int en7581_emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 }; -static const int en7581_pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 }; -static const int en7581_gpio0_pins[] = { 13 }; -static const int en7581_gpio1_pins[] = { 14 }; -static const int en7581_gpio2_pins[] = { 15 }; -static const int en7581_gpio3_pins[] = { 16 }; -static const int en7581_gpio4_pins[] = { 17 }; -static const int en7581_gpio5_pins[] = { 18 }; -static const int en7581_gpio6_pins[] = { 19 }; -static const int en7581_gpio7_pins[] = { 20 }; -static const int en7581_gpio8_pins[] = { 21 }; -static const int en7581_gpio9_pins[] = { 22 }; -static const int en7581_gpio10_pins[] = { 23 }; -static const int en7581_gpio11_pins[] = { 24 }; -static const int en7581_gpio12_pins[] = { 25 }; -static const int en7581_gpio13_pins[] = { 26 }; -static const int en7581_gpio14_pins[] = { 27 }; -static const int en7581_gpio15_pins[] = { 28 }; -static const int en7581_gpio16_pins[] = { 29 }; -static const int en7581_gpio17_pins[] = { 30 }; -static const int en7581_gpio18_pins[] = { 31 }; -static const int en7581_gpio19_pins[] = { 32 }; -static const int en7581_gpio20_pins[] = { 33 }; -static const int en7581_gpio21_pins[] = { 34 }; -static const int en7581_gpio22_pins[] = { 35 }; -static const int en7581_gpio23_pins[] = { 36 }; -static const int en7581_gpio24_pins[] = { 37 }; -static const int en7581_gpio25_pins[] = { 38 }; -static const int en7581_gpio26_pins[] = { 39 }; -static const int en7581_gpio27_pins[] = { 40 }; -static const int en7581_gpio28_pins[] = { 41 }; -static const int en7581_gpio29_pins[] = { 42 }; -static const int en7581_gpio30_pins[] = { 43 }; -static const int en7581_gpio31_pins[] = { 44 }; -static const int en7581_gpio32_pins[] = { 45 }; -static const int en7581_gpio33_pins[] = { 46 }; -static const int en7581_gpio34_pins[] = { 47 }; -static const int en7581_gpio35_pins[] = { 48 }; -static const int en7581_gpio36_pins[] = { 49 }; -static const int en7581_gpio37_pins[] = { 50 }; -static const int en7581_gpio38_pins[] = { 51 }; -static const int en7581_gpio39_pins[] = { 52 }; -static const int en7581_gpio40_pins[] = { 53 }; -static const int en7581_gpio41_pins[] = { 54 }; -static const int en7581_gpio42_pins[] = { 55 }; -static const int en7581_gpio43_pins[] = { 56 }; -static const int en7581_gpio44_pins[] = { 57 }; -static const int en7581_gpio45_pins[] = { 58 }; -static const int en7581_gpio46_pins[] = { 59 }; -static const int en7581_gpio47_pins[] = { 60 }; -static const int en7581_gpio48_pins[] = { 61 }; -static const int en7581_gpio49_pins[] = { 62 }; -static const int en7581_pcie_reset0_pins[] = { 60 }; -static const int en7581_pcie_reset1_pins[] = { 61 }; -static const int en7581_pcie_reset2_pins[] = { 62 }; - -static const struct pingroup en7581_pinctrl_groups[] = { - PINCTRL_PIN_GROUP("pon", en7581_pon), - PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps), - PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps), - PINCTRL_PIN_GROUP("sipo", en7581_sipo), - PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk), - PINCTRL_PIN_GROUP("mdio", en7581_mdio), - PINCTRL_PIN_GROUP("uart2", en7581_uart2), - PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts), - PINCTRL_PIN_GROUP("hsuart", en7581_hsuart), - PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts), - PINCTRL_PIN_GROUP("uart4", en7581_uart4), - PINCTRL_PIN_GROUP("uart5", en7581_uart5), - PINCTRL_PIN_GROUP("i2c0", en7581_i2c0), - PINCTRL_PIN_GROUP("i2c1", en7581_i2c1), - PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi), - PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd), - PINCTRL_PIN_GROUP("i2s", en7581_i2s), - PINCTRL_PIN_GROUP("pcm1", en7581_pcm1), - PINCTRL_PIN_GROUP("pcm2", en7581_pcm2), - PINCTRL_PIN_GROUP("spi", en7581_spi), - PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad), - PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1), - PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi), - PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int), - PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst), - PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1), - PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128), - PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156), - PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2), - PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3), - PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4), - PINCTRL_PIN_GROUP("emmc", en7581_emmc), - PINCTRL_PIN_GROUP("pnand", en7581_pnand), - PINCTRL_PIN_GROUP("gpio0", en7581_gpio0), - PINCTRL_PIN_GROUP("gpio1", en7581_gpio1), - PINCTRL_PIN_GROUP("gpio2", en7581_gpio2), - PINCTRL_PIN_GROUP("gpio3", en7581_gpio3), - PINCTRL_PIN_GROUP("gpio4", en7581_gpio4), - PINCTRL_PIN_GROUP("gpio5", en7581_gpio5), - PINCTRL_PIN_GROUP("gpio6", en7581_gpio6), - PINCTRL_PIN_GROUP("gpio7", en7581_gpio7), - PINCTRL_PIN_GROUP("gpio8", en7581_gpio8), - PINCTRL_PIN_GROUP("gpio9", en7581_gpio9), - PINCTRL_PIN_GROUP("gpio10", en7581_gpio10), - PINCTRL_PIN_GROUP("gpio11", en7581_gpio11), - PINCTRL_PIN_GROUP("gpio12", en7581_gpio12), - PINCTRL_PIN_GROUP("gpio13", en7581_gpio13), - PINCTRL_PIN_GROUP("gpio14", en7581_gpio14), - PINCTRL_PIN_GROUP("gpio15", en7581_gpio15), - PINCTRL_PIN_GROUP("gpio16", en7581_gpio16), - PINCTRL_PIN_GROUP("gpio17", en7581_gpio17), - PINCTRL_PIN_GROUP("gpio18", en7581_gpio18), - PINCTRL_PIN_GROUP("gpio19", en7581_gpio19), - PINCTRL_PIN_GROUP("gpio20", en7581_gpio20), - PINCTRL_PIN_GROUP("gpio21", en7581_gpio21), - PINCTRL_PIN_GROUP("gpio22", en7581_gpio22), - PINCTRL_PIN_GROUP("gpio23", en7581_gpio23), - PINCTRL_PIN_GROUP("gpio24", en7581_gpio24), - PINCTRL_PIN_GROUP("gpio25", en7581_gpio25), - PINCTRL_PIN_GROUP("gpio26", en7581_gpio26), - PINCTRL_PIN_GROUP("gpio27", en7581_gpio27), - PINCTRL_PIN_GROUP("gpio28", en7581_gpio28), - PINCTRL_PIN_GROUP("gpio29", en7581_gpio29), - PINCTRL_PIN_GROUP("gpio30", en7581_gpio30), - PINCTRL_PIN_GROUP("gpio31", en7581_gpio31), - PINCTRL_PIN_GROUP("gpio32", en7581_gpio32), - PINCTRL_PIN_GROUP("gpio33", en7581_gpio33), - PINCTRL_PIN_GROUP("gpio34", en7581_gpio34), - PINCTRL_PIN_GROUP("gpio35", en7581_gpio35), - PINCTRL_PIN_GROUP("gpio36", en7581_gpio36), - PINCTRL_PIN_GROUP("gpio37", en7581_gpio37), - PINCTRL_PIN_GROUP("gpio38", en7581_gpio38), - PINCTRL_PIN_GROUP("gpio39", en7581_gpio39), - PINCTRL_PIN_GROUP("gpio40", en7581_gpio40), - PINCTRL_PIN_GROUP("gpio41", en7581_gpio41), - PINCTRL_PIN_GROUP("gpio42", en7581_gpio42), - PINCTRL_PIN_GROUP("gpio43", en7581_gpio43), - PINCTRL_PIN_GROUP("gpio44", en7581_gpio44), - PINCTRL_PIN_GROUP("gpio45", en7581_gpio45), - PINCTRL_PIN_GROUP("gpio46", en7581_gpio46), - PINCTRL_PIN_GROUP("gpio47", en7581_gpio47), - PINCTRL_PIN_GROUP("gpio48", en7581_gpio48), - PINCTRL_PIN_GROUP("gpio49", en7581_gpio49), - PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0), - PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1), - PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2), -}; - -static struct pinctrl_pin_desc an7583_pinctrl_pins[] = { - PINCTRL_PIN(2, "gpio0"), - PINCTRL_PIN(3, "gpio1"), - PINCTRL_PIN(4, "gpio2"), - PINCTRL_PIN(5, "gpio3"), - PINCTRL_PIN(6, "gpio4"), - PINCTRL_PIN(7, "gpio5"), - PINCTRL_PIN(8, "gpio6"), - PINCTRL_PIN(9, "gpio7"), - PINCTRL_PIN(10, "gpio8"), - PINCTRL_PIN(11, "gpio9"), - PINCTRL_PIN(12, "gpio10"), - PINCTRL_PIN(13, "gpio11"), - PINCTRL_PIN(14, "gpio12"), - PINCTRL_PIN(15, "gpio13"), - PINCTRL_PIN(16, "gpio14"), - PINCTRL_PIN(17, "gpio15"), - PINCTRL_PIN(18, "gpio16"), - PINCTRL_PIN(19, "gpio17"), - PINCTRL_PIN(20, "gpio18"), - PINCTRL_PIN(21, "gpio19"), - PINCTRL_PIN(22, "gpio20"), - PINCTRL_PIN(23, "gpio21"), - PINCTRL_PIN(24, "gpio22"), - PINCTRL_PIN(25, "gpio23"), - PINCTRL_PIN(26, "gpio24"), - PINCTRL_PIN(27, "gpio25"), - PINCTRL_PIN(28, "gpio26"), - PINCTRL_PIN(29, "gpio27"), - PINCTRL_PIN(30, "gpio28"), - PINCTRL_PIN(31, "gpio29"), - PINCTRL_PIN(32, "gpio30"), - PINCTRL_PIN(33, "gpio31"), - PINCTRL_PIN(34, "gpio32"), - PINCTRL_PIN(35, "gpio33"), - PINCTRL_PIN(36, "gpio34"), - PINCTRL_PIN(37, "gpio35"), - PINCTRL_PIN(38, "gpio36"), - PINCTRL_PIN(39, "gpio37"), - PINCTRL_PIN(40, "gpio38"), - PINCTRL_PIN(41, "i2c0_scl"), - PINCTRL_PIN(42, "i2c0_sda"), - PINCTRL_PIN(43, "i2c1_scl"), - PINCTRL_PIN(44, "i2c1_sda"), - PINCTRL_PIN(45, "spi_clk"), - PINCTRL_PIN(46, "spi_cs"), - PINCTRL_PIN(47, "spi_mosi"), - PINCTRL_PIN(48, "spi_miso"), - PINCTRL_PIN(49, "uart_txd"), - PINCTRL_PIN(50, "uart_rxd"), - PINCTRL_PIN(51, "pcie_reset0"), - PINCTRL_PIN(52, "pcie_reset1"), - PINCTRL_PIN(53, "mdc_0"), - PINCTRL_PIN(54, "mdio_0"), -}; - -static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 }; -static const int an7583_pon_tod_1pps_pins[] = { 32 }; -static const int an7583_gsw_tod_1pps_pins[] = { 32 }; -static const int an7583_sipo_pins[] = { 34, 35 }; -static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 }; -static const int an7583_mdio_pins[] = { 53, 54 }; -static const int an7583_mdio1_pins[] = { 43, 44 }; -static const int an7583_uart2_pins[] = { 34, 35 }; -static const int an7583_uart2_cts_rts_pins[] = { 32, 33 }; -static const int an7583_hsuart_pins[] = { 30, 31 }; -static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 }; -static const int an7583_npu_uart_pins[] = { 7, 8 }; -static const int an7583_uart4_pins[] = { 7, 8 }; -static const int an7583_uart5_pins[] = { 23, 24 }; -static const int an7583_i2c0_pins[] = { 41, 42 }; -static const int an7583_i2c1_pins[] = { 43, 44 }; -static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 }; -static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 }; -static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 }; -static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 }; -static const int an7583_spi_pins[] = { 45, 46, 47, 48 }; -static const int an7583_spi_quad_pins[] = { 25, 26 }; -static const int an7583_spi_cs1_pins[] = { 27 }; -static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 }; -static const int an7583_pcm_spi_rst_pins[] = { 14 }; -static const int an7583_pcm_spi_cs1_pins[] = { 24 }; -static const int an7583_emmc_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47 }; -static const int an7583_pnand_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48 }; -static const int an7583_gpio0_pins[] = { 2 }; -static const int an7583_gpio1_pins[] = { 3 }; -static const int an7583_gpio2_pins[] = { 4 }; -static const int an7583_gpio3_pins[] = { 5 }; -static const int an7583_gpio4_pins[] = { 6 }; -static const int an7583_gpio5_pins[] = { 7 }; -static const int an7583_gpio6_pins[] = { 8 }; -static const int an7583_gpio7_pins[] = { 9 }; -static const int an7583_gpio8_pins[] = { 10 }; -static const int an7583_gpio9_pins[] = { 11 }; -static const int an7583_gpio10_pins[] = { 12 }; -static const int an7583_gpio11_pins[] = { 13 }; -static const int an7583_gpio12_pins[] = { 14 }; -static const int an7583_gpio13_pins[] = { 15 }; -static const int an7583_gpio14_pins[] = { 16 }; -static const int an7583_gpio15_pins[] = { 17 }; -static const int an7583_gpio16_pins[] = { 18 }; -static const int an7583_gpio17_pins[] = { 19 }; -static const int an7583_gpio18_pins[] = { 20 }; -static const int an7583_gpio19_pins[] = { 21 }; -static const int an7583_gpio20_pins[] = { 22 }; -static const int an7583_gpio21_pins[] = { 23 }; -static const int an7583_gpio22_pins[] = { 24 }; -static const int an7583_gpio23_pins[] = { 25 }; -static const int an7583_gpio24_pins[] = { 26 }; -static const int an7583_gpio25_pins[] = { 27 }; -static const int an7583_gpio26_pins[] = { 28 }; -static const int an7583_gpio27_pins[] = { 29 }; -static const int an7583_gpio28_pins[] = { 30 }; -static const int an7583_gpio29_pins[] = { 31 }; -static const int an7583_gpio30_pins[] = { 32 }; -static const int an7583_gpio31_pins[] = { 33 }; -static const int an7583_gpio32_pins[] = { 34 }; -static const int an7583_gpio33_pins[] = { 35 }; -static const int an7583_gpio34_pins[] = { 36 }; -static const int an7583_gpio35_pins[] = { 37 }; -static const int an7583_gpio36_pins[] = { 38 }; -static const int an7583_gpio37_pins[] = { 39 }; -static const int an7583_gpio38_pins[] = { 40 }; -static const int an7583_gpio39_pins[] = { 41 }; -static const int an7583_gpio40_pins[] = { 42 }; -static const int an7583_gpio41_pins[] = { 43 }; -static const int an7583_gpio42_pins[] = { 44 }; -static const int an7583_gpio43_pins[] = { 45 }; -static const int an7583_gpio44_pins[] = { 46 }; -static const int an7583_gpio45_pins[] = { 47 }; -static const int an7583_gpio46_pins[] = { 48 }; -static const int an7583_gpio47_pins[] = { 49 }; -static const int an7583_gpio48_pins[] = { 50 }; -static const int an7583_gpio49_pins[] = { 51 }; -static const int an7583_gpio50_pins[] = { 52 }; -static const int an7583_gpio51_pins[] = { 53 }; -static const int an7583_gpio52_pins[] = { 54 }; -static const int an7583_pcie_reset0_pins[] = { 51 }; -static const int an7583_pcie_reset1_pins[] = { 52 }; - -static const struct pingroup an7583_pinctrl_groups[] = { - PINCTRL_PIN_GROUP("pon", an7583_pon), - PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps), - PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps), - PINCTRL_PIN_GROUP("sipo", an7583_sipo), - PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk), - PINCTRL_PIN_GROUP("mdio", an7583_mdio), - PINCTRL_PIN_GROUP("mdio1", an7583_mdio1), - PINCTRL_PIN_GROUP("uart2", an7583_uart2), - PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts), - PINCTRL_PIN_GROUP("hsuart", an7583_hsuart), - PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts), - PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart), - PINCTRL_PIN_GROUP("uart4", an7583_uart4), - PINCTRL_PIN_GROUP("uart5", an7583_uart5), - PINCTRL_PIN_GROUP("i2c0", an7583_i2c0), - PINCTRL_PIN_GROUP("i2c1", an7583_i2c1), - PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi), - PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd), - PINCTRL_PIN_GROUP("pcm1", an7583_pcm1), - PINCTRL_PIN_GROUP("pcm2", an7583_pcm2), - PINCTRL_PIN_GROUP("spi", an7583_spi), - PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad), - PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1), - PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi), - PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst), - PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1), - PINCTRL_PIN_GROUP("emmc", an7583_emmc), - PINCTRL_PIN_GROUP("pnand", an7583_pnand), - PINCTRL_PIN_GROUP("gpio0", an7583_gpio0), - PINCTRL_PIN_GROUP("gpio1", an7583_gpio1), - PINCTRL_PIN_GROUP("gpio2", an7583_gpio2), - PINCTRL_PIN_GROUP("gpio3", an7583_gpio3), - PINCTRL_PIN_GROUP("gpio4", an7583_gpio4), - PINCTRL_PIN_GROUP("gpio5", an7583_gpio5), - PINCTRL_PIN_GROUP("gpio6", an7583_gpio6), - PINCTRL_PIN_GROUP("gpio7", an7583_gpio7), - PINCTRL_PIN_GROUP("gpio8", an7583_gpio8), - PINCTRL_PIN_GROUP("gpio9", an7583_gpio9), - PINCTRL_PIN_GROUP("gpio10", an7583_gpio10), - PINCTRL_PIN_GROUP("gpio11", an7583_gpio11), - PINCTRL_PIN_GROUP("gpio12", an7583_gpio12), - PINCTRL_PIN_GROUP("gpio13", an7583_gpio13), - PINCTRL_PIN_GROUP("gpio14", an7583_gpio14), - PINCTRL_PIN_GROUP("gpio15", an7583_gpio15), - PINCTRL_PIN_GROUP("gpio16", an7583_gpio16), - PINCTRL_PIN_GROUP("gpio17", an7583_gpio17), - PINCTRL_PIN_GROUP("gpio18", an7583_gpio18), - PINCTRL_PIN_GROUP("gpio19", an7583_gpio19), - PINCTRL_PIN_GROUP("gpio20", an7583_gpio20), - PINCTRL_PIN_GROUP("gpio21", an7583_gpio21), - PINCTRL_PIN_GROUP("gpio22", an7583_gpio22), - PINCTRL_PIN_GROUP("gpio23", an7583_gpio23), - PINCTRL_PIN_GROUP("gpio24", an7583_gpio24), - PINCTRL_PIN_GROUP("gpio25", an7583_gpio25), - PINCTRL_PIN_GROUP("gpio26", an7583_gpio26), - PINCTRL_PIN_GROUP("gpio27", an7583_gpio27), - PINCTRL_PIN_GROUP("gpio28", an7583_gpio28), - PINCTRL_PIN_GROUP("gpio29", an7583_gpio29), - PINCTRL_PIN_GROUP("gpio30", an7583_gpio30), - PINCTRL_PIN_GROUP("gpio31", an7583_gpio31), - PINCTRL_PIN_GROUP("gpio32", an7583_gpio32), - PINCTRL_PIN_GROUP("gpio33", an7583_gpio33), - PINCTRL_PIN_GROUP("gpio34", an7583_gpio34), - PINCTRL_PIN_GROUP("gpio35", an7583_gpio35), - PINCTRL_PIN_GROUP("gpio36", an7583_gpio36), - PINCTRL_PIN_GROUP("gpio37", an7583_gpio37), - PINCTRL_PIN_GROUP("gpio38", an7583_gpio38), - PINCTRL_PIN_GROUP("gpio39", an7583_gpio39), - PINCTRL_PIN_GROUP("gpio40", an7583_gpio40), - PINCTRL_PIN_GROUP("gpio41", an7583_gpio41), - PINCTRL_PIN_GROUP("gpio42", an7583_gpio42), - PINCTRL_PIN_GROUP("gpio43", an7583_gpio43), - PINCTRL_PIN_GROUP("gpio44", an7583_gpio44), - PINCTRL_PIN_GROUP("gpio45", an7583_gpio45), - PINCTRL_PIN_GROUP("gpio46", an7583_gpio46), - PINCTRL_PIN_GROUP("gpio47", an7583_gpio47), - PINCTRL_PIN_GROUP("gpio48", an7583_gpio48), - PINCTRL_PIN_GROUP("gpio49", an7583_gpio49), - PINCTRL_PIN_GROUP("gpio50", an7583_gpio50), - PINCTRL_PIN_GROUP("gpio51", an7583_gpio51), - PINCTRL_PIN_GROUP("gpio52", an7583_gpio52), - PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0), - PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1), -}; - -static const char *const pon_groups[] = { "pon" }; -static const char *const tod_1pps_groups[] = { "pon_tod_1pps", "gsw_tod_1pps" }; -static const char *const sipo_groups[] = { "sipo", "sipo_rclk" }; -static const char *const mdio_groups[] = { "mdio" }; -static const char *const an7583_mdio_groups[] = { "mdio" }; -static const char *const uart_groups[] = { "uart2", "uart2_cts_rts", "hsuart", - "hsuart_cts_rts", "uart4", - "uart5" }; -static const char *const i2c_groups[] = { "i2c1" }; -static const char *const an7583_i2c_groups[] = { "i2c0", "i2c1" }; -static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" }; -static const char *const pcm_groups[] = { "pcm1", "pcm2" }; -static const char *const spi_groups[] = { "spi_quad", "spi_cs1" }; -static const char *const pcm_spi_groups[] = { "pcm_spi", "pcm_spi_int", - "pcm_spi_rst", "pcm_spi_cs1", - "pcm_spi_cs2_p156", - "pcm_spi_cs2_p128", - "pcm_spi_cs3", "pcm_spi_cs4" }; -static const char *const an7583_pcm_spi_groups[] = { "pcm_spi", - "pcm_spi_rst", "pcm_spi_cs1" }; -static const char *const i2s_groups[] = { "i2s" }; -static const char *const emmc_groups[] = { "emmc" }; -static const char *const pnand_groups[] = { "pnand" }; -static const char *const gpio_groups[] = { "gpio47", "gpio48", "gpio49" }; -static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1", - "pcie_reset2" }; -static const char *const an7583_gpio_groups[] = { "gpio39", "gpio40", "gpio41", - "gpio42", "gpio43", "gpio44", - "gpio45", "gpio46", "gpio47", - "gpio48", "gpio49", "gpio50", - "gpio51", "gpio52" }; -static const char *const an7583_pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1" }; -static const char *const pwm_groups[] = { "gpio0", "gpio1", - "gpio2", "gpio3", - "gpio4", "gpio5", - "gpio6", "gpio7", - "gpio8", "gpio9", - "gpio10", "gpio11", - "gpio12", "gpio13", - "gpio14", "gpio15", - "gpio16", "gpio17", - "gpio18", "gpio19", - "gpio20", "gpio21", - "gpio22", "gpio23", - "gpio24", "gpio25", - "gpio26", "gpio27", - "gpio28", "gpio29", - "gpio30", "gpio31", - "gpio36", "gpio37", - "gpio38", "gpio39", - "gpio40", "gpio41", - "gpio42", "gpio43", - "gpio44", "gpio45", - "gpio46", "gpio47", - "gpio48", "gpio49" }; -static const char *const an7583_pwm_groups[] = { "gpio0", "gpio1", - "gpio2", "gpio3", - "gpio4", "gpio5", - "gpio6", "gpio7", - "gpio8", "gpio9", - "gpio10", "gpio11", - "gpio12", "gpio13", - "gpio14", "gpio15", - "gpio16", "gpio17", - "gpio18", "gpio19", - "gpio20", "gpio21", - "gpio22", "gpio23", - "gpio24", "gpio25", - "gpio26", "gpio27", - "gpio28", "gpio29", - "gpio30", "gpio31", - "gpio36", "gpio37", - "gpio38", "gpio39", - "gpio40", "gpio41", - "gpio42", "gpio43", - "gpio44", "gpio45", - "gpio46", "gpio47", - "gpio48", "gpio49", - "gpio50", "gpio51" }; -static const char *const phy1_led0_groups[] = { "gpio33", "gpio34", - "gpio35", "gpio42" }; -static const char *const phy2_led0_groups[] = { "gpio33", "gpio34", - "gpio35", "gpio42" }; -static const char *const phy3_led0_groups[] = { "gpio33", "gpio34", - "gpio35", "gpio42" }; -static const char *const phy4_led0_groups[] = { "gpio33", "gpio34", - "gpio35", "gpio42" }; -static const char *const phy1_led1_groups[] = { "gpio43", "gpio44", - "gpio45", "gpio46" }; -static const char *const phy2_led1_groups[] = { "gpio43", "gpio44", - "gpio45", "gpio46" }; -static const char *const phy3_led1_groups[] = { "gpio43", "gpio44", - "gpio45", "gpio46" }; -static const char *const phy4_led1_groups[] = { "gpio43", "gpio44", - "gpio45", "gpio46" }; -static const char *const an7583_phy1_led0_groups[] = { "gpio1", "gpio2", - "gpio3", "gpio4" }; -static const char *const an7583_phy2_led0_groups[] = { "gpio1", "gpio2", - "gpio3", "gpio4" }; -static const char *const an7583_phy3_led0_groups[] = { "gpio1", "gpio2", - "gpio3", "gpio4" }; -static const char *const an7583_phy4_led0_groups[] = { "gpio1", "gpio2", - "gpio3", "gpio4" }; -static const char *const an7583_phy1_led1_groups[] = { "gpio8", "gpio9", - "gpio10", "gpio11" }; -static const char *const an7583_phy2_led1_groups[] = { "gpio8", "gpio9", - "gpio10", "gpio11" }; -static const char *const an7583_phy3_led1_groups[] = { "gpio8", "gpio9", - "gpio10", "gpio11" }; -static const char *const an7583_phy4_led1_groups[] = { "gpio8", "gpio9", - "gpio10", "gpio11" }; - -static const struct airoha_pinctrl_func_group pon_func_group[] = { - { - .name = "pon", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_PON_MODE_MASK, - GPIO_PON_MODE_MASK - }, - .regmap_size = 1, - }, -}; - -static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = { - { - .name = "pon_tod_1pps", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - PON_TOD_1PPS_MODE_MASK, - PON_TOD_1PPS_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "gsw_tod_1pps", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GSW_TOD_1PPS_MODE_MASK, - GSW_TOD_1PPS_MODE_MASK - }, - .regmap_size = 1, - }, -}; - -static const struct airoha_pinctrl_func_group sipo_func_group[] = { - { - .name = "sipo", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, - GPIO_SIPO_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "sipo_rclk", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, - GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK - }, - .regmap_size = 1, - }, -}; - -static const struct airoha_pinctrl_func_group mdio_func_group[] = { - { - .name = "mdio", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_MDC_IO_MASTER_MODE_MASK, - GPIO_MDC_IO_MASTER_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_FORCE_GPIO_EN, - FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2), - FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2) - }, - .regmap_size = 2, - }, -}; - -static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = { - { - .name = "mdio", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - AN7583_MDC_0_GPIO_MODE_MASK | AN7583_MDIO_0_GPIO_MODE_MASK, - 0 - }, - .regmap_size = 1, - }, -}; - -static const struct airoha_pinctrl_func_group uart_func_group[] = { - { - .name = "uart2", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_UART2_MODE_MASK, - GPIO_UART2_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "uart2_cts_rts", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK, - GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "hsuart", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, - GPIO_HSUART_MODE_MASK - }, - .regmap_size = 1, - }, - { - .name = "hsuart_cts_rts", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, - GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "uart4", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_UART4_MODE_MASK, - GPIO_UART4_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "uart5", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_UART5_MODE_MASK, - GPIO_UART5_MODE_MASK - }, - .regmap_size = 1, - }, -}; - -static const struct airoha_pinctrl_func_group i2c_func_group[] = { - { - .name = "i2c1", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_2ND_I2C_MODE_MASK | GPIO_I2C_MASTER_MODE_MODE, - GPIO_2ND_I2C_MODE_MASK | GPIO_I2C_MASTER_MODE_MODE, - }, - .regmap_size = 1, - }, -}; - -static const struct airoha_pinctrl_func_group an7583_i2c_func_group[] = { - { - .name = "i2c0", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - AN7583_I2C0_SCL_GPIO_MODE_MASK | AN7583_I2C0_SDA_GPIO_MODE_MASK, - 0 - }, - .regmap_size = 1, - }, { - .name = "i2c1", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - AN7583_I2C1_SCL_GPIO_MODE_MASK | AN7583_I2C1_SDA_GPIO_MODE_MASK, - 0 - }, - .regmap_size = 1, - }, -}; - -static const struct airoha_pinctrl_func_group jtag_func_group[] = { - { - .name = "jtag_udi", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_NPU_UART_EN, - JTAG_UDI_EN_MASK, - JTAG_UDI_EN_MASK - }, - .regmap_size = 1, - }, { - .name = "jtag_dfd", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_NPU_UART_EN, - JTAG_DFD_EN_MASK, - JTAG_DFD_EN_MASK - }, - .regmap_size = 1, - }, -}; - -static const struct airoha_pinctrl_func_group pcm_func_group[] = { - { - .name = "pcm1", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM1_MODE_MASK, - GPIO_PCM1_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "pcm2", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM2_MODE_MASK, - GPIO_PCM2_MODE_MASK - }, - .regmap_size = 1, - }, -}; - -static const struct airoha_pinctrl_func_group spi_func_group[] = { - { - .name = "spi_quad", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_SPI_QUAD_MODE_MASK, - GPIO_SPI_QUAD_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "spi_cs1", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_SPI_CS1_MODE_MASK, - GPIO_SPI_CS1_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "spi_cs2", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_SPI_CS2_MODE_MASK, - GPIO_SPI_CS2_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "spi_cs3", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_SPI_CS3_MODE_MASK, - GPIO_SPI_CS3_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "spi_cs4", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_SPI_CS4_MODE_MASK, - GPIO_SPI_CS4_MODE_MASK - }, - .regmap_size = 1, - }, -}; - -static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = { - { - .name = "pcm_spi", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_SPI_MODE_MASK, - GPIO_PCM_SPI_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "pcm_spi_int", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_INT_MODE_MASK, - GPIO_PCM_INT_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "pcm_spi_rst", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_RESET_MODE_MASK, - GPIO_PCM_RESET_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "pcm_spi_cs1", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_SPI_CS1_MODE_MASK, - GPIO_PCM_SPI_CS1_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "pcm_spi_cs2_p128", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_SPI_CS2_MODE_P128_MASK, - GPIO_PCM_SPI_CS2_MODE_P128_MASK - }, - .regmap_size = 1, - }, { - .name = "pcm_spi_cs2_p156", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_SPI_CS2_MODE_P156_MASK, - GPIO_PCM_SPI_CS2_MODE_P156_MASK - }, - .regmap_size = 1, - }, { - .name = "pcm_spi_cs3", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_SPI_CS3_MODE_MASK, - GPIO_PCM_SPI_CS3_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "pcm_spi_cs4", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_SPI_CS4_MODE_MASK, - GPIO_PCM_SPI_CS4_MODE_MASK - }, - .regmap_size = 1, - }, -}; - -static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = { - { - .name = "pcm_spi", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_SPI_MODE_MASK, - GPIO_PCM_SPI_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "pcm_spi_int", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_INT_MODE_MASK, - GPIO_PCM_INT_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "pcm_spi_rst", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_RESET_MODE_MASK, - GPIO_PCM_RESET_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "pcm_spi_cs1", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_SPI_CS1_MODE_MASK, - GPIO_PCM_SPI_CS1_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "pcm_spi_cs2", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - AN7583_GPIO_PCM_SPI_CS2_MODE_MASK, - AN7583_GPIO_PCM_SPI_CS2_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "pcm_spi_cs3", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_SPI_CS3_MODE_MASK, - GPIO_PCM_SPI_CS3_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "pcm_spi_cs4", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_SPI_CS4_MODE_MASK, - GPIO_PCM_SPI_CS4_MODE_MASK - }, - .regmap_size = 1, - }, -}; - -static const struct airoha_pinctrl_func_group i2s_func_group[] = { - { - .name = "i2s", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_I2S_MODE_MASK, - GPIO_I2S_MODE_MASK - }, - .regmap_size = 1, - }, -}; - -static const struct airoha_pinctrl_func_group emmc_func_group[] = { - { - .name = "emmc", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_EMMC_MODE_MASK, - GPIO_EMMC_MODE_MASK - }, - .regmap_size = 1, - }, -}; - -static const struct airoha_pinctrl_func_group pnand_func_group[] = { - { - .name = "pnand", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_PARALLEL_NAND_MODE_MASK, - GPIO_PARALLEL_NAND_MODE_MASK - }, - .regmap_size = 1, - }, -}; - -static const struct airoha_pinctrl_func_group gpio_func_group[] = { - AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG, - GPIO_PCIE_RESET0_MASK), - AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG, - GPIO_PCIE_RESET1_MASK), - AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG, - GPIO_PCIE_RESET2_MASK), -}; - -static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = { - { - .name = "pcie_reset0", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_PCIE_RESET0_MASK, - 0 - }, - .regmap_size = 1, - }, { - .name = "pcie_reset1", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_PCIE_RESET1_MASK, - 0 - }, - .regmap_size = 1, - }, { - .name = "pcie_reset2", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_PCIE_RESET2_MASK, - 0 - }, - .regmap_size = 1, - }, -}; - -static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = { - AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG, - AN7583_I2C0_SCL_GPIO_MODE_MASK), - AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG, - AN7583_I2C0_SDA_GPIO_MODE_MASK), - AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG, - AN7583_I2C1_SCL_GPIO_MODE_MASK), - AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG, - AN7583_I2C1_SDA_GPIO_MODE_MASK), - AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG, - AN7583_SPI_CLK_GPIO_MODE_MASK), - AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG, - AN7583_SPI_CS_GPIO_MODE_MASK), - AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG, - AN7583_SPI_MOSI_GPIO_MODE_MASK), - AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG, - AN7583_SPI_MISO_GPIO_MODE_MASK), - AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG, - AN7583_UART_TXD_GPIO_MODE_MASK), - AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG, - AN7583_UART_RXD_GPIO_MODE_MASK), - AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG, - GPIO_PCIE_RESET0_MASK), - AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG, - GPIO_PCIE_RESET1_MASK), - AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG, - AN7583_MDC_0_GPIO_MODE_MASK), - AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK), -}; - -static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = { - { - .name = "pcie_reset0", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_PCIE_RESET0_MASK, - 0 - }, - .regmap_size = 1, - }, { - .name = "pcie_reset1", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_PCIE_RESET1_MASK, - 0 - }, - .regmap_size = 1, - }, -}; - -static const struct airoha_pinctrl_func_group pwm_func_group[] = { - AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG, - GPIO_PCIE_RESET0_MASK), - AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG, - GPIO_PCIE_RESET1_MASK), - AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG, - GPIO_PCIE_RESET2_MASK), -}; - -static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = { - AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG, - AN7583_I2C0_SCL_GPIO_MODE_MASK), - AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG, - AN7583_I2C0_SDA_GPIO_MODE_MASK), - AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG, - AN7583_I2C1_SCL_GPIO_MODE_MASK), - AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG, - AN7583_I2C1_SDA_GPIO_MODE_MASK), - AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG, - AN7583_SPI_CLK_GPIO_MODE_MASK), - AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG, - AN7583_SPI_CS_GPIO_MODE_MASK), - AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG, - AN7583_SPI_MOSI_GPIO_MODE_MASK), - AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG, - AN7583_SPI_MISO_GPIO_MODE_MASK), - AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG, - AN7583_UART_TXD_GPIO_MODE_MASK), - AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG, - AN7583_UART_RXD_GPIO_MODE_MASK), - AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG, - GPIO_PCIE_RESET0_MASK), - AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG, - GPIO_PCIE_RESET1_MASK), - AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG, - AN7583_MDC_0_GPIO_MODE_MASK), -}; - -static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = { - AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), -}; - -static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = { - AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), -}; - -static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = { - AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), -}; - -static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = { - AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), -}; - -static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = { - AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), -}; - -static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = { - AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), -}; - -static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = { - AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), -}; - -static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = { - AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), -}; - -static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = { - AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), -}; - -static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = { - AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), -}; - -static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = { - AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), -}; - -static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = { - AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), -}; - -static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = { - AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), -}; - -static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = { - AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), -}; - -static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = { - AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), -}; - -static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = { - AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), -}; - -static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = { - PINCTRL_FUNC_DESC("pon", pon), - PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), - PINCTRL_FUNC_DESC("sipo", sipo), - PINCTRL_FUNC_DESC("mdio", mdio), - PINCTRL_FUNC_DESC("uart", uart), - PINCTRL_FUNC_DESC("i2c", i2c), - PINCTRL_FUNC_DESC("jtag", jtag), - PINCTRL_FUNC_DESC("pcm", pcm), - PINCTRL_FUNC_DESC("spi", spi), - PINCTRL_FUNC_DESC("pcm_spi", pcm_spi), - PINCTRL_FUNC_DESC("i2s", i2s), - PINCTRL_FUNC_DESC("emmc", emmc), - PINCTRL_FUNC_DESC("pnand", pnand), - PINCTRL_FUNC_DESC("gpio", gpio), - PINCTRL_FUNC_DESC("pcie_reset", pcie_reset), - PINCTRL_FUNC_DESC("pwm", pwm), - PINCTRL_FUNC_DESC("phy1_led0", phy1_led0), - PINCTRL_FUNC_DESC("phy2_led0", phy2_led0), - PINCTRL_FUNC_DESC("phy3_led0", phy3_led0), - PINCTRL_FUNC_DESC("phy4_led0", phy4_led0), - PINCTRL_FUNC_DESC("phy1_led1", phy1_led1), - PINCTRL_FUNC_DESC("phy2_led1", phy2_led1), - PINCTRL_FUNC_DESC("phy3_led1", phy3_led1), - PINCTRL_FUNC_DESC("phy4_led1", phy4_led1), -}; - -static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = { - PINCTRL_FUNC_DESC("pon", pon), - PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), - PINCTRL_FUNC_DESC("sipo", sipo), - PINCTRL_FUNC_DESC("mdio", an7583_mdio), - PINCTRL_FUNC_DESC("uart", uart), - PINCTRL_FUNC_DESC("i2c", an7583_i2c), - PINCTRL_FUNC_DESC("jtag", jtag), - PINCTRL_FUNC_DESC("pcm", pcm), - PINCTRL_FUNC_DESC("spi", spi), - PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi), - PINCTRL_FUNC_DESC("emmc", emmc), - PINCTRL_FUNC_DESC("pnand", pnand), - PINCTRL_FUNC_DESC("gpio", an7583_gpio), - PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset), - PINCTRL_FUNC_DESC("pwm", an7583_pwm), - PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0), - PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0), - PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0), - PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0), - PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1), - PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1), - PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1), - PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1), -}; - -static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = { - PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), - PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), - PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), - PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), - PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), - PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), - PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), - PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK), - PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)), - PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)), - PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)), - PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)), - PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)), - PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)), - PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)), - PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)), - PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)), - PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)), - PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)), - PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)), - PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)), - PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)), - PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)), - PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)), - PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)), - PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)), - PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)), - PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(19)), - PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)), - PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)), - PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)), - PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)), - PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)), - PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)), - PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)), - PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)), - PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)), - PINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)), - PINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)), - PINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)), - PINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)), - PINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)), - PINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)), - PINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)), - PINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)), - PINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)), - PINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)), - PINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)), - PINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)), - PINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)), - PINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)), - PINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)), - PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)), - PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)), - PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)), - PINCTRL_CONF_DESC(60, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), - PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), - PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK), -}; - -static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = { - PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)), - PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)), - PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)), - PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)), - PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)), - PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)), - PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)), - PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)), - PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)), - PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)), - PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)), - PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)), - PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)), - PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)), - PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)), - PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)), - PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)), - PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)), - PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)), - PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(19)), - PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)), - PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)), - PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)), - PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)), - PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)), - PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)), - PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)), - PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)), - PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)), - PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)), - PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)), - PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)), - PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)), - PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)), - PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)), - PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)), - PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)), - PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)), - PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)), - PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), - PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), - PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK), - PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK), - PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), - PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), - PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), - PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK), - PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), - PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), - PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), - PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), - PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK), - PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK), -}; - -static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = { - PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), - PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), - PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), - PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), - PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), - PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), - PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), - PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK), - PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)), - PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)), - PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)), - PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)), - PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)), - PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)), - PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)), - PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)), - PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)), - PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)), - PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)), - PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)), - PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)), - PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)), - PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)), - PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)), - PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)), - PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)), - PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)), - PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(19)), - PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)), - PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)), - PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)), - PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)), - PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)), - PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)), - PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)), - PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)), - PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)), - PINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)), - PINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)), - PINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)), - PINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)), - PINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)), - PINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)), - PINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)), - PINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)), - PINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)), - PINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)), - PINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)), - PINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)), - PINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)), - PINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)), - PINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)), - PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)), - PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)), - PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)), - PINCTRL_CONF_DESC(60, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), - PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), - PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK), -}; - -static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = { - PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)), - PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)), - PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)), - PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)), - PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)), - PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)), - PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)), - PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)), - PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)), - PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)), - PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)), - PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)), - PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)), - PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)), - PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)), - PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)), - PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)), - PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)), - PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)), - PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(19)), - PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)), - PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)), - PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)), - PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)), - PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)), - PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)), - PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)), - PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)), - PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)), - PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)), - PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)), - PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)), - PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)), - PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)), - PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)), - PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)), - PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)), - PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)), - PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)), - PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), - PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), - PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK), - PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK), - PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), - PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), - PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), - PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK), - PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), - PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), - PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), - PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), - PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK), - PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK), -}; - -static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = { - PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), - PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), - PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), - PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), - PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), - PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), - PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), - PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK), - PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)), - PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)), - PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)), - PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)), - PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)), - PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)), - PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)), - PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)), - PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)), - PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)), - PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)), - PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)), - PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)), - PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)), - PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)), - PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)), - PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)), - PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)), - PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)), - PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(19)), - PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)), - PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)), - PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)), - PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)), - PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)), - PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)), - PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)), - PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)), - PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)), - PINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)), - PINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)), - PINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)), - PINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)), - PINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)), - PINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)), - PINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)), - PINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)), - PINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)), - PINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)), - PINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)), - PINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)), - PINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)), - PINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)), - PINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)), - PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)), - PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)), - PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)), - PINCTRL_CONF_DESC(60, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), - PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), - PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK), -}; - -static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = { - PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)), - PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)), - PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)), - PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)), - PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)), - PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)), - PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)), - PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)), - PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)), - PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)), - PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)), - PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)), - PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)), - PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)), - PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)), - PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)), - PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)), - PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)), - PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)), - PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(19)), - PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)), - PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)), - PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)), - PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)), - PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)), - PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)), - PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)), - PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)), - PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)), - PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)), - PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)), - PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)), - PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)), - PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)), - PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)), - PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)), - PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)), - PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)), - PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)), - PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), - PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), - PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK), - PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK), - PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), - PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), - PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), - PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK), - PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), - PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), - PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), - PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), - PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK), - PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK), -}; - -static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = { - PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), - PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), - PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), - PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), - PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), - PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), - PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), - PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK), - PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)), - PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)), - PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)), - PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)), - PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)), - PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)), - PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)), - PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)), - PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)), - PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)), - PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)), - PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)), - PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)), - PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)), - PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)), - PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)), - PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)), - PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)), - PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)), - PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(19)), - PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)), - PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)), - PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)), - PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)), - PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)), - PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)), - PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)), - PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)), - PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)), - PINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)), - PINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)), - PINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)), - PINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)), - PINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)), - PINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)), - PINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)), - PINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)), - PINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)), - PINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)), - PINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)), - PINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)), - PINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)), - PINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)), - PINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)), - PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)), - PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)), - PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)), - PINCTRL_CONF_DESC(60, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), - PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), - PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK), -}; - -static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = { - PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)), - PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)), - PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)), - PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)), - PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)), - PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)), - PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)), - PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)), - PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)), - PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)), - PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)), - PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)), - PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)), - PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)), - PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)), - PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)), - PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)), - PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)), - PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)), - PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(19)), - PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)), - PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)), - PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)), - PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)), - PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)), - PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)), - PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)), - PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)), - PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)), - PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)), - PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)), - PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)), - PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)), - PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)), - PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)), - PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)), - PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)), - PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)), - PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)), - PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), - PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), - PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK), - PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK), - PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), - PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), - PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), - PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK), - PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), - PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), - PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), - PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), - PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK), - PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK), -}; - -static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = { - PINCTRL_CONF_DESC(60, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), - PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), - PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK), -}; - -static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = { - PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), - PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), -}; - static int airoha_convert_pin_to_reg_offset(struct pinctrl_dev *pctrl_dev, struct pinctrl_gpio_range *range, int pin) @@ -3060,7 +771,7 @@ static const struct pinctrl_ops airoha_pctlops = { .dt_free_map = pinconf_generic_dt_free_map, }; -static int airoha_pinctrl_probe(struct platform_device *pdev) +int airoha_pinctrl_probe(struct platform_device *pdev) { const struct airoha_pinctrl_match_data *data; struct device *dev = &pdev->dev; @@ -3069,6 +780,8 @@ static int airoha_pinctrl_probe(struct platform_device *pdev) int err, i; data = device_get_match_data(dev); + if (!data) + return -EINVAL; pinctrl = devm_kzalloc(dev, sizeof(*pinctrl), GFP_KERNEL); if (!pinctrl) @@ -3085,8 +798,8 @@ static int airoha_pinctrl_probe(struct platform_device *pdev) pinctrl->chip_scu = map; /* Init pinctrl desc struct */ - pinctrl->desc.name = KBUILD_MODNAME; - pinctrl->desc.owner = THIS_MODULE; + pinctrl->desc.name = data->pinctrl_name; + pinctrl->desc.owner = data->pinctrl_owner; pinctrl->desc.pctlops = &airoha_pctlops; pinctrl->desc.pmxops = &airoha_pmxops; pinctrl->desc.confops = &airoha_confops; @@ -3140,87 +853,10 @@ static int airoha_pinctrl_probe(struct platform_device *pdev) /* build gpio-chip */ return airoha_pinctrl_add_gpiochip(pinctrl, pdev); } - -static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = { - .pins = en7581_pinctrl_pins, - .num_pins = ARRAY_SIZE(en7581_pinctrl_pins), - .grps = en7581_pinctrl_groups, - .num_grps = ARRAY_SIZE(en7581_pinctrl_groups), - .funcs = en7581_pinctrl_funcs, - .num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs), - .confs_info = { - [AIROHA_PINCTRL_CONFS_PULLUP] = { - .confs = en7581_pinctrl_pullup_conf, - .num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf), - }, - [AIROHA_PINCTRL_CONFS_PULLDOWN] = { - .confs = en7581_pinctrl_pulldown_conf, - .num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf), - }, - [AIROHA_PINCTRL_CONFS_DRIVE_E2] = { - .confs = en7581_pinctrl_drive_e2_conf, - .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf), - }, - [AIROHA_PINCTRL_CONFS_DRIVE_E4] = { - .confs = en7581_pinctrl_drive_e4_conf, - .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf), - }, - [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = { - .confs = en7581_pinctrl_pcie_rst_od_conf, - .num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf), - }, - }, -}; - -static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = { - .pins = an7583_pinctrl_pins, - .num_pins = ARRAY_SIZE(an7583_pinctrl_pins), - .grps = an7583_pinctrl_groups, - .num_grps = ARRAY_SIZE(an7583_pinctrl_groups), - .funcs = an7583_pinctrl_funcs, - .num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs), - .confs_info = { - [AIROHA_PINCTRL_CONFS_PULLUP] = { - .confs = an7583_pinctrl_pullup_conf, - .num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf), - }, - [AIROHA_PINCTRL_CONFS_PULLDOWN] = { - .confs = an7583_pinctrl_pulldown_conf, - .num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf), - }, - [AIROHA_PINCTRL_CONFS_DRIVE_E2] = { - .confs = an7583_pinctrl_drive_e2_conf, - .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf), - }, - [AIROHA_PINCTRL_CONFS_DRIVE_E4] = { - .confs = an7583_pinctrl_drive_e4_conf, - .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf), - }, - [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = { - .confs = an7583_pinctrl_pcie_rst_od_conf, - .num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf), - }, - }, -}; - -static const struct of_device_id airoha_pinctrl_of_match[] = { - { .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data }, - { .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match); - -static struct platform_driver airoha_pinctrl_driver = { - .probe = airoha_pinctrl_probe, - .driver = { - .name = "pinctrl-airoha", - .of_match_table = airoha_pinctrl_of_match, - }, -}; -module_platform_driver(airoha_pinctrl_driver); +EXPORT_SYMBOL_GPL(airoha_pinctrl_probe); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Lorenzo Bianconi "); MODULE_AUTHOR("Benjamin Larsson "); MODULE_AUTHOR("Markus Gothe "); -MODULE_DESCRIPTION("Pinctrl driver for Airoha SoC"); +MODULE_DESCRIPTION("Pinctrl common driver for Airoha SoC"); diff --git a/drivers/pinctrl/airoha/pinctrl-an7581.c b/drivers/pinctrl/airoha/pinctrl-an7581.c new file mode 100644 index 000000000000..7bb104d80589 --- /dev/null +++ b/drivers/pinctrl/airoha/pinctrl-an7581.c @@ -0,0 +1,1486 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: Lorenzo Bianconi + * Author: Benjamin Larsson + * Author: Markus Gothe + */ + +#include "airoha-common.h" + +/* MUX */ +#define REG_GPIO_2ND_I2C_MODE 0x0214 +#define GPIO_MDC_IO_MASTER_MODE_MASK BIT(14) +#define GPIO_I2C_MASTER_MODE_MODE BIT(13) +#define GPIO_I2S_MODE_MASK BIT(12) +#define GPIO_I2C_SLAVE_MODE_MODE BIT(11) +#define GPIO_LAN3_LED1_MODE_MASK BIT(10) +#define GPIO_LAN3_LED0_MODE_MASK BIT(9) +#define GPIO_LAN2_LED1_MODE_MASK BIT(8) +#define GPIO_LAN2_LED0_MODE_MASK BIT(7) +#define GPIO_LAN1_LED1_MODE_MASK BIT(6) +#define GPIO_LAN1_LED0_MODE_MASK BIT(5) +#define GPIO_LAN0_LED1_MODE_MASK BIT(4) +#define GPIO_LAN0_LED0_MODE_MASK BIT(3) +#define PON_TOD_1PPS_MODE_MASK BIT(2) +#define GSW_TOD_1PPS_MODE_MASK BIT(1) +#define GPIO_2ND_I2C_MODE_MASK BIT(0) + +#define REG_GPIO_SPI_CS1_MODE 0x0218 +#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21) +#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20) +#define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19) +#define GPIO_PCM_SPI_CS2_MODE_P128_MASK BIT(18) +#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17) +#define GPIO_PCM_SPI_MODE_MASK BIT(16) +#define GPIO_PCM2_MODE_MASK BIT(13) +#define GPIO_PCM1_MODE_MASK BIT(12) +#define GPIO_PCM_INT_MODE_MASK BIT(9) +#define GPIO_PCM_RESET_MODE_MASK BIT(8) +#define GPIO_SPI_QUAD_MODE_MASK BIT(4) +#define GPIO_SPI_CS4_MODE_MASK BIT(3) +#define GPIO_SPI_CS3_MODE_MASK BIT(2) +#define GPIO_SPI_CS2_MODE_MASK BIT(1) +#define GPIO_SPI_CS1_MODE_MASK BIT(0) + +#define REG_GPIO_PON_MODE 0x021c +#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14) +#define GPIO_SGMII_MDIO_MODE_MASK BIT(13) +#define GPIO_PCIE_RESET2_MASK BIT(12) +#define SIPO_RCLK_MODE_MASK BIT(11) +#define GPIO_PCIE_RESET1_MASK BIT(10) +#define GPIO_PCIE_RESET0_MASK BIT(9) +#define GPIO_UART5_MODE_MASK BIT(8) +#define GPIO_UART4_MODE_MASK BIT(7) +#define GPIO_HSUART_CTS_RTS_MODE_MASK BIT(6) +#define GPIO_HSUART_MODE_MASK BIT(5) +#define GPIO_UART2_CTS_RTS_MODE_MASK BIT(4) +#define GPIO_UART2_MODE_MASK BIT(3) +#define GPIO_SIPO_MODE_MASK BIT(2) +#define GPIO_EMMC_MODE_MASK BIT(1) +#define GPIO_PON_MODE_MASK BIT(0) + +#define REG_NPU_UART_EN 0x0224 +#define JTAG_UDI_EN_MASK BIT(4) +#define JTAG_DFD_EN_MASK BIT(3) + +#define REG_FORCE_GPIO_EN 0x0228 +#define FORCE_GPIO_EN(n) BIT(n) + +/* LED MAP */ +#define REG_LAN_LED0_MAPPING 0x027c +#define REG_LAN_LED1_MAPPING 0x0280 + +#define LAN4_LED_MAPPING_MASK GENMASK(18, 16) +#define LAN4_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n)) + +#define LAN3_LED_MAPPING_MASK GENMASK(14, 12) +#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n)) + +#define LAN2_LED_MAPPING_MASK GENMASK(10, 8) +#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n)) + +#define LAN1_LED_MAPPING_MASK GENMASK(6, 4) +#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n)) + +#define LAN0_LED_MAPPING_MASK GENMASK(2, 0) +#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n)) + +/* CONF */ +#define REG_I2C_SDA_E2 0x001c +#define SPI_MISO_E2_MASK BIT(14) +#define SPI_MOSI_E2_MASK BIT(13) +#define SPI_CLK_E2_MASK BIT(12) +#define SPI_CS0_E2_MASK BIT(11) +#define PCIE2_RESET_E2_MASK BIT(10) +#define PCIE1_RESET_E2_MASK BIT(9) +#define PCIE0_RESET_E2_MASK BIT(8) +#define UART1_RXD_E2_MASK BIT(3) +#define UART1_TXD_E2_MASK BIT(2) +#define I2C_SCL_E2_MASK BIT(1) +#define I2C_SDA_E2_MASK BIT(0) + +#define REG_I2C_SDA_E4 0x0020 +#define SPI_MISO_E4_MASK BIT(14) +#define SPI_MOSI_E4_MASK BIT(13) +#define SPI_CLK_E4_MASK BIT(12) +#define SPI_CS0_E4_MASK BIT(11) +#define PCIE2_RESET_E4_MASK BIT(10) +#define PCIE1_RESET_E4_MASK BIT(9) +#define PCIE0_RESET_E4_MASK BIT(8) +#define UART1_RXD_E4_MASK BIT(3) +#define UART1_TXD_E4_MASK BIT(2) +#define I2C_SCL_E4_MASK BIT(1) +#define I2C_SDA_E4_MASK BIT(0) + +#define REG_GPIO_L_E2 0x0024 +#define REG_GPIO_L_E4 0x0028 +#define REG_GPIO_H_E2 0x002c +#define REG_GPIO_H_E4 0x0030 + +#define REG_I2C_SDA_PU 0x0044 +#define SPI_MISO_PU_MASK BIT(14) +#define SPI_MOSI_PU_MASK BIT(13) +#define SPI_CLK_PU_MASK BIT(12) +#define SPI_CS0_PU_MASK BIT(11) +#define PCIE2_RESET_PU_MASK BIT(10) +#define PCIE1_RESET_PU_MASK BIT(9) +#define PCIE0_RESET_PU_MASK BIT(8) +#define UART1_RXD_PU_MASK BIT(3) +#define UART1_TXD_PU_MASK BIT(2) +#define I2C_SCL_PU_MASK BIT(1) +#define I2C_SDA_PU_MASK BIT(0) + +#define REG_I2C_SDA_PD 0x0048 +#define SPI_MISO_PD_MASK BIT(14) +#define SPI_MOSI_PD_MASK BIT(13) +#define SPI_CLK_PD_MASK BIT(12) +#define SPI_CS0_PD_MASK BIT(11) +#define PCIE2_RESET_PD_MASK BIT(10) +#define PCIE1_RESET_PD_MASK BIT(9) +#define PCIE0_RESET_PD_MASK BIT(8) +#define UART1_RXD_PD_MASK BIT(3) +#define UART1_TXD_PD_MASK BIT(2) +#define I2C_SCL_PD_MASK BIT(1) +#define I2C_SDA_PD_MASK BIT(0) + +#define REG_GPIO_L_PU 0x004c +#define REG_GPIO_L_PD 0x0050 +#define REG_GPIO_H_PU 0x0054 +#define REG_GPIO_H_PD 0x0058 + +#define REG_PCIE_RESET_OD 0x018c +#define PCIE2_RESET_OD_MASK BIT(2) +#define PCIE1_RESET_OD_MASK BIT(1) +#define PCIE0_RESET_OD_MASK BIT(0) + +/* PWM MODE CONF */ +#define REG_GPIO_FLASH_MODE_CFG 0x0034 +#define GPIO15_FLASH_MODE_CFG BIT(15) +#define GPIO14_FLASH_MODE_CFG BIT(14) +#define GPIO13_FLASH_MODE_CFG BIT(13) +#define GPIO12_FLASH_MODE_CFG BIT(12) +#define GPIO11_FLASH_MODE_CFG BIT(11) +#define GPIO10_FLASH_MODE_CFG BIT(10) +#define GPIO9_FLASH_MODE_CFG BIT(9) +#define GPIO8_FLASH_MODE_CFG BIT(8) +#define GPIO7_FLASH_MODE_CFG BIT(7) +#define GPIO6_FLASH_MODE_CFG BIT(6) +#define GPIO5_FLASH_MODE_CFG BIT(5) +#define GPIO4_FLASH_MODE_CFG BIT(4) +#define GPIO3_FLASH_MODE_CFG BIT(3) +#define GPIO2_FLASH_MODE_CFG BIT(2) +#define GPIO1_FLASH_MODE_CFG BIT(1) +#define GPIO0_FLASH_MODE_CFG BIT(0) + +/* PWM MODE CONF EXT */ +#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068 +#define GPIO51_FLASH_MODE_CFG BIT(31) +#define GPIO50_FLASH_MODE_CFG BIT(30) +#define GPIO49_FLASH_MODE_CFG BIT(29) +#define GPIO48_FLASH_MODE_CFG BIT(28) +#define GPIO47_FLASH_MODE_CFG BIT(27) +#define GPIO46_FLASH_MODE_CFG BIT(26) +#define GPIO45_FLASH_MODE_CFG BIT(25) +#define GPIO44_FLASH_MODE_CFG BIT(24) +#define GPIO43_FLASH_MODE_CFG BIT(23) +#define GPIO42_FLASH_MODE_CFG BIT(22) +#define GPIO41_FLASH_MODE_CFG BIT(21) +#define GPIO40_FLASH_MODE_CFG BIT(20) +#define GPIO39_FLASH_MODE_CFG BIT(19) +#define GPIO38_FLASH_MODE_CFG BIT(18) +#define GPIO37_FLASH_MODE_CFG BIT(17) +#define GPIO36_FLASH_MODE_CFG BIT(16) +#define GPIO31_FLASH_MODE_CFG BIT(15) +#define GPIO30_FLASH_MODE_CFG BIT(14) +#define GPIO29_FLASH_MODE_CFG BIT(13) +#define GPIO28_FLASH_MODE_CFG BIT(12) +#define GPIO27_FLASH_MODE_CFG BIT(11) +#define GPIO26_FLASH_MODE_CFG BIT(10) +#define GPIO25_FLASH_MODE_CFG BIT(9) +#define GPIO24_FLASH_MODE_CFG BIT(8) +#define GPIO23_FLASH_MODE_CFG BIT(7) +#define GPIO22_FLASH_MODE_CFG BIT(6) +#define GPIO21_FLASH_MODE_CFG BIT(5) +#define GPIO20_FLASH_MODE_CFG BIT(4) +#define GPIO19_FLASH_MODE_CFG BIT(3) +#define GPIO18_FLASH_MODE_CFG BIT(2) +#define GPIO17_FLASH_MODE_CFG BIT(1) +#define GPIO16_FLASH_MODE_CFG BIT(0) + +#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + 0 \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (smux_val), \ + (smux_val) \ + }, \ + .regmap_size = 2, \ + } + +/* PWM */ +#define AIROHA_PINCTRL_PWM(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_MUX, \ + REG_GPIO_FLASH_MODE_CFG, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (smux_val), \ + (smux_val) \ + }, \ + .regmap_size = 2, \ + } + +#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_2ND_I2C_MODE, \ + (mux_val), \ + (mux_val), \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_LAN_LED0_MAPPING, \ + (map_mask), \ + (map_val), \ + }, \ + .regmap_size = 2, \ + } + +#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_2ND_I2C_MODE, \ + (mux_val), \ + (mux_val), \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_LAN_LED1_MAPPING, \ + (map_mask), \ + (map_val), \ + }, \ + .regmap_size = 2, \ + } + +static struct pinctrl_pin_desc en7581_pinctrl_pins[] = { + PINCTRL_PIN(0, "uart1_txd"), + PINCTRL_PIN(1, "uart1_rxd"), + PINCTRL_PIN(2, "i2c_scl"), + PINCTRL_PIN(3, "i2c_sda"), + PINCTRL_PIN(4, "spi_cs0"), + PINCTRL_PIN(5, "spi_clk"), + PINCTRL_PIN(6, "spi_mosi"), + PINCTRL_PIN(7, "spi_miso"), + PINCTRL_PIN(13, "gpio0"), + PINCTRL_PIN(14, "gpio1"), + PINCTRL_PIN(15, "gpio2"), + PINCTRL_PIN(16, "gpio3"), + PINCTRL_PIN(17, "gpio4"), + PINCTRL_PIN(18, "gpio5"), + PINCTRL_PIN(19, "gpio6"), + PINCTRL_PIN(20, "gpio7"), + PINCTRL_PIN(21, "gpio8"), + PINCTRL_PIN(22, "gpio9"), + PINCTRL_PIN(23, "gpio10"), + PINCTRL_PIN(24, "gpio11"), + PINCTRL_PIN(25, "gpio12"), + PINCTRL_PIN(26, "gpio13"), + PINCTRL_PIN(27, "gpio14"), + PINCTRL_PIN(28, "gpio15"), + PINCTRL_PIN(29, "gpio16"), + PINCTRL_PIN(30, "gpio17"), + PINCTRL_PIN(31, "gpio18"), + PINCTRL_PIN(32, "gpio19"), + PINCTRL_PIN(33, "gpio20"), + PINCTRL_PIN(34, "gpio21"), + PINCTRL_PIN(35, "gpio22"), + PINCTRL_PIN(36, "gpio23"), + PINCTRL_PIN(37, "gpio24"), + PINCTRL_PIN(38, "gpio25"), + PINCTRL_PIN(39, "gpio26"), + PINCTRL_PIN(40, "gpio27"), + PINCTRL_PIN(41, "gpio28"), + PINCTRL_PIN(42, "gpio29"), + PINCTRL_PIN(43, "gpio30"), + PINCTRL_PIN(44, "gpio31"), + PINCTRL_PIN(45, "gpio32"), + PINCTRL_PIN(46, "gpio33"), + PINCTRL_PIN(47, "gpio34"), + PINCTRL_PIN(48, "gpio35"), + PINCTRL_PIN(49, "gpio36"), + PINCTRL_PIN(50, "gpio37"), + PINCTRL_PIN(51, "gpio38"), + PINCTRL_PIN(52, "gpio39"), + PINCTRL_PIN(53, "gpio40"), + PINCTRL_PIN(54, "gpio41"), + PINCTRL_PIN(55, "gpio42"), + PINCTRL_PIN(56, "gpio43"), + PINCTRL_PIN(57, "gpio44"), + PINCTRL_PIN(58, "gpio45"), + PINCTRL_PIN(59, "gpio46"), + PINCTRL_PIN(60, "pcie_reset0"), + PINCTRL_PIN(61, "pcie_reset1"), + PINCTRL_PIN(62, "pcie_reset2"), +}; + +static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 }; +static const int en7581_pon_tod_1pps_pins[] = { 46 }; +static const int en7581_gsw_tod_1pps_pins[] = { 46 }; +static const int en7581_sipo_pins[] = { 16, 17 }; +static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 }; +static const int en7581_mdio_pins[] = { 14, 15 }; +static const int en7581_uart2_pins[] = { 48, 55 }; +static const int en7581_uart2_cts_rts_pins[] = { 46, 47 }; +static const int en7581_hsuart_pins[] = { 28, 29 }; +static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 }; +static const int en7581_uart4_pins[] = { 38, 39 }; +static const int en7581_uart5_pins[] = { 18, 19 }; +static const int en7581_i2c0_pins[] = { 2, 3 }; +static const int en7581_i2c1_pins[] = { 14, 15 }; +static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 }; +static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 }; +static const int en7581_i2s_pins[] = { 26, 27, 28, 29 }; +static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 }; +static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 }; +static const int en7581_spi_quad_pins[] = { 32, 33 }; +static const int en7581_spi_pins[] = { 4, 5, 6, 7 }; +static const int en7581_spi_cs1_pins[] = { 34 }; +static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 }; +static const int en7581_pcm_spi_int_pins[] = { 14 }; +static const int en7581_pcm_spi_rst_pins[] = { 15 }; +static const int en7581_pcm_spi_cs1_pins[] = { 43 }; +static const int en7581_pcm_spi_cs2_pins[] = { 40 }; +static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 }; +static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 }; +static const int en7581_pcm_spi_cs3_pins[] = { 41 }; +static const int en7581_pcm_spi_cs4_pins[] = { 42 }; +static const int en7581_emmc_pins[] = { + 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 +}; +static const int en7581_pnand_pins[] = { + 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 +}; +static const int en7581_gpio0_pins[] = { 13 }; +static const int en7581_gpio1_pins[] = { 14 }; +static const int en7581_gpio2_pins[] = { 15 }; +static const int en7581_gpio3_pins[] = { 16 }; +static const int en7581_gpio4_pins[] = { 17 }; +static const int en7581_gpio5_pins[] = { 18 }; +static const int en7581_gpio6_pins[] = { 19 }; +static const int en7581_gpio7_pins[] = { 20 }; +static const int en7581_gpio8_pins[] = { 21 }; +static const int en7581_gpio9_pins[] = { 22 }; +static const int en7581_gpio10_pins[] = { 23 }; +static const int en7581_gpio11_pins[] = { 24 }; +static const int en7581_gpio12_pins[] = { 25 }; +static const int en7581_gpio13_pins[] = { 26 }; +static const int en7581_gpio14_pins[] = { 27 }; +static const int en7581_gpio15_pins[] = { 28 }; +static const int en7581_gpio16_pins[] = { 29 }; +static const int en7581_gpio17_pins[] = { 30 }; +static const int en7581_gpio18_pins[] = { 31 }; +static const int en7581_gpio19_pins[] = { 32 }; +static const int en7581_gpio20_pins[] = { 33 }; +static const int en7581_gpio21_pins[] = { 34 }; +static const int en7581_gpio22_pins[] = { 35 }; +static const int en7581_gpio23_pins[] = { 36 }; +static const int en7581_gpio24_pins[] = { 37 }; +static const int en7581_gpio25_pins[] = { 38 }; +static const int en7581_gpio26_pins[] = { 39 }; +static const int en7581_gpio27_pins[] = { 40 }; +static const int en7581_gpio28_pins[] = { 41 }; +static const int en7581_gpio29_pins[] = { 42 }; +static const int en7581_gpio30_pins[] = { 43 }; +static const int en7581_gpio31_pins[] = { 44 }; +static const int en7581_gpio32_pins[] = { 45 }; +static const int en7581_gpio33_pins[] = { 46 }; +static const int en7581_gpio34_pins[] = { 47 }; +static const int en7581_gpio35_pins[] = { 48 }; +static const int en7581_gpio36_pins[] = { 49 }; +static const int en7581_gpio37_pins[] = { 50 }; +static const int en7581_gpio38_pins[] = { 51 }; +static const int en7581_gpio39_pins[] = { 52 }; +static const int en7581_gpio40_pins[] = { 53 }; +static const int en7581_gpio41_pins[] = { 54 }; +static const int en7581_gpio42_pins[] = { 55 }; +static const int en7581_gpio43_pins[] = { 56 }; +static const int en7581_gpio44_pins[] = { 57 }; +static const int en7581_gpio45_pins[] = { 58 }; +static const int en7581_gpio46_pins[] = { 59 }; +static const int en7581_gpio47_pins[] = { 60 }; +static const int en7581_gpio48_pins[] = { 61 }; +static const int en7581_gpio49_pins[] = { 62 }; +static const int en7581_pcie_reset0_pins[] = { 60 }; +static const int en7581_pcie_reset1_pins[] = { 61 }; +static const int en7581_pcie_reset2_pins[] = { 62 }; + +static const struct pingroup en7581_pinctrl_groups[] = { + PINCTRL_PIN_GROUP("pon", en7581_pon), + PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps), + PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps), + PINCTRL_PIN_GROUP("sipo", en7581_sipo), + PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk), + PINCTRL_PIN_GROUP("mdio", en7581_mdio), + PINCTRL_PIN_GROUP("uart2", en7581_uart2), + PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts), + PINCTRL_PIN_GROUP("hsuart", en7581_hsuart), + PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts), + PINCTRL_PIN_GROUP("uart4", en7581_uart4), + PINCTRL_PIN_GROUP("uart5", en7581_uart5), + PINCTRL_PIN_GROUP("i2c0", en7581_i2c0), + PINCTRL_PIN_GROUP("i2c1", en7581_i2c1), + PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi), + PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd), + PINCTRL_PIN_GROUP("i2s", en7581_i2s), + PINCTRL_PIN_GROUP("pcm1", en7581_pcm1), + PINCTRL_PIN_GROUP("pcm2", en7581_pcm2), + PINCTRL_PIN_GROUP("spi", en7581_spi), + PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad), + PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1), + PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi), + PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int), + PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst), + PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1), + PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128), + PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156), + PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2), + PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3), + PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4), + PINCTRL_PIN_GROUP("emmc", en7581_emmc), + PINCTRL_PIN_GROUP("pnand", en7581_pnand), + PINCTRL_PIN_GROUP("gpio0", en7581_gpio0), + PINCTRL_PIN_GROUP("gpio1", en7581_gpio1), + PINCTRL_PIN_GROUP("gpio2", en7581_gpio2), + PINCTRL_PIN_GROUP("gpio3", en7581_gpio3), + PINCTRL_PIN_GROUP("gpio4", en7581_gpio4), + PINCTRL_PIN_GROUP("gpio5", en7581_gpio5), + PINCTRL_PIN_GROUP("gpio6", en7581_gpio6), + PINCTRL_PIN_GROUP("gpio7", en7581_gpio7), + PINCTRL_PIN_GROUP("gpio8", en7581_gpio8), + PINCTRL_PIN_GROUP("gpio9", en7581_gpio9), + PINCTRL_PIN_GROUP("gpio10", en7581_gpio10), + PINCTRL_PIN_GROUP("gpio11", en7581_gpio11), + PINCTRL_PIN_GROUP("gpio12", en7581_gpio12), + PINCTRL_PIN_GROUP("gpio13", en7581_gpio13), + PINCTRL_PIN_GROUP("gpio14", en7581_gpio14), + PINCTRL_PIN_GROUP("gpio15", en7581_gpio15), + PINCTRL_PIN_GROUP("gpio16", en7581_gpio16), + PINCTRL_PIN_GROUP("gpio17", en7581_gpio17), + PINCTRL_PIN_GROUP("gpio18", en7581_gpio18), + PINCTRL_PIN_GROUP("gpio19", en7581_gpio19), + PINCTRL_PIN_GROUP("gpio20", en7581_gpio20), + PINCTRL_PIN_GROUP("gpio21", en7581_gpio21), + PINCTRL_PIN_GROUP("gpio22", en7581_gpio22), + PINCTRL_PIN_GROUP("gpio23", en7581_gpio23), + PINCTRL_PIN_GROUP("gpio24", en7581_gpio24), + PINCTRL_PIN_GROUP("gpio25", en7581_gpio25), + PINCTRL_PIN_GROUP("gpio26", en7581_gpio26), + PINCTRL_PIN_GROUP("gpio27", en7581_gpio27), + PINCTRL_PIN_GROUP("gpio28", en7581_gpio28), + PINCTRL_PIN_GROUP("gpio29", en7581_gpio29), + PINCTRL_PIN_GROUP("gpio30", en7581_gpio30), + PINCTRL_PIN_GROUP("gpio31", en7581_gpio31), + PINCTRL_PIN_GROUP("gpio32", en7581_gpio32), + PINCTRL_PIN_GROUP("gpio33", en7581_gpio33), + PINCTRL_PIN_GROUP("gpio34", en7581_gpio34), + PINCTRL_PIN_GROUP("gpio35", en7581_gpio35), + PINCTRL_PIN_GROUP("gpio36", en7581_gpio36), + PINCTRL_PIN_GROUP("gpio37", en7581_gpio37), + PINCTRL_PIN_GROUP("gpio38", en7581_gpio38), + PINCTRL_PIN_GROUP("gpio39", en7581_gpio39), + PINCTRL_PIN_GROUP("gpio40", en7581_gpio40), + PINCTRL_PIN_GROUP("gpio41", en7581_gpio41), + PINCTRL_PIN_GROUP("gpio42", en7581_gpio42), + PINCTRL_PIN_GROUP("gpio43", en7581_gpio43), + PINCTRL_PIN_GROUP("gpio44", en7581_gpio44), + PINCTRL_PIN_GROUP("gpio45", en7581_gpio45), + PINCTRL_PIN_GROUP("gpio46", en7581_gpio46), + PINCTRL_PIN_GROUP("gpio47", en7581_gpio47), + PINCTRL_PIN_GROUP("gpio48", en7581_gpio48), + PINCTRL_PIN_GROUP("gpio49", en7581_gpio49), + PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0), + PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1), + PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2), +}; + +static const char *const pon_groups[] = { "pon" }; +static const char *const tod_1pps_groups[] = { + "pon_tod_1pps", "gsw_tod_1pps" +}; +static const char *const sipo_groups[] = { "sipo", "sipo_rclk" }; +static const char *const mdio_groups[] = { "mdio" }; +static const char *const uart_groups[] = { + "uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts", + "uart4", "uart5" +}; +static const char *const i2c_groups[] = { "i2c1" }; +static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" }; +static const char *const pcm_groups[] = { "pcm1", "pcm2" }; +static const char *const spi_groups[] = { "spi_quad", "spi_cs1" }; +static const char *const pcm_spi_groups[] = { + "pcm_spi", "pcm_spi_int", "pcm_spi_rst", "pcm_spi_cs1", + "pcm_spi_cs2_p156", "pcm_spi_cs2_p128", "pcm_spi_cs3", + "pcm_spi_cs4" +}; +static const char *const i2s_groups[] = { "i2s" }; +static const char *const emmc_groups[] = { "emmc" }; +static const char *const pnand_groups[] = { "pnand" }; +static const char *const gpio_groups[] = { "gpio47", "gpio48", "gpio49" }; +static const char *const pcie_reset_groups[] = { + "pcie_reset0", "pcie_reset1", "pcie_reset2" +}; +static const char *const pwm_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio36", "gpio37", "gpio38", "gpio39", + "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47", "gpio48", "gpio49" +}; +static const char *const phy1_led0_groups[] = { + "gpio33", "gpio34", "gpio35", "gpio42" +}; +static const char *const phy2_led0_groups[] = { + "gpio33", "gpio34", "gpio35", "gpio42" +}; +static const char *const phy3_led0_groups[] = { + "gpio33", "gpio34", "gpio35", "gpio42" +}; +static const char *const phy4_led0_groups[] = { + "gpio33", "gpio34", "gpio35", "gpio42" +}; +static const char *const phy1_led1_groups[] = { + "gpio43", "gpio44", "gpio45", "gpio46" +}; +static const char *const phy2_led1_groups[] = { + "gpio43", "gpio44", "gpio45", "gpio46" +}; +static const char *const phy3_led1_groups[] = { + "gpio43", "gpio44", "gpio45", "gpio46" +}; +static const char *const phy4_led1_groups[] = { + "gpio43", "gpio44", "gpio45", "gpio46" +}; + +static const struct airoha_pinctrl_func_group pon_func_group[] = { + { + .name = "pon", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PON_MODE_MASK, + GPIO_PON_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = { + { + .name = "pon_tod_1pps", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + PON_TOD_1PPS_MODE_MASK, + PON_TOD_1PPS_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "gsw_tod_1pps", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GSW_TOD_1PPS_MODE_MASK, + GSW_TOD_1PPS_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group sipo_func_group[] = { + { + .name = "sipo", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "sipo_rclk", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group mdio_func_group[] = { + { + .name = "mdio", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_MDC_IO_MASTER_MODE_MASK, + GPIO_MDC_IO_MASTER_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_FORCE_GPIO_EN, + FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2), + FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2) + }, + .regmap_size = 2, + }, +}; + +static const struct airoha_pinctrl_func_group uart_func_group[] = { + { + .name = "uart2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART2_MODE_MASK, + GPIO_UART2_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "uart2_cts_rts", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK, + GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "hsuart", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, + GPIO_HSUART_MODE_MASK + }, + .regmap_size = 1, + }, + { + .name = "hsuart_cts_rts", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "uart4", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART4_MODE_MASK, + GPIO_UART4_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "uart5", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART5_MODE_MASK, + GPIO_UART5_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group i2c_func_group[] = { + { + .name = "i2c1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_2ND_I2C_MODE_MASK | GPIO_I2C_MASTER_MODE_MODE, + GPIO_2ND_I2C_MODE_MASK | GPIO_I2C_MASTER_MODE_MODE + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group jtag_func_group[] = { + { + .name = "jtag_udi", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + JTAG_UDI_EN_MASK, + JTAG_UDI_EN_MASK + }, + .regmap_size = 1, + }, { + .name = "jtag_dfd", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + JTAG_DFD_EN_MASK, + JTAG_DFD_EN_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pcm_func_group[] = { + { + .name = "pcm1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM1_MODE_MASK, + GPIO_PCM1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM2_MODE_MASK, + GPIO_PCM2_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group spi_func_group[] = { + { + .name = "spi_quad", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_QUAD_MODE_MASK, + GPIO_SPI_QUAD_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS1_MODE_MASK, + GPIO_SPI_CS1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS2_MODE_MASK, + GPIO_SPI_CS2_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs3", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS3_MODE_MASK, + GPIO_SPI_CS3_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs4", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS4_MODE_MASK, + GPIO_SPI_CS4_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = { + { + .name = "pcm_spi", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_MODE_MASK, + GPIO_PCM_SPI_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_int", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_INT_MODE_MASK, + GPIO_PCM_INT_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_rst", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_RESET_MODE_MASK, + GPIO_PCM_RESET_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS1_MODE_MASK, + GPIO_PCM_SPI_CS1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs2_p128", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS2_MODE_P128_MASK, + GPIO_PCM_SPI_CS2_MODE_P128_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs2_p156", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS2_MODE_P156_MASK, + GPIO_PCM_SPI_CS2_MODE_P156_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs3", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS3_MODE_MASK, + GPIO_PCM_SPI_CS3_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs4", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS4_MODE_MASK, + GPIO_PCM_SPI_CS4_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group i2s_func_group[] = { + { + .name = "i2s", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_I2S_MODE_MASK, + GPIO_I2S_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group emmc_func_group[] = { + { + .name = "emmc", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_EMMC_MODE_MASK, + GPIO_EMMC_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pnand_func_group[] = { + { + .name = "pnand", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PARALLEL_NAND_MODE_MASK, + GPIO_PARALLEL_NAND_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group gpio_func_group[] = { + AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG, + GPIO_PCIE_RESET0_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG, + GPIO_PCIE_RESET1_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG, + GPIO_PCIE_RESET2_MASK), +}; + +static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = { + { + .name = "pcie_reset0", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET0_MASK, + 0 + }, + .regmap_size = 1, + }, { + .name = "pcie_reset1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET1_MASK, + 0 + }, + .regmap_size = 1, + }, { + .name = "pcie_reset2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET2_MASK, + 0 + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pwm_func_group[] = { + AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG, + GPIO_PCIE_RESET0_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG, + GPIO_PCIE_RESET1_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG, + GPIO_PCIE_RESET2_MASK), +}; + +static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), +}; + +static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), +}; + +static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = { + PINCTRL_FUNC_DESC("pon", pon), + PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), + PINCTRL_FUNC_DESC("sipo", sipo), + PINCTRL_FUNC_DESC("mdio", mdio), + PINCTRL_FUNC_DESC("uart", uart), + PINCTRL_FUNC_DESC("i2c", i2c), + PINCTRL_FUNC_DESC("jtag", jtag), + PINCTRL_FUNC_DESC("pcm", pcm), + PINCTRL_FUNC_DESC("spi", spi), + PINCTRL_FUNC_DESC("pcm_spi", pcm_spi), + PINCTRL_FUNC_DESC("i2s", i2s), + PINCTRL_FUNC_DESC("emmc", emmc), + PINCTRL_FUNC_DESC("pnand", pnand), + PINCTRL_FUNC_DESC("gpio", gpio), + PINCTRL_FUNC_DESC("pcie_reset", pcie_reset), + PINCTRL_FUNC_DESC("pwm", pwm), + PINCTRL_FUNC_DESC("phy1_led0", phy1_led0), + PINCTRL_FUNC_DESC("phy2_led0", phy2_led0), + PINCTRL_FUNC_DESC("phy3_led0", phy3_led0), + PINCTRL_FUNC_DESC("phy4_led0", phy4_led0), + PINCTRL_FUNC_DESC("phy1_led1", phy1_led1), + PINCTRL_FUNC_DESC("phy2_led1", phy2_led1), + PINCTRL_FUNC_DESC("phy3_led1", phy3_led1), + PINCTRL_FUNC_DESC("phy4_led1", phy4_led1), +}; + +static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = { + PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), + PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), + PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), + PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), + PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), + PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), + PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(19)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)), + PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)), + PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)), + PINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)), + PINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)), + PINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)), + PINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)), + PINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)), + PINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)), + PINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)), + PINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)), + PINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)), + PINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)), + PINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)), + PINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)), + PINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)), + PINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)), + PINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)), + PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)), + PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)), + PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)), + PINCTRL_CONF_DESC(60, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), + PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), + PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK), +}; + +static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = { + PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), + PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), + PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), + PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), + PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), + PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), + PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(19)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)), + PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)), + PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)), + PINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)), + PINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)), + PINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)), + PINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)), + PINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)), + PINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)), + PINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)), + PINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)), + PINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)), + PINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)), + PINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)), + PINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)), + PINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)), + PINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)), + PINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)), + PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)), + PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)), + PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)), + PINCTRL_CONF_DESC(60, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), + PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), + PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK), +}; + +static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = { + PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), + PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), + PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), + PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), + PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), + PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), + PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(19)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)), + PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)), + PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)), + PINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)), + PINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)), + PINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)), + PINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)), + PINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)), + PINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)), + PINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)), + PINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)), + PINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)), + PINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)), + PINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)), + PINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)), + PINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)), + PINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)), + PINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)), + PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)), + PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)), + PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)), + PINCTRL_CONF_DESC(60, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), + PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), + PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK), +}; + +static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = { + PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), + PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), + PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), + PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), + PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), + PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), + PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(19)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)), + PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)), + PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)), + PINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)), + PINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)), + PINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)), + PINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)), + PINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)), + PINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)), + PINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)), + PINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)), + PINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)), + PINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)), + PINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)), + PINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)), + PINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)), + PINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)), + PINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)), + PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)), + PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)), + PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)), + PINCTRL_CONF_DESC(60, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), + PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), + PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK), +}; + +static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = { + PINCTRL_CONF_DESC(60, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), + PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), + PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK), +}; + +static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = { + .pinctrl_name = KBUILD_MODNAME, + .pinctrl_owner = THIS_MODULE, + .pins = en7581_pinctrl_pins, + .num_pins = ARRAY_SIZE(en7581_pinctrl_pins), + .grps = en7581_pinctrl_groups, + .num_grps = ARRAY_SIZE(en7581_pinctrl_groups), + .funcs = en7581_pinctrl_funcs, + .num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs), + .confs_info = { + [AIROHA_PINCTRL_CONFS_PULLUP] = { + .confs = en7581_pinctrl_pullup_conf, + .num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf), + }, + [AIROHA_PINCTRL_CONFS_PULLDOWN] = { + .confs = en7581_pinctrl_pulldown_conf, + .num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E2] = { + .confs = en7581_pinctrl_drive_e2_conf, + .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E4] = { + .confs = en7581_pinctrl_drive_e4_conf, + .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf), + }, + [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = { + .confs = en7581_pinctrl_pcie_rst_od_conf, + .num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf), + }, + }, +}; + +static const struct of_device_id airoha_pinctrl_of_match[] = { + { .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match); + +static struct platform_driver airoha_pinctrl_driver = { + .probe = airoha_pinctrl_probe, + .driver = { + .name = "pinctrl-airoha-an7581", + .of_match_table = airoha_pinctrl_of_match, + }, +}; +module_platform_driver(airoha_pinctrl_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Lorenzo Bianconi "); +MODULE_AUTHOR("Benjamin Larsson "); +MODULE_AUTHOR("Markus Gothe "); +MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7581 SoC"); diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c new file mode 100644 index 000000000000..bf053767fdb5 --- /dev/null +++ b/drivers/pinctrl/airoha/pinctrl-an7583.c @@ -0,0 +1,1476 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: Lorenzo Bianconi + * Author: Benjamin Larsson + * Author: Markus Gothe + */ + +#include "airoha-common.h" + +/* MUX */ +#define REG_GPIO_2ND_I2C_MODE 0x0214 +#define GPIO_LAN3_LED1_MODE_MASK BIT(10) +#define GPIO_LAN3_LED0_MODE_MASK BIT(9) +#define GPIO_LAN2_LED1_MODE_MASK BIT(8) +#define GPIO_LAN2_LED0_MODE_MASK BIT(7) +#define GPIO_LAN1_LED1_MODE_MASK BIT(6) +#define GPIO_LAN1_LED0_MODE_MASK BIT(5) +#define GPIO_LAN0_LED1_MODE_MASK BIT(4) +#define GPIO_LAN0_LED0_MODE_MASK BIT(3) +#define PON_TOD_1PPS_MODE_MASK BIT(2) +#define GSW_TOD_1PPS_MODE_MASK BIT(1) + +#define REG_GPIO_SPI_CS1_MODE 0x0218 +#define GPIO_MDC_IO_MASTER_MODE_MASK BIT(22) +#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21) +#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20) +#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK BIT(18) +#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17) +#define GPIO_PCM_SPI_MODE_MASK BIT(16) +#define GPIO_PCM2_MODE_MASK BIT(13) +#define GPIO_PCM1_MODE_MASK BIT(12) +#define GPIO_PCM_INT_MODE_MASK BIT(9) +#define GPIO_PCM_RESET_MODE_MASK BIT(8) +#define GPIO_SPI_QUAD_MODE_MASK BIT(4) +#define GPIO_SPI_CS4_MODE_MASK BIT(3) +#define GPIO_SPI_CS3_MODE_MASK BIT(2) +#define GPIO_SPI_CS2_MODE_MASK BIT(1) +#define GPIO_SPI_CS1_MODE_MASK BIT(0) + +#define REG_GPIO_PON_MODE 0x021c +#define AN7583_MDIO_0_GPIO_MODE_MASK BIT(26) +#define AN7583_MDC_0_GPIO_MODE_MASK BIT(25) +#define AN7583_UART_RXD_GPIO_MODE_MASK BIT(24) +#define AN7583_UART_TXD_GPIO_MODE_MASK BIT(23) +#define AN7583_SPI_MISO_GPIO_MODE_MASK BIT(22) +#define AN7583_SPI_MOSI_GPIO_MODE_MASK BIT(21) +#define AN7583_SPI_CS_GPIO_MODE_MASK BIT(20) +#define AN7583_SPI_CLK_GPIO_MODE_MASK BIT(19) +#define AN7583_I2C1_SDA_GPIO_MODE_MASK BIT(18) +#define AN7583_I2C1_SCL_GPIO_MODE_MASK BIT(17) +#define AN7583_I2C0_SDA_GPIO_MODE_MASK BIT(16) +#define AN7583_I2C0_SCL_GPIO_MODE_MASK BIT(15) +#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14) +#define GPIO_SGMII_MDIO_MODE_MASK BIT(13) +#define SIPO_RCLK_MODE_MASK BIT(11) +#define GPIO_PCIE_RESET1_MASK BIT(10) +#define GPIO_PCIE_RESET0_MASK BIT(9) +#define GPIO_UART5_MODE_MASK BIT(8) +#define GPIO_UART4_MODE_MASK BIT(7) +#define GPIO_HSUART_CTS_RTS_MODE_MASK BIT(6) +#define GPIO_HSUART_MODE_MASK BIT(5) +#define GPIO_UART2_CTS_RTS_MODE_MASK BIT(4) +#define GPIO_UART2_MODE_MASK BIT(3) +#define GPIO_SIPO_MODE_MASK BIT(2) +#define GPIO_EMMC_MODE_MASK BIT(1) +#define GPIO_PON_MODE_MASK BIT(0) + +#define REG_NPU_UART_EN 0x0224 +#define JTAG_UDI_EN_MASK BIT(4) +#define JTAG_DFD_EN_MASK BIT(3) + +#define REG_FORCE_GPIO_EN 0x0228 +#define FORCE_GPIO_EN(n) BIT(n) + +/* LED MAP */ +#define REG_LAN_LED0_MAPPING 0x027c +#define REG_LAN_LED1_MAPPING 0x0280 + +#define LAN4_LED_MAPPING_MASK GENMASK(18, 16) +#define LAN4_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n)) + +#define LAN3_LED_MAPPING_MASK GENMASK(14, 12) +#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n)) + +#define LAN2_LED_MAPPING_MASK GENMASK(10, 8) +#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n)) + +#define LAN1_LED_MAPPING_MASK GENMASK(6, 4) +#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n)) + +#define LAN0_LED_MAPPING_MASK GENMASK(2, 0) +#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n)) + +/* CONF */ +#define REG_I2C_SDA_E2 0x001c +#define AN7583_I2C1_SCL_E2_MASK BIT(16) +#define AN7583_I2C1_SDA_E2_MASK BIT(15) +#define SPI_MISO_E2_MASK BIT(14) +#define SPI_MOSI_E2_MASK BIT(13) +#define SPI_CLK_E2_MASK BIT(12) +#define SPI_CS0_E2_MASK BIT(11) +#define PCIE1_RESET_E2_MASK BIT(9) +#define PCIE0_RESET_E2_MASK BIT(8) +#define AN7583_MDIO_0_E2_MASK BIT(5) +#define AN7583_MDC_0_E2_MASK BIT(4) +#define UART1_RXD_E2_MASK BIT(3) +#define UART1_TXD_E2_MASK BIT(2) +#define I2C_SCL_E2_MASK BIT(1) +#define I2C_SDA_E2_MASK BIT(0) + +#define REG_I2C_SDA_E4 0x0020 +#define AN7583_I2C1_SCL_E4_MASK BIT(16) +#define AN7583_I2C1_SDA_E4_MASK BIT(15) +#define SPI_MISO_E4_MASK BIT(14) +#define SPI_MOSI_E4_MASK BIT(13) +#define SPI_CLK_E4_MASK BIT(12) +#define SPI_CS0_E4_MASK BIT(11) +#define PCIE1_RESET_E4_MASK BIT(9) +#define PCIE0_RESET_E4_MASK BIT(8) +#define AN7583_MDIO_0_E4_MASK BIT(5) +#define AN7583_MDC_0_E4_MASK BIT(4) +#define UART1_RXD_E4_MASK BIT(3) +#define UART1_TXD_E4_MASK BIT(2) +#define I2C_SCL_E4_MASK BIT(1) +#define I2C_SDA_E4_MASK BIT(0) + +#define REG_GPIO_L_E2 0x0024 +#define REG_GPIO_L_E4 0x0028 +#define REG_GPIO_H_E2 0x002c +#define REG_GPIO_H_E4 0x0030 + +#define REG_I2C_SDA_PU 0x0044 +#define AN7583_I2C1_SCL_PU_MASK BIT(16) +#define AN7583_I2C1_SDA_PU_MASK BIT(15) +#define SPI_MISO_PU_MASK BIT(14) +#define SPI_MOSI_PU_MASK BIT(13) +#define SPI_CLK_PU_MASK BIT(12) +#define SPI_CS0_PU_MASK BIT(11) +#define PCIE1_RESET_PU_MASK BIT(9) +#define PCIE0_RESET_PU_MASK BIT(8) +#define AN7583_MDIO_0_PU_MASK BIT(5) +#define AN7583_MDC_0_PU_MASK BIT(4) +#define UART1_RXD_PU_MASK BIT(3) +#define UART1_TXD_PU_MASK BIT(2) +#define I2C_SCL_PU_MASK BIT(1) +#define I2C_SDA_PU_MASK BIT(0) + +#define REG_I2C_SDA_PD 0x0048 +#define AN7583_I2C1_SCL_PD_MASK BIT(16) +#define AN7583_I2C1_SDA_PD_MASK BIT(15) +#define SPI_MISO_PD_MASK BIT(14) +#define SPI_MOSI_PD_MASK BIT(13) +#define SPI_CLK_PD_MASK BIT(12) +#define SPI_CS0_PD_MASK BIT(11) +#define PCIE1_RESET_PD_MASK BIT(9) +#define PCIE0_RESET_PD_MASK BIT(8) +#define AN7583_MDIO_0_PD_MASK BIT(5) +#define AN7583_MDC_0_PD_MASK BIT(4) +#define UART1_RXD_PD_MASK BIT(3) +#define UART1_TXD_PD_MASK BIT(2) +#define I2C_SCL_PD_MASK BIT(1) +#define I2C_SDA_PD_MASK BIT(0) + +#define REG_GPIO_L_PU 0x004c +#define REG_GPIO_L_PD 0x0050 +#define REG_GPIO_H_PU 0x0054 +#define REG_GPIO_H_PD 0x0058 + +#define REG_PCIE_RESET_OD 0x018c +#define PCIE1_RESET_OD_MASK BIT(1) +#define PCIE0_RESET_OD_MASK BIT(0) + +/* PWM MODE CONF */ +#define REG_GPIO_FLASH_MODE_CFG 0x0034 +#define GPIO15_FLASH_MODE_CFG BIT(15) +#define GPIO14_FLASH_MODE_CFG BIT(14) +#define GPIO13_FLASH_MODE_CFG BIT(13) +#define GPIO12_FLASH_MODE_CFG BIT(12) +#define GPIO11_FLASH_MODE_CFG BIT(11) +#define GPIO10_FLASH_MODE_CFG BIT(10) +#define GPIO9_FLASH_MODE_CFG BIT(9) +#define GPIO8_FLASH_MODE_CFG BIT(8) +#define GPIO7_FLASH_MODE_CFG BIT(7) +#define GPIO6_FLASH_MODE_CFG BIT(6) +#define GPIO5_FLASH_MODE_CFG BIT(5) +#define GPIO4_FLASH_MODE_CFG BIT(4) +#define GPIO3_FLASH_MODE_CFG BIT(3) +#define GPIO2_FLASH_MODE_CFG BIT(2) +#define GPIO1_FLASH_MODE_CFG BIT(1) +#define GPIO0_FLASH_MODE_CFG BIT(0) + +/* PWM MODE CONF EXT */ +#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068 +#define GPIO51_FLASH_MODE_CFG BIT(31) +#define GPIO50_FLASH_MODE_CFG BIT(30) +#define GPIO49_FLASH_MODE_CFG BIT(29) +#define GPIO48_FLASH_MODE_CFG BIT(28) +#define GPIO47_FLASH_MODE_CFG BIT(27) +#define GPIO46_FLASH_MODE_CFG BIT(26) +#define GPIO45_FLASH_MODE_CFG BIT(25) +#define GPIO44_FLASH_MODE_CFG BIT(24) +#define GPIO43_FLASH_MODE_CFG BIT(23) +#define GPIO42_FLASH_MODE_CFG BIT(22) +#define GPIO41_FLASH_MODE_CFG BIT(21) +#define GPIO40_FLASH_MODE_CFG BIT(20) +#define GPIO39_FLASH_MODE_CFG BIT(19) +#define GPIO38_FLASH_MODE_CFG BIT(18) +#define GPIO37_FLASH_MODE_CFG BIT(17) +#define GPIO36_FLASH_MODE_CFG BIT(16) +#define GPIO31_FLASH_MODE_CFG BIT(15) +#define GPIO30_FLASH_MODE_CFG BIT(14) +#define GPIO29_FLASH_MODE_CFG BIT(13) +#define GPIO28_FLASH_MODE_CFG BIT(12) +#define GPIO27_FLASH_MODE_CFG BIT(11) +#define GPIO26_FLASH_MODE_CFG BIT(10) +#define GPIO25_FLASH_MODE_CFG BIT(9) +#define GPIO24_FLASH_MODE_CFG BIT(8) +#define GPIO23_FLASH_MODE_CFG BIT(7) +#define GPIO22_FLASH_MODE_CFG BIT(6) +#define GPIO21_FLASH_MODE_CFG BIT(5) +#define GPIO20_FLASH_MODE_CFG BIT(4) +#define GPIO19_FLASH_MODE_CFG BIT(3) +#define GPIO18_FLASH_MODE_CFG BIT(2) +#define GPIO17_FLASH_MODE_CFG BIT(1) +#define GPIO16_FLASH_MODE_CFG BIT(0) + +#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + 0 \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (smux_val), \ + (smux_val) \ + }, \ + .regmap_size = 2, \ + } + +/* PWM */ +#define AIROHA_PINCTRL_PWM(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_MUX, \ + REG_GPIO_FLASH_MODE_CFG, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (smux_val), \ + (smux_val) \ + }, \ + .regmap_size = 2, \ + } + +#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_2ND_I2C_MODE, \ + (mux_val), \ + (mux_val), \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_LAN_LED0_MAPPING, \ + (map_mask), \ + (map_val), \ + }, \ + .regmap_size = 2, \ + } + +#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_2ND_I2C_MODE, \ + (mux_val), \ + (mux_val), \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_LAN_LED1_MAPPING, \ + (map_mask), \ + (map_val), \ + }, \ + .regmap_size = 2, \ + } + +static struct pinctrl_pin_desc an7583_pinctrl_pins[] = { + PINCTRL_PIN(2, "gpio0"), + PINCTRL_PIN(3, "gpio1"), + PINCTRL_PIN(4, "gpio2"), + PINCTRL_PIN(5, "gpio3"), + PINCTRL_PIN(6, "gpio4"), + PINCTRL_PIN(7, "gpio5"), + PINCTRL_PIN(8, "gpio6"), + PINCTRL_PIN(9, "gpio7"), + PINCTRL_PIN(10, "gpio8"), + PINCTRL_PIN(11, "gpio9"), + PINCTRL_PIN(12, "gpio10"), + PINCTRL_PIN(13, "gpio11"), + PINCTRL_PIN(14, "gpio12"), + PINCTRL_PIN(15, "gpio13"), + PINCTRL_PIN(16, "gpio14"), + PINCTRL_PIN(17, "gpio15"), + PINCTRL_PIN(18, "gpio16"), + PINCTRL_PIN(19, "gpio17"), + PINCTRL_PIN(20, "gpio18"), + PINCTRL_PIN(21, "gpio19"), + PINCTRL_PIN(22, "gpio20"), + PINCTRL_PIN(23, "gpio21"), + PINCTRL_PIN(24, "gpio22"), + PINCTRL_PIN(25, "gpio23"), + PINCTRL_PIN(26, "gpio24"), + PINCTRL_PIN(27, "gpio25"), + PINCTRL_PIN(28, "gpio26"), + PINCTRL_PIN(29, "gpio27"), + PINCTRL_PIN(30, "gpio28"), + PINCTRL_PIN(31, "gpio29"), + PINCTRL_PIN(32, "gpio30"), + PINCTRL_PIN(33, "gpio31"), + PINCTRL_PIN(34, "gpio32"), + PINCTRL_PIN(35, "gpio33"), + PINCTRL_PIN(36, "gpio34"), + PINCTRL_PIN(37, "gpio35"), + PINCTRL_PIN(38, "gpio36"), + PINCTRL_PIN(39, "gpio37"), + PINCTRL_PIN(40, "gpio38"), + PINCTRL_PIN(41, "i2c0_scl"), + PINCTRL_PIN(42, "i2c0_sda"), + PINCTRL_PIN(43, "i2c1_scl"), + PINCTRL_PIN(44, "i2c1_sda"), + PINCTRL_PIN(45, "spi_clk"), + PINCTRL_PIN(46, "spi_cs"), + PINCTRL_PIN(47, "spi_mosi"), + PINCTRL_PIN(48, "spi_miso"), + PINCTRL_PIN(49, "uart_txd"), + PINCTRL_PIN(50, "uart_rxd"), + PINCTRL_PIN(51, "pcie_reset0"), + PINCTRL_PIN(52, "pcie_reset1"), + PINCTRL_PIN(53, "mdc_0"), + PINCTRL_PIN(54, "mdio_0"), +}; + +static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 }; +static const int an7583_pon_tod_1pps_pins[] = { 32 }; +static const int an7583_gsw_tod_1pps_pins[] = { 32 }; +static const int an7583_sipo_pins[] = { 34, 35 }; +static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 }; +static const int an7583_mdio_pins[] = { 53, 54 }; +static const int an7583_mdio1_pins[] = { 43, 44 }; +static const int an7583_uart2_pins[] = { 34, 35 }; +static const int an7583_uart2_cts_rts_pins[] = { 32, 33 }; +static const int an7583_hsuart_pins[] = { 30, 31 }; +static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 }; +static const int an7583_npu_uart_pins[] = { 7, 8 }; +static const int an7583_uart4_pins[] = { 7, 8 }; +static const int an7583_uart5_pins[] = { 23, 24 }; +static const int an7583_i2c0_pins[] = { 41, 42 }; +static const int an7583_i2c1_pins[] = { 43, 44 }; +static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 }; +static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 }; +static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 }; +static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 }; +static const int an7583_spi_pins[] = { 45, 46, 47, 48 }; +static const int an7583_spi_quad_pins[] = { 25, 26 }; +static const int an7583_spi_cs1_pins[] = { 27 }; +static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 }; +static const int an7583_pcm_spi_rst_pins[] = { 14 }; +static const int an7583_pcm_spi_cs1_pins[] = { 24 }; +static const int an7583_emmc_pins[] = { + 7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47 +}; +static const int an7583_pnand_pins[] = { + 7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48 +}; +static const int an7583_gpio0_pins[] = { 2 }; +static const int an7583_gpio1_pins[] = { 3 }; +static const int an7583_gpio2_pins[] = { 4 }; +static const int an7583_gpio3_pins[] = { 5 }; +static const int an7583_gpio4_pins[] = { 6 }; +static const int an7583_gpio5_pins[] = { 7 }; +static const int an7583_gpio6_pins[] = { 8 }; +static const int an7583_gpio7_pins[] = { 9 }; +static const int an7583_gpio8_pins[] = { 10 }; +static const int an7583_gpio9_pins[] = { 11 }; +static const int an7583_gpio10_pins[] = { 12 }; +static const int an7583_gpio11_pins[] = { 13 }; +static const int an7583_gpio12_pins[] = { 14 }; +static const int an7583_gpio13_pins[] = { 15 }; +static const int an7583_gpio14_pins[] = { 16 }; +static const int an7583_gpio15_pins[] = { 17 }; +static const int an7583_gpio16_pins[] = { 18 }; +static const int an7583_gpio17_pins[] = { 19 }; +static const int an7583_gpio18_pins[] = { 20 }; +static const int an7583_gpio19_pins[] = { 21 }; +static const int an7583_gpio20_pins[] = { 22 }; +static const int an7583_gpio21_pins[] = { 23 }; +static const int an7583_gpio22_pins[] = { 24 }; +static const int an7583_gpio23_pins[] = { 25 }; +static const int an7583_gpio24_pins[] = { 26 }; +static const int an7583_gpio25_pins[] = { 27 }; +static const int an7583_gpio26_pins[] = { 28 }; +static const int an7583_gpio27_pins[] = { 29 }; +static const int an7583_gpio28_pins[] = { 30 }; +static const int an7583_gpio29_pins[] = { 31 }; +static const int an7583_gpio30_pins[] = { 32 }; +static const int an7583_gpio31_pins[] = { 33 }; +static const int an7583_gpio32_pins[] = { 34 }; +static const int an7583_gpio33_pins[] = { 35 }; +static const int an7583_gpio34_pins[] = { 36 }; +static const int an7583_gpio35_pins[] = { 37 }; +static const int an7583_gpio36_pins[] = { 38 }; +static const int an7583_gpio37_pins[] = { 39 }; +static const int an7583_gpio38_pins[] = { 40 }; +static const int an7583_gpio39_pins[] = { 41 }; +static const int an7583_gpio40_pins[] = { 42 }; +static const int an7583_gpio41_pins[] = { 43 }; +static const int an7583_gpio42_pins[] = { 44 }; +static const int an7583_gpio43_pins[] = { 45 }; +static const int an7583_gpio44_pins[] = { 46 }; +static const int an7583_gpio45_pins[] = { 47 }; +static const int an7583_gpio46_pins[] = { 48 }; +static const int an7583_gpio47_pins[] = { 49 }; +static const int an7583_gpio48_pins[] = { 50 }; +static const int an7583_gpio49_pins[] = { 51 }; +static const int an7583_gpio50_pins[] = { 52 }; +static const int an7583_gpio51_pins[] = { 53 }; +static const int an7583_gpio52_pins[] = { 54 }; +static const int an7583_pcie_reset0_pins[] = { 51 }; +static const int an7583_pcie_reset1_pins[] = { 52 }; + +static const struct pingroup an7583_pinctrl_groups[] = { + PINCTRL_PIN_GROUP("pon", an7583_pon), + PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps), + PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps), + PINCTRL_PIN_GROUP("sipo", an7583_sipo), + PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk), + PINCTRL_PIN_GROUP("mdio", an7583_mdio), + PINCTRL_PIN_GROUP("mdio1", an7583_mdio1), + PINCTRL_PIN_GROUP("uart2", an7583_uart2), + PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts), + PINCTRL_PIN_GROUP("hsuart", an7583_hsuart), + PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts), + PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart), + PINCTRL_PIN_GROUP("uart4", an7583_uart4), + PINCTRL_PIN_GROUP("uart5", an7583_uart5), + PINCTRL_PIN_GROUP("i2c0", an7583_i2c0), + PINCTRL_PIN_GROUP("i2c1", an7583_i2c1), + PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi), + PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd), + PINCTRL_PIN_GROUP("pcm1", an7583_pcm1), + PINCTRL_PIN_GROUP("pcm2", an7583_pcm2), + PINCTRL_PIN_GROUP("spi", an7583_spi), + PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad), + PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1), + PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi), + PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst), + PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1), + PINCTRL_PIN_GROUP("emmc", an7583_emmc), + PINCTRL_PIN_GROUP("pnand", an7583_pnand), + PINCTRL_PIN_GROUP("gpio0", an7583_gpio0), + PINCTRL_PIN_GROUP("gpio1", an7583_gpio1), + PINCTRL_PIN_GROUP("gpio2", an7583_gpio2), + PINCTRL_PIN_GROUP("gpio3", an7583_gpio3), + PINCTRL_PIN_GROUP("gpio4", an7583_gpio4), + PINCTRL_PIN_GROUP("gpio5", an7583_gpio5), + PINCTRL_PIN_GROUP("gpio6", an7583_gpio6), + PINCTRL_PIN_GROUP("gpio7", an7583_gpio7), + PINCTRL_PIN_GROUP("gpio8", an7583_gpio8), + PINCTRL_PIN_GROUP("gpio9", an7583_gpio9), + PINCTRL_PIN_GROUP("gpio10", an7583_gpio10), + PINCTRL_PIN_GROUP("gpio11", an7583_gpio11), + PINCTRL_PIN_GROUP("gpio12", an7583_gpio12), + PINCTRL_PIN_GROUP("gpio13", an7583_gpio13), + PINCTRL_PIN_GROUP("gpio14", an7583_gpio14), + PINCTRL_PIN_GROUP("gpio15", an7583_gpio15), + PINCTRL_PIN_GROUP("gpio16", an7583_gpio16), + PINCTRL_PIN_GROUP("gpio17", an7583_gpio17), + PINCTRL_PIN_GROUP("gpio18", an7583_gpio18), + PINCTRL_PIN_GROUP("gpio19", an7583_gpio19), + PINCTRL_PIN_GROUP("gpio20", an7583_gpio20), + PINCTRL_PIN_GROUP("gpio21", an7583_gpio21), + PINCTRL_PIN_GROUP("gpio22", an7583_gpio22), + PINCTRL_PIN_GROUP("gpio23", an7583_gpio23), + PINCTRL_PIN_GROUP("gpio24", an7583_gpio24), + PINCTRL_PIN_GROUP("gpio25", an7583_gpio25), + PINCTRL_PIN_GROUP("gpio26", an7583_gpio26), + PINCTRL_PIN_GROUP("gpio27", an7583_gpio27), + PINCTRL_PIN_GROUP("gpio28", an7583_gpio28), + PINCTRL_PIN_GROUP("gpio29", an7583_gpio29), + PINCTRL_PIN_GROUP("gpio30", an7583_gpio30), + PINCTRL_PIN_GROUP("gpio31", an7583_gpio31), + PINCTRL_PIN_GROUP("gpio32", an7583_gpio32), + PINCTRL_PIN_GROUP("gpio33", an7583_gpio33), + PINCTRL_PIN_GROUP("gpio34", an7583_gpio34), + PINCTRL_PIN_GROUP("gpio35", an7583_gpio35), + PINCTRL_PIN_GROUP("gpio36", an7583_gpio36), + PINCTRL_PIN_GROUP("gpio37", an7583_gpio37), + PINCTRL_PIN_GROUP("gpio38", an7583_gpio38), + PINCTRL_PIN_GROUP("gpio39", an7583_gpio39), + PINCTRL_PIN_GROUP("gpio40", an7583_gpio40), + PINCTRL_PIN_GROUP("gpio41", an7583_gpio41), + PINCTRL_PIN_GROUP("gpio42", an7583_gpio42), + PINCTRL_PIN_GROUP("gpio43", an7583_gpio43), + PINCTRL_PIN_GROUP("gpio44", an7583_gpio44), + PINCTRL_PIN_GROUP("gpio45", an7583_gpio45), + PINCTRL_PIN_GROUP("gpio46", an7583_gpio46), + PINCTRL_PIN_GROUP("gpio47", an7583_gpio47), + PINCTRL_PIN_GROUP("gpio48", an7583_gpio48), + PINCTRL_PIN_GROUP("gpio49", an7583_gpio49), + PINCTRL_PIN_GROUP("gpio50", an7583_gpio50), + PINCTRL_PIN_GROUP("gpio51", an7583_gpio51), + PINCTRL_PIN_GROUP("gpio52", an7583_gpio52), + PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0), + PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1), +}; + +static const char *const pon_groups[] = { "pon" }; +static const char *const tod_1pps_groups[] = { + "pon_tod_1pps", "gsw_tod_1pps" +}; +static const char *const sipo_groups[] = { "sipo", "sipo_rclk" }; +static const char *const an7583_mdio_groups[] = { "mdio" }; +static const char *const uart_groups[] = { + "uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts", + "uart4", "uart5" +}; +static const char *const an7583_i2c_groups[] = { "i2c0", "i2c1" }; +static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" }; +static const char *const pcm_groups[] = { "pcm1", "pcm2" }; +static const char *const spi_groups[] = { "spi_quad", "spi_cs1" }; +static const char *const an7583_pcm_spi_groups[] = { + "pcm_spi", "pcm_spi_rst", "pcm_spi_cs1" +}; +static const char *const emmc_groups[] = { "emmc" }; +static const char *const pnand_groups[] = { "pnand" }; +static const char *const an7583_gpio_groups[] = { + "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", + "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", + "gpio49", "gpio50", "gpio51", "gpio52" +}; +static const char *const an7583_pcie_reset_groups[] = { + "pcie_reset0", "pcie_reset1" +}; +static const char *const an7583_pwm_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio36", "gpio37", "gpio38", "gpio39", + "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51" +}; +static const char *const an7583_phy1_led0_groups[] = { + "gpio1", "gpio2", "gpio3", "gpio4" +}; +static const char *const an7583_phy2_led0_groups[] = { + "gpio1", "gpio2", "gpio3", "gpio4" +}; +static const char *const an7583_phy3_led0_groups[] = { + "gpio1", "gpio2", "gpio3", "gpio4" +}; +static const char *const an7583_phy4_led0_groups[] = { + "gpio1", "gpio2", "gpio3", "gpio4" +}; +static const char *const an7583_phy1_led1_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; +static const char *const an7583_phy2_led1_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; +static const char *const an7583_phy3_led1_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; +static const char *const an7583_phy4_led1_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; + +static const struct airoha_pinctrl_func_group pon_func_group[] = { + { + .name = "pon", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PON_MODE_MASK, + GPIO_PON_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = { + { + .name = "pon_tod_1pps", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + PON_TOD_1PPS_MODE_MASK, + PON_TOD_1PPS_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "gsw_tod_1pps", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GSW_TOD_1PPS_MODE_MASK, + GSW_TOD_1PPS_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group sipo_func_group[] = { + { + .name = "sipo", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "sipo_rclk", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = { + { + .name = "mdio", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + AN7583_MDC_0_GPIO_MODE_MASK | AN7583_MDIO_0_GPIO_MODE_MASK, + 0 + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group uart_func_group[] = { + { + .name = "uart2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART2_MODE_MASK, + GPIO_UART2_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "uart2_cts_rts", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK, + GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "hsuart", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, + GPIO_HSUART_MODE_MASK + }, + .regmap_size = 1, + }, + { + .name = "hsuart_cts_rts", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "uart4", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART4_MODE_MASK, + GPIO_UART4_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "uart5", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART5_MODE_MASK, + GPIO_UART5_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group an7583_i2c_func_group[] = { + { + .name = "i2c0", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + AN7583_I2C0_SCL_GPIO_MODE_MASK | AN7583_I2C0_SDA_GPIO_MODE_MASK, + 0 + }, + .regmap_size = 1, + }, { + .name = "i2c1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + AN7583_I2C1_SCL_GPIO_MODE_MASK | AN7583_I2C1_SDA_GPIO_MODE_MASK, + 0 + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group jtag_func_group[] = { + { + .name = "jtag_udi", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + JTAG_UDI_EN_MASK, + JTAG_UDI_EN_MASK + }, + .regmap_size = 1, + }, { + .name = "jtag_dfd", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + JTAG_DFD_EN_MASK, + JTAG_DFD_EN_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pcm_func_group[] = { + { + .name = "pcm1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM1_MODE_MASK, + GPIO_PCM1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM2_MODE_MASK, + GPIO_PCM2_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group spi_func_group[] = { + { + .name = "spi_quad", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_QUAD_MODE_MASK, + GPIO_SPI_QUAD_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS1_MODE_MASK, + GPIO_SPI_CS1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS2_MODE_MASK, + GPIO_SPI_CS2_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs3", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS3_MODE_MASK, + GPIO_SPI_CS3_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs4", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS4_MODE_MASK, + GPIO_SPI_CS4_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = { + { + .name = "pcm_spi", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_MODE_MASK, + GPIO_PCM_SPI_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_int", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_INT_MODE_MASK, + GPIO_PCM_INT_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_rst", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_RESET_MODE_MASK, + GPIO_PCM_RESET_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS1_MODE_MASK, + GPIO_PCM_SPI_CS1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + AN7583_GPIO_PCM_SPI_CS2_MODE_MASK, + AN7583_GPIO_PCM_SPI_CS2_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs3", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS3_MODE_MASK, + GPIO_PCM_SPI_CS3_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs4", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS4_MODE_MASK, + GPIO_PCM_SPI_CS4_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group emmc_func_group[] = { + { + .name = "emmc", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_EMMC_MODE_MASK, + GPIO_EMMC_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pnand_func_group[] = { + { + .name = "pnand", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PARALLEL_NAND_MODE_MASK, + GPIO_PARALLEL_NAND_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = { + AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG, + AN7583_I2C0_SCL_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG, + AN7583_I2C0_SDA_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG, + AN7583_I2C1_SCL_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG, + AN7583_I2C1_SDA_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG, + AN7583_SPI_CLK_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG, + AN7583_SPI_CS_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG, + AN7583_SPI_MOSI_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG, + AN7583_SPI_MISO_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG, + AN7583_UART_TXD_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG, + AN7583_UART_RXD_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG, + GPIO_PCIE_RESET0_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG, + GPIO_PCIE_RESET1_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG, + AN7583_MDC_0_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK), +}; + +static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = { + { + .name = "pcie_reset0", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET0_MASK, + 0 + }, + .regmap_size = 1, + }, { + .name = "pcie_reset1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET1_MASK, + 0 + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = { + AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG, + AN7583_I2C0_SCL_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG, + AN7583_I2C0_SDA_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG, + AN7583_I2C1_SCL_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG, + AN7583_I2C1_SDA_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG, + AN7583_SPI_CLK_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG, + AN7583_SPI_CS_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG, + AN7583_SPI_MOSI_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG, + AN7583_SPI_MISO_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG, + AN7583_UART_TXD_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG, + AN7583_UART_RXD_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG, + GPIO_PCIE_RESET0_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG, + GPIO_PCIE_RESET1_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG, + AN7583_MDC_0_GPIO_MODE_MASK), +}; + +static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), +}; + +static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), +}; + +static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = { + PINCTRL_FUNC_DESC("pon", pon), + PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), + PINCTRL_FUNC_DESC("sipo", sipo), + PINCTRL_FUNC_DESC("mdio", an7583_mdio), + PINCTRL_FUNC_DESC("uart", uart), + PINCTRL_FUNC_DESC("i2c", an7583_i2c), + PINCTRL_FUNC_DESC("jtag", jtag), + PINCTRL_FUNC_DESC("pcm", pcm), + PINCTRL_FUNC_DESC("spi", spi), + PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi), + PINCTRL_FUNC_DESC("emmc", emmc), + PINCTRL_FUNC_DESC("pnand", pnand), + PINCTRL_FUNC_DESC("gpio", an7583_gpio), + PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset), + PINCTRL_FUNC_DESC("pwm", an7583_pwm), + PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0), + PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0), + PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0), + PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0), + PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1), + PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1), + PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1), + PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1), +}; + +static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = { + PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(19)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)), + PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)), + PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)), + PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)), + PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)), + PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)), + PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)), + PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), + PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), + PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK), + PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK), + PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), + PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), + PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), + PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK), + PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), + PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), + PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), + PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), + PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK), + PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK), +}; + +static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = { + PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(19)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)), + PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)), + PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)), + PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)), + PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)), + PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)), + PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)), + PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), + PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), + PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK), + PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK), + PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), + PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), + PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), + PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK), + PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), + PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), + PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), + PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), + PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK), + PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK), +}; + +static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = { + PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(19)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)), + PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)), + PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)), + PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)), + PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)), + PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)), + PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)), + PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), + PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), + PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK), + PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK), + PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), + PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), + PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), + PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK), + PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), + PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), + PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), + PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), + PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK), + PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK), +}; + +static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = { + PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(19)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)), + PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)), + PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)), + PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)), + PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)), + PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)), + PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)), + PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), + PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), + PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK), + PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK), + PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), + PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), + PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), + PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK), + PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), + PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), + PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), + PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), + PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK), + PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK), +}; + +static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = { + PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), + PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), +}; + +static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = { + .pinctrl_name = KBUILD_MODNAME, + .pinctrl_owner = THIS_MODULE, + .pins = an7583_pinctrl_pins, + .num_pins = ARRAY_SIZE(an7583_pinctrl_pins), + .grps = an7583_pinctrl_groups, + .num_grps = ARRAY_SIZE(an7583_pinctrl_groups), + .funcs = an7583_pinctrl_funcs, + .num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs), + .confs_info = { + [AIROHA_PINCTRL_CONFS_PULLUP] = { + .confs = an7583_pinctrl_pullup_conf, + .num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf), + }, + [AIROHA_PINCTRL_CONFS_PULLDOWN] = { + .confs = an7583_pinctrl_pulldown_conf, + .num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E2] = { + .confs = an7583_pinctrl_drive_e2_conf, + .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E4] = { + .confs = an7583_pinctrl_drive_e4_conf, + .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf), + }, + [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = { + .confs = an7583_pinctrl_pcie_rst_od_conf, + .num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf), + }, + }, +}; + +static const struct of_device_id airoha_pinctrl_of_match[] = { + { .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match); + +static struct platform_driver airoha_pinctrl_driver = { + .probe = airoha_pinctrl_probe, + .driver = { + .name = "pinctrl-airoha-an7583", + .of_match_table = airoha_pinctrl_of_match, + }, +}; +module_platform_driver(airoha_pinctrl_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Lorenzo Bianconi "); +MODULE_AUTHOR("Benjamin Larsson "); +MODULE_AUTHOR("Markus Gothe "); +MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7583 SoC"); From cb9b160da45cd4e317da4b4a72051f9eea97e539 Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:06:04 +0300 Subject: [PATCH 108/130] pinctrl: airoha: an7581: remove en7581 prefix from variable names We have only an7581 specific code in the pinctrl-an7581 kernel module, so 'en7581_' prefix is not necessary anymore. Remove it. Signed-off-by: Mikhail Kshevetskiy Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/pinctrl-an7581.c | 396 ++++++++++++------------ 1 file changed, 198 insertions(+), 198 deletions(-) diff --git a/drivers/pinctrl/airoha/pinctrl-an7581.c b/drivers/pinctrl/airoha/pinctrl-an7581.c index 7bb104d80589..cd2a78382bc6 100644 --- a/drivers/pinctrl/airoha/pinctrl-an7581.c +++ b/drivers/pinctrl/airoha/pinctrl-an7581.c @@ -316,7 +316,7 @@ .regmap_size = 2, \ } -static struct pinctrl_pin_desc en7581_pinctrl_pins[] = { +static struct pinctrl_pin_desc pinctrl_pins[] = { PINCTRL_PIN(0, "uart1_txd"), PINCTRL_PIN(1, "uart1_rxd"), PINCTRL_PIN(2, "i2c_scl"), @@ -377,184 +377,184 @@ static struct pinctrl_pin_desc en7581_pinctrl_pins[] = { PINCTRL_PIN(62, "pcie_reset2"), }; -static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 }; -static const int en7581_pon_tod_1pps_pins[] = { 46 }; -static const int en7581_gsw_tod_1pps_pins[] = { 46 }; -static const int en7581_sipo_pins[] = { 16, 17 }; -static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 }; -static const int en7581_mdio_pins[] = { 14, 15 }; -static const int en7581_uart2_pins[] = { 48, 55 }; -static const int en7581_uart2_cts_rts_pins[] = { 46, 47 }; -static const int en7581_hsuart_pins[] = { 28, 29 }; -static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 }; -static const int en7581_uart4_pins[] = { 38, 39 }; -static const int en7581_uart5_pins[] = { 18, 19 }; -static const int en7581_i2c0_pins[] = { 2, 3 }; -static const int en7581_i2c1_pins[] = { 14, 15 }; -static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 }; -static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 }; -static const int en7581_i2s_pins[] = { 26, 27, 28, 29 }; -static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 }; -static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 }; -static const int en7581_spi_quad_pins[] = { 32, 33 }; -static const int en7581_spi_pins[] = { 4, 5, 6, 7 }; -static const int en7581_spi_cs1_pins[] = { 34 }; -static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 }; -static const int en7581_pcm_spi_int_pins[] = { 14 }; -static const int en7581_pcm_spi_rst_pins[] = { 15 }; -static const int en7581_pcm_spi_cs1_pins[] = { 43 }; -static const int en7581_pcm_spi_cs2_pins[] = { 40 }; -static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 }; -static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 }; -static const int en7581_pcm_spi_cs3_pins[] = { 41 }; -static const int en7581_pcm_spi_cs4_pins[] = { 42 }; -static const int en7581_emmc_pins[] = { +static const int pon_pins[] = { 49, 50, 51, 52, 53, 54 }; +static const int pon_tod_1pps_pins[] = { 46 }; +static const int gsw_tod_1pps_pins[] = { 46 }; +static const int sipo_pins[] = { 16, 17 }; +static const int sipo_rclk_pins[] = { 16, 17, 43 }; +static const int mdio_pins[] = { 14, 15 }; +static const int uart2_pins[] = { 48, 55 }; +static const int uart2_cts_rts_pins[] = { 46, 47 }; +static const int hsuart_pins[] = { 28, 29 }; +static const int hsuart_cts_rts_pins[] = { 26, 27 }; +static const int uart4_pins[] = { 38, 39 }; +static const int uart5_pins[] = { 18, 19 }; +static const int i2c0_pins[] = { 2, 3 }; +static const int i2c1_pins[] = { 14, 15 }; +static const int jtag_udi_pins[] = { 16, 17, 18, 19, 20 }; +static const int jtag_dfd_pins[] = { 16, 17, 18, 19, 20 }; +static const int i2s_pins[] = { 26, 27, 28, 29 }; +static const int pcm1_pins[] = { 22, 23, 24, 25 }; +static const int pcm2_pins[] = { 18, 19, 20, 21 }; +static const int spi_quad_pins[] = { 32, 33 }; +static const int spi_pins[] = { 4, 5, 6, 7 }; +static const int spi_cs1_pins[] = { 34 }; +static const int pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 }; +static const int pcm_spi_int_pins[] = { 14 }; +static const int pcm_spi_rst_pins[] = { 15 }; +static const int pcm_spi_cs1_pins[] = { 43 }; +static const int pcm_spi_cs2_pins[] = { 40 }; +static const int pcm_spi_cs2_p128_pins[] = { 40 }; +static const int pcm_spi_cs2_p156_pins[] = { 40 }; +static const int pcm_spi_cs3_pins[] = { 41 }; +static const int pcm_spi_cs4_pins[] = { 42 }; +static const int emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 }; -static const int en7581_pnand_pins[] = { +static const int pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 }; -static const int en7581_gpio0_pins[] = { 13 }; -static const int en7581_gpio1_pins[] = { 14 }; -static const int en7581_gpio2_pins[] = { 15 }; -static const int en7581_gpio3_pins[] = { 16 }; -static const int en7581_gpio4_pins[] = { 17 }; -static const int en7581_gpio5_pins[] = { 18 }; -static const int en7581_gpio6_pins[] = { 19 }; -static const int en7581_gpio7_pins[] = { 20 }; -static const int en7581_gpio8_pins[] = { 21 }; -static const int en7581_gpio9_pins[] = { 22 }; -static const int en7581_gpio10_pins[] = { 23 }; -static const int en7581_gpio11_pins[] = { 24 }; -static const int en7581_gpio12_pins[] = { 25 }; -static const int en7581_gpio13_pins[] = { 26 }; -static const int en7581_gpio14_pins[] = { 27 }; -static const int en7581_gpio15_pins[] = { 28 }; -static const int en7581_gpio16_pins[] = { 29 }; -static const int en7581_gpio17_pins[] = { 30 }; -static const int en7581_gpio18_pins[] = { 31 }; -static const int en7581_gpio19_pins[] = { 32 }; -static const int en7581_gpio20_pins[] = { 33 }; -static const int en7581_gpio21_pins[] = { 34 }; -static const int en7581_gpio22_pins[] = { 35 }; -static const int en7581_gpio23_pins[] = { 36 }; -static const int en7581_gpio24_pins[] = { 37 }; -static const int en7581_gpio25_pins[] = { 38 }; -static const int en7581_gpio26_pins[] = { 39 }; -static const int en7581_gpio27_pins[] = { 40 }; -static const int en7581_gpio28_pins[] = { 41 }; -static const int en7581_gpio29_pins[] = { 42 }; -static const int en7581_gpio30_pins[] = { 43 }; -static const int en7581_gpio31_pins[] = { 44 }; -static const int en7581_gpio32_pins[] = { 45 }; -static const int en7581_gpio33_pins[] = { 46 }; -static const int en7581_gpio34_pins[] = { 47 }; -static const int en7581_gpio35_pins[] = { 48 }; -static const int en7581_gpio36_pins[] = { 49 }; -static const int en7581_gpio37_pins[] = { 50 }; -static const int en7581_gpio38_pins[] = { 51 }; -static const int en7581_gpio39_pins[] = { 52 }; -static const int en7581_gpio40_pins[] = { 53 }; -static const int en7581_gpio41_pins[] = { 54 }; -static const int en7581_gpio42_pins[] = { 55 }; -static const int en7581_gpio43_pins[] = { 56 }; -static const int en7581_gpio44_pins[] = { 57 }; -static const int en7581_gpio45_pins[] = { 58 }; -static const int en7581_gpio46_pins[] = { 59 }; -static const int en7581_gpio47_pins[] = { 60 }; -static const int en7581_gpio48_pins[] = { 61 }; -static const int en7581_gpio49_pins[] = { 62 }; -static const int en7581_pcie_reset0_pins[] = { 60 }; -static const int en7581_pcie_reset1_pins[] = { 61 }; -static const int en7581_pcie_reset2_pins[] = { 62 }; +static const int gpio0_pins[] = { 13 }; +static const int gpio1_pins[] = { 14 }; +static const int gpio2_pins[] = { 15 }; +static const int gpio3_pins[] = { 16 }; +static const int gpio4_pins[] = { 17 }; +static const int gpio5_pins[] = { 18 }; +static const int gpio6_pins[] = { 19 }; +static const int gpio7_pins[] = { 20 }; +static const int gpio8_pins[] = { 21 }; +static const int gpio9_pins[] = { 22 }; +static const int gpio10_pins[] = { 23 }; +static const int gpio11_pins[] = { 24 }; +static const int gpio12_pins[] = { 25 }; +static const int gpio13_pins[] = { 26 }; +static const int gpio14_pins[] = { 27 }; +static const int gpio15_pins[] = { 28 }; +static const int gpio16_pins[] = { 29 }; +static const int gpio17_pins[] = { 30 }; +static const int gpio18_pins[] = { 31 }; +static const int gpio19_pins[] = { 32 }; +static const int gpio20_pins[] = { 33 }; +static const int gpio21_pins[] = { 34 }; +static const int gpio22_pins[] = { 35 }; +static const int gpio23_pins[] = { 36 }; +static const int gpio24_pins[] = { 37 }; +static const int gpio25_pins[] = { 38 }; +static const int gpio26_pins[] = { 39 }; +static const int gpio27_pins[] = { 40 }; +static const int gpio28_pins[] = { 41 }; +static const int gpio29_pins[] = { 42 }; +static const int gpio30_pins[] = { 43 }; +static const int gpio31_pins[] = { 44 }; +static const int gpio32_pins[] = { 45 }; +static const int gpio33_pins[] = { 46 }; +static const int gpio34_pins[] = { 47 }; +static const int gpio35_pins[] = { 48 }; +static const int gpio36_pins[] = { 49 }; +static const int gpio37_pins[] = { 50 }; +static const int gpio38_pins[] = { 51 }; +static const int gpio39_pins[] = { 52 }; +static const int gpio40_pins[] = { 53 }; +static const int gpio41_pins[] = { 54 }; +static const int gpio42_pins[] = { 55 }; +static const int gpio43_pins[] = { 56 }; +static const int gpio44_pins[] = { 57 }; +static const int gpio45_pins[] = { 58 }; +static const int gpio46_pins[] = { 59 }; +static const int gpio47_pins[] = { 60 }; +static const int gpio48_pins[] = { 61 }; +static const int gpio49_pins[] = { 62 }; +static const int pcie_reset0_pins[] = { 60 }; +static const int pcie_reset1_pins[] = { 61 }; +static const int pcie_reset2_pins[] = { 62 }; -static const struct pingroup en7581_pinctrl_groups[] = { - PINCTRL_PIN_GROUP("pon", en7581_pon), - PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps), - PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps), - PINCTRL_PIN_GROUP("sipo", en7581_sipo), - PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk), - PINCTRL_PIN_GROUP("mdio", en7581_mdio), - PINCTRL_PIN_GROUP("uart2", en7581_uart2), - PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts), - PINCTRL_PIN_GROUP("hsuart", en7581_hsuart), - PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts), - PINCTRL_PIN_GROUP("uart4", en7581_uart4), - PINCTRL_PIN_GROUP("uart5", en7581_uart5), - PINCTRL_PIN_GROUP("i2c0", en7581_i2c0), - PINCTRL_PIN_GROUP("i2c1", en7581_i2c1), - PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi), - PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd), - PINCTRL_PIN_GROUP("i2s", en7581_i2s), - PINCTRL_PIN_GROUP("pcm1", en7581_pcm1), - PINCTRL_PIN_GROUP("pcm2", en7581_pcm2), - PINCTRL_PIN_GROUP("spi", en7581_spi), - PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad), - PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1), - PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi), - PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int), - PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst), - PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1), - PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128), - PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156), - PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2), - PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3), - PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4), - PINCTRL_PIN_GROUP("emmc", en7581_emmc), - PINCTRL_PIN_GROUP("pnand", en7581_pnand), - PINCTRL_PIN_GROUP("gpio0", en7581_gpio0), - PINCTRL_PIN_GROUP("gpio1", en7581_gpio1), - PINCTRL_PIN_GROUP("gpio2", en7581_gpio2), - PINCTRL_PIN_GROUP("gpio3", en7581_gpio3), - PINCTRL_PIN_GROUP("gpio4", en7581_gpio4), - PINCTRL_PIN_GROUP("gpio5", en7581_gpio5), - PINCTRL_PIN_GROUP("gpio6", en7581_gpio6), - PINCTRL_PIN_GROUP("gpio7", en7581_gpio7), - PINCTRL_PIN_GROUP("gpio8", en7581_gpio8), - PINCTRL_PIN_GROUP("gpio9", en7581_gpio9), - PINCTRL_PIN_GROUP("gpio10", en7581_gpio10), - PINCTRL_PIN_GROUP("gpio11", en7581_gpio11), - PINCTRL_PIN_GROUP("gpio12", en7581_gpio12), - PINCTRL_PIN_GROUP("gpio13", en7581_gpio13), - PINCTRL_PIN_GROUP("gpio14", en7581_gpio14), - PINCTRL_PIN_GROUP("gpio15", en7581_gpio15), - PINCTRL_PIN_GROUP("gpio16", en7581_gpio16), - PINCTRL_PIN_GROUP("gpio17", en7581_gpio17), - PINCTRL_PIN_GROUP("gpio18", en7581_gpio18), - PINCTRL_PIN_GROUP("gpio19", en7581_gpio19), - PINCTRL_PIN_GROUP("gpio20", en7581_gpio20), - PINCTRL_PIN_GROUP("gpio21", en7581_gpio21), - PINCTRL_PIN_GROUP("gpio22", en7581_gpio22), - PINCTRL_PIN_GROUP("gpio23", en7581_gpio23), - PINCTRL_PIN_GROUP("gpio24", en7581_gpio24), - PINCTRL_PIN_GROUP("gpio25", en7581_gpio25), - PINCTRL_PIN_GROUP("gpio26", en7581_gpio26), - PINCTRL_PIN_GROUP("gpio27", en7581_gpio27), - PINCTRL_PIN_GROUP("gpio28", en7581_gpio28), - PINCTRL_PIN_GROUP("gpio29", en7581_gpio29), - PINCTRL_PIN_GROUP("gpio30", en7581_gpio30), - PINCTRL_PIN_GROUP("gpio31", en7581_gpio31), - PINCTRL_PIN_GROUP("gpio32", en7581_gpio32), - PINCTRL_PIN_GROUP("gpio33", en7581_gpio33), - PINCTRL_PIN_GROUP("gpio34", en7581_gpio34), - PINCTRL_PIN_GROUP("gpio35", en7581_gpio35), - PINCTRL_PIN_GROUP("gpio36", en7581_gpio36), - PINCTRL_PIN_GROUP("gpio37", en7581_gpio37), - PINCTRL_PIN_GROUP("gpio38", en7581_gpio38), - PINCTRL_PIN_GROUP("gpio39", en7581_gpio39), - PINCTRL_PIN_GROUP("gpio40", en7581_gpio40), - PINCTRL_PIN_GROUP("gpio41", en7581_gpio41), - PINCTRL_PIN_GROUP("gpio42", en7581_gpio42), - PINCTRL_PIN_GROUP("gpio43", en7581_gpio43), - PINCTRL_PIN_GROUP("gpio44", en7581_gpio44), - PINCTRL_PIN_GROUP("gpio45", en7581_gpio45), - PINCTRL_PIN_GROUP("gpio46", en7581_gpio46), - PINCTRL_PIN_GROUP("gpio47", en7581_gpio47), - PINCTRL_PIN_GROUP("gpio48", en7581_gpio48), - PINCTRL_PIN_GROUP("gpio49", en7581_gpio49), - PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0), - PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1), - PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2), +static const struct pingroup pinctrl_groups[] = { + PINCTRL_PIN_GROUP("pon", pon), + PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps), + PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps), + PINCTRL_PIN_GROUP("sipo", sipo), + PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk), + PINCTRL_PIN_GROUP("mdio", mdio), + PINCTRL_PIN_GROUP("uart2", uart2), + PINCTRL_PIN_GROUP("uart2_cts_rts", uart2_cts_rts), + PINCTRL_PIN_GROUP("hsuart", hsuart), + PINCTRL_PIN_GROUP("hsuart_cts_rts", hsuart_cts_rts), + PINCTRL_PIN_GROUP("uart4", uart4), + PINCTRL_PIN_GROUP("uart5", uart5), + PINCTRL_PIN_GROUP("i2c0", i2c0), + PINCTRL_PIN_GROUP("i2c1", i2c1), + PINCTRL_PIN_GROUP("jtag_udi", jtag_udi), + PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd), + PINCTRL_PIN_GROUP("i2s", i2s), + PINCTRL_PIN_GROUP("pcm1", pcm1), + PINCTRL_PIN_GROUP("pcm2", pcm2), + PINCTRL_PIN_GROUP("spi", spi), + PINCTRL_PIN_GROUP("spi_quad", spi_quad), + PINCTRL_PIN_GROUP("spi_cs1", spi_cs1), + PINCTRL_PIN_GROUP("pcm_spi", pcm_spi), + PINCTRL_PIN_GROUP("pcm_spi_int", pcm_spi_int), + PINCTRL_PIN_GROUP("pcm_spi_rst", pcm_spi_rst), + PINCTRL_PIN_GROUP("pcm_spi_cs1", pcm_spi_cs1), + PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", pcm_spi_cs2_p128), + PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", pcm_spi_cs2_p156), + PINCTRL_PIN_GROUP("pcm_spi_cs2", pcm_spi_cs2), + PINCTRL_PIN_GROUP("pcm_spi_cs3", pcm_spi_cs3), + PINCTRL_PIN_GROUP("pcm_spi_cs4", pcm_spi_cs4), + PINCTRL_PIN_GROUP("emmc", emmc), + PINCTRL_PIN_GROUP("pnand", pnand), + PINCTRL_PIN_GROUP("gpio0", gpio0), + PINCTRL_PIN_GROUP("gpio1", gpio1), + PINCTRL_PIN_GROUP("gpio2", gpio2), + PINCTRL_PIN_GROUP("gpio3", gpio3), + PINCTRL_PIN_GROUP("gpio4", gpio4), + PINCTRL_PIN_GROUP("gpio5", gpio5), + PINCTRL_PIN_GROUP("gpio6", gpio6), + PINCTRL_PIN_GROUP("gpio7", gpio7), + PINCTRL_PIN_GROUP("gpio8", gpio8), + PINCTRL_PIN_GROUP("gpio9", gpio9), + PINCTRL_PIN_GROUP("gpio10", gpio10), + PINCTRL_PIN_GROUP("gpio11", gpio11), + PINCTRL_PIN_GROUP("gpio12", gpio12), + PINCTRL_PIN_GROUP("gpio13", gpio13), + PINCTRL_PIN_GROUP("gpio14", gpio14), + PINCTRL_PIN_GROUP("gpio15", gpio15), + PINCTRL_PIN_GROUP("gpio16", gpio16), + PINCTRL_PIN_GROUP("gpio17", gpio17), + PINCTRL_PIN_GROUP("gpio18", gpio18), + PINCTRL_PIN_GROUP("gpio19", gpio19), + PINCTRL_PIN_GROUP("gpio20", gpio20), + PINCTRL_PIN_GROUP("gpio21", gpio21), + PINCTRL_PIN_GROUP("gpio22", gpio22), + PINCTRL_PIN_GROUP("gpio23", gpio23), + PINCTRL_PIN_GROUP("gpio24", gpio24), + PINCTRL_PIN_GROUP("gpio25", gpio25), + PINCTRL_PIN_GROUP("gpio26", gpio26), + PINCTRL_PIN_GROUP("gpio27", gpio27), + PINCTRL_PIN_GROUP("gpio28", gpio28), + PINCTRL_PIN_GROUP("gpio29", gpio29), + PINCTRL_PIN_GROUP("gpio30", gpio30), + PINCTRL_PIN_GROUP("gpio31", gpio31), + PINCTRL_PIN_GROUP("gpio32", gpio32), + PINCTRL_PIN_GROUP("gpio33", gpio33), + PINCTRL_PIN_GROUP("gpio34", gpio34), + PINCTRL_PIN_GROUP("gpio35", gpio35), + PINCTRL_PIN_GROUP("gpio36", gpio36), + PINCTRL_PIN_GROUP("gpio37", gpio37), + PINCTRL_PIN_GROUP("gpio38", gpio38), + PINCTRL_PIN_GROUP("gpio39", gpio39), + PINCTRL_PIN_GROUP("gpio40", gpio40), + PINCTRL_PIN_GROUP("gpio41", gpio41), + PINCTRL_PIN_GROUP("gpio42", gpio42), + PINCTRL_PIN_GROUP("gpio43", gpio43), + PINCTRL_PIN_GROUP("gpio44", gpio44), + PINCTRL_PIN_GROUP("gpio45", gpio45), + PINCTRL_PIN_GROUP("gpio46", gpio46), + PINCTRL_PIN_GROUP("gpio47", gpio47), + PINCTRL_PIN_GROUP("gpio48", gpio48), + PINCTRL_PIN_GROUP("gpio49", gpio49), + PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0), + PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1), + PINCTRL_PIN_GROUP("pcie_reset2", pcie_reset2), }; static const char *const pon_groups[] = { "pon" }; @@ -1154,7 +1154,7 @@ static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = { LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), }; -static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = { +static const struct airoha_pinctrl_func pinctrl_funcs[] = { PINCTRL_FUNC_DESC("pon", pon), PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), PINCTRL_FUNC_DESC("sipo", sipo), @@ -1181,7 +1181,7 @@ static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = { PINCTRL_FUNC_DESC("phy4_led1", phy4_led1), }; -static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = { +static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = { PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), @@ -1242,7 +1242,7 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = { PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK), }; -static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = { +static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = { PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), @@ -1303,7 +1303,7 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = { PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK), }; -static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = { +static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = { PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), @@ -1364,7 +1364,7 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = { PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK), }; -static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = { +static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = { PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), @@ -1425,47 +1425,47 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = { PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK), }; -static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = { +static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = { PINCTRL_CONF_DESC(60, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK), }; -static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = { +static const struct airoha_pinctrl_match_data pinctrl_match_data = { .pinctrl_name = KBUILD_MODNAME, .pinctrl_owner = THIS_MODULE, - .pins = en7581_pinctrl_pins, - .num_pins = ARRAY_SIZE(en7581_pinctrl_pins), - .grps = en7581_pinctrl_groups, - .num_grps = ARRAY_SIZE(en7581_pinctrl_groups), - .funcs = en7581_pinctrl_funcs, - .num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs), + .pins = pinctrl_pins, + .num_pins = ARRAY_SIZE(pinctrl_pins), + .grps = pinctrl_groups, + .num_grps = ARRAY_SIZE(pinctrl_groups), + .funcs = pinctrl_funcs, + .num_funcs = ARRAY_SIZE(pinctrl_funcs), .confs_info = { [AIROHA_PINCTRL_CONFS_PULLUP] = { - .confs = en7581_pinctrl_pullup_conf, - .num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf), + .confs = pinctrl_pullup_conf, + .num_confs = ARRAY_SIZE(pinctrl_pullup_conf), }, [AIROHA_PINCTRL_CONFS_PULLDOWN] = { - .confs = en7581_pinctrl_pulldown_conf, - .num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf), + .confs = pinctrl_pulldown_conf, + .num_confs = ARRAY_SIZE(pinctrl_pulldown_conf), }, [AIROHA_PINCTRL_CONFS_DRIVE_E2] = { - .confs = en7581_pinctrl_drive_e2_conf, - .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf), + .confs = pinctrl_drive_e2_conf, + .num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf), }, [AIROHA_PINCTRL_CONFS_DRIVE_E4] = { - .confs = en7581_pinctrl_drive_e4_conf, - .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf), + .confs = pinctrl_drive_e4_conf, + .num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf), }, [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = { - .confs = en7581_pinctrl_pcie_rst_od_conf, - .num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf), + .confs = pinctrl_pcie_rst_od_conf, + .num_confs = ARRAY_SIZE(pinctrl_pcie_rst_od_conf), }, }, }; static const struct of_device_id airoha_pinctrl_of_match[] = { - { .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data }, + { .compatible = "airoha,en7581-pinctrl", .data = &pinctrl_match_data }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match); From bf3cdf90e37ef2621766be138dfc2ae62bfc11f3 Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:06:05 +0300 Subject: [PATCH 109/130] pinctrl: airoha: an7583: remove an7583 prefix from variable names and definitions We have only an7583 specific code in the pinctrl-an7583 kernel module, so an7583 prefix is not necessary anymore. Remove it. Signed-off-by: Mikhail Kshevetskiy Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/pinctrl-an7583.c | 614 ++++++++++++------------ 1 file changed, 307 insertions(+), 307 deletions(-) diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c index bf053767fdb5..6d195096495f 100644 --- a/drivers/pinctrl/airoha/pinctrl-an7583.c +++ b/drivers/pinctrl/airoha/pinctrl-an7583.c @@ -24,7 +24,7 @@ #define GPIO_MDC_IO_MASTER_MODE_MASK BIT(22) #define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21) #define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20) -#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK BIT(18) +#define GPIO_PCM_SPI_CS2_MODE_MASK BIT(18) #define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17) #define GPIO_PCM_SPI_MODE_MASK BIT(16) #define GPIO_PCM2_MODE_MASK BIT(13) @@ -38,18 +38,18 @@ #define GPIO_SPI_CS1_MODE_MASK BIT(0) #define REG_GPIO_PON_MODE 0x021c -#define AN7583_MDIO_0_GPIO_MODE_MASK BIT(26) -#define AN7583_MDC_0_GPIO_MODE_MASK BIT(25) -#define AN7583_UART_RXD_GPIO_MODE_MASK BIT(24) -#define AN7583_UART_TXD_GPIO_MODE_MASK BIT(23) -#define AN7583_SPI_MISO_GPIO_MODE_MASK BIT(22) -#define AN7583_SPI_MOSI_GPIO_MODE_MASK BIT(21) -#define AN7583_SPI_CS_GPIO_MODE_MASK BIT(20) -#define AN7583_SPI_CLK_GPIO_MODE_MASK BIT(19) -#define AN7583_I2C1_SDA_GPIO_MODE_MASK BIT(18) -#define AN7583_I2C1_SCL_GPIO_MODE_MASK BIT(17) -#define AN7583_I2C0_SDA_GPIO_MODE_MASK BIT(16) -#define AN7583_I2C0_SCL_GPIO_MODE_MASK BIT(15) +#define MDIO_0_GPIO_MODE_MASK BIT(26) +#define MDC_0_GPIO_MODE_MASK BIT(25) +#define UART_RXD_GPIO_MODE_MASK BIT(24) +#define UART_TXD_GPIO_MODE_MASK BIT(23) +#define SPI_MISO_GPIO_MODE_MASK BIT(22) +#define SPI_MOSI_GPIO_MODE_MASK BIT(21) +#define SPI_CS_GPIO_MODE_MASK BIT(20) +#define SPI_CLK_GPIO_MODE_MASK BIT(19) +#define I2C1_SDA_GPIO_MODE_MASK BIT(18) +#define I2C1_SCL_GPIO_MODE_MASK BIT(17) +#define I2C0_SDA_GPIO_MODE_MASK BIT(16) +#define I2C0_SCL_GPIO_MODE_MASK BIT(15) #define GPIO_PARALLEL_NAND_MODE_MASK BIT(14) #define GPIO_SGMII_MDIO_MODE_MASK BIT(13) #define SIPO_RCLK_MODE_MASK BIT(11) @@ -93,32 +93,32 @@ /* CONF */ #define REG_I2C_SDA_E2 0x001c -#define AN7583_I2C1_SCL_E2_MASK BIT(16) -#define AN7583_I2C1_SDA_E2_MASK BIT(15) +#define I2C1_SCL_E2_MASK BIT(16) +#define I2C1_SDA_E2_MASK BIT(15) #define SPI_MISO_E2_MASK BIT(14) #define SPI_MOSI_E2_MASK BIT(13) #define SPI_CLK_E2_MASK BIT(12) #define SPI_CS0_E2_MASK BIT(11) #define PCIE1_RESET_E2_MASK BIT(9) #define PCIE0_RESET_E2_MASK BIT(8) -#define AN7583_MDIO_0_E2_MASK BIT(5) -#define AN7583_MDC_0_E2_MASK BIT(4) +#define MDIO_0_E2_MASK BIT(5) +#define MDC_0_E2_MASK BIT(4) #define UART1_RXD_E2_MASK BIT(3) #define UART1_TXD_E2_MASK BIT(2) #define I2C_SCL_E2_MASK BIT(1) #define I2C_SDA_E2_MASK BIT(0) #define REG_I2C_SDA_E4 0x0020 -#define AN7583_I2C1_SCL_E4_MASK BIT(16) -#define AN7583_I2C1_SDA_E4_MASK BIT(15) +#define I2C1_SCL_E4_MASK BIT(16) +#define I2C1_SDA_E4_MASK BIT(15) #define SPI_MISO_E4_MASK BIT(14) #define SPI_MOSI_E4_MASK BIT(13) #define SPI_CLK_E4_MASK BIT(12) #define SPI_CS0_E4_MASK BIT(11) #define PCIE1_RESET_E4_MASK BIT(9) #define PCIE0_RESET_E4_MASK BIT(8) -#define AN7583_MDIO_0_E4_MASK BIT(5) -#define AN7583_MDC_0_E4_MASK BIT(4) +#define MDIO_0_E4_MASK BIT(5) +#define MDC_0_E4_MASK BIT(4) #define UART1_RXD_E4_MASK BIT(3) #define UART1_TXD_E4_MASK BIT(2) #define I2C_SCL_E4_MASK BIT(1) @@ -130,32 +130,32 @@ #define REG_GPIO_H_E4 0x0030 #define REG_I2C_SDA_PU 0x0044 -#define AN7583_I2C1_SCL_PU_MASK BIT(16) -#define AN7583_I2C1_SDA_PU_MASK BIT(15) +#define I2C1_SCL_PU_MASK BIT(16) +#define I2C1_SDA_PU_MASK BIT(15) #define SPI_MISO_PU_MASK BIT(14) #define SPI_MOSI_PU_MASK BIT(13) #define SPI_CLK_PU_MASK BIT(12) #define SPI_CS0_PU_MASK BIT(11) #define PCIE1_RESET_PU_MASK BIT(9) #define PCIE0_RESET_PU_MASK BIT(8) -#define AN7583_MDIO_0_PU_MASK BIT(5) -#define AN7583_MDC_0_PU_MASK BIT(4) +#define MDIO_0_PU_MASK BIT(5) +#define MDC_0_PU_MASK BIT(4) #define UART1_RXD_PU_MASK BIT(3) #define UART1_TXD_PU_MASK BIT(2) #define I2C_SCL_PU_MASK BIT(1) #define I2C_SDA_PU_MASK BIT(0) #define REG_I2C_SDA_PD 0x0048 -#define AN7583_I2C1_SCL_PD_MASK BIT(16) -#define AN7583_I2C1_SDA_PD_MASK BIT(15) +#define I2C1_SCL_PD_MASK BIT(16) +#define I2C1_SDA_PD_MASK BIT(15) #define SPI_MISO_PD_MASK BIT(14) #define SPI_MOSI_PD_MASK BIT(13) #define SPI_CLK_PD_MASK BIT(12) #define SPI_CS0_PD_MASK BIT(11) #define PCIE1_RESET_PD_MASK BIT(9) #define PCIE0_RESET_PD_MASK BIT(8) -#define AN7583_MDIO_0_PD_MASK BIT(5) -#define AN7583_MDC_0_PD_MASK BIT(4) +#define MDIO_0_PD_MASK BIT(5) +#define MDC_0_PD_MASK BIT(4) #define UART1_RXD_PD_MASK BIT(3) #define UART1_TXD_PD_MASK BIT(2) #define I2C_SCL_PD_MASK BIT(1) @@ -333,7 +333,7 @@ .regmap_size = 2, \ } -static struct pinctrl_pin_desc an7583_pinctrl_pins[] = { +static struct pinctrl_pin_desc pinctrl_pins[] = { PINCTRL_PIN(2, "gpio0"), PINCTRL_PIN(3, "gpio1"), PINCTRL_PIN(4, "gpio2"), @@ -389,178 +389,178 @@ static struct pinctrl_pin_desc an7583_pinctrl_pins[] = { PINCTRL_PIN(54, "mdio_0"), }; -static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 }; -static const int an7583_pon_tod_1pps_pins[] = { 32 }; -static const int an7583_gsw_tod_1pps_pins[] = { 32 }; -static const int an7583_sipo_pins[] = { 34, 35 }; -static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 }; -static const int an7583_mdio_pins[] = { 53, 54 }; -static const int an7583_mdio1_pins[] = { 43, 44 }; -static const int an7583_uart2_pins[] = { 34, 35 }; -static const int an7583_uart2_cts_rts_pins[] = { 32, 33 }; -static const int an7583_hsuart_pins[] = { 30, 31 }; -static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 }; -static const int an7583_npu_uart_pins[] = { 7, 8 }; -static const int an7583_uart4_pins[] = { 7, 8 }; -static const int an7583_uart5_pins[] = { 23, 24 }; -static const int an7583_i2c0_pins[] = { 41, 42 }; -static const int an7583_i2c1_pins[] = { 43, 44 }; -static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 }; -static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 }; -static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 }; -static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 }; -static const int an7583_spi_pins[] = { 45, 46, 47, 48 }; -static const int an7583_spi_quad_pins[] = { 25, 26 }; -static const int an7583_spi_cs1_pins[] = { 27 }; -static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 }; -static const int an7583_pcm_spi_rst_pins[] = { 14 }; -static const int an7583_pcm_spi_cs1_pins[] = { 24 }; -static const int an7583_emmc_pins[] = { +static const int pon_pins[] = { 15, 16, 17, 18, 19, 20 }; +static const int pon_tod_1pps_pins[] = { 32 }; +static const int gsw_tod_1pps_pins[] = { 32 }; +static const int sipo_pins[] = { 34, 35 }; +static const int sipo_rclk_pins[] = { 34, 35, 33 }; +static const int mdio_pins[] = { 53, 54 }; +static const int mdio1_pins[] = { 43, 44 }; +static const int uart2_pins[] = { 34, 35 }; +static const int uart2_cts_rts_pins[] = { 32, 33 }; +static const int hsuart_pins[] = { 30, 31 }; +static const int hsuart_cts_rts_pins[] = { 28, 29 }; +static const int npu_uart_pins[] = { 7, 8 }; +static const int uart4_pins[] = { 7, 8 }; +static const int uart5_pins[] = { 23, 24 }; +static const int i2c0_pins[] = { 41, 42 }; +static const int i2c1_pins[] = { 43, 44 }; +static const int jtag_udi_pins[] = { 23, 24, 22, 25, 26 }; +static const int jtag_dfd_pins[] = { 23, 24, 22, 25, 26 }; +static const int pcm1_pins[] = { 10, 11, 12, 13, 14 }; +static const int pcm2_pins[] = { 28, 29, 30, 31, 24 }; +static const int spi_pins[] = { 45, 46, 47, 48 }; +static const int spi_quad_pins[] = { 25, 26 }; +static const int spi_cs1_pins[] = { 27 }; +static const int pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 }; +static const int pcm_spi_rst_pins[] = { 14 }; +static const int pcm_spi_cs1_pins[] = { 24 }; +static const int emmc_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47 }; -static const int an7583_pnand_pins[] = { +static const int pnand_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48 }; -static const int an7583_gpio0_pins[] = { 2 }; -static const int an7583_gpio1_pins[] = { 3 }; -static const int an7583_gpio2_pins[] = { 4 }; -static const int an7583_gpio3_pins[] = { 5 }; -static const int an7583_gpio4_pins[] = { 6 }; -static const int an7583_gpio5_pins[] = { 7 }; -static const int an7583_gpio6_pins[] = { 8 }; -static const int an7583_gpio7_pins[] = { 9 }; -static const int an7583_gpio8_pins[] = { 10 }; -static const int an7583_gpio9_pins[] = { 11 }; -static const int an7583_gpio10_pins[] = { 12 }; -static const int an7583_gpio11_pins[] = { 13 }; -static const int an7583_gpio12_pins[] = { 14 }; -static const int an7583_gpio13_pins[] = { 15 }; -static const int an7583_gpio14_pins[] = { 16 }; -static const int an7583_gpio15_pins[] = { 17 }; -static const int an7583_gpio16_pins[] = { 18 }; -static const int an7583_gpio17_pins[] = { 19 }; -static const int an7583_gpio18_pins[] = { 20 }; -static const int an7583_gpio19_pins[] = { 21 }; -static const int an7583_gpio20_pins[] = { 22 }; -static const int an7583_gpio21_pins[] = { 23 }; -static const int an7583_gpio22_pins[] = { 24 }; -static const int an7583_gpio23_pins[] = { 25 }; -static const int an7583_gpio24_pins[] = { 26 }; -static const int an7583_gpio25_pins[] = { 27 }; -static const int an7583_gpio26_pins[] = { 28 }; -static const int an7583_gpio27_pins[] = { 29 }; -static const int an7583_gpio28_pins[] = { 30 }; -static const int an7583_gpio29_pins[] = { 31 }; -static const int an7583_gpio30_pins[] = { 32 }; -static const int an7583_gpio31_pins[] = { 33 }; -static const int an7583_gpio32_pins[] = { 34 }; -static const int an7583_gpio33_pins[] = { 35 }; -static const int an7583_gpio34_pins[] = { 36 }; -static const int an7583_gpio35_pins[] = { 37 }; -static const int an7583_gpio36_pins[] = { 38 }; -static const int an7583_gpio37_pins[] = { 39 }; -static const int an7583_gpio38_pins[] = { 40 }; -static const int an7583_gpio39_pins[] = { 41 }; -static const int an7583_gpio40_pins[] = { 42 }; -static const int an7583_gpio41_pins[] = { 43 }; -static const int an7583_gpio42_pins[] = { 44 }; -static const int an7583_gpio43_pins[] = { 45 }; -static const int an7583_gpio44_pins[] = { 46 }; -static const int an7583_gpio45_pins[] = { 47 }; -static const int an7583_gpio46_pins[] = { 48 }; -static const int an7583_gpio47_pins[] = { 49 }; -static const int an7583_gpio48_pins[] = { 50 }; -static const int an7583_gpio49_pins[] = { 51 }; -static const int an7583_gpio50_pins[] = { 52 }; -static const int an7583_gpio51_pins[] = { 53 }; -static const int an7583_gpio52_pins[] = { 54 }; -static const int an7583_pcie_reset0_pins[] = { 51 }; -static const int an7583_pcie_reset1_pins[] = { 52 }; +static const int gpio0_pins[] = { 2 }; +static const int gpio1_pins[] = { 3 }; +static const int gpio2_pins[] = { 4 }; +static const int gpio3_pins[] = { 5 }; +static const int gpio4_pins[] = { 6 }; +static const int gpio5_pins[] = { 7 }; +static const int gpio6_pins[] = { 8 }; +static const int gpio7_pins[] = { 9 }; +static const int gpio8_pins[] = { 10 }; +static const int gpio9_pins[] = { 11 }; +static const int gpio10_pins[] = { 12 }; +static const int gpio11_pins[] = { 13 }; +static const int gpio12_pins[] = { 14 }; +static const int gpio13_pins[] = { 15 }; +static const int gpio14_pins[] = { 16 }; +static const int gpio15_pins[] = { 17 }; +static const int gpio16_pins[] = { 18 }; +static const int gpio17_pins[] = { 19 }; +static const int gpio18_pins[] = { 20 }; +static const int gpio19_pins[] = { 21 }; +static const int gpio20_pins[] = { 22 }; +static const int gpio21_pins[] = { 23 }; +static const int gpio22_pins[] = { 24 }; +static const int gpio23_pins[] = { 25 }; +static const int gpio24_pins[] = { 26 }; +static const int gpio25_pins[] = { 27 }; +static const int gpio26_pins[] = { 28 }; +static const int gpio27_pins[] = { 29 }; +static const int gpio28_pins[] = { 30 }; +static const int gpio29_pins[] = { 31 }; +static const int gpio30_pins[] = { 32 }; +static const int gpio31_pins[] = { 33 }; +static const int gpio32_pins[] = { 34 }; +static const int gpio33_pins[] = { 35 }; +static const int gpio34_pins[] = { 36 }; +static const int gpio35_pins[] = { 37 }; +static const int gpio36_pins[] = { 38 }; +static const int gpio37_pins[] = { 39 }; +static const int gpio38_pins[] = { 40 }; +static const int gpio39_pins[] = { 41 }; +static const int gpio40_pins[] = { 42 }; +static const int gpio41_pins[] = { 43 }; +static const int gpio42_pins[] = { 44 }; +static const int gpio43_pins[] = { 45 }; +static const int gpio44_pins[] = { 46 }; +static const int gpio45_pins[] = { 47 }; +static const int gpio46_pins[] = { 48 }; +static const int gpio47_pins[] = { 49 }; +static const int gpio48_pins[] = { 50 }; +static const int gpio49_pins[] = { 51 }; +static const int gpio50_pins[] = { 52 }; +static const int gpio51_pins[] = { 53 }; +static const int gpio52_pins[] = { 54 }; +static const int pcie_reset0_pins[] = { 51 }; +static const int pcie_reset1_pins[] = { 52 }; -static const struct pingroup an7583_pinctrl_groups[] = { - PINCTRL_PIN_GROUP("pon", an7583_pon), - PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps), - PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps), - PINCTRL_PIN_GROUP("sipo", an7583_sipo), - PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk), - PINCTRL_PIN_GROUP("mdio", an7583_mdio), - PINCTRL_PIN_GROUP("mdio1", an7583_mdio1), - PINCTRL_PIN_GROUP("uart2", an7583_uart2), - PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts), - PINCTRL_PIN_GROUP("hsuart", an7583_hsuart), - PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts), - PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart), - PINCTRL_PIN_GROUP("uart4", an7583_uart4), - PINCTRL_PIN_GROUP("uart5", an7583_uart5), - PINCTRL_PIN_GROUP("i2c0", an7583_i2c0), - PINCTRL_PIN_GROUP("i2c1", an7583_i2c1), - PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi), - PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd), - PINCTRL_PIN_GROUP("pcm1", an7583_pcm1), - PINCTRL_PIN_GROUP("pcm2", an7583_pcm2), - PINCTRL_PIN_GROUP("spi", an7583_spi), - PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad), - PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1), - PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi), - PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst), - PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1), - PINCTRL_PIN_GROUP("emmc", an7583_emmc), - PINCTRL_PIN_GROUP("pnand", an7583_pnand), - PINCTRL_PIN_GROUP("gpio0", an7583_gpio0), - PINCTRL_PIN_GROUP("gpio1", an7583_gpio1), - PINCTRL_PIN_GROUP("gpio2", an7583_gpio2), - PINCTRL_PIN_GROUP("gpio3", an7583_gpio3), - PINCTRL_PIN_GROUP("gpio4", an7583_gpio4), - PINCTRL_PIN_GROUP("gpio5", an7583_gpio5), - PINCTRL_PIN_GROUP("gpio6", an7583_gpio6), - PINCTRL_PIN_GROUP("gpio7", an7583_gpio7), - PINCTRL_PIN_GROUP("gpio8", an7583_gpio8), - PINCTRL_PIN_GROUP("gpio9", an7583_gpio9), - PINCTRL_PIN_GROUP("gpio10", an7583_gpio10), - PINCTRL_PIN_GROUP("gpio11", an7583_gpio11), - PINCTRL_PIN_GROUP("gpio12", an7583_gpio12), - PINCTRL_PIN_GROUP("gpio13", an7583_gpio13), - PINCTRL_PIN_GROUP("gpio14", an7583_gpio14), - PINCTRL_PIN_GROUP("gpio15", an7583_gpio15), - PINCTRL_PIN_GROUP("gpio16", an7583_gpio16), - PINCTRL_PIN_GROUP("gpio17", an7583_gpio17), - PINCTRL_PIN_GROUP("gpio18", an7583_gpio18), - PINCTRL_PIN_GROUP("gpio19", an7583_gpio19), - PINCTRL_PIN_GROUP("gpio20", an7583_gpio20), - PINCTRL_PIN_GROUP("gpio21", an7583_gpio21), - PINCTRL_PIN_GROUP("gpio22", an7583_gpio22), - PINCTRL_PIN_GROUP("gpio23", an7583_gpio23), - PINCTRL_PIN_GROUP("gpio24", an7583_gpio24), - PINCTRL_PIN_GROUP("gpio25", an7583_gpio25), - PINCTRL_PIN_GROUP("gpio26", an7583_gpio26), - PINCTRL_PIN_GROUP("gpio27", an7583_gpio27), - PINCTRL_PIN_GROUP("gpio28", an7583_gpio28), - PINCTRL_PIN_GROUP("gpio29", an7583_gpio29), - PINCTRL_PIN_GROUP("gpio30", an7583_gpio30), - PINCTRL_PIN_GROUP("gpio31", an7583_gpio31), - PINCTRL_PIN_GROUP("gpio32", an7583_gpio32), - PINCTRL_PIN_GROUP("gpio33", an7583_gpio33), - PINCTRL_PIN_GROUP("gpio34", an7583_gpio34), - PINCTRL_PIN_GROUP("gpio35", an7583_gpio35), - PINCTRL_PIN_GROUP("gpio36", an7583_gpio36), - PINCTRL_PIN_GROUP("gpio37", an7583_gpio37), - PINCTRL_PIN_GROUP("gpio38", an7583_gpio38), - PINCTRL_PIN_GROUP("gpio39", an7583_gpio39), - PINCTRL_PIN_GROUP("gpio40", an7583_gpio40), - PINCTRL_PIN_GROUP("gpio41", an7583_gpio41), - PINCTRL_PIN_GROUP("gpio42", an7583_gpio42), - PINCTRL_PIN_GROUP("gpio43", an7583_gpio43), - PINCTRL_PIN_GROUP("gpio44", an7583_gpio44), - PINCTRL_PIN_GROUP("gpio45", an7583_gpio45), - PINCTRL_PIN_GROUP("gpio46", an7583_gpio46), - PINCTRL_PIN_GROUP("gpio47", an7583_gpio47), - PINCTRL_PIN_GROUP("gpio48", an7583_gpio48), - PINCTRL_PIN_GROUP("gpio49", an7583_gpio49), - PINCTRL_PIN_GROUP("gpio50", an7583_gpio50), - PINCTRL_PIN_GROUP("gpio51", an7583_gpio51), - PINCTRL_PIN_GROUP("gpio52", an7583_gpio52), - PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0), - PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1), +static const struct pingroup pinctrl_groups[] = { + PINCTRL_PIN_GROUP("pon", pon), + PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps), + PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps), + PINCTRL_PIN_GROUP("sipo", sipo), + PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk), + PINCTRL_PIN_GROUP("mdio", mdio), + PINCTRL_PIN_GROUP("mdio1", mdio1), + PINCTRL_PIN_GROUP("uart2", uart2), + PINCTRL_PIN_GROUP("uart2_cts_rts", uart2_cts_rts), + PINCTRL_PIN_GROUP("hsuart", hsuart), + PINCTRL_PIN_GROUP("hsuart_cts_rts", hsuart_cts_rts), + PINCTRL_PIN_GROUP("npu_uart", npu_uart), + PINCTRL_PIN_GROUP("uart4", uart4), + PINCTRL_PIN_GROUP("uart5", uart5), + PINCTRL_PIN_GROUP("i2c0", i2c0), + PINCTRL_PIN_GROUP("i2c1", i2c1), + PINCTRL_PIN_GROUP("jtag_udi", jtag_udi), + PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd), + PINCTRL_PIN_GROUP("pcm1", pcm1), + PINCTRL_PIN_GROUP("pcm2", pcm2), + PINCTRL_PIN_GROUP("spi", spi), + PINCTRL_PIN_GROUP("spi_quad", spi_quad), + PINCTRL_PIN_GROUP("spi_cs1", spi_cs1), + PINCTRL_PIN_GROUP("pcm_spi", pcm_spi), + PINCTRL_PIN_GROUP("pcm_spi_rst", pcm_spi_rst), + PINCTRL_PIN_GROUP("pcm_spi_cs1", pcm_spi_cs1), + PINCTRL_PIN_GROUP("emmc", emmc), + PINCTRL_PIN_GROUP("pnand", pnand), + PINCTRL_PIN_GROUP("gpio0", gpio0), + PINCTRL_PIN_GROUP("gpio1", gpio1), + PINCTRL_PIN_GROUP("gpio2", gpio2), + PINCTRL_PIN_GROUP("gpio3", gpio3), + PINCTRL_PIN_GROUP("gpio4", gpio4), + PINCTRL_PIN_GROUP("gpio5", gpio5), + PINCTRL_PIN_GROUP("gpio6", gpio6), + PINCTRL_PIN_GROUP("gpio7", gpio7), + PINCTRL_PIN_GROUP("gpio8", gpio8), + PINCTRL_PIN_GROUP("gpio9", gpio9), + PINCTRL_PIN_GROUP("gpio10", gpio10), + PINCTRL_PIN_GROUP("gpio11", gpio11), + PINCTRL_PIN_GROUP("gpio12", gpio12), + PINCTRL_PIN_GROUP("gpio13", gpio13), + PINCTRL_PIN_GROUP("gpio14", gpio14), + PINCTRL_PIN_GROUP("gpio15", gpio15), + PINCTRL_PIN_GROUP("gpio16", gpio16), + PINCTRL_PIN_GROUP("gpio17", gpio17), + PINCTRL_PIN_GROUP("gpio18", gpio18), + PINCTRL_PIN_GROUP("gpio19", gpio19), + PINCTRL_PIN_GROUP("gpio20", gpio20), + PINCTRL_PIN_GROUP("gpio21", gpio21), + PINCTRL_PIN_GROUP("gpio22", gpio22), + PINCTRL_PIN_GROUP("gpio23", gpio23), + PINCTRL_PIN_GROUP("gpio24", gpio24), + PINCTRL_PIN_GROUP("gpio25", gpio25), + PINCTRL_PIN_GROUP("gpio26", gpio26), + PINCTRL_PIN_GROUP("gpio27", gpio27), + PINCTRL_PIN_GROUP("gpio28", gpio28), + PINCTRL_PIN_GROUP("gpio29", gpio29), + PINCTRL_PIN_GROUP("gpio30", gpio30), + PINCTRL_PIN_GROUP("gpio31", gpio31), + PINCTRL_PIN_GROUP("gpio32", gpio32), + PINCTRL_PIN_GROUP("gpio33", gpio33), + PINCTRL_PIN_GROUP("gpio34", gpio34), + PINCTRL_PIN_GROUP("gpio35", gpio35), + PINCTRL_PIN_GROUP("gpio36", gpio36), + PINCTRL_PIN_GROUP("gpio37", gpio37), + PINCTRL_PIN_GROUP("gpio38", gpio38), + PINCTRL_PIN_GROUP("gpio39", gpio39), + PINCTRL_PIN_GROUP("gpio40", gpio40), + PINCTRL_PIN_GROUP("gpio41", gpio41), + PINCTRL_PIN_GROUP("gpio42", gpio42), + PINCTRL_PIN_GROUP("gpio43", gpio43), + PINCTRL_PIN_GROUP("gpio44", gpio44), + PINCTRL_PIN_GROUP("gpio45", gpio45), + PINCTRL_PIN_GROUP("gpio46", gpio46), + PINCTRL_PIN_GROUP("gpio47", gpio47), + PINCTRL_PIN_GROUP("gpio48", gpio48), + PINCTRL_PIN_GROUP("gpio49", gpio49), + PINCTRL_PIN_GROUP("gpio50", gpio50), + PINCTRL_PIN_GROUP("gpio51", gpio51), + PINCTRL_PIN_GROUP("gpio52", gpio52), + PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0), + PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1), }; static const char *const pon_groups[] = { "pon" }; @@ -568,29 +568,29 @@ static const char *const tod_1pps_groups[] = { "pon_tod_1pps", "gsw_tod_1pps" }; static const char *const sipo_groups[] = { "sipo", "sipo_rclk" }; -static const char *const an7583_mdio_groups[] = { "mdio" }; +static const char *const mdio_groups[] = { "mdio" }; static const char *const uart_groups[] = { "uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts", "uart4", "uart5" }; -static const char *const an7583_i2c_groups[] = { "i2c0", "i2c1" }; +static const char *const i2c_groups[] = { "i2c0", "i2c1" }; static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" }; static const char *const pcm_groups[] = { "pcm1", "pcm2" }; static const char *const spi_groups[] = { "spi_quad", "spi_cs1" }; -static const char *const an7583_pcm_spi_groups[] = { +static const char *const pcm_spi_groups[] = { "pcm_spi", "pcm_spi_rst", "pcm_spi_cs1" }; static const char *const emmc_groups[] = { "emmc" }; static const char *const pnand_groups[] = { "pnand" }; -static const char *const an7583_gpio_groups[] = { +static const char *const gpio_groups[] = { "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51", "gpio52" }; -static const char *const an7583_pcie_reset_groups[] = { +static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1" }; -static const char *const an7583_pwm_groups[] = { +static const char *const pwm_groups[] = { "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", @@ -600,28 +600,28 @@ static const char *const an7583_pwm_groups[] = { "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51" }; -static const char *const an7583_phy1_led0_groups[] = { +static const char *const phy1_led0_groups[] = { "gpio1", "gpio2", "gpio3", "gpio4" }; -static const char *const an7583_phy2_led0_groups[] = { +static const char *const phy2_led0_groups[] = { "gpio1", "gpio2", "gpio3", "gpio4" }; -static const char *const an7583_phy3_led0_groups[] = { +static const char *const phy3_led0_groups[] = { "gpio1", "gpio2", "gpio3", "gpio4" }; -static const char *const an7583_phy4_led0_groups[] = { +static const char *const phy4_led0_groups[] = { "gpio1", "gpio2", "gpio3", "gpio4" }; -static const char *const an7583_phy1_led1_groups[] = { +static const char *const phy1_led1_groups[] = { "gpio8", "gpio9", "gpio10", "gpio11" }; -static const char *const an7583_phy2_led1_groups[] = { +static const char *const phy2_led1_groups[] = { "gpio8", "gpio9", "gpio10", "gpio11" }; -static const char *const an7583_phy3_led1_groups[] = { +static const char *const phy3_led1_groups[] = { "gpio8", "gpio9", "gpio10", "gpio11" }; -static const char *const an7583_phy4_led1_groups[] = { +static const char *const phy4_led1_groups[] = { "gpio8", "gpio9", "gpio10", "gpio11" }; @@ -682,13 +682,13 @@ static const struct airoha_pinctrl_func_group sipo_func_group[] = { }, }; -static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = { +static const struct airoha_pinctrl_func_group mdio_func_group[] = { { .name = "mdio", .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE, - AN7583_MDC_0_GPIO_MODE_MASK | AN7583_MDIO_0_GPIO_MODE_MASK, + MDC_0_GPIO_MODE_MASK | MDIO_0_GPIO_MODE_MASK, 0 }, .regmap_size = 1, @@ -754,13 +754,13 @@ static const struct airoha_pinctrl_func_group uart_func_group[] = { }, }; -static const struct airoha_pinctrl_func_group an7583_i2c_func_group[] = { +static const struct airoha_pinctrl_func_group i2c_func_group[] = { { .name = "i2c0", .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE, - AN7583_I2C0_SCL_GPIO_MODE_MASK | AN7583_I2C0_SDA_GPIO_MODE_MASK, + I2C0_SCL_GPIO_MODE_MASK | I2C0_SDA_GPIO_MODE_MASK, 0 }, .regmap_size = 1, @@ -769,7 +769,7 @@ static const struct airoha_pinctrl_func_group an7583_i2c_func_group[] = { .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE, - AN7583_I2C1_SCL_GPIO_MODE_MASK | AN7583_I2C1_SDA_GPIO_MODE_MASK, + I2C1_SCL_GPIO_MODE_MASK | I2C1_SDA_GPIO_MODE_MASK, 0 }, .regmap_size = 1, @@ -869,7 +869,7 @@ static const struct airoha_pinctrl_func_group spi_func_group[] = { }, }; -static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = { +static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = { { .name = "pcm_spi", .regmap[0] = { @@ -911,8 +911,8 @@ static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = { .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE, - AN7583_GPIO_PCM_SPI_CS2_MODE_MASK, - AN7583_GPIO_PCM_SPI_CS2_MODE_MASK + GPIO_PCM_SPI_CS2_MODE_MASK, + GPIO_PCM_SPI_CS2_MODE_MASK }, .regmap_size = 1, }, { @@ -962,37 +962,37 @@ static const struct airoha_pinctrl_func_group pnand_func_group[] = { }, }; -static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = { +static const struct airoha_pinctrl_func_group gpio_func_group[] = { AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG, - AN7583_I2C0_SCL_GPIO_MODE_MASK), + I2C0_SCL_GPIO_MODE_MASK), AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG, - AN7583_I2C0_SDA_GPIO_MODE_MASK), + I2C0_SDA_GPIO_MODE_MASK), AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG, - AN7583_I2C1_SCL_GPIO_MODE_MASK), + I2C1_SCL_GPIO_MODE_MASK), AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG, - AN7583_I2C1_SDA_GPIO_MODE_MASK), + I2C1_SDA_GPIO_MODE_MASK), AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG, - AN7583_SPI_CLK_GPIO_MODE_MASK), + SPI_CLK_GPIO_MODE_MASK), AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG, - AN7583_SPI_CS_GPIO_MODE_MASK), + SPI_CS_GPIO_MODE_MASK), AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG, - AN7583_SPI_MOSI_GPIO_MODE_MASK), + SPI_MOSI_GPIO_MODE_MASK), AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG, - AN7583_SPI_MISO_GPIO_MODE_MASK), + SPI_MISO_GPIO_MODE_MASK), AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG, - AN7583_UART_TXD_GPIO_MODE_MASK), + UART_TXD_GPIO_MODE_MASK), AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG, - AN7583_UART_RXD_GPIO_MODE_MASK), + UART_RXD_GPIO_MODE_MASK), AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG, GPIO_PCIE_RESET0_MASK), AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG, GPIO_PCIE_RESET1_MASK), AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG, - AN7583_MDC_0_GPIO_MODE_MASK), - AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK), + MDC_0_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO("gpio52", MDIO_0_GPIO_MODE_MASK), }; -static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = { +static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = { { .name = "pcie_reset0", .regmap[0] = { @@ -1014,7 +1014,7 @@ static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = { }, }; -static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = { +static const struct airoha_pinctrl_func_group pwm_func_group[] = { AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), @@ -1051,34 +1051,34 @@ static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = { AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG), AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG), AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG, - AN7583_I2C0_SCL_GPIO_MODE_MASK), + I2C0_SCL_GPIO_MODE_MASK), AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG, - AN7583_I2C0_SDA_GPIO_MODE_MASK), + I2C0_SDA_GPIO_MODE_MASK), AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG, - AN7583_I2C1_SCL_GPIO_MODE_MASK), + I2C1_SCL_GPIO_MODE_MASK), AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG, - AN7583_I2C1_SDA_GPIO_MODE_MASK), + I2C1_SDA_GPIO_MODE_MASK), AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG, - AN7583_SPI_CLK_GPIO_MODE_MASK), + SPI_CLK_GPIO_MODE_MASK), AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG, - AN7583_SPI_CS_GPIO_MODE_MASK), + SPI_CS_GPIO_MODE_MASK), AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG, - AN7583_SPI_MOSI_GPIO_MODE_MASK), + SPI_MOSI_GPIO_MODE_MASK), AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG, - AN7583_SPI_MISO_GPIO_MODE_MASK), + SPI_MISO_GPIO_MODE_MASK), AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG, - AN7583_UART_TXD_GPIO_MODE_MASK), + UART_TXD_GPIO_MODE_MASK), AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG, - AN7583_UART_RXD_GPIO_MODE_MASK), + UART_RXD_GPIO_MODE_MASK), AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG, GPIO_PCIE_RESET0_MASK), AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG, GPIO_PCIE_RESET1_MASK), AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG, - AN7583_MDC_0_GPIO_MODE_MASK), + MDC_0_GPIO_MODE_MASK), }; -static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = { +static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = { AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, @@ -1089,7 +1089,7 @@ static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = { LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), }; -static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = { +static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = { AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, @@ -1100,7 +1100,7 @@ static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = { LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), }; -static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = { +static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = { AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, @@ -1111,7 +1111,7 @@ static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = { LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), }; -static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = { +static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = { AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, @@ -1122,7 +1122,7 @@ static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = { LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), }; -static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = { +static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = { AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, @@ -1133,7 +1133,7 @@ static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = { LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), }; -static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = { +static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = { AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, @@ -1144,7 +1144,7 @@ static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = { LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), }; -static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = { +static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = { AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, @@ -1155,7 +1155,7 @@ static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = { LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), }; -static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = { +static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = { AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, @@ -1166,33 +1166,33 @@ static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = { LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), }; -static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = { +static const struct airoha_pinctrl_func pinctrl_funcs[] = { PINCTRL_FUNC_DESC("pon", pon), PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), PINCTRL_FUNC_DESC("sipo", sipo), - PINCTRL_FUNC_DESC("mdio", an7583_mdio), + PINCTRL_FUNC_DESC("mdio", mdio), PINCTRL_FUNC_DESC("uart", uart), - PINCTRL_FUNC_DESC("i2c", an7583_i2c), + PINCTRL_FUNC_DESC("i2c", i2c), PINCTRL_FUNC_DESC("jtag", jtag), PINCTRL_FUNC_DESC("pcm", pcm), PINCTRL_FUNC_DESC("spi", spi), - PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi), + PINCTRL_FUNC_DESC("pcm_spi", pcm_spi), PINCTRL_FUNC_DESC("emmc", emmc), PINCTRL_FUNC_DESC("pnand", pnand), - PINCTRL_FUNC_DESC("gpio", an7583_gpio), - PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset), - PINCTRL_FUNC_DESC("pwm", an7583_pwm), - PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0), - PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0), - PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0), - PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0), - PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1), - PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1), - PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1), - PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1), + PINCTRL_FUNC_DESC("gpio", gpio), + PINCTRL_FUNC_DESC("pcie_reset", pcie_reset), + PINCTRL_FUNC_DESC("pwm", pwm), + PINCTRL_FUNC_DESC("phy1_led0", phy1_led0), + PINCTRL_FUNC_DESC("phy2_led0", phy2_led0), + PINCTRL_FUNC_DESC("phy3_led0", phy3_led0), + PINCTRL_FUNC_DESC("phy4_led0", phy4_led0), + PINCTRL_FUNC_DESC("phy1_led1", phy1_led1), + PINCTRL_FUNC_DESC("phy2_led1", phy2_led1), + PINCTRL_FUNC_DESC("phy3_led1", phy3_led1), + PINCTRL_FUNC_DESC("phy4_led1", phy4_led1), }; -static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = { +static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = { PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)), PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)), PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)), @@ -1234,8 +1234,8 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = { PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)), PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), - PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK), - PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK), + PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, I2C1_SCL_PU_MASK), + PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, I2C1_SDA_PU_MASK), PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), @@ -1244,11 +1244,11 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = { PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), - PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK), - PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK), + PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, MDC_0_PU_MASK), + PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, MDIO_0_PU_MASK), }; -static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = { +static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = { PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)), PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)), PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)), @@ -1290,8 +1290,8 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = { PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)), PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), - PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK), - PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK), + PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, I2C1_SCL_PD_MASK), + PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, I2C1_SDA_PD_MASK), PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), @@ -1300,11 +1300,11 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = { PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), - PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK), - PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK), + PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, MDC_0_PD_MASK), + PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, MDIO_0_PD_MASK), }; -static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = { +static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = { PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)), PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)), PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)), @@ -1346,8 +1346,8 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = { PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)), PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), - PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK), - PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK), + PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, I2C1_SCL_E2_MASK), + PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, I2C1_SDA_E2_MASK), PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), @@ -1356,11 +1356,11 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = { PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), - PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK), - PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK), + PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, MDC_0_E2_MASK), + PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, MDIO_0_E2_MASK), }; -static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = { +static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = { PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)), PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)), PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)), @@ -1402,8 +1402,8 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = { PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)), PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), - PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK), - PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK), + PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, I2C1_SCL_E4_MASK), + PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, I2C1_SDA_E4_MASK), PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), @@ -1412,50 +1412,50 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = { PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), - PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK), - PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK), + PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, MDC_0_E4_MASK), + PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, MDIO_0_E4_MASK), }; -static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = { +static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = { PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), }; -static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = { +static const struct airoha_pinctrl_match_data pinctrl_match_data = { .pinctrl_name = KBUILD_MODNAME, .pinctrl_owner = THIS_MODULE, - .pins = an7583_pinctrl_pins, - .num_pins = ARRAY_SIZE(an7583_pinctrl_pins), - .grps = an7583_pinctrl_groups, - .num_grps = ARRAY_SIZE(an7583_pinctrl_groups), - .funcs = an7583_pinctrl_funcs, - .num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs), + .pins = pinctrl_pins, + .num_pins = ARRAY_SIZE(pinctrl_pins), + .grps = pinctrl_groups, + .num_grps = ARRAY_SIZE(pinctrl_groups), + .funcs = pinctrl_funcs, + .num_funcs = ARRAY_SIZE(pinctrl_funcs), .confs_info = { [AIROHA_PINCTRL_CONFS_PULLUP] = { - .confs = an7583_pinctrl_pullup_conf, - .num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf), + .confs = pinctrl_pullup_conf, + .num_confs = ARRAY_SIZE(pinctrl_pullup_conf), }, [AIROHA_PINCTRL_CONFS_PULLDOWN] = { - .confs = an7583_pinctrl_pulldown_conf, - .num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf), + .confs = pinctrl_pulldown_conf, + .num_confs = ARRAY_SIZE(pinctrl_pulldown_conf), }, [AIROHA_PINCTRL_CONFS_DRIVE_E2] = { - .confs = an7583_pinctrl_drive_e2_conf, - .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf), + .confs = pinctrl_drive_e2_conf, + .num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf), }, [AIROHA_PINCTRL_CONFS_DRIVE_E4] = { - .confs = an7583_pinctrl_drive_e4_conf, - .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf), + .confs = pinctrl_drive_e4_conf, + .num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf), }, [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = { - .confs = an7583_pinctrl_pcie_rst_od_conf, - .num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf), + .confs = pinctrl_pcie_rst_od_conf, + .num_confs = ARRAY_SIZE(pinctrl_pcie_rst_od_conf), }, }, }; static const struct of_device_id airoha_pinctrl_of_match[] = { - { .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data }, + { .compatible = "airoha,an7583-pinctrl", .data = &pinctrl_match_data }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match); From c4776d20be8ced21d5b556f853823f16a624fac3 Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:06:06 +0300 Subject: [PATCH 110/130] pinctrl: airoha: an7583: rename registers to match its an7583 names In the an7581 case the register at 0x1FA20214 is called RG_GPIO_2ND_I2C_MODE. The same register in the an7583 case is called RG_SW_TOD_1PPS_MODE. Let's rename this register to avoid potential confuse. Signed-off-by: Mikhail Kshevetskiy Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/pinctrl-an7583.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c index 6d195096495f..44efccce78c5 100644 --- a/drivers/pinctrl/airoha/pinctrl-an7583.c +++ b/drivers/pinctrl/airoha/pinctrl-an7583.c @@ -8,7 +8,7 @@ #include "airoha-common.h" /* MUX */ -#define REG_GPIO_2ND_I2C_MODE 0x0214 +#define REG_SW_TOD_1PPS_MODE 0x0214 #define GPIO_LAN3_LED1_MODE_MASK BIT(10) #define GPIO_LAN3_LED0_MODE_MASK BIT(9) #define GPIO_LAN2_LED1_MODE_MASK BIT(8) @@ -302,7 +302,7 @@ .name = (gpio), \ .regmap[0] = { \ AIROHA_FUNC_MUX, \ - REG_GPIO_2ND_I2C_MODE, \ + REG_SW_TOD_1PPS_MODE, \ (mux_val), \ (mux_val), \ }, \ @@ -320,7 +320,7 @@ .name = (gpio), \ .regmap[0] = { \ AIROHA_FUNC_MUX, \ - REG_GPIO_2ND_I2C_MODE, \ + REG_SW_TOD_1PPS_MODE, \ (mux_val), \ (mux_val), \ }, \ @@ -643,7 +643,7 @@ static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = { .name = "pon_tod_1pps", .regmap[0] = { AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, + REG_SW_TOD_1PPS_MODE, PON_TOD_1PPS_MODE_MASK, PON_TOD_1PPS_MODE_MASK }, @@ -652,7 +652,7 @@ static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = { .name = "gsw_tod_1pps", .regmap[0] = { AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, + REG_SW_TOD_1PPS_MODE, GSW_TOD_1PPS_MODE_MASK, GSW_TOD_1PPS_MODE_MASK }, From 8095e8785a901b50ccc883a7287476fd4b44dbac Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:06:07 +0300 Subject: [PATCH 111/130] dt-bindings: pinctrl: airoha: an7583: add missed features Changes: * add npu_uart pin-group support for uart pin-function * add pon_alt pin-group support for pon pin-function * add support for olt pin group/function Signed-off-by: Mikhail Kshevetskiy Reviewed-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- .../bindings/pinctrl/airoha,an7583-pinctrl.yaml | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml index 24f1ac60eea8..aad2e9880ec6 100644 --- a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml @@ -60,7 +60,7 @@ patternProperties: function: description: A string containing the name of the function to mux to the group. - enum: [pon, tod_1pps, sipo, mdio, uart, i2c, jtag, pcm, spi, + enum: [pon, olt, tod_1pps, sipo, mdio, uart, i2c, jtag, pcm, spi, pcm_spi, emmc, pnand, gpio, pcie_reset, pwm, phy1_led0, phy2_led0, phy3_led0, phy4_led0, phy1_led1, phy2_led1, phy3_led1, phy4_led1] @@ -81,7 +81,15 @@ patternProperties: then: properties: groups: - enum: [pon] + enum: [pon, pon_alt] + - if: + properties: + function: + const: olt + then: + properties: + groups: + enum: [olt] - if: properties: function: @@ -115,7 +123,7 @@ patternProperties: groups: items: enum: [uart2, uart2_cts_rts, hsuart, hsuart_cts_rts, - uart4, uart5] + uart4, uart5, npu_uart] maxItems: 2 - if: properties: From 24cde06b06967baa99c2be27829baa0ba2ab33c0 Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:06:08 +0300 Subject: [PATCH 112/130] pinctrl: airoha: an7583: add support for npu_uart pinmux Add support for uart pin function for npu_uart pin group. Signed-off-by: Mikhail Kshevetskiy Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/pinctrl-an7583.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c index 44efccce78c5..dc88cbd8746b 100644 --- a/drivers/pinctrl/airoha/pinctrl-an7583.c +++ b/drivers/pinctrl/airoha/pinctrl-an7583.c @@ -68,6 +68,7 @@ #define REG_NPU_UART_EN 0x0224 #define JTAG_UDI_EN_MASK BIT(4) #define JTAG_DFD_EN_MASK BIT(3) +#define NPU_UART_EN_MASK BIT(2) #define REG_FORCE_GPIO_EN 0x0228 #define FORCE_GPIO_EN(n) BIT(n) @@ -571,7 +572,7 @@ static const char *const sipo_groups[] = { "sipo", "sipo_rclk" }; static const char *const mdio_groups[] = { "mdio" }; static const char *const uart_groups[] = { "uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts", - "uart4", "uart5" + "uart4", "uart5", "npu_uart" }; static const char *const i2c_groups[] = { "i2c0", "i2c1" }; static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" }; @@ -751,6 +752,15 @@ static const struct airoha_pinctrl_func_group uart_func_group[] = { GPIO_UART5_MODE_MASK }, .regmap_size = 1, + }, { + .name = "npu_uart", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + NPU_UART_EN_MASK, + NPU_UART_EN_MASK + }, + .regmap_size = 1, }, }; From 1594233ef61888f1870d0617deb3db771c81bffe Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:06:09 +0300 Subject: [PATCH 113/130] pinctrl: airoha: an7583: add support for pon_alt pinmux Add support for pon pin function for pon_alt pin group. Signed-off-by: Mikhail Kshevetskiy Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/pinctrl-an7583.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c index dc88cbd8746b..2e145ef5a224 100644 --- a/drivers/pinctrl/airoha/pinctrl-an7583.c +++ b/drivers/pinctrl/airoha/pinctrl-an7583.c @@ -38,6 +38,7 @@ #define GPIO_SPI_CS1_MODE_MASK BIT(0) #define REG_GPIO_PON_MODE 0x021c +#define GPIO_PON_ALT_MODE_MASK BIT(27) #define MDIO_0_GPIO_MODE_MASK BIT(26) #define MDC_0_GPIO_MODE_MASK BIT(25) #define UART_RXD_GPIO_MODE_MASK BIT(24) @@ -391,6 +392,7 @@ static struct pinctrl_pin_desc pinctrl_pins[] = { }; static const int pon_pins[] = { 15, 16, 17, 18, 19, 20 }; +static const int pon_alt_pins[] = { 36, 37, 38, 39, 40 }; static const int pon_tod_1pps_pins[] = { 32 }; static const int gsw_tod_1pps_pins[] = { 32 }; static const int sipo_pins[] = { 34, 35 }; @@ -480,6 +482,7 @@ static const int pcie_reset1_pins[] = { 52 }; static const struct pingroup pinctrl_groups[] = { PINCTRL_PIN_GROUP("pon", pon), + PINCTRL_PIN_GROUP("pon_alt", pon_alt), PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps), PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps), PINCTRL_PIN_GROUP("sipo", sipo), @@ -564,7 +567,7 @@ static const struct pingroup pinctrl_groups[] = { PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1), }; -static const char *const pon_groups[] = { "pon" }; +static const char *const pon_groups[] = { "pon", "pon_alt" }; static const char *const tod_1pps_groups[] = { "pon_tod_1pps", "gsw_tod_1pps" }; @@ -632,10 +635,19 @@ static const struct airoha_pinctrl_func_group pon_func_group[] = { .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE, - GPIO_PON_MODE_MASK, + GPIO_PON_MODE_MASK | GPIO_PON_ALT_MODE_MASK, GPIO_PON_MODE_MASK }, .regmap_size = 1, + }, { + .name = "pon_alt", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PON_MODE_MASK | GPIO_PON_ALT_MODE_MASK, + GPIO_PON_ALT_MODE_MASK + }, + .regmap_size = 1, }, }; From 13243f4178b02c7bea413db03292d1dad65af577 Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:06:10 +0300 Subject: [PATCH 114/130] pinctrl: airoha: an7583: add support for olt pinmux Add support for olt pin function for olt pin group. Signed-off-by: Mikhail Kshevetskiy Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/pinctrl-an7583.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c index 2e145ef5a224..031a8b36e002 100644 --- a/drivers/pinctrl/airoha/pinctrl-an7583.c +++ b/drivers/pinctrl/airoha/pinctrl-an7583.c @@ -53,6 +53,7 @@ #define I2C0_SCL_GPIO_MODE_MASK BIT(15) #define GPIO_PARALLEL_NAND_MODE_MASK BIT(14) #define GPIO_SGMII_MDIO_MODE_MASK BIT(13) +#define GPIO_OLT_MODE_MASK BIT(12) #define SIPO_RCLK_MODE_MASK BIT(11) #define GPIO_PCIE_RESET1_MASK BIT(10) #define GPIO_PCIE_RESET0_MASK BIT(9) @@ -393,6 +394,7 @@ static struct pinctrl_pin_desc pinctrl_pins[] = { static const int pon_pins[] = { 15, 16, 17, 18, 19, 20 }; static const int pon_alt_pins[] = { 36, 37, 38, 39, 40 }; +static const int olt_pins[] = { 36, 37, 38, 39, 40 }; static const int pon_tod_1pps_pins[] = { 32 }; static const int gsw_tod_1pps_pins[] = { 32 }; static const int sipo_pins[] = { 34, 35 }; @@ -483,6 +485,7 @@ static const int pcie_reset1_pins[] = { 52 }; static const struct pingroup pinctrl_groups[] = { PINCTRL_PIN_GROUP("pon", pon), PINCTRL_PIN_GROUP("pon_alt", pon_alt), + PINCTRL_PIN_GROUP("olt", olt), PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps), PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps), PINCTRL_PIN_GROUP("sipo", sipo), @@ -568,6 +571,7 @@ static const struct pingroup pinctrl_groups[] = { }; static const char *const pon_groups[] = { "pon", "pon_alt" }; +static const char *const olt_groups[] = { "olt" }; static const char *const tod_1pps_groups[] = { "pon_tod_1pps", "gsw_tod_1pps" }; @@ -651,6 +655,19 @@ static const struct airoha_pinctrl_func_group pon_func_group[] = { }, }; +static const struct airoha_pinctrl_func_group olt_func_group[] = { + { + .name = "olt", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_OLT_MODE_MASK, + GPIO_OLT_MODE_MASK + }, + .regmap_size = 1, + }, +}; + static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = { { .name = "pon_tod_1pps", @@ -1190,6 +1207,7 @@ static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = { static const struct airoha_pinctrl_func pinctrl_funcs[] = { PINCTRL_FUNC_DESC("pon", pon), + PINCTRL_FUNC_DESC("olt", olt), PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), PINCTRL_FUNC_DESC("sipo", sipo), PINCTRL_FUNC_DESC("mdio", mdio), From 973fdfd62ccf523c9e309f89784207b8f9e8fbdc Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:06:11 +0300 Subject: [PATCH 115/130] dt-bindings: pinctrl: airoha: add support of en7523 pin controller Introduce device tree binding schema for Airoha EN7523 SoC pin controller. Signed-off-by: Mikhail Kshevetskiy Signed-off-by: Linus Walleij --- .../pinctrl/airoha,en7523-pinctrl.yaml | 378 ++++++++++++++++++ 1 file changed, 378 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/airoha,en7523-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,en7523-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,en7523-pinctrl.yaml new file mode 100644 index 000000000000..599f80e94432 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/airoha,en7523-pinctrl.yaml @@ -0,0 +1,378 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/airoha,en7523-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha EN7523 Pin Controller + +maintainers: + - Lorenzo Bianconi + +description: + The Airoha's EN7523 Pin controller is used to control SoC pins. + +properties: + compatible: + const: airoha,en7523-pinctrl + + interrupts: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - interrupts + - gpio-controller + - gpio-ranges + - "#gpio-cells" + - interrupt-controller + - "#interrupt-cells" + +patternProperties: + '-pins$': + type: object + + patternProperties: + '^mux(-|$)': + type: object + + description: + pinmux configuration nodes. + + $ref: /schemas/pinctrl/pinmux-node.yaml + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [pon, tod_1pps, sipo, mdio, uart, i2c, jtag, pcm, spi, + pcm_spi, i2s, gpio, pcie_reset, pwm, phy1_led0, + phy2_led0, phy3_led0, phy4_led0, phy1_led1, phy2_led1, + phy3_led1, phy4_led1] + + groups: + description: + An array of strings. Each string contains the name of a group. + + required: + - function + - groups + + allOf: + - if: + properties: + function: + const: pon + then: + properties: + groups: + enum: [pon] + - if: + properties: + function: + const: tod_1pps + then: + properties: + groups: + enum: [pon_tod_1pps, gsw_tod_1pps] + - if: + properties: + function: + const: sipo + then: + properties: + groups: + enum: [sipo, sipo_rclk] + - if: + properties: + function: + const: mdio + then: + properties: + groups: + enum: [mdio] + - if: + properties: + function: + const: uart + then: + properties: + groups: + items: + enum: [uart2, npu_uart] + maxItems: 2 + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c1] + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag_udi, jtag_dfd] + - if: + properties: + function: + const: pcm + then: + properties: + groups: + enum: [pcm1, pcm2] + - if: + properties: + function: + const: spi + then: + properties: + groups: + items: + enum: [spi_quad, spi_cs1] + maxItems: 2 + - if: + properties: + function: + const: pcm_spi + then: + properties: + groups: + items: + enum: [pcm_spi, pcm_spi_int, pcm_spi_rst, pcm_spi_cs1, + pcm_spi_cs2_p156, pcm_spi_cs2_p128, pcm_spi_cs3, + pcm_spi_cs4] + maxItems: 7 + - if: + properties: + function: + const: i2s + then: + properties: + groups: + enum: [i2s] + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [gpio28, gpio29] + - if: + properties: + function: + const: pcie_reset + then: + properties: + groups: + enum: [pcie_reset0, pcie_reset1] + - if: + properties: + function: + const: pwm + then: + properties: + groups: + enum: [gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, + gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, + gpio14, gpio15, gpio16, gpio17, gpio18, gpio19, + gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, + gpio26, gpio27, gpio28, gpio29] + - if: + properties: + function: + const: phy1_led0 + then: + properties: + groups: + enum: [gpio22, gpio23, gpio24, gpio25] + - if: + properties: + function: + const: phy2_led0 + then: + properties: + groups: + enum: [gpio22, gpio23, gpio24, gpio25] + - if: + properties: + function: + const: phy3_led0 + then: + properties: + groups: + enum: [gpio22, gpio23, gpio24, gpio25] + - if: + properties: + function: + const: phy4_led0 + then: + properties: + groups: + enum: [gpio22, gpio23, gpio24, gpio25] + - if: + properties: + function: + const: phy1_led1 + then: + properties: + groups: + enum: [gpio7, gpio6, gpio5, gpio4] + - if: + properties: + function: + const: phy2_led1 + then: + properties: + groups: + enum: [gpio7, gpio6, gpio5, gpio4] + - if: + properties: + function: + const: phy3_led1 + then: + properties: + groups: + enum: [gpio7, gpio6, gpio5, gpio4] + - if: + properties: + function: + const: phy4_led1 + then: + properties: + groups: + enum: [gpio7, gpio6, gpio5, gpio4] + + additionalProperties: false + + '^conf(-|$)': + type: object + + description: + pinconf configuration nodes. + + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pins: + description: + An array of strings. Each string contains the name of a pin. + items: + enum: [i2c_sda, i2c_scl, spi_cs0, spi_clk, spi_mosi, spi_miso, + uart1_txd, uart1_rxd, gpio0, gpio1, gpio2, gpio3, gpio4, + gpio5, gpio6, gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, + gpio13, gpio14, gpio15, gpio16, gpio17, gpio18, gpio19, + gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, gpio26, + gpio27, pcie_reset0, pcie_reset1] + minItems: 1 + maxItems: 38 + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + input-enable: true + + output-enable: true + + output-low: true + + output-high: true + + drive-open-drain: true + + drive-strength: + description: + Selects the drive strength for MIO pins, in mA. + enum: [2, 4, 6, 8] + + required: + - pins + + additionalProperties: false + + additionalProperties: false + +additionalProperties: false + +examples: + - | + #include + + pinctrl { + compatible = "airoha,en7523-pinctrl"; + + interrupt-parent = <&gic>; + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + gpio-ranges = <&pinctrl 0 12 30>; + + pcie1-rst-pins { + conf { + pins = "pcie_reset1"; + drive-open-drain = <1>; + }; + }; + + pwm-pins { + mux { + function = "pwm"; + groups = "gpio18"; + }; + }; + + spi-pins { + mux { + function = "spi"; + groups = "spi_quad", "spi_cs1"; + }; + }; + + uart2-pins { + mux { + function = "uart"; + groups = "uart2"; + }; + }; + + mdio-pins { + mux { + function = "mdio"; + groups = "mdio"; + }; + + conf { + pins = "gpio2"; + output-enable; + }; + }; + }; From 3b8247058338a28de8f66bfc51dac176e1d9259f Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:06:12 +0300 Subject: [PATCH 116/130] pinctrl: airoha: add support of en7523 SoC This patch adds support of Airoha en7523 SoC pin controller. Signed-off-by: Mikhail Kshevetskiy Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/Kconfig | 9 + drivers/pinctrl/airoha/Makefile | 1 + drivers/pinctrl/airoha/pinctrl-en7523.c | 1156 +++++++++++++++++++++++ 3 files changed, 1166 insertions(+) create mode 100644 drivers/pinctrl/airoha/pinctrl-en7523.c diff --git a/drivers/pinctrl/airoha/Kconfig b/drivers/pinctrl/airoha/Kconfig index dae6608bc72d..363d6b7ff906 100644 --- a/drivers/pinctrl/airoha/Kconfig +++ b/drivers/pinctrl/airoha/Kconfig @@ -15,6 +15,7 @@ config PINCTRL_AIROHA select REGMAP_MMIO imply PINCTRL_AIROHA_AN7581 imply PINCTRL_AIROHA_AN7583 + imply PINCTRL_AIROHA_EN7523 help Shared pin controller and gpio driver code for different Airoha SoCs. @@ -35,4 +36,12 @@ config PINCTRL_AIROHA_AN7583 Say yes here to support pin controller and gpio driver on Airoha AN7583, AN7553, AN7567 and other compatible SoCs. +config PINCTRL_AIROHA_EN7523 + tristate "EN7523 pinctrl" + depends on ARM || COMPILE_TEST + depends on PINCTRL_AIROHA + help + Say yes here to support pin controller and gpio driver + on Airoha EN7523, EN7529, EN7562 and other compatible SoCs. + endmenu diff --git a/drivers/pinctrl/airoha/Makefile b/drivers/pinctrl/airoha/Makefile index cfd68c45ae0f..8b9202321ba8 100644 --- a/drivers/pinctrl/airoha/Makefile +++ b/drivers/pinctrl/airoha/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_AIROHA) += pinctrl-airoha.o # SoC drivers obj-$(CONFIG_PINCTRL_AIROHA_AN7581) += pinctrl-an7581.o obj-$(CONFIG_PINCTRL_AIROHA_AN7583) += pinctrl-an7583.o +obj-$(CONFIG_PINCTRL_AIROHA_EN7523) += pinctrl-en7523.o diff --git a/drivers/pinctrl/airoha/pinctrl-en7523.c b/drivers/pinctrl/airoha/pinctrl-en7523.c new file mode 100644 index 000000000000..91490418e9ab --- /dev/null +++ b/drivers/pinctrl/airoha/pinctrl-en7523.c @@ -0,0 +1,1156 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: Lorenzo Bianconi + * Author: Benjamin Larsson + * Author: Markus Gothe + * Author: Matheus Sampaio Queiroga + * Author: Mikhail Kshevetskiy + */ +#include "airoha-common.h" + +/* MUX */ +#define REG_GPIO_2ND_I2C_MODE 0x0210 +#define GPIO_I2S_MODE_MASK BIT(12) +#define GPIO_I2C_SLAVE_MODE_MODE BIT(11) +#define GPIO_LAN3_LED1_MODE_MASK BIT(10) +#define GPIO_LAN3_LED0_MODE_MASK BIT(9) +#define GPIO_LAN2_LED1_MODE_MASK BIT(8) +#define GPIO_LAN2_LED0_MODE_MASK BIT(7) +#define GPIO_LAN1_LED1_MODE_MASK BIT(6) +#define GPIO_LAN1_LED0_MODE_MASK BIT(5) +#define GPIO_LAN0_LED1_MODE_MASK BIT(4) +#define GPIO_LAN0_LED0_MODE_MASK BIT(3) +#define PON_TOD_1PPS_MODE_MASK BIT(2) +#define GSW_TOD_1PPS_MODE_MASK BIT(1) +#define GPIO_2ND_I2C_MODE_MASK BIT(0) + +#define REG_GPIO_SPI_CS1_MODE 0x0214 +#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21) +#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20) +#define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19) +#define GPIO_PCM_SPI_CS2_MODE_P128_MASK BIT(18) +#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17) +#define GPIO_PCM_SPI_MODE_MASK BIT(16) +#define GPIO_PCM2_MODE_MASK BIT(13) +#define GPIO_PCM1_MODE_MASK BIT(12) +#define GPIO_PCM_INT_MODE_MASK BIT(9) +#define GPIO_PCM_RESET_MODE_MASK BIT(8) +#define GPIO_SPI_QUAD_MODE_MASK BIT(4) +#define GPIO_SPI_CS1_MODE_MASK BIT(0) + +#define REG_GPIO_PON_MODE 0x0218 +#define GPIO_SGMII_MDIO_MODE_MASK BIT(13) +#define SIPO_RCLK_MODE_MASK BIT(11) +#define GPIO_PCIE_RESET1_MASK BIT(10) +#define GPIO_PCIE_RESET0_MASK BIT(9) +#define GPIO_UART2_MODE_MASK BIT(3) +#define GPIO_SIPO_MODE_MASK BIT(2) +#define GPIO_PON_MODE_MASK BIT(0) + +#define REG_NPU_UART_EN 0x0220 +#define JTAG_UDI_EN_MASK BIT(4) +#define JTAG_DFD_EN_MASK BIT(3) +#define NPU_UART_EN_MASK BIT(2) + +#define REG_FORCE_GPIO_EN 0x0224 +#define FORCE_GPIO_EN(n) BIT(n) + +/* LED MAP */ +#define REG_LAN_LED0_MAPPING 0x0278 +#define REG_LAN_LED1_MAPPING 0x027c + +#define LAN3_LED_MAPPING_MASK GENMASK(14, 12) +#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n)) + +#define LAN2_LED_MAPPING_MASK GENMASK(10, 8) +#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n)) + +#define LAN1_LED_MAPPING_MASK GENMASK(6, 4) +#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n)) + +#define LAN0_LED_MAPPING_MASK GENMASK(2, 0) +#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n)) + +/* CONF */ +#define REG_I2C_SDA_E2 0x001c +#define SPI_MISO_E2_MASK BIT(13) +#define SPI_MOSI_E2_MASK BIT(12) +#define SPI_CLK_E2_MASK BIT(11) +#define SPI_CS0_E2_MASK BIT(10) +#define PCIE1_RESET_E2_MASK BIT(9) +#define PCIE0_RESET_E2_MASK BIT(8) +#define UART1_RXD_E2_MASK BIT(3) +#define UART1_TXD_E2_MASK BIT(2) +#define I2C_SCL_E2_MASK BIT(1) +#define I2C_SDA_E2_MASK BIT(0) + +#define REG_I2C_SDA_E4 0x0020 +#define SPI_MISO_E4_MASK BIT(13) +#define SPI_MOSI_E4_MASK BIT(12) +#define SPI_CLK_E4_MASK BIT(11) +#define SPI_CS0_E4_MASK BIT(10) +#define PCIE1_RESET_E4_MASK BIT(9) +#define PCIE0_RESET_E4_MASK BIT(8) +#define UART1_RXD_E4_MASK BIT(3) +#define UART1_TXD_E4_MASK BIT(2) +#define I2C_SCL_E4_MASK BIT(1) +#define I2C_SDA_E4_MASK BIT(0) + +#define REG_GPIO_L_E2 0x0024 +#define REG_GPIO_L_E4 0x0028 + +#define REG_I2C_SDA_PU 0x0044 +#define SPI_MISO_PU_MASK BIT(13) +#define SPI_MOSI_PU_MASK BIT(12) +#define SPI_CLK_PU_MASK BIT(11) +#define SPI_CS0_PU_MASK BIT(10) +#define PCIE1_RESET_PU_MASK BIT(9) +#define PCIE0_RESET_PU_MASK BIT(8) +#define UART1_RXD_PU_MASK BIT(3) +#define UART1_TXD_PU_MASK BIT(2) +#define I2C_SCL_PU_MASK BIT(1) +#define I2C_SDA_PU_MASK BIT(0) + +#define REG_I2C_SDA_PD 0x0048 +#define SPI_MISO_PD_MASK BIT(13) +#define SPI_MOSI_PD_MASK BIT(12) +#define SPI_CLK_PD_MASK BIT(11) +#define SPI_CS0_PD_MASK BIT(10) +#define PCIE1_RESET_PD_MASK BIT(9) +#define PCIE0_RESET_PD_MASK BIT(8) +#define UART1_RXD_PD_MASK BIT(3) +#define UART1_TXD_PD_MASK BIT(2) +#define I2C_SCL_PD_MASK BIT(1) +#define I2C_SDA_PD_MASK BIT(0) + +#define REG_GPIO_L_PU 0x004c +#define REG_GPIO_L_PD 0x0050 + +/* PWM MODE CONF */ +#define REG_GPIO_FLASH_MODE_CFG 0x0034 +#define GPIO15_FLASH_MODE_CFG BIT(15) +#define GPIO14_FLASH_MODE_CFG BIT(14) +#define GPIO13_FLASH_MODE_CFG BIT(13) +#define GPIO12_FLASH_MODE_CFG BIT(12) +#define GPIO11_FLASH_MODE_CFG BIT(11) +#define GPIO10_FLASH_MODE_CFG BIT(10) +#define GPIO9_FLASH_MODE_CFG BIT(9) +#define GPIO8_FLASH_MODE_CFG BIT(8) +#define GPIO7_FLASH_MODE_CFG BIT(7) +#define GPIO6_FLASH_MODE_CFG BIT(6) +#define GPIO5_FLASH_MODE_CFG BIT(5) +#define GPIO4_FLASH_MODE_CFG BIT(4) +#define GPIO3_FLASH_MODE_CFG BIT(3) +#define GPIO2_FLASH_MODE_CFG BIT(2) +#define GPIO1_FLASH_MODE_CFG BIT(1) +#define GPIO0_FLASH_MODE_CFG BIT(0) + +/* PWM MODE CONF EXT */ +#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068 +#define GPIO51_FLASH_MODE_CFG BIT(31) +#define GPIO50_FLASH_MODE_CFG BIT(30) +#define GPIO49_FLASH_MODE_CFG BIT(29) +#define GPIO48_FLASH_MODE_CFG BIT(28) +#define GPIO47_FLASH_MODE_CFG BIT(27) +#define GPIO46_FLASH_MODE_CFG BIT(26) +#define GPIO45_FLASH_MODE_CFG BIT(25) +#define GPIO44_FLASH_MODE_CFG BIT(24) +#define GPIO43_FLASH_MODE_CFG BIT(23) +#define GPIO42_FLASH_MODE_CFG BIT(22) +#define GPIO41_FLASH_MODE_CFG BIT(21) +#define GPIO40_FLASH_MODE_CFG BIT(20) +#define GPIO39_FLASH_MODE_CFG BIT(19) +#define GPIO38_FLASH_MODE_CFG BIT(18) +#define GPIO37_FLASH_MODE_CFG BIT(17) +#define GPIO36_FLASH_MODE_CFG BIT(16) +#define GPIO31_FLASH_MODE_CFG BIT(15) +#define GPIO30_FLASH_MODE_CFG BIT(14) +#define GPIO29_FLASH_MODE_CFG BIT(13) +#define GPIO28_FLASH_MODE_CFG BIT(12) +#define GPIO27_FLASH_MODE_CFG BIT(11) +#define GPIO26_FLASH_MODE_CFG BIT(10) +#define GPIO25_FLASH_MODE_CFG BIT(9) +#define GPIO24_FLASH_MODE_CFG BIT(8) +#define GPIO23_FLASH_MODE_CFG BIT(7) +#define GPIO22_FLASH_MODE_CFG BIT(6) +#define GPIO21_FLASH_MODE_CFG BIT(5) +#define GPIO20_FLASH_MODE_CFG BIT(4) +#define GPIO19_FLASH_MODE_CFG BIT(3) +#define GPIO18_FLASH_MODE_CFG BIT(2) +#define GPIO17_FLASH_MODE_CFG BIT(1) +#define GPIO16_FLASH_MODE_CFG BIT(0) + +#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + 0 \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (smux_val), \ + (smux_val) \ + }, \ + .regmap_size = 2, \ + } + +/* PWM */ +#define AIROHA_PINCTRL_PWM(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_MUX, \ + REG_GPIO_FLASH_MODE_CFG, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (smux_val), \ + (smux_val) \ + }, \ + .regmap_size = 2, \ + } + +#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_2ND_I2C_MODE, \ + (mux_val), \ + (mux_val), \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_LAN_LED0_MAPPING, \ + (map_mask), \ + (map_val), \ + }, \ + .regmap_size = 2, \ + } + +#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_2ND_I2C_MODE, \ + (mux_val), \ + (mux_val), \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_LAN_LED1_MAPPING, \ + (map_mask), \ + (map_val), \ + }, \ + .regmap_size = 2, \ + } + +static struct pinctrl_pin_desc pinctrl_pins[] = { + PINCTRL_PIN(2, "i2c_sda"), + PINCTRL_PIN(3, "i2c_scl"), + PINCTRL_PIN(4, "spi_cs0"), + PINCTRL_PIN(5, "spi_clk"), + PINCTRL_PIN(6, "spi_mosi"), + PINCTRL_PIN(7, "spi_miso"), + PINCTRL_PIN(8, "uart1_txd"), + PINCTRL_PIN(9, "uart1_rxd"), + PINCTRL_PIN(12, "gpio0"), + PINCTRL_PIN(13, "gpio1"), + PINCTRL_PIN(14, "gpio2"), + PINCTRL_PIN(15, "gpio3"), + PINCTRL_PIN(16, "gpio4"), + PINCTRL_PIN(17, "gpio5"), + PINCTRL_PIN(18, "gpio6"), + PINCTRL_PIN(19, "gpio7"), + PINCTRL_PIN(20, "gpio8"), + PINCTRL_PIN(21, "gpio9"), + PINCTRL_PIN(22, "gpio10"), + PINCTRL_PIN(23, "gpio11"), + PINCTRL_PIN(24, "gpio12"), + PINCTRL_PIN(25, "gpio13"), + PINCTRL_PIN(26, "gpio14"), + PINCTRL_PIN(27, "gpio15"), + PINCTRL_PIN(28, "gpio16"), + PINCTRL_PIN(29, "gpio17"), + PINCTRL_PIN(30, "gpio18"), + PINCTRL_PIN(31, "gpio19"), + PINCTRL_PIN(32, "gpio20"), + PINCTRL_PIN(33, "gpio21"), + PINCTRL_PIN(34, "gpio22"), + PINCTRL_PIN(35, "gpio23"), + PINCTRL_PIN(36, "gpio24"), + PINCTRL_PIN(37, "gpio25"), + PINCTRL_PIN(38, "gpio26"), + PINCTRL_PIN(39, "gpio27"), + PINCTRL_PIN(40, "pcie_reset0"), + PINCTRL_PIN(41, "pcie_reset1"), +}; + +static const int pon_pins[] = { 28, 29, 30, 31, 32, 33 }; +static const int pon_tod_1pps_pins[] = { 21 }; +static const int gsw_tod_1pps_pins[] = { 21 }; +static const int sipo_pins[] = { 13, 38 }; +static const int sipo_rclk_pins[] = { 13, 30, 38 }; +static const int mdio_pins[] = { 20, 21 }; +static const int uart2_pins[] = { 20, 21 }; +static const int npu_uart_pins[] = { 13, 38 }; +static const int i2c0_pins[] = { 2, 3 }; +static const int i2c1_pins[] = { 14, 15 }; +static const int jtag_udi_pins[] = { 34, 35, 36, 37, 38 }; +static const int jtag_dfd_pins[] = { 34, 35, 36, 37, 38 }; +static const int i2s_pins[] = { 16, 17, 18, 19 }; +static const int pcm1_pins[] = { 24, 25, 26, 27 }; +static const int pcm2_pins[] = { 16, 17, 18, 19 }; +static const int spi_pins[] = { 4, 5, 6, 7 }; +static const int spi_quad_pins[] = { 14, 15 }; +static const int spi_cs1_pins[] = { 21 }; +static const int pcm_spi_pins[] = { 16, 17, 18, 19, 24, 25, 26, 27 }; +static const int pcm_spi_int_pins[] = { 15 }; +static const int pcm_spi_rst_pins[] = { 14 }; +static const int pcm_spi_cs1_pins[] = { 22 }; +static const int pcm_spi_cs2_p128_pins[] = { 39 }; +static const int pcm_spi_cs2_p156_pins[] = { 39 }; +static const int pcm_spi_cs3_pins[] = { 20 }; +static const int pcm_spi_cs4_pins[] = { 23 }; +static const int gpio0_pins[] = { 12 }; +static const int gpio1_pins[] = { 13 }; +static const int gpio2_pins[] = { 14 }; +static const int gpio3_pins[] = { 15 }; +static const int gpio4_pins[] = { 16 }; +static const int gpio5_pins[] = { 17 }; +static const int gpio6_pins[] = { 18 }; +static const int gpio7_pins[] = { 19 }; +static const int gpio8_pins[] = { 20 }; +static const int gpio9_pins[] = { 21 }; +static const int gpio10_pins[] = { 22 }; +static const int gpio11_pins[] = { 23 }; +static const int gpio12_pins[] = { 24 }; +static const int gpio13_pins[] = { 25 }; +static const int gpio14_pins[] = { 26 }; +static const int gpio15_pins[] = { 27 }; +static const int gpio16_pins[] = { 28 }; +static const int gpio17_pins[] = { 29 }; +static const int gpio18_pins[] = { 30 }; +static const int gpio19_pins[] = { 31 }; +static const int gpio20_pins[] = { 32 }; +static const int gpio21_pins[] = { 33 }; +static const int gpio22_pins[] = { 34 }; +static const int gpio23_pins[] = { 35 }; +static const int gpio24_pins[] = { 36 }; +static const int gpio25_pins[] = { 37 }; +static const int gpio26_pins[] = { 38 }; +static const int gpio27_pins[] = { 39 }; +static const int gpio28_pins[] = { 40 }; +static const int gpio29_pins[] = { 41 }; +static const int pcie_reset0_pins[] = { 40 }; +static const int pcie_reset1_pins[] = { 41 }; + +static const struct pingroup pinctrl_groups[] = { + PINCTRL_PIN_GROUP("pon", pon), + PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps), + PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps), + PINCTRL_PIN_GROUP("sipo", sipo), + PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk), + PINCTRL_PIN_GROUP("mdio", mdio), + PINCTRL_PIN_GROUP("uart2", uart2), + PINCTRL_PIN_GROUP("npu_uart", npu_uart), + PINCTRL_PIN_GROUP("i2c0", i2c0), + PINCTRL_PIN_GROUP("i2c1", i2c1), + PINCTRL_PIN_GROUP("jtag_udi", jtag_udi), + PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd), + PINCTRL_PIN_GROUP("i2s", i2s), + PINCTRL_PIN_GROUP("pcm1", pcm1), + PINCTRL_PIN_GROUP("pcm2", pcm2), + PINCTRL_PIN_GROUP("spi", spi), + PINCTRL_PIN_GROUP("spi_quad", spi_quad), + PINCTRL_PIN_GROUP("spi_cs1", spi_cs1), + PINCTRL_PIN_GROUP("pcm_spi", pcm_spi), + PINCTRL_PIN_GROUP("pcm_spi_int", pcm_spi_int), + PINCTRL_PIN_GROUP("pcm_spi_rst", pcm_spi_rst), + PINCTRL_PIN_GROUP("pcm_spi_cs1", pcm_spi_cs1), + PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", pcm_spi_cs2_p128), + PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", pcm_spi_cs2_p156), + PINCTRL_PIN_GROUP("pcm_spi_cs3", pcm_spi_cs3), + PINCTRL_PIN_GROUP("pcm_spi_cs4", pcm_spi_cs4), + PINCTRL_PIN_GROUP("gpio0", gpio0), + PINCTRL_PIN_GROUP("gpio1", gpio1), + PINCTRL_PIN_GROUP("gpio2", gpio2), + PINCTRL_PIN_GROUP("gpio3", gpio3), + PINCTRL_PIN_GROUP("gpio4", gpio4), + PINCTRL_PIN_GROUP("gpio5", gpio5), + PINCTRL_PIN_GROUP("gpio6", gpio6), + PINCTRL_PIN_GROUP("gpio7", gpio7), + PINCTRL_PIN_GROUP("gpio8", gpio8), + PINCTRL_PIN_GROUP("gpio9", gpio9), + PINCTRL_PIN_GROUP("gpio10", gpio10), + PINCTRL_PIN_GROUP("gpio11", gpio11), + PINCTRL_PIN_GROUP("gpio12", gpio12), + PINCTRL_PIN_GROUP("gpio13", gpio13), + PINCTRL_PIN_GROUP("gpio14", gpio14), + PINCTRL_PIN_GROUP("gpio15", gpio15), + PINCTRL_PIN_GROUP("gpio16", gpio16), + PINCTRL_PIN_GROUP("gpio17", gpio17), + PINCTRL_PIN_GROUP("gpio18", gpio18), + PINCTRL_PIN_GROUP("gpio19", gpio19), + PINCTRL_PIN_GROUP("gpio20", gpio20), + PINCTRL_PIN_GROUP("gpio21", gpio21), + PINCTRL_PIN_GROUP("gpio22", gpio22), + PINCTRL_PIN_GROUP("gpio23", gpio23), + PINCTRL_PIN_GROUP("gpio24", gpio24), + PINCTRL_PIN_GROUP("gpio25", gpio25), + PINCTRL_PIN_GROUP("gpio26", gpio26), + PINCTRL_PIN_GROUP("gpio27", gpio27), + PINCTRL_PIN_GROUP("gpio28", gpio28), + PINCTRL_PIN_GROUP("gpio29", gpio29), + PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0), + PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1), +}; + +static const char *const pon_groups[] = { "pon" }; +static const char *const tod_1pps_groups[] = { + "pon_tod_1pps", "gsw_tod_1pps" +}; +static const char *const sipo_groups[] = { "sipo", "sipo_rclk" }; +static const char *const mdio_groups[] = { "mdio" }; +static const char *const uart_groups[] = { "uart2", "npu_uart" }; +static const char *const i2c_groups[] = { "i2c1" }; +static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" }; +static const char *const pcm_groups[] = { "pcm1", "pcm2" }; +static const char *const spi_groups[] = { "spi_quad", "spi_cs1" }; +static const char *const pcm_spi_groups[] = { + "pcm_spi", "pcm_spi_int", "pcm_spi_rst", "pcm_spi_cs1", + "pcm_spi_cs2_p156", "pcm_spi_cs2_p128", "pcm_spi_cs3", "pcm_spi_cs4" +}; +static const char *const i2s_groups[] = { "i2s" }; +static const char *const gpio_groups[] = { "gpio28", "gpio29" }; +static const char *const pcie_reset_groups[] = { + "pcie_reset0", "pcie_reset1" +}; +static const char *const pwm_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29" +}; +static const char *const phy1_led0_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25" +}; +static const char *const phy2_led0_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25" +}; +static const char *const phy3_led0_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25" +}; +static const char *const phy4_led0_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25" +}; +static const char *const phy1_led1_groups[] = { + "gpio7", "gpio6", "gpio5", "gpio4" +}; +static const char *const phy2_led1_groups[] = { + "gpio7", "gpio6", "gpio5", "gpio4" +}; +static const char *const phy3_led1_groups[] = { + "gpio7", "gpio6", "gpio5", "gpio4" +}; +static const char *const phy4_led1_groups[] = { + "gpio7", "gpio6", "gpio5", "gpio4" +}; + +static const struct airoha_pinctrl_func_group pon_func_group[] = { + { + .name = "pon", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PON_MODE_MASK, + GPIO_PON_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = { + { + .name = "pon_tod_1pps", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + PON_TOD_1PPS_MODE_MASK, + PON_TOD_1PPS_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "gsw_tod_1pps", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GSW_TOD_1PPS_MODE_MASK, + GSW_TOD_1PPS_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group sipo_func_group[] = { + { + .name = "sipo", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "sipo_rclk", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group mdio_func_group[] = { + { + .name = "mdio", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SGMII_MDIO_MODE_MASK, + GPIO_SGMII_MDIO_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group uart_func_group[] = { + { + .name = "uart2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART2_MODE_MASK, + GPIO_UART2_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "npu_uart", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + NPU_UART_EN_MASK, + NPU_UART_EN_MASK + }, + .regmap_size = 1, + } +}; + +static const struct airoha_pinctrl_func_group i2c_func_group[] = { + { + .name = "i2c1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_2ND_I2C_MODE_MASK, + GPIO_2ND_I2C_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group jtag_func_group[] = { + { + .name = "jtag_udi", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + JTAG_UDI_EN_MASK, + JTAG_UDI_EN_MASK + }, + .regmap_size = 1, + }, { + .name = "jtag_dfd", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + JTAG_DFD_EN_MASK, + JTAG_DFD_EN_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pcm_func_group[] = { + { + .name = "pcm1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM1_MODE_MASK, + GPIO_PCM1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM2_MODE_MASK, + GPIO_PCM2_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group spi_func_group[] = { + { + .name = "spi_quad", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_QUAD_MODE_MASK, + GPIO_SPI_QUAD_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS1_MODE_MASK, + GPIO_SPI_CS1_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = { + { + .name = "pcm_spi", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_MODE_MASK, + GPIO_PCM_SPI_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_int", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_INT_MODE_MASK, + GPIO_PCM_INT_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_rst", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_RESET_MODE_MASK, + GPIO_PCM_RESET_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS1_MODE_MASK, + GPIO_PCM_SPI_CS1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs2_p128", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS2_MODE_P128_MASK, + GPIO_PCM_SPI_CS2_MODE_P128_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs2_p156", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS2_MODE_P156_MASK, + GPIO_PCM_SPI_CS2_MODE_P156_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs3", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS3_MODE_MASK, + GPIO_PCM_SPI_CS3_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs4", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS4_MODE_MASK, + GPIO_PCM_SPI_CS4_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group i2s_func_group[] = { + { + .name = "i2s", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_I2S_MODE_MASK, + GPIO_I2S_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group gpio_func_group[] = { + AIROHA_PINCTRL_GPIO_EXT("gpio28", GPIO28_FLASH_MODE_CFG, + GPIO_PCIE_RESET0_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio29", GPIO29_FLASH_MODE_CFG, + GPIO_PCIE_RESET1_MASK), +}; + +static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = { + { + .name = "pcie_reset0", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET0_MASK, + 0 + }, + .regmap_size = 1, + }, { + .name = "pcie_reset1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET1_MASK, + 0 + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pwm_func_group[] = { + AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio28", GPIO28_FLASH_MODE_CFG, + GPIO_PCIE_RESET0_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio29", GPIO29_FLASH_MODE_CFG, + GPIO_PCIE_RESET1_MASK), +}; + +static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), +}; + +static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), +}; + +static const struct airoha_pinctrl_func pinctrl_funcs[] = { + PINCTRL_FUNC_DESC("pon", pon), + PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), + PINCTRL_FUNC_DESC("sipo", sipo), + PINCTRL_FUNC_DESC("mdio", mdio), + PINCTRL_FUNC_DESC("uart", uart), + PINCTRL_FUNC_DESC("i2c", i2c), + PINCTRL_FUNC_DESC("jtag", jtag), + PINCTRL_FUNC_DESC("pcm", pcm), + PINCTRL_FUNC_DESC("spi", spi), + PINCTRL_FUNC_DESC("pcm_spi", pcm_spi), + PINCTRL_FUNC_DESC("i2s", i2s), + PINCTRL_FUNC_DESC("gpio", gpio), + PINCTRL_FUNC_DESC("pcie_reset", pcie_reset), + PINCTRL_FUNC_DESC("pwm", pwm), + PINCTRL_FUNC_DESC("phy1_led0", phy1_led0), + PINCTRL_FUNC_DESC("phy2_led0", phy2_led0), + PINCTRL_FUNC_DESC("phy3_led0", phy3_led0), + PINCTRL_FUNC_DESC("phy4_led0", phy4_led0), + PINCTRL_FUNC_DESC("phy1_led1", phy1_led1), + PINCTRL_FUNC_DESC("phy2_led1", phy2_led1), + PINCTRL_FUNC_DESC("phy3_led1", phy3_led1), + PINCTRL_FUNC_DESC("phy4_led1", phy4_led1), +}; + +static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = { + PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), + PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), + PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), + PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), + PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK), + PINCTRL_CONF_DESC(8, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), + PINCTRL_CONF_DESC(9, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), + PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(0)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(1)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(2)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(3)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(4)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(5)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(6)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(7)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(8)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(9)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(10)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(11)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(12)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(13)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(14)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(15)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(16)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(17)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(18)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(19)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(20)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(21)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(22)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(23)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(24)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(25)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(26)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(27)), + PINCTRL_CONF_DESC(40, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = { + PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), + PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), + PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), + PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), + PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK), + PINCTRL_CONF_DESC(8, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), + PINCTRL_CONF_DESC(9, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), + PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(0)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(1)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(2)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(3)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(4)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(5)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(6)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(7)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(8)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(9)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(10)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(11)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(12)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(13)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(14)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(15)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(16)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(17)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(18)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(19)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(20)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(21)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(22)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(23)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(24)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(25)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(26)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(27)), + PINCTRL_CONF_DESC(40, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = { + PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), + PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), + PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), + PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), + PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK), + PINCTRL_CONF_DESC(8, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), + PINCTRL_CONF_DESC(9, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), + PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(0)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(1)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(2)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(3)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(4)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(5)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(6)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(7)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(8)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(9)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(10)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(11)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(12)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(13)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(14)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(15)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(16)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(17)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(18)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(19)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(20)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(21)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(22)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(23)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(24)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(25)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(26)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(27)), + PINCTRL_CONF_DESC(40, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = { + PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), + PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), + PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), + PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), + PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK), + PINCTRL_CONF_DESC(8, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), + PINCTRL_CONF_DESC(9, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), + PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(0)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(1)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(2)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(3)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(4)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(5)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(6)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(7)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(8)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(9)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(10)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(11)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(12)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(13)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(14)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(15)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(16)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(17)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(18)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(19)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(20)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(21)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(22)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(23)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(24)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(25)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(26)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(27)), + PINCTRL_CONF_DESC(40, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), +}; + +static const struct airoha_pinctrl_match_data pinctrl_match_data = { + .pinctrl_name = KBUILD_MODNAME, + .pinctrl_owner = THIS_MODULE, + .pins = pinctrl_pins, + .num_pins = ARRAY_SIZE(pinctrl_pins), + .grps = pinctrl_groups, + .num_grps = ARRAY_SIZE(pinctrl_groups), + .funcs = pinctrl_funcs, + .num_funcs = ARRAY_SIZE(pinctrl_funcs), + .confs_info = { + [AIROHA_PINCTRL_CONFS_PULLUP] = { + .confs = pinctrl_pullup_conf, + .num_confs = ARRAY_SIZE(pinctrl_pullup_conf), + }, + [AIROHA_PINCTRL_CONFS_PULLDOWN] = { + .confs = pinctrl_pulldown_conf, + .num_confs = ARRAY_SIZE(pinctrl_pulldown_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E2] = { + .confs = pinctrl_drive_e2_conf, + .num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E4] = { + .confs = pinctrl_drive_e4_conf, + .num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf), + }, + }, +}; + +static const struct of_device_id airoha_pinctrl_of_match[] = { + { .compatible = "airoha,en7523-pinctrl", .data = &pinctrl_match_data }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match); + +static struct platform_driver airoha_pinctrl_driver = { + .probe = airoha_pinctrl_probe, + .driver = { + .name = "pinctrl-airoha-en7523", + .of_match_table = airoha_pinctrl_of_match, + }, +}; +module_platform_driver(airoha_pinctrl_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Lorenzo Bianconi "); +MODULE_AUTHOR("Benjamin Larsson "); +MODULE_AUTHOR("Markus Gothe "); +MODULE_AUTHOR("Matheus Sampaio Queiroga "); +MODULE_AUTHOR("Mikhail Kshevetskiy "); +MODULE_DESCRIPTION("Pinctrl driver for Airoha EN7523 SoC"); From 18c510bafad133684403414fcb248e21c65b42d6 Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:06:13 +0300 Subject: [PATCH 117/130] pinctrl: airoha: try to find chip scu node by phandle first The "airoha,en7581-chip-scu" is not a good compatible string in the en7523 case. Let's search chip scu regmap with "airoha,chip-scu" phangle first and fallback to SoC specific chip scu compatible string on failure. Signed-off-by: Mikhail Kshevetskiy Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/airoha-common.h | 1 + drivers/pinctrl/airoha/pinctrl-airoha.c | 9 ++++++--- drivers/pinctrl/airoha/pinctrl-an7581.c | 1 + drivers/pinctrl/airoha/pinctrl-an7583.c | 1 + drivers/pinctrl/airoha/pinctrl-en7523.c | 1 + 5 files changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoha/airoha-common.h index e6b60c8f9fa7..c1acbfb7426e 100644 --- a/drivers/pinctrl/airoha/airoha-common.h +++ b/drivers/pinctrl/airoha/airoha-common.h @@ -130,6 +130,7 @@ struct airoha_pinctrl { }; struct airoha_pinctrl_match_data { + const char *chip_scu_compatible; const char *pinctrl_name; struct module *pinctrl_owner; const struct pinctrl_pin_desc *pins; diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c index 7f6c6279f7f8..f505a3f69c5d 100644 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c @@ -791,9 +791,12 @@ int airoha_pinctrl_probe(struct platform_device *pdev) if (IS_ERR(pinctrl->regmap)) return PTR_ERR(pinctrl->regmap); - map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu"); - if (IS_ERR(map)) - return PTR_ERR(map); + map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "airoha,chip-scu"); + if (IS_ERR_OR_NULL(map)) { + map = syscon_regmap_lookup_by_compatible(data->chip_scu_compatible); + if (IS_ERR(map)) + return PTR_ERR(map); + } pinctrl->chip_scu = map; diff --git a/drivers/pinctrl/airoha/pinctrl-an7581.c b/drivers/pinctrl/airoha/pinctrl-an7581.c index cd2a78382bc6..2fcf88106e11 100644 --- a/drivers/pinctrl/airoha/pinctrl-an7581.c +++ b/drivers/pinctrl/airoha/pinctrl-an7581.c @@ -1432,6 +1432,7 @@ static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = { }; static const struct airoha_pinctrl_match_data pinctrl_match_data = { + .chip_scu_compatible = "airoha,en7581-chip-scu", .pinctrl_name = KBUILD_MODNAME, .pinctrl_owner = THIS_MODULE, .pins = pinctrl_pins, diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c index 031a8b36e002..2c3a75c35915 100644 --- a/drivers/pinctrl/airoha/pinctrl-an7583.c +++ b/drivers/pinctrl/airoha/pinctrl-an7583.c @@ -1462,6 +1462,7 @@ static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = { }; static const struct airoha_pinctrl_match_data pinctrl_match_data = { + .chip_scu_compatible = "airoha,en7581-chip-scu", .pinctrl_name = KBUILD_MODNAME, .pinctrl_owner = THIS_MODULE, .pins = pinctrl_pins, diff --git a/drivers/pinctrl/airoha/pinctrl-en7523.c b/drivers/pinctrl/airoha/pinctrl-en7523.c index 91490418e9ab..5aa39bacf460 100644 --- a/drivers/pinctrl/airoha/pinctrl-en7523.c +++ b/drivers/pinctrl/airoha/pinctrl-en7523.c @@ -1104,6 +1104,7 @@ static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = { }; static const struct airoha_pinctrl_match_data pinctrl_match_data = { + .chip_scu_compatible = "airoha,en7523-chip-scu", .pinctrl_name = KBUILD_MODNAME, .pinctrl_owner = THIS_MODULE, .pins = pinctrl_pins, From 59f044601839452570f1a315b15ad04757637469 Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:06:14 +0300 Subject: [PATCH 118/130] dt-bindings: pinctrl: airoha: add support of an7563 pin controller Introduce device tree binding schema for Airoha AN7563 SoC pin controller. Signed-off-by: Mikhail Kshevetskiy Signed-off-by: Linus Walleij --- .../pinctrl/airoha,an7563-pinctrl.yaml | 350 ++++++++++++++++++ 1 file changed, 350 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/airoha,an7563-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,an7563-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,an7563-pinctrl.yaml new file mode 100644 index 000000000000..6d186ebe4a41 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/airoha,an7563-pinctrl.yaml @@ -0,0 +1,350 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/airoha,an7563-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha AN7563 Pin Controller + +maintainers: + - Lorenzo Bianconi + +description: + The Airoha's AN7563 Pin controller is used to control SoC pins. + +properties: + compatible: + const: airoha,an7563-pinctrl + + interrupts: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - interrupts + - gpio-controller + - "#gpio-cells" + - interrupt-controller + - "#interrupt-cells" + +patternProperties: + '-pins$': + type: object + + patternProperties: + '^mux(-|$)': + type: object + + description: + pinmux configuration nodes. + + $ref: /schemas/pinctrl/pinmux-node.yaml + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [pon, sipo, mdio, uart, jtag, pcm, spi, pnand, gpio, + pcie_reset, pwm, phy1_led0, phy2_led0, phy3_led0, + phy4_led0, phy1_led1, phy2_led1, phy3_led1, phy4_led1] + + groups: + description: + An array of strings. Each string contains the name of a group. + + required: + - function + - groups + + allOf: + - if: + properties: + function: + const: pon + then: + properties: + groups: + enum: [pon] + - if: + properties: + function: + const: sipo + then: + properties: + groups: + enum: [sipo, sipo_rclk] + - if: + properties: + function: + const: mdio + then: + properties: + groups: + enum: [mdio] + - if: + properties: + function: + const: uart + then: + properties: + groups: + items: + enum: [hsuart, hsuart_cts_rts] + maxItems: 2 + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag_udi, jtag_dfd] + - if: + properties: + function: + const: pcm + then: + properties: + groups: + enum: [pcm1, pcm2] + - if: + properties: + function: + const: spi + then: + properties: + groups: + items: + enum: [spi_quad, spi_cs1] + maxItems: 2 + - if: + properties: + function: + const: pnand + then: + properties: + groups: + enum: [pnand] + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [gpio28, gpio29, gpio30, gpio31, gpio32, + gpio33, gpio34, gpio35, gpio36, gpio37] + - if: + properties: + function: + const: pcie_reset + then: + properties: + groups: + enum: [pcie_reset0, pcie_reset1] + - if: + properties: + function: + const: pwm + then: + properties: + groups: + enum: [gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, + gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, + gpio14, gpio15, gpio16, gpio17, gpio18, gpio19, + gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, + gpio26, gpio27, gpio28, gpio29, gpio30, gpio31, + gpio36, gpio37] + - if: + properties: + function: + const: phy1_led0 + then: + properties: + groups: + enum: [gpio8, gpio9, gpio10, gpio11] + - if: + properties: + function: + const: phy2_led0 + then: + properties: + groups: + enum: [gpio8, gpio9, gpio10, gpio11] + - if: + properties: + function: + const: phy3_led0 + then: + properties: + groups: + enum: [gpio8, gpio9, gpio10, gpio11] + - if: + properties: + function: + const: phy4_led0 + then: + properties: + groups: + enum: [gpio8, gpio9, gpio10, gpio11] + - if: + properties: + function: + const: phy1_led1 + then: + properties: + groups: + enum: [gpio4, gpio5, gpio6, gpio7] + - if: + properties: + function: + const: phy2_led1 + then: + properties: + groups: + enum: [gpio4, gpio5, gpio6, gpio7] + - if: + properties: + function: + const: phy3_led1 + then: + properties: + groups: + enum: [gpio4, gpio5, gpio6, gpio7] + - if: + properties: + function: + const: phy4_led1 + then: + properties: + groups: + enum: [gpio4, gpio5, gpio6, gpio7] + + additionalProperties: false + + '^conf(-|$)': + type: object + + description: + pinconf configuration nodes. + + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pins: + description: + An array of strings. Each string contains the name of a pin. + items: + enum: [gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, + gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio14, + gpio15, gpio16, gpio17, gpio18, gpio19, gpio20, gpio21, + gpio22, gpio23, gpio24, gpio25, gpio26, gpio27, + pcie_reset0, pcie_reset1, i2c_scl, i2c_sda, spi_clk, + spi_cs, spi_mosi, spi_miso, uart_txd, uart_rxd] + minItems: 1 + maxItems: 38 + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + input-enable: true + + output-enable: true + + output-low: true + + output-high: true + + drive-open-drain: true + + drive-strength: + description: + Selects the drive strength for MIO pins, in mA. + enum: [2, 4, 6, 8] + + required: + - pins + + additionalProperties: false + + additionalProperties: false + +additionalProperties: false + +examples: + - | + #include + + pinctrl { + compatible = "airoha,an7563-pinctrl"; + + interrupt-parent = <&gic>; + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + gpio-ranges = <&pinctrl 0 0 38>; + + pcie1-rst-pins { + conf { + pins = "pcie_reset1"; + drive-open-drain = <1>; + }; + }; + + pwm-pins { + mux { + function = "pwm"; + groups = "gpio18"; + }; + }; + + spi-pins { + mux { + function = "spi"; + groups = "spi_quad", "spi_cs1"; + }; + }; + + hsuart-pins { + mux { + function = "uart"; + groups = "hsuart", "hsuart_cts_rts"; + }; + }; + + mdio-pins { + mux { + function = "mdio"; + groups = "mdio"; + }; + + conf { + pins = "gpio2"; + output-enable; + }; + }; + }; From 87b42c8b216923b813bd7d43624c340d74be4099 Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Fri, 7 Aug 2026 01:06:15 +0300 Subject: [PATCH 119/130] pinctrl: airoha: add support of an7563 SoC This patch adds support of Airoha an7563 SoC pin controller. Signed-off-by: Mikhail Kshevetskiy Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/Kconfig | 9 + drivers/pinctrl/airoha/Makefile | 1 + drivers/pinctrl/airoha/pinctrl-an7563.c | 1115 +++++++++++++++++++++++ 3 files changed, 1125 insertions(+) create mode 100644 drivers/pinctrl/airoha/pinctrl-an7563.c diff --git a/drivers/pinctrl/airoha/Kconfig b/drivers/pinctrl/airoha/Kconfig index 363d6b7ff906..22b8f850cee1 100644 --- a/drivers/pinctrl/airoha/Kconfig +++ b/drivers/pinctrl/airoha/Kconfig @@ -13,6 +13,7 @@ config PINCTRL_AIROHA select GPIOLIB select GPIOLIB_IRQCHIP select REGMAP_MMIO + imply PINCTRL_AIROHA_AN7563 imply PINCTRL_AIROHA_AN7581 imply PINCTRL_AIROHA_AN7583 imply PINCTRL_AIROHA_EN7523 @@ -20,6 +21,14 @@ config PINCTRL_AIROHA Shared pin controller and gpio driver code for different Airoha SoCs. +config PINCTRL_AIROHA_AN7563 + tristate "AN7563 pinctrl" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_AIROHA + help + Say yes here to support pin controller and gpio driver + on Airoha AN7563 and other compatible SoCs. + config PINCTRL_AIROHA_AN7581 tristate "AN7581 pinctrl" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/airoha/Makefile b/drivers/pinctrl/airoha/Makefile index 8b9202321ba8..30e4bee57a4a 100644 --- a/drivers/pinctrl/airoha/Makefile +++ b/drivers/pinctrl/airoha/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_AIROHA) += pinctrl-airoha.o # SoC drivers +obj-$(CONFIG_PINCTRL_AIROHA_AN7563) += pinctrl-an7563.o obj-$(CONFIG_PINCTRL_AIROHA_AN7581) += pinctrl-an7581.o obj-$(CONFIG_PINCTRL_AIROHA_AN7583) += pinctrl-an7583.o obj-$(CONFIG_PINCTRL_AIROHA_EN7523) += pinctrl-en7523.o diff --git a/drivers/pinctrl/airoha/pinctrl-an7563.c b/drivers/pinctrl/airoha/pinctrl-an7563.c new file mode 100644 index 000000000000..40cbbe90cc46 --- /dev/null +++ b/drivers/pinctrl/airoha/pinctrl-an7563.c @@ -0,0 +1,1115 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * AN7563 SoC pinctrl data for the Airoha pinctrl driver (pinctrl-airoha.c). + * + * Sources: AN7563 Programming Guide chapter 2 (CHIP SCU, base 0x1fa20000), + * chapter 17 (GPIO controller, base 0x1fbf0200) and AN7563PT datasheet + * chapter 4.3 (pin sharing scheme). + * + * Pin numbering follows the GPIO line numbering of the SoC: + * pins 0-27 -> GPIO0-GPIO27 (dedicated GPIO pads) + * pins 28/29 -> PCIE_RESET0/PCIE_RESET1 pads (GPIO28/GPIO29) + * pins 30/31 -> I2C_SCL/I2C_SDA pads (GPIO30/GPIO31) + * pins 32-35 -> SPI_CLK/SPI_CS/SPI_MOSI/SPI_MISO pads (GPIO32-GPIO35) + * pins 36/37 -> UART_TXD/UART_RXD pads (GPIO36/GPIO37) + * + * Definitions marked "shared" are identical to the ones already present in + * pinctrl-airoha.c (EN7581/AN7583) and must be dropped when this data is + * merged there. + */ + +#include "airoha-common.h" + +/* + * shared - named RG_SW_TOD_1PPS_MODE on AN7563. Only the LAN LED mode + * bits and GSW_TOD_1PPS exist on AN7563 (no 2nd I2C, I2S or PON 1PPS). + */ +#define REG_GPIO_2ND_I2C_MODE 0x0214 +#define GPIO_LAN3_LED1_MODE_MASK BIT(10) +#define GPIO_LAN3_LED0_MODE_MASK BIT(9) +#define GPIO_LAN2_LED1_MODE_MASK BIT(8) +#define GPIO_LAN2_LED0_MODE_MASK BIT(7) +#define GPIO_LAN1_LED1_MODE_MASK BIT(6) +#define GPIO_LAN1_LED0_MODE_MASK BIT(5) +#define GPIO_LAN0_LED1_MODE_MASK BIT(4) +#define GPIO_LAN0_LED0_MODE_MASK BIT(3) +#define GSW_TOD_1PPS_MODE_MASK BIT(1) + +/* shared */ +#define REG_GPIO_SPI_CS1_MODE 0x0218 +#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21) +#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20) +#define GPIO_PCM_SPI_CS2_MODE_MASK BIT(18) +#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17) +#define GPIO_PCM_SPI_MODE_MASK BIT(16) +#define GPIO_PCM2_MODE_MASK BIT(13) +#define GPIO_PCM1_MODE_MASK BIT(12) +#define GPIO_PCM_INT_MODE_MASK BIT(9) +#define GPIO_PCM_RESET_MODE_MASK BIT(8) +#define GPIO_SPI_QUAD_MODE_MASK BIT(4) +#define GPIO_SPI_CS4_MODE_MASK BIT(3) +#define GPIO_SPI_CS3_MODE_MASK BIT(2) +#define GPIO_SPI_CS2_MODE_MASK BIT(1) +#define GPIO_SPI_CS1_MODE_MASK BIT(0) + +#define REG_GPIO_PON_MODE 0x021c +/* + * AN7563 specific: route the standalone pads to their GPIO function. + * 0: pad keeps its base function, 1: pad is GPIO. + */ +#define UART_RXD_GPIO_MODE_MASK BIT(22) /* GPIO37 */ +#define UART_TXD_GPIO_MODE_MASK BIT(21) /* GPIO36 */ +#define SPI_MISO_GPIO_MODE_MASK BIT(20) /* GPIO35 */ +#define SPI_MOSI_GPIO_MODE_MASK BIT(19) /* GPIO34 */ +#define SPI_CS_GPIO_MODE_MASK BIT(18) /* GPIO33 */ +#define SPI_CLK_GPIO_MODE_MASK BIT(17) /* GPIO32 */ +#define I2C_SDA_GPIO_MODE_MASK BIT(16) /* GPIO31 */ +#define I2C_SCL_GPIO_MODE_MASK BIT(15) /* GPIO30 */ +/* shared */ +#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14) +#define GPIO_SGMII_MDIO_MODE_MASK BIT(13) +#define SIPO_RCLK_MODE_MASK BIT(11) +/* + * Note: on AN7563 GPIO_PCIE_RESET{0,1} select the GPIO function of the + * PCIE_RESET pads (0: PCIe reset, 1: GPIO28/GPIO29). + */ +#define GPIO_PCIE_RESET1_MASK BIT(10) /* GPIO29 */ +#define GPIO_PCIE_RESET0_MASK BIT(9) /* GPIO28 */ +#define GPIO_HSUART_CTS_RTS_MODE_MASK BIT(6) +#define GPIO_HSUART_MODE_MASK BIT(5) +#define GPIO_SIPO_MODE_MASK BIT(2) +#define GPIO_PON_MODE_MASK BIT(0) + +/* shared */ +#define REG_NPU_UART_EN 0x0224 +#define JTAG_UDI_EN_MASK BIT(4) +#define JTAG_DFD_EN_MASK BIT(3) + +/* LED MAP - shared */ +#define REG_LAN_LED0_MAPPING 0x027c +#define REG_LAN_LED1_MAPPING 0x0280 + +#define LAN3_LED_MAPPING_MASK GENMASK(14, 12) +#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n)) + +#define LAN2_LED_MAPPING_MASK GENMASK(10, 8) +#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n)) + +#define LAN1_LED_MAPPING_MASK GENMASK(6, 4) +#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n)) + +#define LAN0_LED_MAPPING_MASK GENMASK(2, 0) +#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n)) + +/* + * CONF - shared. + * The AN7563 standalone IO conf registers use the same bit layout as + * EN7581 (UART1_TXD/RXD are named UART_TXD/RXD on AN7563). + */ +#define REG_I2C_SDA_E2 0x001c +#define SPI_MISO_E2_MASK BIT(14) +#define SPI_MOSI_E2_MASK BIT(13) +#define SPI_CLK_E2_MASK BIT(12) +#define SPI_CS0_E2_MASK BIT(11) +#define PCIE1_RESET_E2_MASK BIT(9) +#define PCIE0_RESET_E2_MASK BIT(8) +#define UART1_RXD_E2_MASK BIT(3) +#define UART1_TXD_E2_MASK BIT(2) +#define I2C_SCL_E2_MASK BIT(1) +#define I2C_SDA_E2_MASK BIT(0) + +#define REG_I2C_SDA_E4 0x0020 +#define SPI_MISO_E4_MASK BIT(14) +#define SPI_MOSI_E4_MASK BIT(13) +#define SPI_CLK_E4_MASK BIT(12) +#define SPI_CS0_E4_MASK BIT(11) +#define PCIE1_RESET_E4_MASK BIT(9) +#define PCIE0_RESET_E4_MASK BIT(8) +#define UART1_RXD_E4_MASK BIT(3) +#define UART1_TXD_E4_MASK BIT(2) +#define I2C_SCL_E4_MASK BIT(1) +#define I2C_SDA_E4_MASK BIT(0) + +#define REG_GPIO_L_E2 0x0024 +#define REG_GPIO_L_E4 0x0028 + +#define REG_I2C_SDA_PU 0x0044 +#define SPI_MISO_PU_MASK BIT(14) +#define SPI_MOSI_PU_MASK BIT(13) +#define SPI_CLK_PU_MASK BIT(12) +#define SPI_CS0_PU_MASK BIT(11) +#define PCIE1_RESET_PU_MASK BIT(9) +#define PCIE0_RESET_PU_MASK BIT(8) +#define UART1_RXD_PU_MASK BIT(3) +#define UART1_TXD_PU_MASK BIT(2) +#define I2C_SCL_PU_MASK BIT(1) +#define I2C_SDA_PU_MASK BIT(0) + +#define REG_I2C_SDA_PD 0x0048 +#define SPI_MISO_PD_MASK BIT(14) +#define SPI_MOSI_PD_MASK BIT(13) +#define SPI_CLK_PD_MASK BIT(12) +#define SPI_CS0_PD_MASK BIT(11) +#define PCIE1_RESET_PD_MASK BIT(9) +#define PCIE0_RESET_PD_MASK BIT(8) +#define UART1_RXD_PD_MASK BIT(3) +#define UART1_TXD_PD_MASK BIT(2) +#define I2C_SCL_PD_MASK BIT(1) +#define I2C_SDA_PD_MASK BIT(0) + +#define REG_GPIO_L_PU 0x004c +#define REG_GPIO_L_PD 0x0050 + +#define REG_PCIE_RESET_OD 0x018c +#define PCIE1_RESET_OD_MASK BIT(1) +#define PCIE0_RESET_OD_MASK BIT(0) + +/* + * PWM MODE CONF - shared. + * The AN7563 GPIO flash mode registers use the same layout as EN7581: + * REG_GPIO_FLASH_MODE_CFG covers GPIO0-15, REG_GPIO_FLASH_MODE_CFG_EXT + * covers GPIO16-31 (bits 0-15) and GPIO36+ (bits 16+). The SPI pads + * (GPIO32-35) have no flash mode configuration bit. + */ +#define REG_GPIO_FLASH_MODE_CFG 0x0034 +#define GPIO15_FLASH_MODE_CFG BIT(15) +#define GPIO14_FLASH_MODE_CFG BIT(14) +#define GPIO13_FLASH_MODE_CFG BIT(13) +#define GPIO12_FLASH_MODE_CFG BIT(12) +#define GPIO11_FLASH_MODE_CFG BIT(11) +#define GPIO10_FLASH_MODE_CFG BIT(10) +#define GPIO9_FLASH_MODE_CFG BIT(9) +#define GPIO8_FLASH_MODE_CFG BIT(8) +#define GPIO7_FLASH_MODE_CFG BIT(7) +#define GPIO6_FLASH_MODE_CFG BIT(6) +#define GPIO5_FLASH_MODE_CFG BIT(5) +#define GPIO4_FLASH_MODE_CFG BIT(4) +#define GPIO3_FLASH_MODE_CFG BIT(3) +#define GPIO2_FLASH_MODE_CFG BIT(2) +#define GPIO1_FLASH_MODE_CFG BIT(1) +#define GPIO0_FLASH_MODE_CFG BIT(0) + +#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068 +#define GPIO37_FLASH_MODE_CFG BIT(17) +#define GPIO36_FLASH_MODE_CFG BIT(16) +#define GPIO31_FLASH_MODE_CFG BIT(15) +#define GPIO30_FLASH_MODE_CFG BIT(14) +#define GPIO29_FLASH_MODE_CFG BIT(13) +#define GPIO28_FLASH_MODE_CFG BIT(12) +#define GPIO27_FLASH_MODE_CFG BIT(11) +#define GPIO26_FLASH_MODE_CFG BIT(10) +#define GPIO25_FLASH_MODE_CFG BIT(9) +#define GPIO24_FLASH_MODE_CFG BIT(8) +#define GPIO23_FLASH_MODE_CFG BIT(7) +#define GPIO22_FLASH_MODE_CFG BIT(6) +#define GPIO21_FLASH_MODE_CFG BIT(5) +#define GPIO20_FLASH_MODE_CFG BIT(4) +#define GPIO19_FLASH_MODE_CFG BIT(3) +#define GPIO18_FLASH_MODE_CFG BIT(2) +#define GPIO17_FLASH_MODE_CFG BIT(1) +#define GPIO16_FLASH_MODE_CFG BIT(0) + +#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + 0 \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (smux_val), \ + (smux_val) \ + }, \ + .regmap_size = 2, \ + } + +/* PWM */ +#define AIROHA_PINCTRL_PWM(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_MUX, \ + REG_GPIO_FLASH_MODE_CFG, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (smux_val), \ + (smux_val) \ + }, \ + .regmap_size = 2, \ + } + +#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_2ND_I2C_MODE, \ + (mux_val), \ + (mux_val), \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_LAN_LED0_MAPPING, \ + (map_mask), \ + (map_val), \ + }, \ + .regmap_size = 2, \ + } + +#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_2ND_I2C_MODE, \ + (mux_val), \ + (mux_val), \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_LAN_LED1_MAPPING, \ + (map_mask), \ + (map_val), \ + }, \ + .regmap_size = 2, \ + } + +static const struct pinctrl_pin_desc pinctrl_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), + PINCTRL_PIN(19, "gpio19"), + PINCTRL_PIN(20, "gpio20"), + PINCTRL_PIN(21, "gpio21"), + PINCTRL_PIN(22, "gpio22"), + PINCTRL_PIN(23, "gpio23"), + PINCTRL_PIN(24, "gpio24"), + PINCTRL_PIN(25, "gpio25"), + PINCTRL_PIN(26, "gpio26"), + PINCTRL_PIN(27, "gpio27"), + PINCTRL_PIN(28, "pcie_reset0"), /* GPIO28 */ + PINCTRL_PIN(29, "pcie_reset1"), /* GPIO29 */ + PINCTRL_PIN(30, "i2c_scl"), /* GPIO30 */ + PINCTRL_PIN(31, "i2c_sda"), /* GPIO31 */ + PINCTRL_PIN(32, "spi_clk"), /* GPIO32 */ + PINCTRL_PIN(33, "spi_cs"), /* GPIO33 */ + PINCTRL_PIN(34, "spi_mosi"), /* GPIO34 */ + PINCTRL_PIN(35, "spi_miso"), /* GPIO35 */ + PINCTRL_PIN(36, "uart_txd"), /* GPIO36 */ + PINCTRL_PIN(37, "uart_rxd"), /* GPIO37 */ +}; + +static const int pon_pins[] = { 14, 15, 16, 17, 18, 19 }; +static const int sipo_pins[] = { 20, 21 }; +static const int sipo_rclk_pins[] = { 20, 21, 26 }; +static const int mdio_pins[] = { 30, 31 }; +static const int hsuart_pins[] = { 16, 17 }; +static const int hsuart_cts_rts_pins[] = { 14, 15 }; +static const int i2c_pins[] = { 30, 31 }; +static const int jtag_udi_pins[] = { 7, 8, 9, 10, 11 }; +static const int jtag_dfd_pins[] = { 7, 8, 9, 10, 11 }; +static const int pcm1_pins[] = { 22, 23, 24, 25 }; +static const int pcm2_pins[] = { 1, 2, 3, 4 }; +static const int spi_pins[] = { 32, 33, 34, 35 }; +static const int spi_quad_pins[] = { 2, 3 }; +static const int spi_cs1_pins[] = { 4 }; +static const int pnand_pins[] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 32, 33, 34, 35 +}; +static const int gpio0_pins[] = { 0 }; +static const int gpio1_pins[] = { 1 }; +static const int gpio2_pins[] = { 2 }; +static const int gpio3_pins[] = { 3 }; +static const int gpio4_pins[] = { 4 }; +static const int gpio5_pins[] = { 5 }; +static const int gpio6_pins[] = { 6 }; +static const int gpio7_pins[] = { 7 }; +static const int gpio8_pins[] = { 8 }; +static const int gpio9_pins[] = { 9 }; +static const int gpio10_pins[] = { 10 }; +static const int gpio11_pins[] = { 11 }; +static const int gpio12_pins[] = { 12 }; +static const int gpio13_pins[] = { 13 }; +static const int gpio14_pins[] = { 14 }; +static const int gpio15_pins[] = { 15 }; +static const int gpio16_pins[] = { 16 }; +static const int gpio17_pins[] = { 17 }; +static const int gpio18_pins[] = { 18 }; +static const int gpio19_pins[] = { 19 }; +static const int gpio20_pins[] = { 20 }; +static const int gpio21_pins[] = { 21 }; +static const int gpio22_pins[] = { 22 }; +static const int gpio23_pins[] = { 23 }; +static const int gpio24_pins[] = { 24 }; +static const int gpio25_pins[] = { 25 }; +static const int gpio26_pins[] = { 26 }; +static const int gpio27_pins[] = { 27 }; +static const int gpio28_pins[] = { 28 }; +static const int gpio29_pins[] = { 29 }; +static const int gpio30_pins[] = { 30 }; +static const int gpio31_pins[] = { 31 }; +static const int gpio32_pins[] = { 32 }; +static const int gpio33_pins[] = { 33 }; +static const int gpio34_pins[] = { 34 }; +static const int gpio35_pins[] = { 35 }; +static const int gpio36_pins[] = { 36 }; +static const int gpio37_pins[] = { 37 }; +static const int pcie_reset0_pins[] = { 28 }; +static const int pcie_reset1_pins[] = { 29 }; + +static const struct pingroup pinctrl_groups[] = { + PINCTRL_PIN_GROUP("pon", pon), + PINCTRL_PIN_GROUP("sipo", sipo), + PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk), + PINCTRL_PIN_GROUP("mdio", mdio), + PINCTRL_PIN_GROUP("hsuart", hsuart), + PINCTRL_PIN_GROUP("hsuart_cts_rts", hsuart_cts_rts), + PINCTRL_PIN_GROUP("i2c", i2c), + PINCTRL_PIN_GROUP("jtag_udi", jtag_udi), + PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd), + PINCTRL_PIN_GROUP("pcm1", pcm1), + PINCTRL_PIN_GROUP("pcm2", pcm2), + PINCTRL_PIN_GROUP("spi", spi), + PINCTRL_PIN_GROUP("spi_quad", spi_quad), + PINCTRL_PIN_GROUP("spi_cs1", spi_cs1), + PINCTRL_PIN_GROUP("pnand", pnand), + PINCTRL_PIN_GROUP("gpio0", gpio0), + PINCTRL_PIN_GROUP("gpio1", gpio1), + PINCTRL_PIN_GROUP("gpio2", gpio2), + PINCTRL_PIN_GROUP("gpio3", gpio3), + PINCTRL_PIN_GROUP("gpio4", gpio4), + PINCTRL_PIN_GROUP("gpio5", gpio5), + PINCTRL_PIN_GROUP("gpio6", gpio6), + PINCTRL_PIN_GROUP("gpio7", gpio7), + PINCTRL_PIN_GROUP("gpio8", gpio8), + PINCTRL_PIN_GROUP("gpio9", gpio9), + PINCTRL_PIN_GROUP("gpio10", gpio10), + PINCTRL_PIN_GROUP("gpio11", gpio11), + PINCTRL_PIN_GROUP("gpio12", gpio12), + PINCTRL_PIN_GROUP("gpio13", gpio13), + PINCTRL_PIN_GROUP("gpio14", gpio14), + PINCTRL_PIN_GROUP("gpio15", gpio15), + PINCTRL_PIN_GROUP("gpio16", gpio16), + PINCTRL_PIN_GROUP("gpio17", gpio17), + PINCTRL_PIN_GROUP("gpio18", gpio18), + PINCTRL_PIN_GROUP("gpio19", gpio19), + PINCTRL_PIN_GROUP("gpio20", gpio20), + PINCTRL_PIN_GROUP("gpio21", gpio21), + PINCTRL_PIN_GROUP("gpio22", gpio22), + PINCTRL_PIN_GROUP("gpio23", gpio23), + PINCTRL_PIN_GROUP("gpio24", gpio24), + PINCTRL_PIN_GROUP("gpio25", gpio25), + PINCTRL_PIN_GROUP("gpio26", gpio26), + PINCTRL_PIN_GROUP("gpio27", gpio27), + PINCTRL_PIN_GROUP("gpio28", gpio28), + PINCTRL_PIN_GROUP("gpio29", gpio29), + PINCTRL_PIN_GROUP("gpio30", gpio30), + PINCTRL_PIN_GROUP("gpio31", gpio31), + PINCTRL_PIN_GROUP("gpio32", gpio32), + PINCTRL_PIN_GROUP("gpio33", gpio33), + PINCTRL_PIN_GROUP("gpio34", gpio34), + PINCTRL_PIN_GROUP("gpio35", gpio35), + PINCTRL_PIN_GROUP("gpio36", gpio36), + PINCTRL_PIN_GROUP("gpio37", gpio37), + PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0), + PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1), +}; + +/* shared */ +static const char *const pon_groups[] = { "pon" }; +static const char *const sipo_groups[] = { "sipo", "sipo_rclk" }; +static const char *const mdio_groups[] = { "mdio" }; +static const char *const uart_groups[] = { + "hsuart", "hsuart_cts_rts" +}; +static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" }; +static const char *const pcm_groups[] = { "pcm1", "pcm2" }; +static const char *const spi_groups[] = { "spi_quad", "spi_cs1" }; +static const char *const pnand_groups[] = { "pnand" }; +static const char *const gpio_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", + "gpio33", "gpio34", "gpio35", "gpio36", "gpio37" +}; +static const char *const pcie_reset_groups[] = { + "pcie_reset0", "pcie_reset1" +}; +static const char *const pwm_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio36", "gpio37" +}; +static const char *const phy1_led0_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; +static const char *const phy2_led0_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; +static const char *const phy3_led0_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; +static const char *const phy4_led0_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; +static const char *const phy1_led1_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; +static const char *const phy2_led1_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; +static const char *const phy3_led1_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; +static const char *const phy4_led1_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; + +/* shared */ +static const struct airoha_pinctrl_func_group pon_func_group[] = { + { + .name = "pon", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PON_MODE_MASK, + GPIO_PON_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +/* shared */ +static const struct airoha_pinctrl_func_group sipo_func_group[] = { + { + .name = "sipo", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "sipo_rclk", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +/* + * On AN7563 the SMI master (MDC/MDIO) is shared with the I2C_SCL/I2C_SDA + * pads and selected via the SGMII MDIO mode bit. I2C is the default pad + * function (no mux bit). + */ +static const struct airoha_pinctrl_func_group mdio_func_group[] = { + { + .name = "mdio", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SGMII_MDIO_MODE_MASK, + GPIO_SGMII_MDIO_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group uart_func_group[] = { + { + .name = "hsuart", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, + GPIO_HSUART_MODE_MASK + }, + .regmap_size = 1, + }, + { + .name = "hsuart_cts_rts", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +/* shared */ +static const struct airoha_pinctrl_func_group jtag_func_group[] = { + { + .name = "jtag_udi", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + JTAG_UDI_EN_MASK, + JTAG_UDI_EN_MASK + }, + .regmap_size = 1, + }, { + .name = "jtag_dfd", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + JTAG_DFD_EN_MASK, + JTAG_DFD_EN_MASK + }, + .regmap_size = 1, + }, +}; + +/* shared */ +static const struct airoha_pinctrl_func_group pcm_func_group[] = { + { + .name = "pcm1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM1_MODE_MASK, + GPIO_PCM1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM2_MODE_MASK, + GPIO_PCM2_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +/* shared */ +static const struct airoha_pinctrl_func_group spi_func_group[] = { + { + .name = "spi_quad", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_QUAD_MODE_MASK, + GPIO_SPI_QUAD_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS1_MODE_MASK, + GPIO_SPI_CS1_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +/* shared */ +static const struct airoha_pinctrl_func_group pnand_func_group[] = { + { + .name = "pnand", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PARALLEL_NAND_MODE_MASK, + GPIO_PARALLEL_NAND_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group gpio_func_group[] = { + AIROHA_PINCTRL_GPIO_EXT("gpio28", GPIO28_FLASH_MODE_CFG, + GPIO_PCIE_RESET0_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio29", GPIO29_FLASH_MODE_CFG, + GPIO_PCIE_RESET1_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio30", GPIO30_FLASH_MODE_CFG, + I2C_SCL_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio31", GPIO31_FLASH_MODE_CFG, + I2C_SDA_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO("gpio32", SPI_CLK_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO("gpio33", SPI_CS_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO("gpio34", SPI_MOSI_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO("gpio35", SPI_MISO_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio36", GPIO36_FLASH_MODE_CFG, + UART_TXD_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio37", GPIO37_FLASH_MODE_CFG, + UART_RXD_GPIO_MODE_MASK), +}; + +/* + * On AN7563 a set GPIO_PCIE_RESET{0,1} bit routes the pad to its GPIO + * function, so the PCIe reset function must clear it. + */ +static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = { + { + .name = "pcie_reset0", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET0_MASK, + 0 + }, + .regmap_size = 1, + }, { + .name = "pcie_reset1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET1_MASK, + 0 + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pwm_func_group[] = { + AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio28", GPIO28_FLASH_MODE_CFG, + GPIO_PCIE_RESET0_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio29", GPIO29_FLASH_MODE_CFG, + GPIO_PCIE_RESET1_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio30", GPIO30_FLASH_MODE_CFG, + I2C_SCL_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio31", GPIO31_FLASH_MODE_CFG, + I2C_SDA_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio36", GPIO36_FLASH_MODE_CFG, + UART_TXD_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio37", GPIO37_FLASH_MODE_CFG, + UART_RXD_GPIO_MODE_MASK), +}; + +/* + * LED pad mapping (datasheet table 4-9): + * GPIO8: LAN0_LED0, GPIO9: LAN1_LED0, GPIO10: LAN2_LED0, GPIO11: LAN3_LED0 + * GPIO7: LAN0_LED1, GPIO6: LAN1_LED1, GPIO5: LAN2_LED1, GPIO4: LAN3_LED1 + */ +static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio8", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio9", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio10", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio11", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio8", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio9", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio10", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio11", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio8", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio9", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio10", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio11", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio8", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio9", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio10", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio11", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), +}; + +static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), +}; + +static const struct airoha_pinctrl_func pinctrl_funcs[] = { + PINCTRL_FUNC_DESC("pon", pon), + PINCTRL_FUNC_DESC("sipo", sipo), + PINCTRL_FUNC_DESC("mdio", mdio), + PINCTRL_FUNC_DESC("uart", uart), + PINCTRL_FUNC_DESC("jtag", jtag), + PINCTRL_FUNC_DESC("pcm", pcm), + PINCTRL_FUNC_DESC("spi", spi), + PINCTRL_FUNC_DESC("pnand", pnand), + PINCTRL_FUNC_DESC("gpio", gpio), + PINCTRL_FUNC_DESC("pcie_reset", pcie_reset), + PINCTRL_FUNC_DESC("pwm", pwm), + PINCTRL_FUNC_DESC("phy1_led0", phy1_led0), + PINCTRL_FUNC_DESC("phy2_led0", phy2_led0), + PINCTRL_FUNC_DESC("phy3_led0", phy3_led0), + PINCTRL_FUNC_DESC("phy4_led0", phy4_led0), + PINCTRL_FUNC_DESC("phy1_led1", phy1_led1), + PINCTRL_FUNC_DESC("phy2_led1", phy2_led1), + PINCTRL_FUNC_DESC("phy3_led1", phy3_led1), + PINCTRL_FUNC_DESC("phy4_led1", phy4_led1), +}; + +static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = { + PINCTRL_CONF_DESC(0, REG_GPIO_L_PU, BIT(0)), + PINCTRL_CONF_DESC(1, REG_GPIO_L_PU, BIT(1)), + PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(2)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(3)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(4)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(5)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(6)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(7)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(8)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(9)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(10)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(11)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(12)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(13)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(14)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(15)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(16)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(17)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(18)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(19)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(20)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(21)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(22)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(23)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(24)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(25)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(26)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(27)), + PINCTRL_CONF_DESC(28, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), + PINCTRL_CONF_DESC(29, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), + PINCTRL_CONF_DESC(30, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), + PINCTRL_CONF_DESC(31, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), + PINCTRL_CONF_DESC(32, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), + PINCTRL_CONF_DESC(33, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), + PINCTRL_CONF_DESC(34, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), + PINCTRL_CONF_DESC(35, REG_I2C_SDA_PU, SPI_MISO_PU_MASK), + PINCTRL_CONF_DESC(36, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), + PINCTRL_CONF_DESC(37, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = { + PINCTRL_CONF_DESC(0, REG_GPIO_L_PD, BIT(0)), + PINCTRL_CONF_DESC(1, REG_GPIO_L_PD, BIT(1)), + PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(2)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(3)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(4)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(5)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(6)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(7)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(8)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(9)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(10)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(11)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(12)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(13)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(14)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(15)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(16)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(17)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(18)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(19)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(20)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(21)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(22)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(23)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(24)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(25)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(26)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(27)), + PINCTRL_CONF_DESC(28, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), + PINCTRL_CONF_DESC(29, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), + PINCTRL_CONF_DESC(30, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), + PINCTRL_CONF_DESC(31, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), + PINCTRL_CONF_DESC(32, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), + PINCTRL_CONF_DESC(33, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), + PINCTRL_CONF_DESC(34, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), + PINCTRL_CONF_DESC(35, REG_I2C_SDA_PD, SPI_MISO_PD_MASK), + PINCTRL_CONF_DESC(36, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), + PINCTRL_CONF_DESC(37, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = { + PINCTRL_CONF_DESC(0, REG_GPIO_L_E2, BIT(0)), + PINCTRL_CONF_DESC(1, REG_GPIO_L_E2, BIT(1)), + PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(2)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(3)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(4)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(5)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(6)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(7)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(8)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(9)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(10)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(11)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(12)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(13)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(14)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(15)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(16)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(17)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(18)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(19)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(20)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(21)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(22)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(23)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(24)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(25)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(26)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(27)), + PINCTRL_CONF_DESC(28, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), + PINCTRL_CONF_DESC(29, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), + PINCTRL_CONF_DESC(30, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), + PINCTRL_CONF_DESC(31, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), + PINCTRL_CONF_DESC(32, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), + PINCTRL_CONF_DESC(33, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), + PINCTRL_CONF_DESC(34, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), + PINCTRL_CONF_DESC(35, REG_I2C_SDA_E2, SPI_MISO_E2_MASK), + PINCTRL_CONF_DESC(36, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), + PINCTRL_CONF_DESC(37, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = { + PINCTRL_CONF_DESC(0, REG_GPIO_L_E4, BIT(0)), + PINCTRL_CONF_DESC(1, REG_GPIO_L_E4, BIT(1)), + PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(2)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(3)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(4)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(5)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(6)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(7)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(8)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(9)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(10)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(11)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(12)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(13)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(14)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(15)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(16)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(17)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(18)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(19)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(20)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(21)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(22)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(23)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(24)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(25)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(26)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(27)), + PINCTRL_CONF_DESC(28, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), + PINCTRL_CONF_DESC(29, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), + PINCTRL_CONF_DESC(30, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), + PINCTRL_CONF_DESC(31, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), + PINCTRL_CONF_DESC(32, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), + PINCTRL_CONF_DESC(33, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), + PINCTRL_CONF_DESC(34, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), + PINCTRL_CONF_DESC(35, REG_I2C_SDA_E4, SPI_MISO_E4_MASK), + PINCTRL_CONF_DESC(36, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), + PINCTRL_CONF_DESC(37, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = { + PINCTRL_CONF_DESC(28, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), + PINCTRL_CONF_DESC(29, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), +}; + +static const struct airoha_pinctrl_match_data pinctrl_match_data = { + .chip_scu_compatible = "airoha,en7581-chip-scu", + .pinctrl_name = KBUILD_MODNAME, + .pinctrl_owner = THIS_MODULE, + .pins = pinctrl_pins, + .num_pins = ARRAY_SIZE(pinctrl_pins), + .grps = pinctrl_groups, + .num_grps = ARRAY_SIZE(pinctrl_groups), + .funcs = pinctrl_funcs, + .num_funcs = ARRAY_SIZE(pinctrl_funcs), + .confs_info = { + [AIROHA_PINCTRL_CONFS_PULLUP] = { + .confs = pinctrl_pullup_conf, + .num_confs = ARRAY_SIZE(pinctrl_pullup_conf), + }, + [AIROHA_PINCTRL_CONFS_PULLDOWN] = { + .confs = pinctrl_pulldown_conf, + .num_confs = ARRAY_SIZE(pinctrl_pulldown_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E2] = { + .confs = pinctrl_drive_e2_conf, + .num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E4] = { + .confs = pinctrl_drive_e4_conf, + .num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf), + }, + [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = { + .confs = pinctrl_pcie_rst_od_conf, + .num_confs = ARRAY_SIZE(pinctrl_pcie_rst_od_conf), + }, + }, +}; + +static const struct of_device_id airoha_pinctrl_of_match[] = { + { .compatible = "airoha,an7563-pinctrl", .data = &pinctrl_match_data }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match); + +static struct platform_driver airoha_pinctrl_driver = { + .probe = airoha_pinctrl_probe, + .driver = { + .name = "pinctrl-airoha-an7563", + .of_match_table = airoha_pinctrl_of_match, + }, +}; +module_platform_driver(airoha_pinctrl_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Lorenzo Bianconi "); +MODULE_AUTHOR("Benjamin Larsson "); +MODULE_AUTHOR("Markus Gothe "); +MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7563 SoC"); From 465f276bb928093685c2a2b98bf0a7ccc4283b8d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alvin=20=C5=A0ipraga?= Date: Mon, 27 Jul 2026 14:20:08 +0200 Subject: [PATCH 120/130] pinctrl: fix PINCTRL_GENERIC_MUX not always being selectable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CONFIG_MULTIPLEXER can only be enabled indirectly. If it's not already enabled, then CONFIG_PINCTRL_GENERIC_MUX cannot be selected at all in menuconfig. That's because it depends on MULTIPLEXER. Follow similar consumers of the multiplexer core and select MULTIPLEXER instead. This way the driver will be visible in menuconfig as long as PINCTRL is selected. Fixes: 34acc5a8adfb ("pinctrl: add generic board-level pinctrl driver using mux framework") Signed-off-by: Alvin Šipraga Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index fdcd0ea34d6f..582701445308 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -274,8 +274,8 @@ config PINCTRL_GEMINI config PINCTRL_GENERIC_MUX tristate "Generic Pinctrl driver by using multiplexer" - depends on MULTIPLEXER depends on OF + select MULTIPLEXER select PINMUX select GENERIC_PINCTRL help From 8aa25c6e8893ed911b0cad37a5562fda9bc98438 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 29 Jul 2026 07:27:25 -0600 Subject: [PATCH 121/130] pinctrl: rockchip: Decode drive strength in the get function The decoding of the 2-bit and 8-bit level drive-strength values sits in rockchip_set_drive_perpin(), where it is unreachable: the SoCs whose banks declare these drive types (RK3506 and RV1103B) take the early ctrl->type branch in the set path, and the read-and-decode logic in a set function has no purpose. Meanwhile rockchip_get_drive_perpin() lacks the decoding, so pin_config_get() and the debugfs output report -EINVAL for these SoCs. Move the two cases to rockchip_get_drive_perpin(), where they belong. Fixes: dbd2317d7b9f ("pinctrl: rockchip: Add rk3506 pinctrl support") Signed-off-by: Simon Glass Reviewed-by: Heiko Stuebner Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-rockchip.c | 38 +++++++++++++++--------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 8c7e410ec9d1..4ad522c6d6d6 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -3405,6 +3405,25 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, case DRV_TYPE_IO_1V8_ONLY: rmask_bits = RK3288_DRV_BITS_PER_PIN; break; + case DRV_TYPE_IO_LEVEL_2_BIT: + ret = regmap_read(regmap, reg, &data); + if (ret) + return ret; + data >>= bit; + + return data & 0x3; + case DRV_TYPE_IO_LEVEL_8_BIT: + ret = regmap_read(regmap, reg, &data); + if (ret) + return ret; + data >>= bit; + data &= (1 << 8) - 1; + + ret = hweight8(data); + if (ret > 0) + return ret - 1; + else + return -EINVAL; default: dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type); return -EINVAL; @@ -3528,25 +3547,6 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, case DRV_TYPE_IO_1V8_ONLY: rmask_bits = RK3288_DRV_BITS_PER_PIN; break; - case DRV_TYPE_IO_LEVEL_2_BIT: - ret = regmap_read(regmap, reg, &data); - if (ret) - return ret; - data >>= bit; - - return data & 0x3; - case DRV_TYPE_IO_LEVEL_8_BIT: - ret = regmap_read(regmap, reg, &data); - if (ret) - return ret; - data >>= bit; - data &= (1 << 8) - 1; - - ret = hweight8(data); - if (ret > 0) - return ret - 1; - else - return -EINVAL; default: dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type); return -EINVAL; From 80c44921f9e6a1cda748db8cbc39976045bebfbb Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 29 Jul 2026 07:27:27 -0600 Subject: [PATCH 122/130] dt-bindings: pinctrl: rockchip: Add RV1106 compatible Add the compatible for the pin controller of the Rockchip RV1106 and its RV1103 package variant. Signed-off-by: Simon Glass Acked-by: Rob Herring (Arm) Reviewed-by: Heiko Stuebner Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml index 9b3cbeb54fed..81747bb53056 100644 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml @@ -51,6 +51,7 @@ properties: - rockchip,rk3576-pinctrl - rockchip,rk3588-pinctrl - rockchip,rv1103b-pinctrl + - rockchip,rv1106-pinctrl - rockchip,rv1108-pinctrl - rockchip,rv1126-pinctrl From 63113d4fce6ca60a3de84a6f8bb0371513969bda Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 29 Jul 2026 07:27:28 -0600 Subject: [PATCH 123/130] pinctrl: rockchip: Add RV1106 pinctrl support Add pinctrl support for the Rockchip RV1106, based on the vendor kernel in the Luckfox Pico SDK [1] at commit 824b817f8 (a Linux 5.10.160 kernel tree). Each GPIO bank has its own IO control (IOC) register block, referenced by the rockchip,grf phandle of the bank node; the register offsets are relative to the bank's own block. The drive strength uses the RK3568-style exponential encoding and only pins 0-6 of GPIO0 have drive-strength registers. The RV1103 is a package variant of the RV1106 with fewer pins and uses the same pin controller. [1] https://github.com/LuckfoxTECH/luckfox-pico Signed-off-by: Simon Glass Reviewed-by: Heiko Stuebner Link: https://github.com/LuckfoxTECH/luckfox-pico Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-rockchip.c | 192 +++++++++++++++++++++++++++++ drivers/pinctrl/pinctrl-rockchip.h | 4 + 2 files changed, 196 insertions(+) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 4ad522c6d6d6..ba47b6f323cc 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -1326,6 +1326,12 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) else regmap = info->regmap_base; + /* Banks with their own IOC block use its regmap for the iomux */ + if (bank->regmap_ioc) + regmap = bank->regmap_ioc; + else if (ctrl->type == RV1106) + return -EINVAL; + if (ctrl->type == RV1103B && bank->bank_num == 2 && pin >= 12) return 0; @@ -1455,6 +1461,12 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) else regmap = info->regmap_base; + /* Banks with their own IOC block use its regmap for the iomux */ + if (bank->regmap_ioc) + regmap = bank->regmap_ioc; + else if (ctrl->type == RV1106) + return -EINVAL; + if (ctrl->type == RV1103B && bank->bank_num == 2 && pin >= 12) return 0; @@ -1863,6 +1875,78 @@ static int rv1103b_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, return 0; } +#define RV1106_DRV_BITS_PER_PIN 8 +#define RV1106_DRV_PINS_PER_REG 2 +#define RV1106_PULL_BITS_PER_PIN 2 +#define RV1106_PULL_PINS_PER_REG 8 +#define RV1106_SMT_BITS_PER_PIN 1 +#define RV1106_SMT_PINS_PER_REG 8 + +/* + * Each bank has its own IOC block, referenced by the rockchip,grf + * phandle of the bank node. The offsets below are relative to the + * bank's own block. + */ +static const int rv1106_drv_offsets[] = { 0x10, 0x80, 0xc0, 0x100, 0x20 }; +static const int rv1106_pull_offsets[] = { 0x38, 0x1c0, 0x1d0, 0x1e0, 0x70 }; +static const int rv1106_smt_offsets[] = { 0x40, 0x280, 0x290, 0x2a0, 0xa0 }; + +static int rv1106_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + if (bank->bank_num >= ARRAY_SIZE(rv1106_drv_offsets) || + !bank->regmap_ioc) + return -EINVAL; + + /* Only pins 0-6 of GPIO0 have drive-strength registers */ + if (bank->bank_num == 0 && pin_num > 6) + return -ENOTSUPP; + + *regmap = bank->regmap_ioc; + *reg = rv1106_drv_offsets[bank->bank_num]; + *reg += ((pin_num / RV1106_DRV_PINS_PER_REG) * 4); + *bit = pin_num % RV1106_DRV_PINS_PER_REG; + *bit *= RV1106_DRV_BITS_PER_PIN; + + return 0; +} + +static int rv1106_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + if (bank->bank_num >= ARRAY_SIZE(rv1106_pull_offsets) || + !bank->regmap_ioc) + return -EINVAL; + + *regmap = bank->regmap_ioc; + *reg = rv1106_pull_offsets[bank->bank_num]; + *reg += ((pin_num / RV1106_PULL_PINS_PER_REG) * 4); + *bit = pin_num % RV1106_PULL_PINS_PER_REG; + *bit *= RV1106_PULL_BITS_PER_PIN; + + return 0; +} + +static int rv1106_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, + struct regmap **regmap, + int *reg, u8 *bit) +{ + if (bank->bank_num >= ARRAY_SIZE(rv1106_smt_offsets) || + !bank->regmap_ioc) + return -EINVAL; + + *regmap = bank->regmap_ioc; + *reg = rv1106_smt_offsets[bank->bank_num]; + *reg += ((pin_num / RV1106_SMT_PINS_PER_REG) * 4); + *bit = pin_num % RV1106_SMT_PINS_PER_REG; + *bit *= RV1106_SMT_BITS_PER_PIN; + + return 0; +} + #define RV1108_PULL_PMU_OFFSET 0x10 #define RV1108_PULL_OFFSET 0x110 #define RV1108_PULL_PINS_PER_REG 8 @@ -3467,6 +3551,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, ret = strength; goto config; } else if (ctrl->type == RV1103B || + ctrl->type == RV1106 || ctrl->type == RK3506 || ctrl->type == RK3528 || ctrl->type == RK3562 || @@ -3620,6 +3705,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) : PIN_CONFIG_BIAS_DISABLE; case PX30: case RV1103B: + case RV1106: case RV1108: case RK3188: case RK3288: @@ -3686,6 +3772,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, break; case PX30: case RV1103B: + case RV1106: case RV1108: case RV1126: case RK3188: @@ -3983,6 +4070,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, return pull ? false : true; case PX30: case RV1103B: + case RV1106: case RV1108: case RV1126: case RK3188: @@ -4682,6 +4770,7 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) struct resource *res; void __iomem *base; int ret; + int i; if (!dev->of_node) return dev_err_probe(dev, -ENODEV, "device tree node not found\n"); @@ -4743,6 +4832,44 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) iomux_recalced_routes_init(info); + /* + * On SoCs where each GPIO bank has its own IOC block, the bank nodes + * carry a rockchip,grf phandle pointing at it. The bank number comes + * from the gpio alias, as used by the gpio driver, falling back to + * the node position for devicetrees without aliases. The fallback is + * wrong when an SoC variant omits a bank, so aliases are needed + * there. + */ + i = 0; + for_each_child_of_node_scoped(np, child) { + struct rockchip_pin_bank *bank = NULL; + int id, j; + + if (!of_match_node(rockchip_bank_match, child)) + continue; + + id = of_alias_get_id(child, "gpio"); + if (id < 0) + id = i; + i++; + + for (j = 0; j < ctrl->nr_banks; j++) { + if (ctrl->pin_banks[j].bank_num == id) { + bank = &ctrl->pin_banks[j]; + break; + } + } + if (!bank) + continue; + + bank->regmap_ioc = syscon_regmap_lookup_by_phandle_optional( + child, "rockchip,grf"); + if (IS_ERR(bank->regmap_ioc)) + return dev_err_probe(dev, PTR_ERR(bank->regmap_ioc), + "%pOFn: failed to look up bank ioc\n", + child); + } + ret = rockchip_pinctrl_register(pdev, info); if (ret) return ret; @@ -4861,6 +4988,69 @@ static struct rockchip_pin_ctrl rv1103b_pin_ctrl __maybe_unused = { .schmitt_calc_reg = rv1103b_calc_schmitt_reg_and_bit, }; +static struct rockchip_pin_bank rv1106_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(0, 32, "gpio0", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0, -1, -1, -1, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT), + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(1, 32, "gpio1", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0, -1, -1, -1, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT), + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(2, 32, "gpio2", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x20, -1, -1, -1, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT), + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(3, 32, "gpio3", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x40, -1, -1, -1, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT), + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(4, 24, "gpio4", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0, + 0, -1, -1, -1, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT), +}; + +static struct rockchip_pin_ctrl rv1106_pin_ctrl __maybe_unused = { + .pin_banks = rv1106_pin_banks, + .nr_banks = ARRAY_SIZE(rv1106_pin_banks), + .label = "RV1106-GPIO", + .type = RV1106, + .pull_calc_reg = rv1106_calc_pull_reg_and_bit, + .drv_calc_reg = rv1106_calc_drv_reg_and_bit, + .schmitt_calc_reg = rv1106_calc_schmitt_reg_and_bit, +}; + static struct rockchip_pin_bank rv1108_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, IOMUX_SOURCE_PMU, @@ -5499,6 +5689,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = { .data = &px30_pin_ctrl }, { .compatible = "rockchip,rv1103b-pinctrl", .data = &rv1103b_pin_ctrl }, + { .compatible = "rockchip,rv1106-pinctrl", + .data = &rv1106_pin_ctrl }, { .compatible = "rockchip,rv1108-pinctrl", .data = &rv1108_pin_ctrl }, { .compatible = "rockchip,rv1126-pinctrl", diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h index 914582c87dd8..950097699643 100644 --- a/drivers/pinctrl/pinctrl-rockchip.h +++ b/drivers/pinctrl/pinctrl-rockchip.h @@ -186,6 +186,7 @@ enum rockchip_pinctrl_type { PX30, RV1103B, + RV1106, RV1108, RV1126, RK2928, @@ -296,6 +297,8 @@ struct rockchip_drv { * @dev: the pinctrl device bind to the bank * @reg_base: register base of the gpio bank * @regmap_pull: optional separate register for additional pull settings + * @regmap_ioc: optional per-bank IO control regmap, for SoCs where each + * bank has its own IOC block * @clk: clock of the gpio bank * @db_clk: clock of the gpio debounce * @irq: interrupt of the gpio bank @@ -324,6 +327,7 @@ struct rockchip_pin_bank { struct device *dev; void __iomem *reg_base; struct regmap *regmap_pull; + struct regmap *regmap_ioc; struct clk *clk; struct clk *db_clk; int irq; From fedfa225fd6f3802885060591faf5fc05777ec85 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 11 Aug 2026 08:49:40 +0200 Subject: [PATCH 124/130] Revert "Merge branch 'ib-rsk7204' into devel" This reverts commit d922b54e942ee9c798b0d688b025362a24d864ea, reversing changes made to 3f0245e23a176e78f00a760291b8e4f88d01d77e. The SH maintainer has indicated that he want to carry these changes in the SH tree instead, and need more time to review and merge the changes, so reverting it out from my tree. Signed-off-by: Linus Walleij --- arch/sh/boards/mach-rsk/devices-rsk7203.c | 302 ++++++---------------- arch/sh/include/cpu-common/cpu/pfc.h | 3 - arch/sh/kernel/cpu/pfc.c | 20 +- drivers/pinctrl/renesas/gpio.c | 28 -- 4 files changed, 89 insertions(+), 264 deletions(-) diff --git a/arch/sh/boards/mach-rsk/devices-rsk7203.c b/arch/sh/boards/mach-rsk/devices-rsk7203.c index e8a8fc1d2ca9..e6b05d4588b7 100644 --- a/arch/sh/boards/mach-rsk/devices-rsk7203.c +++ b/arch/sh/boards/mach-rsk/devices-rsk7203.c @@ -4,18 +4,17 @@ * * Copyright (C) 2008 - 2010 Paul Mundt */ -#include #include #include #include #include #include #include -#include -#include -#include +#include +#include +#include #include -#include +#include #include static struct smsc911x_platform_config smsc911x_config = { @@ -38,236 +37,101 @@ static struct resource smsc911x_resources[] = { }, }; -static const struct software_node rsk7203_gpio_leds_node = { - .name = "rsk7203-gpio-leds", -}; - -static const struct software_node rsk7203_green_led_node = { - .name = "green", - .parent = &rsk7203_gpio_leds_node, - .properties = (const struct property_entry[]) { - PROPERTY_ENTRY_STRING("label", "green"), - PROPERTY_ENTRY_GPIO("gpios", &pfc_gpiochip_node, - GPIO_PE10, GPIO_ACTIVE_LOW), - { } +static struct platform_device smsc911x_device = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, + .dev = { + .platform_data = &smsc911x_config, }, }; -static const struct software_node rsk7203_orange_led_node = { - .name = "orange", - .parent = &rsk7203_gpio_leds_node, - .properties = (const struct property_entry[]) { - PROPERTY_ENTRY_STRING("label", "orange"), - PROPERTY_ENTRY_STRING("linux,default-trigger", "nand-disk"), - PROPERTY_ENTRY_GPIO("gpios", &pfc_gpiochip_node, - GPIO_PE12, GPIO_ACTIVE_LOW), - { } - }, -}; - -static const struct software_node rsk7203_red1_led_node = { - .name = "red:timer", - .parent = &rsk7203_gpio_leds_node, - .properties = (const struct property_entry[]) { - PROPERTY_ENTRY_STRING("label", "red:timer"), - PROPERTY_ENTRY_STRING("linux,default-trigger", "timer"), - PROPERTY_ENTRY_GPIO("gpios", &pfc_gpiochip_node, - GPIO_PC14, GPIO_ACTIVE_LOW), - { } - }, -}; - -static const struct software_node rsk7203_red2_led_node = { - .name = "red:heartbeat", - .parent = &rsk7203_gpio_leds_node, - .properties = (const struct property_entry[]) { - PROPERTY_ENTRY_STRING("label", "red:heartbeat"), - PROPERTY_ENTRY_STRING("linux,default-trigger", "heartbeat"), - PROPERTY_ENTRY_GPIO("gpios", &pfc_gpiochip_node, - GPIO_PE11, GPIO_ACTIVE_LOW), - { } - }, -}; - -static const struct software_node rsk7203_gpio_keys_node = { - .name = "rsk7203-gpio-keys", - .properties = (const struct property_entry[]) { - PROPERTY_ENTRY_U32("poll-interval", 50), - { } - }, -}; - -static const struct software_node rsk7203_sw1_key_node = { - .parent = &rsk7203_gpio_keys_node, - .properties = (const struct property_entry[]) { - PROPERTY_ENTRY_U32("linux,code", BTN_0), - PROPERTY_ENTRY_GPIO("gpios", &pfc_gpiochip_node, - GPIO_PB0, GPIO_ACTIVE_LOW), - PROPERTY_ENTRY_STRING("label", "SW1"), - { } - }, -}; - -static const struct software_node rsk7203_sw2_key_node = { - .parent = &rsk7203_gpio_keys_node, - .properties = (const struct property_entry[]) { - PROPERTY_ENTRY_U32("linux,code", BTN_1), - PROPERTY_ENTRY_GPIO("gpios", &pfc_gpiochip_node, - GPIO_PB1, GPIO_ACTIVE_LOW), - PROPERTY_ENTRY_STRING("label", "SW2"), - { } - }, -}; - -static const struct software_node rsk7203_sw3_key_node = { - .parent = &rsk7203_gpio_keys_node, - .properties = (const struct property_entry[]) { - PROPERTY_ENTRY_U32("linux,code", BTN_2), - PROPERTY_ENTRY_GPIO("gpios", &pfc_gpiochip_node, - GPIO_PB2, GPIO_ACTIVE_LOW), - PROPERTY_ENTRY_STRING("label", "SW3"), - { } - }, -}; - -/* The base of the function GPIOs in the flat enum */ -#define SH7203_FN_BASE GPIO_FN_PINT7_PB - -static const struct software_node rsk7203_pfc_functions_node = { - .name = "functions", - .parent = &pfc_gpiochip_node, -}; - -static const struct software_node rsk7203_txd0_hog_node = { - .name = "txd0-hog", - .parent = &rsk7203_pfc_functions_node, - .properties = (const struct property_entry[]) { - PROPERTY_ENTRY_BOOL("gpio-hog"), - PROPERTY_ENTRY_U32_ARRAY("gpios", ((u32[]){ - GPIO_FN_TXD0 - SH7203_FN_BASE, GPIO_ACTIVE_HIGH - })), - PROPERTY_ENTRY_BOOL("input"), - PROPERTY_ENTRY_STRING("line-name", "TXD0"), - { } - }, -}; - -static const struct software_node rsk7203_rxd0_hog_node = { - .name = "rxd0-hog", - .parent = &rsk7203_pfc_functions_node, - .properties = (const struct property_entry[]) { - PROPERTY_ENTRY_BOOL("gpio-hog"), - PROPERTY_ENTRY_U32_ARRAY("gpios", ((u32[]){ - GPIO_FN_RXD0 - SH7203_FN_BASE, GPIO_ACTIVE_HIGH - })), - PROPERTY_ENTRY_BOOL("input"), - PROPERTY_ENTRY_STRING("line-name", "RXD0"), - { } - }, -}; - -static const struct software_node rsk7203_irq0_hog_node = { - .name = "irq0-hog", - .parent = &rsk7203_pfc_functions_node, - .properties = (const struct property_entry[]) { - PROPERTY_ENTRY_BOOL("gpio-hog"), - PROPERTY_ENTRY_U32_ARRAY("gpios", ((u32[]){ - GPIO_FN_IRQ0_PB - SH7203_FN_BASE, GPIO_ACTIVE_HIGH - })), - PROPERTY_ENTRY_BOOL("input"), - PROPERTY_ENTRY_STRING("line-name", "IRQ0_PB"), - { } - }, -}; - -static const struct software_node * const rsk7203_swnodes[] __initconst = { - &rsk7203_gpio_leds_node, - &rsk7203_green_led_node, - &rsk7203_orange_led_node, - &rsk7203_red1_led_node, - &rsk7203_red2_led_node, - &rsk7203_gpio_keys_node, - &rsk7203_sw1_key_node, - &rsk7203_sw2_key_node, - &rsk7203_sw3_key_node, - &rsk7203_pfc_functions_node, - &rsk7203_txd0_hog_node, - &rsk7203_rxd0_hog_node, - &rsk7203_irq0_hog_node, - NULL -}; - -static const struct platform_device_info rsk7203_devices[] __initconst = { +static struct gpio_led rsk7203_gpio_leds[] = { { - .name = "smsc911x", - .id = PLATFORM_DEVID_NONE, - .res = smsc911x_resources, - .num_res = ARRAY_SIZE(smsc911x_resources), - .data = &smsc911x_config, - .size_data = sizeof(smsc911x_config), - }, - { - .name = "leds-gpio", - .id = PLATFORM_DEVID_NONE, - .swnode = &rsk7203_gpio_leds_node, - }, - { - .name = "gpio-keys-polled", - .id = PLATFORM_DEVID_NONE, - .swnode = &rsk7203_gpio_keys_node, + .name = "green", + .gpio = GPIO_PE10, + .active_low = 1, + }, { + .name = "orange", + .default_trigger = "nand-disk", + .gpio = GPIO_PE12, + .active_low = 1, + }, { + .name = "red:timer", + .default_trigger = "timer", + .gpio = GPIO_PC14, + .active_low = 1, + }, { + .name = "red:heartbeat", + .default_trigger = "heartbeat", + .gpio = GPIO_PE11, + .active_low = 1, }, }; -/* - * The pfc-sh7203 device is registered at arch_initcall level, and the - * sh-pfc driver (registered at postcore_initcall level) probes as soon - * as the device is created. - * - * We need to register our software nodes at postcore_initcall level so - * they are already present in the system when the driver probes and - * tries to apply GPIO hogs. - */ -static int __init rsk7203_sw_nodes_setup(void) -{ - int error; +static struct gpio_led_platform_data rsk7203_gpio_leds_info = { + .leds = rsk7203_gpio_leds, + .num_leds = ARRAY_SIZE(rsk7203_gpio_leds), +}; - error = software_node_register(&pfc_gpiochip_node); - if (error && error != -EEXIST) { - pr_err("RSK7203: failed to register PFC software node: %d\n", - error); - return error; - } +static struct platform_device led_device = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &rsk7203_gpio_leds_info, + }, +}; - error = software_node_register_node_group(rsk7203_swnodes); - if (error) { - pr_err("RSK7203: failed to register board software nodes: %d\n", - error); - return error; - } +static struct gpio_keys_button rsk7203_gpio_keys_table[] = { + { + .code = BTN_0, + .gpio = GPIO_PB0, + .active_low = 1, + .desc = "SW1", + }, { + .code = BTN_1, + .gpio = GPIO_PB1, + .active_low = 1, + .desc = "SW2", + }, { + .code = BTN_2, + .gpio = GPIO_PB2, + .active_low = 1, + .desc = "SW3", + }, +}; - return 0; -} -postcore_initcall(rsk7203_sw_nodes_setup); +static struct gpio_keys_platform_data rsk7203_gpio_keys_info = { + .buttons = rsk7203_gpio_keys_table, + .nbuttons = ARRAY_SIZE(rsk7203_gpio_keys_table), + .poll_interval = 50, /* default to 50ms */ +}; + +static struct platform_device keys_device = { + .name = "gpio-keys-polled", + .dev = { + .platform_data = &rsk7203_gpio_keys_info, + }, +}; + +static struct platform_device *rsk7203_devices[] __initdata = { + &smsc911x_device, + &led_device, + &keys_device, +}; static int __init rsk7203_devices_setup(void) { - struct platform_device *pd; - int error; - int i; + /* Select pins for SCIF0 */ + gpio_request(GPIO_FN_TXD0, NULL); + gpio_request(GPIO_FN_RXD0, NULL); /* Setup LAN9118: CS1 in 16-bit Big Endian Mode, IRQ0 at Port B */ __raw_writel(0x36db0400, 0xfffc0008); /* CS1BCR */ + gpio_request(GPIO_FN_IRQ0_PB, NULL); - for (i = 0; i < ARRAY_SIZE(rsk7203_devices); i++) { - pd = platform_device_register_full(&rsk7203_devices[i]); - error = PTR_ERR_OR_ZERO(pd); - if (error) { - pr_err("failed to create platform device %s: %d\n", - rsk7203_devices[i].name, error); - return error; - } - } - - return 0; + return platform_add_devices(rsk7203_devices, + ARRAY_SIZE(rsk7203_devices)); } device_initcall(rsk7203_devices_setup); diff --git a/arch/sh/include/cpu-common/cpu/pfc.h b/arch/sh/include/cpu-common/cpu/pfc.h index d57e38c05bdb..879d2c9da537 100644 --- a/arch/sh/include/cpu-common/cpu/pfc.h +++ b/arch/sh/include/cpu-common/cpu/pfc.h @@ -11,9 +11,6 @@ #include struct resource; -struct software_node; - -extern const struct software_node pfc_gpiochip_node; int sh_pfc_register(const char *name, struct resource *resource, u32 num_resources); diff --git a/arch/sh/kernel/cpu/pfc.c b/arch/sh/kernel/cpu/pfc.c index 5a8d804d607b..062056ede88d 100644 --- a/arch/sh/kernel/cpu/pfc.c +++ b/arch/sh/kernel/cpu/pfc.c @@ -5,29 +5,21 @@ * Copyright (C) 2012 Renesas Solutions Corp. */ -#include #include #include -#include #include -const struct software_node pfc_gpiochip_node = { - .name = "sh-pfc", +static struct platform_device sh_pfc_device = { + .id = -1, }; int __init sh_pfc_register(const char *name, struct resource *resource, u32 num_resources) { - struct platform_device_info pdev_info = { - .name = name, - .id = PLATFORM_DEVID_NONE, - .res = resource, - .num_res = num_resources, - .swnode = &pfc_gpiochip_node, - }; - struct platform_device *pdev; + sh_pfc_device.name = name; + sh_pfc_device.num_resources = num_resources; + sh_pfc_device.resource = resource; - pdev = platform_device_register_full(&pdev_info); - return PTR_ERR_OR_ZERO(pdev); + return platform_device_register(&sh_pfc_device); } diff --git a/drivers/pinctrl/renesas/gpio.c b/drivers/pinctrl/renesas/gpio.c index b49a3e14da91..2293af642849 100644 --- a/drivers/pinctrl/renesas/gpio.c +++ b/drivers/pinctrl/renesas/gpio.c @@ -271,41 +271,13 @@ static int gpio_function_request(struct gpio_chip *gc, unsigned offset) return ret; } -static void sh_pfc_fwnode_put(void *data) -{ - fwnode_handle_put(data); -} - static int gpio_function_setup(struct sh_pfc_chip *chip) { struct sh_pfc *pfc = chip->pfc; struct gpio_chip *gc = &chip->gpio_chip; - struct fwnode_handle *fwnode = dev_fwnode(pfc->dev); gc->request = gpio_function_request; - if (is_software_node(fwnode)) { - fwnode = fwnode_get_named_child_node(fwnode, "functions"); - if (fwnode) { - int ret; - - ret = devm_add_action_or_reset(pfc->dev, - sh_pfc_fwnode_put, - fwnode); - if (ret) - return ret; - - gc->fwnode = fwnode; - } - } - - /* - * If we did not find 'functions' node, explicitly mask the parent's - * fwnode to prevent gpiolib from reusing it for function GPIOs. - */ - if (!gc->fwnode) - gc->fwnode = ERR_PTR(-ENODEV); - gc->label = pfc->info->name; gc->owner = THIS_MODULE; gc->base = pfc->nr_gpio_pins; From daa12f3a63a366123a88e66dac23a26a536a240d Mon Sep 17 00:00:00 2001 From: Udaya Kiran Challa Date: Fri, 31 Jul 2026 23:15:51 +0530 Subject: [PATCH 125/130] dt-bindings: pinctrl: microchip,pic32mzda-pinctrl: Convert to DT schema Convert Microchip PIC32 Pin Controller devicetree binding from legacy text format to DT schema. Signed-off-by: Udaya Kiran Challa Reviewed-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- .../pinctrl/microchip,pic32-pinctrl.txt | 60 ---------- .../pinctrl/microchip,pic32mzda-pinctrl.yaml | 109 ++++++++++++++++++ 2 files changed, 109 insertions(+), 60 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,pic32mzda-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt deleted file mode 100644 index 51efd2085113..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt +++ /dev/null @@ -1,60 +0,0 @@ -* Microchip PIC32 Pin Controller - -Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and -../interrupt-controller/interrupts.txt for generic information regarding -pin controller, GPIO, and interrupt bindings. - -PIC32 'pin configuration node' is a node of a group of pins which can be -used for a specific device or function. This node represents configurations of -pins, optional function, and optional mux related configuration. - -Required properties for pin controller node: - - compatible: "microchip,pic32mada-pinctrl" - - reg: Address range of the pinctrl registers. - - clocks: Clock specifier (see clock bindings for details) - -Required properties for pin configuration sub-nodes: - - pins: List of pins to which the configuration applies. - -Optional properties for pin configuration sub-nodes: ----------------------------------------------------- - - function: Mux function for the specified pins. - - bias-pull-up: Enable weak pull-up. - - bias-pull-down: Enable weak pull-down. - - input-enable: Set the pin as an input. - - output-low: Set the pin as an output level low. - - output-high: Set the pin as an output level high. - - microchip,digital: Enable digital I/O. - - microchip,analog: Enable analog I/O. - -Example: - -pic32_pinctrl: pinctrl@1f801400{ - #address-cells = <1>; - #size-cells = <1>; - compatible = "microchip,pic32mzda-pinctrl"; - reg = <0x1f801400 0x400>; - clocks = <&rootclk PB1CLK>; - - pinctrl_uart2: pinctrl_uart2 { - uart2-tx { - pins = "G9"; - function = "U2TX"; - microchip,digital; - output-low; - }; - uart2-rx { - pins = "B0"; - function = "U2RX"; - microchip,digital; - input-enable; - }; - }; -}; - -uart2: serial@1f822200 { - compatible = "microchip,pic32mzda-uart"; - reg = <0x1f822200 0x50>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,pic32mzda-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,pic32mzda-pinctrl.yaml new file mode 100644 index 000000000000..dcaa87d9a30b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/microchip,pic32mzda-pinctrl.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/microchip,pic32mzda-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PIC32 Pin Controller + +maintainers: + - Linus Walleij + +description: + PIC32 pin configuration node is a node of a group of pins which can be used + for a specific device or function. This node represents configurations of + pins, optional function, and optional mux related configuration. + +properties: + compatible: + const: microchip,pic32mzda-pinctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +$defs: + pin-node: + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml# + - $ref: /schemas/pinctrl/pinmux-node.yaml# + + properties: + pins: + description: List of pins to which the configuration applies. + items: + type: string + minItems: 1 + + function: true + + bias-pull-up: true + bias-pull-down: true + input-enable: true + output-low: true + output-high: true + + microchip,digital: + description: Enable digital I/O. + type: boolean + + microchip,analog: + description: Enable analog I/O. + type: boolean + + required: + - pins + + unevaluatedProperties: false + +additionalProperties: + oneOf: + - additionalProperties: + $ref: '#/$defs/pin-node' + - $ref: '#/$defs/pin-node' + +required: + - compatible + - reg + - clocks + +examples: + - | + #include + #include + + pic32_pinctrl: pinctrl@1f801400 { + compatible = "microchip,pic32mzda-pinctrl"; + reg = <0x1f801400 0x400>; + clocks = <&rootclk PB1CLK>; + + pinctrl_uart2: pinctrl_uart2 { + uart2-tx { + pins = "G9"; + function = "U2TX"; + microchip,digital; + output-low; + }; + + uart2-rx { + pins = "B0"; + function = "U2RX"; + microchip,digital; + input-enable; + }; + }; + }; + + uart2: serial@1f822200 { + compatible = "microchip,pic32mzda-uart"; + reg = <0x1f822200 0x50>; + interrupts = <145 IRQ_TYPE_LEVEL_HIGH>, + <146 IRQ_TYPE_LEVEL_HIGH>, + <147 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rootclk PB2CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + }; From 287ff7feb1c7925cc1bf45d8c8e0751cdc96534f Mon Sep 17 00:00:00 2001 From: Yu-Chun Lin Date: Wed, 12 Aug 2026 09:59:14 +0800 Subject: [PATCH 126/130] pinctrl: realtek: rtd1625: fix base_bit for VE4 GPIO 13 Fix a typo in the base_bit of RTD1625_VE4_GPIO_13. It was incorrectly set to 18, which overlaps with GPIO 16. Signed-off-by: Yu-Chun Lin Signed-off-by: Linus Walleij --- drivers/pinctrl/realtek/pinctrl-rtd1625.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/realtek/pinctrl-rtd1625.c b/drivers/pinctrl/realtek/pinctrl-rtd1625.c index 2d623bdbf9ca..796e51f9dff9 100644 --- a/drivers/pinctrl/realtek/pinctrl-rtd1625.c +++ b/drivers/pinctrl/realtek/pinctrl-rtd1625.c @@ -2867,7 +2867,7 @@ static const struct rtd_pin_config_desc rtd1625_ve4_configs[] = { [RTD1625_VE4_GPIO_6] = RTK_PIN_CONFIG_V2(gpio_6, 0x1c, 24, 1, 2, 0, 3, 4, 5, PADDRI_4_8), [RTD1625_VE4_GPIO_7] = RTK_PIN_CONFIG_V2(gpio_7, 0x20, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8), [RTD1625_VE4_GPIO_12] = RTK_PIN_CONFIG_V2(gpio_12, 0x20, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8), - [RTD1625_VE4_GPIO_13] = RTK_PIN_CONFIG_V2(gpio_13, 0x20, 18, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_13] = RTK_PIN_CONFIG_V2(gpio_13, 0x20, 12, 1, 2, 0, 3, 4, 5, PADDRI_4_8), [RTD1625_VE4_GPIO_16] = RTK_PIN_CONFIG_V2(gpio_16, 0x20, 18, 1, 2, 0, 3, 4, 5, PADDRI_4_8), [RTD1625_VE4_GPIO_17] = RTK_PIN_CONFIG_V2(gpio_17, 0x20, 24, 1, 2, 0, 3, 4, 5, PADDRI_4_8), [RTD1625_VE4_GPIO_18] = RTK_PIN_CONFIG_V2(gpio_18, 0x24, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8), From f080cfd001809eee9d647cd44de3267ee68c914c Mon Sep 17 00:00:00 2001 From: Yu-Chun Lin Date: Wed, 12 Aug 2026 09:59:15 +0800 Subject: [PATCH 127/130] pinctrl: realtek: rtd1625: remove unused group name spdif_sel Remove the undefined "spdif_sel" from rtd1625_iso_spdif_in_coaxial_groups to clean up the code. Signed-off-by: Yu-Chun Lin Signed-off-by: Linus Walleij --- drivers/pinctrl/realtek/pinctrl-rtd1625.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/realtek/pinctrl-rtd1625.c b/drivers/pinctrl/realtek/pinctrl-rtd1625.c index 796e51f9dff9..88f2be37f743 100644 --- a/drivers/pinctrl/realtek/pinctrl-rtd1625.c +++ b/drivers/pinctrl/realtek/pinctrl-rtd1625.c @@ -986,7 +986,7 @@ static const char * const rtd1625_iso_pwm0_loc2_groups[] = { }; static const char * const rtd1625_iso_spdif_in_coaxial_groups[] = { - "gpio_163", "spdif_sel", "spdif_in_mode" + "gpio_163", "spdif_in_mode" }; static const char * const rtd1625_iso_spdif_in_gpio_groups[] = { From 44f10eb88869bd6236ea525e9542116dad8972c0 Mon Sep 17 00:00:00 2001 From: Xianwei Zhao Date: Wed, 12 Aug 2026 10:17:44 +0000 Subject: [PATCH 128/130] pinctrl: meson: a4: Add input enable pin configuration Add support for PIN_CONFIG_INPUT_ENABLE in the Amlogic A4 pinctrl driver. Use the existing output enable control to configure the input enable state, since the hardware uses the same control with inverse semantics. Also update PIN_CONFIG_OUTPUT_ENABLE handling to return the actual output enable state instead of treating any non-zero value as enabled. Signed-off-by: Xianwei Zhao Signed-off-by: Linus Walleij --- drivers/pinctrl/meson/pinctrl-amlogic-a4.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/meson/pinctrl-amlogic-a4.c b/drivers/pinctrl/meson/pinctrl-amlogic-a4.c index 420f7915c010..39eb8cc7fc0d 100644 --- a/drivers/pinctrl/meson/pinctrl-amlogic-a4.c +++ b/drivers/pinctrl/meson/pinctrl-amlogic-a4.c @@ -469,9 +469,15 @@ static int aml_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin, break; case PIN_CONFIG_OUTPUT_ENABLE: ret = aml_pinconf_get_output(info, pin); - if (ret <= 0) + if (ret < 0) return -EINVAL; - arg = 1; + arg = ret; + break; + case PIN_CONFIG_INPUT_ENABLE: + ret = aml_pinconf_get_output(info, pin); + if (ret < 0) + return -EINVAL; + arg = !ret; break; case PIN_CONFIG_LEVEL: ret = aml_pinconf_get_output(info, pin); @@ -619,6 +625,7 @@ static int aml_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, switch (param) { case PIN_CONFIG_DRIVE_STRENGTH_UA: case PIN_CONFIG_OUTPUT_ENABLE: + case PIN_CONFIG_INPUT_ENABLE: case PIN_CONFIG_LEVEL: arg = pinconf_to_config_argument(configs[i]); break; @@ -643,6 +650,9 @@ static int aml_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, case PIN_CONFIG_OUTPUT_ENABLE: ret = aml_pinconf_set_output(info, pin, arg); break; + case PIN_CONFIG_INPUT_ENABLE: + ret = aml_pinconf_set_output(info, pin, !arg); + break; case PIN_CONFIG_LEVEL: ret = aml_pinconf_set_output_drive(info, pin, arg); break; From fa410c316520e65022ae3ea3b83bfe784dc67fd3 Mon Sep 17 00:00:00 2001 From: Xianwei Zhao Date: Wed, 12 Aug 2026 10:22:12 +0000 Subject: [PATCH 129/130] pinctrl: meson: sync some modify from A4 Set the drive strength before enabling the output to avoid enabling the output with an unintended drive strength. Also return the actual output enable state from PIN_CONFIG_OUTPUT_ENABLE instead of always reporting it as enabled. Signed-off-by: Xianwei Zhao Signed-off-by: Linus Walleij --- drivers/pinctrl/meson/pinctrl-meson.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index 4507dc8b5563..1eea3e9d1cb2 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -252,11 +252,11 @@ static int meson_pinconf_set_output_drive(struct meson_pinctrl *pc, { int ret; - ret = meson_pinconf_set_output(pc, pin, true); + ret = meson_pinconf_set_drive(pc, pin, high); if (ret) return ret; - return meson_pinconf_set_drive(pc, pin, high); + return meson_pinconf_set_output(pc, pin, true); } static int meson_pinconf_disable_bias(struct meson_pinctrl *pc, @@ -498,9 +498,9 @@ static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin, break; case PIN_CONFIG_OUTPUT_ENABLE: ret = meson_pinconf_get_output(pc, pin); - if (ret <= 0) + if (ret < 0) return -EINVAL; - arg = 1; + arg = ret; break; case PIN_CONFIG_LEVEL: ret = meson_pinconf_get_output(pc, pin); From fc301955cf09564ab52af81e6aca14ed2a2ce335 Mon Sep 17 00:00:00 2001 From: Eduard Bostina Date: Wed, 12 Aug 2026 10:36:21 +0000 Subject: [PATCH 130/130] dt-bindings: pinctrl: Convert TI DA850 pupd to DT schema Convert the Texas Instruments DA850/OMAP-L138/AM18x pullup/down controller bindings to DT schema. Signed-off-by: Eduard Bostina Reviewed-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- .../bindings/pinctrl/ti,da850-pupd.txt | 55 -------------- .../bindings/pinctrl/ti,da850-pupd.yaml | 74 +++++++++++++++++++ 2 files changed, 74 insertions(+), 55 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/ti,da850-pupd.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/ti,da850-pupd.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/ti,da850-pupd.txt b/Documentation/devicetree/bindings/pinctrl/ti,da850-pupd.txt deleted file mode 100644 index 7f2980567c9f..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/ti,da850-pupd.txt +++ /dev/null @@ -1,55 +0,0 @@ -* Pin configuration for TI DA850/OMAP-L138/AM18x - -These SoCs have a separate controller for setting bias (internal pullup/down). -Bias can only be selected for groups rather than individual pins. - -Required Properties: - - - compatible: Must be "ti,da850-pupd" - - reg: Base address and length of the memory resource used by the pullup/down - controller hardware module. - -The controller node also acts as a container for pin group configuration nodes. -The names of these groups are ignored. - -Pin Group Node Properties: - -- groups: An array of strings, each string containing the name of a pin group. - Valid names are "cp0".."cp31". - -The pin configuration parameters use the generic pinconf bindings defined in -pinctrl-bindings.txt in this directory. The supported parameters are -bias-disable, bias-pull-up, bias-pull-down. - - -Example -------- - -In common dtsi file: - - pinconf: pin-controller@22c00c { - compatible = "ti,da850-pupd"; - reg = <0x22c00c 0x8>; - }; - -In board-specific file: - - &pinconf { - pinctrl-0 = <&pinconf_bias_groups>; - pinctrl-names = "default"; - - pinconf_bias_groups: bias-groups { - pull-up { - groups = "cp30", "cp31"; - bias-pull-up; - }; - pull-down { - groups = "cp29", "cp28"; - bias-pull-down; - }; - disable { - groups = "cp27", "cp26"; - bias-disable; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/ti,da850-pupd.yaml b/Documentation/devicetree/bindings/pinctrl/ti,da850-pupd.yaml new file mode 100644 index 000000000000..21d439e08d4b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ti,da850-pupd.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ti,da850-pupd.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments DA850/OMAP-L138/AM18x Pin Configuration + +maintainers: + - Eduard Bostina + +description: + These SoCs have a separate controller for setting bias (internal pullup/down). + Bias can only be selected for groups rather than individual pins. + The controller node also acts as a container for pin group configuration nodes. + The names of these groups are ignored. + +properties: + compatible: + const: ti,da850-pupd + + reg: + maxItems: 1 + + pinctrl-0: true + pinctrl-names: true + +patternProperties: + "-groups$": + type: object + additionalProperties: false + patternProperties: + "^(disable|pull-(up|down))$": + $ref: /schemas/pinctrl/pincfg-node.yaml# + properties: + groups: + $ref: /schemas/types.yaml#/definitions/string-array + description: An array of strings containing the name of a pin group. + items: + pattern: "^cp([0-9]|[1-2][0-9]|3[0-1])$" + bias-disable: true + bias-pull-up: true + bias-pull-down: true + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinconf: pin-controller@22c00c { + compatible = "ti,da850-pupd"; + reg = <0x22c00c 0x8>; + pinctrl-0 = <&pinconf_bias_groups>; + pinctrl-names = "default"; + + pinconf_bias_groups: bias-groups { + pull-up { + groups = "cp30", "cp31"; + bias-pull-up; + }; + pull-down { + groups = "cp29", "cp28"; + bias-pull-down; + }; + disable { + groups = "cp27", "cp26"; + bias-disable; + }; + }; + };