From cb19b8a9add2ed3774c1276e0a3906e52e8cf39a Mon Sep 17 00:00:00 2001 From: "WEI-HONG, YE" <1234567weewee457@gmail.com> Date: Mon, 25 May 2026 13:04:50 +0000 Subject: [PATCH] locking/qspinlock: Clarify pending field layout For CONFIG_NR_CPUS < 16K, _Q_PENDING_BITS is 8 and the pending field occupies bits 8-15 of the lock word. The current comment documents bit 8 as pending and bits 9-15 as unused, which describes the pending flag value rather than the field layout. Describe bits 8-15 as the pending byte so the layout description is consistent with the lock byte. Signed-off-by: WEI-HONG, YE <1234567weewee457@gmail.com> Signed-off-by: Peter Zijlstra (Intel) Acked-by: Waiman Long Link: https://patch.msgid.link/20260525130450.723937-1-1234567weewee457@gmail.com --- include/asm-generic/qspinlock_types.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/asm-generic/qspinlock_types.h b/include/asm-generic/qspinlock_types.h index 2fd1fb89ec36..7d17b9bb069c 100644 --- a/include/asm-generic/qspinlock_types.h +++ b/include/asm-generic/qspinlock_types.h @@ -53,8 +53,7 @@ typedef struct qspinlock { * * When NR_CPUS < 16K * 0- 7: locked byte - * 8: pending - * 9-15: not used + * 8-15: pending byte * 16-17: tail index * 18-31: tail cpu (+1) *