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https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-intel-next-2024-02-27-1' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
drm/i915 feature pull #2 for v6.9: Features and functionality: - DP tunneling and bandwidth allocation support (Imre) - Add more ADL-N PCI IDs (Gustavo) - Enable fastboot also on older platforms (Ville) - Bigjoiner force enable debugfs option for testing (Stan) Refactoring and cleanups: - Remove unused structs and struct members (Jiri Slaby) - Use per-device debug logging (Ville) - State check improvements (Ville) - Hardcoded cd2x divider cleanups (Ville) - CDCLK documentation updates (Ville, Rodrigo) Fixes: - HDCP MST Type1 fixes (Suraj) - Fix MTL C20 PHY PLL values (Ravi) - More hardware access prevention during init (Imre) - Always enable decompression with tile4 on Xe2 (Juha-Pekka) - Improve LNL package C residency (Suraj) drm core changes: - DP tunneling and bandwidth allocation helpers (Imre) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/87sf1devbj.fsf@intel.com
This commit is contained in:
Dave Airlie
@@ -1081,6 +1081,7 @@
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# define STREAM_STATUS_CHANGED (1 << 2)
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# define HDMI_LINK_STATUS_CHANGED (1 << 3)
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# define CONNECTED_OFF_ENTRY_REQUESTED (1 << 4)
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# define DP_TUNNELING_IRQ (1 << 5)
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#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
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# define DP_PSR_LINK_CRC_ERROR (1 << 0)
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@@ -1382,6 +1383,66 @@
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#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494
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#define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518
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/* DP-tunneling */
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#define DP_TUNNELING_OUI 0xe0000
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#define DP_TUNNELING_OUI_BYTES 3
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#define DP_TUNNELING_DEV_ID 0xe0003
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#define DP_TUNNELING_DEV_ID_BYTES 6
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#define DP_TUNNELING_HW_REV 0xe0009
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#define DP_TUNNELING_HW_REV_MAJOR_SHIFT 4
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#define DP_TUNNELING_HW_REV_MAJOR_MASK (0xf << DP_TUNNELING_HW_REV_MAJOR_SHIFT)
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#define DP_TUNNELING_HW_REV_MINOR_SHIFT 0
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#define DP_TUNNELING_HW_REV_MINOR_MASK (0xf << DP_TUNNELING_HW_REV_MINOR_SHIFT)
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#define DP_TUNNELING_SW_REV_MAJOR 0xe000a
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#define DP_TUNNELING_SW_REV_MINOR 0xe000b
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#define DP_TUNNELING_CAPABILITIES 0xe000d
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#define DP_IN_BW_ALLOCATION_MODE_SUPPORT (1 << 7)
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#define DP_PANEL_REPLAY_OPTIMIZATION_SUPPORT (1 << 6)
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#define DP_TUNNELING_SUPPORT (1 << 0)
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#define DP_IN_ADAPTER_INFO 0xe000e
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#define DP_IN_ADAPTER_NUMBER_BITS 7
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#define DP_IN_ADAPTER_NUMBER_MASK ((1 << DP_IN_ADAPTER_NUMBER_BITS) - 1)
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#define DP_USB4_DRIVER_ID 0xe000f
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#define DP_USB4_DRIVER_ID_BITS 4
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#define DP_USB4_DRIVER_ID_MASK ((1 << DP_USB4_DRIVER_ID_BITS) - 1)
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#define DP_USB4_DRIVER_BW_CAPABILITY 0xe0020
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#define DP_USB4_DRIVER_BW_ALLOCATION_MODE_SUPPORT (1 << 7)
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#define DP_IN_ADAPTER_TUNNEL_INFORMATION 0xe0021
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#define DP_GROUP_ID_BITS 3
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#define DP_GROUP_ID_MASK ((1 << DP_GROUP_ID_BITS) - 1)
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#define DP_BW_GRANULARITY 0xe0022
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#define DP_BW_GRANULARITY_MASK 0x3
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#define DP_ESTIMATED_BW 0xe0023
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#define DP_ALLOCATED_BW 0xe0024
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#define DP_TUNNELING_STATUS 0xe0025
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#define DP_BW_ALLOCATION_CAPABILITY_CHANGED (1 << 3)
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#define DP_ESTIMATED_BW_CHANGED (1 << 2)
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#define DP_BW_REQUEST_SUCCEEDED (1 << 1)
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#define DP_BW_REQUEST_FAILED (1 << 0)
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#define DP_TUNNELING_MAX_LINK_RATE 0xe0028
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#define DP_TUNNELING_MAX_LANE_COUNT 0xe0029
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#define DP_TUNNELING_MAX_LANE_COUNT_MASK 0x1f
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#define DP_DPTX_BW_ALLOCATION_MODE_CONTROL 0xe0030
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#define DP_DISPLAY_DRIVER_BW_ALLOCATION_MODE_ENABLE (1 << 7)
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#define DP_UNMASK_BW_ALLOCATION_IRQ (1 << 6)
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#define DP_REQUEST_BW 0xe0031
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#define MAX_DP_REQUEST_BW 255
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/* LTTPR: Link Training (LT)-tunable PHY Repeaters */
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#define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */
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#define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */
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@@ -811,5 +811,6 @@ int drm_dp_bw_overhead(int lane_count, int hactive,
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int dsc_slice_count,
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int bpp_x16, unsigned long flags);
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int drm_dp_bw_channel_coding_efficiency(bool is_uhbr);
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int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes);
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#endif /* _DRM_DP_HELPER_H_ */
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248
include/drm/display/drm_dp_tunnel.h
Normal file
248
include/drm/display/drm_dp_tunnel.h
Normal file
@@ -0,0 +1,248 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef __DRM_DP_TUNNEL_H__
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#define __DRM_DP_TUNNEL_H__
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/types.h>
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struct drm_dp_aux;
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struct drm_device;
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struct drm_atomic_state;
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struct drm_dp_tunnel_mgr;
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struct drm_dp_tunnel_state;
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struct ref_tracker;
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struct drm_dp_tunnel_ref {
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struct drm_dp_tunnel *tunnel;
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struct ref_tracker *tracker;
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};
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#ifdef CONFIG_DRM_DISPLAY_DP_TUNNEL
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struct drm_dp_tunnel *
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drm_dp_tunnel_get(struct drm_dp_tunnel *tunnel, struct ref_tracker **tracker);
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void
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drm_dp_tunnel_put(struct drm_dp_tunnel *tunnel, struct ref_tracker **tracker);
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static inline void drm_dp_tunnel_ref_get(struct drm_dp_tunnel *tunnel,
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struct drm_dp_tunnel_ref *tunnel_ref)
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{
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tunnel_ref->tunnel = drm_dp_tunnel_get(tunnel, &tunnel_ref->tracker);
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}
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static inline void drm_dp_tunnel_ref_put(struct drm_dp_tunnel_ref *tunnel_ref)
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{
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drm_dp_tunnel_put(tunnel_ref->tunnel, &tunnel_ref->tracker);
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tunnel_ref->tunnel = NULL;
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}
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struct drm_dp_tunnel *
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drm_dp_tunnel_detect(struct drm_dp_tunnel_mgr *mgr,
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struct drm_dp_aux *aux);
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int drm_dp_tunnel_destroy(struct drm_dp_tunnel *tunnel);
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int drm_dp_tunnel_enable_bw_alloc(struct drm_dp_tunnel *tunnel);
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int drm_dp_tunnel_disable_bw_alloc(struct drm_dp_tunnel *tunnel);
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bool drm_dp_tunnel_bw_alloc_is_enabled(const struct drm_dp_tunnel *tunnel);
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int drm_dp_tunnel_alloc_bw(struct drm_dp_tunnel *tunnel, int bw);
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int drm_dp_tunnel_get_allocated_bw(struct drm_dp_tunnel *tunnel);
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int drm_dp_tunnel_update_state(struct drm_dp_tunnel *tunnel);
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void drm_dp_tunnel_set_io_error(struct drm_dp_tunnel *tunnel);
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int drm_dp_tunnel_handle_irq(struct drm_dp_tunnel_mgr *mgr,
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struct drm_dp_aux *aux);
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int drm_dp_tunnel_max_dprx_rate(const struct drm_dp_tunnel *tunnel);
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int drm_dp_tunnel_max_dprx_lane_count(const struct drm_dp_tunnel *tunnel);
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int drm_dp_tunnel_available_bw(const struct drm_dp_tunnel *tunnel);
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const char *drm_dp_tunnel_name(const struct drm_dp_tunnel *tunnel);
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struct drm_dp_tunnel_state *
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drm_dp_tunnel_atomic_get_state(struct drm_atomic_state *state,
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struct drm_dp_tunnel *tunnel);
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struct drm_dp_tunnel_state *
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drm_dp_tunnel_atomic_get_old_state(struct drm_atomic_state *state,
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const struct drm_dp_tunnel *tunnel);
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struct drm_dp_tunnel_state *
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drm_dp_tunnel_atomic_get_new_state(struct drm_atomic_state *state,
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const struct drm_dp_tunnel *tunnel);
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int drm_dp_tunnel_atomic_set_stream_bw(struct drm_atomic_state *state,
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struct drm_dp_tunnel *tunnel,
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u8 stream_id, int bw);
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int drm_dp_tunnel_atomic_get_group_streams_in_state(struct drm_atomic_state *state,
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const struct drm_dp_tunnel *tunnel,
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u32 *stream_mask);
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int drm_dp_tunnel_atomic_check_stream_bws(struct drm_atomic_state *state,
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u32 *failed_stream_mask);
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int drm_dp_tunnel_atomic_get_required_bw(const struct drm_dp_tunnel_state *tunnel_state);
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struct drm_dp_tunnel_mgr *
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drm_dp_tunnel_mgr_create(struct drm_device *dev, int max_group_count);
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void drm_dp_tunnel_mgr_destroy(struct drm_dp_tunnel_mgr *mgr);
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#else
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static inline struct drm_dp_tunnel *
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drm_dp_tunnel_get(struct drm_dp_tunnel *tunnel, struct ref_tracker **tracker)
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{
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return NULL;
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}
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static inline void
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drm_dp_tunnel_put(struct drm_dp_tunnel *tunnel, struct ref_tracker **tracker) {}
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static inline void drm_dp_tunnel_ref_get(struct drm_dp_tunnel *tunnel,
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struct drm_dp_tunnel_ref *tunnel_ref) {}
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static inline void drm_dp_tunnel_ref_put(struct drm_dp_tunnel_ref *tunnel_ref) {}
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static inline struct drm_dp_tunnel *
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drm_dp_tunnel_detect(struct drm_dp_tunnel_mgr *mgr,
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struct drm_dp_aux *aux)
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{
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return ERR_PTR(-EOPNOTSUPP);
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}
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static inline int
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drm_dp_tunnel_destroy(struct drm_dp_tunnel *tunnel)
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{
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return 0;
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}
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static inline int drm_dp_tunnel_enable_bw_alloc(struct drm_dp_tunnel *tunnel)
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{
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return -EOPNOTSUPP;
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}
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static inline int drm_dp_tunnel_disable_bw_alloc(struct drm_dp_tunnel *tunnel)
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{
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return -EOPNOTSUPP;
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}
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static inline bool drm_dp_tunnel_bw_alloc_is_enabled(const struct drm_dp_tunnel *tunnel)
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{
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return false;
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}
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static inline int
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drm_dp_tunnel_alloc_bw(struct drm_dp_tunnel *tunnel, int bw)
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{
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return -EOPNOTSUPP;
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}
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static inline int
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drm_dp_tunnel_get_allocated_bw(struct drm_dp_tunnel *tunnel)
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{
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return -1;
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}
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static inline int
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drm_dp_tunnel_update_state(struct drm_dp_tunnel *tunnel)
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{
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return -EOPNOTSUPP;
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}
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static inline void drm_dp_tunnel_set_io_error(struct drm_dp_tunnel *tunnel) {}
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static inline int
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drm_dp_tunnel_handle_irq(struct drm_dp_tunnel_mgr *mgr,
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struct drm_dp_aux *aux)
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{
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return -EOPNOTSUPP;
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}
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static inline int
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drm_dp_tunnel_max_dprx_rate(const struct drm_dp_tunnel *tunnel)
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{
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return 0;
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}
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static inline int
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drm_dp_tunnel_max_dprx_lane_count(const struct drm_dp_tunnel *tunnel)
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{
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return 0;
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}
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static inline int
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drm_dp_tunnel_available_bw(const struct drm_dp_tunnel *tunnel)
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{
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return -1;
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}
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static inline const char *
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drm_dp_tunnel_name(const struct drm_dp_tunnel *tunnel)
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{
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return NULL;
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}
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static inline struct drm_dp_tunnel_state *
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drm_dp_tunnel_atomic_get_state(struct drm_atomic_state *state,
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struct drm_dp_tunnel *tunnel)
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{
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return ERR_PTR(-EOPNOTSUPP);
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}
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static inline struct drm_dp_tunnel_state *
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drm_dp_tunnel_atomic_get_new_state(struct drm_atomic_state *state,
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const struct drm_dp_tunnel *tunnel)
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{
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return ERR_PTR(-EOPNOTSUPP);
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}
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static inline int
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drm_dp_tunnel_atomic_set_stream_bw(struct drm_atomic_state *state,
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struct drm_dp_tunnel *tunnel,
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u8 stream_id, int bw)
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{
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return -EOPNOTSUPP;
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}
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static inline int
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drm_dp_tunnel_atomic_get_group_streams_in_state(struct drm_atomic_state *state,
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const struct drm_dp_tunnel *tunnel,
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u32 *stream_mask)
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{
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return -EOPNOTSUPP;
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}
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static inline int
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drm_dp_tunnel_atomic_check_stream_bws(struct drm_atomic_state *state,
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u32 *failed_stream_mask)
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{
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return -EOPNOTSUPP;
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}
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static inline int
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drm_dp_tunnel_atomic_get_required_bw(const struct drm_dp_tunnel_state *tunnel_state)
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{
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return 0;
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}
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static inline struct drm_dp_tunnel_mgr *
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drm_dp_tunnel_mgr_create(struct drm_device *dev, int max_group_count)
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{
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return ERR_PTR(-EOPNOTSUPP);
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}
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static inline
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void drm_dp_tunnel_mgr_destroy(struct drm_dp_tunnel_mgr *mgr) {}
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#endif /* CONFIG_DRM_DISPLAY_DP_TUNNEL */
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#endif /* __DRM_DP_TUNNEL_H__ */
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@@ -672,7 +672,9 @@
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#define INTEL_ADLN_IDS(info) \
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INTEL_VGA_DEVICE(0x46D0, info), \
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INTEL_VGA_DEVICE(0x46D1, info), \
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INTEL_VGA_DEVICE(0x46D2, info)
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INTEL_VGA_DEVICE(0x46D2, info), \
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INTEL_VGA_DEVICE(0x46D3, info), \
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INTEL_VGA_DEVICE(0x46D4, info)
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/* RPL-S */
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#define INTEL_RPLS_IDS(info) \
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