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Merge tag 'drm-next-2023-04-24' of git://anongit.freedesktop.org/drm/drm

Browse Source 
Pull drm updates from Dave Airlie:
 "There is a new Qualcomm accel driver for their QAIC, dma-fence got a
  deadline feature added, lots of refactoring around fbdev emulation,
  and the usual pre-release hw enablements from AMD and Intel and fixes
  everywhere.

  New drivers:
   - add QAIC acceleration driver

  dma-buf:
   - constify kobj_type structs
   - Reject prime DMA-Buf attachment if get_sg_table is missing.

  fbdev:
   - cmdline parser fixes
   - implement fbdev emulation for GEM DMA drivers
   - always use shadow buffer in fbdev emulation helpers

  dma-fence:
   - add deadline hint to fences
   - signal private stub fence

  core:
   - improve DisplayID 2.0 and EDID parsing
   - add gem eviction function + callback
   - prep to convert shmem helper to GEM resv lock
   - move suballocator from radeon/amdgpu to core for Xe
   - HPD polling fixes
   - Documentation improvements
   - Add atomic enable_plane callback
   - use tgid instead of pid for client tracking
   - DP: Add SDP Error Detection Configuration Register
   - Add prime import/export to vram-helper
   - use pci aperture helpers in more drivers

  panel:
   - Radxa 8/10HD support
   - Samsung AMD495QA01 support
   - Elida KD50T048A
   - Sony TD4353
   - Novatek NT36523
   - STARRY 2081101QFH032011-53G
   - B133UAN01.0
   - AUO NE135FBM-N41

  i915:
   - More MTL enabling
   - fix s/r problems with MEI/PXP
   - Implement fb_dirty for PSR,FBC,DRRS fixes
   - Fix eDP+DSI dual panel systems
   - Fix issue #6333: "list_add corruption" and full system lockup from
     performance monitoring
   - Don't use stolen memory or BAR for ring buffers on LLC platforms
   - Make sure DSM size has correct 1MiB granularity on Gen12+
   - Whitelist COMMON_SLICE_CHICKEN3 for UMD access on Gen12+
   - Add engine TLB invalidation for Meteorlake
   - Fix GSC races on driver load/unload on Meteorlake+
   - Make kobj_type structures constant
   - Move fd_install after last use of fence
   - wm/vblank refactoring
   - display code refactoring
   - Create GSC submission targeting HDCP and PXP usages on MTL+
   - Enable HDCP2.x via GSC CS
   - Fix context runtime accounting on sysfs fdinfo for heavy workloads
   - Use i915 instead of dev_priv insied the file_priv structure
   - Replace fake flex-array with flexible-array member

  amdgpu:
   - Make kobj structures const
   - Generalize dmabuf import to work with KFD
   - Add capped/uncapped workload handling for supported APUs
   - Expose additional memory stats via fdinfo
   - Register vga_switcheroo for apple-gmux
   - Initial NBIO7.9, GC 9.4.3, GFXHUB 1.2, MMHUB 1.8 support
   - Initial DC FAM infrastructure
   - Link DC backlight to connector device rather than PCI device
   - Add sysfs nodes for secondary VCN clocks

  amdkfd:
   - Make kobj structures const
   - Support for exporting buffers via dmabuf
   - Multi-VMA page migration fixes
   - initial GC 9.4.3 support

  radeon:
   - iMac fix
   - convert to client based fbdev emulation

  habanalabs:
   - Add opcodes to the CS ioctl to allow user to stall/resume specific
     engines inside Gaudi2.
   - INFO ioctl the amount of device memory that the driver and f/w
     reserve for themselves.
   - INFO ioctl a bit-mask of the available rotator engines
   - INFO ioctl the register's address of the f/w that should be used to
     trigger interrupts
   - INFO ioctl two new opcodes to fetch information on h/w and f/w
     events
   - Enable graceful reset mechanism for compute-reset.
   - Align to the latest firmware specs.
   - Enforce the release order of the compute device and dma-buf.

  msm:
   - UBWC decoder programming rework
   - SM8550, SM8450 bindings update
   - uapi C++ fix
   - a3xx and a4xx devfreq support
   - GPU and GEM updates to avoid allocations which could trigger
     reclaim (shrinker) in fence signaling path
   - dma-fence deadline hint support and wait-boost
   - a640/650 speed bin support

  cirrus:
   - convert to regular atomic helpers
   - add damage clipping

  mediatek:
   - 10-bit overlay support
   - mt8195 support
   - Only trigger DRM HPD events if bridge is attached
   - Change the aux retries times when receiving AUX_DEFER

  rockchip:
   - add 4K support

  vc4:
   - use drm_gem_objects

  virtio:
   - allow KMS support to be disabled
   - add damage clipping

  vmwgfx:
   - buffer object lifetime fixes

  exynos:
   - move MIPI DSI driver to drm bridge for iMX sharing
   - use kernel fbdev emulation

  panfrost:
   - add support for mali MT81xx devices
   - add speed binning support

  lima:
   - add usage stats

  tegra:
   - fbdev client conversion

  vkms:
   - Add primary plane positioning support"

* tag 'drm-next-2023-04-24' of git://anongit.freedesktop.org/drm/drm: (1495 commits)
  drm/i915/dp_mst: Fix active port PLL selection for secondary MST streams
  drm/exynos: Implement fbdev emulation as in-kernel client
  drm/exynos: Initialize fbdev DRM client
  drm/exynos: Remove fb_helper from struct exynos_drm_private
  drm/exynos: Remove struct exynos_drm_fbdev
  drm/exynos: Remove exynos_gem from struct exynos_drm_fbdev
  drm/i915: Fix memory leaks in i915 selftests
  drm/i915: Make intel_get_crtc_new_encoder() less oopsy
  drm/i915/gt: Avoid out-of-bounds access when loading HuC
  drm/amdgpu: add some basic elements for multiple XCD case
  drm/amdgpu: move vmhub out of amdgpu_ring_funcs (v4)
  Revert "drm/amdgpu: enable ras for mp0 v13_0_10 on SRIOV"
  drm/amdgpu: add common ip block for GC 9.4.3
  drm/amd/display: Add logging when DP link training Clock recovery is Successful
  drm/amdgpu: add common early init support for GC 9.4.3
  drm/amdgpu: switch to v9_4_3 gfx_funcs callbacks for GC 9.4.3
  drm/amd/display: Add logging when setting DP sink power state fails
  drm/amdkfd: Add gfx_target_version for GC 9.4.3
  drm/amdkfd: Enable HW_UPDATE_RPTR on GC 9.4.3
  drm/amdgpu: reserve the old gc_11_0_*_mes.bin
  ...
This commit is contained in:
Linus Torvalds
2023-04-25 16:12:15 -07:00
parent 736b378b29 289af45508
commit c8cc58e289
1192 changed files with 183422 additions and 30711 deletions
Download Patch File Download Diff File Expand all files Collapse all files

115
include/drm/bridge/samsung-dsim.h Normal file
View File

@@ -0,0 +1,115 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2022 Amarula Solutions(India)
* Author: Jagan Teki <jagan@amarulasolutions.com>
*/
#ifndef __SAMSUNG_DSIM__
#define __SAMSUNG_DSIM__
#include <linux/gpio/consumer.h>
#include <linux/regulator/consumer.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_of.h>
#include <drm/drm_mipi_dsi.h>
struct samsung_dsim;
#define DSIM_STATE_ENABLED BIT(0)
#define DSIM_STATE_INITIALIZED BIT(1)
#define DSIM_STATE_CMD_LPM BIT(2)
#define DSIM_STATE_VIDOUT_AVAILABLE BIT(3)
enum samsung_dsim_type {
DSIM_TYPE_EXYNOS3250,
DSIM_TYPE_EXYNOS4210,
DSIM_TYPE_EXYNOS5410,
DSIM_TYPE_EXYNOS5422,
DSIM_TYPE_EXYNOS5433,
DSIM_TYPE_IMX8MM,
DSIM_TYPE_IMX8MP,
DSIM_TYPE_COUNT,
};
#define samsung_dsim_hw_is_exynos(hw) \
((hw) >= DSIM_TYPE_EXYNOS3250 && (hw) <= DSIM_TYPE_EXYNOS5433)
struct samsung_dsim_transfer {
struct list_head list;
struct completion completed;
int result;
struct mipi_dsi_packet packet;
u16 flags;
u16 tx_done;
u8 *rx_payload;
u16 rx_len;
u16 rx_done;
};
struct samsung_dsim_driver_data {
const unsigned int *reg_ofs;
unsigned int plltmr_reg;
unsigned int has_freqband:1;
unsigned int has_clklane_stop:1;
unsigned int num_clks;
unsigned int max_freq;
unsigned int wait_for_reset;
unsigned int num_bits_resol;
unsigned int pll_p_offset;
const unsigned int *reg_values;
};
struct samsung_dsim_host_ops {
int (*register_host)(struct samsung_dsim *dsim);
void (*unregister_host)(struct samsung_dsim *dsim);
int (*attach)(struct samsung_dsim *dsim, struct mipi_dsi_device *device);
void (*detach)(struct samsung_dsim *dsim, struct mipi_dsi_device *device);
irqreturn_t (*te_irq_handler)(struct samsung_dsim *dsim);
};
struct samsung_dsim_plat_data {
enum samsung_dsim_type hw_type;
const struct samsung_dsim_host_ops *host_ops;
};
struct samsung_dsim {
struct mipi_dsi_host dsi_host;
struct drm_bridge bridge;
struct drm_bridge *out_bridge;
struct device *dev;
struct drm_display_mode mode;
void __iomem *reg_base;
struct phy *phy;
struct clk **clks;
struct regulator_bulk_data supplies[2];
int irq;
struct gpio_desc *te_gpio;
u32 pll_clk_rate;
u32 burst_clk_rate;
u32 esc_clk_rate;
u32 lanes;
u32 mode_flags;
u32 format;
int state;
struct drm_property *brightness;
struct completion completed;
spinlock_t transfer_lock; /* protects transfer_list */
struct list_head transfer_list;
const struct samsung_dsim_driver_data *driver_data;
const struct samsung_dsim_plat_data *plat_data;
void *priv;
};
extern int samsung_dsim_probe(struct platform_device *pdev);
extern int samsung_dsim_remove(struct platform_device *pdev);
extern const struct dev_pm_ops samsung_dsim_pm_ops;
#endif /* __SAMSUNG_DSIM__ */

3
include/drm/display/drm_dp.h
View File

@@ -692,6 +692,9 @@
# define DP_FEC_LANE_2_SELECT (2 << 4)
# define DP_FEC_LANE_3_SELECT (3 << 4)
#define DP_SDP_ERROR_DETECTION_CONFIGURATION 0x121 /* DP 2.0 E11 */
#define DP_SDP_CRC16_128B132B_EN BIT(0)
#define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
# define DP_AUX_FRAME_SYNC_VALID (1 << 0)

13
include/drm/display/drm_dp_helper.h
View File

@@ -194,6 +194,19 @@ drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
DP_DSC_SLICE_WIDTH_MULTIPLIER;
}
/**
* drm_dp_dsc_sink_supports_format() - check if sink supports DSC with given output format
* @dsc_dpcd : DSC-capability DPCDs of the sink
* @output_format: output_format which is to be checked
*
* Returns true if the sink supports DSC with the given output_format, false otherwise.
*/
static inline bool
drm_dp_dsc_sink_supports_format(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 output_format)
{
return dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & output_format;
}
/* Forward Error Correction Support on DP 1.4 */
static inline bool
drm_dp_sink_supports_fec(const u8 fec_capable)

7
include/drm/display/drm_scdc_helper.h
View File

@@ -28,6 +28,7 @@
#include <drm/display/drm_scdc.h>
struct drm_connector;
struct i2c_adapter;
ssize_t drm_scdc_read(struct i2c_adapter *adapter, u8 offset, void *buffer,
@@ -71,9 +72,9 @@ static inline int drm_scdc_writeb(struct i2c_adapter *adapter, u8 offset,
return drm_scdc_write(adapter, offset, &value, sizeof(value));
}
bool drm_scdc_get_scrambling_status(struct i2c_adapter *adapter);
bool drm_scdc_get_scrambling_status(struct drm_connector *connector);
bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable);
bool drm_scdc_set_high_tmds_clock_ratio(struct i2c_adapter *adapter, bool set);
bool drm_scdc_set_scrambling(struct drm_connector *connector, bool enable);
bool drm_scdc_set_high_tmds_clock_ratio(struct drm_connector *connector, bool set);
#endif

7
include/drm/drm_atomic.h
View File

@@ -528,6 +528,13 @@ struct drm_connector *
drm_atomic_get_new_connector_for_encoder(const struct drm_atomic_state *state,
struct drm_encoder *encoder);
struct drm_crtc *
drm_atomic_get_old_crtc_for_encoder(struct drm_atomic_state *state,
struct drm_encoder *encoder);
struct drm_crtc *
drm_atomic_get_new_crtc_for_encoder(struct drm_atomic_state *state,
struct drm_encoder *encoder);
/**
* drm_atomic_get_existing_crtc_state - get CRTC state, if it exists
* @state: global atomic state object

26
include/drm/drm_atomic_helper.h
View File

@@ -209,6 +209,32 @@ int drm_atomic_helper_page_flip_target(
__drm_atomic_get_current_plane_state((crtc_state)->state, \
plane)))
/**
* drm_atomic_plane_enabling - check whether a plane is being enabled
* @old_plane_state: old atomic plane state
* @new_plane_state: new atomic plane state
*
* Checks the atomic state of a plane to determine whether it's being enabled
* or not. This also WARNs if it detects an invalid state (both CRTC and FB
* need to either both be NULL or both be non-NULL).
*
* RETURNS:
* True if the plane is being enabled, false otherwise.
*/
static inline bool drm_atomic_plane_enabling(struct drm_plane_state *old_plane_state,
struct drm_plane_state *new_plane_state)
{
/*
* When enabling a plane, CRTC and FB should always be set together.
* Anything else should be considered a bug in the atomic core, so we
* gently warn about it.
*/
WARN_ON((!new_plane_state->crtc && new_plane_state->fb) ||
(new_plane_state->crtc && !new_plane_state->fb));
return !old_plane_state->crtc && new_plane_state->crtc;
}
/**
* drm_atomic_plane_disabling - check whether a plane is being disabled
* @old_plane_state: old atomic plane state

12
include/drm/drm_displayid.h
View File

@@ -139,7 +139,11 @@ struct displayid_vesa_vendor_specific_block {
u8 mso;
} __packed;
/* DisplayID iteration */
/*
* DisplayID iteration.
*
* Do not access directly, this is private.
*/
struct displayid_iter {
const struct drm_edid *drm_edid;
@@ -147,6 +151,9 @@ struct displayid_iter {
int length;
int idx;
int ext_index;
u8 version;
u8 primary_use;
};
void displayid_iter_edid_begin(const struct drm_edid *drm_edid,
@@ -157,4 +164,7 @@ __displayid_iter_next(struct displayid_iter *iter);
while (((__block) = __displayid_iter_next(__iter)))
void displayid_iter_end(struct displayid_iter *iter);
u8 displayid_version(const struct displayid_iter *iter);
u8 displayid_primary_use(const struct displayid_iter *iter);
#endif

21
include/drm/drm_drv.h
View File

@@ -400,25 +400,6 @@ struct drm_driver {
int (*dumb_map_offset)(struct drm_file *file_priv,
struct drm_device *dev, uint32_t handle,
uint64_t *offset);
/**
* @dumb_destroy:
*
* This destroys the userspace handle for the given dumb backing storage buffer.
* Since buffer objects must be reference counted in the kernel a buffer object
* won't be immediately freed if a framebuffer modeset object still uses it.
*
* Called by the user via ioctl.
*
* The default implementation is drm_gem_dumb_destroy(). GEM based drivers
* must not overwrite this.
*
* Returns:
*
* Zero on success, negative errno on failure.
*/
int (*dumb_destroy)(struct drm_file *file_priv,
struct drm_device *dev,
uint32_t handle);
/** @major: driver major number */
int major;
@@ -603,8 +584,6 @@ static inline bool drm_drv_uses_atomic_modeset(struct drm_device *dev)
}
int drm_dev_set_unique(struct drm_device *dev, const char *name);
/* TODO: Inline drm_firmware_drivers_only() in all its callers. */
static inline bool drm_firmware_drivers_only(void)
{

12
include/drm/drm_edid.h
View File

@@ -61,9 +61,15 @@ struct std_timing {
u8 vfreq_aspect;
} __attribute__((packed));
#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
#define DRM_EDID_PT_SEPARATE_SYNC (3 << 3)
#define DRM_EDID_PT_SYNC_MASK (3 << 3)
# define DRM_EDID_PT_ANALOG_CSYNC (0 << 3)
# define DRM_EDID_PT_BIPOLAR_ANALOG_CSYNC (1 << 3)
# define DRM_EDID_PT_DIGITAL_CSYNC (2 << 3)
# define DRM_EDID_PT_CSYNC_ON_RGB (1 << 1) /* analog csync only */
# define DRM_EDID_PT_CSYNC_SERRATE (1 << 2)
# define DRM_EDID_PT_DIGITAL_SEPARATE_SYNC (3 << 3)
# define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) /* also digital csync */
# define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
#define DRM_EDID_PT_STEREO (1 << 5)
#define DRM_EDID_PT_INTERLACED (1 << 7)

14
include/drm/drm_fb_helper.h
View File

@@ -195,15 +195,6 @@ struct drm_fb_helper {
*/
int preferred_bpp;
/**
* @hint_leak_smem_start:
*
* Hint to the fbdev emulation to store the framebuffer's physical
* address in struct &fb_info.fix.smem_start. If the hint is unset,
* the smem_start field should always be cleared to zero.
*/
bool hint_leak_smem_start;
#ifdef CONFIG_FB_DEFERRED_IO
/**
* @fbdefio:
@@ -256,6 +247,7 @@ int drm_fb_helper_check_var(struct fb_var_screeninfo *var,
int drm_fb_helper_restore_fbdev_mode_unlocked(struct drm_fb_helper *fb_helper);
struct fb_info *drm_fb_helper_alloc_info(struct drm_fb_helper *fb_helper);
void drm_fb_helper_release_info(struct drm_fb_helper *fb_helper);
void drm_fb_helper_unregister_info(struct drm_fb_helper *fb_helper);
void drm_fb_helper_fill_info(struct fb_info *info,
struct drm_fb_helper *fb_helper,
@@ -365,6 +357,10 @@ drm_fb_helper_alloc_info(struct drm_fb_helper *fb_helper)
return NULL;
}
static inline void drm_fb_helper_release_info(struct drm_fb_helper *fb_helper)
{
}
static inline void drm_fb_helper_unregister_info(struct drm_fb_helper *fb_helper)
{
}

15
include/drm/drm_fbdev_dma.h Normal file
View File

@@ -0,0 +1,15 @@
/* SPDX-License-Identifier: MIT */
#ifndef DRM_FBDEV_DMA_H
#define DRM_FBDEV_DMA_H
struct drm_device;
#ifdef CONFIG_DRM_FBDEV_EMULATION
void drm_fbdev_dma_setup(struct drm_device *dev, unsigned int preferred_bpp);
#else
static inline void drm_fbdev_dma_setup(struct drm_device *dev, unsigned int preferred_bpp)
{ }
#endif
#endif

3
include/drm/drm_file.h
View File

@@ -408,7 +408,8 @@ static inline bool drm_is_render_client(const struct drm_file *file_priv)
* Returns true if this is an open file of the compute acceleration node, i.e.
* &drm_file.minor of @file_priv is a accel minor.
*
* See also the :ref:`section on accel nodes <drm_accel_node>`.
* See also :doc:`Introduction to compute accelerators subsystem
* </accel/introduction>`.
*/
static inline bool drm_is_accel_client(const struct drm_file *file_priv)
{

13
include/drm/drm_gem.h
View File

@@ -164,6 +164,16 @@ struct drm_gem_object_funcs {
*/
int (*mmap)(struct drm_gem_object *obj, struct vm_area_struct *vma);
/**
* @evict:
*
* Evicts gem object out from memory. Used by the drm_gem_object_evict()
* helper. Returns 0 on success, -errno otherwise.
*
* This callback is optional.
*/
int (*evict)(struct drm_gem_object *obj);
/**
* @vm_ops:
*
@@ -475,10 +485,13 @@ int drm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
void drm_gem_lru_init(struct drm_gem_lru *lru, struct mutex *lock);
void drm_gem_lru_remove(struct drm_gem_object *obj);
void drm_gem_lru_move_tail_locked(struct drm_gem_lru *lru, struct drm_gem_object *obj);
void drm_gem_lru_move_tail(struct drm_gem_lru *lru, struct drm_gem_object *obj);
unsigned long drm_gem_lru_scan(struct drm_gem_lru *lru,
unsigned int nr_to_scan,
unsigned long *remaining,
bool (*shrink)(struct drm_gem_object *obj));
int drm_gem_evict(struct drm_gem_object *obj);
#endif /* __DRM_GEM_H__ */

30
include/drm/drm_gem_shmem_helper.h
View File

@@ -60,20 +60,6 @@ struct drm_gem_shmem_object {
*/
struct list_head madv_list;
/**
* @pages_mark_dirty_on_put:
*
* Mark pages as dirty when they are put.
*/
unsigned int pages_mark_dirty_on_put : 1;
/**
* @pages_mark_accessed_on_put:
*
* Mark pages as accessed when they are put.
*/
unsigned int pages_mark_accessed_on_put : 1;
/**
* @sgt: Scatter/gather table for imported PRIME buffers
*/
@@ -97,10 +83,24 @@ struct drm_gem_shmem_object {
*/
unsigned int vmap_use_count;
/**
* @pages_mark_dirty_on_put:
*
* Mark pages as dirty when they are put.
*/
bool pages_mark_dirty_on_put : 1;
/**
* @pages_mark_accessed_on_put:
*
* Mark pages as accessed when they are put.
*/
bool pages_mark_accessed_on_put : 1;
/**
* @map_wc: map object write-combined (instead of using shmem defaults).
*/
bool map_wc;
bool map_wc : 1;
};
#define to_drm_gem_shmem_obj(obj) \

4
include/drm/drm_gem_vram_helper.h
View File

@@ -160,7 +160,9 @@ void drm_gem_vram_simple_display_pipe_cleanup_fb(
.debugfs_init = drm_vram_mm_debugfs_init, \
.dumb_create = drm_gem_vram_driver_dumb_create, \
.dumb_map_offset = drm_gem_ttm_dumb_map_offset, \
.gem_prime_mmap = drm_gem_prime_mmap
.gem_prime_mmap = drm_gem_prime_mmap, \
.prime_handle_to_fd = drm_gem_prime_handle_to_fd, \
.prime_fd_to_handle = drm_gem_prime_fd_to_handle
/*
* VRAM memory manager

7
include/drm/drm_mode_config.h
View File

@@ -890,13 +890,6 @@ struct drm_mode_config {
/* dumb ioctl parameters */
uint32_t preferred_depth, prefer_shadow;
/**
* @prefer_shadow_fbdev:
*
* Hint to framebuffer emulation to prefer shadow-fb rendering.
*/
bool prefer_shadow_fbdev;
/**
* @quirk_addfb_prefer_xbgr_30bpp:
*

29
include/drm/drm_modeset_helper_vtables.h
View File

@@ -1331,6 +1331,32 @@ struct drm_plane_helper_funcs {
*/
void (*atomic_update)(struct drm_plane *plane,
struct drm_atomic_state *state);
/**
* @atomic_enable:
*
* Drivers should use this function to unconditionally enable a plane.
* This hook is called in-between the &drm_crtc_helper_funcs.atomic_begin
* and drm_crtc_helper_funcs.atomic_flush callbacks. It is called after
* @atomic_update, which will be called for all enabled planes. Drivers
* that use @atomic_enable should set up a plane in @atomic_update and
* afterwards enable the plane in @atomic_enable. If a plane needs to be
* enabled before installing the scanout buffer, drivers can still do
* so in @atomic_update.
*
* Note that the power state of the display pipe when this function is
* called depends upon the exact helpers and calling sequence the driver
* has picked. See drm_atomic_helper_commit_planes() for a discussion of
* the tradeoffs and variants of plane commit helpers.
*
* This callback is used by the atomic modeset helpers, but it is
* optional. If implemented, @atomic_enable should be the inverse of
* @atomic_disable. Drivers that don't want to use either can still
* implement the complete plane update in @atomic_update.
*/
void (*atomic_enable)(struct drm_plane *plane,
struct drm_atomic_state *state);
/**
* @atomic_disable:
*
@@ -1351,7 +1377,8 @@ struct drm_plane_helper_funcs {
* the tradeoffs and variants of plane commit helpers.
*
* This callback is used by the atomic modeset helpers and by the
* transitional plane helpers, but it is optional.
* transitional plane helpers, but it is optional. It's intended to
* reverse the effects of @atomic_enable.
*/
void (*atomic_disable)(struct drm_plane *plane,
struct drm_atomic_state *state);

12
include/drm/drm_of.h
View File

@@ -15,6 +15,8 @@ struct drm_encoder;
struct drm_panel;
struct drm_bridge;
struct device_node;
struct mipi_dsi_device_info;
struct mipi_dsi_host;
/**
* enum drm_lvds_dual_link_pixels - Pixel order of an LVDS dual-link connection
@@ -129,6 +131,16 @@ drm_of_get_data_lanes_count_ep(const struct device_node *port,
}
#endif
#if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DRM_MIPI_DSI)
struct mipi_dsi_host *drm_of_get_dsi_bus(struct device *dev);
#else
static inline struct
mipi_dsi_host *drm_of_get_dsi_bus(struct device *dev)
{
return ERR_PTR(-EINVAL);
}
#endif /* CONFIG_OF && CONFIG_DRM_MIPI_DSI */
/*
* drm_of_panel_bridge_remove - remove panel bridge
* @np: device tree node containing panel bridge output ports

108
include/drm/drm_suballoc.h Normal file
View File

@@ -0,0 +1,108 @@
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
* Copyright 2011 Red Hat Inc.
* Copyright © 2022 Intel Corporation
*/
#ifndef _DRM_SUBALLOC_H_
#define _DRM_SUBALLOC_H_
#include <drm/drm_mm.h>
#include <linux/dma-fence.h>
#include <linux/types.h>
#define DRM_SUBALLOC_MAX_QUEUES 32
/**
* struct drm_suballoc_manager - fenced range allocations
* @wq: Wait queue for sleeping allocations on contention.
* @hole: Pointer to first hole node.
* @olist: List of allocated ranges.
* @flist: Array[fence context hash] of queues of fenced allocated ranges.
* @size: Size of the managed range.
* @align: Default alignment for the managed range.
*/
struct drm_suballoc_manager {
wait_queue_head_t wq;
struct list_head *hole;
struct list_head olist;
struct list_head flist[DRM_SUBALLOC_MAX_QUEUES];
size_t size;
size_t align;
};
/**
* struct drm_suballoc - Sub-allocated range
* @olist: List link for list of allocated ranges.
* @flist: List linkk for the manager fenced allocated ranges queues.
* @manager: The drm_suballoc_manager.
* @soffset: Start offset.
* @eoffset: End offset + 1 so that @eoffset - @soffset = size.
* @dma_fence: The fence protecting the allocation.
*/
struct drm_suballoc {
struct list_head olist;
struct list_head flist;
struct drm_suballoc_manager *manager;
size_t soffset;
size_t eoffset;
struct dma_fence *fence;
};
void drm_suballoc_manager_init(struct drm_suballoc_manager *sa_manager,
size_t size, size_t align);
void drm_suballoc_manager_fini(struct drm_suballoc_manager *sa_manager);
struct drm_suballoc *
drm_suballoc_new(struct drm_suballoc_manager *sa_manager, size_t size,
gfp_t gfp, bool intr, size_t align);
void drm_suballoc_free(struct drm_suballoc *sa, struct dma_fence *fence);
/**
* drm_suballoc_soffset - Range start.
* @sa: The struct drm_suballoc.
*
* Return: The start of the allocated range.
*/
static inline size_t drm_suballoc_soffset(struct drm_suballoc *sa)
{
return sa->soffset;
}
/**
* drm_suballoc_eoffset - Range end.
* @sa: The struct drm_suballoc.
*
* Return: The end of the allocated range + 1.
*/
static inline size_t drm_suballoc_eoffset(struct drm_suballoc *sa)
{
return sa->eoffset;
}
/**
* drm_suballoc_size - Range size.
* @sa: The struct drm_suballoc.
*
* Return: The size of the allocated range.
*/
static inline size_t drm_suballoc_size(struct drm_suballoc *sa)
{
return sa->eoffset - sa->soffset;
}
#ifdef CONFIG_DEBUG_FS
void drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager,
struct drm_printer *p,
unsigned long long suballoc_base);
#else
static inline void
drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager,
struct drm_printer *p,
unsigned long long suballoc_base)
{ }
#endif
#endif /* _DRM_SUBALLOC_H_ */

1
include/drm/drm_vblank.h
View File

@@ -230,6 +230,7 @@ bool drm_dev_has_vblank(const struct drm_device *dev);
u64 drm_crtc_vblank_count(struct drm_crtc *crtc);
u64 drm_crtc_vblank_count_and_time(struct drm_crtc *crtc,
ktime_t *vblanktime);
int drm_crtc_next_vblank_start(struct drm_crtc *crtc, ktime_t *vblanktime);
void drm_crtc_send_vblank_event(struct drm_crtc *crtc,
struct drm_pending_vblank_event *e);
void drm_crtc_arm_vblank_event(struct drm_crtc *crtc,

23
include/drm/gpu_scheduler.h
View File

@@ -41,6 +41,15 @@
*/
#define DRM_SCHED_FENCE_DONT_PIPELINE DMA_FENCE_FLAG_USER_BITS
/**
* DRM_SCHED_FENCE_FLAG_HAS_DEADLINE_BIT - A fence deadline hint has been set
*
* Because we could have a deadline hint can be set before the backing hw
* fence is created, we need to keep track of whether a deadline has already
* been set.
*/
#define DRM_SCHED_FENCE_FLAG_HAS_DEADLINE_BIT (DMA_FENCE_FLAG_USER_BITS + 1)
enum dma_resv_usage;
struct dma_resv;
struct drm_gem_object;
@@ -48,6 +57,8 @@ struct drm_gem_object;
struct drm_gpu_scheduler;
struct drm_sched_rq;
struct drm_file;
/* These are often used as an (initial) index
* to an array, and as such should start at 0.
*/
@@ -273,6 +284,12 @@ struct drm_sched_fence {
*/
struct dma_fence finished;
/**
* @deadline: deadline set on &drm_sched_fence.finished which
* potentially needs to be propagated to &drm_sched_fence.parent
*/
ktime_t deadline;
/**
* @parent: the fence returned by &drm_sched_backend_ops.run_job
* when scheduling the job on hardware. We signal the
@@ -515,6 +532,10 @@ int drm_sched_job_init(struct drm_sched_job *job,
void drm_sched_job_arm(struct drm_sched_job *job);
int drm_sched_job_add_dependency(struct drm_sched_job *job,
struct dma_fence *fence);
int drm_sched_job_add_syncobj_dependency(struct drm_sched_job *job,
struct drm_file *file,
u32 handle,
u32 point);
int drm_sched_job_add_resv_dependencies(struct drm_sched_job *job,
struct dma_resv *resv,
enum dma_resv_usage usage);
@@ -561,6 +582,8 @@ void drm_sched_entity_set_priority(struct drm_sched_entity *entity,
enum drm_sched_priority priority);
bool drm_sched_entity_is_ready(struct drm_sched_entity *entity);
void drm_sched_fence_set_parent(struct drm_sched_fence *s_fence,
struct dma_fence *fence);
struct drm_sched_fence *drm_sched_fence_alloc(
struct drm_sched_entity *s_entity, void *owner);
void drm_sched_fence_init(struct drm_sched_fence *fence,

539
include/drm/i915_hdcp_interface.h Normal file
View File

@@ -0,0 +1,539 @@
/* SPDX-License-Identifier: (GPL-2.0+) */
/*
* Copyright © 2017-2019 Intel Corporation
*
* Authors:
* Ramalingam C <ramalingam.c@intel.com>
*/
#ifndef _I915_HDCP_INTERFACE_H_
#define _I915_HDCP_INTERFACE_H_
#include <linux/mutex.h>
#include <linux/device.h>
#include <drm/display/drm_hdcp.h>
/**
* enum hdcp_port_type - HDCP port implementation type defined by ME/GSC FW
* @HDCP_PORT_TYPE_INVALID: Invalid hdcp port type
* @HDCP_PORT_TYPE_INTEGRATED: In-Host HDCP2.x port
* @HDCP_PORT_TYPE_LSPCON: HDCP2.2 discrete wired Tx port with LSPCON
* (HDMI 2.0) solution
* @HDCP_PORT_TYPE_CPDP: HDCP2.2 discrete wired Tx port using the CPDP (DP 1.3)
* solution
*/
enum hdcp_port_type {
HDCP_PORT_TYPE_INVALID,
HDCP_PORT_TYPE_INTEGRATED,
HDCP_PORT_TYPE_LSPCON,
HDCP_PORT_TYPE_CPDP
};
/**
* enum hdcp_wired_protocol - HDCP adaptation used on the port
* @HDCP_PROTOCOL_INVALID: Invalid HDCP adaptation protocol
* @HDCP_PROTOCOL_HDMI: HDMI adaptation of HDCP used on the port
* @HDCP_PROTOCOL_DP: DP adaptation of HDCP used on the port
*/
enum hdcp_wired_protocol {
HDCP_PROTOCOL_INVALID,
HDCP_PROTOCOL_HDMI,
HDCP_PROTOCOL_DP
};
enum hdcp_ddi {
HDCP_DDI_INVALID_PORT = 0x0,
HDCP_DDI_B = 1,
HDCP_DDI_C,
HDCP_DDI_D,
HDCP_DDI_E,
HDCP_DDI_F,
HDCP_DDI_A = 7,
HDCP_DDI_RANGE_END = HDCP_DDI_A,
};
/**
* enum hdcp_tc - ME/GSC Firmware defined index for transcoders
* @HDCP_INVALID_TRANSCODER: Index for Invalid transcoder
* @HDCP_TRANSCODER_EDP: Index for EDP Transcoder
* @HDCP_TRANSCODER_DSI0: Index for DSI0 Transcoder
* @HDCP_TRANSCODER_DSI1: Index for DSI1 Transcoder
* @HDCP_TRANSCODER_A: Index for Transcoder A
* @HDCP_TRANSCODER_B: Index for Transcoder B
* @HDCP_TRANSCODER_C: Index for Transcoder C
* @HDCP_TRANSCODER_D: Index for Transcoder D
*/
enum hdcp_transcoder {
HDCP_INVALID_TRANSCODER = 0x00,
HDCP_TRANSCODER_EDP,
HDCP_TRANSCODER_DSI0,
HDCP_TRANSCODER_DSI1,
HDCP_TRANSCODER_A = 0x10,
HDCP_TRANSCODER_B,
HDCP_TRANSCODER_C,
HDCP_TRANSCODER_D
};
/**
* struct hdcp_port_data - intel specific HDCP port data
* @hdcp_ddi: ddi index as per ME/GSC FW
* @hdcp_transcoder: transcoder index as per ME/GSC FW
* @port_type: HDCP port type as per ME/GSC FW classification
* @protocol: HDCP adaptation as per ME/GSC FW
* @k: No of streams transmitted on a port. Only on DP MST this is != 1
* @seq_num_m: Count of RepeaterAuth_Stream_Manage msg propagated.
* Initialized to 0 on AKE_INIT. Incremented after every successful
* transmission of RepeaterAuth_Stream_Manage message. When it rolls
* over re-Auth has to be triggered.
* @streams: struct hdcp2_streamid_type[k]. Defines the type and id for the
* streams
*/
struct hdcp_port_data {
enum hdcp_ddi hdcp_ddi;
enum hdcp_transcoder hdcp_transcoder;
u8 port_type;
u8 protocol;
u16 k;
u32 seq_num_m;
struct hdcp2_streamid_type *streams;
};
/**
* struct i915_hdcp_ops- ops for HDCP2.2 services.
* @owner: Module providing the ops
* @initiate_hdcp2_session: Initiate a Wired HDCP2.2 Tx Session.
* And Prepare AKE_Init.
* @verify_receiver_cert_prepare_km: Verify the Receiver Certificate
* AKE_Send_Cert and prepare
AKE_Stored_Km/AKE_No_Stored_Km
* @verify_hprime: Verify AKE_Send_H_prime
* @store_pairing_info: Store pairing info received
* @initiate_locality_check: Prepare LC_Init
* @verify_lprime: Verify lprime
* @get_session_key: Prepare SKE_Send_Eks
* @repeater_check_flow_prepare_ack: Validate the Downstream topology
* and prepare rep_ack
* @verify_mprime: Verify mprime
* @enable_hdcp_authentication: Mark a port as authenticated.
* @close_hdcp_session: Close the Wired HDCP Tx session per port.
* This also disables the authenticated state of the port.
*/
struct i915_hdcp_ops {
/**
* @owner: hdcp module
*/
struct module *owner;
int (*initiate_hdcp2_session)(struct device *dev,
struct hdcp_port_data *data,
struct hdcp2_ake_init *ake_data);
int (*verify_receiver_cert_prepare_km)(struct device *dev,
struct hdcp_port_data *data,
struct hdcp2_ake_send_cert
*rx_cert,
bool *km_stored,
struct hdcp2_ake_no_stored_km
*ek_pub_km,
size_t *msg_sz);
int (*verify_hprime)(struct device *dev,
struct hdcp_port_data *data,
struct hdcp2_ake_send_hprime *rx_hprime);
int (*store_pairing_info)(struct device *dev,
struct hdcp_port_data *data,
struct hdcp2_ake_send_pairing_info
*pairing_info);
int (*initiate_locality_check)(struct device *dev,
struct hdcp_port_data *data,
struct hdcp2_lc_init *lc_init_data);
int (*verify_lprime)(struct device *dev,
struct hdcp_port_data *data,
struct hdcp2_lc_send_lprime *rx_lprime);
int (*get_session_key)(struct device *dev,
struct hdcp_port_data *data,
struct hdcp2_ske_send_eks *ske_data);
int (*repeater_check_flow_prepare_ack)(struct device *dev,
struct hdcp_port_data *data,
struct hdcp2_rep_send_receiverid_list
*rep_topology,
struct hdcp2_rep_send_ack
*rep_send_ack);
int (*verify_mprime)(struct device *dev,
struct hdcp_port_data *data,
struct hdcp2_rep_stream_ready *stream_ready);
int (*enable_hdcp_authentication)(struct device *dev,
struct hdcp_port_data *data);
int (*close_hdcp_session)(struct device *dev,
struct hdcp_port_data *data);
};
/**
* struct i915_hdcp_master - Used for communication between i915
* and hdcp drivers for the HDCP2.2 services
* @hdcp_dev: device that provide the HDCP2.2 service from MEI Bus.
* @hdcp_ops: Ops implemented by hdcp driver or intel_hdcp_gsc , used by i915 driver.
*/
struct i915_hdcp_master {
struct device *hdcp_dev;
const struct i915_hdcp_ops *ops;
/* To protect the above members. */
struct mutex mutex;
};
/* fw_hdcp_status: Enumeration of all HDCP Status Codes */
enum fw_hdcp_status {
FW_HDCP_STATUS_SUCCESS = 0x0000,
/* WiDi Generic Status Codes */
FW_HDCP_STATUS_INTERNAL_ERROR = 0x1000,
FW_HDCP_STATUS_UNKNOWN_ERROR = 0x1001,
FW_HDCP_STATUS_INCORRECT_API_VERSION = 0x1002,
FW_HDCP_STATUS_INVALID_FUNCTION = 0x1003,
FW_HDCP_STATUS_INVALID_BUFFER_LENGTH = 0x1004,
FW_HDCP_STATUS_INVALID_PARAMS = 0x1005,
FW_HDCP_STATUS_AUTHENTICATION_FAILED = 0x1006,
/* WiDi Status Codes */
FW_HDCP_INVALID_SESSION_STATE = 0x6000,
FW_HDCP_SRM_FRAGMENT_UNEXPECTED = 0x6001,
FW_HDCP_SRM_INVALID_LENGTH = 0x6002,
FW_HDCP_SRM_FRAGMENT_OFFSET_INVALID = 0x6003,
FW_HDCP_SRM_VERIFICATION_FAILED = 0x6004,
FW_HDCP_SRM_VERSION_TOO_OLD = 0x6005,
FW_HDCP_RX_CERT_VERIFICATION_FAILED = 0x6006,
FW_HDCP_RX_REVOKED = 0x6007,
FW_HDCP_H_VERIFICATION_FAILED = 0x6008,
FW_HDCP_REPEATER_CHECK_UNEXPECTED = 0x6009,
FW_HDCP_TOPOLOGY_MAX_EXCEEDED = 0x600A,
FW_HDCP_V_VERIFICATION_FAILED = 0x600B,
FW_HDCP_L_VERIFICATION_FAILED = 0x600C,
FW_HDCP_STREAM_KEY_ALLOC_FAILED = 0x600D,
FW_HDCP_BASE_KEY_RESET_FAILED = 0x600E,
FW_HDCP_NONCE_GENERATION_FAILED = 0x600F,
FW_HDCP_STATUS_INVALID_E_KEY_STATE = 0x6010,
FW_HDCP_STATUS_INVALID_CS_ICV = 0x6011,
FW_HDCP_STATUS_INVALID_KB_KEY_STATE = 0x6012,
FW_HDCP_STATUS_INVALID_PAVP_MODE_ICV = 0x6013,
FW_HDCP_STATUS_INVALID_PAVP_MODE = 0x6014,
FW_HDCP_STATUS_LC_MAX_ATTEMPTS = 0x6015,
/* New status for HDCP 2.1 */
FW_HDCP_STATUS_MISMATCH_IN_M = 0x6016,
/* New status code for HDCP 2.2 Rx */
FW_HDCP_STATUS_RX_PROV_NOT_ALLOWED = 0x6017,
FW_HDCP_STATUS_RX_PROV_WRONG_SUBJECT = 0x6018,
FW_HDCP_RX_NEEDS_PROVISIONING = 0x6019,
FW_HDCP_BKSV_ICV_AUTH_FAILED = 0x6020,
FW_HDCP_STATUS_INVALID_STREAM_ID = 0x6021,
FW_HDCP_STATUS_CHAIN_NOT_INITIALIZED = 0x6022,
FW_HDCP_FAIL_NOT_EXPECTED = 0x6023,
FW_HDCP_FAIL_HDCP_OFF = 0x6024,
FW_HDCP_FAIL_INVALID_PAVP_MEMORY_MODE = 0x6025,
FW_HDCP_FAIL_AES_ECB_FAILURE = 0x6026,
FW_HDCP_FEATURE_NOT_SUPPORTED = 0x6027,
FW_HDCP_DMA_READ_ERROR = 0x6028,
FW_HDCP_DMA_WRITE_ERROR = 0x6029,
FW_HDCP_FAIL_INVALID_PACKET_SIZE = 0x6030,
FW_HDCP_H264_PARSING_ERROR = 0x6031,
FW_HDCP_HDCP2_ERRATA_VIDEO_VIOLATION = 0x6032,
FW_HDCP_HDCP2_ERRATA_AUDIO_VIOLATION = 0x6033,
FW_HDCP_TX_ACTIVE_ERROR = 0x6034,
FW_HDCP_MODE_CHANGE_ERROR = 0x6035,
FW_HDCP_STREAM_TYPE_ERROR = 0x6036,
FW_HDCP_STREAM_MANAGE_NOT_POSSIBLE = 0x6037,
FW_HDCP_STATUS_PORT_INVALID_COMMAND = 0x6038,
FW_HDCP_STATUS_UNSUPPORTED_PROTOCOL = 0x6039,
FW_HDCP_STATUS_INVALID_PORT_INDEX = 0x603a,
FW_HDCP_STATUS_TX_AUTH_NEEDED = 0x603b,
FW_HDCP_STATUS_NOT_INTEGRATED_PORT = 0x603c,
FW_HDCP_STATUS_SESSION_MAX_REACHED = 0x603d,
/* hdcp capable bit is not set in rx_caps(error is unique to DP) */
FW_HDCP_STATUS_NOT_HDCP_CAPABLE = 0x6041,
FW_HDCP_STATUS_INVALID_STREAM_COUNT = 0x6042,
};
#define HDCP_API_VERSION 0x00010000
#define HDCP_M_LEN 16
#define HDCP_KH_LEN 16
/* Payload Buffer size(Excluding Header) for CMDs and corresponding response */
/* Wired_Tx_AKE */
#define WIRED_CMD_BUF_LEN_INITIATE_HDCP2_SESSION_IN (4 + 1)
#define WIRED_CMD_BUF_LEN_INITIATE_HDCP2_SESSION_OUT (4 + 8 + 3)
#define WIRED_CMD_BUF_LEN_VERIFY_RECEIVER_CERT_IN (4 + 522 + 8 + 3)
#define WIRED_CMD_BUF_LEN_VERIFY_RECEIVER_CERT_MIN_OUT (4 + 1 + 3 + 16 + 16)
#define WIRED_CMD_BUF_LEN_VERIFY_RECEIVER_CERT_MAX_OUT (4 + 1 + 3 + 128)
#define WIRED_CMD_BUF_LEN_AKE_SEND_HPRIME_IN (4 + 32)
#define WIRED_CMD_BUF_LEN_AKE_SEND_HPRIME_OUT (4)
#define WIRED_CMD_BUF_LEN_SEND_PAIRING_INFO_IN (4 + 16)
#define WIRED_CMD_BUF_LEN_SEND_PAIRING_INFO_OUT (4)
#define WIRED_CMD_BUF_LEN_CLOSE_SESSION_IN (4)
#define WIRED_CMD_BUF_LEN_CLOSE_SESSION_OUT (4)
/* Wired_Tx_LC */
#define WIRED_CMD_BUF_LEN_INIT_LOCALITY_CHECK_IN (4)
#define WIRED_CMD_BUF_LEN_INIT_LOCALITY_CHECK_OUT (4 + 8)
#define WIRED_CMD_BUF_LEN_VALIDATE_LOCALITY_IN (4 + 32)
#define WIRED_CMD_BUF_LEN_VALIDATE_LOCALITY_OUT (4)
/* Wired_Tx_SKE */
#define WIRED_CMD_BUF_LEN_GET_SESSION_KEY_IN (4)
#define WIRED_CMD_BUF_LEN_GET_SESSION_KEY_OUT (4 + 16 + 8)
/* Wired_Tx_SKE */
#define WIRED_CMD_BUF_LEN_ENABLE_AUTH_IN (4 + 1)
#define WIRED_CMD_BUF_LEN_ENABLE_AUTH_OUT (4)
/* Wired_Tx_Repeater */
#define WIRED_CMD_BUF_LEN_VERIFY_REPEATER_IN (4 + 2 + 3 + 16 + 155)
#define WIRED_CMD_BUF_LEN_VERIFY_REPEATER_OUT (4 + 1 + 16)
#define WIRED_CMD_BUF_LEN_REPEATER_AUTH_STREAM_REQ_MIN_IN (4 + 3 + \
32 + 2 + 2)
#define WIRED_CMD_BUF_LEN_REPEATER_AUTH_STREAM_REQ_OUT (4)
/* hdcp_command_id: Enumeration of all WIRED HDCP Command IDs */
enum hdcp_command_id {
_WIDI_COMMAND_BASE = 0x00030000,
WIDI_INITIATE_HDCP2_SESSION = _WIDI_COMMAND_BASE,
HDCP_GET_SRM_STATUS,
HDCP_SEND_SRM_FRAGMENT,
/* The wired HDCP Tx commands */
_WIRED_COMMAND_BASE = 0x00031000,
WIRED_INITIATE_HDCP2_SESSION = _WIRED_COMMAND_BASE,
WIRED_VERIFY_RECEIVER_CERT,
WIRED_AKE_SEND_HPRIME,
WIRED_AKE_SEND_PAIRING_INFO,
WIRED_INIT_LOCALITY_CHECK,
WIRED_VALIDATE_LOCALITY,
WIRED_GET_SESSION_KEY,
WIRED_ENABLE_AUTH,
WIRED_VERIFY_REPEATER,
WIRED_REPEATER_AUTH_STREAM_REQ,
WIRED_CLOSE_SESSION,
_WIRED_COMMANDS_COUNT,
};
union encrypted_buff {
u8 e_kpub_km[HDCP_2_2_E_KPUB_KM_LEN];
u8 e_kh_km_m[HDCP_2_2_E_KH_KM_M_LEN];
struct {
u8 e_kh_km[HDCP_KH_LEN];
u8 m[HDCP_M_LEN];
} __packed;
};
/* HDCP HECI message header. All header values are little endian. */
struct hdcp_cmd_header {
u32 api_version;
u32 command_id;
enum fw_hdcp_status status;
/* Length of the HECI message (excluding the header) */
u32 buffer_len;
} __packed;
/* Empty command request or response. No data follows the header. */
struct hdcp_cmd_no_data {
struct hdcp_cmd_header header;
} __packed;
/* Uniquely identifies the hdcp port being addressed for a given command. */
struct hdcp_port_id {
u8 integrated_port_type;
/* physical_port is used until Gen11.5. Must be zero for Gen11.5+ */
u8 physical_port;
/* attached_transcoder is for Gen11.5+. Set to zero for <Gen11.5 */
u8 attached_transcoder;
u8 reserved;
} __packed;
/*
* Data structures for integrated wired HDCP2 Tx in
* support of the AKE protocol
*/
/* HECI struct for integrated wired HDCP Tx session initiation. */
struct wired_cmd_initiate_hdcp2_session_in {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
u8 protocol; /* for HDMI vs DP */
} __packed;
struct wired_cmd_initiate_hdcp2_session_out {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
u8 r_tx[HDCP_2_2_RTX_LEN];
struct hdcp2_tx_caps tx_caps;
} __packed;
/* HECI struct for ending an integrated wired HDCP Tx session. */
struct wired_cmd_close_session_in {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
} __packed;
struct wired_cmd_close_session_out {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
} __packed;
/* HECI struct for integrated wired HDCP Tx Rx Cert verification. */
struct wired_cmd_verify_receiver_cert_in {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
struct hdcp2_cert_rx cert_rx;
u8 r_rx[HDCP_2_2_RRX_LEN];
u8 rx_caps[HDCP_2_2_RXCAPS_LEN];
} __packed;
struct wired_cmd_verify_receiver_cert_out {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
u8 km_stored;
u8 reserved[3];
union encrypted_buff ekm_buff;
} __packed;
/* HECI struct for verification of Rx's Hprime in a HDCP Tx session */
struct wired_cmd_ake_send_hprime_in {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
u8 h_prime[HDCP_2_2_H_PRIME_LEN];
} __packed;
struct wired_cmd_ake_send_hprime_out {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
} __packed;
/*
* HECI struct for sending in AKE pairing data generated by the Rx in an
* integrated wired HDCP Tx session.
*/
struct wired_cmd_ake_send_pairing_info_in {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
u8 e_kh_km[HDCP_2_2_E_KH_KM_LEN];
} __packed;
struct wired_cmd_ake_send_pairing_info_out {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
} __packed;
/* Data structures for integrated wired HDCP2 Tx in support of the LC protocol*/
/*
* HECI struct for initiating locality check with an
* integrated wired HDCP Tx session.
*/
struct wired_cmd_init_locality_check_in {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
} __packed;
struct wired_cmd_init_locality_check_out {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
u8 r_n[HDCP_2_2_RN_LEN];
} __packed;
/*
* HECI struct for validating an Rx's LPrime value in an
* integrated wired HDCP Tx session.
*/
struct wired_cmd_validate_locality_in {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
u8 l_prime[HDCP_2_2_L_PRIME_LEN];
} __packed;
struct wired_cmd_validate_locality_out {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
} __packed;
/*
* Data structures for integrated wired HDCP2 Tx in support of the
* SKE protocol
*/
/* HECI struct for creating session key */
struct wired_cmd_get_session_key_in {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
} __packed;
struct wired_cmd_get_session_key_out {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
u8 e_dkey_ks[HDCP_2_2_E_DKEY_KS_LEN];
u8 r_iv[HDCP_2_2_RIV_LEN];
} __packed;
/* HECI struct for the Tx enable authentication command */
struct wired_cmd_enable_auth_in {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
u8 stream_type;
} __packed;
struct wired_cmd_enable_auth_out {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
} __packed;
/*
* Data structures for integrated wired HDCP2 Tx in support of
* the repeater protocols
*/
/*
* HECI struct for verifying the downstream repeater's HDCP topology in an
* integrated wired HDCP Tx session.
*/
struct wired_cmd_verify_repeater_in {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
u8 rx_info[HDCP_2_2_RXINFO_LEN];
u8 seq_num_v[HDCP_2_2_SEQ_NUM_LEN];
u8 v_prime[HDCP_2_2_V_PRIME_HALF_LEN];
u8 receiver_ids[HDCP_2_2_RECEIVER_IDS_MAX_LEN];
} __packed;
struct wired_cmd_verify_repeater_out {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
u8 content_type_supported;
u8 v[HDCP_2_2_V_PRIME_HALF_LEN];
} __packed;
/*
* HECI struct in support of stream management in an
* integrated wired HDCP Tx session.
*/
struct wired_cmd_repeater_auth_stream_req_in {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
u8 seq_num_m[HDCP_2_2_SEQ_NUM_LEN];
u8 m_prime[HDCP_2_2_MPRIME_LEN];
__be16 k;
struct hdcp2_streamid_type streams[];
} __packed;
struct wired_cmd_repeater_auth_stream_req_out {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
} __packed;
#endif /* _I915_HDCP_INTERFACE_H_ */

184
include/drm/i915_mei_hdcp_interface.h
View File

@@ -1,184 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0+) */
/*
* Copyright © 2017-2019 Intel Corporation
*
* Authors:
* Ramalingam C <ramalingam.c@intel.com>
*/
#ifndef _I915_MEI_HDCP_INTERFACE_H_
#define _I915_MEI_HDCP_INTERFACE_H_
#include <linux/mutex.h>
#include <linux/device.h>
#include <drm/display/drm_hdcp.h>
/**
* enum hdcp_port_type - HDCP port implementation type defined by ME FW
* @HDCP_PORT_TYPE_INVALID: Invalid hdcp port type
* @HDCP_PORT_TYPE_INTEGRATED: In-Host HDCP2.x port
* @HDCP_PORT_TYPE_LSPCON: HDCP2.2 discrete wired Tx port with LSPCON
* (HDMI 2.0) solution
* @HDCP_PORT_TYPE_CPDP: HDCP2.2 discrete wired Tx port using the CPDP (DP 1.3)
* solution
*/
enum hdcp_port_type {
HDCP_PORT_TYPE_INVALID,
HDCP_PORT_TYPE_INTEGRATED,
HDCP_PORT_TYPE_LSPCON,
HDCP_PORT_TYPE_CPDP
};
/**
* enum hdcp_wired_protocol - HDCP adaptation used on the port
* @HDCP_PROTOCOL_INVALID: Invalid HDCP adaptation protocol
* @HDCP_PROTOCOL_HDMI: HDMI adaptation of HDCP used on the port
* @HDCP_PROTOCOL_DP: DP adaptation of HDCP used on the port
*/
enum hdcp_wired_protocol {
HDCP_PROTOCOL_INVALID,
HDCP_PROTOCOL_HDMI,
HDCP_PROTOCOL_DP
};
enum mei_fw_ddi {
MEI_DDI_INVALID_PORT = 0x0,
MEI_DDI_B = 1,
MEI_DDI_C,
MEI_DDI_D,
MEI_DDI_E,
MEI_DDI_F,
MEI_DDI_A = 7,
MEI_DDI_RANGE_END = MEI_DDI_A,
};
/**
* enum mei_fw_tc - ME Firmware defined index for transcoders
* @MEI_INVALID_TRANSCODER: Index for Invalid transcoder
* @MEI_TRANSCODER_EDP: Index for EDP Transcoder
* @MEI_TRANSCODER_DSI0: Index for DSI0 Transcoder
* @MEI_TRANSCODER_DSI1: Index for DSI1 Transcoder
* @MEI_TRANSCODER_A: Index for Transcoder A
* @MEI_TRANSCODER_B: Index for Transcoder B
* @MEI_TRANSCODER_C: Index for Transcoder C
* @MEI_TRANSCODER_D: Index for Transcoder D
*/
enum mei_fw_tc {
MEI_INVALID_TRANSCODER = 0x00,
MEI_TRANSCODER_EDP,
MEI_TRANSCODER_DSI0,
MEI_TRANSCODER_DSI1,
MEI_TRANSCODER_A = 0x10,
MEI_TRANSCODER_B,
MEI_TRANSCODER_C,
MEI_TRANSCODER_D
};
/**
* struct hdcp_port_data - intel specific HDCP port data
* @fw_ddi: ddi index as per ME FW
* @fw_tc: transcoder index as per ME FW
* @port_type: HDCP port type as per ME FW classification
* @protocol: HDCP adaptation as per ME FW
* @k: No of streams transmitted on a port. Only on DP MST this is != 1
* @seq_num_m: Count of RepeaterAuth_Stream_Manage msg propagated.
* Initialized to 0 on AKE_INIT. Incremented after every successful
* transmission of RepeaterAuth_Stream_Manage message. When it rolls
* over re-Auth has to be triggered.
* @streams: struct hdcp2_streamid_type[k]. Defines the type and id for the
* streams
*/
struct hdcp_port_data {
enum mei_fw_ddi fw_ddi;
enum mei_fw_tc fw_tc;
u8 port_type;
u8 protocol;
u16 k;
u32 seq_num_m;
struct hdcp2_streamid_type *streams;
};
/**
* struct i915_hdcp_component_ops- ops for HDCP2.2 services.
* @owner: Module providing the ops
* @initiate_hdcp2_session: Initiate a Wired HDCP2.2 Tx Session.
* And Prepare AKE_Init.
* @verify_receiver_cert_prepare_km: Verify the Receiver Certificate
* AKE_Send_Cert and prepare
AKE_Stored_Km/AKE_No_Stored_Km
* @verify_hprime: Verify AKE_Send_H_prime
* @store_pairing_info: Store pairing info received
* @initiate_locality_check: Prepare LC_Init
* @verify_lprime: Verify lprime
* @get_session_key: Prepare SKE_Send_Eks
* @repeater_check_flow_prepare_ack: Validate the Downstream topology
* and prepare rep_ack
* @verify_mprime: Verify mprime
* @enable_hdcp_authentication: Mark a port as authenticated.
* @close_hdcp_session: Close the Wired HDCP Tx session per port.
* This also disables the authenticated state of the port.
*/
struct i915_hdcp_component_ops {
/**
* @owner: mei_hdcp module
*/
struct module *owner;
int (*initiate_hdcp2_session)(struct device *dev,
struct hdcp_port_data *data,
struct hdcp2_ake_init *ake_data);
int (*verify_receiver_cert_prepare_km)(struct device *dev,
struct hdcp_port_data *data,
struct hdcp2_ake_send_cert
*rx_cert,
bool *km_stored,
struct hdcp2_ake_no_stored_km
*ek_pub_km,
size_t *msg_sz);
int (*verify_hprime)(struct device *dev,
struct hdcp_port_data *data,
struct hdcp2_ake_send_hprime *rx_hprime);
int (*store_pairing_info)(struct device *dev,
struct hdcp_port_data *data,
struct hdcp2_ake_send_pairing_info
*pairing_info);
int (*initiate_locality_check)(struct device *dev,
struct hdcp_port_data *data,
struct hdcp2_lc_init *lc_init_data);
int (*verify_lprime)(struct device *dev,
struct hdcp_port_data *data,
struct hdcp2_lc_send_lprime *rx_lprime);
int (*get_session_key)(struct device *dev,
struct hdcp_port_data *data,
struct hdcp2_ske_send_eks *ske_data);
int (*repeater_check_flow_prepare_ack)(struct device *dev,
struct hdcp_port_data *data,
struct hdcp2_rep_send_receiverid_list
*rep_topology,
struct hdcp2_rep_send_ack
*rep_send_ack);
int (*verify_mprime)(struct device *dev,
struct hdcp_port_data *data,
struct hdcp2_rep_stream_ready *stream_ready);
int (*enable_hdcp_authentication)(struct device *dev,
struct hdcp_port_data *data);
int (*close_hdcp_session)(struct device *dev,
struct hdcp_port_data *data);
};
/**
* struct i915_hdcp_component_master - Used for communication between i915
* and mei_hdcp drivers for the HDCP2.2 services
* @mei_dev: device that provide the HDCP2.2 service from MEI Bus.
* @hdcp_ops: Ops implemented by mei_hdcp driver, used by i915 driver.
*/
struct i915_hdcp_comp_master {
struct device *mei_dev;
const struct i915_hdcp_component_ops *ops;
/* To protect the above members. */
struct mutex mutex;
};
#endif /* _I915_MEI_HDCP_INTERFACE_H_ */

14
include/drm/i915_pciids.h
View File

@@ -588,6 +588,7 @@
INTEL_VGA_DEVICE(0x4551, info), \
INTEL_VGA_DEVICE(0x4555, info), \
INTEL_VGA_DEVICE(0x4557, info), \
INTEL_VGA_DEVICE(0x4570, info), \
INTEL_VGA_DEVICE(0x4571, info)
/* JSL */
@@ -684,14 +685,18 @@
INTEL_VGA_DEVICE(0xA78A, info), \
INTEL_VGA_DEVICE(0xA78B, info)
/* RPL-U */
#define INTEL_RPLU_IDS(info) \
INTEL_VGA_DEVICE(0xA721, info), \
INTEL_VGA_DEVICE(0xA7A1, info), \
INTEL_VGA_DEVICE(0xA7A9, info)
/* RPL-P */
#define INTEL_RPLP_IDS(info) \
INTEL_RPLU_IDS(info), \
INTEL_VGA_DEVICE(0xA720, info), \
INTEL_VGA_DEVICE(0xA721, info), \
INTEL_VGA_DEVICE(0xA7A0, info), \
INTEL_VGA_DEVICE(0xA7A1, info), \
INTEL_VGA_DEVICE(0xA7A8, info), \
INTEL_VGA_DEVICE(0xA7A9, info)
INTEL_VGA_DEVICE(0xA7A8, info)
/* DG2 */
#define INTEL_DG2_G10_IDS(info) \
@@ -706,7 +711,6 @@
INTEL_VGA_DEVICE(0x5693, info), \
INTEL_VGA_DEVICE(0x5694, info), \
INTEL_VGA_DEVICE(0x5695, info), \
INTEL_VGA_DEVICE(0x5698, info), \
INTEL_VGA_DEVICE(0x56A5, info), \
INTEL_VGA_DEVICE(0x56A6, info), \
INTEL_VGA_DEVICE(0x56B0, info), \

2
include/drm/ttm/ttm_device.h
View File

@@ -141,7 +141,7 @@ struct ttm_device_funcs {
* the graphics address space
* @ctx: context for this move with parameters
* @new_mem: the new memory region receiving the buffer
@ @hop: placement for driver directed intermediate hop
* @hop: placement for driver directed intermediate hop
*
* Move a buffer between two memory regions.
* Returns errno -EMULTIHOP if driver requests a hop

10
include/drm/ttm/ttm_tt.h
View File

@@ -83,12 +83,12 @@ struct ttm_tt {
* set by TTM after ttm_tt_populate() has successfully returned, and is
* then unset when TTM calls ttm_tt_unpopulate().
*/
#define TTM_TT_FLAG_SWAPPED (1 << 0)
#define TTM_TT_FLAG_ZERO_ALLOC (1 << 1)
#define TTM_TT_FLAG_EXTERNAL (1 << 2)
#define TTM_TT_FLAG_EXTERNAL_MAPPABLE (1 << 3)
#define TTM_TT_FLAG_SWAPPED BIT(0)
#define TTM_TT_FLAG_ZERO_ALLOC BIT(1)
#define TTM_TT_FLAG_EXTERNAL BIT(2)
#define TTM_TT_FLAG_EXTERNAL_MAPPABLE BIT(3)
#define TTM_TT_FLAG_PRIV_POPULATED (1U << 31)
#define TTM_TT_FLAG_PRIV_POPULATED BIT(4)
uint32_t page_flags;
/** @num_pages: Number of pages in the page array. */
uint32_t num_pages;