From 4fab69dd1fa52e28bb692afcb159fa8807d6d03f Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Wed, 27 Aug 2025 19:03:44 +0100 Subject: [PATCH 1/2] dt-bindings: cache: ax45mp: add 2048 as a supported cache-sets value The QiLai implementation of this cache controller uses a cache-sets of 2048, and mandates it in an if/else block - but the definition of the property only permits 1024. Add 2048 as an option, and deny its use outside of the QiLai. Fixes: 51b081cdb9237 ("dt-bindings: cache: add QiLai compatible to ax45mp") Reviewed-by: Ben Zong-You Xie Signed-off-by: Conor Dooley --- .../devicetree/bindings/cache/andestech,ax45mp-cache.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml index 4de5bb2e5f24..b135ffa4ab6b 100644 --- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml @@ -47,7 +47,7 @@ properties: const: 2 cache-sets: - const: 1024 + enum: [1024, 2048] cache-size: enum: [131072, 262144, 524288, 1048576, 2097152] @@ -81,6 +81,10 @@ allOf: const: 2048 cache-size: const: 2097152 + else: + properties: + cache-sets: + const: 1024 examples: - | From 941327ca5ddd45cfc4dd960cbbabed9e2b5cb1b0 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Tue, 9 Sep 2025 15:41:27 -0700 Subject: [PATCH 2/2] cache: sifive_ccache: Optimize cache flushes Fence instructions are required only at the beginning and the end of a flush operation, not separately for each cache line being flushed. Speed up cache flushes by about 15% by removing the extra fences. Signed-off-by: Samuel Holland Signed-off-by: Conor Dooley --- drivers/cache/sifive_ccache.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/cache/sifive_ccache.c b/drivers/cache/sifive_ccache.c index e1a283805ea7..a86800b123b9 100644 --- a/drivers/cache/sifive_ccache.c +++ b/drivers/cache/sifive_ccache.c @@ -151,16 +151,16 @@ static void ccache_flush_range(phys_addr_t start, size_t len) if (!len) return; - mb(); + mb(); /* complete earlier memory accesses before the cache flush */ for (line = ALIGN_DOWN(start, SIFIVE_CCACHE_LINE_SIZE); line < end; line += SIFIVE_CCACHE_LINE_SIZE) { #ifdef CONFIG_32BIT - writel(line >> 4, ccache_base + SIFIVE_CCACHE_FLUSH32); + writel_relaxed(line >> 4, ccache_base + SIFIVE_CCACHE_FLUSH32); #else - writeq(line, ccache_base + SIFIVE_CCACHE_FLUSH64); + writeq_relaxed(line, ccache_base + SIFIVE_CCACHE_FLUSH64); #endif - mb(); } + mb(); /* issue later memory accesses after the cache flush */ } static const struct riscv_nonstd_cache_ops ccache_mgmt_ops __initconst = {