From 587aed72c6b98612190bbae77330f341cf98f4f7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 19 Sep 2016 21:40:43 +0000 Subject: [PATCH 1/9] ARM: dts: socfpga: Add new MCVEVK manufacturer compat The board is now manufactured by Aries Embedded GmbH, update compat string. Signed-off-by: Marek Vasut Cc: Dinh Nguyen Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi | 2 +- arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi b/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi index f86f9c060d7a..6ad3b1eb9b86 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi @@ -18,7 +18,7 @@ #include "socfpga_cyclone5.dtsi" / { - model = "DENX MCV"; + model = "Aries/DENX MCV"; compatible = "altr,socfpga-cyclone5", "altr,socfpga"; memory { diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts index 7186a29b8b86..424523b0d381 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts @@ -18,7 +18,7 @@ #include "socfpga_cyclone5_mcv.dtsi" / { - model = "DENX MCV EVK"; + model = "Aries/DENX MCV EVK"; compatible = "altr,socfpga-cyclone5", "altr,socfpga"; aliases { From 73c7d4203c2fd9aa888df0196f7e8c058186baaa Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Sat, 24 Sep 2016 23:59:45 +0000 Subject: [PATCH 2/9] ARM: dts: socfpga: Add Macnica sodia board Add support for board based on the Altera Cyclone V SoC. This board has the following functions: - 1 GiB of DRAM - 1 Gigabit ethernet - 1 SD card slot - 1 USB gadget port - QSPI NOR Flash - I2C EEPROMs and I2C RTC - DVI output - Audio port This commit supports without QSPI, DVI and Audio. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/socfpga_cyclone5_sodia.dts | 123 +++++++++++++++++++ 2 files changed, 124 insertions(+) create mode 100644 arch/arm/boot/dts/socfpga_cyclone5_sodia.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index befcd2619902..7c5f0c31b6f6 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -696,6 +696,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_cyclone5_de0_sockit.dtb \ socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb \ + socfpga_cyclone5_sodia.dtb \ socfpga_cyclone5_vining_fpga.dtb \ socfpga_vt.dtb dtb-$(CONFIG_ARCH_SPEAR13XX) += \ diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts new file mode 100644 index 000000000000..9aaf413b80de --- /dev/null +++ b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts @@ -0,0 +1,123 @@ +/* + * Copyright (C) 2016 Nobuhiro Iwamatsu + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "socfpga_cyclone5.dtsi" +#include +#include + +/ { + model = "Altera SOCFPGA Cyclone V SoC Macnica Sodia board"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + aliases { + ethernet0 = &gmac1; + }; + + regulator_3_3v: 3-3-v-regulator { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + + hps_led0 { + label = "hps:green:led0"; + gpios = <&portb 12 GPIO_ACTIVE_LOW>; + }; + + hps_led1 { + label = "hps:green:led1"; + gpios = <&portb 13 GPIO_ACTIVE_LOW>; + }; + + hps_led2 { + label = "hps:green:led2"; + gpios = <&portb 14 GPIO_ACTIVE_LOW>; + }; + + hps_led3 { + label = "hps:green:led3"; + gpios = <&portb 15 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + phy = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { + reg = <0>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <3000>; + txen-skew-ps = <0>; + txc-skew-ps = <3000>; + }; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; + + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&mmc0 { + cd-gpios = <&portb 18 0>; + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; From ecba2390e350cdce2c47800cde34d0fe91b53870 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 26 Sep 2016 14:29:30 -0500 Subject: [PATCH 3/9] ARM: dts: socfpga: enable arm,shared-override in the pl310 Enable the bit(22) shared-override bit for the SoCFPGA family. While at it, enable the prefetch-data and prefetch-instr settings for the Arria10. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 1 + arch/arm/boot/dts/socfpga_arria10.dtsi | 3 +++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 9f48141270b8..28ff6e4cd54e 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -686,6 +686,7 @@ L2: l2-cache@fffef000 { arm,data-latency = <2 1 1>; prefetch-data = <1>; prefetch-instr = <1>; + arm,shared-override; }; mmc: dwmmc0@ff704000 { diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index f520cbff5e1c..ac0e19ca14b0 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -573,6 +573,9 @@ L2: l2-cache@fffff000 { interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; cache-unified; cache-level = <2>; + prefetch-data = <1>; + prefetch-instr = <1>; + arm,shared-override; }; mmc: dwmmc0@ff808000 { From f2d6f8f8178142519c5b576582bec5cf9eabbaaf Mon Sep 17 00:00:00 2001 From: Thor Thayer Date: Thu, 2 Jun 2016 17:52:25 +0000 Subject: [PATCH 4/9] ARM: dts: socfpga: Add SPI Master1 for Arria10 SR chip Add the Altera Arria10 SPI Master Node in preparation for the A10SR MFD node. Signed-off-by: Thor Thayer Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index ac0e19ca14b0..1149216c78c5 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -562,6 +562,21 @@ i2c4: i2c@ffc02600 { status = "disabled"; }; + spi1: spi@ffda5000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xffda5000 0x100>; + interrupts = <0 102 4>; + num-chipselect = <4>; + bus-num = <0>; + /*32bit_access;*/ + tx-dma-channel = <&pdma 16>; + rx-dma-channel = <&pdma 17>; + clocks = <&spi_m_clk>; + status = "disabled"; + }; + sdr: sdr@ffc25000 { compatible = "syscon"; reg = <0xffcfb100 0x80>; From 5984be047d35379012184310cafcac9efac366b8 Mon Sep 17 00:00:00 2001 From: Thor Thayer Date: Thu, 2 Jun 2016 17:52:26 +0000 Subject: [PATCH 5/9] ARM: dts: socfpga: Add Devkit A10-SR fields for Arria10 Add the Altera Arria10 System Resource node. This is a Multi-Function device with GPIO expander support. Signed-off-by: Thor Thayer Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 21 ++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi index 8e3a4adc389f..9f97756693f4 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi @@ -75,6 +75,27 @@ &gmac0 { status = "okay"; }; +&spi1 { + status = "okay"; + + resource-manager@0 { + compatible = "altr,a10sr"; + reg = <0>; + spi-max-frequency = <100000>; + /* low-level active IRQ at GPIO1_5 */ + interrupt-parent = <&portb>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + a10sr_gpio: gpio-controller { + compatible = "altr,a10sr-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; +}; + &i2c1 { speed-mode = <0>; status = "okay"; From 07e75f4393b42b6c82c5d31714ceeba429fa34c3 Mon Sep 17 00:00:00 2001 From: Thor Thayer Date: Thu, 2 Jun 2016 17:52:27 +0000 Subject: [PATCH 6/9] ARM: dts: socfpga: Enable GPIO parent for Arria10 SR chip Enable the Altera Arria10 GPIO parent for MFD operation. Signed-off-by: Thor Thayer Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi index 9f97756693f4..693fa508cb97 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi @@ -75,6 +75,10 @@ &gmac0 { status = "okay"; }; +&gpio1 { + status = "okay"; +}; + &spi1 { status = "okay"; From acf3b20c23861d38a911f3e0b916fc39ff4211f6 Mon Sep 17 00:00:00 2001 From: Thor Thayer Date: Thu, 2 Jun 2016 17:52:28 +0000 Subject: [PATCH 7/9] ARM: dts: socfpga: Add LED framework to A10-SR GPIO Add the LED framework to the Arria10 System Resource chip GPIO hooks. Signed-off-by: Thor Thayer Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 24 ++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi index 693fa508cb97..eb00ae37f316 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi @@ -36,6 +36,30 @@ memory { reg = <0x0 0x40000000>; /* 1GB */ }; + a10leds { + compatible = "gpio-leds"; + + a10sr_led0 { + label = "a10sr-led0"; + gpios = <&a10sr_gpio 0 1>; + }; + + a10sr_led1 { + label = "a10sr-led1"; + gpios = <&a10sr_gpio 1 1>; + }; + + a10sr_led2 { + label = "a10sr-led2"; + gpios = <&a10sr_gpio 2 1>; + }; + + a10sr_led3 { + label = "a10sr-led3"; + gpios = <&a10sr_gpio 3 1>; + }; + }; + soc { clkmgr@ffd04000 { clocks { From c6deff00b90496d5453d471277a8b469dc3e150d Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Tue, 18 Oct 2016 07:43:02 +0000 Subject: [PATCH 8/9] ARM: dts: socfpga: add qspi node Add the qspi node to the socfpga dtsi file. Signed-off-by: Steffen Trumtrar Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 28ff6e4cd54e..dda6b4500b9a 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -706,6 +706,20 @@ ocram: sram@ffff0000 { reg = <0xffff0000 0x10000>; }; + qspi: spi@ff705000 { + compatible = "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff705000 0x1000>, + <0xffa00000 0x1000>; + interrupts = <0 151 4>; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + clocks = <&qspi_clk>; + status = "disabled"; + }; + rst: rstmgr@ffd05000 { #reset-cells = <1>; compatible = "altr,rst-mgr"; From c96f5919e6b0d132aa9afe9f1adc872fc107d5bb Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Tue, 18 Oct 2016 07:43:03 +0000 Subject: [PATCH 9/9] ARM: dts: socfpga: socrates: enable qspi Enable the qspi controller on the socrates and add the flash chip. Signed-off-by: Steffen Trumtrar Signed-off-by: Dinh Nguyen --- .../boot/dts/socfpga_cyclone5_socrates.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts index d79853775061..c3d52f27b21e 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts @@ -80,3 +80,22 @@ led@2 { &mmc { status = "okay"; }; + +&qspi { + status = "okay"; + + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q256a"; + reg = <0>; + spi-max-frequency = <100000000>; + m25p,fast-read; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + status = "okay"; + }; +};