mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-05-10 21:14:56 -04:00
Merge branches 'clk-of', 'clk-samsung', 'clk-rockchip' and 'clk-qcom' into clk-next
* clk-of: clk: add missing of_node_put() in "assigned-clocks" property parsing * clk-samsung: clk: samsung: exynos850: Make PMU_ALIVE_PCLK critical clk: samsung: Convert to platform remove callback returning void clk: samsung: exynos5433: Extract PM support to common ARM64 layer clk: samsung: Extract parent clock enabling to common function clk: samsung: Extract clocks registration to common function clk: samsung: exynos850: Add AUD and HSI main gate clocks clk: samsung: exynos850: Implement CMU_G3D domain clk: samsung: clk-pll: Implement pll0818x PLL type clk: samsung: Set dev in samsung_clk_init() clk: samsung: Don't pass reg_base to samsung_clk_register_pll() clk: samsung: Remove np argument from samsung_clk_init() dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D * clk-rockchip: clk: rockchip: rk3588: make gate linked clocks critical clk: rockchip: rk3399: allow clk_cifout to force clk_cifout_src to reparent * clk-qcom: (57 commits) clk: qcom: gcc-sc8280xp: Add EMAC GDSCs clk: qcom: dispcc-qcm2290: Remove inexistent DSI1PHY clk clk: qcom: add the GPUCC driver for sa8775p dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P clk: qcom: gcc-sm8350: fix PCIe PIPE clocks handling clk: qcom: lpassaudiocc-sc7280: Add required gdsc power domain clks in lpass_cc_sc7280_desc clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registration dt-bindings: clock: qcom,sc7280-lpasscc: Add qcom,adsp-pil-mode property clk: qcom: rpm: Use managed `of_clk_add_hw_provider()` clk: qcom: Add Global Clock Controller driver for IPQ9574 dt-bindings: clock: Add ipq9574 clock and reset definitions clk: qcom: gpucc-sm6375: Configure CX_GDSC disable wait value clk: qcom: gcc-sm6115: Mark RCGs shared where applicable clk: qcom: dispcc-qcm2290: Add MDSS_CORE reset dt-bindings: clock: dispcc-qcm2290: Add MDSS_CORE reset clk: qcom: apss-ipq-pll: add support for IPQ5332 dt-bindings: clock: qcom,a53pll: add IPQ5332 compatible clk: qcom: apss-ipq-pll: refactor the driver to accommodate different PLL types dt-bindings: mailbox: qcom,apcs-kpss-global: fix SDX55 'if' match dt-bindings: mailbox: qcom,apcs-kpss-global: correct SDX55 clocks ...
This commit is contained in:
Stephen Boyd
@@ -1,49 +0,0 @@
|
||||
Krait Processor Sub-system (KPSS) Application Clock Controller (ACC)
|
||||
|
||||
The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
|
||||
There is one ACC register region per CPU within the KPSS remapped region as
|
||||
well as an alias register region that remaps accesses to the ACC associated
|
||||
with the CPU accessing the region.
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: should be one of:
|
||||
"qcom,kpss-acc-v1"
|
||||
"qcom,kpss-acc-v2"
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: the first element specifies the base address and size of
|
||||
the register region. An optional second element specifies
|
||||
the base address and size of the alias register region.
|
||||
|
||||
- clocks:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: reference to the pll parents.
|
||||
|
||||
- clock-names:
|
||||
Usage: required
|
||||
Value type: <stringlist>
|
||||
Definition: must be "pll8_vote", "pxo".
|
||||
|
||||
- clock-output-names:
|
||||
Usage: optional
|
||||
Value type: <string>
|
||||
Definition: Name of the output clock. Typically acpuX_aux where X is a
|
||||
CPU number starting at 0.
|
||||
|
||||
Example:
|
||||
|
||||
clock-controller@2088000 {
|
||||
compatible = "qcom,kpss-acc-v2";
|
||||
reg = <0x02088000 0x1000>,
|
||||
<0x02008000 0x1000>;
|
||||
clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
|
||||
clock-names = "pll8_vote", "pxo";
|
||||
clock-output-names = "acpu0_aux";
|
||||
};
|
||||
@@ -1,44 +0,0 @@
|
||||
Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: should be one of the following. The generic compatible
|
||||
"qcom,kpss-gcc" should also be included.
|
||||
"qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"
|
||||
"qcom,kpss-gcc-apq8064", "qcom,kpss-gcc"
|
||||
"qcom,kpss-gcc-msm8974", "qcom,kpss-gcc"
|
||||
"qcom,kpss-gcc-msm8960", "qcom,kpss-gcc"
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: base address and size of the register region
|
||||
|
||||
- clocks:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: reference to the pll parents.
|
||||
|
||||
- clock-names:
|
||||
Usage: required
|
||||
Value type: <stringlist>
|
||||
Definition: must be "pll8_vote", "pxo".
|
||||
|
||||
- clock-output-names:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Name of the output clock. Typically acpu_l2_aux indicating
|
||||
an L2 cache auxiliary clock.
|
||||
|
||||
Example:
|
||||
|
||||
l2cc: clock-controller@2011000 {
|
||||
compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc";
|
||||
reg = <0x2011000 0x1000>;
|
||||
clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
|
||||
clock-names = "pll8_vote", "pxo";
|
||||
clock-output-names = "acpu_l2_aux";
|
||||
};
|
||||
@@ -16,6 +16,7 @@ description:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,ipq5332-a53pll
|
||||
- qcom,ipq6018-a53pll
|
||||
- qcom,ipq8074-a53pll
|
||||
- qcom,msm8916-a53pll
|
||||
|
||||
@@ -0,0 +1,53 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq4019.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller on IPQ4019
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
- Robert Marko <robert.markoo@sartura.hr>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on IPQ4019.
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,gcc-ipq4019.h
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-ipq4019
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: board XO clock
|
||||
- description: sleep clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: sleep_clk
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@1800000 {
|
||||
compatible = "qcom,gcc-ipq4019";
|
||||
reg = <0x1800000 0x60000>;
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
clocks = <&xo>, <&sleep_clk>;
|
||||
clock-names = "xo", "sleep_clk";
|
||||
};
|
||||
...
|
||||
@@ -4,20 +4,25 @@
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8909.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller on MSM8909
|
||||
title: Qualcomm Global Clock & Reset Controller on MSM8909, MSM8917 and QM215
|
||||
|
||||
maintainers:
|
||||
- Stephan Gerhold <stephan@gerhold.net>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on MSM8909.
|
||||
domains on MSM8909, MSM8917 or QM215.
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,gcc-msm8909.h
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,gcc-msm8909.h
|
||||
include/dt-bindings/clock/qcom,gcc-msm8917.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-msm8909
|
||||
enum:
|
||||
- qcom,gcc-msm8909
|
||||
- qcom,gcc-msm8917
|
||||
- qcom,gcc-qm215
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
||||
@@ -15,7 +15,6 @@ description: |
|
||||
domains.
|
||||
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,gcc-ipq4019.h
|
||||
include/dt-bindings/clock/qcom,gcc-ipq6018.h
|
||||
include/dt-bindings/reset/qcom,gcc-ipq6018.h
|
||||
include/dt-bindings/clock/qcom,gcc-msm8953.h
|
||||
@@ -29,7 +28,6 @@ allOf:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,gcc-ipq4019
|
||||
- qcom,gcc-ipq6018
|
||||
- qcom,gcc-mdm9607
|
||||
- qcom,gcc-msm8953
|
||||
|
||||
@@ -15,6 +15,7 @@ description: |
|
||||
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,gpucc-sdm845.h
|
||||
include/dt-bindings/clock/qcom,gpucc-sa8775p.h
|
||||
include/dt-bindings/clock/qcom,gpucc-sc7180.h
|
||||
include/dt-bindings/clock/qcom,gpucc-sc7280.h
|
||||
include/dt-bindings/clock/qcom,gpucc-sc8280xp.h
|
||||
@@ -27,6 +28,7 @@ properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sdm845-gpucc
|
||||
- qcom,sa8775p-gpucc
|
||||
- qcom,sc7180-gpucc
|
||||
- qcom,sc7280-gpucc
|
||||
- qcom,sc8180x-gpucc
|
||||
|
||||
@@ -0,0 +1,53 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller on IPQ5332
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on IPQ5332.
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,ipq5332-gcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO clock source
|
||||
- description: Sleep clock source
|
||||
- description: PCIE 2lane PHY pipe clock source
|
||||
- description: PCIE 2lane x1 PHY pipe clock source (For second lane)
|
||||
- description: USB PCIE wrapper pipe clock source
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@1800000 {
|
||||
compatible = "qcom,ipq5332-gcc";
|
||||
reg = <0x01800000 0x80000>;
|
||||
clocks = <&xo_board>,
|
||||
<&sleep_clk>,
|
||||
<&pcie_2lane_phy_pipe_clk>,
|
||||
<&pcie_2lane_phy_pipe_clk_x1>,
|
||||
<&usb_pcie_wrapper_pipe_clk>;
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
...
|
||||
@@ -0,0 +1,61 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,ipq9574-gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller on IPQ9574
|
||||
|
||||
maintainers:
|
||||
- Anusha Rao <quic_anusha@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on IPQ9574
|
||||
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,ipq9574-gcc.h
|
||||
include/dt-bindings/reset/qcom,ipq9574-gcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,ipq9574-gcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Sleep clock source
|
||||
- description: Bias PLL ubi clock source
|
||||
- description: PCIE30 PHY0 pipe clock source
|
||||
- description: PCIE30 PHY1 pipe clock source
|
||||
- description: PCIE30 PHY2 pipe clock source
|
||||
- description: PCIE30 PHY3 pipe clock source
|
||||
- description: USB3 PHY pipe clock source
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@1800000 {
|
||||
compatible = "qcom,ipq9574-gcc";
|
||||
reg = <0x01800000 0x80000>;
|
||||
clocks = <&xo_board_clk>,
|
||||
<&sleep_clk>,
|
||||
<&bias_pll_ubi_nc_clk>,
|
||||
<&pcie30_phy0_pipe_clk>,
|
||||
<&pcie30_phy1_pipe_clk>,
|
||||
<&pcie30_phy2_pipe_clk>,
|
||||
<&pcie30_phy3_pipe_clk>,
|
||||
<&usb3phy_0_cc_pipe_clk>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@@ -0,0 +1,72 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,kpss-acc-v1.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) v1
|
||||
|
||||
maintainers:
|
||||
- Christian Marangi <ansuelsmth@gmail.com>
|
||||
|
||||
description:
|
||||
The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
|
||||
There is one ACC register region per CPU within the KPSS remapped region as
|
||||
well as an alias register region that remaps accesses to the ACC associated
|
||||
with the CPU accessing the region. ACC v1 is currently used as a
|
||||
clock-controller for enabling the cpu and hanling the aux clocks.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,kpss-acc-v1
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Base address and size of the register region
|
||||
- description: Optional base address and size of the alias register region
|
||||
minItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pll8_vote
|
||||
- const: pxo
|
||||
|
||||
clock-output-names:
|
||||
description: Name of the aux clock. Krait can have at most 4 cpu.
|
||||
enum:
|
||||
- acpu0_aux
|
||||
- acpu1_aux
|
||||
- acpu2_aux
|
||||
- acpu3_aux
|
||||
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- clock-output-names
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
|
||||
|
||||
clock-controller@2088000 {
|
||||
compatible = "qcom,kpss-acc-v1";
|
||||
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
|
||||
clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
|
||||
clock-names = "pll8_vote", "pxo";
|
||||
clock-output-names = "acpu0_aux";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
...
|
||||
88
Documentation/devicetree/bindings/clock/qcom,kpss-gcc.yaml
Normal file
88
Documentation/devicetree/bindings/clock/qcom,kpss-gcc.yaml
Normal file
@@ -0,0 +1,88 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,kpss-gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
|
||||
|
||||
maintainers:
|
||||
- Christian Marangi <ansuelsmth@gmail.com>
|
||||
|
||||
description:
|
||||
Krait Processor Sub-system (KPSS) Global Clock Controller (GCC). Used
|
||||
to control L2 mux (in the current implementation) and provide access
|
||||
to the kpss-gcc registers.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- qcom,kpss-gcc-ipq8064
|
||||
- qcom,kpss-gcc-apq8064
|
||||
- qcom,kpss-gcc-msm8974
|
||||
- qcom,kpss-gcc-msm8960
|
||||
- qcom,kpss-gcc-msm8660
|
||||
- qcom,kpss-gcc-mdm9615
|
||||
- const: qcom,kpss-gcc
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pll8_vote
|
||||
- const: pxo
|
||||
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,kpss-gcc-ipq8064
|
||||
- qcom,kpss-gcc-apq8064
|
||||
- qcom,kpss-gcc-msm8974
|
||||
- qcom,kpss-gcc-msm8960
|
||||
then:
|
||||
required:
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
else:
|
||||
properties:
|
||||
clock: false
|
||||
clock-names: false
|
||||
'#clock-cells': false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
|
||||
|
||||
clock-controller@2011000 {
|
||||
compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon";
|
||||
reg = <0x2011000 0x1000>;
|
||||
clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
|
||||
clock-names = "pll8_vote", "pxo";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
- |
|
||||
clock-controller@2011000 {
|
||||
compatible = "qcom,kpss-gcc-mdm9615", "qcom,kpss-gcc", "syscon";
|
||||
reg = <0x02011000 0x1000>;
|
||||
};
|
||||
...
|
||||
@@ -31,6 +31,7 @@ properties:
|
||||
- qcom,rpmcc-msm8660
|
||||
- qcom,rpmcc-msm8909
|
||||
- qcom,rpmcc-msm8916
|
||||
- qcom,rpmcc-msm8917
|
||||
- qcom,rpmcc-msm8936
|
||||
- qcom,rpmcc-msm8953
|
||||
- qcom,rpmcc-msm8974
|
||||
@@ -107,6 +108,7 @@ allOf:
|
||||
- qcom,rpmcc-mdm9607
|
||||
- qcom,rpmcc-msm8226
|
||||
- qcom,rpmcc-msm8916
|
||||
- qcom,rpmcc-msm8917
|
||||
- qcom,rpmcc-msm8936
|
||||
- qcom,rpmcc-msm8953
|
||||
- qcom,rpmcc-msm8974
|
||||
|
||||
@@ -41,6 +41,12 @@ properties:
|
||||
- const: qdsp6ss
|
||||
- const: top_cc
|
||||
|
||||
qcom,adsp-pil-mode:
|
||||
description:
|
||||
Indicates if the LPASS would be brought out of reset using
|
||||
remoteproc peripheral loader.
|
||||
type: boolean
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
@@ -60,6 +66,7 @@ examples:
|
||||
reg-names = "qdsp6ss", "top_cc";
|
||||
clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
|
||||
clock-names = "iface";
|
||||
qcom,adsp-pil-mode;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
||||
@@ -0,0 +1,58 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm6115-gpucc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Graphics Clock & Reset Controller on SM6115
|
||||
|
||||
maintainers:
|
||||
- Konrad Dybcio <konrad.dybcio@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm graphics clock control module provides clocks, resets and power
|
||||
domains on Qualcomm SoCs.
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sm6115-gpucc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sm6115-gpucc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: GPLL0 main branch source
|
||||
- description: GPLL0 main div source
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sm6115.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
clock-controller@5990000 {
|
||||
compatible = "qcom,sm6115-gpucc";
|
||||
reg = <0x05990000 0x9000>;
|
||||
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
|
||||
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
|
||||
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
};
|
||||
...
|
||||
@@ -0,0 +1,64 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm6125-gpucc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Graphics Clock & Reset Controller on SM6125
|
||||
|
||||
maintainers:
|
||||
- Konrad Dybcio <konrad.dybcio@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm graphics clock control module provides clocks and power domains on
|
||||
Qualcomm SoCs.
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sm6125-gpucc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sm6125-gpucc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: GPLL0 main branch source
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sm6125.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
clock-controller@5990000 {
|
||||
compatible = "qcom,sm6125-gpucc";
|
||||
reg = <0x05990000 0x9000>;
|
||||
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
|
||||
<&gcc GCC_GPU_GPLL0_CLK_SRC>;
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
};
|
||||
...
|
||||
@@ -0,0 +1,60 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm6375-gpucc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Graphics Clock & Reset Controller on SM6375
|
||||
|
||||
maintainers:
|
||||
- Konrad Dybcio <konrad.dybcio@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm graphics clock control module provides clocks, resets and power
|
||||
domains on Qualcomm SoCs.
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sm6375-gpucc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sm6375-gpucc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: GPLL0 main branch source
|
||||
- description: GPLL0 div branch source
|
||||
- description: SNoC DVM GFX source
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,sm6375-gcc.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clock-controller@5990000 {
|
||||
compatible = "qcom,sm6375-gpucc";
|
||||
reg = <0 0x05990000 0 0x9000>;
|
||||
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
|
||||
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
|
||||
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>,
|
||||
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
};
|
||||
...
|
||||
52
Documentation/devicetree/bindings/clock/qcom,sm7150-gcc.yaml
Normal file
52
Documentation/devicetree/bindings/clock/qcom,sm7150-gcc.yaml
Normal file
@@ -0,0 +1,52 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm7150-gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller on SM7150
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Danila Tikhonov <danila@jiaxyga.com>
|
||||
- David Wronek <davidwronek@gmail.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on SM7150
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sm7150-gcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm7150-gcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board XO Active-Only source
|
||||
- description: Sleep clock source
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,sm7150-gcc";
|
||||
reg = <0x00100000 0x001f0000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@@ -37,6 +37,7 @@ properties:
|
||||
- samsung,exynos850-cmu-cmgp
|
||||
- samsung,exynos850-cmu-core
|
||||
- samsung,exynos850-cmu-dpu
|
||||
- samsung,exynos850-cmu-g3d
|
||||
- samsung,exynos850-cmu-hsi
|
||||
- samsung,exynos850-cmu-is
|
||||
- samsung,exynos850-cmu-mfcmscl
|
||||
@@ -169,6 +170,24 @@ allOf:
|
||||
- const: oscclk
|
||||
- const: dout_dpu
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos850-cmu-g3d
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: G3D clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: dout_g3d_switch
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@@ -91,20 +91,21 @@ allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sdx55-apcs-gcc
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sdx55-apcs-gcc
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: reference clock
|
||||
- description: primary pll parent of the clock driver
|
||||
- description: auxiliary parent
|
||||
- description: reference clock
|
||||
clock-names:
|
||||
items:
|
||||
- const: ref
|
||||
- const: pll
|
||||
- const: aux
|
||||
- const: ref
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@@ -0,0 +1,42 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/power/qcom,kpss-acc-v2.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) v2
|
||||
|
||||
maintainers:
|
||||
- Christian Marangi <ansuelsmth@gmail.com>
|
||||
|
||||
description:
|
||||
The KPSS ACC provides clock, power manager, and reset control to a Krait CPU.
|
||||
There is one ACC register region per CPU within the KPSS remapped region as
|
||||
well as an alias register region that remaps accesses to the ACC associated
|
||||
with the CPU accessing the region. ACC v2 is currently used as a
|
||||
power-manager for enabling the cpu.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,kpss-acc-v2
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Base address and size of the register region
|
||||
- description: Optional base address and size of the alias register region
|
||||
minItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
power-manager@f9088000 {
|
||||
compatible = "qcom,kpss-acc-v2";
|
||||
reg = <0xf9088000 0x1000>,
|
||||
<0xf9008000 0x1000>;
|
||||
};
|
||||
...
|
||||
Reference in New Issue
Block a user