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dt-bindings: clock: ipq5424-apss-clk: Add ipq5424 apss clock controller

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The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
The RCG and PLL have a separate register space from the GCC.
Also the L3 cache has a separate pll and needs to be scaled along
with the CPU.

Co-developed-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
[ Added interconnect related changes ]
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20250811090954.2854440-2-quic_varada@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Sricharan Ramabadhran
2025-08-11 14:39:51 +05:30
committed by Bjorn Andersson
parent 8f5ae30d69
commit c17ccefb61
3 changed files with 64 additions and 0 deletions
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6
include/dt-bindings/clock/qcom,apss-ipq.h
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@@ -8,5 +8,11 @@
#define APCS_ALIAS0_CLK_SRC 0
#define APCS_ALIAS0_CORE_CLK 1
#define APSS_PLL_EARLY 2
#define APSS_SILVER_CLK_SRC 3
#define APSS_SILVER_CORE_CLK 4
#define L3_PLL 5
#define L3_CLK_SRC 6
#define L3_CORE_CLK 7
#endif