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dpll: add phase-offset-monitor feature to netlink spec
Add enum dpll_feature_state for control over features. Add dpll device level attribute: DPLL_A_PHASE_OFFSET_MONITOR - to allow control over a phase offset monitor feature. Attribute is present and shall return current state of a feature (enum dpll_feature_state), if the device driver provides such capability, otherwie attribute shall not be present. Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com> Reviewed-by: Milena Olech <milena.olech@intel.com> Reviewed-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com> Acked-by: Vadim Fedorenko <vadim.fedorenko@linux.dev> Link: https://patch.msgid.link/20250612152835.1703397-2-arkadiusz.kubalewski@intel.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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committed by
Jakub Kicinski
parent
bd1d76a6f1
commit
c035e73603
@@ -192,6 +192,17 @@ enum dpll_pin_capabilities {
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#define DPLL_PHASE_OFFSET_DIVIDER 1000
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/**
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* enum dpll_feature_state - Allow control (enable/disable) and status checking
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* over features.
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* @DPLL_FEATURE_STATE_DISABLE: feature shall be disabled
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* @DPLL_FEATURE_STATE_ENABLE: feature shall be enabled
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*/
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enum dpll_feature_state {
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DPLL_FEATURE_STATE_DISABLE,
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DPLL_FEATURE_STATE_ENABLE,
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};
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enum dpll_a {
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DPLL_A_ID = 1,
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DPLL_A_MODULE_NAME,
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@@ -204,6 +215,7 @@ enum dpll_a {
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DPLL_A_TYPE,
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DPLL_A_LOCK_STATUS_ERROR,
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DPLL_A_CLOCK_QUALITY_LEVEL,
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DPLL_A_PHASE_OFFSET_MONITOR,
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__DPLL_A_MAX,
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DPLL_A_MAX = (__DPLL_A_MAX - 1)
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