From bf8cdde4ef35b47cff5611a2a7062ac6a64fa7ff Mon Sep 17 00:00:00 2001 From: Daniil Agalakov Date: Wed, 15 Jul 2026 15:58:48 +0300 Subject: [PATCH] net: hns: use u32 for register offset in RCB TX coalescing In both hns_rcb_get_tx_coalesced_frames() and hns_rcb_set_tx_coalesced_frames(), the local variable reg holds a register offset passed to dsaf_read_dev() or dsaf_write_dev(). Register offsets on this hardware are 32-bit values. Use u32 for reg to match the register access interfaces and avoid implying that 64-bit offsets are supported. Signed-off-by: Daniil Agalakov Signed-off-by: Daniil Iskhakov Link: https://patch.msgid.link/20260715125856.19346-1-dish@amicon.ru Signed-off-by: Jakub Kicinski --- drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c index 635b3a95dd82..3c4e4e8ca140 100644 --- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c +++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c @@ -563,7 +563,7 @@ u32 hns_rcb_get_rx_coalesced_frames( u32 hns_rcb_get_tx_coalesced_frames( struct rcb_common_cb *rcb_common, u32 port_idx) { - u64 reg; + u32 reg; reg = RCB_CFG_PKTLINE_REG + (port_idx + HNS_RCB_TX_PKTLINE_OFFSET) * 4; return dsaf_read_dev(rcb_common, reg); @@ -634,7 +634,7 @@ int hns_rcb_set_tx_coalesced_frames( { u32 old_waterline = hns_rcb_get_tx_coalesced_frames(rcb_common, port_idx); - u64 reg; + u32 reg; if (coalesced_frames == old_waterline) return 0;