From e249fc7d9b1cfa046bc448b27c3fde5619442a7a Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 2 Sep 2015 22:30:51 +0200 Subject: [PATCH 1/2] ARM: dts: nomadik: add accelerometer IRQ and pin setting The LIS3LV02DL accelerometer on the Nomadik NHK15 can generate IRQs by the DRDY line. Map this in the DTS file and set up the pin as input to the SoC. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-nomadik-nhk15.dts | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ste-nomadik-nhk15.dts b/arch/arm/boot/dts/ste-nomadik-nhk15.dts index 4a21c6492dbb..d35aa88791ad 100644 --- a/arch/arm/boot/dts/ste-nomadik-nhk15.dts +++ b/arch/arm/boot/dts/ste-nomadik-nhk15.dts @@ -57,8 +57,15 @@ nhk_cfg2 { }; }; }; + lis3lv02dl { + lis3lv02dl_nhk_mode: lis3lv02dl_nhk { + nhk_cfg1 { + pins = "GPIO82_C10"; // IRQ line + ste,input = <0>; + }; + }; + }; }; - src@101e0000 { /* These chrystal outputs are not used on this board */ disable-sxtalo; @@ -86,6 +93,10 @@ i2c0 { lis3lv02dl@1d { /* Accelerometer */ compatible = "st,lis3lv02dl-accel"; + interrupt-parent = <&gpio2>; + interrupts = <18 IRQ_TYPE_EDGE_RISING>; // GPIO 82 + pinctrl-0 = <&lis3lv02dl_nhk_mode>; + pinctrl-names = "default"; reg = <0x1d>; }; stmpe0: stmpe2401@43 { From a22d7768860aedcd9c4011075c4d3bc1eaaddd63 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 6 Oct 2015 12:03:27 +0200 Subject: [PATCH 2/2] ARM: dts: nomadik: add DMA engine and some channels This adds the DMA engine to the Nomadik and assigns the UART DMA channels. Both slave DMA for UARTs and the memcpy engine works fine, tested on the Nomadik NHK15. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-nomadik-stn8815.dtsi | 38 ++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi index e2be53343064..d2d532a9d783 100644 --- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi @@ -748,6 +748,9 @@ uart0: uart@101fd000 { clocks = <&uart0clk>, <&pclkuart0>; clock-names = "uartclk", "apb_pclk"; status = "disabled"; + dmas = <&dmac0 14 1>, + <&dmac0 15 1>; + dma-names = "rx", "tx"; }; uart1: uart@101fb000 { @@ -759,6 +762,9 @@ uart1: uart@101fb000 { clock-names = "uartclk", "apb_pclk"; pinctrl-names = "default"; pinctrl-0 = <&uart1_default_mux>; + dmas = <&dmac1 22 1>, + <&dmac1 23 1>; + dma-names = "rx", "tx"; }; uart2: uart@101f2000 { @@ -769,6 +775,9 @@ uart2: uart@101f2000 { clocks = <&uart2clk>, <&pclkuart2>; clock-names = "uartclk", "apb_pclk"; status = "disabled"; + dmas = <&dmac1 30 1>, + <&dmac1 31 1>; + dma-names = "rx", "tx"; }; rng: rng@101b0000 { @@ -813,5 +822,34 @@ mmcsd: sdi@101f6000 { pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>; vmmc-supply = <&vmmc_regulator>; }; + + dmac0: dma-controller@10130000 { + compatible = "arm,pl080", "arm,primecell"; + reg = <0x10130000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <15>; + clocks = <&hclkdma0>; + clock-names = "apb_pclk"; + lli-bus-interface-ahb1; + lli-bus-interface-ahb2; + mem-bus-interface-ahb2; + memcpy-burst-size = <256>; + memcpy-bus-width = <32>; + #dma-cells = <2>; + }; + dmac1: dma-controller@10150000 { + compatible = "arm,pl080", "arm,primecell"; + reg = <0x10150000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <13>; + clocks = <&hclkdma1>; + clock-names = "apb_pclk"; + lli-bus-interface-ahb1; + lli-bus-interface-ahb2; + mem-bus-interface-ahb2; + memcpy-burst-size = <256>; + memcpy-bus-width = <32>; + #dma-cells = <2>; + }; }; };