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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
* 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: (49 commits) [POWERPC] Add zImage.iseries to arch/powerpc/boot/.gitignore [POWERPC] bootwrapper: fix build error on virtex405-head.S [POWERPC] 4xx: Fix 460GT support to not enable FPU [POWERPC] 4xx: Add NOR FLASH entries to Canyonlands and Glacier dts [POWERPC] Xilinx: of_serial support for Xilinx uart 16550. [POWERPC] Xilinx: boot support for Xilinx uart 16550. [POWERPC] celleb: Add support for PCI Express [POWERPC] celleb: Move miscellaneous files for Beat [POWERPC] celleb: Move a file for SPU on Beat [POWERPC] celleb: Move files for Beat mmu and iommu [POWERPC] celleb: Move files for Beat hvcall interfaces [POWERPC] celleb: Move the SCC related code for celleb [POWERPC] celleb: Move the files for celleb base support [POWERPC] celleb: Consolidate io-workarounds code [POWERPC] cell: Generalize io-workarounds code [POWERPC] Add CONFIG_PPC_PSERIES_DEBUG to enable debugging for platforms/pseries [POWERPC] Convert from DBG() to pr_debug() in platforms/pseries/ [POWERPC] Register udbg console early on pseries LPAR [POWERPC] Mark udbg console as CON_ANYTIME, ie. callable early in boot [POWERPC] Set udbg_console index to 0 ...
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@@ -2601,6 +2601,17 @@ platforms are moved over to use the flattened-device-tree model.
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differ between different families. May be
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'virtex2p', 'virtex4', or 'virtex5'.
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vi) Xilinx Uart 16550
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Xilinx UART 16550 devices are very similar to the NS16550 but with
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different register spacing and an offset from the base address.
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Requred properties:
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- clock-frequency : Frequency of the clock input
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- reg-offset : A value of 3 is required
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- reg-shift : A value of 2 is required
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p) Freescale Synchronous Serial Interface
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The SSI is a serial device that communicates with audio codecs. It can
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