From 4c5773f9f5462dcb372857813918bbfe8c0cdcdd Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 28 May 2016 11:54:12 +0200 Subject: [PATCH 01/41] dt-bindings: clock: Add license and reformat Exynos5410 clock IDs Add license and copyrights (file introduced in 2014) to header with Exynos5410 clock IDs. Additionally reformat it to improve readability. Signed-off-by: Krzysztof Kozlowski Acked-by: Stephen Boyd Reviewed-by: Javier Martinez Canillas Signed-off-by: Sylwester Nawrocki --- include/dt-bindings/clock/exynos5410.h | 54 +++++++++++++++----------- 1 file changed, 32 insertions(+), 22 deletions(-) diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h index 9b180f032e2d..213f19e02870 100644 --- a/include/dt-bindings/clock/exynos5410.h +++ b/include/dt-bindings/clock/exynos5410.h @@ -1,33 +1,43 @@ +/* + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Device Tree binding constants for Exynos5421 clock controller. +*/ + #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H #define _DT_BINDINGS_CLOCK_EXYNOS_5410_H /* core clocks */ -#define CLK_FIN_PLL 1 -#define CLK_FOUT_APLL 2 -#define CLK_FOUT_CPLL 3 -#define CLK_FOUT_MPLL 4 -#define CLK_FOUT_BPLL 5 -#define CLK_FOUT_KPLL 6 +#define CLK_FIN_PLL 1 +#define CLK_FOUT_APLL 2 +#define CLK_FOUT_CPLL 3 +#define CLK_FOUT_MPLL 4 +#define CLK_FOUT_BPLL 5 +#define CLK_FOUT_KPLL 6 /* gate for special clocks (sclk) */ -#define CLK_SCLK_UART0 128 -#define CLK_SCLK_UART1 129 -#define CLK_SCLK_UART2 130 -#define CLK_SCLK_UART3 131 -#define CLK_SCLK_MMC0 132 -#define CLK_SCLK_MMC1 133 -#define CLK_SCLK_MMC2 134 +#define CLK_SCLK_UART0 128 +#define CLK_SCLK_UART1 129 +#define CLK_SCLK_UART2 130 +#define CLK_SCLK_UART3 131 +#define CLK_SCLK_MMC0 132 +#define CLK_SCLK_MMC1 133 +#define CLK_SCLK_MMC2 134 /* gate clocks */ -#define CLK_UART0 257 -#define CLK_UART1 258 -#define CLK_UART2 259 -#define CLK_UART3 260 -#define CLK_MCT 315 -#define CLK_MMC0 351 -#define CLK_MMC1 352 -#define CLK_MMC2 353 +#define CLK_UART0 257 +#define CLK_UART1 258 +#define CLK_UART2 259 +#define CLK_UART3 260 +#define CLK_MCT 315 +#define CLK_MMC0 351 +#define CLK_MMC1 352 +#define CLK_MMC2 353 -#define CLK_NR_CLKS 512 +#define CLK_NR_CLKS 512 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */ From 5cd3535a27a7cf8fc4070b499d66e419e7e72b61 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 28 May 2016 11:54:13 +0200 Subject: [PATCH 02/41] dt-bindings: clock: Add PWM and USB clock IDs to Exynos5410 Add IDs for PWM and USB clocks to Exynos5410. Use the same number as for Exynos5420 just in case in future these drivers were merged. Signed-off-by: Krzysztof Kozlowski Acked-by: Stephen Boyd Reviewed-by: Javier Martinez Canillas Signed-off-by: Sylwester Nawrocki --- include/dt-bindings/clock/exynos5410.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h index 213f19e02870..34c8e96987a1 100644 --- a/include/dt-bindings/clock/exynos5410.h +++ b/include/dt-bindings/clock/exynos5410.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * Copyright (c) 2016 Krzysztof Kozlowski * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -27,16 +28,25 @@ #define CLK_SCLK_MMC0 132 #define CLK_SCLK_MMC1 133 #define CLK_SCLK_MMC2 134 +#define CLK_SCLK_USBD300 150 +#define CLK_SCLK_USBD301 151 +#define CLK_SCLK_USBPHY300 152 +#define CLK_SCLK_USBPHY301 153 +#define CLK_SCLK_PWM 155 /* gate clocks */ #define CLK_UART0 257 #define CLK_UART1 258 #define CLK_UART2 259 #define CLK_UART3 260 +#define CLK_PWM 279 #define CLK_MCT 315 #define CLK_MMC0 351 #define CLK_MMC1 352 #define CLK_MMC2 353 +#define CLK_USBH20 365 +#define CLK_USBD300 366 +#define CLK_USBD301 367 #define CLK_NR_CLKS 512 From ed1e1505db0c116affdfab01e650c44a9c459c65 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 28 May 2016 11:54:29 +0200 Subject: [PATCH 03/41] dt-bindings: clock: Add I2C, HSI2C and RTC clock IDs to Exynos5410 Add IDs for I2C, USI (HSI2C) and RTC clocks to Exynos5410. Use the same number as for Exynos5420 just in case in future these drivers are merged. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Signed-off-by: Sylwester Nawrocki --- include/dt-bindings/clock/exynos5410.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h index 34c8e96987a1..e94b7bbfd6af 100644 --- a/include/dt-bindings/clock/exynos5410.h +++ b/include/dt-bindings/clock/exynos5410.h @@ -38,9 +38,18 @@ #define CLK_UART0 257 #define CLK_UART1 258 #define CLK_UART2 259 +#define CLK_I2C0 261 +#define CLK_I2C1 262 +#define CLK_I2C2 263 +#define CLK_I2C3 264 +#define CLK_USI0 265 +#define CLK_USI1 266 +#define CLK_USI2 267 +#define CLK_USI3 268 #define CLK_UART3 260 #define CLK_PWM 279 #define CLK_MCT 315 +#define CLK_RTC 317 #define CLK_MMC0 351 #define CLK_MMC1 352 #define CLK_MMC2 353 From 109869f522852094393b829918b56327c0feb360 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 31 May 2016 20:39:00 +0200 Subject: [PATCH 04/41] dt-bindings: clock: Add TMU clock ID to Exynos5410 Add ID for TMU clock to Exynos5410. Use the same number as for Exynos5420 just in case in future these drivers were merged. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Signed-off-by: Sylwester Nawrocki --- include/dt-bindings/clock/exynos5410.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h index e94b7bbfd6af..705b2aa84317 100644 --- a/include/dt-bindings/clock/exynos5410.h +++ b/include/dt-bindings/clock/exynos5410.h @@ -50,6 +50,7 @@ #define CLK_PWM 279 #define CLK_MCT 315 #define CLK_RTC 317 +#define CLK_TMU 318 #define CLK_MMC0 351 #define CLK_MMC1 352 #define CLK_MMC2 353 From 4528dd8ed477bf202bd33ee48d38d656672d37f8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 1 Jun 2016 11:45:49 +0200 Subject: [PATCH 05/41] dt-bindings: clock: Add watchdog and SSS clock IDs to Exynos5410 Add IDs for watchdog and Security SubSystem to Exynos5410. Use the same number as for Exynos5420 just in case in future these drivers were merged. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Signed-off-by: Sylwester Nawrocki --- include/dt-bindings/clock/exynos5410.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h index 705b2aa84317..85b467b3a207 100644 --- a/include/dt-bindings/clock/exynos5410.h +++ b/include/dt-bindings/clock/exynos5410.h @@ -49,6 +49,7 @@ #define CLK_UART3 260 #define CLK_PWM 279 #define CLK_MCT 315 +#define CLK_WDT 316 #define CLK_RTC 317 #define CLK_TMU 318 #define CLK_MMC0 351 @@ -57,6 +58,7 @@ #define CLK_USBH20 365 #define CLK_USBD300 366 #define CLK_USBD301 367 +#define CLK_SSS 471 #define CLK_NR_CLKS 512 From 9da752f0e37022e40de8f00891be958d351f4526 Mon Sep 17 00:00:00 2001 From: Alim Akhtar Date: Thu, 14 Apr 2016 10:12:52 +0530 Subject: [PATCH 06/41] clk: samsung: exynos7: Don't gate CMU_{CCORE, FSYS0} blocks clock This patch adds CLK_IS_CRITICAL flag to ACLK_CCORE_133 and ACLK_FSYS0_200 clocks. These clocks are critical for accessing CMU_CCORE and CMU_FSYS0 blocks registers. Let these clocks to be enabled all the time. Signed-off-by: Alim Akhtar Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos7.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c index ad68d463b12c..03a82da63910 100644 --- a/drivers/clk/samsung/clk-exynos7.c +++ b/drivers/clk/samsung/clk-exynos7.c @@ -146,7 +146,7 @@ static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = { static struct samsung_gate_clock topc_gate_clks[] __initdata = { GATE(ACLK_CCORE_133, "aclk_ccore_133", "dout_aclk_ccore_133", - ENABLE_ACLK_TOPC0, 4, 0, 0), + ENABLE_ACLK_TOPC0, 4, CLK_IS_CRITICAL, 0), GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532", ENABLE_ACLK_TOPC1, 20, 0, 0), @@ -539,7 +539,8 @@ static struct samsung_gate_clock top1_gate_clks[] __initdata = { ENABLE_SCLK_TOP1_FSYS11, 12, CLK_SET_RATE_PARENT, 0), GATE(CLK_ACLK_FSYS0_200, "aclk_fsys0_200", "dout_aclk_fsys0_200", - ENABLE_ACLK_TOP13, 28, CLK_SET_RATE_PARENT, 0), + ENABLE_ACLK_TOP13, 28, CLK_SET_RATE_PARENT | + CLK_IS_CRITICAL, 0), GATE(CLK_ACLK_FSYS1_200, "aclk_fsys1_200", "dout_aclk_fsys1_200", ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT, 0), From dfb86ade53a94963eafe0d78360616faa90cde3b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 9 May 2016 19:32:31 +0200 Subject: [PATCH 07/41] clk: samsung: Remove useless check for return value of samsung_clk_init The samsung_clk_init() cannot return NULL. Either it returns allocated memory or it panics. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos4.c | 2 -- drivers/clk/samsung/clk-exynos5250.c | 3 +-- drivers/clk/samsung/clk-exynos5420.c | 2 -- drivers/clk/samsung/clk-exynos5440.c | 2 -- drivers/clk/samsung/clk-s3c2410.c | 2 -- drivers/clk/samsung/clk-s3c2412.c | 2 -- drivers/clk/samsung/clk-s3c2443.c | 2 -- drivers/clk/samsung/clk-s3c64xx.c | 2 -- drivers/clk/samsung/clk-s5pv210.c | 2 -- 9 files changed, 1 insertion(+), 18 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 7b3d0f975987..2f458233908b 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -1450,8 +1450,6 @@ static void __init exynos4_clk_init(struct device_node *np, panic("%s: failed to map registers\n", __func__); ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); - if (!ctx) - panic("%s: unable to allocate context.\n", __func__); samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks, ARRAY_SIZE(exynos4_fixed_rate_ext_clks), diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 837197db4ffb..d8621cf31786 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -805,8 +805,7 @@ static void __init exynos5250_clk_init(struct device_node *np) } ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); - if (!ctx) - panic("%s: unable to allocate context.\n", __func__); + samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks, ARRAY_SIZE(exynos5250_fixed_rate_ext_clks), ext_clk_match); diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 92382cef9f90..770c0f007c6b 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1356,8 +1356,6 @@ static void __init exynos5x_clk_init(struct device_node *np, exynos5x_soc = soc; ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); - if (!ctx) - panic("%s: unable to allocate context.\n", __func__); samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks, ARRAY_SIZE(exynos5x_fixed_rate_ext_clks), diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c index c57cff1e1798..22c73d4a5ee3 100644 --- a/drivers/clk/samsung/clk-exynos5440.c +++ b/drivers/clk/samsung/clk-exynos5440.c @@ -125,8 +125,6 @@ static void __init exynos5440_clk_init(struct device_node *np) } ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); - if (!ctx) - panic("%s: unable to allocate context.\n", __func__); samsung_clk_of_register_fixed_ext(ctx, exynos5440_fixed_rate_ext_clks, ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match); diff --git a/drivers/clk/samsung/clk-s3c2410.c b/drivers/clk/samsung/clk-s3c2410.c index d7b011c1fcf8..d7a1e772d95a 100644 --- a/drivers/clk/samsung/clk-s3c2410.c +++ b/drivers/clk/samsung/clk-s3c2410.c @@ -374,8 +374,6 @@ void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f, } ctx = samsung_clk_init(np, reg_base, NR_CLKS); - if (!ctx) - panic("%s: unable to allocate context.\n", __func__); /* Register external clocks only in non-dt cases */ if (!np) diff --git a/drivers/clk/samsung/clk-s3c2412.c b/drivers/clk/samsung/clk-s3c2412.c index effe3736ec6b..ec873ee15d37 100644 --- a/drivers/clk/samsung/clk-s3c2412.c +++ b/drivers/clk/samsung/clk-s3c2412.c @@ -265,8 +265,6 @@ void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f, } ctx = samsung_clk_init(np, reg_base, NR_CLKS); - if (!ctx) - panic("%s: unable to allocate context.\n", __func__); /* Register external clocks only in non-dt cases */ if (!np) diff --git a/drivers/clk/samsung/clk-s3c2443.c b/drivers/clk/samsung/clk-s3c2443.c index 37562783b25e..5e24a17e10e6 100644 --- a/drivers/clk/samsung/clk-s3c2443.c +++ b/drivers/clk/samsung/clk-s3c2443.c @@ -400,8 +400,6 @@ void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f, } ctx = samsung_clk_init(np, reg_base, NR_CLKS); - if (!ctx) - panic("%s: unable to allocate context.\n", __func__); /* Register external clocks only in non-dt cases */ if (!np) diff --git a/drivers/clk/samsung/clk-s3c64xx.c b/drivers/clk/samsung/clk-s3c64xx.c index 60aa775bd374..a48bd5f17330 100644 --- a/drivers/clk/samsung/clk-s3c64xx.c +++ b/drivers/clk/samsung/clk-s3c64xx.c @@ -471,8 +471,6 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f, } ctx = samsung_clk_init(np, reg_base, NR_CLKS); - if (!ctx) - panic("%s: unable to allocate context.\n", __func__); /* Register external clocks. */ if (!np) diff --git a/drivers/clk/samsung/clk-s5pv210.c b/drivers/clk/samsung/clk-s5pv210.c index 52302262045d..fd2725710a6f 100644 --- a/drivers/clk/samsung/clk-s5pv210.c +++ b/drivers/clk/samsung/clk-s5pv210.c @@ -784,8 +784,6 @@ static void __init __s5pv210_clk_init(struct device_node *np, struct samsung_clk_provider *ctx; ctx = samsung_clk_init(np, reg_base, NR_CLKS); - if (!ctx) - panic("%s: unable to allocate context.\n", __func__); samsung_clk_register_mux(ctx, early_mux_clks, ARRAY_SIZE(early_mux_clks)); From d8137e035f6f36002943f32a2aa809cfde74bbc2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 16 May 2016 10:26:47 +0200 Subject: [PATCH 08/41] clk: samsung: clkout: Add support for Exynos5410 Add compatible for Exynos5410 so the PMU on this SoC would provide CLKOUT. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos-clkout.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos-clkout.c b/drivers/clk/samsung/clk-exynos-clkout.c index 7cd02ff37a1f..96fab6cfb202 100644 --- a/drivers/clk/samsung/clk-exynos-clkout.c +++ b/drivers/clk/samsung/clk-exynos-clkout.c @@ -151,6 +151,8 @@ static void __init exynos5_clkout_init(struct device_node *node) } CLK_OF_DECLARE(exynos5250_clkout, "samsung,exynos5250-pmu", exynos5_clkout_init); +CLK_OF_DECLARE(exynos5410_clkout, "samsung,exynos5410-pmu", + exynos5_clkout_init); CLK_OF_DECLARE(exynos5420_clkout, "samsung,exynos5420-pmu", exynos5_clkout_init); CLK_OF_DECLARE(exynos5433_clkout, "samsung,exynos5433-pmu", From 9f92c0bace11a84c57cdd62d96de8113d1aba89f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 11 May 2016 14:01:57 +0200 Subject: [PATCH 09/41] clk: samsung: Constify clock init data with clock arrays samsung_cmu_register_one() can accept pointer to const initialization data: struct samsung_cmu_info. The members of the latter can also be pointers to const data. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk.c | 2 +- drivers/clk/samsung/clk.h | 16 ++++++++-------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c index f38a6c49f744..e4d14589cc4a 100644 --- a/drivers/clk/samsung/clk.c +++ b/drivers/clk/samsung/clk.c @@ -381,7 +381,7 @@ static void samsung_clk_sleep_init(void __iomem *reg_base, */ struct samsung_clk_provider * __init samsung_cmu_register_one( struct device_node *np, - struct samsung_cmu_info *cmu) + const struct samsung_cmu_info *cmu) { void __iomem *reg_base; struct samsung_clk_provider *ctx; diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h index aa872d2c5105..61db98dd01a2 100644 --- a/drivers/clk/samsung/clk.h +++ b/drivers/clk/samsung/clk.h @@ -330,28 +330,28 @@ struct samsung_clock_reg_cache { struct samsung_cmu_info { /* list of pll clocks and respective count */ - struct samsung_pll_clock *pll_clks; + const struct samsung_pll_clock *pll_clks; unsigned int nr_pll_clks; /* list of mux clocks and respective count */ - struct samsung_mux_clock *mux_clks; + const struct samsung_mux_clock *mux_clks; unsigned int nr_mux_clks; /* list of div clocks and respective count */ - struct samsung_div_clock *div_clks; + const struct samsung_div_clock *div_clks; unsigned int nr_div_clks; /* list of gate clocks and respective count */ - struct samsung_gate_clock *gate_clks; + const struct samsung_gate_clock *gate_clks; unsigned int nr_gate_clks; /* list of fixed clocks and respective count */ - struct samsung_fixed_rate_clock *fixed_clks; + const struct samsung_fixed_rate_clock *fixed_clks; unsigned int nr_fixed_clks; /* list of fixed factor clocks and respective count */ - struct samsung_fixed_factor_clock *fixed_factor_clks; + const struct samsung_fixed_factor_clock *fixed_factor_clks; unsigned int nr_fixed_factor_clks; /* total number of clocks with IDs assigned*/ unsigned int nr_clk_ids; /* list and number of clocks registers */ - unsigned long *clk_regs; + const unsigned long *clk_regs; unsigned int nr_clk_regs; }; @@ -395,7 +395,7 @@ extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx, extern struct samsung_clk_provider __init *samsung_cmu_register_one( struct device_node *, - struct samsung_cmu_info *); + const struct samsung_cmu_info *); extern unsigned long _get_rate(const char *clk_name); From b3a96eed8e84780d300b79b58047ea277ba358b7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 11 May 2016 14:01:58 +0200 Subject: [PATCH 10/41] clk: samsung: exynos3250: Move platform driver and of_device_id to init section The platform_driver and of_device_id structs can be moved to init section because they are referenced only from subsys_initcall-level function. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos3250.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c index 16575ee874cb..e26b04fea33b 100644 --- a/drivers/clk/samsung/clk-exynos3250.c +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -1079,12 +1079,12 @@ static int __init exynos3250_cmu_isp_probe(struct platform_device *pdev) return 0; } -static const struct of_device_id exynos3250_cmu_isp_of_match[] = { +static const struct of_device_id exynos3250_cmu_isp_of_match[] __initconst = { { .compatible = "samsung,exynos3250-cmu-isp", }, { /* sentinel */ } }; -static struct platform_driver exynos3250_cmu_isp_driver = { +static struct platform_driver exynos3250_cmu_isp_driver __initdata = { .driver = { .name = "exynos3250-cmu-isp", .of_match_table = exynos3250_cmu_isp_of_match, From 0a7d82e6ee75db55b99096080ff4f12ac9a7aec3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 11 May 2016 14:01:59 +0200 Subject: [PATCH 11/41] clk: samsung: exynos3250: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos3250.c | 36 ++++++++++++++-------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c index e26b04fea33b..057c3f0d0e35 100644 --- a/drivers/clk/samsung/clk-exynos3250.c +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -103,7 +103,7 @@ #define PWR_CTRL1_USE_CORE1_WFI (1 << 1) #define PWR_CTRL1_USE_CORE0_WFI (1 << 0) -static unsigned long exynos3250_cmu_clk_regs[] __initdata = { +static const unsigned long exynos3250_cmu_clk_regs[] __initconst = { SRC_LEFTBUS, DIV_LEFTBUS, GATE_IP_LEFTBUS, @@ -226,7 +226,7 @@ PNAME(group_sclk_fimd0_p) = { "xxti", "xusbxti", PNAME(mout_mfc_p) = { "mout_mfc_0", "mout_mfc_1" }; PNAME(mout_g3d_p) = { "mout_g3d_0", "mout_g3d_1" }; -static struct samsung_fixed_factor_clock fixed_factor_clks[] __initdata = { +static const struct samsung_fixed_factor_clock fixed_factor_clks[] __initconst = { FFACTOR(0, "sclk_mpll_1600", "mout_mpll", 1, 1, 0), FFACTOR(0, "sclk_mpll_mif", "mout_mpll", 1, 2, 0), FFACTOR(0, "sclk_bpll", "fout_bpll", 1, 2, 0), @@ -237,7 +237,7 @@ static struct samsung_fixed_factor_clock fixed_factor_clks[] __initdata = { FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0), }; -static struct samsung_mux_clock mux_clks[] __initdata = { +static const struct samsung_mux_clock mux_clks[] __initconst = { /* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done @@ -326,7 +326,7 @@ static struct samsung_mux_clock mux_clks[] __initdata = { CLK_SET_RATE_PARENT, 0), }; -static struct samsung_div_clock div_clks[] __initdata = { +static const struct samsung_div_clock div_clks[] __initconst = { /* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done @@ -429,7 +429,7 @@ static struct samsung_div_clock div_clks[] __initdata = { DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3), }; -static struct samsung_gate_clock gate_clks[] __initdata = { +static const struct samsung_gate_clock gate_clks[] __initconst = { /* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done @@ -669,7 +669,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = { }; /* APLL & MPLL & BPLL & UPLL */ -static struct samsung_pll_rate_table exynos3250_pll_rates[] = { +static const struct samsung_pll_rate_table exynos3250_pll_rates[] = { PLL_35XX_RATE(1200000000, 400, 4, 1), PLL_35XX_RATE(1100000000, 275, 3, 1), PLL_35XX_RATE(1066000000, 533, 6, 1), @@ -691,7 +691,7 @@ static struct samsung_pll_rate_table exynos3250_pll_rates[] = { }; /* EPLL */ -static struct samsung_pll_rate_table exynos3250_epll_rates[] = { +static const struct samsung_pll_rate_table exynos3250_epll_rates[] = { PLL_36XX_RATE(800000000, 200, 3, 1, 0), PLL_36XX_RATE(288000000, 96, 2, 2, 0), PLL_36XX_RATE(192000000, 128, 2, 3, 0), @@ -710,7 +710,7 @@ static struct samsung_pll_rate_table exynos3250_epll_rates[] = { }; /* VPLL */ -static struct samsung_pll_rate_table exynos3250_vpll_rates[] = { +static const struct samsung_pll_rate_table exynos3250_vpll_rates[] __initconst = { PLL_36XX_RATE(600000000, 100, 2, 1, 0), PLL_36XX_RATE(533000000, 266, 3, 2, 32768), PLL_36XX_RATE(519230987, 173, 2, 2, 5046), @@ -740,7 +740,7 @@ static struct samsung_pll_rate_table exynos3250_vpll_rates[] = { { /* sentinel */ } }; -static struct samsung_pll_clock exynos3250_plls[] __initdata = { +static const struct samsung_pll_clock exynos3250_plls[] __initconst = { PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, APLL_CON0, exynos3250_pll_rates), PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", @@ -772,7 +772,7 @@ static void __init exynos3_core_down_clock(void __iomem *reg_base) __raw_writel(0x0, reg_base + PWR_CTRL2); } -static struct samsung_cmu_info cmu_info __initdata = { +static const struct samsung_cmu_info cmu_info __initconst = { .pll_clks = exynos3250_plls, .nr_pll_clks = ARRAY_SIZE(exynos3250_plls), .mux_clks = mux_clks, @@ -848,7 +848,7 @@ CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init); #define EPLL_CON2 0x111c #define SRC_EPLL 0x1120 -static unsigned long exynos3250_cmu_dmc_clk_regs[] __initdata = { +static const unsigned long exynos3250_cmu_dmc_clk_regs[] __initconst = { BPLL_LOCK, BPLL_CON0, BPLL_CON1, @@ -874,7 +874,7 @@ PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", }; PNAME(mout_mpll_mif_p) = { "fin_pll", "sclk_mpll_mif", }; PNAME(mout_dphy_p) = { "mout_mpll_mif", "mout_bpll", }; -static struct samsung_mux_clock dmc_mux_clks[] __initdata = { +static const struct samsung_mux_clock dmc_mux_clks[] __initconst = { /* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done @@ -893,7 +893,7 @@ static struct samsung_mux_clock dmc_mux_clks[] __initdata = { MUX(CLK_MOUT_EPLL, "mout_epll", mout_epll_p, SRC_EPLL, 4, 1), }; -static struct samsung_div_clock dmc_div_clks[] __initdata = { +static const struct samsung_div_clock dmc_div_clks[] __initconst = { /* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done @@ -910,14 +910,14 @@ static struct samsung_div_clock dmc_div_clks[] __initdata = { DIV(CLK_DIV_DMCD, "div_dmcd", "div_dmc", DIV_DMC1, 11, 3), }; -static struct samsung_pll_clock exynos3250_dmc_plls[] __initdata = { +static const struct samsung_pll_clock exynos3250_dmc_plls[] __initconst = { PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, BPLL_CON0, exynos3250_pll_rates), PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, EPLL_CON0, exynos3250_epll_rates), }; -static struct samsung_cmu_info dmc_cmu_info __initdata = { +static const struct samsung_cmu_info dmc_cmu_info __initconst = { .pll_clks = exynos3250_dmc_plls, .nr_pll_clks = ARRAY_SIZE(exynos3250_dmc_plls), .mux_clks = dmc_mux_clks, @@ -947,7 +947,7 @@ CLK_OF_DECLARE(exynos3250_cmu_dmc, "samsung,exynos3250-cmu-dmc", #define GATE_IP_ISP1 0x804 #define GATE_SCLK_ISP 0x900 -static struct samsung_div_clock isp_div_clks[] __initdata = { +static const struct samsung_div_clock isp_div_clks[] __initconst = { /* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done @@ -967,7 +967,7 @@ static struct samsung_div_clock isp_div_clks[] __initdata = { DIV(CLK_DIV_MPWM, "div_mpwm", "div_isp1", DIV_ISP1, 0, 3), }; -static struct samsung_gate_clock isp_gate_clks[] __initdata = { +static const struct samsung_gate_clock isp_gate_clks[] __initconst = { /* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done @@ -1063,7 +1063,7 @@ static struct samsung_gate_clock isp_gate_clks[] __initdata = { GATE_SCLK_ISP, 0, CLK_IGNORE_UNUSED, 0), }; -static struct samsung_cmu_info isp_cmu_info __initdata = { +static const struct samsung_cmu_info isp_cmu_info __initconst = { .div_clks = isp_div_clks, .nr_div_clks = ARRAY_SIZE(isp_div_clks), .gate_clks = isp_gate_clks, From 8f3ac36de17ab056f43b509926ee81a09adae99b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 11 May 2016 14:02:00 +0200 Subject: [PATCH 12/41] clk: samsung: exynos4: Move local function to init section The local exynos4_get_xom() function is referenced only from other init-level functions. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos4.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 2f458233908b..5cac5b7892d7 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -1211,7 +1211,7 @@ static struct samsung_clock_alias exynos4x12_aliases[] __initdata = { * controller is first remapped and the value of XOM[0] bit is read to * determine the parent clock. */ -static unsigned long exynos4_get_xom(void) +static unsigned long __init exynos4_get_xom(void) { unsigned long xom = 0; void __iomem *chipid_base; From d0e4ca56958cea68dd9493a84c77a713e172da5c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 11 May 2016 14:02:01 +0200 Subject: [PATCH 13/41] clk: samsung: exynos4: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos4.c | 56 +++++++++++++++---------------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 5cac5b7892d7..13eaf4cb0dbc 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -169,7 +169,7 @@ static struct samsung_clk_reg_dump *exynos4_save_pll; * list of controller registers to be saved and restored during a * suspend/resume cycle. */ -static unsigned long exynos4210_clk_save[] __initdata = { +static const unsigned long exynos4210_clk_save[] __initconst = { E4210_SRC_IMAGE, E4210_SRC_LCD1, E4210_SRC_MASK_LCD1, @@ -181,7 +181,7 @@ static unsigned long exynos4210_clk_save[] __initdata = { PWR_CTRL1, }; -static unsigned long exynos4x12_clk_save[] __initdata = { +static const unsigned long exynos4x12_clk_save[] __initconst = { E4X12_GATE_IP_IMAGE, E4X12_GATE_IP_PERIR, E4X12_SRC_CAM1, @@ -192,7 +192,7 @@ static unsigned long exynos4x12_clk_save[] __initdata = { E4X12_PWR_CTRL2, }; -static unsigned long exynos4_clk_pll_regs[] __initdata = { +static const unsigned long exynos4_clk_pll_regs[] __initconst = { EPLL_LOCK, VPLL_LOCK, EPLL_CON0, @@ -203,7 +203,7 @@ static unsigned long exynos4_clk_pll_regs[] __initdata = { VPLL_CON2, }; -static unsigned long exynos4_clk_regs[] __initdata = { +static const unsigned long exynos4_clk_regs[] __initconst = { SRC_LEFTBUS, DIV_LEFTBUS, GATE_IP_LEFTBUS, @@ -505,28 +505,28 @@ static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata }; /* fixed rate clocks generated inside the soc */ -static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = { +static const struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initconst = { FRATE(0, "sclk_hdmi24m", NULL, 0, 24000000), FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", "hdmi", 0, 27000000), FRATE(0, "sclk_usbphy0", NULL, 0, 48000000), }; -static struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = { +static const struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initconst = { FRATE(0, "sclk_usbphy1", NULL, 0, 48000000), }; -static struct samsung_fixed_factor_clock exynos4_fixed_factor_clks[] __initdata = { +static const struct samsung_fixed_factor_clock exynos4_fixed_factor_clks[] __initconst = { FFACTOR(0, "sclk_apll_div_2", "sclk_apll", 1, 2, 0), FFACTOR(0, "fout_mpll_div_2", "fout_mpll", 1, 2, 0), FFACTOR(0, "fout_apll_div_2", "fout_apll", 1, 2, 0), FFACTOR(0, "arm_clk_div_2", "div_core2", 1, 2, 0), }; -static struct samsung_fixed_factor_clock exynos4210_fixed_factor_clks[] __initdata = { +static const struct samsung_fixed_factor_clock exynos4210_fixed_factor_clks[] __initconst = { FFACTOR(0, "sclk_mpll_div_2", "sclk_mpll", 1, 2, 0), }; -static struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __initdata = { +static const struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __initconst = { FFACTOR(0, "sclk_mpll_user_l_div_2", "mout_mpll_user_l", 1, 2, 0), FFACTOR(0, "sclk_mpll_user_r_div_2", "mout_mpll_user_r", 1, 2, 0), FFACTOR(0, "sclk_mpll_user_t_div_2", "mout_mpll_user_t", 1, 2, 0), @@ -534,7 +534,7 @@ static struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __initda }; /* list of mux clocks supported in all exynos4 soc's */ -static struct samsung_mux_clock exynos4_mux_clks[] __initdata = { +static const struct samsung_mux_clock exynos4_mux_clks[] __initconst = { MUX_FA(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0, "mout_apll"), @@ -555,11 +555,11 @@ static struct samsung_mux_clock exynos4_mux_clks[] __initdata = { }; /* list of mux clocks supported in exynos4210 soc */ -static struct samsung_mux_clock exynos4210_mux_early[] __initdata = { +static const struct samsung_mux_clock exynos4210_mux_early[] __initconst = { MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1), }; -static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { +static const struct samsung_mux_clock exynos4210_mux_clks[] __initconst = { MUX(0, "mout_gdl", sclk_ampll_p4210, SRC_LEFTBUS, 0, 1), MUX(0, "mout_clkout_leftbus", clkout_left_p4210, CLKOUT_CMU_LEFTBUS, 0, 5), @@ -622,7 +622,7 @@ static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { }; /* list of mux clocks supported in exynos4x12 soc */ -static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { +static const struct samsung_mux_clock exynos4x12_mux_clks[] __initconst = { MUX(0, "mout_mpll_user_l", mout_mpll_p, SRC_LEFTBUS, 4, 1), MUX(0, "mout_gdl", mout_gdl_p4x12, SRC_LEFTBUS, 0, 1), MUX(0, "mout_clkout_leftbus", clkout_left_p4x12, @@ -705,7 +705,7 @@ static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { }; /* list of divider clocks supported in all exynos4 soc's */ -static struct samsung_div_clock exynos4_div_clks[] __initdata = { +static const struct samsung_div_clock exynos4_div_clks[] __initconst = { DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3), DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3), DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus", @@ -795,7 +795,7 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = { }; /* list of divider clocks supported in exynos4210 soc */ -static struct samsung_div_clock exynos4210_div_clks[] __initdata = { +static const struct samsung_div_clock exynos4210_div_clks[] __initconst = { DIV(CLK_ACLK200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3), DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4), DIV(0, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4), @@ -806,7 +806,7 @@ static struct samsung_div_clock exynos4210_div_clks[] __initdata = { }; /* list of divider clocks supported in exynos4x12 soc */ -static struct samsung_div_clock exynos4x12_div_clks[] __initdata = { +static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = { DIV(0, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4), DIV(0, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4), DIV(0, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4), @@ -837,7 +837,7 @@ static struct samsung_div_clock exynos4x12_div_clks[] __initdata = { }; /* list of gate clocks supported in all exynos4 soc's */ -static struct samsung_gate_clock exynos4_gate_clks[] __initdata = { +static const struct samsung_gate_clock exynos4_gate_clks[] __initconst = { /* * After all Exynos4 based platforms are migrated to use device tree, * the device name and clock alias names specified below for some @@ -1043,7 +1043,7 @@ static struct samsung_gate_clock exynos4_gate_clks[] __initdata = { }; /* list of gate clocks supported in exynos4210 soc */ -static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = { +static const struct samsung_gate_clock exynos4210_gate_clks[] __initconst = { GATE(CLK_TVENC, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0), GATE(CLK_G2D, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0), GATE(CLK_ROTATOR, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0), @@ -1090,7 +1090,7 @@ static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = { }; /* list of gate clocks supported in exynos4x12 soc */ -static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { +static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = { GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0), GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0), GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0), @@ -1190,17 +1190,17 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { 0), }; -static struct samsung_clock_alias exynos4_aliases[] __initdata = { +static const struct samsung_clock_alias exynos4_aliases[] __initconst = { ALIAS(CLK_MOUT_CORE, NULL, "moutcore"), ALIAS(CLK_ARM_CLK, NULL, "armclk"), ALIAS(CLK_SCLK_APLL, NULL, "mout_apll"), }; -static struct samsung_clock_alias exynos4210_aliases[] __initdata = { +static const struct samsung_clock_alias exynos4210_aliases[] __initconst = { ALIAS(CLK_SCLK_MPLL, NULL, "mout_mpll"), }; -static struct samsung_clock_alias exynos4x12_aliases[] __initdata = { +static const struct samsung_clock_alias exynos4x12_aliases[] __initconst = { ALIAS(CLK_MOUT_MPLL_USER_C, NULL, "mout_mpll"), }; @@ -1264,7 +1264,7 @@ static const struct of_device_id ext_clk_match[] __initconst = { }; /* PLLs PMS values */ -static struct samsung_pll_rate_table exynos4210_apll_rates[] __initdata = { +static const struct samsung_pll_rate_table exynos4210_apll_rates[] __initconst = { PLL_45XX_RATE(1200000000, 150, 3, 1, 28), PLL_45XX_RATE(1000000000, 250, 6, 1, 28), PLL_45XX_RATE( 800000000, 200, 6, 1, 28), @@ -1277,7 +1277,7 @@ static struct samsung_pll_rate_table exynos4210_apll_rates[] __initdata = { { /* sentinel */ } }; -static struct samsung_pll_rate_table exynos4210_epll_rates[] __initdata = { +static const struct samsung_pll_rate_table exynos4210_epll_rates[] __initconst = { PLL_4600_RATE(192000000, 48, 3, 1, 0, 0), PLL_4600_RATE(180633605, 45, 3, 1, 10381, 0), PLL_4600_RATE(180000000, 45, 3, 1, 0, 0), @@ -1288,7 +1288,7 @@ static struct samsung_pll_rate_table exynos4210_epll_rates[] __initdata = { { /* sentinel */ } }; -static struct samsung_pll_rate_table exynos4210_vpll_rates[] __initdata = { +static const struct samsung_pll_rate_table exynos4210_vpll_rates[] __initconst = { PLL_4650_RATE(360000000, 44, 3, 0, 1024, 0, 14, 0), PLL_4650_RATE(324000000, 53, 2, 1, 1024, 1, 1, 1), PLL_4650_RATE(259617187, 63, 3, 1, 1950, 0, 20, 1), @@ -1297,7 +1297,7 @@ static struct samsung_pll_rate_table exynos4210_vpll_rates[] __initdata = { { /* sentinel */ } }; -static struct samsung_pll_rate_table exynos4x12_apll_rates[] __initdata = { +static const struct samsung_pll_rate_table exynos4x12_apll_rates[] __initconst = { PLL_35XX_RATE(1500000000, 250, 4, 0), PLL_35XX_RATE(1400000000, 175, 3, 0), PLL_35XX_RATE(1300000000, 325, 6, 0), @@ -1315,7 +1315,7 @@ static struct samsung_pll_rate_table exynos4x12_apll_rates[] __initdata = { { /* sentinel */ } }; -static struct samsung_pll_rate_table exynos4x12_epll_rates[] __initdata = { +static const struct samsung_pll_rate_table exynos4x12_epll_rates[] __initconst = { PLL_36XX_RATE(192000000, 48, 3, 1, 0), PLL_36XX_RATE(180633605, 45, 3, 1, 10381), PLL_36XX_RATE(180000000, 45, 3, 1, 0), @@ -1326,7 +1326,7 @@ static struct samsung_pll_rate_table exynos4x12_epll_rates[] __initdata = { { /* sentinel */ } }; -static struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initdata = { +static const struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initconst = { PLL_36XX_RATE(533000000, 133, 3, 1, 16384), PLL_36XX_RATE(440000000, 110, 3, 1, 0), PLL_36XX_RATE(350000000, 175, 3, 2, 0), From ab7cc66dfa8e35e84a90ddfbb54f9bfadfbc2817 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 11 May 2016 14:02:02 +0200 Subject: [PATCH 14/41] clk: samsung: exynos4415: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos4415.c | 30 ++++++++++++++-------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4415.c b/drivers/clk/samsung/clk-exynos4415.c index 86ee06b226bd..1a9e9d039a3f 100644 --- a/drivers/clk/samsung/clk-exynos4415.c +++ b/drivers/clk/samsung/clk-exynos4415.c @@ -111,7 +111,7 @@ #define DIV_CPU0 0x14500 #define DIV_CPU1 0x14504 -static unsigned long exynos4415_cmu_clk_regs[] __initdata = { +static const unsigned long exynos4415_cmu_clk_regs[] __initconst = { SRC_LEFTBUS, DIV_LEFTBUS, GATE_IP_LEFTBUS, @@ -268,16 +268,16 @@ PNAME(group_aclk_isp0_300_user_p) = { "fin_pll", "mout_aclk_isp0_300" }; PNAME(group_aclk_isp1_300_user_p) = { "fin_pll", "mout_aclk_isp1_300" }; PNAME(group_mout_mpll_user_t_p) = { "mout_mpll_user_t" }; -static struct samsung_fixed_factor_clock exynos4415_fixed_factor_clks[] __initdata = { +static const struct samsung_fixed_factor_clock exynos4415_fixed_factor_clks[] __initconst = { /* HACK: fin_pll hardcoded to xusbxti until detection is implemented. */ FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0), }; -static struct samsung_fixed_rate_clock exynos4415_fixed_rate_clks[] __initdata = { +static const struct samsung_fixed_rate_clock exynos4415_fixed_rate_clks[] __initconst = { FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 27000000), }; -static struct samsung_mux_clock exynos4415_mux_clks[] __initdata = { +static const struct samsung_mux_clock exynos4415_mux_clks[] __initconst = { /* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done @@ -427,7 +427,7 @@ static struct samsung_mux_clock exynos4415_mux_clks[] __initdata = { group_aclk_isp1_300_user_p, SRC_TOP_ISP1, 0, 1), }; -static struct samsung_div_clock exynos4415_div_clks[] __initdata = { +static const struct samsung_div_clock exynos4415_div_clks[] __initconst = { /* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done @@ -566,7 +566,7 @@ static struct samsung_div_clock exynos4415_div_clks[] __initdata = { DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3), }; -static struct samsung_gate_clock exynos4415_gate_clks[] __initdata = { +static const struct samsung_gate_clock exynos4415_gate_clks[] __initconst = { /* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done @@ -859,7 +859,7 @@ static struct samsung_gate_clock exynos4415_gate_clks[] __initdata = { /* * APLL & MPLL & BPLL & ISP_PLL & DISP_PLL & G3D_PLL */ -static struct samsung_pll_rate_table exynos4415_pll_rates[] = { +static const struct samsung_pll_rate_table exynos4415_pll_rates[] = { PLL_35XX_RATE(1600000000, 400, 3, 1), PLL_35XX_RATE(1500000000, 250, 2, 1), PLL_35XX_RATE(1400000000, 175, 3, 0), @@ -891,7 +891,7 @@ static struct samsung_pll_rate_table exynos4415_pll_rates[] = { }; /* EPLL */ -static struct samsung_pll_rate_table exynos4415_epll_rates[] = { +static const struct samsung_pll_rate_table exynos4415_epll_rates[] = { PLL_36XX_RATE(800000000, 200, 3, 1, 0), PLL_36XX_RATE(288000000, 96, 2, 2, 0), PLL_36XX_RATE(192000000, 128, 2, 3, 0), @@ -909,7 +909,7 @@ static struct samsung_pll_rate_table exynos4415_epll_rates[] = { { /* sentinel */ } }; -static struct samsung_pll_clock exynos4415_plls[] __initdata = { +static const struct samsung_pll_clock exynos4415_plls[] __initconst = { PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, APLL_CON0, exynos4415_pll_rates), PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", @@ -922,7 +922,7 @@ static struct samsung_pll_clock exynos4415_plls[] __initdata = { "fin_pll", DISP_PLL_LOCK, DISP_PLL_CON0, exynos4415_pll_rates), }; -static struct samsung_cmu_info cmu_info __initdata = { +static const struct samsung_cmu_info cmu_info __initconst = { .pll_clks = exynos4415_plls, .nr_pll_clks = ARRAY_SIZE(exynos4415_plls), .mux_clks = exynos4415_mux_clks, @@ -961,7 +961,7 @@ CLK_OF_DECLARE(exynos4415_cmu, "samsung,exynos4415-cmu", exynos4415_cmu_init); #define SRC_DMC 0x300 #define DIV_DMC1 0x504 -static unsigned long exynos4415_cmu_dmc_clk_regs[] __initdata = { +static const unsigned long exynos4415_cmu_dmc_clk_regs[] __initconst = { MPLL_LOCK, MPLL_CON0, MPLL_CON1, @@ -978,14 +978,14 @@ PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", }; PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", }; PNAME(mbpll_p) = { "mout_mpll", "mout_bpll", }; -static struct samsung_mux_clock exynos4415_dmc_mux_clks[] __initdata = { +static const struct samsung_mux_clock exynos4415_dmc_mux_clks[] __initconst = { MUX(CLK_DMC_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_DMC, 12, 1), MUX(CLK_DMC_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_DMC, 10, 1), MUX(CLK_DMC_MOUT_DPHY, "mout_dphy", mbpll_p, SRC_DMC, 8, 1), MUX(CLK_DMC_MOUT_DMC_BUS, "mout_dmc_bus", mbpll_p, SRC_DMC, 4, 1), }; -static struct samsung_div_clock exynos4415_dmc_div_clks[] __initdata = { +static const struct samsung_div_clock exynos4415_dmc_div_clks[] __initconst = { DIV(CLK_DMC_DIV_DMC, "div_dmc", "div_dmc_pre", DIV_DMC1, 27, 3), DIV(CLK_DMC_DIV_DPHY, "div_dphy", "mout_dphy", DIV_DMC1, 23, 3), DIV(CLK_DMC_DIV_DMC_PRE, "div_dmc_pre", "mout_dmc_bus", @@ -995,14 +995,14 @@ static struct samsung_div_clock exynos4415_dmc_div_clks[] __initdata = { DIV(CLK_DMC_DIV_MPLL_PRE, "div_mpll_pre", "mout_mpll", DIV_DMC1, 8, 2), }; -static struct samsung_pll_clock exynos4415_dmc_plls[] __initdata = { +static const struct samsung_pll_clock exynos4415_dmc_plls[] __initconst = { PLL(pll_35xx, CLK_DMC_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK, MPLL_CON0, exynos4415_pll_rates), PLL(pll_35xx, CLK_DMC_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, BPLL_CON0, exynos4415_pll_rates), }; -static struct samsung_cmu_info cmu_dmc_info __initdata = { +static const struct samsung_cmu_info cmu_dmc_info __initconst = { .pll_clks = exynos4415_dmc_plls, .nr_pll_clks = ARRAY_SIZE(exynos4415_dmc_plls), .mux_clks = exynos4415_dmc_mux_clks, From ccd12b5cd69fbe33551922f03fe22e1053e5243c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 11 May 2016 14:02:03 +0200 Subject: [PATCH 15/41] clk: samsung: exynos4415: Move PLL rates data to init section The arrays with initialization data of PLLs can be moved to initconst section because they are referenced only from other initconst-level symbols. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos4415.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4415.c b/drivers/clk/samsung/clk-exynos4415.c index 1a9e9d039a3f..6c9063159717 100644 --- a/drivers/clk/samsung/clk-exynos4415.c +++ b/drivers/clk/samsung/clk-exynos4415.c @@ -859,7 +859,7 @@ static const struct samsung_gate_clock exynos4415_gate_clks[] __initconst = { /* * APLL & MPLL & BPLL & ISP_PLL & DISP_PLL & G3D_PLL */ -static const struct samsung_pll_rate_table exynos4415_pll_rates[] = { +static const struct samsung_pll_rate_table exynos4415_pll_rates[] __initconst = { PLL_35XX_RATE(1600000000, 400, 3, 1), PLL_35XX_RATE(1500000000, 250, 2, 1), PLL_35XX_RATE(1400000000, 175, 3, 0), @@ -891,7 +891,7 @@ static const struct samsung_pll_rate_table exynos4415_pll_rates[] = { }; /* EPLL */ -static const struct samsung_pll_rate_table exynos4415_epll_rates[] = { +static const struct samsung_pll_rate_table exynos4415_epll_rates[] __initconst = { PLL_36XX_RATE(800000000, 200, 3, 1, 0), PLL_36XX_RATE(288000000, 96, 2, 2, 0), PLL_36XX_RATE(192000000, 128, 2, 3, 0), From 5b37e8494d5ce1f4a8a07fb5288c3b63a533cd3c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 11 May 2016 14:02:04 +0200 Subject: [PATCH 16/41] clk: samsung: exynos5250: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos5250.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index d8621cf31786..a6ebc068689f 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -117,7 +117,7 @@ static struct samsung_clk_reg_dump *exynos5250_save; * list of controller registers to be saved and restored during a * suspend/resume cycle. */ -static unsigned long exynos5250_clk_regs[] __initdata = { +static const unsigned long exynos5250_clk_regs[] __initconst = { SRC_CPU, DIV_CPU0, PWR_CTRL1, @@ -266,23 +266,23 @@ static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initda }; /* fixed rate clocks generated inside the soc */ -static struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = { +static const struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initconst = { FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000), FRATE(0, "sclk_hdmi27m", NULL, 0, 27000000), FRATE(0, "sclk_dptxphy", NULL, 0, 24000000), FRATE(0, "sclk_uhostphy", NULL, 0, 48000000), }; -static struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = { +static const struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initconst = { FFACTOR(0, "fout_mplldiv2", "fout_mpll", 1, 2, 0), FFACTOR(0, "fout_bplldiv2", "fout_bpll", 1, 2, 0), }; -static struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initdata = { +static const struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initconst = { MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1), }; -static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { +static const struct samsung_mux_clock exynos5250_mux_clks[] __initconst = { /* * NOTE: Following table is sorted by (clock domain, register address, * bitfield shift) triplet in ascending order. When adding new entries, @@ -378,7 +378,7 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { MUX(0, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1), }; -static struct samsung_div_clock exynos5250_div_clks[] __initdata = { +static const struct samsung_div_clock exynos5250_div_clks[] __initconst = { /* * NOTE: Following table is sorted by (clock domain, register address, * bitfield shift) triplet in ascending order. When adding new entries, @@ -470,7 +470,7 @@ static struct samsung_div_clock exynos5250_div_clks[] __initdata = { DIV(CLK_DIV_I2S2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6), }; -static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { +static const struct samsung_gate_clock exynos5250_gate_clks[] __initconst = { /* * NOTE: Following table is sorted by (clock domain, register address, * bitfield shift) triplet in ascending order. When adding new entries, @@ -698,7 +698,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { GATE_IP_ISP1, 7, 0, 0), }; -static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = { +static const struct samsung_pll_rate_table vpll_24mhz_tbl[] __initconst = { /* sorted in descending order */ /* PLL_36XX_RATE(rate, m, p, s, k) */ PLL_36XX_RATE(266000000, 266, 3, 3, 0), @@ -707,7 +707,7 @@ static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = { { }, }; -static struct samsung_pll_rate_table epll_24mhz_tbl[] __initdata = { +static const struct samsung_pll_rate_table epll_24mhz_tbl[] __initconst = { /* sorted in descending order */ /* PLL_36XX_RATE(rate, m, p, s, k) */ PLL_36XX_RATE(192000000, 64, 2, 2, 0), @@ -721,7 +721,7 @@ static struct samsung_pll_rate_table epll_24mhz_tbl[] __initdata = { { }, }; -static struct samsung_pll_rate_table apll_24mhz_tbl[] __initdata = { +static const struct samsung_pll_rate_table apll_24mhz_tbl[] __initconst = { /* sorted in descending order */ /* PLL_35XX_RATE(rate, m, p, s) */ PLL_35XX_RATE(1700000000, 425, 6, 0), From c10d80f8e1c4eed487d845f3efd52078fdc764eb Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 11 May 2016 14:02:05 +0200 Subject: [PATCH 17/41] clk: samsung: exynos5260: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos5260.c | 114 +++++++++++++-------------- 1 file changed, 57 insertions(+), 57 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5260.c b/drivers/clk/samsung/clk-exynos5260.c index 7a7ed075a573..a43642c36039 100644 --- a/drivers/clk/samsung/clk-exynos5260.c +++ b/drivers/clk/samsung/clk-exynos5260.c @@ -22,7 +22,7 @@ * Applicable for all 2550 Type PLLS for Exynos5260, listed below * DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL. */ -static struct samsung_pll_rate_table pll2550_24mhz_tbl[] __initdata = { +static const struct samsung_pll_rate_table pll2550_24mhz_tbl[] __initconst = { PLL_35XX_RATE(1700000000, 425, 6, 0), PLL_35XX_RATE(1600000000, 200, 3, 0), PLL_35XX_RATE(1500000000, 250, 4, 0), @@ -55,7 +55,7 @@ static struct samsung_pll_rate_table pll2550_24mhz_tbl[] __initdata = { /* * Applicable for 2650 Type PLL for AUD_PLL. */ -static struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initdata = { +static const struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initconst = { PLL_36XX_RATE(1600000000, 200, 3, 0, 0), PLL_36XX_RATE(1200000000, 100, 2, 0, 0), PLL_36XX_RATE(1000000000, 250, 3, 1, 0), @@ -78,7 +78,7 @@ static struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initdata = { /* CMU_AUD */ -static unsigned long aud_clk_regs[] __initdata = { +static const unsigned long aud_clk_regs[] __initconst = { MUX_SEL_AUD, DIV_AUD0, DIV_AUD1, @@ -92,7 +92,7 @@ PNAME(mout_aud_pll_user_p) = {"fin_pll", "fout_aud_pll"}; PNAME(mout_sclk_aud_i2s_p) = {"mout_aud_pll_user", "ioclk_i2s_cdclk"}; PNAME(mout_sclk_aud_pcm_p) = {"mout_aud_pll_user", "ioclk_pcm_extclk"}; -static struct samsung_mux_clock aud_mux_clks[] __initdata = { +static const struct samsung_mux_clock aud_mux_clks[] __initconst = { MUX(AUD_MOUT_AUD_PLL_USER, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 0, 1), MUX(AUD_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_i2s_p, @@ -101,7 +101,7 @@ static struct samsung_mux_clock aud_mux_clks[] __initdata = { MUX_SEL_AUD, 8, 1), }; -static struct samsung_div_clock aud_div_clks[] __initdata = { +static const struct samsung_div_clock aud_div_clks[] __initconst = { DIV(AUD_DOUT_ACLK_AUD_131, "dout_aclk_aud_131", "mout_aud_pll_user", DIV_AUD0, 0, 4), @@ -113,7 +113,7 @@ static struct samsung_div_clock aud_div_clks[] __initdata = { DIV_AUD1, 12, 4), }; -static struct samsung_gate_clock aud_gate_clks[] __initdata = { +static const struct samsung_gate_clock aud_gate_clks[] __initconst = { GATE(AUD_SCLK_I2S, "sclk_aud_i2s", "dout_sclk_aud_i2s", EN_SCLK_AUD, 0, CLK_SET_RATE_PARENT, 0), GATE(AUD_SCLK_PCM, "sclk_aud_pcm", "dout_sclk_aud_pcm", @@ -154,7 +154,7 @@ CLK_OF_DECLARE(exynos5260_clk_aud, "samsung,exynos5260-clock-aud", /* CMU_DISP */ -static unsigned long disp_clk_regs[] __initdata = { +static const unsigned long disp_clk_regs[] __initconst = { MUX_SEL_DISP0, MUX_SEL_DISP1, MUX_SEL_DISP2, @@ -201,7 +201,7 @@ PNAME(mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p) = {"fin_pll", PNAME(mout_sclk_hdmi_spdif_p) = {"fin_pll", "ioclk_spdif_extclk", "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"}; -static struct samsung_mux_clock disp_mux_clks[] __initdata = { +static const struct samsung_mux_clock disp_mux_clks[] __initconst = { MUX(DISP_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user", mout_aclk_disp_333_user_p, MUX_SEL_DISP0, 0, 1), @@ -270,7 +270,7 @@ static struct samsung_mux_clock disp_mux_clks[] __initdata = { MUX_SEL_DISP4, 4, 2), }; -static struct samsung_div_clock disp_div_clks[] __initdata = { +static const struct samsung_div_clock disp_div_clks[] __initconst = { DIV(DISP_DOUT_PCLK_DISP_111, "dout_pclk_disp_111", "mout_aclk_disp_222_user", DIV_DISP, 8, 4), @@ -283,7 +283,7 @@ static struct samsung_div_clock disp_div_clks[] __initdata = { DIV_DISP, 16, 4), }; -static struct samsung_gate_clock disp_gate_clks[] __initdata = { +static const struct samsung_gate_clock disp_gate_clks[] __initconst = { GATE(DISP_MOUT_HDMI_PHY_PIXEL_USER, "sclk_hdmi_link_i_pixel", "mout_phyclk_hdmi_phy_pixel_clko_user", EN_SCLK_DISP0, 26, CLK_SET_RATE_PARENT, 0), @@ -344,7 +344,7 @@ CLK_OF_DECLARE(exynos5260_clk_disp, "samsung,exynos5260-clock-disp", /* CMU_EGL */ -static unsigned long egl_clk_regs[] __initdata = { +static const unsigned long egl_clk_regs[] __initconst = { EGL_PLL_LOCK, EGL_PLL_CON0, EGL_PLL_CON1, @@ -361,13 +361,13 @@ static unsigned long egl_clk_regs[] __initdata = { PNAME(mout_egl_b_p) = {"mout_egl_pll", "dout_bus_pll"}; PNAME(mout_egl_pll_p) = {"fin_pll", "fout_egl_pll"}; -static struct samsung_mux_clock egl_mux_clks[] __initdata = { +static const struct samsung_mux_clock egl_mux_clks[] __initconst = { MUX(EGL_MOUT_EGL_PLL, "mout_egl_pll", mout_egl_pll_p, MUX_SEL_EGL, 4, 1), MUX(EGL_MOUT_EGL_B, "mout_egl_b", mout_egl_b_p, MUX_SEL_EGL, 16, 1), }; -static struct samsung_div_clock egl_div_clks[] __initdata = { +static const struct samsung_div_clock egl_div_clks[] __initconst = { DIV(EGL_DOUT_EGL1, "dout_egl1", "mout_egl_b", DIV_EGL, 0, 3), DIV(EGL_DOUT_EGL2, "dout_egl2", "dout_egl1", DIV_EGL, 4, 3), DIV(EGL_DOUT_ACLK_EGL, "dout_aclk_egl", "dout_egl2", DIV_EGL, 8, 3), @@ -379,7 +379,7 @@ static struct samsung_div_clock egl_div_clks[] __initdata = { DIV(EGL_DOUT_EGL_PLL, "dout_egl_pll", "mout_egl_b", DIV_EGL, 24, 3), }; -static struct samsung_pll_clock egl_pll_clks[] __initdata = { +static const struct samsung_pll_clock egl_pll_clks[] __initconst = { PLL(pll_2550xx, EGL_FOUT_EGL_PLL, "fout_egl_pll", "fin_pll", EGL_PLL_LOCK, EGL_PLL_CON0, pll2550_24mhz_tbl), @@ -408,7 +408,7 @@ CLK_OF_DECLARE(exynos5260_clk_egl, "samsung,exynos5260-clock-egl", /* CMU_FSYS */ -static unsigned long fsys_clk_regs[] __initdata = { +static const unsigned long fsys_clk_regs[] __initconst = { MUX_SEL_FSYS0, MUX_SEL_FSYS1, EN_ACLK_FSYS, @@ -431,7 +431,7 @@ PNAME(mout_phyclk_usbdrd30_pipe_pclk_user_p) = {"fin_pll", PNAME(mout_phyclk_usbdrd30_phyclock_user_p) = {"fin_pll", "phyclk_usbdrd30_udrd30_phyclock"}; -static struct samsung_mux_clock fsys_mux_clks[] __initdata = { +static const struct samsung_mux_clock fsys_mux_clks[] __initconst = { MUX(FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER, "mout_phyclk_usbdrd30_phyclock_user", mout_phyclk_usbdrd30_phyclock_user_p, @@ -454,7 +454,7 @@ static struct samsung_mux_clock fsys_mux_clks[] __initdata = { MUX_SEL_FSYS1, 16, 1), }; -static struct samsung_gate_clock fsys_gate_clks[] __initdata = { +static const struct samsung_gate_clock fsys_gate_clks[] __initconst = { GATE(FSYS_PHYCLK_USBHOST20, "phyclk_usbhost20_phyclock", "mout_phyclk_usbdrd30_phyclock_user", EN_SCLK_FSYS, 1, 0, 0), @@ -508,7 +508,7 @@ CLK_OF_DECLARE(exynos5260_clk_fsys, "samsung,exynos5260-clock-fsys", /* CMU_G2D */ -static unsigned long g2d_clk_regs[] __initdata = { +static const unsigned long g2d_clk_regs[] __initconst = { MUX_SEL_G2D, MUX_STAT_G2D, DIV_G2D, @@ -535,18 +535,18 @@ static unsigned long g2d_clk_regs[] __initdata = { PNAME(mout_aclk_g2d_333_user_p) = {"fin_pll", "dout_aclk_g2d_333"}; -static struct samsung_mux_clock g2d_mux_clks[] __initdata = { +static const struct samsung_mux_clock g2d_mux_clks[] __initconst = { MUX(G2D_MOUT_ACLK_G2D_333_USER, "mout_aclk_g2d_333_user", mout_aclk_g2d_333_user_p, MUX_SEL_G2D, 0, 1), }; -static struct samsung_div_clock g2d_div_clks[] __initdata = { +static const struct samsung_div_clock g2d_div_clks[] __initconst = { DIV(G2D_DOUT_PCLK_G2D_83, "dout_pclk_g2d_83", "mout_aclk_g2d_333_user", DIV_G2D, 0, 3), }; -static struct samsung_gate_clock g2d_gate_clks[] __initdata = { +static const struct samsung_gate_clock g2d_gate_clks[] __initconst = { GATE(G2D_CLK_G2D, "clk_g2d", "mout_aclk_g2d_333_user", EN_IP_G2D, 4, 0, 0), GATE(G2D_CLK_JPEG, "clk_jpeg", "mout_aclk_g2d_333_user", @@ -599,7 +599,7 @@ CLK_OF_DECLARE(exynos5260_clk_g2d, "samsung,exynos5260-clock-g2d", /* CMU_G3D */ -static unsigned long g3d_clk_regs[] __initdata = { +static const unsigned long g3d_clk_regs[] __initconst = { G3D_PLL_LOCK, G3D_PLL_CON0, G3D_PLL_CON1, @@ -615,23 +615,23 @@ static unsigned long g3d_clk_regs[] __initdata = { PNAME(mout_g3d_pll_p) = {"fin_pll", "fout_g3d_pll"}; -static struct samsung_mux_clock g3d_mux_clks[] __initdata = { +static const struct samsung_mux_clock g3d_mux_clks[] __initconst = { MUX(G3D_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p, MUX_SEL_G3D, 0, 1), }; -static struct samsung_div_clock g3d_div_clks[] __initdata = { +static const struct samsung_div_clock g3d_div_clks[] __initconst = { DIV(G3D_DOUT_PCLK_G3D, "dout_pclk_g3d", "dout_aclk_g3d", DIV_G3D, 0, 3), DIV(G3D_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_g3d_pll", DIV_G3D, 4, 3), }; -static struct samsung_gate_clock g3d_gate_clks[] __initdata = { +static const struct samsung_gate_clock g3d_gate_clks[] __initconst = { GATE(G3D_CLK_G3D, "clk_g3d", "dout_aclk_g3d", EN_IP_G3D, 2, 0, 0), GATE(G3D_CLK_G3D_HPM, "clk_g3d_hpm", "dout_aclk_g3d", EN_IP_G3D, 3, 0, 0), }; -static struct samsung_pll_clock g3d_pll_clks[] __initdata = { +static const struct samsung_pll_clock g3d_pll_clks[] __initconst = { PLL(pll_2550, G3D_FOUT_G3D_PLL, "fout_g3d_pll", "fin_pll", G3D_PLL_LOCK, G3D_PLL_CON0, pll2550_24mhz_tbl), @@ -662,7 +662,7 @@ CLK_OF_DECLARE(exynos5260_clk_g3d, "samsung,exynos5260-clock-g3d", /* CMU_GSCL */ -static unsigned long gscl_clk_regs[] __initdata = { +static const unsigned long gscl_clk_regs[] __initconst = { MUX_SEL_GSCL, DIV_GSCL, EN_ACLK_GSCL, @@ -692,7 +692,7 @@ PNAME(mout_aclk_m2m_400_user_p) = {"fin_pll", "dout_aclk_gscl_400"}; PNAME(mout_aclk_gscl_fimc_user_p) = {"fin_pll", "dout_aclk_gscl_400"}; PNAME(mout_aclk_csis_p) = {"dout_aclk_csis_200", "mout_aclk_gscl_fimc_user"}; -static struct samsung_mux_clock gscl_mux_clks[] __initdata = { +static const struct samsung_mux_clock gscl_mux_clks[] __initconst = { MUX(GSCL_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user", mout_aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1), @@ -706,7 +706,7 @@ static struct samsung_mux_clock gscl_mux_clks[] __initdata = { MUX_SEL_GSCL, 24, 1), }; -static struct samsung_div_clock gscl_div_clks[] __initdata = { +static const struct samsung_div_clock gscl_div_clks[] __initconst = { DIV(GSCL_DOUT_PCLK_M2M_100, "dout_pclk_m2m_100", "mout_aclk_m2m_400_user", DIV_GSCL, 0, 3), @@ -715,7 +715,7 @@ static struct samsung_div_clock gscl_div_clks[] __initdata = { DIV_GSCL, 4, 3), }; -static struct samsung_gate_clock gscl_gate_clks[] __initdata = { +static const struct samsung_gate_clock gscl_gate_clks[] __initconst = { GATE(GSCL_SCLK_CSIS0_WRAP, "sclk_csis0_wrap", "dout_aclk_csis_200", EN_SCLK_GSCL_FIMC, 0, CLK_SET_RATE_PARENT, 0), GATE(GSCL_SCLK_CSIS1_WRAP, "sclk_csis1_wrap", "dout_aclk_csis_200", @@ -795,7 +795,7 @@ CLK_OF_DECLARE(exynos5260_clk_gscl, "samsung,exynos5260-clock-gscl", /* CMU_ISP */ -static unsigned long isp_clk_regs[] __initdata = { +static const unsigned long isp_clk_regs[] __initconst = { MUX_SEL_ISP0, MUX_SEL_ISP1, DIV_ISP, @@ -811,14 +811,14 @@ static unsigned long isp_clk_regs[] __initdata = { PNAME(mout_isp_400_user_p) = {"fin_pll", "dout_aclk_isp1_400"}; PNAME(mout_isp_266_user_p) = {"fin_pll", "dout_aclk_isp1_266"}; -static struct samsung_mux_clock isp_mux_clks[] __initdata = { +static const struct samsung_mux_clock isp_mux_clks[] __initconst = { MUX(ISP_MOUT_ISP_266_USER, "mout_isp_266_user", mout_isp_266_user_p, MUX_SEL_ISP0, 0, 1), MUX(ISP_MOUT_ISP_400_USER, "mout_isp_400_user", mout_isp_400_user_p, MUX_SEL_ISP0, 4, 1), }; -static struct samsung_div_clock isp_div_clks[] __initdata = { +static const struct samsung_div_clock isp_div_clks[] __initconst = { DIV(ISP_DOUT_PCLK_ISP_66, "dout_pclk_isp_66", "mout_kfc", DIV_ISP, 0, 3), DIV(ISP_DOUT_PCLK_ISP_133, "dout_pclk_isp_133", "mout_kfc", @@ -830,7 +830,7 @@ static struct samsung_div_clock isp_div_clks[] __initdata = { DIV(ISP_DOUT_SCLK_MPWM, "dout_sclk_mpwm", "mout_kfc", DIV_ISP, 20, 2), }; -static struct samsung_gate_clock isp_gate_clks[] __initdata = { +static const struct samsung_gate_clock isp_gate_clks[] __initconst = { GATE(ISP_CLK_GIC, "clk_isp_gic", "mout_aclk_isp1_266", EN_IP_ISP0, 15, 0, 0), @@ -914,7 +914,7 @@ CLK_OF_DECLARE(exynos5260_clk_isp, "samsung,exynos5260-clock-isp", /* CMU_KFC */ -static unsigned long kfc_clk_regs[] __initdata = { +static const unsigned long kfc_clk_regs[] __initconst = { KFC_PLL_LOCK, KFC_PLL_CON0, KFC_PLL_CON1, @@ -932,13 +932,13 @@ static unsigned long kfc_clk_regs[] __initdata = { PNAME(mout_kfc_pll_p) = {"fin_pll", "fout_kfc_pll"}; PNAME(mout_kfc_p) = {"mout_kfc_pll", "dout_media_pll"}; -static struct samsung_mux_clock kfc_mux_clks[] __initdata = { +static const struct samsung_mux_clock kfc_mux_clks[] __initconst = { MUX(KFC_MOUT_KFC_PLL, "mout_kfc_pll", mout_kfc_pll_p, MUX_SEL_KFC0, 0, 1), MUX(KFC_MOUT_KFC, "mout_kfc", mout_kfc_p, MUX_SEL_KFC2, 0, 1), }; -static struct samsung_div_clock kfc_div_clks[] __initdata = { +static const struct samsung_div_clock kfc_div_clks[] __initconst = { DIV(KFC_DOUT_KFC1, "dout_kfc1", "mout_kfc", DIV_KFC, 0, 3), DIV(KFC_DOUT_KFC2, "dout_kfc2", "dout_kfc1", DIV_KFC, 4, 3), DIV(KFC_DOUT_KFC_ATCLK, "dout_kfc_atclk", "dout_kfc2", DIV_KFC, 8, 3), @@ -949,7 +949,7 @@ static struct samsung_div_clock kfc_div_clks[] __initdata = { DIV(KFC_DOUT_KFC_PLL, "dout_kfc_pll", "mout_kfc", DIV_KFC, 24, 3), }; -static struct samsung_pll_clock kfc_pll_clks[] __initdata = { +static const struct samsung_pll_clock kfc_pll_clks[] __initconst = { PLL(pll_2550xx, KFC_FOUT_KFC_PLL, "fout_kfc_pll", "fin_pll", KFC_PLL_LOCK, KFC_PLL_CON0, pll2550_24mhz_tbl), @@ -978,7 +978,7 @@ CLK_OF_DECLARE(exynos5260_clk_kfc, "samsung,exynos5260-clock-kfc", /* CMU_MFC */ -static unsigned long mfc_clk_regs[] __initdata = { +static const unsigned long mfc_clk_regs[] __initconst = { MUX_SEL_MFC, DIV_MFC, EN_ACLK_MFC, @@ -991,18 +991,18 @@ static unsigned long mfc_clk_regs[] __initdata = { PNAME(mout_aclk_mfc_333_user_p) = {"fin_pll", "dout_aclk_mfc_333"}; -static struct samsung_mux_clock mfc_mux_clks[] __initdata = { +static const struct samsung_mux_clock mfc_mux_clks[] __initconst = { MUX(MFC_MOUT_ACLK_MFC_333_USER, "mout_aclk_mfc_333_user", mout_aclk_mfc_333_user_p, MUX_SEL_MFC, 0, 1), }; -static struct samsung_div_clock mfc_div_clks[] __initdata = { +static const struct samsung_div_clock mfc_div_clks[] __initconst = { DIV(MFC_DOUT_PCLK_MFC_83, "dout_pclk_mfc_83", "mout_aclk_mfc_333_user", DIV_MFC, 0, 3), }; -static struct samsung_gate_clock mfc_gate_clks[] __initdata = { +static const struct samsung_gate_clock mfc_gate_clks[] __initconst = { GATE(MFC_CLK_MFC, "clk_mfc", "mout_aclk_mfc_333_user", EN_IP_MFC, 1, 0, 0), GATE(MFC_CLK_SMMU2_MFCM0, "clk_smmu2_mfcm0", "mout_aclk_mfc_333_user", @@ -1034,7 +1034,7 @@ CLK_OF_DECLARE(exynos5260_clk_mfc, "samsung,exynos5260-clock-mfc", /* CMU_MIF */ -static unsigned long mif_clk_regs[] __initdata = { +static const unsigned long mif_clk_regs[] __initconst = { MEM_PLL_LOCK, BUS_PLL_LOCK, MEDIA_PLL_LOCK, @@ -1076,7 +1076,7 @@ PNAME(mout_mif_drex2x_p) = {"dout_mem_pll", "dout_bus_pll"}; PNAME(mout_clkm_phy_p) = {"mout_mif_drex", "dout_media_pll"}; PNAME(mout_clk2x_phy_p) = {"mout_mif_drex2x", "dout_media_pll"}; -static struct samsung_mux_clock mif_mux_clks[] __initdata = { +static const struct samsung_mux_clock mif_mux_clks[] __initconst = { MUX(MIF_MOUT_MEM_PLL, "mout_mem_pll", mout_mem_pll_p, MUX_SEL_MIF, 0, 1), MUX(MIF_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, @@ -1093,7 +1093,7 @@ static struct samsung_mux_clock mif_mux_clks[] __initdata = { MUX_SEL_MIF, 24, 1), }; -static struct samsung_div_clock mif_div_clks[] __initdata = { +static const struct samsung_div_clock mif_div_clks[] __initconst = { DIV(MIF_DOUT_MEDIA_PLL, "dout_media_pll", "mout_media_pll", DIV_MIF, 0, 3), DIV(MIF_DOUT_MEM_PLL, "dout_mem_pll", "mout_mem_pll", @@ -1112,7 +1112,7 @@ static struct samsung_div_clock mif_div_clks[] __initdata = { DIV_MIF, 28, 4), }; -static struct samsung_gate_clock mif_gate_clks[] __initdata = { +static const struct samsung_gate_clock mif_gate_clks[] __initconst = { GATE(MIF_CLK_LPDDR3PHY_WRAP0, "clk_lpddr3phy_wrap0", "dout_clk2x_phy", EN_IP_MIF, 12, CLK_IGNORE_UNUSED, 0), GATE(MIF_CLK_LPDDR3PHY_WRAP1, "clk_lpddr3phy_wrap1", "dout_clk2x_phy", @@ -1146,7 +1146,7 @@ static struct samsung_gate_clock mif_gate_clks[] __initdata = { CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), }; -static struct samsung_pll_clock mif_pll_clks[] __initdata = { +static const struct samsung_pll_clock mif_pll_clks[] __initconst = { PLL(pll_2550xx, MIF_FOUT_MEM_PLL, "fout_mem_pll", "fin_pll", MEM_PLL_LOCK, MEM_PLL_CON0, pll2550_24mhz_tbl), @@ -1183,7 +1183,7 @@ CLK_OF_DECLARE(exynos5260_clk_mif, "samsung,exynos5260-clock-mif", /* CMU_PERI */ -static unsigned long peri_clk_regs[] __initdata = { +static const unsigned long peri_clk_regs[] __initconst = { MUX_SEL_PERI, MUX_SEL_PERI1, DIV_PERI, @@ -1219,7 +1219,7 @@ PNAME(mout_sclk_i2scod_p) = {"ioclk_i2s_cdclk", "fin_pll", "dout_aclk_peri_aud", PNAME(mout_sclk_spdif_p) = {"ioclk_spdif_extclk", "fin_pll", "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"}; -static struct samsung_mux_clock peri_mux_clks[] __initdata = { +static const struct samsung_mux_clock peri_mux_clks[] __initconst = { MUX(PERI_MOUT_SCLK_PCM, "mout_sclk_pcm", mout_sclk_pcm_p, MUX_SEL_PERI1, 4, 2), MUX(PERI_MOUT_SCLK_I2SCOD, "mout_sclk_i2scod", mout_sclk_i2scod_p, @@ -1228,12 +1228,12 @@ static struct samsung_mux_clock peri_mux_clks[] __initdata = { MUX_SEL_PERI1, 20, 2), }; -static struct samsung_div_clock peri_div_clks[] __initdata = { +static const struct samsung_div_clock peri_div_clks[] __initconst = { DIV(PERI_DOUT_PCM, "dout_pcm", "mout_sclk_pcm", DIV_PERI, 0, 8), DIV(PERI_DOUT_I2S, "dout_i2s", "mout_sclk_i2scod", DIV_PERI, 8, 6), }; -static struct samsung_gate_clock peri_gate_clks[] __initdata = { +static const struct samsung_gate_clock peri_gate_clks[] __initconst = { GATE(PERI_SCLK_PCM1, "sclk_pcm1", "dout_pcm", EN_SCLK_PERI, 0, CLK_SET_RATE_PARENT, 0), GATE(PERI_SCLK_I2S, "sclk_i2s", "dout_i2s", EN_SCLK_PERI, 1, @@ -1389,7 +1389,7 @@ CLK_OF_DECLARE(exynos5260_clk_peri, "samsung,exynos5260-clock-peri", /* CMU_TOP */ -static unsigned long top_clk_regs[] __initdata = { +static const unsigned long top_clk_regs[] __initconst = { DISP_PLL_LOCK, AUD_PLL_LOCK, DISP_PLL_CON0, @@ -1430,7 +1430,7 @@ static unsigned long top_clk_regs[] __initdata = { }; /* fixed rate clocks generated inside the soc */ -static struct samsung_fixed_rate_clock fixed_rate_clks[] __initdata = { +static const struct samsung_fixed_rate_clock fixed_rate_clks[] __initconst = { FRATE(PHYCLK_DPTX_PHY_CH3_TXD_CLK, "phyclk_dptx_phy_ch3_txd_clk", NULL, 0, 270000000), FRATE(PHYCLK_DPTX_PHY_CH2_TXD_CLK, "phyclk_dptx_phy_ch2_txd_clk", NULL, @@ -1513,7 +1513,7 @@ PNAME(mout_sclk_fsys_mmc1_sdclkin_b_p) = {"mout_sclk_fsys_mmc1_sdclkin_a", PNAME(mout_sclk_fsys_mmc2_sdclkin_b_p) = {"mout_sclk_fsys_mmc2_sdclkin_a", "mout_mediatop_pll_user"}; -static struct samsung_mux_clock top_mux_clks[] __initdata = { +static const struct samsung_mux_clock top_mux_clks[] __initconst = { MUX(TOP_MOUT_MEDIATOP_PLL_USER, "mout_mediatop_pll_user", mout_mediatop_pll_user_p, MUX_SEL_TOP_PLL0, 0, 1), @@ -1673,7 +1673,7 @@ static struct samsung_mux_clock top_mux_clks[] __initdata = { MUX_SEL_TOP_GSCL, 20, 1), }; -static struct samsung_div_clock top_div_clks[] __initdata = { +static const struct samsung_div_clock top_div_clks[] __initconst = { DIV(TOP_DOUT_ACLK_G2D_333, "dout_aclk_g2d_333", "mout_aclk_g2d_333", DIV_TOP_G2D_MFC, 0, 3), DIV(TOP_DOUT_ACLK_MFC_333, "dout_aclk_mfc_333", "mout_aclk_mfc_333", @@ -1794,7 +1794,7 @@ static struct samsung_div_clock top_div_clks[] __initdata = { }; -static struct samsung_gate_clock top_gate_clks[] __initdata = { +static const struct samsung_gate_clock top_gate_clks[] __initconst = { GATE(TOP_SCLK_MMC0, "sclk_fsys_mmc0_sdclkin", "dout_sclk_fsys_mmc0_sdclkin_b", EN_SCLK_TOP, 7, CLK_SET_RATE_PARENT, 0), @@ -1809,7 +1809,7 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = { CLK_SET_RATE_PARENT, 0), }; -static struct samsung_pll_clock top_pll_clks[] __initdata = { +static const struct samsung_pll_clock top_pll_clks[] __initconst = { PLL(pll_2550xx, TOP_FOUT_DISP_PLL, "fout_disp_pll", "fin_pll", DISP_PLL_LOCK, DISP_PLL_CON0, pll2550_24mhz_tbl), From 408860ba5329c547002c087cfc296851c59f6b57 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 11 May 2016 14:02:06 +0200 Subject: [PATCH 18/41] clk: samsung: exynos5410: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos5410.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c index d5d5dcabc4a9..8e8c7cca8c62 100644 --- a/drivers/clk/samsung/clk-exynos5410.c +++ b/drivers/clk/samsung/clk-exynos5410.c @@ -76,7 +76,7 @@ PNAME(group2_p) = { "fin_pll", "fin_pll", "none", "none", "none", "none", "sclk_mpll_bpll", "none", "none", "sclk_cpll" }; -static struct samsung_mux_clock exynos5410_mux_clks[] __initdata = { +static const struct samsung_mux_clock exynos5410_mux_clks[] __initconst = { MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1), MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), @@ -105,7 +105,7 @@ static struct samsung_mux_clock exynos5410_mux_clks[] __initdata = { MUX(0, "mout_aclk400", mpll_bpll_p, SRC_TOP0, 20, 1), }; -static struct samsung_div_clock exynos5410_div_clks[] __initdata = { +static const struct samsung_div_clock exynos5410_div_clks[] __initconst = { DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3), @@ -141,7 +141,7 @@ static struct samsung_div_clock exynos5410_div_clks[] __initdata = { DIV(0, "aclk400", "mout_aclk400", DIV_TOP0, 24, 3), }; -static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = { +static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = { GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0), GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", @@ -167,7 +167,7 @@ static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = { SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0), }; -static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = { +static const struct samsung_pll_clock exynos5410_plls[nr_plls] __initconst = { [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, APLL_CON0, NULL), [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, From ad98c64fbb792d7089118b6568ce7bc35fce1875 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 11 May 2016 14:02:07 +0200 Subject: [PATCH 19/41] clk: samsung: exynos5420: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos5420.c | 30 ++++++++++++++-------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 770c0f007c6b..427725c8262c 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -160,7 +160,7 @@ static struct samsung_clk_reg_dump *exynos5800_save; * list of controller registers to be saved and restored during a * suspend/resume cycle. */ -static unsigned long exynos5x_clk_regs[] __initdata = { +static const unsigned long exynos5x_clk_regs[] __initconst = { SRC_CPU, DIV_CPU0, DIV_CPU1, @@ -248,7 +248,7 @@ static unsigned long exynos5x_clk_regs[] __initdata = { DIV_KFC0, }; -static unsigned long exynos5800_clk_regs[] __initdata = { +static const unsigned long exynos5800_clk_regs[] __initconst = { SRC_TOP8, SRC_TOP9, SRC_CAM, @@ -484,7 +484,7 @@ static struct samsung_fixed_rate_clock }; /* fixed rate clocks generated inside the soc */ -static struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initdata = { +static const struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initconst = { FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000), FRATE(0, "sclk_pwi", NULL, 0, 24000000), FRATE(0, "sclk_usbh20", NULL, 0, 48000000), @@ -492,19 +492,19 @@ static struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initdata = { FRATE(0, "sclk_usbh20_scan_clk", NULL, 0, 480000000), }; -static struct samsung_fixed_factor_clock - exynos5x_fixed_factor_clks[] __initdata = { +static const struct samsung_fixed_factor_clock + exynos5x_fixed_factor_clks[] __initconst = { FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0), FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0), }; -static struct samsung_fixed_factor_clock - exynos5800_fixed_factor_clks[] __initdata = { +static const struct samsung_fixed_factor_clock + exynos5800_fixed_factor_clks[] __initconst = { FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0), FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0), }; -static struct samsung_mux_clock exynos5800_mux_clks[] __initdata = { +static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = { MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3), MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3), MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3), @@ -553,7 +553,7 @@ static struct samsung_mux_clock exynos5800_mux_clks[] __initdata = { MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3), }; -static struct samsung_div_clock exynos5800_div_clks[] __initdata = { +static const struct samsung_div_clock exynos5800_div_clks[] __initconst = { DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", "mout_aclk400_wcore", DIV_TOP0, 16, 3), DIV(0, "dout_aclk550_cam", "mout_aclk550_cam", @@ -569,14 +569,14 @@ static struct samsung_div_clock exynos5800_div_clks[] __initdata = { DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6), }; -static struct samsung_gate_clock exynos5800_gate_clks[] __initdata = { +static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = { GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam", GATE_BUS_TOP, 24, 0, 0), GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler", GATE_BUS_TOP, 27, 0, 0), }; -static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { +static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = { MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1), MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p, TOP_SPARE2, 4, 1), @@ -606,12 +606,12 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1), }; -static struct samsung_div_clock exynos5420_div_clks[] __initdata = { +static const struct samsung_div_clock exynos5420_div_clks[] __initconst = { DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3), }; -static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { +static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p, SRC_TOP7, 4, 1), MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2), @@ -778,7 +778,7 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3), }; -static struct samsung_div_clock exynos5x_div_clks[] __initdata = { +static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3), @@ -911,7 +911,7 @@ static struct samsung_div_clock exynos5x_div_clks[] __initdata = { CLK_SET_RATE_PARENT, 0), }; -static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = { +static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { /* G2D */ GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0), GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0), From 880c81b3b6604a004d56b5975c8bed47276e8bf6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 11 May 2016 14:02:08 +0200 Subject: [PATCH 20/41] clk: samsung: exynos5440: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos5440.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c index 22c73d4a5ee3..a57d01b99b76 100644 --- a/drivers/clk/samsung/clk-exynos5440.c +++ b/drivers/clk/samsung/clk-exynos5440.c @@ -35,7 +35,7 @@ static struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initda }; /* fixed rate clocks */ -static struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = { +static const struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initconst = { FRATE(0, "ppll", NULL, 0, 1000000000), FRATE(0, "usb_phy0", NULL, 0, 60000000), FRATE(0, "usb_phy1", NULL, 0, 60000000), @@ -44,26 +44,26 @@ static struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = }; /* fixed factor clocks */ -static struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initdata = { +static const struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initconst = { FFACTOR(0, "div250", "ppll", 1, 4, 0), FFACTOR(0, "div200", "ppll", 1, 5, 0), FFACTOR(0, "div125", "div250", 1, 2, 0), }; /* mux clocks */ -static struct samsung_mux_clock exynos5440_mux_clks[] __initdata = { +static const struct samsung_mux_clock exynos5440_mux_clks[] __initconst = { MUX(0, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1), MUX_A(CLK_ARM_CLK, "arm_clk", mout_armclk_p, CPU_CLK_STATUS, 0, 1, "armclk"), }; /* divider clocks */ -static struct samsung_div_clock exynos5440_div_clks[] __initdata = { +static const struct samsung_div_clock exynos5440_div_clks[] __initconst = { DIV(CLK_SPI_BAUD, "div_spi", "mout_spi", MISC_DOUT1, 3, 2), }; /* gate clocks */ -static struct samsung_gate_clock exynos5440_gate_clks[] __initdata = { +static const struct samsung_gate_clock exynos5440_gate_clks[] __initconst = { GATE(CLK_PB0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0), GATE(CLK_PR0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0), GATE(CLK_PR1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0), From a3618933c167ec6cff69ebc41a2584b0d886bc3b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 11 May 2016 14:02:09 +0200 Subject: [PATCH 21/41] clk: samsung: exynos7: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos7.c | 114 +++++++++++++++--------------- 1 file changed, 57 insertions(+), 57 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c index 03a82da63910..5931a4140c3d 100644 --- a/drivers/clk/samsung/clk-exynos7.c +++ b/drivers/clk/samsung/clk-exynos7.c @@ -36,7 +36,7 @@ #define ENABLE_ACLK_TOPC1 0x0804 #define ENABLE_SCLK_TOPC1 0x0A04 -static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = { +static const struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initconst = { FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_topc_bus0_pll", 1, 2, 0), FFACTOR(0, "ffac_topc_bus0_pll_div4", "ffac_topc_bus0_pll_div2", 1, 2, 0), @@ -69,7 +69,7 @@ PNAME(mout_topc_mfc_pll_half_p) = { "mout_topc_mfc_pll", PNAME(mout_topc_bus0_pll_out_p) = {"mout_topc_bus0_pll", "ffac_topc_bus0_pll_div2"}; -static unsigned long topc_clk_regs[] __initdata = { +static const unsigned long topc_clk_regs[] __initconst = { CC_PLL_LOCK, BUS0_PLL_LOCK, BUS1_DPLL_LOCK, @@ -89,7 +89,7 @@ static unsigned long topc_clk_regs[] __initdata = { DIV_TOPC3, }; -static struct samsung_mux_clock topc_mux_clks[] __initdata = { +static const struct samsung_mux_clock topc_mux_clks[] __initconst = { MUX(0, "mout_topc_bus0_pll", mout_topc_bus0_pll_ctrl_p, MUX_SEL_TOPC0, 0, 1), MUX(0, "mout_topc_bus1_pll", mout_topc_bus1_pll_ctrl_p, @@ -118,7 +118,7 @@ static struct samsung_mux_clock topc_mux_clks[] __initdata = { MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2), }; -static struct samsung_div_clock topc_div_clks[] __initdata = { +static const struct samsung_div_clock topc_div_clks[] __initconst = { DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133", DIV_TOPC0, 4, 4), @@ -139,12 +139,12 @@ static struct samsung_div_clock topc_div_clks[] __initdata = { DIV_TOPC3, 28, 4), }; -static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = { +static const struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initconst = { PLL_36XX_RATE(491520000, 20, 1, 0, 31457), {}, }; -static struct samsung_gate_clock topc_gate_clks[] __initdata = { +static const struct samsung_gate_clock topc_gate_clks[] __initconst = { GATE(ACLK_CCORE_133, "aclk_ccore_133", "dout_aclk_ccore_133", ENABLE_ACLK_TOPC0, 4, CLK_IS_CRITICAL, 0), @@ -174,7 +174,7 @@ static struct samsung_gate_clock topc_gate_clks[] __initdata = { ENABLE_SCLK_TOPC1, 0, 0, 0), }; -static struct samsung_pll_clock topc_pll_clks[] __initdata = { +static const struct samsung_pll_clock topc_pll_clks[] __initconst = { PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK, BUS0_PLL_CON0, NULL), PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK, @@ -187,7 +187,7 @@ static struct samsung_pll_clock topc_pll_clks[] __initdata = { AUD_PLL_CON0, pll1460x_24mhz_tbl), }; -static struct samsung_cmu_info topc_cmu_info __initdata = { +static const struct samsung_cmu_info topc_cmu_info __initconst = { .pll_clks = topc_pll_clks, .nr_pll_clks = ARRAY_SIZE(topc_pll_clks), .mux_clks = topc_mux_clks, @@ -256,7 +256,7 @@ PNAME(mout_top0_group3) = {"ioclk_audiocdclk0", PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll_user", "mout_top0_bus0_pll_half", "mout_top0_bus1_pll_half"}; -static unsigned long top0_clk_regs[] __initdata = { +static const unsigned long top0_clk_regs[] __initconst = { MUX_SEL_TOP00, MUX_SEL_TOP01, MUX_SEL_TOP03, @@ -275,7 +275,7 @@ static unsigned long top0_clk_regs[] __initdata = { ENABLE_SCLK_TOP0_PERIC3, }; -static struct samsung_mux_clock top0_mux_clks[] __initdata = { +static const struct samsung_mux_clock top0_mux_clks[] __initconst = { MUX(0, "mout_top0_aud_pll_user", mout_top0_aud_pll_user_p, MUX_SEL_TOP00, 0, 1), MUX(0, "mout_top0_mfc_pll_user", mout_top0_mfc_pll_user_p, @@ -315,7 +315,7 @@ static struct samsung_mux_clock top0_mux_clks[] __initdata = { MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2), }; -static struct samsung_div_clock top0_div_clks[] __initdata = { +static const struct samsung_div_clock top0_div_clks[] __initconst = { DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66", DIV_TOP03, 12, 6), DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66", @@ -338,7 +338,7 @@ static struct samsung_div_clock top0_div_clks[] __initdata = { DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12), }; -static struct samsung_gate_clock top0_gate_clks[] __initdata = { +static const struct samsung_gate_clock top0_gate_clks[] __initconst = { GATE(CLK_ACLK_PERIC0_66, "aclk_peric0_66", "dout_aclk_peric0_66", ENABLE_ACLK_TOP03, 20, CLK_SET_RATE_PARENT, 0), GATE(CLK_ACLK_PERIC1_66, "aclk_peric1_66", "dout_aclk_peric1_66", @@ -372,7 +372,7 @@ static struct samsung_gate_clock top0_gate_clks[] __initdata = { ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0), }; -static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = { +static const struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initconst = { FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll_user", 1, 2, 0), FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll_user", @@ -381,7 +381,7 @@ static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = { FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll_user", 1, 2, 0), }; -static struct samsung_cmu_info top0_cmu_info __initdata = { +static const struct samsung_cmu_info top0_cmu_info __initconst = { .mux_clks = top0_mux_clks, .nr_mux_clks = ARRAY_SIZE(top0_mux_clks), .div_clks = top0_div_clks, @@ -438,7 +438,7 @@ PNAME(mout_top1_group1) = {"mout_top1_bus0_pll_half", "mout_top1_bus1_pll_half", "mout_top1_cc_pll_half", "mout_top1_mfc_pll_half"}; -static unsigned long top1_clk_regs[] __initdata = { +static const unsigned long top1_clk_regs[] __initconst = { MUX_SEL_TOP10, MUX_SEL_TOP11, MUX_SEL_TOP13, @@ -455,7 +455,7 @@ static unsigned long top1_clk_regs[] __initdata = { ENABLE_SCLK_TOP1_FSYS11, }; -static struct samsung_mux_clock top1_mux_clks[] __initdata = { +static const struct samsung_mux_clock top1_mux_clks[] __initconst = { MUX(0, "mout_top1_mfc_pll_user", mout_top1_mfc_pll_user_p, MUX_SEL_TOP10, 4, 1), MUX(0, "mout_top1_cc_pll_user", mout_top1_cc_pll_user_p, @@ -494,7 +494,7 @@ static struct samsung_mux_clock top1_mux_clks[] __initdata = { MUX_SEL_TOP1_FSYS11, 24, 2), }; -static struct samsung_div_clock top1_div_clks[] __initdata = { +static const struct samsung_div_clock top1_div_clks[] __initconst = { DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200", DIV_TOP13, 24, 4), DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200", @@ -521,7 +521,7 @@ static struct samsung_div_clock top1_div_clks[] __initdata = { "mout_sclk_phy_fsys1_26m", DIV_TOP1_FSYS11, 24, 6), }; -static struct samsung_gate_clock top1_gate_clks[] __initdata = { +static const struct samsung_gate_clock top1_gate_clks[] __initconst = { GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2", ENABLE_SCLK_TOP1_FSYS0, 16, CLK_SET_RATE_PARENT, 0), GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300", @@ -549,7 +549,7 @@ static struct samsung_gate_clock top1_gate_clks[] __initdata = { 24, CLK_SET_RATE_PARENT, 0), }; -static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = { +static const struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initconst = { FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll_user", 1, 2, 0), FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll_user", @@ -558,7 +558,7 @@ static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = { FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll_user", 1, 2, 0), }; -static struct samsung_cmu_info top1_cmu_info __initdata = { +static const struct samsung_cmu_info top1_cmu_info __initconst = { .mux_clks = top1_mux_clks, .nr_mux_clks = ARRAY_SIZE(top1_mux_clks), .div_clks = top1_div_clks, @@ -592,22 +592,22 @@ CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1", */ PNAME(mout_aclk_ccore_133_user_p) = { "fin_pll", "aclk_ccore_133" }; -static unsigned long ccore_clk_regs[] __initdata = { +static const unsigned long ccore_clk_regs[] __initconst = { MUX_SEL_CCORE, ENABLE_PCLK_CCORE, }; -static struct samsung_mux_clock ccore_mux_clks[] __initdata = { +static const struct samsung_mux_clock ccore_mux_clks[] __initconst = { MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_user_p, MUX_SEL_CCORE, 1, 1), }; -static struct samsung_gate_clock ccore_gate_clks[] __initdata = { +static const struct samsung_gate_clock ccore_gate_clks[] __initconst = { GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user", ENABLE_PCLK_CCORE, 8, 0, 0), }; -static struct samsung_cmu_info ccore_cmu_info __initdata = { +static const struct samsung_cmu_info ccore_cmu_info __initconst = { .mux_clks = ccore_mux_clks, .nr_mux_clks = ARRAY_SIZE(ccore_mux_clks), .gate_clks = ccore_gate_clks, @@ -634,20 +634,20 @@ CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore", PNAME(mout_aclk_peric0_66_user_p) = { "fin_pll", "aclk_peric0_66" }; PNAME(mout_sclk_uart0_user_p) = { "fin_pll", "sclk_uart0" }; -static unsigned long peric0_clk_regs[] __initdata = { +static const unsigned long peric0_clk_regs[] __initconst = { MUX_SEL_PERIC0, ENABLE_PCLK_PERIC0, ENABLE_SCLK_PERIC0, }; -static struct samsung_mux_clock peric0_mux_clks[] __initdata = { +static const struct samsung_mux_clock peric0_mux_clks[] __initconst = { MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_user_p, MUX_SEL_PERIC0, 0, 1), MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_user_p, MUX_SEL_PERIC0, 16, 1), }; -static struct samsung_gate_clock peric0_gate_clks[] __initdata = { +static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user", ENABLE_PCLK_PERIC0, 8, 0, 0), GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user", @@ -674,7 +674,7 @@ static struct samsung_gate_clock peric0_gate_clks[] __initdata = { GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0), }; -static struct samsung_cmu_info peric0_cmu_info __initdata = { +static const struct samsung_cmu_info peric0_cmu_info __initconst = { .mux_clks = peric0_mux_clks, .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), .gate_clks = peric0_gate_clks, @@ -710,7 +710,7 @@ PNAME(mout_sclk_spi2_user_p) = { "fin_pll", "sclk_spi2" }; PNAME(mout_sclk_spi3_user_p) = { "fin_pll", "sclk_spi3" }; PNAME(mout_sclk_spi4_user_p) = { "fin_pll", "sclk_spi4" }; -static unsigned long peric1_clk_regs[] __initdata = { +static const unsigned long peric1_clk_regs[] __initconst = { MUX_SEL_PERIC10, MUX_SEL_PERIC11, MUX_SEL_PERIC12, @@ -718,7 +718,7 @@ static unsigned long peric1_clk_regs[] __initdata = { ENABLE_SCLK_PERIC10, }; -static struct samsung_mux_clock peric1_mux_clks[] __initdata = { +static const struct samsung_mux_clock peric1_mux_clks[] __initconst = { MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_user_p, MUX_SEL_PERIC10, 0, 1), @@ -740,7 +740,7 @@ static struct samsung_mux_clock peric1_mux_clks[] __initdata = { MUX_SEL_PERIC11, 28, 1), }; -static struct samsung_gate_clock peric1_gate_clks[] __initdata = { +static const struct samsung_gate_clock peric1_gate_clks[] __initconst = { GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user", ENABLE_PCLK_PERIC1, 4, 0, 0), GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user", @@ -798,7 +798,7 @@ static struct samsung_gate_clock peric1_gate_clks[] __initdata = { ENABLE_SCLK_PERIC10, 19, CLK_SET_RATE_PARENT, 0), }; -static struct samsung_cmu_info peric1_cmu_info __initdata = { +static const struct samsung_cmu_info peric1_cmu_info __initconst = { .mux_clks = peric1_mux_clks, .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks), .gate_clks = peric1_gate_clks, @@ -826,7 +826,7 @@ CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1", /* List of parent clocks for Muxes in CMU_PERIS */ PNAME(mout_aclk_peris_66_user_p) = { "fin_pll", "aclk_peris_66" }; -static unsigned long peris_clk_regs[] __initdata = { +static const unsigned long peris_clk_regs[] __initconst = { MUX_SEL_PERIS, ENABLE_PCLK_PERIS, ENABLE_PCLK_PERIS_SECURE_CHIPID, @@ -834,12 +834,12 @@ static unsigned long peris_clk_regs[] __initdata = { ENABLE_SCLK_PERIS_SECURE_CHIPID, }; -static struct samsung_mux_clock peris_mux_clks[] __initdata = { +static const struct samsung_mux_clock peris_mux_clks[] __initconst = { MUX(0, "mout_aclk_peris_66_user", mout_aclk_peris_66_user_p, MUX_SEL_PERIS, 0, 1), }; -static struct samsung_gate_clock peris_gate_clks[] __initdata = { +static const struct samsung_gate_clock peris_gate_clks[] __initconst = { GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user", ENABLE_PCLK_PERIS, 6, 0, 0), GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user", @@ -853,7 +853,7 @@ static struct samsung_gate_clock peris_gate_clks[] __initdata = { GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0), }; -static struct samsung_cmu_info peris_cmu_info __initdata = { +static const struct samsung_cmu_info peris_cmu_info __initconst = { .mux_clks = peris_mux_clks, .nr_mux_clks = ARRAY_SIZE(peris_mux_clks), .gate_clks = peris_gate_clks, @@ -894,12 +894,12 @@ PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p) = { "fin_pll", "phyclk_usbdrd300_udrd30_pipe_pclk" }; /* fixed rate clocks used in the FSYS0 block */ -static struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initdata = { +static const struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initconst = { FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL, 0, 60000000), FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL, 0, 125000000), }; -static unsigned long fsys0_clk_regs[] __initdata = { +static const unsigned long fsys0_clk_regs[] __initconst = { MUX_SEL_FSYS00, MUX_SEL_FSYS01, MUX_SEL_FSYS02, @@ -910,7 +910,7 @@ static unsigned long fsys0_clk_regs[] __initdata = { ENABLE_SCLK_FSYS04, }; -static struct samsung_mux_clock fsys0_mux_clks[] __initdata = { +static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = { MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_user_p, MUX_SEL_FSYS00, 24, 1), @@ -927,7 +927,7 @@ static struct samsung_mux_clock fsys0_mux_clks[] __initdata = { MUX_SEL_FSYS02, 28, 1), }; -static struct samsung_gate_clock fsys0_gate_clks[] __initdata = { +static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = { GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user", ENABLE_ACLK_FSYS00, 3, 0, 0), GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user", @@ -961,7 +961,7 @@ static struct samsung_gate_clock fsys0_gate_clks[] __initdata = { ENABLE_SCLK_FSYS04, 28, 0, 0), }; -static struct samsung_cmu_info fsys0_cmu_info __initdata = { +static const struct samsung_cmu_info fsys0_cmu_info __initconst = { .fixed_clks = fixed_rate_clks_fsys0, .nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys0), .mux_clks = fsys0_mux_clks, @@ -1006,7 +1006,7 @@ PNAME(mout_phyclk_ufs20_rx0_user_p) = { "fin_pll", "phyclk_ufs20_rx0_symbol" }; PNAME(mout_phyclk_ufs20_rx1_user_p) = { "fin_pll", "phyclk_ufs20_rx1_symbol" }; /* fixed rate clocks used in the FSYS1 block */ -static struct samsung_fixed_rate_clock fixed_rate_clks_fsys1[] __initdata = { +static const struct samsung_fixed_rate_clock fixed_rate_clks_fsys1[] __initconst = { FRATE(PHYCLK_UFS20_TX0_SYMBOL, "phyclk_ufs20_tx0_symbol", NULL, 0, 300000000), FRATE(PHYCLK_UFS20_RX0_SYMBOL, "phyclk_ufs20_rx0_symbol", NULL, @@ -1015,7 +1015,7 @@ static struct samsung_fixed_rate_clock fixed_rate_clks_fsys1[] __initdata = { 0, 300000000), }; -static unsigned long fsys1_clk_regs[] __initdata = { +static const unsigned long fsys1_clk_regs[] __initconst = { MUX_SEL_FSYS10, MUX_SEL_FSYS11, MUX_SEL_FSYS12, @@ -1027,7 +1027,7 @@ static unsigned long fsys1_clk_regs[] __initdata = { ENABLE_SCLK_FSYS13, }; -static struct samsung_mux_clock fsys1_mux_clks[] __initdata = { +static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = { MUX(MOUT_FSYS1_PHYCLK_SEL1, "mout_fsys1_phyclk_sel1", mout_fsys1_group_p, MUX_SEL_FSYS10, 16, 2), MUX(0, "mout_fsys1_phyclk_sel0", mout_fsys1_group_p, @@ -1050,12 +1050,12 @@ static struct samsung_mux_clock fsys1_mux_clks[] __initdata = { mout_phyclk_ufs20_tx0_user_p, MUX_SEL_FSYS12, 28, 1), }; -static struct samsung_div_clock fsys1_div_clks[] __initdata = { +static const struct samsung_div_clock fsys1_div_clks[] __initconst = { DIV(DOUT_PCLK_FSYS1, "dout_pclk_fsys1", "mout_aclk_fsys1_200_user", DIV_FSYS1, 0, 2), }; -static struct samsung_gate_clock fsys1_gate_clks[] __initdata = { +static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = { GATE(SCLK_UFSUNIPRO20_USER, "sclk_ufsunipro20_user", "mout_sclk_ufsunipro20_user", ENABLE_SCLK_FSYS11, 20, 0, 0), @@ -1090,7 +1090,7 @@ static struct samsung_gate_clock fsys1_gate_clks[] __initdata = { ENABLE_SCLK_FSYS13, 24, CLK_IGNORE_UNUSED, 0), }; -static struct samsung_cmu_info fsys1_cmu_info __initdata = { +static const struct samsung_cmu_info fsys1_cmu_info __initconst = { .fixed_clks = fixed_rate_clks_fsys1, .nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys1), .mux_clks = fsys1_mux_clks, @@ -1120,22 +1120,22 @@ CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1", /* List of parent clocks for Muxes in CMU_MSCL */ PNAME(mout_aclk_mscl_532_user_p) = { "fin_pll", "aclk_mscl_532" }; -static unsigned long mscl_clk_regs[] __initdata = { +static const unsigned long mscl_clk_regs[] __initconst = { MUX_SEL_MSCL, DIV_MSCL, ENABLE_ACLK_MSCL, ENABLE_PCLK_MSCL, }; -static struct samsung_mux_clock mscl_mux_clks[] __initdata = { +static const struct samsung_mux_clock mscl_mux_clks[] __initconst = { MUX(USERMUX_ACLK_MSCL_532, "usermux_aclk_mscl_532", mout_aclk_mscl_532_user_p, MUX_SEL_MSCL, 0, 1), }; -static struct samsung_div_clock mscl_div_clks[] __initdata = { +static const struct samsung_div_clock mscl_div_clks[] __initconst = { DIV(DOUT_PCLK_MSCL, "dout_pclk_mscl", "usermux_aclk_mscl_532", DIV_MSCL, 0, 3), }; -static struct samsung_gate_clock mscl_gate_clks[] __initdata = { +static const struct samsung_gate_clock mscl_gate_clks[] __initconst = { GATE(ACLK_MSCL_0, "aclk_mscl_0", "usermux_aclk_mscl_532", ENABLE_ACLK_MSCL, 31, 0, 0), @@ -1205,7 +1205,7 @@ static struct samsung_gate_clock mscl_gate_clks[] __initdata = { ENABLE_PCLK_MSCL, 20, 0, 0), }; -static struct samsung_cmu_info mscl_cmu_info __initdata = { +static const struct samsung_cmu_info mscl_cmu_info __initconst = { .mux_clks = mscl_mux_clks, .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks), .div_clks = mscl_div_clks, @@ -1239,7 +1239,7 @@ CLK_OF_DECLARE(exynos7_clk_mscl, "samsung,exynos7-clock-mscl", PNAME(mout_aud_pll_user_p) = { "fin_pll", "fout_aud_pll" }; PNAME(mout_aud_group_p) = { "dout_aud_cdclk", "ioclk_audiocdclk0" }; -static unsigned long aud_clk_regs[] __initdata = { +static const unsigned long aud_clk_regs[] __initconst = { MUX_SEL_AUD, DIV_AUD0, DIV_AUD1, @@ -1248,13 +1248,13 @@ static unsigned long aud_clk_regs[] __initdata = { ENABLE_SCLK_AUD, }; -static struct samsung_mux_clock aud_mux_clks[] __initdata = { +static const struct samsung_mux_clock aud_mux_clks[] __initconst = { MUX(0, "mout_sclk_i2s", mout_aud_group_p, MUX_SEL_AUD, 12, 1), MUX(0, "mout_sclk_pcm", mout_aud_group_p, MUX_SEL_AUD, 16, 1), MUX(0, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 20, 1), }; -static struct samsung_div_clock aud_div_clks[] __initdata = { +static const struct samsung_div_clock aud_div_clks[] __initconst = { DIV(0, "dout_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 0, 4), DIV(0, "dout_aclk_aud", "dout_aud_ca5", DIV_AUD0, 4, 4), DIV(0, "dout_aud_pclk_dbg", "dout_aud_ca5", DIV_AUD0, 8, 4), @@ -1266,7 +1266,7 @@ static struct samsung_div_clock aud_div_clks[] __initdata = { DIV(0, "dout_aud_cdclk", "mout_aud_pll_user", DIV_AUD1, 24, 4), }; -static struct samsung_gate_clock aud_gate_clks[] __initdata = { +static const struct samsung_gate_clock aud_gate_clks[] __initconst = { GATE(SCLK_PCM, "sclk_pcm", "dout_sclk_pcm", ENABLE_SCLK_AUD, 27, CLK_SET_RATE_PARENT, 0), GATE(SCLK_I2S, "sclk_i2s", "dout_sclk_i2s", @@ -1294,7 +1294,7 @@ static struct samsung_gate_clock aud_gate_clks[] __initdata = { GATE(ACLK_ADMA, "aclk_dmac", "dout_aclk_aud", ENABLE_ACLK_AUD, 31, 0, 0), }; -static struct samsung_cmu_info aud_cmu_info __initdata = { +static const struct samsung_cmu_info aud_cmu_info __initconst = { .mux_clks = aud_mux_clks, .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), .div_clks = aud_div_clks, From a6cd1fbc4b9d96becf7aa884f98e8a260da5301c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 11 May 2016 14:02:10 +0200 Subject: [PATCH 22/41] clk: samsung: exynos5433: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos5433.c | 240 +++++++++++++-------------- 1 file changed, 120 insertions(+), 120 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 128527b8fbeb..f202a51ff99b 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -108,7 +108,7 @@ #define ENABLE_CMU_TOP 0x0c00 #define ENABLE_CMU_TOP_DIV_STAT 0x0c04 -static unsigned long top_clk_regs[] __initdata = { +static const unsigned long top_clk_regs[] __initconst = { ISP_PLL_LOCK, AUD_PLL_LOCK, ISP_PLL_CON0, @@ -218,11 +218,11 @@ PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "oscclk", PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", }; -static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = { +static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = { FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0), }; -static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = { +static const struct samsung_fixed_rate_clock top_fixed_clks[] __initconst = { /* Xi2s{0|1}CDCLK input clock for I2S/PCM */ FRATE(0, "ioclk_audiocdclk1", NULL, 0, 100000000), FRATE(0, "ioclk_audiocdclk0", NULL, 0, 100000000), @@ -238,7 +238,7 @@ static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = { FRATE(0, "ioclk_i2s1_bclk_in", NULL, 0, 12288000), }; -static struct samsung_mux_clock top_mux_clks[] __initdata = { +static const struct samsung_mux_clock top_mux_clks[] __initconst = { /* MUX_SEL_TOP0 */ MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0, 4, 1), @@ -374,7 +374,7 @@ static struct samsung_mux_clock top_mux_clks[] __initdata = { mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1), }; -static struct samsung_div_clock top_div_clks[] __initdata = { +static const struct samsung_div_clock top_div_clks[] __initconst = { /* DIV_TOP0 */ DIV(CLK_DIV_ACLK_CAM1_333, "div_aclk_cam1_333", "mout_aclk_cam1_333", DIV_TOP0, 28, 3), @@ -538,7 +538,7 @@ static struct samsung_div_clock top_div_clks[] __initdata = { DIV_TOP_PERIC4, 0, 4), }; -static struct samsung_gate_clock top_gate_clks[] __initdata = { +static const struct samsung_gate_clock top_gate_clks[] __initconst = { /* ENABLE_ACLK_TOP */ GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400", ENABLE_ACLK_TOP, 30, 0, 0), @@ -693,7 +693,7 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = { * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL */ -static struct samsung_pll_rate_table exynos5443_pll_rates[] = { +static const struct samsung_pll_rate_table exynos5443_pll_rates[] = { PLL_35XX_RATE(2500000000U, 625, 6, 0), PLL_35XX_RATE(2400000000U, 500, 5, 0), PLL_35XX_RATE(2300000000U, 575, 6, 0), @@ -744,7 +744,7 @@ static struct samsung_pll_rate_table exynos5443_pll_rates[] = { }; /* AUD_PLL */ -static struct samsung_pll_rate_table exynos5443_aud_pll_rates[] = { +static const struct samsung_pll_rate_table exynos5443_aud_pll_rates[] = { PLL_36XX_RATE(400000000U, 200, 3, 2, 0), PLL_36XX_RATE(393216000U, 197, 3, 2, -25690), PLL_36XX_RATE(384000000U, 128, 2, 2, 0), @@ -757,14 +757,14 @@ static struct samsung_pll_rate_table exynos5443_aud_pll_rates[] = { { /* sentinel */ } }; -static struct samsung_pll_clock top_pll_clks[] __initdata = { +static const struct samsung_pll_clock top_pll_clks[] __initconst = { PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk", ISP_PLL_LOCK, ISP_PLL_CON0, exynos5443_pll_rates), PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk", AUD_PLL_LOCK, AUD_PLL_CON0, exynos5443_aud_pll_rates), }; -static struct samsung_cmu_info top_cmu_info __initdata = { +static const struct samsung_cmu_info top_cmu_info __initconst = { .pll_clks = top_pll_clks, .nr_pll_clks = ARRAY_SIZE(top_pll_clks), .mux_clks = top_mux_clks, @@ -800,7 +800,7 @@ CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top", #define DIV_CPIF 0x0600 #define ENABLE_SCLK_CPIF 0x0a00 -static unsigned long cpif_clk_regs[] __initdata = { +static const unsigned long cpif_clk_regs[] __initconst = { MPHY_PLL_LOCK, MPHY_PLL_CON0, MPHY_PLL_CON1, @@ -813,24 +813,24 @@ static unsigned long cpif_clk_regs[] __initdata = { /* list of all parent clock list */ PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", }; -static struct samsung_pll_clock cpif_pll_clks[] __initdata = { +static const struct samsung_pll_clock cpif_pll_clks[] __initconst = { PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk", MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5443_pll_rates), }; -static struct samsung_mux_clock cpif_mux_clks[] __initdata = { +static const struct samsung_mux_clock cpif_mux_clks[] __initconst = { /* MUX_SEL_CPIF0 */ MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0, 0, 1), }; -static struct samsung_div_clock cpif_div_clks[] __initdata = { +static const struct samsung_div_clock cpif_div_clks[] __initconst = { /* DIV_CPIF */ DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF, 0, 6), }; -static struct samsung_gate_clock cpif_gate_clks[] __initdata = { +static const struct samsung_gate_clock cpif_gate_clks[] __initconst = { /* ENABLE_SCLK_CPIF */ GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll", ENABLE_SCLK_CPIF, 9, 0, 0), @@ -838,7 +838,7 @@ static struct samsung_gate_clock cpif_gate_clks[] __initdata = { ENABLE_SCLK_CPIF, 4, 0, 0), }; -static struct samsung_cmu_info cpif_cmu_info __initdata = { +static const struct samsung_cmu_info cpif_cmu_info __initconst = { .pll_clks = cpif_pll_clks, .nr_pll_clks = ARRAY_SIZE(cpif_pll_clks), .mux_clks = cpif_mux_clks, @@ -939,7 +939,7 @@ CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif", #define PAUSE 0x1008 #define DDRPHY_LOCK_CTRL 0x100c -static unsigned long mif_clk_regs[] __initdata = { +static const unsigned long mif_clk_regs[] __initconst = { MEM0_PLL_LOCK, MEM1_PLL_LOCK, BUS_PLL_LOCK, @@ -1004,7 +1004,7 @@ static unsigned long mif_clk_regs[] __initdata = { DDRPHY_LOCK_CTRL, }; -static struct samsung_pll_clock mif_pll_clks[] __initdata = { +static const struct samsung_pll_clock mif_pll_clks[] __initconst = { PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk", MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5443_pll_rates), PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk", @@ -1065,7 +1065,7 @@ PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a", PNAME(mout_sclk_dsim1_c_p) = { "mout_sclk_dsim1_b", "sclk_mphy_pll", }; PNAME(mout_sclk_dsim1_b_p) = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",}; -static struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initdata = { +static const struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initconst = { /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */ FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0), FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0), @@ -1073,7 +1073,7 @@ static struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initdata = { FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0), }; -static struct samsung_mux_clock mif_mux_clks[] __initdata = { +static const struct samsung_mux_clock mif_mux_clks[] __initconst = { /* MUX_SEL_MIF0 */ MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p, MUX_SEL_MIF0, 28, 1), @@ -1169,7 +1169,7 @@ static struct samsung_mux_clock mif_mux_clks[] __initdata = { MUX_SEL_MIF7, 0, 1), }; -static struct samsung_div_clock mif_div_clks[] __initdata = { +static const struct samsung_div_clock mif_div_clks[] __initconst = { /* DIV_MIF1 */ DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy", DIV_MIF1, 16, 2), @@ -1223,7 +1223,7 @@ static struct samsung_div_clock mif_div_clks[] __initdata = { 0, 3), }; -static struct samsung_gate_clock mif_gate_clks[] __initdata = { +static const struct samsung_gate_clock mif_gate_clks[] __initconst = { /* ENABLE_ACLK_MIF0 */ GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0, 19, CLK_IGNORE_UNUSED, 0), @@ -1486,7 +1486,7 @@ static struct samsung_gate_clock mif_gate_clks[] __initdata = { ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0), }; -static struct samsung_cmu_info mif_cmu_info __initdata = { +static const struct samsung_cmu_info mif_cmu_info __initconst = { .pll_clks = mif_pll_clks, .nr_pll_clks = ARRAY_SIZE(mif_pll_clks), .mux_clks = mif_mux_clks, @@ -1522,7 +1522,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif", #define ENABLE_IP_PERIC1 0x0B04 #define ENABLE_IP_PERIC2 0x0B08 -static unsigned long peric_clk_regs[] __initdata = { +static const unsigned long peric_clk_regs[] __initconst = { DIV_PERIC, ENABLE_ACLK_PERIC, ENABLE_PCLK_PERIC0, @@ -1533,13 +1533,13 @@ static unsigned long peric_clk_regs[] __initdata = { ENABLE_IP_PERIC2, }; -static struct samsung_div_clock peric_div_clks[] __initdata = { +static const struct samsung_div_clock peric_div_clks[] __initconst = { /* DIV_PERIC */ DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4), DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4), }; -static struct samsung_gate_clock peric_gate_clks[] __initdata = { +static const struct samsung_gate_clock peric_gate_clks[] __initconst = { /* ENABLE_ACLK_PERIC */ GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66", ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0), @@ -1681,7 +1681,7 @@ static struct samsung_gate_clock peric_gate_clks[] __initdata = { ENABLE_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), }; -static struct samsung_cmu_info peric_cmu_info __initdata = { +static const struct samsung_cmu_info peric_cmu_info __initconst = { .div_clks = peric_div_clks, .nr_div_clks = ARRAY_SIZE(peric_div_clks), .gate_clks = peric_gate_clks, @@ -1728,7 +1728,7 @@ CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric", #define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c #define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20 -static unsigned long peris_clk_regs[] __initdata = { +static const unsigned long peris_clk_regs[] __initconst = { ENABLE_ACLK_PERIS, ENABLE_PCLK_PERIS, ENABLE_PCLK_PERIS_SECURE_TZPC, @@ -1756,7 +1756,7 @@ static unsigned long peris_clk_regs[] __initdata = { ENABLE_IP_PERIS_SECURE_OTP_CON, }; -static struct samsung_gate_clock peris_gate_clks[] __initdata = { +static const struct samsung_gate_clock peris_gate_clks[] __initconst = { /* ENABLE_ACLK_PERIS */ GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66", ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0), @@ -1875,7 +1875,7 @@ static struct samsung_gate_clock peris_gate_clks[] __initdata = { ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0), }; -static struct samsung_cmu_info peris_cmu_info __initdata = { +static const struct samsung_cmu_info peris_cmu_info __initconst = { .gate_clks = peris_gate_clks, .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), .nr_clk_ids = PERIS_NR_CLK, @@ -1959,7 +1959,7 @@ PNAME(mout_sclk_mphy_p) = { "mout_sclk_ufs_mphy_user", "mout_phyclk_lli_mphy_to_ufs_user", }; -static unsigned long fsys_clk_regs[] __initdata = { +static const unsigned long fsys_clk_regs[] __initconst = { MUX_SEL_FSYS0, MUX_SEL_FSYS1, MUX_SEL_FSYS2, @@ -1980,7 +1980,7 @@ static unsigned long fsys_clk_regs[] __initdata = { ENABLE_IP_FSYS1, }; -static struct samsung_fixed_rate_clock fsys_fixed_clks[] __initdata = { +static const struct samsung_fixed_rate_clock fsys_fixed_clks[] __initconst = { /* PHY clocks from USBDRD30_PHY */ FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY, "phyclk_usbdrd30_udrd30_phyclock_phy", NULL, @@ -2020,7 +2020,7 @@ static struct samsung_fixed_rate_clock fsys_fixed_clks[] __initdata = { NULL, 0, 26000000), }; -static struct samsung_mux_clock fsys_mux_clks[] __initdata = { +static const struct samsung_mux_clock fsys_mux_clks[] __initconst = { /* MUX_SEL_FSYS0 */ MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user", mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1), @@ -2104,7 +2104,7 @@ static struct samsung_mux_clock fsys_mux_clks[] __initdata = { MUX_SEL_FSYS4, 0, 1), }; -static struct samsung_gate_clock fsys_gate_clks[] __initdata = { +static const struct samsung_gate_clock fsys_gate_clks[] __initconst = { /* ENABLE_ACLK_FSYS0 */ GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0), @@ -2274,7 +2274,7 @@ static struct samsung_gate_clock fsys_gate_clks[] __initdata = { GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0), }; -static struct samsung_cmu_info fsys_cmu_info __initdata = { +static const struct samsung_cmu_info fsys_cmu_info __initconst = { .mux_clks = fsys_mux_clks, .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks), .gate_clks = fsys_gate_clks, @@ -2310,7 +2310,7 @@ CLK_OF_DECLARE(exynos5433_cmu_fsys, "samsung,exynos5433-cmu-fsys", #define DIV_ENABLE_IP_G2D1 0x0b04 #define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08 -static unsigned long g2d_clk_regs[] __initdata = { +static const unsigned long g2d_clk_regs[] __initconst = { MUX_SEL_G2D0, MUX_SEL_ENABLE_G2D0, DIV_G2D, @@ -2327,7 +2327,7 @@ static unsigned long g2d_clk_regs[] __initdata = { PNAME(mout_aclk_g2d_266_user_p) = { "oscclk", "aclk_g2d_266", }; PNAME(mout_aclk_g2d_400_user_p) = { "oscclk", "aclk_g2d_400", }; -static struct samsung_mux_clock g2d_mux_clks[] __initdata = { +static const struct samsung_mux_clock g2d_mux_clks[] __initconst = { /* MUX_SEL_G2D0 */ MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user", mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1), @@ -2335,13 +2335,13 @@ static struct samsung_mux_clock g2d_mux_clks[] __initdata = { mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1), }; -static struct samsung_div_clock g2d_div_clks[] __initdata = { +static const struct samsung_div_clock g2d_div_clks[] __initconst = { /* DIV_G2D */ DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user", DIV_G2D, 0, 2), }; -static struct samsung_gate_clock g2d_gate_clks[] __initdata = { +static const struct samsung_gate_clock g2d_gate_clks[] __initconst = { /* DIV_ENABLE_ACLK_G2D */ GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user", DIV_ENABLE_ACLK_G2D, 12, 0, 0), @@ -2398,7 +2398,7 @@ static struct samsung_gate_clock g2d_gate_clks[] __initdata = { DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0), }; -static struct samsung_cmu_info g2d_cmu_info __initdata = { +static const struct samsung_cmu_info g2d_cmu_info __initconst = { .mux_clks = g2d_mux_clks, .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks), .div_clks = g2d_div_clks, @@ -2454,7 +2454,7 @@ CLK_OF_DECLARE(exynos5433_cmu_g2d, "samsung,exynos5433-cmu-g2d", #define CLKOUT_CMU_DISP 0x0c00 #define CLKOUT_CMU_DISP_DIV_STAT 0x0c04 -static unsigned long disp_clk_regs[] __initdata = { +static const unsigned long disp_clk_regs[] __initconst = { DISP_PLL_LOCK, DISP_PLL_CON0, DISP_PLL_CON1, @@ -2527,12 +2527,12 @@ PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = { PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp", "mout_sclk_decon_tv_vclk_user", }; -static struct samsung_pll_clock disp_pll_clks[] __initdata = { +static const struct samsung_pll_clock disp_pll_clks[] __initconst = { PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk", DISP_PLL_LOCK, DISP_PLL_CON0, exynos5443_pll_rates), }; -static struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initdata = { +static const struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initconst = { /* * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}. * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk} @@ -2544,7 +2544,7 @@ static struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initdata = { 1, 2, 0), }; -static struct samsung_fixed_rate_clock disp_fixed_clks[] __initdata = { +static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = { /* PHY clocks from MIPI_DPHY1 */ FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000), FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000), @@ -2558,7 +2558,7 @@ static struct samsung_fixed_rate_clock disp_fixed_clks[] __initdata = { NULL, 0, 166000000), }; -static struct samsung_mux_clock disp_mux_clks[] __initdata = { +static const struct samsung_mux_clock disp_mux_clks[] __initconst = { /* MUX_SEL_DISP0 */ MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0, 0, 1), @@ -2633,7 +2633,7 @@ static struct samsung_mux_clock disp_mux_clks[] __initdata = { mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1), }; -static struct samsung_div_clock disp_div_clks[] __initdata = { +static const struct samsung_div_clock disp_div_clks[] __initconst = { /* DIV_DISP */ DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp", "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3), @@ -2651,7 +2651,7 @@ static struct samsung_div_clock disp_div_clks[] __initdata = { DIV_DISP, 0, 2), }; -static struct samsung_gate_clock disp_gate_clks[] __initdata = { +static const struct samsung_gate_clock disp_gate_clks[] __initconst = { /* ENABLE_ACLK_DISP0 */ GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user", ENABLE_ACLK_DISP0, 2, 0, 0), @@ -2811,7 +2811,7 @@ static struct samsung_gate_clock disp_gate_clks[] __initdata = { "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0), }; -static struct samsung_cmu_info disp_cmu_info __initdata = { +static const struct samsung_cmu_info disp_cmu_info __initconst = { .pll_clks = disp_pll_clks, .nr_pll_clks = ARRAY_SIZE(disp_pll_clks), .mux_clks = disp_mux_clks, @@ -2856,7 +2856,7 @@ CLK_OF_DECLARE(exynos5433_cmu_disp, "samsung,exynos5433-cmu-disp", #define ENABLE_IP_AUD0 0x0b00 #define ENABLE_IP_AUD1 0x0b04 -static unsigned long aud_clk_regs[] __initdata = { +static const unsigned long aud_clk_regs[] __initconst = { MUX_SEL_AUD0, MUX_SEL_AUD1, MUX_ENABLE_AUD0, @@ -2875,13 +2875,13 @@ static unsigned long aud_clk_regs[] __initdata = { PNAME(mout_aud_pll_user_aud_p) = { "oscclk", "fout_aud_pll", }; PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",}; -static struct samsung_fixed_rate_clock aud_fixed_clks[] __initdata = { +static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = { FRATE(0, "ioclk_jtag_tclk", NULL, 0, 33000000), FRATE(0, "ioclk_slimbus_clk", NULL, 0, 25000000), FRATE(0, "ioclk_i2s_bclk", NULL, 0, 50000000), }; -static struct samsung_mux_clock aud_mux_clks[] __initdata = { +static const struct samsung_mux_clock aud_mux_clks[] __initconst = { /* MUX_SEL_AUD0 */ MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user", mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1), @@ -2893,7 +2893,7 @@ static struct samsung_mux_clock aud_mux_clks[] __initdata = { MUX_SEL_AUD1, 0, 1), }; -static struct samsung_div_clock aud_div_clks[] __initdata = { +static const struct samsung_div_clock aud_div_clks[] __initconst = { /* DIV_AUD0 */ DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0, 12, 4), @@ -2915,7 +2915,7 @@ static struct samsung_div_clock aud_div_clks[] __initdata = { DIV_AUD1, 0, 4), }; -static struct samsung_gate_clock aud_gate_clks[] __initdata = { +static const struct samsung_gate_clock aud_gate_clks[] __initconst = { /* ENABLE_ACLK_AUD */ GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud", ENABLE_ACLK_AUD, 12, 0, 0), @@ -2985,7 +2985,7 @@ static struct samsung_gate_clock aud_gate_clks[] __initdata = { ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0), }; -static struct samsung_cmu_info aud_cmu_info __initdata = { +static const struct samsung_cmu_info aud_cmu_info __initconst = { .mux_clks = aud_mux_clks, .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), .div_clks = aud_div_clks, @@ -3031,24 +3031,24 @@ PNAME(mout_aclk_bus2_400_p) = { "oscclk", "aclk_bus2_400", }; ENABLE_IP_BUS0, \ ENABLE_IP_BUS1 -static unsigned long bus01_clk_regs[] __initdata = { +static const unsigned long bus01_clk_regs[] __initconst = { CMU_BUS_COMMON_CLK_REGS, }; -static unsigned long bus2_clk_regs[] __initdata = { +static const unsigned long bus2_clk_regs[] __initconst = { MUX_SEL_BUS2, MUX_ENABLE_BUS2, CMU_BUS_COMMON_CLK_REGS, }; -static struct samsung_div_clock bus0_div_clks[] __initdata = { +static const struct samsung_div_clock bus0_div_clks[] __initconst = { /* DIV_BUS0 */ DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400", DIV_BUS, 0, 3), }; /* CMU_BUS0 clocks */ -static struct samsung_gate_clock bus0_gate_clks[] __initdata = { +static const struct samsung_gate_clock bus0_gate_clks[] __initconst = { /* ENABLE_ACLK_BUS0 */ GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133", ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0), @@ -3067,13 +3067,13 @@ static struct samsung_gate_clock bus0_gate_clks[] __initdata = { }; /* CMU_BUS1 clocks */ -static struct samsung_div_clock bus1_div_clks[] __initdata = { +static const struct samsung_div_clock bus1_div_clks[] __initconst = { /* DIV_BUS1 */ DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400", DIV_BUS, 0, 3), }; -static struct samsung_gate_clock bus1_gate_clks[] __initdata = { +static const struct samsung_gate_clock bus1_gate_clks[] __initconst = { /* ENABLE_ACLK_BUS1 */ GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133", ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0), @@ -3092,19 +3092,19 @@ static struct samsung_gate_clock bus1_gate_clks[] __initdata = { }; /* CMU_BUS2 clocks */ -static struct samsung_mux_clock bus2_mux_clks[] __initdata = { +static const struct samsung_mux_clock bus2_mux_clks[] __initconst = { /* MUX_SEL_BUS2 */ MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user", mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1), }; -static struct samsung_div_clock bus2_div_clks[] __initdata = { +static const struct samsung_div_clock bus2_div_clks[] __initconst = { /* DIV_BUS2 */ DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133", "mout_aclk_bus2_400_user", DIV_BUS, 0, 3), }; -static struct samsung_gate_clock bus2_gate_clks[] __initdata = { +static const struct samsung_gate_clock bus2_gate_clks[] __initconst = { /* ENABLE_ACLK_BUS2 */ GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133", ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0), @@ -3133,19 +3133,19 @@ static struct samsung_gate_clock bus2_gate_clks[] __initdata = { .nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \ .nr_clk_ids = BUSx_NR_CLK -static struct samsung_cmu_info bus0_cmu_info __initdata = { +static const struct samsung_cmu_info bus0_cmu_info __initconst = { CMU_BUS_INFO_CLKS(0), .clk_regs = bus01_clk_regs, .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs), }; -static struct samsung_cmu_info bus1_cmu_info __initdata = { +static const struct samsung_cmu_info bus1_cmu_info __initconst = { CMU_BUS_INFO_CLKS(1), .clk_regs = bus01_clk_regs, .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs), }; -static struct samsung_cmu_info bus2_cmu_info __initdata = { +static const struct samsung_cmu_info bus2_cmu_info __initconst = { CMU_BUS_INFO_CLKS(2), .mux_clks = bus2_mux_clks, .nr_mux_clks = ARRAY_SIZE(bus2_mux_clks), @@ -3189,7 +3189,7 @@ exynos5433_cmu_bus_init(2); #define CLKOUT_CMU_G3D_DIV_STAT 0x0c04 #define CLK_STOPCTRL 0x1000 -static unsigned long g3d_clk_regs[] __initdata = { +static const unsigned long g3d_clk_regs[] __initconst = { G3D_PLL_LOCK, G3D_PLL_CON0, G3D_PLL_CON1, @@ -3212,12 +3212,12 @@ static unsigned long g3d_clk_regs[] __initdata = { PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", }; PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll", }; -static struct samsung_pll_clock g3d_pll_clks[] __initdata = { +static const struct samsung_pll_clock g3d_pll_clks[] __initconst = { PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk", G3D_PLL_LOCK, G3D_PLL_CON0, exynos5443_pll_rates), }; -static struct samsung_mux_clock g3d_mux_clks[] __initdata = { +static const struct samsung_mux_clock g3d_mux_clks[] __initconst = { /* MUX_SEL_G3D */ MUX_F(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p, MUX_SEL_G3D, 8, 1, CLK_SET_RATE_PARENT, 0), @@ -3225,7 +3225,7 @@ static struct samsung_mux_clock g3d_mux_clks[] __initdata = { MUX_SEL_G3D, 0, 1, CLK_SET_RATE_PARENT, 0), }; -static struct samsung_div_clock g3d_div_clks[] __initdata = { +static const struct samsung_div_clock g3d_div_clks[] __initconst = { /* DIV_G3D */ DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D, 8, 2), @@ -3235,7 +3235,7 @@ static struct samsung_div_clock g3d_div_clks[] __initdata = { 0, 3, CLK_SET_RATE_PARENT, 0), }; -static struct samsung_gate_clock g3d_gate_clks[] __initdata = { +static const struct samsung_gate_clock g3d_gate_clks[] __initconst = { /* ENABLE_ACLK_G3D */ GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d", ENABLE_ACLK_G3D, 7, 0, 0), @@ -3269,7 +3269,7 @@ static struct samsung_gate_clock g3d_gate_clks[] __initdata = { ENABLE_SCLK_G3D, 0, 0, 0), }; -static struct samsung_cmu_info g3d_cmu_info __initdata = { +static const struct samsung_cmu_info g3d_cmu_info __initconst = { .pll_clks = g3d_pll_clks, .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks), .mux_clks = g3d_mux_clks, @@ -3310,7 +3310,7 @@ CLK_OF_DECLARE(exynos5433_cmu_g3d, "samsung,exynos5433-cmu-g3d", #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10 -static unsigned long gscl_clk_regs[] __initdata = { +static const unsigned long gscl_clk_regs[] __initconst = { MUX_SEL_GSCL, MUX_ENABLE_GSCL, ENABLE_ACLK_GSCL, @@ -3332,7 +3332,7 @@ static unsigned long gscl_clk_regs[] __initdata = { PNAME(aclk_gscl_111_user_p) = { "oscclk", "aclk_gscl_111", }; PNAME(aclk_gscl_333_user_p) = { "oscclk", "aclk_gscl_333", }; -static struct samsung_mux_clock gscl_mux_clks[] __initdata = { +static const struct samsung_mux_clock gscl_mux_clks[] __initconst = { /* MUX_SEL_GSCL */ MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user", aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1), @@ -3340,7 +3340,7 @@ static struct samsung_mux_clock gscl_mux_clks[] __initdata = { aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1), }; -static struct samsung_gate_clock gscl_gate_clks[] __initdata = { +static const struct samsung_gate_clock gscl_gate_clks[] __initconst = { /* ENABLE_ACLK_GSCL */ GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 11, 0, 0), @@ -3412,7 +3412,7 @@ static struct samsung_gate_clock gscl_gate_clks[] __initdata = { ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0), }; -static struct samsung_cmu_info gscl_cmu_info __initdata = { +static const struct samsung_cmu_info gscl_cmu_info __initconst = { .mux_clks = gscl_mux_clks, .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks), .gate_clks = gscl_gate_clks, @@ -3465,7 +3465,7 @@ CLK_OF_DECLARE(exynos5433_cmu_gscl, "samsung,exynos5433-cmu-gscl", #define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084 #define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088 -static unsigned long apollo_clk_regs[] __initdata = { +static const unsigned long apollo_clk_regs[] __initconst = { APOLLO_PLL_LOCK, APOLLO_PLL_CON0, APOLLO_PLL_CON1, @@ -3500,12 +3500,12 @@ PNAME(mout_bus_pll_apollo_user_p) = { "oscclk", "sclk_bus_pll_apollo", }; PNAME(mout_apollo_p) = { "mout_apollo_pll", "mout_bus_pll_apollo_user", }; -static struct samsung_pll_clock apollo_pll_clks[] __initdata = { +static const struct samsung_pll_clock apollo_pll_clks[] __initconst = { PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk", APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5443_pll_rates), }; -static struct samsung_mux_clock apollo_mux_clks[] __initdata = { +static const struct samsung_mux_clock apollo_mux_clks[] __initconst = { /* MUX_SEL_APOLLO0 */ MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p, MUX_SEL_APOLLO0, 0, 1, CLK_SET_RATE_PARENT, 0), @@ -3519,7 +3519,7 @@ static struct samsung_mux_clock apollo_mux_clks[] __initdata = { 0, 1, CLK_SET_RATE_PARENT, 0), }; -static struct samsung_div_clock apollo_div_clks[] __initdata = { +static const struct samsung_div_clock apollo_div_clks[] __initconst = { /* DIV_APOLLO0 */ DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2", DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE, @@ -3550,7 +3550,7 @@ static struct samsung_div_clock apollo_div_clks[] __initdata = { CLK_DIVIDER_READ_ONLY), }; -static struct samsung_gate_clock apollo_gate_clks[] __initdata = { +static const struct samsung_gate_clock apollo_gate_clks[] __initconst = { /* ENABLE_ACLK_APOLLO */ GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys", "div_atclk_apollo", ENABLE_ACLK_APOLLO, @@ -3594,7 +3594,7 @@ static struct samsung_gate_clock apollo_gate_clks[] __initdata = { CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), }; -static struct samsung_cmu_info apollo_cmu_info __initdata = { +static const struct samsung_cmu_info apollo_cmu_info __initconst = { .pll_clks = apollo_pll_clks, .nr_pll_clks = ARRAY_SIZE(apollo_pll_clks), .mux_clks = apollo_mux_clks, @@ -3651,7 +3651,7 @@ CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo", #define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0x1084 #define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088 -static unsigned long atlas_clk_regs[] __initdata = { +static const unsigned long atlas_clk_regs[] __initconst = { ATLAS_PLL_LOCK, ATLAS_PLL_CON0, ATLAS_PLL_CON1, @@ -3686,12 +3686,12 @@ PNAME(mout_bus_pll_atlas_user_p) = { "oscclk", "sclk_bus_pll_atlas", }; PNAME(mout_atlas_p) = { "mout_atlas_pll", "mout_bus_pll_atlas_user", }; -static struct samsung_pll_clock atlas_pll_clks[] __initdata = { +static const struct samsung_pll_clock atlas_pll_clks[] __initconst = { PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk", ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5443_pll_rates), }; -static struct samsung_mux_clock atlas_mux_clks[] __initdata = { +static const struct samsung_mux_clock atlas_mux_clks[] __initconst = { /* MUX_SEL_ATLAS0 */ MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p, MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT, 0), @@ -3705,7 +3705,7 @@ static struct samsung_mux_clock atlas_mux_clks[] __initdata = { 0, 1, CLK_SET_RATE_PARENT, 0), }; -static struct samsung_div_clock atlas_div_clks[] __initdata = { +static const struct samsung_div_clock atlas_div_clks[] __initconst = { /* DIV_ATLAS0 */ DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2", DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE, @@ -3736,7 +3736,7 @@ static struct samsung_div_clock atlas_div_clks[] __initdata = { CLK_DIVIDER_READ_ONLY), }; -static struct samsung_gate_clock atlas_gate_clks[] __initdata = { +static const struct samsung_gate_clock atlas_gate_clks[] __initconst = { /* ENABLE_ACLK_ATLAS */ GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys", "div_atclk_atlas", ENABLE_ACLK_ATLAS, @@ -3806,7 +3806,7 @@ static struct samsung_gate_clock atlas_gate_clks[] __initdata = { CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), }; -static struct samsung_cmu_info atlas_cmu_info __initdata = { +static const struct samsung_cmu_info atlas_cmu_info __initconst = { .pll_clks = atlas_pll_clks, .nr_pll_clks = ARRAY_SIZE(atlas_pll_clks), .mux_clks = atlas_mux_clks, @@ -3853,7 +3853,7 @@ CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas", #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 0x0b0c #define ENABLE_IP_MSCL_SECURE_SMMU_JPEG 0x0b10 -static unsigned long mscl_clk_regs[] __initdata = { +static const unsigned long mscl_clk_regs[] __initconst = { MUX_SEL_MSCL0, MUX_SEL_MSCL1, MUX_ENABLE_MSCL0, @@ -3881,7 +3881,7 @@ PNAME(mout_aclk_mscl_400_user_p) = { "oscclk", "aclk_mscl_400", }; PNAME(mout_sclk_jpeg_p) = { "mout_sclk_jpeg_user", "mout_aclk_mscl_400_user", }; -static struct samsung_mux_clock mscl_mux_clks[] __initdata = { +static const struct samsung_mux_clock mscl_mux_clks[] __initconst = { /* MUX_SEL_MSCL0 */ MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user", mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1), @@ -3893,13 +3893,13 @@ static struct samsung_mux_clock mscl_mux_clks[] __initdata = { MUX_SEL_MSCL1, 0, 1), }; -static struct samsung_div_clock mscl_div_clks[] __initdata = { +static const struct samsung_div_clock mscl_div_clks[] __initconst = { /* DIV_MSCL */ DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user", DIV_MSCL, 0, 3), }; -static struct samsung_gate_clock mscl_gate_clks[] __initdata = { +static const struct samsung_gate_clock mscl_gate_clks[] __initconst = { /* ENABLE_ACLK_MSCL */ GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 9, 0, 0), @@ -3977,7 +3977,7 @@ static struct samsung_gate_clock mscl_gate_clks[] __initdata = { CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), }; -static struct samsung_cmu_info mscl_cmu_info __initdata = { +static const struct samsung_cmu_info mscl_cmu_info __initconst = { .mux_clks = mscl_mux_clks, .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks), .div_clks = mscl_div_clks, @@ -4012,7 +4012,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mscl, "samsung,exynos5433-cmu-mscl", #define ENABLE_IP_MFC1 0x0b04 #define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08 -static unsigned long mfc_clk_regs[] __initdata = { +static const unsigned long mfc_clk_regs[] __initconst = { MUX_SEL_MFC, MUX_ENABLE_MFC, DIV_MFC, @@ -4027,19 +4027,19 @@ static unsigned long mfc_clk_regs[] __initdata = { PNAME(mout_aclk_mfc_400_user_p) = { "oscclk", "aclk_mfc_400", }; -static struct samsung_mux_clock mfc_mux_clks[] __initdata = { +static const struct samsung_mux_clock mfc_mux_clks[] __initconst = { /* MUX_SEL_MFC */ MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user", mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0), }; -static struct samsung_div_clock mfc_div_clks[] __initdata = { +static const struct samsung_div_clock mfc_div_clks[] __initconst = { /* DIV_MFC */ DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user", DIV_MFC, 0, 2), }; -static struct samsung_gate_clock mfc_gate_clks[] __initdata = { +static const struct samsung_gate_clock mfc_gate_clks[] __initconst = { /* ENABLE_ACLK_MFC */ GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user", ENABLE_ACLK_MFC, 6, 0, 0), @@ -4085,7 +4085,7 @@ static struct samsung_gate_clock mfc_gate_clks[] __initdata = { 0, CLK_IGNORE_UNUSED, 0), }; -static struct samsung_cmu_info mfc_cmu_info __initdata = { +static const struct samsung_cmu_info mfc_cmu_info __initconst = { .mux_clks = mfc_mux_clks, .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks), .div_clks = mfc_div_clks, @@ -4120,7 +4120,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mfc, "samsung,exynos5433-cmu-mfc", #define ENABLE_IP_HEVC1 0x0b04 #define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0x0b08 -static unsigned long hevc_clk_regs[] __initdata = { +static const unsigned long hevc_clk_regs[] __initconst = { MUX_SEL_HEVC, MUX_ENABLE_HEVC, DIV_HEVC, @@ -4135,19 +4135,19 @@ static unsigned long hevc_clk_regs[] __initdata = { PNAME(mout_aclk_hevc_400_user_p) = { "oscclk", "aclk_hevc_400", }; -static struct samsung_mux_clock hevc_mux_clks[] __initdata = { +static const struct samsung_mux_clock hevc_mux_clks[] __initconst = { /* MUX_SEL_HEVC */ MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user", mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0), }; -static struct samsung_div_clock hevc_div_clks[] __initdata = { +static const struct samsung_div_clock hevc_div_clks[] __initconst = { /* DIV_HEVC */ DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user", DIV_HEVC, 0, 2), }; -static struct samsung_gate_clock hevc_gate_clks[] __initdata = { +static const struct samsung_gate_clock hevc_gate_clks[] __initconst = { /* ENABLE_ACLK_HEVC */ GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user", ENABLE_ACLK_HEVC, 6, 0, 0), @@ -4195,7 +4195,7 @@ static struct samsung_gate_clock hevc_gate_clks[] __initdata = { 0, CLK_IGNORE_UNUSED, 0), }; -static struct samsung_cmu_info hevc_cmu_info __initdata = { +static const struct samsung_cmu_info hevc_cmu_info __initconst = { .mux_clks = hevc_mux_clks, .nr_mux_clks = ARRAY_SIZE(hevc_mux_clks), .div_clks = hevc_div_clks, @@ -4232,7 +4232,7 @@ CLK_OF_DECLARE(exynos5433_cmu_hevc, "samsung,exynos5433-cmu-hevc", #define ENABLE_IP_ISP2 0x0b08 #define ENABLE_IP_ISP3 0x0b0c -static unsigned long isp_clk_regs[] __initdata = { +static const unsigned long isp_clk_regs[] __initconst = { MUX_SEL_ISP, MUX_ENABLE_ISP, DIV_ISP, @@ -4250,7 +4250,7 @@ static unsigned long isp_clk_regs[] __initdata = { PNAME(mout_aclk_isp_dis_400_user_p) = { "oscclk", "aclk_isp_dis_400", }; PNAME(mout_aclk_isp_400_user_p) = { "oscclk", "aclk_isp_400", }; -static struct samsung_mux_clock isp_mux_clks[] __initdata = { +static const struct samsung_mux_clock isp_mux_clks[] __initconst = { /* MUX_SEL_ISP */ MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user", mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0), @@ -4258,7 +4258,7 @@ static struct samsung_mux_clock isp_mux_clks[] __initdata = { mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0), }; -static struct samsung_div_clock isp_div_clks[] __initdata = { +static const struct samsung_div_clock isp_div_clks[] __initconst = { /* DIV_ISP */ DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis", "mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3), @@ -4270,7 +4270,7 @@ static struct samsung_div_clock isp_div_clks[] __initdata = { "mout_aclk_isp_400_user", DIV_ISP, 0, 3), }; -static struct samsung_gate_clock isp_gate_clks[] __initdata = { +static const struct samsung_gate_clock isp_gate_clks[] __initconst = { /* ENABLE_ACLK_ISP0 */ GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user", ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0), @@ -4448,7 +4448,7 @@ static struct samsung_gate_clock isp_gate_clks[] __initdata = { 0, CLK_IGNORE_UNUSED, 0), }; -static struct samsung_cmu_info isp_cmu_info __initdata = { +static const struct samsung_cmu_info isp_cmu_info __initconst = { .mux_clks = isp_mux_clks, .nr_mux_clks = ARRAY_SIZE(isp_mux_clks), .div_clks = isp_div_clks, @@ -4504,7 +4504,7 @@ CLK_OF_DECLARE(exynos5433_cmu_isp, "samsung,exynos5433-cmu-isp", #define ENABLE_IP_CAM02 0X0b08 #define ENABLE_IP_CAM03 0X0b0C -static unsigned long cam0_clk_regs[] __initdata = { +static const unsigned long cam0_clk_regs[] __initconst = { MUX_SEL_CAM00, MUX_SEL_CAM01, MUX_SEL_CAM02, @@ -4588,14 +4588,14 @@ PNAME(mout_sclk_pixelasync_lite_c_init_a_p) = { "mout_aclk_cam0_552_user", "mout_aclk_cam0_400_user", }; -static struct samsung_fixed_rate_clock cam0_fixed_clks[] __initdata = { +static const struct samsung_fixed_rate_clock cam0_fixed_clks[] __initconst = { FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY, "phyclk_rxbyteclkhs0_s4_phy", NULL, 0, 100000000), FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY, "phyclk_rxbyteclkhs0_s2a_phy", NULL, 0, 100000000), }; -static struct samsung_mux_clock cam0_mux_clks[] __initdata = { +static const struct samsung_mux_clock cam0_mux_clks[] __initconst = { /* MUX_SEL_CAM00 */ MUX(CLK_MOUT_ACLK_CAM0_333_USER, "mout_aclk_cam0_333_user", mout_aclk_cam0_333_user_p, MUX_SEL_CAM00, 8, 1), @@ -4669,7 +4669,7 @@ static struct samsung_mux_clock cam0_mux_clks[] __initdata = { MUX_SEL_CAM04, 0, 1), }; -static struct samsung_div_clock cam0_div_clks[] __initdata = { +static const struct samsung_div_clock cam0_div_clks[] __initconst = { /* DIV_CAM00 */ DIV(CLK_DIV_PCLK_CAM0_50, "div_pclk_cam0_50", "div_aclk_cam0_200", DIV_CAM00, 8, 2), @@ -4716,7 +4716,7 @@ static struct samsung_div_clock cam0_div_clks[] __initdata = { "mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03, 0, 3), }; -static struct samsung_gate_clock cam0_gate_clks[] __initdata = { +static const struct samsung_gate_clock cam0_gate_clks[] __initconst = { /* ENABLE_ACLK_CAM00 */ GATE(CLK_ACLK_CSIS1, "aclk_csis1", "div_aclk_csis1", ENABLE_ACLK_CAM00, 6, 0, 0), @@ -4923,7 +4923,7 @@ static struct samsung_gate_clock cam0_gate_clks[] __initdata = { ENABLE_SCLK_CAM0, 0, 0, 0), }; -static struct samsung_cmu_info cam0_cmu_info __initdata = { +static const struct samsung_cmu_info cam0_cmu_info __initconst = { .mux_clks = cam0_mux_clks, .nr_mux_clks = ARRAY_SIZE(cam0_mux_clks), .div_clks = cam0_div_clks, @@ -4970,7 +4970,7 @@ CLK_OF_DECLARE(exynos5433_cmu_cam0, "samsung,exynos5433-cmu-cam0", #define ENABLE_IP_CAM11 0X0b04 #define ENABLE_IP_CAM12 0X0b08 -static unsigned long cam1_clk_regs[] __initdata = { +static const unsigned long cam1_clk_regs[] __initconst = { MUX_SEL_CAM10, MUX_SEL_CAM11, MUX_SEL_CAM12, @@ -5016,12 +5016,12 @@ PNAME(mout_aclk_lite_c_b_p) = { "mout_aclk_lite_c_a", PNAME(mout_aclk_lite_c_a_p) = { "mout_aclk_cam1_552_user", "mout_aclk_cam1_400_user", }; -static struct samsung_fixed_rate_clock cam1_fixed_clks[] __initdata = { +static const struct samsung_fixed_rate_clock cam1_fixed_clks[] __initconst = { FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b_phy", NULL, 0, 100000000), }; -static struct samsung_mux_clock cam1_mux_clks[] __initdata = { +static const struct samsung_mux_clock cam1_mux_clks[] __initconst = { /* MUX_SEL_CAM10 */ MUX(CLK_MOUT_SCLK_ISP_UART_USER, "mout_sclk_isp_uart_user", mout_sclk_isp_uart_user_p, MUX_SEL_CAM10, 20, 1), @@ -5057,7 +5057,7 @@ static struct samsung_mux_clock cam1_mux_clks[] __initdata = { MUX_SEL_CAM12, 0, 1), }; -static struct samsung_div_clock cam1_div_clks[] __initdata = { +static const struct samsung_div_clock cam1_div_clks[] __initconst = { /* DIV_CAM10 */ DIV(CLK_DIV_SCLK_ISP_MPWM, "div_sclk_isp_mpwm", "div_pclk_cam1_83", DIV_CAM10, 16, 2), @@ -5081,7 +5081,7 @@ static struct samsung_div_clock cam1_div_clks[] __initdata = { DIV_CAM11, 0, 3), }; -static struct samsung_gate_clock cam1_gate_clks[] __initdata = { +static const struct samsung_gate_clock cam1_gate_clks[] __initconst = { /* ENABLE_ACLK_CAM10 */ GATE(CLK_ACLK_ISP_GIC, "aclk_isp_gic", "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM10, 4, 0, 0), @@ -5296,7 +5296,7 @@ static struct samsung_gate_clock cam1_gate_clks[] __initdata = { ENABLE_SCLK_CAM1, 0, 0, 0), }; -static struct samsung_cmu_info cam1_cmu_info __initdata = { +static const struct samsung_cmu_info cam1_cmu_info __initconst = { .mux_clks = cam1_mux_clks, .nr_mux_clks = ARRAY_SIZE(cam1_mux_clks), .div_clks = cam1_div_clks, From 402b7cebf286d5c06c847c175ccc8405aabdae61 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 11 May 2016 14:02:11 +0200 Subject: [PATCH 23/41] clk: samsung: exynos5433: Move PLL rates data to init section The arrays with initialization data of PLLs can be moved to initconst section because they are referenced only from other initconst-level symbols. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos5433.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index f202a51ff99b..5993bd5ac6ba 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -693,7 +693,7 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = { * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL */ -static const struct samsung_pll_rate_table exynos5443_pll_rates[] = { +static const struct samsung_pll_rate_table exynos5443_pll_rates[] __initconst = { PLL_35XX_RATE(2500000000U, 625, 6, 0), PLL_35XX_RATE(2400000000U, 500, 5, 0), PLL_35XX_RATE(2300000000U, 575, 6, 0), @@ -744,7 +744,7 @@ static const struct samsung_pll_rate_table exynos5443_pll_rates[] = { }; /* AUD_PLL */ -static const struct samsung_pll_rate_table exynos5443_aud_pll_rates[] = { +static const struct samsung_pll_rate_table exynos5443_aud_pll_rates[] __initconst = { PLL_36XX_RATE(400000000U, 200, 3, 2, 0), PLL_36XX_RATE(393216000U, 197, 3, 2, -25690), PLL_36XX_RATE(384000000U, 128, 2, 2, 0), From ebd217e16522509c2dd371a0c51f623135cfe12c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 11 May 2016 14:02:12 +0200 Subject: [PATCH 24/41] clk: samsung: exynos5420: Move sleep init function and PLL data to init section The exynos5420_clk_sleep_init() function and arrays with initialization data of PLLs can be moved to init section because they are referenced only from other init-level symbols. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos5420.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 427725c8262c..95872b7c47c9 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -306,7 +306,7 @@ static struct syscore_ops exynos5420_clk_syscore_ops = { .resume = exynos5420_clk_resume, }; -static void exynos5420_clk_sleep_init(void) +static void __init exynos5420_clk_sleep_init(void) { exynos5x_save = samsung_clk_alloc_reg_dump(exynos5x_clk_regs, ARRAY_SIZE(exynos5x_clk_regs)); @@ -333,7 +333,7 @@ static void exynos5420_clk_sleep_init(void) return; } #else -static void exynos5420_clk_sleep_init(void) {} +static void __init exynos5420_clk_sleep_init(void) {} #endif /* list of all parent clocks */ @@ -1219,7 +1219,7 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), }; -static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] = { +static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = { PLL_35XX_RATE(2000000000, 250, 3, 0), PLL_35XX_RATE(1900000000, 475, 6, 0), PLL_35XX_RATE(1800000000, 225, 3, 0), From 1d3f15a89e04356aa37cef8f5763cd4e2c6d11af Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 11 May 2016 14:02:13 +0200 Subject: [PATCH 25/41] clk: samsung: exynos5250: Move sleep init function to init section The exynos5250_clk_sleep_init() function can be moved to init section because it is referenced only from other init-level calls. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos5250.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index a6ebc068689f..27a227d6620c 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -190,7 +190,7 @@ static struct syscore_ops exynos5250_clk_syscore_ops = { .resume = exynos5250_clk_resume, }; -static void exynos5250_clk_sleep_init(void) +static void __init exynos5250_clk_sleep_init(void) { exynos5250_save = samsung_clk_alloc_reg_dump(exynos5250_clk_regs, ARRAY_SIZE(exynos5250_clk_regs)); @@ -203,7 +203,7 @@ static void exynos5250_clk_sleep_init(void) register_syscore_ops(&exynos5250_clk_syscore_ops); } #else -static void exynos5250_clk_sleep_init(void) {} +static void __init exynos5250_clk_sleep_init(void) {} #endif /* list of all parent clock list */ From 4dbf01b8df00864787b6c7e3d3e0890d385b0ff5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 11 May 2016 14:02:14 +0200 Subject: [PATCH 26/41] clk: samsung: Fully constify mux parent names The PNAME macro defines array of strings for names of mux parents. Although the strings itself were const but pointers to them were not thus this data resided in initdata. Make this an array of const pointers to const strings and move to initconst section. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h index 61db98dd01a2..77d4657a95c5 100644 --- a/drivers/clk/samsung/clk.h +++ b/drivers/clk/samsung/clk.h @@ -261,7 +261,7 @@ struct samsung_gate_clock { #define GATE_DA(_id, dname, cname, pname, o, b, f, gf, a) \ __GATE(_id, dname, cname, pname, o, b, f, gf, a) -#define PNAME(x) static const char *x[] __initdata +#define PNAME(x) static const char * const x[] __initconst /** * struct samsung_clk_reg_dump: register dump of clock controller registers. From 334393366f3a68f5645b3ec9cfb7abad7e634e01 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 11 May 2016 14:12:16 +0200 Subject: [PATCH 27/41] clk: samsung: exynos3250: Move PLL rates data to init section The arrays with initialization data of PLLs can be moved to initconst section because they are referenced only from other initconst-level symbols. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos3250.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c index 057c3f0d0e35..b2513959252d 100644 --- a/drivers/clk/samsung/clk-exynos3250.c +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -669,7 +669,7 @@ static const struct samsung_gate_clock gate_clks[] __initconst = { }; /* APLL & MPLL & BPLL & UPLL */ -static const struct samsung_pll_rate_table exynos3250_pll_rates[] = { +static const struct samsung_pll_rate_table exynos3250_pll_rates[] __initconst = { PLL_35XX_RATE(1200000000, 400, 4, 1), PLL_35XX_RATE(1100000000, 275, 3, 1), PLL_35XX_RATE(1066000000, 533, 6, 1), @@ -691,7 +691,7 @@ static const struct samsung_pll_rate_table exynos3250_pll_rates[] = { }; /* EPLL */ -static const struct samsung_pll_rate_table exynos3250_epll_rates[] = { +static const struct samsung_pll_rate_table exynos3250_epll_rates[] __initconst = { PLL_36XX_RATE(800000000, 200, 3, 1, 0), PLL_36XX_RATE(288000000, 96, 2, 2, 0), PLL_36XX_RATE(192000000, 128, 2, 3, 0), From 1ebfb67de8f47c5f277f4a59e7f922a6806e54de Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 28 May 2016 11:54:14 +0200 Subject: [PATCH 28/41] clk: samsung: exynos5410: Add serial3, USB and PWM clocks Just like other Exynos5 family SoCs, this one has four UARTs. Add missing UART3 clocks to the Exynos5410 clock driver. Add clocks for USB and PWM. Signed-off-by: Krzysztof Kozlowski Acked-by: Stephen Boyd Reviewed-by: Javier Martinez Canillas Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos5410.c | 36 ++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c index 8e8c7cca8c62..8ad8d5ece7fa 100644 --- a/drivers/clk/samsung/clk-exynos5410.c +++ b/drivers/clk/samsung/clk-exynos5410.c @@ -33,9 +33,11 @@ #define SRC_CPERI1 0x4204 #define DIV_TOP0 0x10510 #define DIV_TOP1 0x10514 +#define DIV_FSYS0 0x10548 #define DIV_FSYS1 0x1054c #define DIV_FSYS2 0x10550 #define DIV_PERIC0 0x10558 +#define DIV_PERIC3 0x10564 #define SRC_TOP0 0x10210 #define SRC_TOP1 0x10214 #define SRC_TOP2 0x10218 @@ -44,6 +46,8 @@ #define SRC_MASK_FSYS 0x10340 #define SRC_MASK_PERIC0 0x10350 #define GATE_BUS_FSYS0 0x10740 +#define GATE_TOP_SCLK_FSYS 0x10840 +#define GATE_TOP_SCLK_PERIC 0x10850 #define GATE_IP_FSYS 0x10944 #define GATE_IP_PERIC 0x10950 #define GATE_IP_PERIS 0x10960 @@ -71,6 +75,7 @@ PNAME(mout_kfc_p) = { "mout_kpll", "sclk_mpll", }; PNAME(mpll_user_p) = { "fin_pll", "sclk_mpll", }; PNAME(bpll_user_p) = { "fin_pll", "sclk_bpll", }; PNAME(mpll_bpll_p) = { "sclk_mpll_muxed", "sclk_bpll_muxed", }; +PNAME(sclk_mpll_bpll_p) = { "sclk_mpll_bpll", "fin_pll", }; PNAME(group2_p) = { "fin_pll", "fin_pll", "none", "none", "none", "none", "sclk_mpll_bpll", @@ -96,10 +101,14 @@ static const struct samsung_mux_clock exynos5410_mux_clks[] __initconst = { MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 0, 4), MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 4, 4), MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 8, 4), + MUX(0, "mout_usbd300", sclk_mpll_bpll_p, SRC_FSYS, 28, 1), + MUX(0, "mout_usbd301", sclk_mpll_bpll_p, SRC_FSYS, 29, 1), MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 0, 4), MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 4, 4), MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 8, 4), + MUX(0, "mout_uart3", group2_p, SRC_PERIC0, 12, 4), + MUX(0, "mout_pwm", group2_p, SRC_PERIC0, 24, 4), MUX(0, "mout_aclk200", mpll_bpll_p, SRC_TOP0, 12, 1), MUX(0, "mout_aclk400", mpll_bpll_p, SRC_TOP0, 20, 1), @@ -121,6 +130,11 @@ static const struct samsung_div_clock exynos5410_div_clks[] __initconst = { DIV(0, "aclk66_pre", "sclk_mpll_muxed", DIV_TOP1, 24, 3), DIV(0, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3), + DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), + DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 20, 4), + DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), + DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 28, 4), + DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4), DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), @@ -137,6 +151,8 @@ static const struct samsung_div_clock exynos5410_div_clks[] __initconst = { DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4), DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4), + DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC3, 0, 4), + DIV(0, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3), DIV(0, "aclk400", "mout_aclk400", DIV_TOP0, 24, 3), }; @@ -155,9 +171,23 @@ static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = { GATE(CLK_MMC1, "sdmmc1", "aclk200", GATE_BUS_FSYS0, 13, 0, 0), GATE(CLK_MMC2, "sdmmc2", "aclk200", GATE_BUS_FSYS0, 14, 0, 0), + GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301", + GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0), + GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300", + GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0), + GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300", + GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), + GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301", + GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0), + + GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm", + GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), + GATE(CLK_UART0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0), GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0), GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0), + GATE(CLK_UART3, "uart3", "aclk66", GATE_IP_PERIC, 3, 0, 0), + GATE(CLK_PWM, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0), GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0), @@ -165,6 +195,12 @@ static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = { SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2", SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0), + GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3", + SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0), + + GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0), + GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0), + GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0), }; static const struct samsung_pll_clock exynos5410_plls[nr_plls] __initconst = { From 31d3953f823291c9a6b4650ae6706d9a6974bc80 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 28 May 2016 11:54:30 +0200 Subject: [PATCH 29/41] clk: samsung: exynos5410: Add I2C, HSI2C and RTC clocks Add clocks for I2C, USI (HSI2C) and RTC to the Exynos5410 clock driver. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Acked-by: Stephen Boyd Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos5410.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c index 8ad8d5ece7fa..6a924f80cfe4 100644 --- a/drivers/clk/samsung/clk-exynos5410.c +++ b/drivers/clk/samsung/clk-exynos5410.c @@ -159,6 +159,7 @@ static const struct samsung_div_clock exynos5410_div_clks[] __initconst = { static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = { GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0), + GATE(CLK_RTC, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0), GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0), @@ -187,6 +188,14 @@ static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = { GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0), GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0), GATE(CLK_UART3, "uart3", "aclk66", GATE_IP_PERIC, 3, 0, 0), + GATE(CLK_I2C0, "i2c0", "aclk66", GATE_IP_PERIC, 6, 0, 0), + GATE(CLK_I2C1, "i2c1", "aclk66", GATE_IP_PERIC, 7, 0, 0), + GATE(CLK_I2C2, "i2c2", "aclk66", GATE_IP_PERIC, 8, 0, 0), + GATE(CLK_I2C3, "i2c3", "aclk66", GATE_IP_PERIC, 9, 0, 0), + GATE(CLK_USI0, "usi0", "aclk66", GATE_IP_PERIC, 10, 0, 0), + GATE(CLK_USI1, "usi1", "aclk66", GATE_IP_PERIC, 11, 0, 0), + GATE(CLK_USI2, "usi2", "aclk66", GATE_IP_PERIC, 12, 0, 0), + GATE(CLK_USI3, "usi3", "aclk66", GATE_IP_PERIC, 13, 0, 0), GATE(CLK_PWM, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0), GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", From 41743a19b6ea786bc528c77868b353ab65ed5f3f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 31 May 2016 20:39:01 +0200 Subject: [PATCH 30/41] clk: samsung: exynos5410: Add TMU clock Add clock for TMU to the Exynos5410 clock driver. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos5410.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c index 6a924f80cfe4..2ddf954e0099 100644 --- a/drivers/clk/samsung/clk-exynos5410.c +++ b/drivers/clk/samsung/clk-exynos5410.c @@ -160,6 +160,7 @@ static const struct samsung_div_clock exynos5410_div_clks[] __initconst = { static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = { GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0), GATE(CLK_RTC, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0), + GATE(CLK_TMU, "tmu", "aclk66", GATE_IP_PERIS, 21, 0, 0), GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0), From 34cba900375ec1751a87d3655ad03b9a5b022362 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Tue, 24 May 2016 13:41:01 -0400 Subject: [PATCH 31/41] clk: samsung: exynos5420: Set ID for aclk333 gate clock The aclk333 clock needs to be ungated during the MFC power domain switch, so set the clock ID to allow the Exynos power domain logic to lookup this clock if is defined in the MFC PD device tree node. Signed-off-by: Javier Martinez Canillas Reviewed-by: Krzysztof Kozlowski Tested-by: Marek Szyprowski Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos5420.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 95872b7c47c9..bb196ca21a77 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -946,7 +946,7 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE_BUS_TOP, 13, 0, 0), GATE(0, "aclk166", "mout_user_aclk166", GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0), - GATE(0, "aclk333", "mout_user_aclk333", + GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333", GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0), GATE(0, "aclk400_isp", "mout_user_aclk400_isp", GATE_BUS_TOP, 16, 0, 0), From f4f4dd0c45676fa3fc7683046f3acc862a088fed Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 17 May 2016 09:26:14 +0200 Subject: [PATCH 32/41] clk: samsung: Suppress unbinding to prevent theoretical attacks Although unbinding a driver requires root privileges but it still might be used theoretically in certain attacks (by triggering NULL pointer exception or memory corruption if driver does not provide proper remove callbacks or core does not handle it). Samsung clock drivers are essential for system operation so their removal is not expected. More over, the Exynos3250 ISP clock driver does not implement remove() driver callback and it is not buildable as modules. Suppress the unbind interface for Exynos3250 ISP and S3C2410 DCLK clock drivers. Suggested-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos3250.c | 1 + drivers/clk/samsung/clk-s3c2410-dclk.c | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c index b2513959252d..1b81e283f605 100644 --- a/drivers/clk/samsung/clk-exynos3250.c +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -1087,6 +1087,7 @@ static const struct of_device_id exynos3250_cmu_isp_of_match[] __initconst = { static struct platform_driver exynos3250_cmu_isp_driver __initdata = { .driver = { .name = "exynos3250-cmu-isp", + .suppress_bind_attrs = true, .of_match_table = exynos3250_cmu_isp_of_match, }, }; diff --git a/drivers/clk/samsung/clk-s3c2410-dclk.c b/drivers/clk/samsung/clk-s3c2410-dclk.c index ec6fb14d951c..ae9a595c72d0 100644 --- a/drivers/clk/samsung/clk-s3c2410-dclk.c +++ b/drivers/clk/samsung/clk-s3c2410-dclk.c @@ -428,8 +428,9 @@ MODULE_DEVICE_TABLE(platform, s3c24xx_dclk_driver_ids); static struct platform_driver s3c24xx_dclk_driver = { .driver = { - .name = "s3c24xx-dclk", - .pm = &s3c24xx_dclk_pm_ops, + .name = "s3c24xx-dclk", + .pm = &s3c24xx_dclk_pm_ops, + .suppress_bind_attrs = true, }, .probe = s3c24xx_dclk_probe, .remove = s3c24xx_dclk_remove, From 0c0cd59a4c31aa0dccb49450fca5e36d1759f1ca Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Tue, 24 May 2016 15:19:15 +0200 Subject: [PATCH 33/41] clk: samsung: exynos5433: prepare for adding CPU clocks Open-code samsung_cmu_register_one() calls for CMU_APOLLO and CMU_ATLAS setup code as a preparation for adding CPU clocks support for Exynos5433. There should be no functional change resulting from this patch. Cc: Kukjin Kim CC: Krzysztof Kozlowski Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos5433.c | 85 ++++++++++++++++++---------- drivers/clk/samsung/clk.c | 12 ++-- drivers/clk/samsung/clk.h | 4 ++ 3 files changed, 65 insertions(+), 36 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 5993bd5ac6ba..70e1df6fc825 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -11,6 +11,7 @@ #include #include +#include #include @@ -3594,23 +3595,35 @@ static const struct samsung_gate_clock apollo_gate_clks[] __initconst = { CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), }; -static const struct samsung_cmu_info apollo_cmu_info __initconst = { - .pll_clks = apollo_pll_clks, - .nr_pll_clks = ARRAY_SIZE(apollo_pll_clks), - .mux_clks = apollo_mux_clks, - .nr_mux_clks = ARRAY_SIZE(apollo_mux_clks), - .div_clks = apollo_div_clks, - .nr_div_clks = ARRAY_SIZE(apollo_div_clks), - .gate_clks = apollo_gate_clks, - .nr_gate_clks = ARRAY_SIZE(apollo_gate_clks), - .nr_clk_ids = APOLLO_NR_CLK, - .clk_regs = apollo_clk_regs, - .nr_clk_regs = ARRAY_SIZE(apollo_clk_regs), -}; - static void __init exynos5433_cmu_apollo_init(struct device_node *np) { - samsung_cmu_register_one(np, &apollo_cmu_info); + void __iomem *reg_base; + struct samsung_clk_provider *ctx; + + reg_base = of_iomap(np, 0); + if (!reg_base) { + panic("%s: failed to map registers\n", __func__); + return; + } + + ctx = samsung_clk_init(np, reg_base, APOLLO_NR_CLK); + if (!ctx) { + panic("%s: unable to allocate ctx\n", __func__); + return; + } + + samsung_clk_register_pll(ctx, apollo_pll_clks, + ARRAY_SIZE(apollo_pll_clks), reg_base); + samsung_clk_register_mux(ctx, apollo_mux_clks, + ARRAY_SIZE(apollo_mux_clks)); + samsung_clk_register_div(ctx, apollo_div_clks, + ARRAY_SIZE(apollo_div_clks)); + samsung_clk_register_gate(ctx, apollo_gate_clks, + ARRAY_SIZE(apollo_gate_clks)); + samsung_clk_sleep_init(reg_base, apollo_clk_regs, + ARRAY_SIZE(apollo_clk_regs)); + + samsung_clk_of_add_provider(np, ctx); } CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo", exynos5433_cmu_apollo_init); @@ -3806,23 +3819,35 @@ static const struct samsung_gate_clock atlas_gate_clks[] __initconst = { CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), }; -static const struct samsung_cmu_info atlas_cmu_info __initconst = { - .pll_clks = atlas_pll_clks, - .nr_pll_clks = ARRAY_SIZE(atlas_pll_clks), - .mux_clks = atlas_mux_clks, - .nr_mux_clks = ARRAY_SIZE(atlas_mux_clks), - .div_clks = atlas_div_clks, - .nr_div_clks = ARRAY_SIZE(atlas_div_clks), - .gate_clks = atlas_gate_clks, - .nr_gate_clks = ARRAY_SIZE(atlas_gate_clks), - .nr_clk_ids = ATLAS_NR_CLK, - .clk_regs = atlas_clk_regs, - .nr_clk_regs = ARRAY_SIZE(atlas_clk_regs), -}; - static void __init exynos5433_cmu_atlas_init(struct device_node *np) { - samsung_cmu_register_one(np, &atlas_cmu_info); + void __iomem *reg_base; + struct samsung_clk_provider *ctx; + + reg_base = of_iomap(np, 0); + if (!reg_base) { + panic("%s: failed to map registers\n", __func__); + return; + } + + ctx = samsung_clk_init(np, reg_base, ATLAS_NR_CLK); + if (!ctx) { + panic("%s: unable to allocate ctx\n", __func__); + return; + } + + samsung_clk_register_pll(ctx, atlas_pll_clks, + ARRAY_SIZE(atlas_pll_clks), reg_base); + samsung_clk_register_mux(ctx, atlas_mux_clks, + ARRAY_SIZE(atlas_mux_clks)); + samsung_clk_register_div(ctx, atlas_div_clks, + ARRAY_SIZE(atlas_div_clks)); + samsung_clk_register_gate(ctx, atlas_gate_clks, + ARRAY_SIZE(atlas_gate_clks)); + samsung_clk_sleep_init(reg_base, atlas_clk_regs, + ARRAY_SIZE(atlas_clk_regs)); + + samsung_clk_of_add_provider(np, ctx); } CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas", exynos5433_cmu_atlas_init); diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c index e4d14589cc4a..b7d87d6db9dc 100644 --- a/drivers/clk/samsung/clk.c +++ b/drivers/clk/samsung/clk.c @@ -346,9 +346,9 @@ static struct syscore_ops samsung_clk_syscore_ops = { .resume = samsung_clk_resume, }; -static void samsung_clk_sleep_init(void __iomem *reg_base, - const unsigned long *rdump, - unsigned long nr_rdump) +void samsung_clk_sleep_init(void __iomem *reg_base, + const unsigned long *rdump, + unsigned long nr_rdump) { struct samsung_clock_reg_cache *reg_cache; @@ -370,9 +370,9 @@ static void samsung_clk_sleep_init(void __iomem *reg_base, } #else -static void samsung_clk_sleep_init(void __iomem *reg_base, - const unsigned long *rdump, - unsigned long nr_rdump) {} +void samsung_clk_sleep_init(void __iomem *reg_base, + const unsigned long *rdump, + unsigned long nr_rdump) {} #endif /* diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h index 77d4657a95c5..da3bdebabf1e 100644 --- a/drivers/clk/samsung/clk.h +++ b/drivers/clk/samsung/clk.h @@ -399,6 +399,10 @@ extern struct samsung_clk_provider __init *samsung_cmu_register_one( extern unsigned long _get_rate(const char *clk_name); +extern void samsung_clk_sleep_init(void __iomem *reg_base, + const unsigned long *rdump, + unsigned long nr_rdump); + extern void samsung_clk_save(void __iomem *base, struct samsung_clk_reg_dump *rd, unsigned int num_regs); From 53f69967dca340d79c8dda0734b8912241cb4d31 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Tue, 24 May 2016 15:19:16 +0200 Subject: [PATCH 34/41] clk: samsung: cpu: prepare for adding Exynos5433 CPU clocks Exynos5433 uses different register layout for CPU clock registers than earlier SoCs so add new code for handling this layout. Also add new CLK_CPU_HAS_E5433_REGS_LAYOUT flag to request using it. There should be no functional change resulting from this patch. Cc: Kukjin Kim CC: Krzysztof Kozlowski Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-cpu.c | 131 +++++++++++++++++++++++++++++++++- drivers/clk/samsung/clk-cpu.h | 4 +- 2 files changed, 133 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c index 813003d6ce09..8bf7e805fd34 100644 --- a/drivers/clk/samsung/clk-cpu.c +++ b/drivers/clk/samsung/clk-cpu.c @@ -45,6 +45,13 @@ #define E4210_DIV_STAT_CPU0 0x400 #define E4210_DIV_STAT_CPU1 0x404 +#define E5433_MUX_SEL2 0x008 +#define E5433_MUX_STAT2 0x208 +#define E5433_DIV_CPU0 0x400 +#define E5433_DIV_CPU1 0x404 +#define E5433_DIV_STAT_CPU0 0x500 +#define E5433_DIV_STAT_CPU1 0x504 + #define E4210_DIV0_RATIO0_MASK 0x7 #define E4210_DIV1_HPM_MASK (0x7 << 4) #define E4210_DIV1_COPY_MASK (0x7 << 0) @@ -252,6 +259,102 @@ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata, return 0; } +/* + * Helper function to set the 'safe' dividers for the CPU clock. The parameters + * div and mask contain the divider value and the register bit mask of the + * dividers to be programmed. + */ +static void exynos5433_set_safe_div(void __iomem *base, unsigned long div, + unsigned long mask) +{ + unsigned long div0; + + div0 = readl(base + E5433_DIV_CPU0); + div0 = (div0 & ~mask) | (div & mask); + writel(div0, base + E5433_DIV_CPU0); + wait_until_divider_stable(base + E5433_DIV_STAT_CPU0, mask); +} + +/* handler for pre-rate change notification from parent clock */ +static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, + struct exynos_cpuclk *cpuclk, void __iomem *base) +{ + const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg; + unsigned long alt_prate = clk_get_rate(cpuclk->alt_parent); + unsigned long alt_div = 0, alt_div_mask = DIV_MASK; + unsigned long div0, div1 = 0, mux_reg; + unsigned long flags; + + /* find out the divider values to use for clock data */ + while ((cfg_data->prate * 1000) != ndata->new_rate) { + if (cfg_data->prate == 0) + return -EINVAL; + cfg_data++; + } + + spin_lock_irqsave(cpuclk->lock, flags); + + /* + * For the selected PLL clock frequency, get the pre-defined divider + * values. + */ + div0 = cfg_data->div0; + div1 = cfg_data->div1; + + /* + * If the old parent clock speed is less than the clock speed of + * the alternate parent, then it should be ensured that at no point + * the armclk speed is more than the old_prate until the dividers are + * set. Also workaround the issue of the dividers being set to lower + * values before the parent clock speed is set to new lower speed + * (this can result in too high speed of armclk output clocks). + */ + if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) { + unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate); + + alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1; + WARN_ON(alt_div >= MAX_DIV); + + exynos5433_set_safe_div(base, alt_div, alt_div_mask); + div0 |= alt_div; + } + + /* select the alternate parent */ + mux_reg = readl(base + E5433_MUX_SEL2); + writel(mux_reg | 1, base + E5433_MUX_SEL2); + wait_until_mux_stable(base + E5433_MUX_STAT2, 0, 2); + + /* alternate parent is active now. set the dividers */ + writel(div0, base + E5433_DIV_CPU0); + wait_until_divider_stable(base + E5433_DIV_STAT_CPU0, DIV_MASK_ALL); + + writel(div1, base + E5433_DIV_CPU1); + wait_until_divider_stable(base + E5433_DIV_STAT_CPU1, DIV_MASK_ALL); + + spin_unlock_irqrestore(cpuclk->lock, flags); + return 0; +} + +/* handler for post-rate change notification from parent clock */ +static int exynos5433_cpuclk_post_rate_change(struct clk_notifier_data *ndata, + struct exynos_cpuclk *cpuclk, void __iomem *base) +{ + unsigned long div = 0, div_mask = DIV_MASK; + unsigned long mux_reg; + unsigned long flags; + + spin_lock_irqsave(cpuclk->lock, flags); + + /* select apll as the alternate parent */ + mux_reg = readl(base + E5433_MUX_SEL2); + writel(mux_reg & ~1, base + E5433_MUX_SEL2); + wait_until_mux_stable(base + E5433_MUX_STAT2, 0, 1); + + exynos5433_set_safe_div(base, div, div_mask); + spin_unlock_irqrestore(cpuclk->lock, flags); + return 0; +} + /* * This notifier function is called for the pre-rate and post-rate change * notifications of the parent clock of cpuclk. @@ -275,6 +378,29 @@ static int exynos_cpuclk_notifier_cb(struct notifier_block *nb, return notifier_from_errno(err); } +/* + * This notifier function is called for the pre-rate and post-rate change + * notifications of the parent clock of cpuclk. + */ +static int exynos5433_cpuclk_notifier_cb(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct clk_notifier_data *ndata = data; + struct exynos_cpuclk *cpuclk; + void __iomem *base; + int err = 0; + + cpuclk = container_of(nb, struct exynos_cpuclk, clk_nb); + base = cpuclk->ctrl_base; + + if (event == PRE_RATE_CHANGE) + err = exynos5433_cpuclk_pre_rate_change(ndata, cpuclk, base); + else if (event == POST_RATE_CHANGE) + err = exynos5433_cpuclk_post_rate_change(ndata, cpuclk, base); + + return notifier_from_errno(err); +} + /* helper function to register a CPU clock */ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, unsigned int lookup_id, const char *name, const char *parent, @@ -301,7 +427,10 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, cpuclk->ctrl_base = ctx->reg_base + offset; cpuclk->lock = &ctx->lock; cpuclk->flags = flags; - cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb; + if (flags & CLK_CPU_HAS_E5433_REGS_LAYOUT) + cpuclk->clk_nb.notifier_call = exynos5433_cpuclk_notifier_cb; + else + cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb; cpuclk->alt_parent = __clk_lookup(alt_parent); if (!cpuclk->alt_parent) { diff --git a/drivers/clk/samsung/clk-cpu.h b/drivers/clk/samsung/clk-cpu.h index 37874d3c3165..d4b6b517fe1b 100644 --- a/drivers/clk/samsung/clk-cpu.h +++ b/drivers/clk/samsung/clk-cpu.h @@ -57,10 +57,12 @@ struct exynos_cpuclk { struct notifier_block clk_nb; unsigned long flags; -/* The CPU clock registers has DIV1 configuration register */ +/* The CPU clock registers have DIV1 configuration register */ #define CLK_CPU_HAS_DIV1 (1 << 0) /* When ALT parent is active, debug clocks need safe divider values */ #define CLK_CPU_NEEDS_DEBUG_ALT_DIV (1 << 1) +/* The CPU clock registers have Exynos5433-compatible layout */ +#define CLK_CPU_HAS_E5433_REGS_LAYOUT (1 << 2) }; extern int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, From d7d7115d498a97a6deb782a20c689a452e77dc28 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Tue, 24 May 2016 15:19:17 +0200 Subject: [PATCH 35/41] clk: samsung: exynos5433: add CPU clocks configuration data and instantiate CPU clocks Add the CPU clocks configuration data and instantiate the CPU clocks type for Exynos5433. Cc: Kukjin Kim CC: Krzysztof Kozlowski Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos5433.c | 72 ++++++++++++++++++++++++---- 1 file changed, 64 insertions(+), 8 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 70e1df6fc825..1d14d1cc1296 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -16,6 +16,7 @@ #include #include "clk.h" +#include "clk-cpu.h" #include "clk-pll.h" /* @@ -3509,7 +3510,8 @@ static const struct samsung_pll_clock apollo_pll_clks[] __initconst = { static const struct samsung_mux_clock apollo_mux_clks[] __initconst = { /* MUX_SEL_APOLLO0 */ MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p, - MUX_SEL_APOLLO0, 0, 1, CLK_SET_RATE_PARENT, 0), + MUX_SEL_APOLLO0, 0, 1, CLK_SET_RATE_PARENT | + CLK_RECALC_NEW_RATES, 0), /* MUX_SEL_APOLLO1 */ MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user", @@ -3590,9 +3592,27 @@ static const struct samsung_gate_clock apollo_gate_clks[] __initconst = { ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0), GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo", ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0), - GATE(CLK_SCLK_APOLLO, "sclk_apollo", "div_apollo2", - ENABLE_SCLK_APOLLO, 0, - CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), +}; + +#define E5433_APOLLO_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \ + (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \ + ((pclk) << 12) | ((aclk) << 8)) + +#define E5433_APOLLO_DIV1(hpm, copy) \ + (((hpm) << 4) | ((copy) << 0)) + +static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst = { + { 1300000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, + { 1200000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, + { 1100000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, + { 1000000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, + { 900000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, + { 800000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, + { 700000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, + { 600000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), }, + { 500000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), }, + { 400000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), }, + { 0 }, }; static void __init exynos5433_cmu_apollo_init(struct device_node *np) @@ -3620,6 +3640,12 @@ static void __init exynos5433_cmu_apollo_init(struct device_node *np) ARRAY_SIZE(apollo_div_clks)); samsung_clk_register_gate(ctx, apollo_gate_clks, ARRAY_SIZE(apollo_gate_clks)); + + exynos_register_cpu_clock(ctx, CLK_SCLK_APOLLO, "apolloclk", + mout_apollo_p[0], mout_apollo_p[1], 0x200, + exynos5433_apolloclk_d, ARRAY_SIZE(exynos5433_apolloclk_d), + CLK_CPU_HAS_E5433_REGS_LAYOUT); + samsung_clk_sleep_init(reg_base, apollo_clk_regs, ARRAY_SIZE(apollo_clk_regs)); @@ -3707,7 +3733,8 @@ static const struct samsung_pll_clock atlas_pll_clks[] __initconst = { static const struct samsung_mux_clock atlas_mux_clks[] __initconst = { /* MUX_SEL_ATLAS0 */ MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p, - MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT, 0), + MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT | + CLK_RECALC_NEW_RATES, 0), /* MUX_SEL_ATLAS1 */ MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user", @@ -3814,9 +3841,32 @@ static const struct samsung_gate_clock atlas_gate_clks[] __initconst = { ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0), GATE(CLK_ATCLK, "atclk", "div_atclk_atlas", ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0), - GATE(CLK_SCLK_ATLAS, "sclk_atlas", "div_atlas2", - ENABLE_SCLK_ATLAS, 0, - CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), +}; + +#define E5433_ATLAS_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \ + (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \ + ((pclk) << 12) | ((aclk) << 8)) + +#define E5433_ATLAS_DIV1(hpm, copy) \ + (((hpm) << 4) | ((copy) << 0)) + +static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst = { + { 1900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), }, + { 1800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), }, + { 1700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), }, + { 1600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), }, + { 1500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, + { 1400000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, + { 1300000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, + { 1200000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, + { 1100000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, + { 1000000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, + { 900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, + { 800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, + { 700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, + { 600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, + { 500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, + { 0 }, }; static void __init exynos5433_cmu_atlas_init(struct device_node *np) @@ -3844,6 +3894,12 @@ static void __init exynos5433_cmu_atlas_init(struct device_node *np) ARRAY_SIZE(atlas_div_clks)); samsung_clk_register_gate(ctx, atlas_gate_clks, ARRAY_SIZE(atlas_gate_clks)); + + exynos_register_cpu_clock(ctx, CLK_SCLK_ATLAS, "atlasclk", + mout_atlas_p[0], mout_atlas_p[1], 0x200, + exynos5433_atlasclk_d, ARRAY_SIZE(exynos5433_atlasclk_d), + CLK_CPU_HAS_E5433_REGS_LAYOUT); + samsung_clk_sleep_init(reg_base, atlas_clk_regs, ARRAY_SIZE(atlas_clk_regs)); From 05af240fe823a6163a9081c106167f2e41d521ee Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 1 Jun 2016 11:45:50 +0200 Subject: [PATCH 36/41] clk: samsung: exynos5410: Add WDT, ACLK266 and SSS clocks Add clock hierarchy for Security SubSystem clock and watchdog. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos5410.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c index 2ddf954e0099..54ec486a5e45 100644 --- a/drivers/clk/samsung/clk-exynos5410.c +++ b/drivers/clk/samsung/clk-exynos5410.c @@ -31,6 +31,7 @@ #define SRC_CPU 0x200 #define DIV_CPU0 0x500 #define SRC_CPERI1 0x4204 +#define GATE_IP_G2D 0x8800 #define DIV_TOP0 0x10510 #define DIV_TOP1 0x10514 #define DIV_FSYS0 0x10548 @@ -154,11 +155,14 @@ static const struct samsung_div_clock exynos5410_div_clks[] __initconst = { DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC3, 0, 4), DIV(0, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3), + DIV(0, "aclk266", "mpll_user_p", DIV_TOP0, 16, 3), DIV(0, "aclk400", "mout_aclk400", DIV_TOP0, 24, 3), }; static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = { + GATE(CLK_SSS, "sss", "aclk266", GATE_IP_G2D, 2, 0, 0), GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0), + GATE(CLK_WDT, "wdt", "aclk66", GATE_IP_PERIS, 19, 0, 0), GATE(CLK_RTC, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0), GATE(CLK_TMU, "tmu", "aclk66", GATE_IP_PERIS, 21, 0, 0), From 4de103397bed108212ac8e382d9285eb6b2700bd Mon Sep 17 00:00:00 2001 From: Matthew Leach Date: Wed, 8 Jun 2016 19:30:56 +0100 Subject: [PATCH 37/41] clk: samsung: fixup endian in pll clk Fix the clk endian access code to deal with kernels built for big endian operation. Signed-off-by: Matthew Leach Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-pll.c | 122 +++++++++++++++++----------------- 1 file changed, 61 insertions(+), 61 deletions(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index b7dd396100d8..48139bd510f1 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -79,7 +79,7 @@ static unsigned long samsung_pll2126_recalc_rate(struct clk_hw *hw, u32 pll_con, mdiv, pdiv, sdiv; u64 fvco = parent_rate; - pll_con = __raw_readl(pll->con_reg); + pll_con = readl_relaxed(pll->con_reg); mdiv = (pll_con >> PLL2126_MDIV_SHIFT) & PLL2126_MDIV_MASK; pdiv = (pll_con >> PLL2126_PDIV_SHIFT) & PLL2126_PDIV_MASK; sdiv = (pll_con >> PLL2126_SDIV_SHIFT) & PLL2126_SDIV_MASK; @@ -112,7 +112,7 @@ static unsigned long samsung_pll3000_recalc_rate(struct clk_hw *hw, u32 pll_con, mdiv, pdiv, sdiv; u64 fvco = parent_rate; - pll_con = __raw_readl(pll->con_reg); + pll_con = readl_relaxed(pll->con_reg); mdiv = (pll_con >> PLL3000_MDIV_SHIFT) & PLL3000_MDIV_MASK; pdiv = (pll_con >> PLL3000_PDIV_SHIFT) & PLL3000_PDIV_MASK; sdiv = (pll_con >> PLL3000_SDIV_SHIFT) & PLL3000_SDIV_MASK; @@ -149,7 +149,7 @@ static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw, u32 mdiv, pdiv, sdiv, pll_con; u64 fvco = parent_rate; - pll_con = __raw_readl(pll->con_reg); + pll_con = readl_relaxed(pll->con_reg); mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK; pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK; sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK; @@ -186,19 +186,19 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, return -EINVAL; } - tmp = __raw_readl(pll->con_reg); + tmp = readl_relaxed(pll->con_reg); if (!(samsung_pll35xx_mp_change(rate, tmp))) { /* If only s change, change just s value only*/ tmp &= ~(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT); tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT; - __raw_writel(tmp, pll->con_reg); + writel_relaxed(tmp, pll->con_reg); return 0; } /* Set PLL lock time. */ - __raw_writel(rate->pdiv * PLL35XX_LOCK_FACTOR, + writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR, pll->lock_reg); /* Change PLL PMS values */ @@ -208,12 +208,12 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, tmp |= (rate->mdiv << PLL35XX_MDIV_SHIFT) | (rate->pdiv << PLL35XX_PDIV_SHIFT) | (rate->sdiv << PLL35XX_SDIV_SHIFT); - __raw_writel(tmp, pll->con_reg); + writel_relaxed(tmp, pll->con_reg); /* wait_lock_time */ do { cpu_relax(); - tmp = __raw_readl(pll->con_reg); + tmp = readl_relaxed(pll->con_reg); } while (!(tmp & (PLL35XX_LOCK_STAT_MASK << PLL35XX_LOCK_STAT_SHIFT))); return 0; @@ -253,8 +253,8 @@ static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw, s16 kdiv; u64 fvco = parent_rate; - pll_con0 = __raw_readl(pll->con_reg); - pll_con1 = __raw_readl(pll->con_reg + 4); + pll_con0 = readl_relaxed(pll->con_reg); + pll_con1 = readl_relaxed(pll->con_reg + 4); mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK; pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK; sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK; @@ -294,20 +294,20 @@ static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate, return -EINVAL; } - pll_con0 = __raw_readl(pll->con_reg); - pll_con1 = __raw_readl(pll->con_reg + 4); + pll_con0 = readl_relaxed(pll->con_reg); + pll_con1 = readl_relaxed(pll->con_reg + 4); if (!(samsung_pll36xx_mpk_change(rate, pll_con0, pll_con1))) { /* If only s change, change just s value only*/ pll_con0 &= ~(PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT); pll_con0 |= (rate->sdiv << PLL36XX_SDIV_SHIFT); - __raw_writel(pll_con0, pll->con_reg); + writel_relaxed(pll_con0, pll->con_reg); return 0; } /* Set PLL lock time. */ - __raw_writel(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg); + writel_relaxed(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg); /* Change PLL PMS values */ pll_con0 &= ~((PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT) | @@ -316,16 +316,16 @@ static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate, pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) | (rate->pdiv << PLL36XX_PDIV_SHIFT) | (rate->sdiv << PLL36XX_SDIV_SHIFT); - __raw_writel(pll_con0, pll->con_reg); + writel_relaxed(pll_con0, pll->con_reg); pll_con1 &= ~(PLL36XX_KDIV_MASK << PLL36XX_KDIV_SHIFT); pll_con1 |= rate->kdiv << PLL36XX_KDIV_SHIFT; - __raw_writel(pll_con1, pll->con_reg + 4); + writel_relaxed(pll_con1, pll->con_reg + 4); /* wait_lock_time */ do { cpu_relax(); - tmp = __raw_readl(pll->con_reg); + tmp = readl_relaxed(pll->con_reg); } while (!(tmp & (1 << PLL36XX_LOCK_STAT_SHIFT))); return 0; @@ -366,7 +366,7 @@ static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw, u32 mdiv, pdiv, sdiv, pll_con; u64 fvco = parent_rate; - pll_con = __raw_readl(pll->con_reg); + pll_con = readl_relaxed(pll->con_reg); mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK; pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK; sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK; @@ -409,14 +409,14 @@ static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate, return -EINVAL; } - con0 = __raw_readl(pll->con_reg); - con1 = __raw_readl(pll->con_reg + 0x4); + con0 = readl_relaxed(pll->con_reg); + con1 = readl_relaxed(pll->con_reg + 0x4); if (!(samsung_pll45xx_mp_change(con0, con1, rate))) { /* If only s change, change just s value only*/ con0 &= ~(PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT); con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT; - __raw_writel(con0, pll->con_reg); + writel_relaxed(con0, pll->con_reg); return 0; } @@ -430,29 +430,29 @@ static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate, (rate->sdiv << PLL45XX_SDIV_SHIFT); /* Set PLL AFC value. */ - con1 = __raw_readl(pll->con_reg + 0x4); + con1 = readl_relaxed(pll->con_reg + 0x4); con1 &= ~(PLL45XX_AFC_MASK << PLL45XX_AFC_SHIFT); con1 |= (rate->afc << PLL45XX_AFC_SHIFT); /* Set PLL lock time. */ switch (pll->type) { case pll_4502: - __raw_writel(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg); + writel_relaxed(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg); break; case pll_4508: - __raw_writel(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg); + writel_relaxed(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg); break; default: break; } /* Set new configuration. */ - __raw_writel(con1, pll->con_reg + 0x4); - __raw_writel(con0, pll->con_reg); + writel_relaxed(con1, pll->con_reg + 0x4); + writel_relaxed(con0, pll->con_reg); /* Wait for locking. */ start = ktime_get(); - while (!(__raw_readl(pll->con_reg) & PLL45XX_LOCKED)) { + while (!(readl_relaxed(pll->con_reg) & PLL45XX_LOCKED)) { ktime_t delta = ktime_sub(ktime_get(), start); if (ktime_to_ms(delta) > PLL_TIMEOUT_MS) { @@ -513,8 +513,8 @@ static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw, u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift; u64 fvco = parent_rate; - pll_con0 = __raw_readl(pll->con_reg); - pll_con1 = __raw_readl(pll->con_reg + 4); + pll_con0 = readl_relaxed(pll->con_reg); + pll_con1 = readl_relaxed(pll->con_reg + 4); mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ? PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK); pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK; @@ -560,14 +560,14 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate, return -EINVAL; } - con0 = __raw_readl(pll->con_reg); - con1 = __raw_readl(pll->con_reg + 0x4); + con0 = readl_relaxed(pll->con_reg); + con1 = readl_relaxed(pll->con_reg + 0x4); if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) { /* If only s change, change just s value only*/ con0 &= ~(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT); con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT; - __raw_writel(con0, pll->con_reg); + writel_relaxed(con0, pll->con_reg); return 0; } @@ -596,7 +596,7 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate, (rate->sdiv << PLL46XX_SDIV_SHIFT); /* Set PLL K, MFR and MRR values. */ - con1 = __raw_readl(pll->con_reg + 0x4); + con1 = readl_relaxed(pll->con_reg + 0x4); con1 &= ~((PLL46XX_KDIV_MASK << PLL46XX_KDIV_SHIFT) | (PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT) | (PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT)); @@ -605,13 +605,13 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate, (rate->mrr << PLL46XX_MRR_SHIFT); /* Write configuration to PLL */ - __raw_writel(lock, pll->lock_reg); - __raw_writel(con0, pll->con_reg); - __raw_writel(con1, pll->con_reg + 0x4); + writel_relaxed(lock, pll->lock_reg); + writel_relaxed(con0, pll->con_reg); + writel_relaxed(con1, pll->con_reg + 0x4); /* Wait for locking. */ start = ktime_get(); - while (!(__raw_readl(pll->con_reg) & PLL46XX_LOCKED)) { + while (!(readl_relaxed(pll->con_reg) & PLL46XX_LOCKED)) { ktime_t delta = ktime_sub(ktime_get(), start); if (ktime_to_ms(delta) > PLL_TIMEOUT_MS) { @@ -656,7 +656,7 @@ static unsigned long samsung_pll6552_recalc_rate(struct clk_hw *hw, u32 mdiv, pdiv, sdiv, pll_con; u64 fvco = parent_rate; - pll_con = __raw_readl(pll->con_reg); + pll_con = readl_relaxed(pll->con_reg); if (pll->type == pll_6552_s3c2416) { mdiv = (pll_con >> PLL6552_MDIV_SHIFT_2416) & PLL6552_MDIV_MASK; pdiv = (pll_con >> PLL6552_PDIV_SHIFT_2416) & PLL6552_PDIV_MASK; @@ -696,8 +696,8 @@ static unsigned long samsung_pll6553_recalc_rate(struct clk_hw *hw, u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1; u64 fvco = parent_rate; - pll_con0 = __raw_readl(pll->con_reg); - pll_con1 = __raw_readl(pll->con_reg + 0x4); + pll_con0 = readl_relaxed(pll->con_reg); + pll_con1 = readl_relaxed(pll->con_reg + 0x4); mdiv = (pll_con0 >> PLL6553_MDIV_SHIFT) & PLL6553_MDIV_MASK; pdiv = (pll_con0 >> PLL6553_PDIV_SHIFT) & PLL6553_PDIV_MASK; sdiv = (pll_con0 >> PLL6553_SDIV_SHIFT) & PLL6553_SDIV_MASK; @@ -734,7 +734,7 @@ static unsigned long samsung_s3c2410_pll_recalc_rate(struct clk_hw *hw, u32 pll_con, mdiv, pdiv, sdiv; u64 fvco = parent_rate; - pll_con = __raw_readl(pll->con_reg); + pll_con = readl_relaxed(pll->con_reg); mdiv = (pll_con >> PLLS3C2410_MDIV_SHIFT) & PLLS3C2410_MDIV_MASK; pdiv = (pll_con >> PLLS3C2410_PDIV_SHIFT) & PLLS3C2410_PDIV_MASK; sdiv = (pll_con >> PLLS3C2410_SDIV_SHIFT) & PLLS3C2410_SDIV_MASK; @@ -752,7 +752,7 @@ static unsigned long samsung_s3c2440_mpll_recalc_rate(struct clk_hw *hw, u32 pll_con, mdiv, pdiv, sdiv; u64 fvco = parent_rate; - pll_con = __raw_readl(pll->con_reg); + pll_con = readl_relaxed(pll->con_reg); mdiv = (pll_con >> PLLS3C2410_MDIV_SHIFT) & PLLS3C2410_MDIV_MASK; pdiv = (pll_con >> PLLS3C2410_PDIV_SHIFT) & PLLS3C2410_PDIV_MASK; sdiv = (pll_con >> PLLS3C2410_SDIV_SHIFT) & PLLS3C2410_SDIV_MASK; @@ -778,7 +778,7 @@ static int samsung_s3c2410_pll_set_rate(struct clk_hw *hw, unsigned long drate, return -EINVAL; } - tmp = __raw_readl(pll->con_reg); + tmp = readl_relaxed(pll->con_reg); /* Change PLL PMS values */ tmp &= ~((PLLS3C2410_MDIV_MASK << PLLS3C2410_MDIV_SHIFT) | @@ -787,7 +787,7 @@ static int samsung_s3c2410_pll_set_rate(struct clk_hw *hw, unsigned long drate, tmp |= (rate->mdiv << PLLS3C2410_MDIV_SHIFT) | (rate->pdiv << PLLS3C2410_PDIV_SHIFT) | (rate->sdiv << PLLS3C2410_SDIV_SHIFT); - __raw_writel(tmp, pll->con_reg); + writel_relaxed(tmp, pll->con_reg); /* Time to settle according to the manual */ udelay(300); @@ -798,7 +798,7 @@ static int samsung_s3c2410_pll_set_rate(struct clk_hw *hw, unsigned long drate, static int samsung_s3c2410_pll_enable(struct clk_hw *hw, int bit, bool enable) { struct samsung_clk_pll *pll = to_clk_pll(hw); - u32 pll_en = __raw_readl(pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET); + u32 pll_en = readl_relaxed(pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET); u32 pll_en_orig = pll_en; if (enable) @@ -806,7 +806,7 @@ static int samsung_s3c2410_pll_enable(struct clk_hw *hw, int bit, bool enable) else pll_en |= BIT(bit); - __raw_writel(pll_en, pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET); + writel_relaxed(pll_en, pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET); /* if we started the UPLL, then allow to settle */ if (enable && (pll_en_orig & BIT(bit))) @@ -905,7 +905,7 @@ static unsigned long samsung_pll2550x_recalc_rate(struct clk_hw *hw, u32 r, p, m, s, pll_stat; u64 fvco = parent_rate; - pll_stat = __raw_readl(pll->reg_base + pll->offset * 3); + pll_stat = readl_relaxed(pll->reg_base + pll->offset * 3); r = (pll_stat >> PLL2550X_R_SHIFT) & PLL2550X_R_MASK; if (!r) return 0; @@ -983,7 +983,7 @@ static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw, u32 mdiv, pdiv, sdiv, pll_con; u64 fvco = parent_rate; - pll_con = __raw_readl(pll->con_reg); + pll_con = readl_relaxed(pll->con_reg); mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK; pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK; sdiv = (pll_con >> PLL2550XX_S_SHIFT) & PLL2550XX_S_MASK; @@ -1019,19 +1019,19 @@ static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate, return -EINVAL; } - tmp = __raw_readl(pll->con_reg); + tmp = readl_relaxed(pll->con_reg); if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) { /* If only s change, change just s value only*/ tmp &= ~(PLL2550XX_S_MASK << PLL2550XX_S_SHIFT); tmp |= rate->sdiv << PLL2550XX_S_SHIFT; - __raw_writel(tmp, pll->con_reg); + writel_relaxed(tmp, pll->con_reg); return 0; } /* Set PLL lock time. */ - __raw_writel(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg); + writel_relaxed(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg); /* Change PLL PMS values */ tmp &= ~((PLL2550XX_M_MASK << PLL2550XX_M_SHIFT) | @@ -1040,12 +1040,12 @@ static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate, tmp |= (rate->mdiv << PLL2550XX_M_SHIFT) | (rate->pdiv << PLL2550XX_P_SHIFT) | (rate->sdiv << PLL2550XX_S_SHIFT); - __raw_writel(tmp, pll->con_reg); + writel_relaxed(tmp, pll->con_reg); /* wait_lock_time */ do { cpu_relax(); - tmp = __raw_readl(pll->con_reg); + tmp = readl_relaxed(pll->con_reg); } while (!(tmp & (PLL2550XX_LOCK_STAT_MASK << PLL2550XX_LOCK_STAT_SHIFT))); @@ -1089,8 +1089,8 @@ static unsigned long samsung_pll2650xx_recalc_rate(struct clk_hw *hw, s16 kdiv; u64 fvco = parent_rate; - pll_con0 = __raw_readl(pll->con_reg); - pll_con2 = __raw_readl(pll->con_reg + 8); + pll_con0 = readl_relaxed(pll->con_reg); + pll_con2 = readl_relaxed(pll->con_reg + 8); mdiv = (pll_con0 >> PLL2650XX_MDIV_SHIFT) & PLL2650XX_MDIV_MASK; pdiv = (pll_con0 >> PLL2650XX_PDIV_SHIFT) & PLL2650XX_PDIV_MASK; sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK; @@ -1117,8 +1117,8 @@ static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate, return -EINVAL; } - pll_con0 = __raw_readl(pll->con_reg); - pll_con2 = __raw_readl(pll->con_reg + 8); + pll_con0 = readl_relaxed(pll->con_reg); + pll_con2 = readl_relaxed(pll->con_reg + 8); /* Change PLL PMS values */ pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT | @@ -1135,13 +1135,13 @@ static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate, << PLL2650XX_KDIV_SHIFT; /* Set PLL lock time. */ - __raw_writel(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg); + writel_relaxed(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg); - __raw_writel(pll_con0, pll->con_reg); - __raw_writel(pll_con2, pll->con_reg + 8); + writel_relaxed(pll_con0, pll->con_reg); + writel_relaxed(pll_con2, pll->con_reg + 8); do { - tmp = __raw_readl(pll->con_reg); + tmp = readl_relaxed(pll->con_reg); } while (!(tmp & (0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT))); return 0; From 21a5560b5dfc79ec03335280e68e6c2d3f1528b1 Mon Sep 17 00:00:00 2001 From: Matthew Leach Date: Wed, 8 Jun 2016 19:30:58 +0100 Subject: [PATCH 38/41] clk: samsung: exynos4: fixup reg access on be Use the byte-order aware big endian accessors, allowing for kernels running under big-endian. Signed-off-by: Matthew Leach Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos4.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 13eaf4cb0dbc..faab9b31baf5 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -1375,12 +1375,12 @@ static void __init exynos4x12_core_down_clock(void) if (num_possible_cpus() == 4) tmp |= PWR_CTRL1_USE_CORE3_WFE | PWR_CTRL1_USE_CORE2_WFE | PWR_CTRL1_USE_CORE3_WFI | PWR_CTRL1_USE_CORE2_WFI; - __raw_writel(tmp, reg_base + PWR_CTRL1); + writel_relaxed(tmp, reg_base + PWR_CTRL1); /* * Disable the clock up feature in case it was enabled by bootloader. */ - __raw_writel(0x0, reg_base + E4X12_PWR_CTRL2); + writel_relaxed(0x0, reg_base + E4X12_PWR_CTRL2); } #define E4210_CPU_DIV0(apll, pclk_dbg, atb, periph, corem1, corem0) \ From 7d058bc4e6bc377cbf3cbbf0c210b84c566a5825 Mon Sep 17 00:00:00 2001 From: Beomho Seo Date: Fri, 10 Jun 2016 13:56:30 +0900 Subject: [PATCH 39/41] clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag for AUD UART This patch adds CLK_IGNORE_UNUSED flag for sclk_aud_uart gate clock for uart3 operation. Signed-off-by: Beomho Seo Signed-off-by: Chanwoo Choi [s.nawrocki@samsung.com: edited the patch's summary] Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos5433.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 1d14d1cc1296..be3658dc9049 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -2978,7 +2978,7 @@ static const struct samsung_gate_clock aud_gate_clks[] __initconst = { GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus", ENABLE_SCLK_AUD1, 4, 0, 0), GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart", - ENABLE_SCLK_AUD1, 3, 0, 0), + ENABLE_SCLK_AUD1, 3, CLK_IGNORE_UNUSED, 0), GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm", ENABLE_SCLK_AUD1, 2, 0, 0), GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk", From 358c9b952db6e85c861d97cb6ea8474671a025d0 Mon Sep 17 00:00:00 2001 From: Jonghwa Lee Date: Fri, 10 Jun 2016 13:56:31 +0900 Subject: [PATCH 40/41] clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flags to avoid hang during S2R Some clocks are required to be unmasked during suspend to RAM. Otherwise the PMU will stuck and the power down sequence will never be completed. Signed-off-by: Jonghwa Lee Signed-off-by: Chanwoo Choi [s.nawrocki@samsung.com: edited the patch's summary] Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos5433.c | 34 ++++++++++++++++++---------- 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index be3658dc9049..5d26c0f9fe0a 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -670,11 +670,14 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = { GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1", ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2", - ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT, 0), + ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT | + CLK_IGNORE_UNUSED, 0), GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1", - ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT, 0), + ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT | + CLK_IGNORE_UNUSED, 0), GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0", - ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT, 0), + ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT | + CLK_IGNORE_UNUSED, 0), GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b", ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b", @@ -835,7 +838,7 @@ static const struct samsung_div_clock cpif_div_clks[] __initconst = { static const struct samsung_gate_clock cpif_gate_clks[] __initconst = { /* ENABLE_SCLK_CPIF */ GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll", - ENABLE_SCLK_CPIF, 9, 0, 0), + ENABLE_SCLK_CPIF, 9, CLK_IGNORE_UNUSED, 0), GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy", ENABLE_SCLK_CPIF, 4, 0, 0), }; @@ -1442,11 +1445,13 @@ static const struct samsung_gate_clock mif_gate_clks[] __initconst = { /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */ GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133", - ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0, 0, 0), + ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0, + CLK_IGNORE_UNUSED, 0), /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */ GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133", - ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0, 0, 0), + ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0, + CLK_IGNORE_UNUSED, 0), /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */ GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133", @@ -1676,11 +1681,14 @@ static const struct samsung_gate_clock peric_gate_clks[] __initconst = { GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric", - ENABLE_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), + ENABLE_SCLK_PERIC, 2, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric", - ENABLE_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0), + ENABLE_SCLK_PERIC, 1, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric", - ENABLE_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), + ENABLE_SCLK_PERIC, 0, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), }; static const struct samsung_cmu_info peric_cmu_info __initconst = { @@ -2964,7 +2972,7 @@ static const struct samsung_gate_clock aud_gate_clks[] __initconst = { /* ENABLE_SCLK_AUD0 */ GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0, - 2, 0, 0), + 2, CLK_IGNORE_UNUSED, 0), GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud", ENABLE_SCLK_AUD0, 1, 0, 0), GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0, @@ -3358,9 +3366,11 @@ static const struct samsung_gate_clock gscl_gate_clks[] __initconst = { GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user", ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0), GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333", - "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5, 0, 0), + "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5, + CLK_IGNORE_UNUSED, 0), GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333", - "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4, 0, 0), + "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4, + CLK_IGNORE_UNUSED, 0), GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 3, 0, 0), GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user", From 0e4504470667d355b53ca3c9802fdd2120c9f946 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Fri, 10 Jun 2016 13:56:32 +0900 Subject: [PATCH 41/41] clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag to PCIE device This patch adds the CLK_IGNORE_UNUSED flag for PCI Express's clocks which need to remain enabled. The 'pcie' gate clock definition is also added. Signed-off-by: Jaehoon Chung Signed-off-by: Chanwoo Choi [s.nawrocki@samsung.com: edited the patch's summary] Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos5433.c | 11 ++++++----- include/dt-bindings/clock/exynos5433.h | 3 ++- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 5d26c0f9fe0a..4204eb828d86 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -641,7 +641,7 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = { /* ENABLE_SCLK_TOP_FSYS */ GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100", - ENABLE_SCLK_TOP_FSYS, 7, 0, 0), + ENABLE_SCLK_TOP_FSYS, 7, CLK_IGNORE_UNUSED, 0), GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b", ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b", @@ -2148,7 +2148,7 @@ static const struct samsung_gate_clock fsys_gate_clks[] __initconst = { GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0), GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user", - ENABLE_ACLK_FSYS1, 24, 0, 0), + ENABLE_ACLK_FSYS1, 24, CLK_IGNORE_UNUSED, 0), GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1", "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 22, CLK_IGNORE_UNUSED, 0), @@ -2195,13 +2195,13 @@ static const struct samsung_gate_clock fsys_gate_clks[] __initconst = { /* ENABLE_PCLK_FSYS */ GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user", - ENABLE_PCLK_FSYS, 17, 0, 0), + ENABLE_PCLK_FSYS, 17, CLK_IGNORE_UNUSED, 0), GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0), GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user", - ENABLE_PCLK_FSYS, 14, 0, 0), + ENABLE_PCLK_FSYS, 14, CLK_IGNORE_UNUSED, 0), GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user", - ENABLE_PCLK_FSYS, 13, 0, 0), + ENABLE_PCLK_FSYS, 13, CLK_IGNORE_UNUSED, 0), GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0), GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user", @@ -2280,6 +2280,7 @@ static const struct samsung_gate_clock fsys_gate_clks[] __initconst = { ENABLE_SCLK_FSYS, 0, 0, 0), /* ENABLE_IP_FSYS0 */ + GATE(CLK_PCIE, "pcie", "sclk_pcie_100", ENABLE_IP_FSYS0, 17, 0, 0), GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0), GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0), }; diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h index 8e024fea26e7..4fa6bb2136e3 100644 --- a/include/dt-bindings/clock/exynos5433.h +++ b/include/dt-bindings/clock/exynos5433.h @@ -622,8 +622,9 @@ #define CLK_SCLK_UFSUNIPRO 112 #define CLK_SCLK_USBHOST30 113 #define CLK_SCLK_USBDRD30 114 +#define CLK_PCIE 115 -#define FSYS_NR_CLK 115 +#define FSYS_NR_CLK 116 /* CMU_G2D */ #define CLK_MUX_ACLK_G2D_266_USER 1