From fd5ef505453f995b4ce6ef6e43ddc15967a94a96 Mon Sep 17 00:00:00 2001 From: Ivan Uvarov Date: Wed, 7 Apr 2021 14:14:24 +0300 Subject: [PATCH 01/29] ARM: dts: sun8i: r40: add /omit-if-no-ref/ to pinmux nodes for UARTs 0&3 This patch adds the /omit-if-no-ref/ keyword to the pio nodes for UART0 and UART3 pins of the R40 SoC, which would reduce the fdt size on boards which do not use these UARTs. Signed-off-by: Ivan Uvarov 1 file changed, 3 insertions(+) Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210407111428.3755684-2-i.uvarov@cognitivepilot.com --- arch/arm/boot/dts/sun8i-r40.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index d5ad3b9efd12..0b257a07792f 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -631,16 +631,19 @@ spi1_cs1_pi_pin: spi1-cs1-pi-pin { function = "spi1"; }; + /omit-if-no-ref/ uart0_pb_pins: uart0-pb-pins { pins = "PB22", "PB23"; function = "uart0"; }; + /omit-if-no-ref/ uart3_pg_pins: uart3-pg-pins { pins = "PG6", "PG7"; function = "uart3"; }; + /omit-if-no-ref/ uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins { pins = "PG8", "PG9"; function = "uart3"; From 492dd7309aed4d2313a6f9d9a26f88707f51161b Mon Sep 17 00:00:00 2001 From: Ivan Uvarov Date: Wed, 7 Apr 2021 14:14:25 +0300 Subject: [PATCH 02/29] ARM: dts: sun8i: r40: add pinmux settings for MMC3 and UARTs 2, 4, 5&7 The Forlinx OKA40i-C devboard makes use of UARTs 0,2,3,4,5 and 7 of the R40 SoC, of which UART 0 is connected to an RS232 converter, UART 5 routed to an RS485 converter, and the rest broken out directly via labeled headers. The board also contains a micro-SD slot connected to SDC3. This patch adds settings to R40's pinmux node for MMC3 and those UARTs that were not already mapped, which would allow us to make use of all available UARTs and the micro-SD slot on this board in a further patch. Reviewed-by: Andre Przywara Signed-off-by: Ivan Uvarov 1 file changed, 41 insertions(+) Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210407111428.3755684-3-i.uvarov@cognitivepilot.com --- arch/arm/boot/dts/sun8i-r40.dtsi | 41 ++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 0b257a07792f..03e054c0bac4 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -357,6 +357,8 @@ mmc3: mmc@1c12000 { clock-names = "ahb", "mmc"; resets = <&ccu RST_BUS_MMC3>; reset-names = "ahb"; + pinctrl-0 = <&mmc3_pins>; + pinctrl-names = "default"; interrupts = ; status = "disabled"; #address-cells = <1>; @@ -601,6 +603,15 @@ mmc2_pins: mmc2-pins { bias-pull-up; }; + /omit-if-no-ref/ + mmc3_pins: mmc3-pins { + pins = "PI4", "PI5", "PI6", + "PI7", "PI8", "PI9"; + function = "mmc3"; + drive-strength = <30>; + bias-pull-up; + }; + /omit-if-no-ref/ spi0_pc_pins: spi0-pc-pins { pins = "PC0", "PC1", "PC2"; @@ -637,6 +648,18 @@ uart0_pb_pins: uart0-pb-pins { function = "uart0"; }; + /omit-if-no-ref/ + uart2_pi_pins: uart2-pi-pins { + pins = "PI18", "PI19"; + function = "uart2"; + }; + + /omit-if-no-ref/ + uart2_rts_cts_pi_pins: uart2-rts-cts-pi-pins{ + pins = "PI16", "PI17"; + function = "uart2"; + }; + /omit-if-no-ref/ uart3_pg_pins: uart3-pg-pins { pins = "PG6", "PG7"; @@ -648,6 +671,24 @@ uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins { pins = "PG8", "PG9"; function = "uart3"; }; + + /omit-if-no-ref/ + uart4_pg_pins: uart4-pg-pins { + pins = "PG10", "PG11"; + function = "uart4"; + }; + + /omit-if-no-ref/ + uart5_ph_pins: uart5-ph-pins { + pins = "PH6", "PH7"; + function = "uart5"; + }; + + /omit-if-no-ref/ + uart7_pi_pins: uart7-pi-pins { + pins = "PI20", "PI21"; + function = "uart7"; + }; }; wdt: watchdog@1c20c90 { From 157da630c7ff848439f721257f26655b5ae2d856 Mon Sep 17 00:00:00 2001 From: Ivan Uvarov Date: Wed, 7 Apr 2021 14:14:26 +0300 Subject: [PATCH 03/29] dt-bindings: add compatible vendor prefix for Forlinx Baoding Forlinx Embedded Technology Co., Ltd. is the manufacturer of the Allwinner R40/A40i-powered FETA40i-C SoM and the OKA40i-C dev/carrier board based on it. This patch adds the DT vendor prefix for Forlinx in preparation for a further patch, which includes a devicetree for the OKA40i-C board. Signed-off-by: Ivan Uvarov 1 file changed, 2 insertions(+) Acked-by: Rob Herring Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210407111428.3755684-4-i.uvarov@cognitivepilot.com --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index b868cefc7c55..44e59ee2ae90 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -409,6 +409,8 @@ patternProperties: description: Firefly "^focaltech,.*": description: FocalTech Systems Co.,Ltd + "^forlinx,.*": + description: Baoding Forlinx Embedded Technology Co., Ltd. "^frida,.*": description: Shenzhen Frida LCD Co., Ltd. "^friendlyarm,.*": From ed85561fe39c994e9ba1a97614b5269158a98ca9 Mon Sep 17 00:00:00 2001 From: Ivan Uvarov Date: Wed, 7 Apr 2021 14:14:27 +0300 Subject: [PATCH 04/29] dt-bindings: arm: add compatible for Forlinx OKA40i-C and FETA40i-C The FETA40i-C is a SoM by Forlinx based on the Allwinner R40/A40i SoC. The OKA40i-C is a carrier/development board by the same company based on this SoM. This patch adds compatible strings for these two devices in preparation for the next patch containing a devicetree for them. Signed-off-by: Ivan Uvarov 1 file changed, 6 insertions(+) Acked-by: Rob Herring Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210407111428.3755684-5-i.uvarov@cognitivepilot.com --- Documentation/devicetree/bindings/arm/sunxi.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index ac750025a2eb..ec8108483b49 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -224,6 +224,12 @@ properties: - const: empire-electronix,m712 - const: allwinner,sun5i-a13 + - description: Forlinx OKA40i-C Development board + items: + - const: forlinx,oka40i-c + - const: forlinx,feta40i-c + - const: allwinner,sun8i-r40 + - description: FriendlyARM NanoPi A64 items: - const: friendlyarm,nanopi-a64 From d0aac8cbbd0ce601ef38317a3f69028b6910bace Mon Sep 17 00:00:00 2001 From: Ivan Uvarov Date: Wed, 7 Apr 2021 14:14:28 +0300 Subject: [PATCH 05/29] ARM: dts: sun8i: r40: add devicetree for Forlinx FETA40i-C & OKA40i-C MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The FETA40i-C is a SoM by Forlinx based on the Allwinner R40/A40i. SoM specifications: - SoC: R40 or A40i - PMIC: AXP221S - RAM: 1GiB/2GiB DDR3 (dual-rank) - eMMC: 8GB, - Mates with carrier board via four 80-pin connectors (AXK6F80337YG). OKA40i-C is a carrier board by the same manufacturer for this SoM, whose main purpose is as a development board with a wide variety of peripherals: - Power: DC5V barrel or USB OTG or 4.2V Lipo battery - Video out: HDMI, TV out, LVDS - WiFi+Bluetooth: RL-UM02WBS-8723BU-V1.2 (802.11 b/g/n, BT V2.1/3.0/4.0) - Ethernet: 10/100Mbps - Storage: µSD, fullsize SD, eMMC (on SoM), SATA - USB: 3 x USB2.0 Host (2 via hub, 1 native), 1 x USB2.0 OTG (micro-B) - UART: RS232, RS485, 4 3.3v uarts (of which 2 have RTS/CTS) - Other I/O: SPI x2, TWI, SDIO header, GPIO header, JTAG header - Mini PCIe slot with sim holder for WLAN modem - Smart card holder - RTC (RX8010SJ) - Two user LEDs - Three user buttons (via KeyADC). This patch adds a devicetree for the aforementioned SoM and devboard. In order to reflect the modularity of this devboard and simplify adding support for future hardware based on the same SoM, the devicetree is split: Everything pertaining to the SoM itself is described in a separate .dtsi file, which is included by the devboard's .dts. Reviewed-by: Andre Przywara Signed-off-by: Ivan Uvarov 3 files changed, 310 insertions(+) Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210407111428.3755684-6-i.uvarov@cognitivepilot.com --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun8i-r40-feta40i.dtsi | 106 ++++++++++++ arch/arm/boot/dts/sun8i-r40-oka40i-c.dts | 203 +++++++++++++++++++++++ 3 files changed, 310 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-r40-feta40i.dtsi create mode 100644 arch/arm/boot/dts/sun8i-r40-oka40i-c.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f8f09c5066e7..1754b562e0b9 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1234,6 +1234,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-r16-nintendo-super-nes-classic.dtb \ sun8i-r16-parrot.dtb \ sun8i-r40-bananapi-m2-ultra.dtb \ + sun8i-r40-oka40i-c.dtb \ sun8i-s3-elimo-initium.dtb \ sun8i-s3-lichee-zero-plus.dtb \ sun8i-s3-pinecube.dtb \ diff --git a/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi b/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi new file mode 100644 index 000000000000..265e0fa57a32 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// Copyright (C) 2021 Ivan Uvarov +// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is: +// Copyright (C) 2017 Chen-Yu Tsai +// Copyright (C) 2017 Icenowy Zheng + +#include "sun8i-r40.dtsi" + +&i2c0 { + status = "okay"; + + axp22x: pmic@34 { + compatible = "x-powers,axp221"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp22x.dtsi" + +&mmc2 { + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_aldo2>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&pio { + pinctrl-names = "default"; + pinctrl-0 = <&clk_out_a_pin>; + vcc-pa-supply = <®_dcdc1>; + vcc-pc-supply = <®_aldo2>; + vcc-pd-supply = <®_dcdc1>; + vcc-pf-supply = <®_dldo4>; + vcc-pg-supply = <®_dldo1>; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pa"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-io"; +}; + +®_dldo4 { + regulator-always-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vdd2v5-sata"; +}; + +®_eldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd1v2-sata"; +}; + +®_eldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc-pe"; +}; diff --git a/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts b/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts new file mode 100644 index 000000000000..0bd1336206b8 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// Copyright (C) 2021 Ivan Uvarov +// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is: +// Copyright (C) 2017 Chen-Yu Tsai +// Copyright (C) 2017 Icenowy Zheng + +/dts-v1/; +#include "sun8i-r40-feta40i.dtsi" + +#include +#include + +/ { + model = "Forlinx OKA40i-C"; + compatible = "forlinx,oka40i-c", "forlinx,feta40i-c", "allwinner,sun8i-r40"; + + aliases { + ethernet0 = &gmac; + serial0 = &uart0; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; /* RS485 */ + serial7 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-5 { /* this is how the leds are labeled on the board */ + gpios = <&pio 7 26 GPIO_ACTIVE_LOW>; /* PH26 */ + color = ; + function = LED_FUNCTION_STATUS; + }; + + led-6 { + gpios = <&pio 8 15 GPIO_ACTIVE_LOW>; /* PI15 */ + color = ; + function = LED_FUNCTION_STATUS; + }; + }; + + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; // PB10 WIFI_EN + clocks = <&ccu CLK_OUTA>; + clock-names = "ext_clock"; + }; +}; + +&ahci { + ahci-supply = <®_dldo4>; + phy-supply = <®_eldo2>; + status = "okay"; +}; + +&de { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + phy-supply = <®_dcdc1>; + status = "okay"; +}; + +&gmac_mdio { + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 8 11 GPIO_ACTIVE_LOW>; // PI11 + status = "okay"; +}; + +&mmc3 { + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 8 10 GPIO_ACTIVE_LOW>; // PI10 + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +®_dc1sw { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-lcd"; +}; + +®_dldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +&tcon_tv0 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pi_pins>, <&uart2_rts_cts_pi_pins>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pg_pins>; + status = "okay"; +}; + +&uart5 { /* RS485 */ + pinctrl-names = "default"; + pinctrl-0 = <&uart5_ph_pins>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pi_pins>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_vcc5v0>; + usb2_vbus-supply = <®_vcc5v0>; + status = "okay"; +}; From 5bd15031337f544891185361899db40961d9044e Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 21 Mar 2021 23:47:03 -0500 Subject: [PATCH 06/29] dt-bindings: timer: Simplify conditional expressions The sun4i timer IP block has a variable number of interrupts based on the compatible. Use enums to combine the two sections for the existing 3-interrupt variants, and to simplify adding new compatible strings. Acked-by: Maxime Ripard Signed-off-by: Samuel Holland Reviewed-by: Rob Herring Acked-by: Daniel Lezcano Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210322044707.19479-2-samuel@sholland.org --- .../timer/allwinner,sun4i-a10-timer.yaml | 25 ++++++------------- 1 file changed, 7 insertions(+), 18 deletions(-) diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml index 1c7cf32e7ac2..3462598e609d 100644 --- a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml +++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml @@ -34,8 +34,8 @@ allOf: - if: properties: compatible: - items: - const: allwinner,sun4i-a10-timer + enum: + - allwinner,sun4i-a10-timer then: properties: @@ -46,8 +46,8 @@ allOf: - if: properties: compatible: - items: - const: allwinner,sun8i-a23-timer + enum: + - allwinner,sun8i-a23-timer then: properties: @@ -58,20 +58,9 @@ allOf: - if: properties: compatible: - items: - const: allwinner,sun8i-v3s-timer - - then: - properties: - interrupts: - minItems: 3 - maxItems: 3 - - - if: - properties: - compatible: - items: - const: allwinner,suniv-f1c100s-timer + enum: + - allwinner,sun8i-v3s-timer + - allwinner,suniv-f1c100s-timer then: properties: From bffdc0f3c26c7d9b5006326e0f7b7871d4eaaf13 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 21 Mar 2021 23:47:04 -0500 Subject: [PATCH 07/29] dt-bindings: timer: Add compatibles for sun50i timers The sun50i SoCs contain timer blocks which are useful as broadcast clockevent sources. They each have 2 interrupts, matching the A23 variant, so add the new compatible strings with the A23 compatible as a fallback. Acked-by: Maxime Ripard Signed-off-by: Samuel Holland Reviewed-by: Rob Herring Acked-by: Daniel Lezcano Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210322044707.19479-3-samuel@sholland.org --- .../timer/allwinner,sun4i-a10-timer.yaml | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml index 3462598e609d..53fd24bdc34e 100644 --- a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml +++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml @@ -12,11 +12,18 @@ maintainers: properties: compatible: - enum: - - allwinner,sun4i-a10-timer - - allwinner,sun8i-a23-timer - - allwinner,sun8i-v3s-timer - - allwinner,suniv-f1c100s-timer + oneOf: + - enum: + - allwinner,sun4i-a10-timer + - allwinner,sun8i-a23-timer + - allwinner,sun8i-v3s-timer + - allwinner,suniv-f1c100s-timer + - items: + - enum: + - allwinner,sun50i-a64-timer + - allwinner,sun50i-h6-timer + - allwinner,sun50i-h616-timer + - const: allwinner,sun8i-a23-timer reg: maxItems: 1 From af97dd5559c59050f452997a4328b1a794f6fd6a Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 21 Mar 2021 23:47:05 -0500 Subject: [PATCH 08/29] arm64: dts: allwinner: a64: Sort watchdog node Nodes should be sorted by unit address. Move the watchdog node to the correct place, so it will be next to the timer node when that is added. Signed-off-by: Samuel Holland Acked-by: Daniel Lezcano Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210322044707.19479-4-samuel@sholland.org --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 5b30e6c1fa05..96525e3b5f9b 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -799,6 +799,14 @@ uart4_rts_cts_pins: uart4-rts-cts-pins { }; }; + wdt0: watchdog@1c20ca0 { + compatible = "allwinner,sun50i-a64-wdt", + "allwinner,sun6i-a31-wdt"; + reg = <0x01c20ca0 0x20>; + interrupts = ; + clocks = <&osc24M>; + }; + spdif: spdif@1c21000 { #sound-dai-cells = <0>; compatible = "allwinner,sun50i-a64-spdif", @@ -1325,13 +1333,5 @@ r_rsb: rsb@1f03400 { #address-cells = <1>; #size-cells = <0>; }; - - wdt0: watchdog@1c20ca0 { - compatible = "allwinner,sun50i-a64-wdt", - "allwinner,sun6i-a31-wdt"; - reg = <0x01c20ca0 0x20>; - interrupts = ; - clocks = <&osc24M>; - }; }; }; From 12bcaacaff49fc18612a7df21b76235ca8eb5c7f Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 21 Mar 2021 23:47:06 -0500 Subject: [PATCH 09/29] arm64: dts: allwinner: Add sun4i MMIO timer nodes For a CPU to enter an idle state, some timer must be available to trigger an IRQ and wake it back up. The local ARM architectural timer is not sufficient, because that timer stops when the CPU is powered down. The ARM architectural timer from some other CPU can be used, but doing so prevents that other CPU from entering an idle state. For all CPUs to power down at the same time, Linux needs a timer which is not tied to any CPU. Hook up the "sun4i" timer so it can be used for this purpose. It runs at 24 MHz, which balances resolution and power consumption. Signed-off-by: Samuel Holland Acked-by: Daniel Lezcano Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210322044707.19479-5-samuel@sholland.org --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 9 +++++++++ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 9 +++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 96525e3b5f9b..08b37d0af529 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -799,6 +799,15 @@ uart4_rts_cts_pins: uart4-rts-cts-pins { }; }; + timer@1c20c00 { + compatible = "allwinner,sun50i-a64-timer", + "allwinner,sun8i-a23-timer"; + reg = <0x01c20c00 0xa0>; + interrupts = , + ; + clocks = <&osc24M>; + }; + wdt0: watchdog@1c20ca0 { compatible = "allwinner,sun50i-a64-wdt", "allwinner,sun6i-a31-wdt"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 50815867ce7b..30d396e8c762 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -271,6 +271,15 @@ cpu_speed_grade: cpu-speed-grade@1c { }; }; + timer@3009000 { + compatible = "allwinner,sun50i-h6-timer", + "allwinner,sun8i-a23-timer"; + reg = <0x03009000 0xa0>; + interrupts = , + ; + clocks = <&osc24M>; + }; + watchdog: watchdog@30090a0 { compatible = "allwinner,sun50i-h6-wdt", "allwinner,sun6i-a31-wdt"; From d88834bfefdeb8f2456934b662613dbe3bae58df Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Thu, 29 Apr 2021 22:58:53 -0500 Subject: [PATCH 10/29] ASoC: dt-bindings: sun8i-codec: Increase #sound-dai-cells Increase sound-dai-cells to 1 to allow using the DAIs in the codec corresponding to AIF2 and AIF3. The generic ASoC OF code supports a #sound-dai-cells value of 0 or 1 with no impact to the driver, so this is a backward-compatible change. Signed-off-by: Samuel Holland Acked-by: Rob Herring Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210430035859.3487-2-samuel@sholland.org --- .../bindings/sound/allwinner,sun8i-a33-codec.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml index 67405e6d8168..19f111f40225 100644 --- a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml +++ b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml @@ -12,7 +12,11 @@ maintainers: properties: "#sound-dai-cells": - const: 0 + minimum: 0 + maximum: 1 + description: + A value of 0 is deprecated. When used, it only allows access to + the ADC/DAC and AIF1 (the CPU DAI), not the other two AIFs/DAIs. compatible: oneOf: @@ -50,7 +54,7 @@ additionalProperties: false examples: - | audio-codec@1c22e00 { - #sound-dai-cells = <0>; + #sound-dai-cells = <1>; compatible = "allwinner,sun8i-a33-codec"; reg = <0x01c22e00 0x400>; interrupts = <0 29 4>; From a691acabac36ea9966c41780d60ee2689c1cead7 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Thu, 29 Apr 2021 22:58:54 -0500 Subject: [PATCH 11/29] ARM: dts: sun8i-a33: Allow using multiple codec DAIs Increase #sound-dai-cells on the digital codec to allow using the other DAIs provided by the codec for AIF2 and AIF3. Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210430035859.3487-3-samuel@sholland.org --- arch/arm/boot/dts/sun8i-a33.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 7344c37107c6..2beddbb3c518 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -198,7 +198,7 @@ simple-audio-card,cpu { }; link_codec: simple-audio-card,codec { - sound-dai = <&codec>; + sound-dai = <&codec 0>; }; }; @@ -238,7 +238,7 @@ dai: dai@1c22c00 { }; codec: codec@1c22e00 { - #sound-dai-cells = <0>; + #sound-dai-cells = <1>; compatible = "allwinner,sun8i-a33-codec"; reg = <0x01c22e00 0x400>; interrupts = ; From e0cd8e0118157b0e2ae970dd9141722225fbd9a4 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Thu, 29 Apr 2021 22:58:55 -0500 Subject: [PATCH 12/29] arm64: dts: allwinner: a64: Allow using multiple codec DAIs Increase #sound-dai-cells on the digital codec to allow using the other DAIs provided by the codec for AIF2 and AIF3. Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210430035859.3487-4-samuel@sholland.org --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 08b37d0af529..8d549b7b28c8 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -150,7 +150,7 @@ cpudai: simple-audio-card,cpu { }; link_codec: simple-audio-card,codec { - sound-dai = <&codec>; + sound-dai = <&codec 0>; }; }; @@ -897,7 +897,7 @@ dai: dai@1c22c00 { }; codec: codec@1c22e00 { - #sound-dai-cells = <0>; + #sound-dai-cells = <1>; compatible = "allwinner,sun50i-a64-codec", "allwinner,sun8i-a33-codec"; reg = <0x01c22e00 0x600>; From 09e0a7ea75e0dcde8db975be52a690663d67c256 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Thu, 29 Apr 2021 22:58:56 -0500 Subject: [PATCH 13/29] arm64: dts: allwinner: a64: Add pinmux nodes for AIF2/AIF3 Now that the sun8i-codec driver supports AIF2 and AIF3, boards can use them in DAI links. Add the necessary pinmux nodes. Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210430035859.3487-5-samuel@sholland.org --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 8d549b7b28c8..34bb455c0f07 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -659,6 +659,18 @@ pio: pinctrl@1c20800 { interrupt-controller; #interrupt-cells = <3>; + /omit-if-no-ref/ + aif2_pins: aif2-pins { + pins = "PB4", "PB5", "PB6", "PB7"; + function = "aif2"; + }; + + /omit-if-no-ref/ + aif3_pins: aif3-pins { + pins = "PG10", "PG11", "PG12", "PG13"; + function = "aif3"; + }; + csi_pins: csi-pins { pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", "PE8", "PE9", "PE10", "PE11"; From 984a51c5308c907ee934e9521cc7a0b3835a1f6e Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Thu, 29 Apr 2021 22:58:57 -0500 Subject: [PATCH 14/29] arm64: dts: allwinner: a64: Allow multiple DAI links simple-audio-card supports either a single DAI link at the top level, or subnodes with one or more DAI links. To use the secondary AIFs on the codec, we need to add additional DAI links to the same sound card, so we need to use the other binding. Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210430035859.3487-6-samuel@sholland.org --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 23 +++++++++++-------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 34bb455c0f07..6ddb717f2f98 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -131,12 +131,10 @@ psci { }; sound: sound { + #address-cells = <1>; + #size-cells = <0>; compatible = "simple-audio-card"; simple-audio-card,name = "sun50i-a64-audio"; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&cpudai>; - simple-audio-card,bitclock-master = <&cpudai>; - simple-audio-card,mclk-fs = <128>; simple-audio-card,aux-devs = <&codec_analog>; simple-audio-card,routing = "Left DAC", "DACL", @@ -145,12 +143,19 @@ sound: sound { "ADCR", "Right ADC"; status = "disabled"; - cpudai: simple-audio-card,cpu { - sound-dai = <&dai>; - }; + simple-audio-card,dai-link@0 { + format = "i2s"; + frame-master = <&link0_cpu>; + bitclock-master = <&link0_cpu>; + mclk-fs = <128>; - link_codec: simple-audio-card,codec { - sound-dai = <&codec 0>; + link0_cpu: cpu { + sound-dai = <&dai>; + }; + + link0_codec: codec { + sound-dai = <&codec 0>; + }; }; }; From 36777d962082bdfd2f8e45d5cd748b21838d76cc Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Thu, 29 Apr 2021 22:58:58 -0500 Subject: [PATCH 15/29] arm64: dts: allwinner: pinephone: Add support for Bluetooth audio The PinePhone has a Bluetooth chip with its PCM interface connected to AIF3. Add the DAI link so headeset audio can be routed in hardware. Even though the link is 16 bit PCM, configuring the link a 32-bit slot is required for compatibility with AIF2, which also uses a 32-bit slot, and which shares clock dividers with AIF3. Using equal clock frequencies allows the modem and headset to be used at the same time. Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210430035859.3487-7-samuel@sholland.org --- .../dts/allwinner/sun50i-a64-pinephone.dtsi | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi index 79adea3f8cc1..4759cd976843 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi @@ -25,6 +25,11 @@ backlight: backlight { /* Backlight configuration differs per PinePhone revision. */ }; + bt_sco_codec: bt-sco-codec { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -91,6 +96,8 @@ vibrator { }; &codec { + pinctrl-names = "default"; + pinctrl-0 = <&aif3_pins>; status = "okay"; }; @@ -447,6 +454,23 @@ &sound { "MIC1", "Internal Microphone", "Headset Microphone", "HBIAS", "MIC2", "Headset Microphone"; + + simple-audio-card,dai-link@2 { + format = "dsp_a"; + frame-master = <&link2_codec>; + bitclock-master = <&link2_codec>; + bitclock-inversion; + + link2_cpu: cpu { + sound-dai = <&bt_sco_codec 0>; + }; + + link2_codec: codec { + sound-dai = <&codec 2>; + dai-tdm-slot-num = <1>; + dai-tdm-slot-width = <32>; + }; + }; }; &uart0 { From 92ed3675574723a963152abbbe527b47f659340f Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 17 May 2021 00:35:23 +0800 Subject: [PATCH 16/29] dt-bindings: arm: Add NanoPi R1S H5 Add the bindings for NanoPi R1S H5 board. Signed-off-by: Chukun Pan Acked-by: Rob Herring Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210516163523.9484-3-amadeus@jmu.edu.cn --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index ec8108483b49..889128acf49a 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -275,6 +275,11 @@ properties: - const: friendlyarm,nanopi-r1 - const: allwinner,sun8i-h3 + - description: FriendlyARM NanoPi R1S H5 + items: + - const: friendlyarm,nanopi-r1s-h5 + - const: allwinner,sun50i-h5 + - description: FriendlyARM ZeroPi items: - const: friendlyarm,zeropi From 9962cb9be2db877c232aaf00db40125c0d7bf4bc Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 17 May 2021 00:35:22 +0800 Subject: [PATCH 17/29] arm64: dts: allwinner: h5: Add NanoPi R1S H5 support The NanoPi R1S H5 is a open source board made by FriendlyElec. It has the following features: - Allwinner H5, Quad-core Cortex-A53 - 512MB DDR3 RAM - 10/100/1000M Ethernet x 2 - RTL8189ETV WiFi 802.11b/g/n - USB 2.0 host port (A) - MicroSD Slot - Serial Debug Port - 5V 2A DC power-supply Signed-off-by: Chukun Pan Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210516163523.9484-2-amadeus@jmu.edu.cn --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts | 195 ++++++++++++++++++ 2 files changed, 196 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index 41ce680e5f8d..a96d9d2d8dd8 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -25,6 +25,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h3-it.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h5-cc.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-r1s-h5.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts new file mode 100644 index 000000000000..55bcdf8d1a07 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 Chukun Pan + * + * Based on sun50i-h5-nanopi-neo-plus2.dts, which is: + * Copyright (C) 2017 Antony Antony + * Copyright (C) 2016 ARM Ltd. + */ + +/dts-v1/; +#include "sun50i-h5.dtsi" +#include "sun50i-h5-cpu-opp.dtsi" + +#include +#include +#include + +/ { + model = "FriendlyARM NanoPi R1S H5"; + compatible = "friendlyarm,nanopi-r1s-h5", "allwinner,sun50i-h5"; + + aliases { + ethernet0 = &emac; + ethernet1 = &rtl8189etv; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_LAN; + color = ; + gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-2 { + function = LED_FUNCTION_WAN; + color = ; + gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; + }; + }; + + r-gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + }; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb0_vbus: usb0-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ + status = "okay"; + }; + + vdd_cpux: gpio-regulator { + compatible = "regulator-gpio"; + regulator-name = "vdd-cpux"; + regulator-type = "voltage"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <50>; /* 4ms */ + gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; + gpios-states = <0x1>; + states = <1100000 0x0>, <1300000 0x1>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + post-power-on-delay-ms = <200>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpux>; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; +}; + +&i2c0 { + status = "okay"; + + eeprom@51 { + compatible = "microchip,24c02"; + reg = <0x51>; + pagesize = <16>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + rtl8189etv: sdio_wifi@1 { + reg = <1>; + }; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pa_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + /* USB Type-A port's VBUS is always on */ + usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + usb0_vbus-supply = <®_usb0_vbus>; + status = "okay"; +}; From cd8d60399ac5634513199b76c7dbd43092e29b1b Mon Sep 17 00:00:00 2001 From: Tobias Schramm Date: Thu, 13 May 2021 22:35:26 +0200 Subject: [PATCH 18/29] dt-bindings: pwm: allwinner: add v3s pwm compatible The Allwinner V3s pwm peripheral is compatible with the pwm peripheral inside the Allwinner A20. This patch adds a compatible string for it. Signed-off-by: Tobias Schramm Reviewed-by: Andre Przywara Acked-by: Rob Herring Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210513203527.2072090-2-t.schramm@manjaro.org --- .../devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml index 7dcab2bf8128..04ff708fdc86 100644 --- a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml @@ -24,6 +24,9 @@ properties: - items: - const: allwinner,sun8i-a83t-pwm - const: allwinner,sun8i-h3-pwm + - items: + - const: allwinner,sun8i-v3s-pwm + - const: allwinner,sun7i-a20-pwm - items: - const: allwinner,sun50i-a64-pwm - const: allwinner,sun5i-a13-pwm From 1d34350cdb6ba23b9b627aec09a14dfc6db046ee Mon Sep 17 00:00:00 2001 From: Tobias Schramm Date: Thu, 13 May 2021 22:35:27 +0200 Subject: [PATCH 19/29] ARM: dts: sun8i: v3s: add pwm controller to v3s dts The Allwinner V3s and V3 SoCs feature a pwm controller identical to the one used in the Allwinner A20. This commit adds it to the V3s dtsi. Signed-off-by: Tobias Schramm Reviewed-by: Andre Przywara Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210513203527.2072090-3-t.schramm@manjaro.org --- arch/arm/boot/dts/sun8i-v3s.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index eb4cb63fef13..456dee9de87f 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -422,6 +422,15 @@ wdt0: watchdog@1c20ca0 { clocks = <&osc24M>; }; + pwm: pwm@1c21400 { + compatible = "allwinner,sun8i-v3s-pwm", + "allwinner,sun7i-a20-pwm"; + reg = <0x01c21400 0xc>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + lradc: lradc@1c22800 { compatible = "allwinner,sun4i-a10-lradc-keys"; reg = <0x01c22800 0x400>; From 49b9e240b84d90511f581c3384582c615b1fd586 Mon Sep 17 00:00:00 2001 From: Tobias Schramm Date: Fri, 14 May 2021 15:43:59 +0200 Subject: [PATCH 20/29] ARM: dts: sun8i: v3s: add DMA controller to v3s dts The Allwinner V3s and V3 feature a DMA controller. This commit adds it to the V3s dtsi. Signed-off-by: Tobias Schramm Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210514134405.2097464-2-t.schramm@manjaro.org --- arch/arm/boot/dts/sun8i-v3s.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 456dee9de87f..1ba078cc70ac 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -1,5 +1,6 @@ /* * Copyright (C) 2016 Icenowy Zheng + * Copyright (C) 2021 Tobias Schramm * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -172,6 +173,15 @@ nmi_intc: interrupt-controller@1c000d0 { interrupts = ; }; + dma: dma-controller@1c02000 { + compatible = "allwinner,sun8i-v3s-dma"; + reg = <0x01c02000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_DMA>; + resets = <&ccu RST_BUS_DMA>; + #dma-cells = <1>; + }; + tcon0: lcd-controller@1c0c000 { compatible = "allwinner,sun8i-v3s-tcon"; reg = <0x01c0c000 0x1000>; From 93bc32b0397ee94ae0a5db92b6d9dd3ff6f9d4fe Mon Sep 17 00:00:00 2001 From: Tobias Schramm Date: Fri, 14 May 2021 15:44:00 +0200 Subject: [PATCH 21/29] ARM: dts: sun8i: v3s: add DMA properties to peripherals supporting DMA This commit adds DMA properties to all peripherals supporting DMA on the Allwinner V3s, enabling accelerated data transfer to them. Signed-off-by: Tobias Schramm Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210514134405.2097464-3-t.schramm@manjaro.org --- arch/arm/boot/dts/sun8i-v3s.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 1ba078cc70ac..d027f34e68eb 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -285,6 +285,8 @@ crypto@1c15000 { interrupts = ; clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; clock-names = "ahb", "mod"; + dmas = <&dma 16>, <&dma 16>; + dma-names = "rx", "tx"; resets = <&ccu RST_BUS_CE>; reset-names = "ahb"; }; @@ -455,6 +457,8 @@ uart0: serial@1c28000 { reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART0>; + dmas = <&dma 6>, <&dma 6>; + dma-names = "rx", "tx"; resets = <&ccu RST_BUS_UART0>; status = "disabled"; }; @@ -466,6 +470,8 @@ uart1: serial@1c28400 { reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART1>; + dmas = <&dma 7>, <&dma 7>; + dma-names = "rx", "tx"; resets = <&ccu RST_BUS_UART1>; status = "disabled"; }; @@ -477,6 +483,8 @@ uart2: serial@1c28800 { reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART2>; + dmas = <&dma 8>, <&dma 8>; + dma-names = "rx", "tx"; resets = <&ccu RST_BUS_UART2>; pinctrl-0 = <&uart2_pins>; pinctrl-names = "default"; @@ -556,6 +564,8 @@ spi0: spi@1c68000 { interrupts = ; clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; clock-names = "ahb", "mod"; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; resets = <&ccu RST_BUS_SPI0>; From 5348915db9b878084ae67f159063550fe0500847 Mon Sep 17 00:00:00 2001 From: Tobias Schramm Date: Fri, 14 May 2021 15:44:01 +0200 Subject: [PATCH 22/29] ARM: dts: sun8i: v3s: add analog codec and frontend to v3s dts The Allwinner V3s and V3 SoCs feature an integrated analog audio codec. Additionally both have an analog frontend with mixers and amplifiers for the codec. This commit adds both, the analog codec and its frontend to the V3s dtsi. Signed-off-by: Tobias Schramm Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210514134405.2097464-4-t.schramm@manjaro.org --- arch/arm/boot/dts/sun8i-v3s.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index d027f34e68eb..b30bc1a25ebb 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -450,6 +450,25 @@ lradc: lradc@1c22800 { status = "disabled"; }; + codec: codec@1c22c00 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-v3s-codec"; + reg = <0x01c22c00 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; + clock-names = "apb", "codec"; + resets = <&ccu RST_BUS_CODEC>; + dmas = <&dma 15>, <&dma 15>; + dma-names = "rx", "tx"; + allwinner,codec-analog-controls = <&codec_analog>; + status = "disabled"; + }; + + codec_analog: codec-analog@1c23000 { + compatible = "allwinner,sun8i-v3s-codec-analog"; + reg = <0x01c23000 0x4>; + }; + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; From 78e8db071b684f4b3975653fd31ffabc8c204501 Mon Sep 17 00:00:00 2001 From: Tobias Schramm Date: Fri, 14 May 2021 15:44:02 +0200 Subject: [PATCH 23/29] ASoC: dt-bindings: sun8i-a23-codec-analog: add compatible for Allwinner V3 The analog codec frontend of the Allwinner V3 is compatible with the analog codec frontend used on the Allwinner H3. This patch adds a compatible string for the analog codec frontend on the Allwinner V3 SoC. Signed-off-by: Tobias Schramm Reviewed-by: Rob Herring Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210514134405.2097464-5-t.schramm@manjaro.org --- .../bindings/sound/allwinner,sun8i-a23-codec-analog.yaml | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a23-codec-analog.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a23-codec-analog.yaml index 9718358826ab..26eca21e1f0f 100644 --- a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a23-codec-analog.yaml +++ b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a23-codec-analog.yaml @@ -12,12 +12,15 @@ maintainers: properties: compatible: - enum: + oneOf: # FIXME: This is documented in the PRCM binding, but needs to be # migrated here at some point # - allwinner,sun8i-a23-codec-analog - - allwinner,sun8i-h3-codec-analog - - allwinner,sun8i-v3s-codec-analog + - const: allwinner,sun8i-h3-codec-analog + - items: + - const: allwinner,sun8i-v3-codec-analog + - const: allwinner,sun8i-h3-codec-analog + - const: allwinner,sun8i-v3s-codec-analog reg: maxItems: 1 From 8575276c1fe3c003c4a31b1c4ec6d47ea50843d0 Mon Sep 17 00:00:00 2001 From: Tobias Schramm Date: Fri, 14 May 2021 15:44:03 +0200 Subject: [PATCH 24/29] ARM: dts: sun8i: V3: add codec analog frontend to V3 dts The Allwinner V3 SoC has a different analog codec frontend than the V3s SoC. The frontend used on the V3 SoC is compatible with the on used in the Allwinner H3 SoC. This patch adds the corresponding node to the Allwinner V3 dtsi. Signed-off-by: Tobias Schramm Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210514134405.2097464-6-t.schramm@manjaro.org --- arch/arm/boot/dts/sun8i-v3.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3.dtsi b/arch/arm/boot/dts/sun8i-v3.dtsi index c279e13583ba..8af790d286b9 100644 --- a/arch/arm/boot/dts/sun8i-v3.dtsi +++ b/arch/arm/boot/dts/sun8i-v3.dtsi @@ -9,6 +9,11 @@ &ccu { compatible = "allwinner,sun8i-v3-ccu"; }; +&codec_analog { + compatible = "allwinner,sun8i-v3-codec-analog", + "allwinner,sun8i-h3-codec-analog"; +}; + &emac { /delete-property/ phy-handle; /delete-property/ phy-mode; From ce09d1a6800df7ce0f73ae4d4b3ad4975cb31498 Mon Sep 17 00:00:00 2001 From: Tobias Schramm Date: Fri, 14 May 2021 15:44:04 +0200 Subject: [PATCH 25/29] dt-bindings: sound: sun4i-i2s: add Allwinner V3 I2S compatible The I2S peripheral of the Allwinner V3 SoC is compatible with the one found in the Allwinner H3 SoC. This patch adds a compatible string for it. Signed-off-by: Tobias Schramm Reviewed-by: Rob Herring Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210514134405.2097464-7-t.schramm@manjaro.org --- .../devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml index a16e37b01e1d..39b66e9ce3e3 100644 --- a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml @@ -20,6 +20,9 @@ properties: - const: allwinner,sun6i-a31-i2s - const: allwinner,sun8i-a83t-i2s - const: allwinner,sun8i-h3-i2s + - items: + - const: allwinner,sun8i-v3-i2s + - const: allwinner,sun8i-h3-i2s - const: allwinner,sun50i-a64-codec-i2s - items: - const: allwinner,sun50i-a64-i2s From 65a50bca77177210c2333789ee7cf7191d3b99ae Mon Sep 17 00:00:00 2001 From: Tobias Schramm Date: Fri, 14 May 2021 15:44:05 +0200 Subject: [PATCH 26/29] ARM: dts: sun8i: V3: add I2S interface to V3 dts The Allwinner V3 SoC features an I2S interface. The I2S peripheral is identical to that in the Allwinner H3 SoC. This commit adds it to the Allwinner V3 dts. Signed-off-by: Tobias Schramm Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210514134405.2097464-8-t.schramm@manjaro.org --- arch/arm/boot/dts/sun8i-v3.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3.dtsi b/arch/arm/boot/dts/sun8i-v3.dtsi index 8af790d286b9..186c30cbe6ee 100644 --- a/arch/arm/boot/dts/sun8i-v3.dtsi +++ b/arch/arm/boot/dts/sun8i-v3.dtsi @@ -1,10 +1,31 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (C) 2019 Icenowy Zheng + * Copyright (C) 2021 Tobias Schramm */ #include "sun8i-v3s.dtsi" +/ { + soc { + i2s0: i2s@1c22000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-v3-i2s", + "allwinner,sun8i-h3-i2s"; + reg = <0x01c22000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; + clock-names = "apb", "mod"; + dmas = <&dma 3>, <&dma 3>; + dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_pins>; + resets = <&ccu RST_BUS_I2S0>; + status = "disabled"; + }; + }; +}; + &ccu { compatible = "allwinner,sun8i-v3-ccu"; }; @@ -30,6 +51,11 @@ external_mdio: mdio@2 { &pio { compatible = "allwinner,sun8i-v3-pinctrl"; + i2s0_pins: i2s0-pins { + pins = "PG10", "PG11", "PG12", "PG13"; + function = "i2s"; + }; + uart1_pg_pins: uart1-pg-pins { pins = "PG6", "PG7"; function = "uart1"; From 086a4302380931ca627b51b4ef5ba3bfeca21276 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Mon, 10 May 2021 18:36:47 +0200 Subject: [PATCH 27/29] ARM: dts: sun8i: r40: Add timer node Allwinner R40 has a timer. Add a node for it. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210510163647.2731675-1-jernej.skrabec@gmail.com --- arch/arm/boot/dts/sun8i-r40.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 03e054c0bac4..291f4784e86c 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -691,6 +691,18 @@ uart7_pi_pins: uart7-pi-pins { }; }; + timer@1c20c00 { + compatible = "allwinner,sun4i-a10-timer"; + reg = <0x01c20c00 0x90>; + interrupts = , + , + , + , + , + ; + clocks = <&osc24M>; + }; + wdt: watchdog@1c20c90 { compatible = "allwinner,sun4i-a10-wdt"; reg = <0x01c20c90 0x10>; From 091d5db0abd6d2530c6c942067ac5c78e64d4d08 Mon Sep 17 00:00:00 2001 From: Arnaud Ferraris Date: Thu, 29 Apr 2021 22:58:59 -0500 Subject: [PATCH 28/29] arm64: dts: allwinner: pinephone: Set audio card name Add the "PinePhone" name to the sound card: this will make upstreaming an ALSA UCM config easier as we can use a unique name. It also avoids an issue where the default card name is truncated. Signed-off-by: Arnaud Ferraris [Samuel: Split out change, updated commit message] Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210430035859.3487-8-samuel@sholland.org --- arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi index 4759cd976843..5b44a979f250 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi @@ -433,6 +433,7 @@ ®_rtc_ldo { &sound { status = "okay"; + simple-audio-card,name = "PinePhone"; simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>; simple-audio-card,widgets = "Microphone", "Headset Microphone", "Microphone", "Internal Microphone", From d42b3e045a34ec7c88c818ee057f7c2ecc8f9fdd Mon Sep 17 00:00:00 2001 From: Andreas Rehn Date: Tue, 25 May 2021 19:31:59 +0200 Subject: [PATCH 29/29] ARM: dts: sun8i: v3s: enable emac for zero Dock dwmac-sun8i supports v3s and Licheepi-zero Dock provides an ethernet port furthermore, align nodes in alphabetical order Signed-off-by: Andreas Rehn Reviewed-by: Andre Przywara Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210525173159.183415-1-rehn.andreas86@gmail.com --- .../boot/dts/sun8i-v3s-licheepi-zero-dock.dts | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts index db5cd0b8574b..752ad05c8f83 100644 --- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts +++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts @@ -49,16 +49,18 @@ / { compatible = "licheepi,licheepi-zero-dock", "licheepi,licheepi-zero", "allwinner,sun8i-v3s"; + aliases { + ethernet0 = &emac; + }; + leds { /* The LEDs use PG0~2 pins, which conflict with MMC1 */ status = "disabled"; }; }; -&mmc1 { - broken-cd; - bus-width = <4>; - vmmc-supply = <®_vcc3v3>; +&emac { + allwinner,leds-active-low; status = "okay"; }; @@ -94,3 +96,10 @@ button-800 { voltage = <800000>; }; }; + +&mmc1 { + broken-cd; + bus-width = <4>; + vmmc-supply = <®_vcc3v3>; + status = "okay"; +};