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xhci: use BIT macro
We have the macro. Use it. Signed-off-by: Oliver Neukum <oneukum@suse.com> Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> Link: https://patch.msgid.link/20260402131342.2628648-2-mathias.nyman@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Oliver Neukum
committed by
Greg Kroah-Hartman
Greg Kroah-Hartman
parent
74a2287209
commit
abe93f27cd
@@ -12,6 +12,7 @@
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#ifndef __LINUX_XHCI_HCD_H
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#define __LINUX_XHCI_HCD_H
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#include <linux/bits.h>
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#include <linux/usb.h>
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#include <linux/timer.h>
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#include <linux/kernel.h>
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@@ -125,17 +126,17 @@ struct xhci_op_regs {
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* PCI config regs). HC does NOT drive a USB reset on the downstream ports.
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* The xHCI driver must reinitialize the xHC after setting this bit.
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*/
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#define CMD_RESET (1 << 1)
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#define CMD_RESET BIT(1)
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/* Event Interrupt Enable - a '1' allows interrupts from the host controller */
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#define CMD_EIE XHCI_CMD_EIE
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/* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
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#define CMD_HSEIE XHCI_CMD_HSEIE
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/* bits 4:6 are reserved (and should be preserved on writes). */
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/* light reset (port status stays unchanged) - reset completed when this is 0 */
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#define CMD_LRESET (1 << 7)
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#define CMD_LRESET BIT(7)
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/* host controller save/restore state. */
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#define CMD_CSS (1 << 8)
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#define CMD_CRS (1 << 9)
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#define CMD_CSS BIT(8)
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#define CMD_CRS BIT(9)
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/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
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#define CMD_EWE XHCI_CMD_EWE
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/* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
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@@ -143,9 +144,9 @@ struct xhci_op_regs {
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* '0' means the xHC can power it off if all ports are in the disconnect,
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* disabled, or powered-off state.
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*/
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#define CMD_PM_INDEX (1 << 11)
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#define CMD_PM_INDEX BIT(11)
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/* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */
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#define CMD_ETE (1 << 14)
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#define CMD_ETE BIT(14)
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/* bits 15:31 are reserved (and should be preserved on writes). */
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#define XHCI_RESET_LONG_USEC (10 * 1000 * 1000)
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@@ -155,22 +156,22 @@ struct xhci_op_regs {
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/* HC not running - set to 1 when run/stop bit is cleared. */
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#define STS_HALT XHCI_STS_HALT
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/* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
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#define STS_FATAL (1 << 2)
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#define STS_FATAL BIT(2)
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/* event interrupt - clear this prior to clearing any IP flags in IR set*/
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#define STS_EINT (1 << 3)
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#define STS_EINT BIT(3)
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/* port change detect */
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#define STS_PORT (1 << 4)
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#define STS_PORT BIT(4)
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/* bits 5:7 reserved and zeroed */
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/* save state status - '1' means xHC is saving state */
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#define STS_SAVE (1 << 8)
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#define STS_SAVE BIT(8)
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/* restore state status - '1' means xHC is restoring state */
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#define STS_RESTORE (1 << 9)
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#define STS_RESTORE BIT(9)
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/* true: save or restore error */
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#define STS_SRE (1 << 10)
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#define STS_SRE BIT(10)
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/* true: Controller Not Ready to accept doorbell or op reg writes after reset */
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#define STS_CNR XHCI_STS_CNR
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/* true: internal Host Controller Error - SW needs to reset and reinitialize */
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#define STS_HCE (1 << 12)
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#define STS_HCE BIT(12)
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/* bits 13:31 reserved and should be preserved */
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/*
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@@ -182,17 +183,17 @@ struct xhci_op_regs {
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/* Most of the device notification types should only be used for debug.
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* SW does need to pay attention to function wake notifications.
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*/
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#define DEV_NOTE_FWAKE (1 << 1)
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#define DEV_NOTE_FWAKE BIT(1)
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/* CRCR - Command Ring Control Register - cmd_ring bitmasks */
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/* bit 0 - Cycle bit indicates the ownership of the command ring */
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#define CMD_RING_CYCLE (1 << 0)
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#define CMD_RING_CYCLE BIT(0)
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/* stop ring operation after completion of the currently executing command */
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#define CMD_RING_PAUSE (1 << 1)
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#define CMD_RING_PAUSE BIT(1)
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/* stop ring immediately - abort the currently executing command */
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#define CMD_RING_ABORT (1 << 2)
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#define CMD_RING_ABORT BIT(2)
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/* true: command ring is running */
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#define CMD_RING_RUNNING (1 << 3)
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#define CMD_RING_RUNNING BIT(3)
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/* bits 63:6 - Command Ring pointer */
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#define CMD_RING_PTR_MASK GENMASK_ULL(63, 6)
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@@ -200,9 +201,9 @@ struct xhci_op_regs {
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/* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
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#define MAX_DEVS(p) ((p) & 0xff)
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/* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */
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#define CONFIG_U3E (1 << 8)
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#define CONFIG_U3E BIT(8)
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/* bit 9: Configuration Information Enable, xhci 1.1 */
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#define CONFIG_CIE (1 << 9)
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#define CONFIG_CIE BIT(9)
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/* bits 10:31 - reserved and should be preserved */
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/* bits 15:0 - HCD page shift bit */
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@@ -235,9 +236,9 @@ struct xhci_intr_reg {
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/* iman bitmasks */
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/* bit 0 - Interrupt Pending (IP), whether there is an interrupt pending. Write-1-to-clear. */
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#define IMAN_IP (1 << 0)
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#define IMAN_IP BIT(0)
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/* bit 1 - Interrupt Enable (IE), whether the interrupter is capable of generating an interrupt */
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#define IMAN_IE (1 << 1)
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#define IMAN_IE BIT(1)
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/* imod bitmasks */
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/*
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@@ -267,7 +268,7 @@ struct xhci_intr_reg {
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* bit 3 - Event Handler Busy (EHB), whether the event ring is scheduled to be serviced by
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* a work queue (or delayed service routine)?
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*/
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#define ERST_EHB (1 << 3)
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#define ERST_EHB BIT(3)
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/* bits 63:4 - Event Ring Dequeue Pointer */
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#define ERST_PTR_MASK GENMASK_ULL(63, 4)
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@@ -356,15 +357,15 @@ struct xhci_slot_ctx {
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#define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20)
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/* bit 24 reserved */
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/* Is this LS/FS device connected through a HS hub? - bit 25 */
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#define DEV_MTT (0x1 << 25)
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#define DEV_MTT BIT(25)
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/* Set if the device is a hub - bit 26 */
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#define DEV_HUB (0x1 << 26)
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#define DEV_HUB BIT(26)
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/* Index of the last valid endpoint context in this device context - 27:31 */
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#define LAST_CTX_MASK (0x1f << 27)
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#define LAST_CTX(p) ((p) << 27)
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#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
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#define SLOT_FLAG (1 << 0)
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#define EP0_FLAG (1 << 1)
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#define SLOT_FLAG BIT(0)
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#define EP0_FLAG BIT(1)
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/* dev_info2 bitmasks */
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/* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
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@@ -463,7 +464,7 @@ struct xhci_ep_ctx {
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#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
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#define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10)
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/* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
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#define EP_HAS_LSA (1 << 15)
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#define EP_HAS_LSA BIT(15)
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/* hosts with LEC=1 use bits 31:24 as ESIT high bits. */
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#define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff)
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@@ -498,7 +499,7 @@ struct xhci_ep_ctx {
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#define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
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/* deq bitmasks */
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#define EP_CTX_CYCLE_MASK (1 << 0)
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#define EP_CTX_CYCLE_MASK BIT(0)
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/* bits 63:4 - TR Dequeue Pointer */
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#define TR_DEQ_PTR_MASK GENMASK_ULL(63, 4)
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@@ -661,18 +662,18 @@ struct xhci_virt_ep {
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struct xhci_ring *new_ring;
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unsigned int err_count;
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unsigned int ep_state;
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#define SET_DEQ_PENDING (1 << 0)
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#define EP_HALTED (1 << 1) /* For stall handling */
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#define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */
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#define SET_DEQ_PENDING BIT(0)
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#define EP_HALTED BIT(1) /* For stall handling */
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#define EP_STOP_CMD_PENDING BIT(2) /* For URB cancellation */
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/* Transitioning the endpoint to using streams, don't enqueue URBs */
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#define EP_GETTING_STREAMS (1 << 3)
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#define EP_HAS_STREAMS (1 << 4)
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#define EP_GETTING_STREAMS BIT(3)
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#define EP_HAS_STREAMS BIT(4)
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/* Transitioning the endpoint to not using streams, don't enqueue URBs */
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#define EP_GETTING_NO_STREAMS (1 << 5)
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#define EP_HARD_CLEAR_TOGGLE (1 << 6)
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#define EP_SOFT_CLEAR_TOGGLE (1 << 7)
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#define EP_GETTING_NO_STREAMS BIT(5)
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#define EP_HARD_CLEAR_TOGGLE BIT(6)
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#define EP_SOFT_CLEAR_TOGGLE BIT(7)
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/* usb_hub_clear_tt_buffer is in progress */
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#define EP_CLEARING_TT (1 << 8)
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#define EP_CLEARING_TT BIT(8)
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/* ---- Related to URB cancellation ---- */
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struct list_head cancelled_td_list;
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struct xhci_hcd *xhci;
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@@ -954,7 +955,7 @@ struct xhci_link_trb {
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};
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/* control bitfields */
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#define LINK_TOGGLE (0x1<<1)
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#define LINK_TOGGLE BIT(1)
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/* Command completion event TRB */
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struct xhci_event_cmd {
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@@ -968,13 +969,13 @@ struct xhci_event_cmd {
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#define COMP_PARAM(p) ((p) & 0xffffff) /* Command Completion Parameter */
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/* Address device - disable SetAddress */
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#define TRB_BSR (1<<9)
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#define TRB_BSR BIT(9)
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/* Configure Endpoint - Deconfigure */
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#define TRB_DC (1<<9)
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#define TRB_DC BIT(9)
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/* Stop Ring - Transfer State Preserve */
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#define TRB_TSP (1<<9)
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#define TRB_TSP BIT(9)
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enum xhci_ep_reset_type {
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EP_HARD_RESET,
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@@ -1017,13 +1018,13 @@ enum xhci_setup_dev {
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#define SCT_FOR_TRB(p) (((p) & 0x7) << 1)
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/* Link TRB specific fields */
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#define TRB_TC (1<<1)
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#define TRB_TC BIT(1)
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/* Port Status Change Event TRB fields */
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/* Port ID - bits 31:24 */
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#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
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#define EVENT_DATA (1 << 2)
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#define EVENT_DATA BIT(2)
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/* Normal TRB fields */
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/* transfer_len bitmasks - bits 0:16 */
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@@ -1038,36 +1039,36 @@ enum xhci_setup_dev {
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#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
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/* Cycle bit - indicates TRB ownership by HC or HCD */
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#define TRB_CYCLE (1<<0)
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#define TRB_CYCLE BIT(0)
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/*
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* Force next event data TRB to be evaluated before task switch.
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* Used to pass OS data back after a TD completes.
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*/
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#define TRB_ENT (1<<1)
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#define TRB_ENT BIT(1)
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/* Interrupt on short packet */
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#define TRB_ISP (1<<2)
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#define TRB_ISP BIT(2)
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/* Set PCIe no snoop attribute */
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#define TRB_NO_SNOOP (1<<3)
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#define TRB_NO_SNOOP BIT(3)
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/* Chain multiple TRBs into a TD */
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#define TRB_CHAIN (1<<4)
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#define TRB_CHAIN BIT(4)
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/* Interrupt on completion */
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#define TRB_IOC (1<<5)
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#define TRB_IOC BIT(5)
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/* The buffer pointer contains immediate data */
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#define TRB_IDT (1<<6)
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#define TRB_IDT BIT(6)
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/* TDs smaller than this might use IDT */
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#define TRB_IDT_MAX_SIZE 8
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/* Block Event Interrupt */
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#define TRB_BEI (1<<9)
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#define TRB_BEI BIT(9)
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/* Control transfer TRB specific fields */
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#define TRB_DIR_IN (1<<16)
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#define TRB_DIR_IN BIT(16)
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#define TRB_TX_TYPE(p) ((p) << 16)
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#define TRB_DATA_OUT 2
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#define TRB_DATA_IN 3
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/* Isochronous TRB specific fields */
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#define TRB_SIA (1<<31)
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#define TRB_SIA BIT(31)
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#define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20)
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#define GET_FRAME_ID(p) (((p) >> 20) & 0x7ff)
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/* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */
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@@ -1535,9 +1536,9 @@ struct xhci_hcd {
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struct xhci_interrupter **interrupters;
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struct xhci_ring *cmd_ring;
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unsigned int cmd_ring_state;
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#define CMD_RING_STATE_RUNNING (1 << 0)
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#define CMD_RING_STATE_ABORTED (1 << 1)
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#define CMD_RING_STATE_STOPPED (1 << 2)
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#define CMD_RING_STATE_RUNNING BIT(0)
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#define CMD_RING_STATE_ABORTED BIT(1)
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#define CMD_RING_STATE_STOPPED BIT(2)
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struct list_head cmd_list;
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unsigned int cmd_ring_reserved_trbs;
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struct delayed_work cmd_timer;
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@@ -1578,9 +1579,9 @@ struct xhci_hcd {
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*
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* There are no reports of xHCI host controllers that display this issue.
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*/
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#define XHCI_STATE_DYING (1 << 0)
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#define XHCI_STATE_HALTED (1 << 1)
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#define XHCI_STATE_REMOVING (1 << 2)
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#define XHCI_STATE_DYING BIT(0)
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#define XHCI_STATE_HALTED BIT(1)
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#define XHCI_STATE_REMOVING BIT(2)
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unsigned long long quirks;
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#define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
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#define XHCI_RESET_EP_QUIRK BIT_ULL(1) /* Deprecated */
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