From b5b481063f5a68ef8361ba025bf655fc451f5d93 Mon Sep 17 00:00:00 2001 From: Jun Yan Date: Fri, 13 Feb 2026 15:38:10 +0800 Subject: [PATCH 001/665] arm64: dts: amlogic: meson-gxl-s905d-phicomm-n1: add bluetooth node The Phicomm N1 uses a CY43455 (BCM43438) module with its Bluetooth interface connected to uart_A. Add the required device tree node to enable proper functionality. Signed-off-by: Jun Yan Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260213073810.552341-1-jerrysteve1101@gmail.com Signed-off-by: Neil Armstrong --- .../dts/amlogic/meson-gxl-s905d-phicomm-n1.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts index 393d3cb33b9e..dea3a60e8527 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts @@ -30,6 +30,21 @@ &cvbs_vdac_port { status = "disabled"; }; +&uart_A { + status = "okay"; + pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + max-speed = <2000000>; + clocks = <&wifi32k>; + clock-names = "lpo"; + }; +}; + &usb { dr_mode = "host"; }; From a895042339c77859adbef957e7c0acaa8774d955 Mon Sep 17 00:00:00 2001 From: Nick Xie Date: Sat, 28 Feb 2026 14:37:47 +0800 Subject: [PATCH 002/665] arm64: dts: amlogic: meson-s4: add UART_A node Add the UART_A node and its related pinctrl definitions to the Meson S4 SoC dtsi. The pinctrl groups are split into basic tx/rx and flow control (cts/rts) to allow board-level flexibility. This interface is typically used for Bluetooth communication on boards like the Khadas VIM1S. Signed-off-by: Nick Xie Reviewed-by: Martin Blumenstingl Link: https://patch.msgid.link/20260228063750.701887-2-nick@khadas.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 26 +++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi index dfc0a30a6e61..4a3e9ad82d28 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi @@ -163,6 +163,22 @@ mux { }; }; + uart_a_pins: uart-a-pins { + mux { + groups = "uart_a_tx", + "uart_a_rx"; + function = "uart_a"; + }; + }; + + uart_a_cts_rts_pins: uart-a-cts-rts-pins { + mux { + groups = "uart_a_cts", + "uart_a_rts"; + function = "uart_a"; + }; + }; + i2c0_pins1: i2c0-pins1 { mux { groups = "i2c0_sda", @@ -814,6 +830,16 @@ mdio0: mdio { }; }; + uart_a: serial@fe078000 { + compatible = "amlogic,meson-s4-uart", + "amlogic,meson-ao-uart"; + reg = <0x0 0xfe078000 0x0 0x18>; + interrupts = ; + clocks = <&xtal>, <&clkc_periphs CLKID_UART_A>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + status = "disabled"; + }; + sdio: mmc@fe088000 { compatible = "amlogic,meson-axg-mmc"; reg = <0x0 0xfe088000 0x0 0x800>; From 75ed598cd6f014f6fbd678ddcfb2db58f088f349 Mon Sep 17 00:00:00 2001 From: Nick Xie Date: Sat, 28 Feb 2026 14:37:48 +0800 Subject: [PATCH 003/665] arm64: dts: amlogic: meson-s4-s905y4-khadas-vim1s: enable bluetooth The Khadas VIM1S board uses the Ampak AP6256 Wi-Fi/Bluetooth module. The Bluetooth controller is connected via UART_A and requires the external 32k clock (LPO). Enable the UART_A node and add the bluetooth child node to support it. Signed-off-by: Nick Xie Reviewed-by: Martin Blumenstingl Link: https://patch.msgid.link/20260228063750.701887-3-nick@khadas.com Signed-off-by: Neil Armstrong --- .../dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts b/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts index 27d0f6134ea9..d36533f5559a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts +++ b/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts @@ -254,6 +254,21 @@ &spicc0 { cs-gpios = <&gpio GPIOX_10 GPIO_ACTIVE_LOW>; }; +&uart_a { + status = "okay"; + pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm4345c5"; + shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + max-speed = <2000000>; + clocks = <&sdio_32k>; + clock-names = "lpo"; + }; +}; + &uart_b { status = "okay"; }; From b6a8c516b5895d24968878546557d6c2b9e5766c Mon Sep 17 00:00:00 2001 From: Nick Xie Date: Sat, 28 Feb 2026 14:37:49 +0800 Subject: [PATCH 004/665] arm64: dts: amlogic: meson-s4-s905y4-khadas-vim1s: add PWM LED support The Khadas VIM1S board features a white LED connected to the PWM_G controller (PWM channel 0). Enable the PWM_G controller and add the pwm-leds node to support using this LED as a heartbeat indicator. Signed-off-by: Nick Xie Reviewed-by: Martin Blumenstingl Link: https://patch.msgid.link/20260228063750.701887-4-nick@khadas.com Signed-off-by: Neil Armstrong --- .../amlogic/meson-s4-s905y4-khadas-vim1s.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts b/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts index d36533f5559a..0bd738c1e786 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts +++ b/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "meson-s4.dtsi" +#include / { model = "Khadas VIM1S"; @@ -43,6 +44,18 @@ emmc_pwrseq: emmc-pwrseq { reset-gpios = <&gpio GPIOB_9 GPIO_ACTIVE_LOW>; }; + pwm-leds { + compatible = "pwm-leds"; + + led-1 { + color = ; + function = LED_FUNCTION_STATUS; + linux,default-trigger = "heartbeat"; + max-brightness = <255>; + pwms = <&pwm_gh 0 30040 0>; + }; + }; + sdio_32k: sdio-32k { compatible = "pwm-clock"; #clock-cells = <0>; @@ -196,6 +209,12 @@ &pwm_ef { pinctrl-names = "default"; }; +&pwm_gh { + status = "okay"; + pinctrl-0 = <&pwm_g_pins1>; + pinctrl-names = "default"; +}; + &pwm_ij { status = "okay"; }; From cb00d65db2fd5367c2066effc18492ddab37ca14 Mon Sep 17 00:00:00 2001 From: Nick Xie Date: Sat, 28 Feb 2026 14:37:50 +0800 Subject: [PATCH 005/665] arm64: dts: amlogic: meson-s4-s905y4-khadas-vim1s: add POWER key support Add the gpio-keys-polled node to support the Power button found on the Khadas VIM1S board. The button is connected to the GPIOD_8 pin. Use polled mode instead of gpio-keys because the GPIO interrupt controller support for Meson S4 SoC is not yet available upstream. Signed-off-by: Nick Xie Reviewed-by: Martin Blumenstingl Link: https://patch.msgid.link/20260228063750.701887-5-nick@khadas.com Signed-off-by: Neil Armstrong --- .../dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts b/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts index 0bd738c1e786..664d64a267f2 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts +++ b/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "meson-s4.dtsi" +#include #include / { @@ -44,6 +45,17 @@ emmc_pwrseq: emmc-pwrseq { reset-gpios = <&gpio GPIOB_9 GPIO_ACTIVE_LOW>; }; + gpio-keys-polled { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + power-button { + label = "power"; + linux,code = ; + gpios = <&gpio GPIOD_8 GPIO_ACTIVE_LOW>; + }; + }; + pwm-leds { compatible = "pwm-leds"; From 3535303d5df2be93a0a8c17621d14af39fc72e2f Mon Sep 17 00:00:00 2001 From: Ronald Claveau Date: Thu, 26 Mar 2026 10:59:12 +0100 Subject: [PATCH 006/665] arm64: dts: amlogic: t7: Add eMMC, SD card and SDIO pinctrl nodes These pinctrl nodes are required by the eMMC, SD card and SDIO drivers to configure pin muxing at runtime. - eMMC: control, 4-bit/8-bit data, data strobe and clock gate pins - SD card: data, clock, command and clock gate pins - SDIO: data, clock, command and clock gate pins Signed-off-by: Ronald Claveau Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260326-add-emmc-t7-vim4-v5-1-d3f182b48e9d@aliel.fr Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 98 +++++++++++++++++++++ 1 file changed, 98 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi index d523cbc0ed22..4a2220e59743 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi @@ -252,6 +252,104 @@ gpio: bank@4000 { #gpio-cells = <2>; gpio-ranges = <&periphs_pinctrl 0 0 157>; }; + + emmc_ctrl_pins: emmc-ctrl { + mux-0 { + groups = "emmc_cmd"; + function = "emmc"; + bias-pull-up; + }; + + mux-1 { + groups = "emmc_clk"; + function = "emmc"; + bias-disable; + }; + }; + + emmc_data_4b_pins: emmc-data-4b { + mux { + groups = "emmc_nand_d0", + "emmc_nand_d1", + "emmc_nand_d2", + "emmc_nand_d3"; + function = "emmc"; + bias-pull-up; + }; + }; + + emmc_data_8b_pins: emmc-data-8b { + mux { + groups = "emmc_nand_d0", + "emmc_nand_d1", + "emmc_nand_d2", + "emmc_nand_d3", + "emmc_nand_d4", + "emmc_nand_d5", + "emmc_nand_d6", + "emmc_nand_d7"; + function = "emmc"; + bias-pull-up; + }; + }; + + emmc_ds_pins: emmc-ds { + mux { + groups = "emmc_nand_ds"; + function = "emmc"; + bias-pull-down; + }; + }; + + emmc_clk_gate_pins: emmc-clk-gate { + mux { + groups = "GPIOB_8"; + function = "gpio_periphs"; + bias-pull-down; + }; + }; + + sdcard_pins: sdcard { + mux { + groups = "sdcard_d0", + "sdcard_d1", + "sdcard_d2", + "sdcard_d3", + "sdcard_clk", + "sdcard_cmd"; + function = "sdcard"; + bias-pull-up; + }; + }; + + sdcard_clk_gate_pins: sdcard-clk-gate { + mux { + groups = "GPIOC_4"; + function = "gpio_periphs"; + bias-pull-down; + }; + }; + + sdio_pins: sdio { + mux { + groups = "sdio_d0", + "sdio_d1", + "sdio_d2", + "sdio_d3", + "sdio_clk", + "sdio_cmd"; + function = "sdio"; + bias-pull-up; + }; + }; + + sdio_clk_gate_pins: sdio-clk-gate { + mux { + groups = "GPIOX_4"; + function = "gpio_periphs"; + bias-pull-up; + }; + }; }; gpio_intc: interrupt-controller@4080 { From a17be027dc5ccd51b99b5bc7b487ba9fbdc554e8 Mon Sep 17 00:00:00 2001 From: Sandie Cao Date: Tue, 21 Apr 2026 14:42:00 +0800 Subject: [PATCH 007/665] dt-bindings: riscv: spacemit: add deepcomputing,fml13v05 Document the compatible string for the Deepcomputing fml13v05. It's based on the SpacemiT K3 RISC-V SoC and is designed for the Framework Laptop 13 Chassis, which has (Framework) SKU FRANHQ0001. Acked-by: Conor Dooley Signed-off-by: Sandie Cao Reviewed-by: Troy Mitchell Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/20260421064200.1582367-1-sandie.cao@deepcomputing.io Signed-off-by: Yixun Lan --- Documentation/devicetree/bindings/riscv/spacemit.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml index b958b94a924d..af8030242bdc 100644 --- a/Documentation/devicetree/bindings/riscv/spacemit.yaml +++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml @@ -29,6 +29,7 @@ properties: - const: spacemit,k1 - items: - enum: + - deepcomputing,fml13v05 - spacemit,k3-pico-itx - const: spacemit,k3 From 448fedd56cdfa68c2e661b16a8dfc8f3c40a1bcf Mon Sep 17 00:00:00 2001 From: Sandie Cao Date: Tue, 21 Apr 2026 14:43:06 +0800 Subject: [PATCH 008/665] riscv: dts: spacemit: add DeepComputing FML13V05 board device tree The FML13V05 board from DeepComputing incorporates a SpacemiT K3 RISC-V SoC.It is a mainboard designed for the Framework Laptop 13 Chassis, which has (Framework) SKU FRANHQ0001. The FML13V05 board features: - SpacemiT K3 RISC-V SoC - LPDDR5 16GB or 32GB - eMMC 32GB ~128GB (Optional) - UFS 3.1 256G (Optional) - QSPI Flash - MicroSD Slot - PCIe-based Wi-Fi - 4 USB-C Ports - Port 1: PD 3.0 (65W Max), USB 3.2 Gen 1 - Port 2: PD 3.0 (65W Max), USB 3.2 Gen 1, DP 1.4 (4K@60Hz) - Port 3 & 4: USB 3.2 Gen 1 This minimal device tree enables booting into a serial console with UART output. Signed-off-by: Sandie Cao Reviewed-by: Troy Mitchell Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/20260421064306.1583888-1-sandie.cao@deepcomputing.io Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/Makefile | 1 + .../spacemit/k3-deepcomputing-fml13v05.dts | 31 +++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile index 7e2b87702571..acb993c452ba 100644 --- a/arch/riscv/boot/dts/spacemit/Makefile +++ b/arch/riscv/boot/dts/spacemit/Makefile @@ -4,4 +4,5 @@ dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-r2s.dtb dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb +dtb-$(CONFIG_ARCH_SPACEMIT) += k3-deepcomputing-fml13v05.dtb dtb-$(CONFIG_ARCH_SPACEMIT) += k3-pico-itx.dtb diff --git a/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts b/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts new file mode 100644 index 000000000000..b5d5112de358 --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2026 DeepComputing (HK) Limited + */ + +#include "k3.dtsi" +#include "k3-pinctrl.dtsi" + +/ { + model = "DeepComputing FML13V05"; + compatible = "deepcomputing,fml13v05", "spacemit,k3"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0"; + }; + + memory@100000000 { + device_type = "memory"; + reg = <0x1 0x00000000 0x4 0x00000000>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_0_cfg>; + status = "okay"; +}; From ece83d42785e12ab7690c0c13b416baf46a74063 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Tue, 7 Apr 2026 23:28:14 +0800 Subject: [PATCH 009/665] riscv: dts: spacemit: Enable i2c8 adapter for OrangePi RV2 The adapter is used to access the SpacemiT P1 PMIC present in this board. Tested-by: Vincent Legoll # OrangePi-RV2 Signed-off-by: Han Gao Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/d66f897b179271f508ac5352e52b1223f3bca5fb.1775575436.git.gaohan@iscas.ac.cn Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts index 7b7331cb3c72..57ec1cc32b03 100644 --- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts @@ -87,6 +87,12 @@ &pdma { status = "okay"; }; +&i2c8 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_cfg>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_2_cfg>; From c02c047b925c0ed101ec6834e1c07a53a45f98d4 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Tue, 7 Apr 2026 23:28:15 +0800 Subject: [PATCH 010/665] riscv: dts: spacemit: Define the P1 PMIC regulators for OrangePi RV2 Define the DC power input and the 4v power as fixed regulator supplies. Define the SpacemiT P1 PMIC voltage regulators and their constraints. Co-developed-by: Chukun Pan Signed-off-by: Chukun Pan Tested-by: Vincent Legoll # OrangePi-RV2 Signed-off-by: Han Gao Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/193370a69e1cc3e4d8c4eb57bfea208e29ac75d8.1775575436.git.gaohan@iscas.ac.cn Signed-off-by: Yixun Lan --- .../boot/dts/spacemit/k1-orangepi-rv2.dts | 131 ++++++++++++++++++ 1 file changed, 131 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts index 57ec1cc32b03..f7a1dadaa95f 100644 --- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts @@ -23,6 +23,25 @@ chosen { stdout-path = "serial0"; }; + vcc_5v0: regulator-vcc-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc4v0: regulator-vcc4v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc4v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; + vin-supply = <&vcc_5v0>; + }; + leds { compatible = "gpio-leds"; @@ -91,6 +110,118 @@ &i2c8 { pinctrl-names = "default"; pinctrl-0 = <&i2c8_cfg>; status = "okay"; + + pmic@41 { + compatible = "spacemit,p1"; + reg = <0x41>; + interrupts = <64>; + vin1-supply = <&vcc4v0>; + vin2-supply = <&vcc4v0>; + vin3-supply = <&vcc4v0>; + vin4-supply = <&vcc4v0>; + vin5-supply = <&vcc4v0>; + vin6-supply = <&vcc4v0>; + aldoin-supply = <&vcc4v0>; + dldoin1-supply = <&buck5>; + dldoin2-supply = <&buck5>; + + regulators { + buck1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck3_1v8: buck3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck4_3v3: buck4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck5: buck5 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck6 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + aldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + + aldo2 { + /* not connected */ + }; + + aldo3 { + /* not connected */ + }; + + aldo4 { + /* not connected */ + }; + + dldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + + dldo2 { + /* not connected */ + }; + + dldo3 { + /* not connected */ + }; + + dldo4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-always-on; + }; + + dldo5 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo6 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-always-on; + }; + + dldo7 { + /* not connected */ + }; + }; + }; }; &uart0 { From e3e433dd9aa04448f8f98d59359cab1340d994a3 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Tue, 7 Apr 2026 23:28:16 +0800 Subject: [PATCH 011/665] riscv: dts: spacemit: Enable USB3.0/PCIe on OrangePi RV2 Enable the DWC3 USB 3.0 controller and its associated usbphy2 on the OrangePi RV2 board. The board utilizes a Genesys Logic GL3523 USB3.0 hub. Define a 3.3v fixed voltage regulator for PCIe and enable PCIe and PHY-related Device Tree nodes for the OrangePi RV2. Co-developed-by: Chukun Pan Signed-off-by: Chukun Pan Tested-by: Vincent Legoll # OrangePi-RV2 Signed-off-by: Han Gao Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/8e397efb06efd9b02788df07f435ce153de05cd5.1775575436.git.gaohan@iscas.ac.cn Signed-off-by: Yixun Lan --- .../boot/dts/spacemit/k1-orangepi-rv2.dts | 80 +++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts index f7a1dadaa95f..3a829e3c9cbc 100644 --- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts @@ -23,6 +23,16 @@ chosen { stdout-path = "serial0"; }; + pcie_vcc3v3: regulator-pcie-vcc3v3 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio K1_GPIO(116) GPIO_ACTIVE_HIGH>; + regulator-name = "pcie_vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_5v0>; + }; + vcc_5v0: regulator-vcc-5v0 { compatible = "regulator-fixed"; regulator-name = "vcc_5v0"; @@ -42,6 +52,16 @@ vcc4v0: regulator-vcc4v0 { vin-supply = <&vcc_5v0>; }; + vcc5v0_usb30: regulator-vcc5v0-usb30 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; + regulator-name = "vcc5v0_usb30"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v0>; + }; + leds { compatible = "gpio-leds"; @@ -54,6 +74,10 @@ led1 { }; }; +&combo_phy { + status = "okay"; +}; + ð0 { phy-handle = <&rgmii0>; phy-mode = "rgmii-id"; @@ -224,8 +248,64 @@ dldo7 { }; }; +&pcie1_phy { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_3_cfg>; + status = "okay"; +}; + +&pcie1_port { + phys = <&pcie1_phy>; + vpcie3v3-supply = <&pcie_vcc3v3>; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie2_phy { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_4_cfg>; + status = "okay"; +}; + +&pcie2_port { + phys = <&pcie2_phy>; + vpcie3v3-supply = <&pcie_vcc3v3>; +}; + +&pcie2 { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_2_cfg>; status = "okay"; }; + +&usbphy2 { + status = "okay"; +}; + +&usb_dwc3 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + vbus-supply = <&vcc5v0_usb30>; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb5e3,610"; + reg = <0x1>; + peer-hub = <&hub_3_0>; + vdd-supply = <&vcc_5v0>; + }; + + hub_3_0: hub@2 { + compatible = "usb5e3,620"; + reg = <0x2>; + peer-hub = <&hub_2_0>; + vdd-supply = <&vcc_5v0>; + }; +}; From c9c008754abd66d48cb04a9045cc12714ce2d720 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 23 Apr 2026 01:36:27 +0200 Subject: [PATCH 012/665] dt-bindings: clock: renesas,cpg-clocks: Document ZT/ZTR trace clock on R-Mobile A1 Document the ZT trace bus and ZTR trace clocks on R-Mobile A1. These clocks supply the coresight tracing modules, PTM, TPIU, ETB and replicator. Without these clocks, coresight tracing can not be operated. While this does change the ABI, it does so by extending the existing clock-output-names, therefore if old software is used with new DT, the coresight tracing parts will likely fail to probe, otherwise if new software is used with an old DT, there is no impact. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260422233744.149872-2-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- .../devicetree/bindings/clock/renesas,cpg-clocks.yaml | 6 ++++-- include/dt-bindings/clock/r8a7740-clock.h | 2 ++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml index a0e09b7002f0..925ed35d6658 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml @@ -41,7 +41,7 @@ properties: clock-output-names: minItems: 3 - maxItems: 17 + maxItems: 19 renesas,mode: description: Board-specific settings of the MD_CK* bits on R-Mobile A1 @@ -123,6 +123,8 @@ allOf: - const: zb - const: m3 - const: cp + - const: ztr + - const: zt required: - renesas,mode @@ -240,6 +242,6 @@ examples: #clock-cells = <1>; clock-output-names = "system", "pllc0", "pllc1", "pllc2", "r", "usb24s", "i", "zg", "b", "m1", "hp", "hpp", - "usbp", "s", "zb", "m3", "cp"; + "usbp", "s", "zb", "m3", "cp", "ztr", "zt"; renesas,mode = <0x05>; }; diff --git a/include/dt-bindings/clock/r8a7740-clock.h b/include/dt-bindings/clock/r8a7740-clock.h index 1b3fdb39cc42..8a8816b2ff6a 100644 --- a/include/dt-bindings/clock/r8a7740-clock.h +++ b/include/dt-bindings/clock/r8a7740-clock.h @@ -24,6 +24,8 @@ #define R8A7740_CLK_ZB 14 #define R8A7740_CLK_M3 15 #define R8A7740_CLK_CP 16 +#define R8A7740_CLK_ZTR 17 +#define R8A7740_CLK_ZT 18 /* MSTP1 */ #define R8A7740_CLK_CEU21 28 From 63fd2f6aa402a105fa22ede6f3c35dafd64827a5 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Wed, 4 Mar 2026 23:00:42 +0200 Subject: [PATCH 013/665] arm64: dts: rockchip: Fix vdec register blocks order on RK3576 When building device trees for the RK3576 based boards, DTC shows the following complaint: rk3576.dtsi:1282.30-1304.5: Warning (simple_bus_reg): /soc/video-codec@27b00000: simple-bus unit address format error, expected "27b00100" Since the video decoder support for the aforementioned SoC in mainline driver and devicetrees hasn't been released yet (just landed in v7.0-rc1), fix the issue by providing the register blocks using the 'link,function,cache' listing, which follows the address-based order as shown in the vendor's datasheet and, implicitly, ensures the unit address points to the primary register range. Fixes: da0de806d8b4 ("arm64: dts: rockchip: Add the vdpu383 Video Decoder on rk3576") Signed-off-by: Cristian Ciocaltea Link: https://patch.msgid.link/20260304-vdec-reg-order-rk3576-v5-3-7006fad42c3a@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index 28175d8200d5..e12a2a0cfb89 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1281,10 +1281,10 @@ gpu: gpu@27800000 { vdec: video-codec@27b00000 { compatible = "rockchip,rk3576-vdec"; - reg = <0x0 0x27b00100 0x0 0x500>, - <0x0 0x27b00000 0x0 0x100>, + reg = <0x0 0x27b00000 0x0 0x100>, + <0x0 0x27b00100 0x0 0x500>, <0x0 0x27b00600 0x0 0x100>; - reg-names = "function", "link", "cache"; + reg-names = "link", "function", "cache"; interrupts = ; clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru HCLK_RKVDEC>, <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_CORE>, From b481c11cd20a114c4df35f3b1ecd28b05e622067 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Wed, 4 Mar 2026 23:00:43 +0200 Subject: [PATCH 014/665] arm64: dts: rockchip: Update vdec register blocks order on RK3588 With the introduction of the RK3588 SoC, three register blocks have been provided for the video decoder unit instead of just one, which are further referenced in the vendor's datasheet by 'link table', 'function' and 'cache'. The former is present at the top of the listing, starting at video decoder unit base address, but the binding got this wrong initially, i.e. the 'function' block got listed before the 'link' one. Since the video decoder support for the aforementioned SoC in mainline driver and devicetrees hasn't been released yet (just landed in v7.0-rc1), address the problem by providing the register blocks for vdec0 & vdec1 nodes using the 'link,function,cache' listing, which ensures the unit address points to the primary register range. This aligns with a similar fix for RK3576, where DTC also complained about the bus address format. Fixes: f61731bd6062 ("arm64: dts: rockchip: Add the vdpu381 Video Decoders on RK3588") Signed-off-by: Cristian Ciocaltea Link: https://patch.msgid.link/20260304-vdec-reg-order-rk3576-v5-4-7006fad42c3a@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 4fb8888c281c..d4dc057e31f0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1355,10 +1355,10 @@ vepu121_3_mmu: iommu@fdbac800 { vdec0: video-codec@fdc38000 { compatible = "rockchip,rk3588-vdec"; - reg = <0x0 0xfdc38100 0x0 0x500>, - <0x0 0xfdc38000 0x0 0x100>, + reg = <0x0 0xfdc38000 0x0 0x100>, + <0x0 0xfdc38100 0x0 0x500>, <0x0 0xfdc38600 0x0 0x100>; - reg-names = "function", "link", "cache"; + reg-names = "link", "function", "cache"; interrupts = ; clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_CORE>, <&cru CLK_RKVDEC0_HEVC_CA>; @@ -1387,10 +1387,10 @@ vdec0_mmu: iommu@fdc38700 { vdec1: video-codec@fdc40000 { compatible = "rockchip,rk3588-vdec"; - reg = <0x0 0xfdc40100 0x0 0x500>, - <0x0 0xfdc40000 0x0 0x100>, + reg = <0x0 0xfdc40000 0x0 0x100>, + <0x0 0xfdc40100 0x0 0x500>, <0x0 0xfdc40600 0x0 0x100>; - reg-names = "function", "link", "cache"; + reg-names = "link", "function", "cache"; interrupts = ; clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_CORE>, <&cru CLK_RKVDEC1_HEVC_CA>; From 6598ed3586a4b1cc79423666e66b9861631a6c7e Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Tue, 21 Apr 2026 11:45:05 +0200 Subject: [PATCH 015/665] arm64: dts: rockchip: fix Ethernet PHY not found on PX30 Cobra When not passing the PHY ID with an ethernet-phy-idX.Y compatible property, the MDIO bus will attempt to auto-detect the PHY by reading its registers and then probing the appropriate driver. For this to work, the PHY needs to be in a working state. Unfortunately, the net subsystem doesn't control the PHY reset GPIO when attempting to auto-detect the PHY. This means the PHY needs to be in a working state when entering the Linux kernel. This historically has been the case for this device, but only because the bootloader was taking care of initializing the Ethernet controller even when not using it. We're attempting to support the removal of the network stack in the bootloader, which means the Linux kernel will be entered with the PHY still in reset and now Ethernet doesn't work anymore. The devices in the field only ever had a TI DP83825, so let's simply bypass the auto-detection mechanism entirely by passing the appropriate PHY IDs via the compatible. Fixes: bb510ddc9d3e ("arm64: dts: rockchip: add px30-cobra base dtsi and board variants") Signed-off-by: Quentin Schulz Link: https://patch.msgid.link/20260421-px30-eth-phy-v2-1-68c375b120fd@cherry.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/px30-cobra.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/px30-cobra.dtsi b/arch/arm64/boot/dts/rockchip/px30-cobra.dtsi index b7e669d8ba4d..add917af5de7 100644 --- a/arch/arm64/boot/dts/rockchip/px30-cobra.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-cobra.dtsi @@ -397,7 +397,7 @@ &io_domains { &mdio { dp83825: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id2000.a140"; reg = <0x0>; pinctrl-names = "default"; pinctrl-0 = <&phy_rst>; From ae653cb854f36d1555681ce70ca3d80d0ec73516 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Tue, 21 Apr 2026 11:45:06 +0200 Subject: [PATCH 016/665] arm64: dts: rockchip: fix Ethernet PHY not found on PX30 Ringneck When not passing the PHY ID with an ethernet-phy-idX.Y compatible property, the MDIO bus will attempt to auto-detect the PHY by reading its registers and then probing the appropriate driver. For this to work, the PHY needs to be in a working state. Unfortunately, the net subsystem doesn't control the PHY reset GPIO when attempting to auto-detect the PHY. This means the PHY needs to be in a working state when entering the Linux kernel. This historically has been the case for this device, but only because the bootloader was taking care of initializing the Ethernet controller even when not using it. We're attempting to support the removal of the network stack in the bootloader, which means the Linux kernel will be entered with the PHY still in reset and now Ethernet doesn't work anymore. The devices in the field only ever had a TI DP83825, so let's simply bypass the auto-detection mechanism entirely by passing the appropriate PHY IDs via the compatible. Note that this is only an issue since commit e463625af7f9 ("arm64: dts: rockchip: move reset to dedicated eth-phy node on ringneck") as before that commit the reset was done by the MAC controller before starting the MDIO auto-detection mechanism, via the snps,reset-* properties. Cc: stable@vger.kernel.org Fixes: e463625af7f9 ("arm64: dts: rockchip: move reset to dedicated eth-phy node on ringneck") Signed-off-by: Quentin Schulz Link: https://patch.msgid.link/20260421-px30-eth-phy-v2-2-68c375b120fd@cherry.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi b/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi index 4203b335a263..973b4c5880e2 100644 --- a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi @@ -344,7 +344,7 @@ &io_domains { &mdio { dp83825: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id2000.a140"; reg = <0x0>; pinctrl-names = "default"; pinctrl-0 = <&phy_rst>; From c83c4a09d4c01c91d6c52d6d4d77a06892a3e83b Mon Sep 17 00:00:00 2001 From: Diederik de Haas Date: Wed, 1 Apr 2026 15:11:38 +0200 Subject: [PATCH 017/665] arm64: dts: rockchip: Fix gmac0 reset pin for NanoPi R5S According to the NanoPi R5S 2204 schematic on page 6, GPIO0_C4 is for GMAC0_INT/PMEB_GPIO0_C4, while GPIO0_C5 is for GMAC0_RSTn_GPIO0_C5. While the 'reset-gpios' property was set correctly, the corresponding pinctrl didn't match that. Next to fixing the pinctrl definition, also change the node name and phandle to match what is used in the schematic. Fixes: c6629b9a6738 ("arm64: dts: rockchip: Add FriendlyElec Nanopi R5S") Signed-off-by: Diederik de Haas Link: https://patch.msgid.link/20260401131551.734456-2-diederik@cknow-tech.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts index 718d1a2da8e5..90ce6f0e1dcf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts @@ -98,7 +98,7 @@ &mdio0 { rgmii_phy0: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; - pinctrl-0 = <ð_phy0_reset_pin>; + pinctrl-0 = <&gmac0_rstn_gpio0_c5_pin>; pinctrl-names = "default"; }; }; @@ -132,8 +132,8 @@ &pcie3x2 { &pinctrl { gmac0 { - eth_phy0_reset_pin: eth-phy0-reset-pin { - rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + gmac0_rstn_gpio0_c5_pin: gmac0-rstn-gpio0-c5-pin { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; }; }; From e4f7054e819eece6fd83072ff2dcefc7a36224c0 Mon Sep 17 00:00:00 2001 From: Sten-Silver Ots Date: Tue, 14 Apr 2026 00:52:49 +0300 Subject: [PATCH 018/665] arm64: dts: rockchip: Enable the NPU on rk3588-rock-5-itx This commit enables the NPU on Radxa Rock 5 ITX board. The regulator vdd_npu_s0 was already in place and since the NPUs power domain supply is now described remove the always-on property from the regulator. Signed-off-by: Sten-Silver Ots Link: https://patch.msgid.link/20260413215301.4656-1-stensilver@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588-rock-5-itx.dts | 35 ++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts index f7dd01d6fa0a..1ff786251eb0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts @@ -433,7 +433,6 @@ vdd_npu_s0: regulator@42 { reg = <0x42>; fcs,suspend-voltage-selector = <1>; regulator-name = "vdd_npu_s0"; - regulator-always-on; regulator-boot-on; regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; @@ -695,6 +694,10 @@ &pd_gpu { domain-supply = <&vdd_gpu_s0>; }; +&pd_npu { + domain-supply = <&vdd_npu_s0>; +}; + &pinctrl { hym8563 { rtc_int: rtc-int { @@ -814,6 +817,36 @@ dp1_hpd: dp1-hpd { }; }; +&rknn_core_0 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_1 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_2 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_mmu_0 { + status = "okay"; +}; + +&rknn_mmu_1 { + status = "okay"; +}; + +&rknn_mmu_2 { + status = "okay"; +}; + &pwm14 { pinctrl-names = "default"; pinctrl-0 = <&pwm14m1_pins>; From 44a024778eeba377d7ac882d15e27ba784e0f647 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 4 Apr 2026 16:50:08 -0300 Subject: [PATCH 019/665] ARM: dts: rockchip: Remove invalid properies from rk3288-veyron-analog-audio The 'rockchip,mic-det-gpios' property is not documented anywhere. The 'rockchip,hp-det-gpios' property is not a valid property for the 'rockchip,rockchip-audio-max98090' compatible. Remove both invalid properties. Signed-off-by: Fabio Estevam Link: https://patch.msgid.link/20260404195008.1951910-1-festevam@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rk3288-veyron-analog-audio.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-analog-audio.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron-analog-audio.dtsi index 51208d161d65..25c7c0667856 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-veyron-analog-audio.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-analog-audio.dtsi @@ -14,8 +14,6 @@ sound { rockchip,model = "VEYRON-I2S"; rockchip,i2s-controller = <&i2s>; rockchip,audio-codec = <&max98090>; - rockchip,hp-det-gpios = <&gpio6 RK_PA5 GPIO_ACTIVE_HIGH>; - rockchip,mic-det-gpios = <&gpio6 RK_PB3 GPIO_ACTIVE_LOW>; rockchip,headset-codec = <&headsetcodec>; rockchip,hdmi-codec = <&hdmi>; }; From 8df9160f6a50dbdae8ec287d429efc9d2d9001bd Mon Sep 17 00:00:00 2001 From: Midgy BALON Date: Fri, 27 Mar 2026 10:11:28 +0100 Subject: [PATCH 020/665] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers. This chip is currently modeled only as a fixed regulator (vcc3v3_pi6c_03), with no clock output representation. The PI6C20100 is a clock generator, not a power supply. Model it properly as a gated-fixed-clock, following the pattern established for the Rock 5 ITX and other boards with similar PCIe clock buffer chips. The gated-fixed-clock node references the regulator as its vdd-supply, allowing the regulator to be enabled on demand. Remove the regulator-always-on and regulator-boot-on properties from vcc3v3_pi6c_03 since the clock framework will manage the regulator lifecycle via vdd-supply. The pcie3x2 node is updated to include the pipe and reference clocks, matching the approach used in rk3588-rock-5-itx.dts. Assisted-by: Claude:claude-3-opus Signed-off-by: Midgy BALON Link: https://patch.msgid.link/20260327091128.2458-1-midgy971@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3568-rock-3b.dts | 20 ++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts index 69001e453732..149a5306bb03 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts @@ -56,7 +56,15 @@ led-0 { }; }; - /* pi6c pcie clock generator */ + /* PI6C20100 PCIe reference clock buffer */ + pcie30_refclk: pcie-clock-generator { + compatible = "gated-fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "pcie30_refclk"; + vdd-supply = <&vcc3v3_pi6c_03>; + }; + vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 { compatible = "regulator-fixed"; enable-active-high; @@ -64,8 +72,6 @@ vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 { pinctrl-names = "default"; pinctrl-0 = <&pcie_pwren_h>; regulator-name = "vcc3v3_pi6c_03"; - regulator-always-on; - regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; startup-delay-us = <10000>; @@ -553,6 +559,14 @@ &pcie30phy { }; &pcie3x2 { + clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, + <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, + <&cru CLK_PCIE30X2_AUX_NDFT>, + <&cru CLK_PCIE30X2_PIPE_DFT>, + <&pcie30_refclk>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux", + "pipe", "ref"; pinctrl-names = "default"; pinctrl-0 = <&pcie30x2m1_pins>; reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; From 803d2de23a9703705c1ed73b0c9f57e8db2c9c75 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Fri, 27 Mar 2026 15:21:06 +0100 Subject: [PATCH 021/665] MAINTAINERS: Add Rockchip keyword matching Add keyword based matching for 'ARM/Rockchip SoC support'. This will match rockchip, Rockchip, RockChip and ROCKCHIP separated by any whitespace character or underscores. The goal is to match arm64 defconfig patches, which should go through the Rockchip tree as they right now only match the LKML and thus are easily lost. The keyword matching is quite good for this, since it also applies to the commit message and the config options itself might not give any hint about being relevant for Rockchip. Signed-off-by: Sebastian Reichel Link: https://patch.msgid.link/20260327-maintainers-rockchip-keyword-v1-1-7f4634f761a6@collabora.com Signed-off-by: Heiko Stuebner --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 2fb1c75afd16..729247415495 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3425,6 +3425,8 @@ F: drivers/i2c/busses/i2c-rk3x.c F: drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c F: sound/soc/rockchip/ N: rockchip +K: \b[Rr]ock[Cc]hip\b +K: (?:\b|_)ROCKCHIP(?:\b|_) ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES M: Krzysztof Kozlowski From 7cd8b37304be367106a02d4d902294e9bea3f45d Mon Sep 17 00:00:00 2001 From: Gray Huang Date: Wed, 25 Mar 2026 13:46:09 +0800 Subject: [PATCH 022/665] arm64: dts: rockchip: Add PMIC support for Khadas Edge 2L Add RK806 PMIC support for the Khadas Edge 2L board. Assign the corresponding PMIC regulators (vdd_cpu_lit_s0 and vdd_cpu_big_s0) to the little and big CPU clusters to enable proper power management and CPU frequency scaling. Signed-off-by: Gray Huang Link: https://patch.msgid.link/20260325054614.1497147-2-gray.huang@wesion.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3576-khadas-edge-2l.dts | 410 ++++++++++++++++++ 1 file changed, 410 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts b/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts index 68630379af63..627d56764c61 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts @@ -17,6 +17,416 @@ aliases { chosen { stdout-path = "serial0:1500000n8"; }; + + vcc_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc_sys>; + }; + + vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_2v0_pldo_s3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + vin-supply = <&vcc_sys>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&i2c1 { + status = "okay"; + + rk806: pmic@23 { + compatible = "rockchip,rk806"; + reg = <0x23>; + interrupt-parent = <&gpio0>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + system-power-controller; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + rk806_dvs1_slp: dvs1-slp-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun1"; + }; + + rk806_dvs1_pwrdn: dvs1-pwrdn-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun2"; + }; + + rk806_dvs1_rst: dvs1-rst-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun3"; + }; + + rk806_dvs2_slp: dvs2-slp-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun1"; + }; + + rk806_dvs2_pwrdn: dvs2-pwrdn-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun2"; + }; + + rk806_dvs2_rst: dvs2-rst-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun3"; + }; + + rk806_dvs2_dvs: dvs2-dvs-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun4"; + }; + + rk806_dvs2_gpio: dvs2-gpio-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun5"; + }; + + rk806_dvs3_slp: dvs3-slp-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun1"; + }; + + rk806_dvs3_pwrdn: dvs3-pwrdn-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun2"; + }; + + rk806_dvs3_rst: dvs3-rst-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun3"; + }; + + rk806_dvs3_dvs: dvs3-dvs-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun4"; + }; + + rk806_dvs3_gpio: dvs3-gpio-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun5"; + }; + + regulators { + vdd_cpu_big_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: dcdc-reg2 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_npu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vcc_3v3_s3: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_gpu_s0: dcdc-reg5 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vddq_ddr_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_logic_s0: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <800000>; + regulator-name = "vdd_logic_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo2_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdda_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v75_hdmi_s0: nldo-reg3 { + regulator-boot-on; + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; + regulator-name = "vdda0v75_hdmi_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdda_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; }; &sdhci { From 6d72e0d07145449a33678624436c73da09873c43 Mon Sep 17 00:00:00 2001 From: Gray Huang Date: Wed, 25 Mar 2026 13:46:11 +0800 Subject: [PATCH 023/665] arm64: dts: rockchip: Enable GPU for Khadas Edge 2L Enable the Mali GPU node on the Khadas Edge 2L board. Assign the corresponding regulator to the mali-supply property to ensure proper power management and dynamic voltage scaling (DVFS). Signed-off-by: Gray Huang Link: https://patch.msgid.link/20260325054614.1497147-4-gray.huang@wesion.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts b/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts index 627d56764c61..59e5e7e25bee 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts @@ -56,6 +56,11 @@ &cpu_b0 { cpu-supply = <&vdd_cpu_big_s0>; }; +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + &i2c1 { status = "okay"; From e9ec83fbc3d46b39fe92a0cbda4795ece30717f5 Mon Sep 17 00:00:00 2001 From: Gray Huang Date: Wed, 25 Mar 2026 13:46:12 +0800 Subject: [PATCH 024/665] arm64: dts: rockchip: Add HDMI and VOP support for Khadas Edge 2L Enable the Video Output Processor (VOP) and the HDMI TX controller to support HDMI display output on the Khadas Edge 2L. Also, enable the associated HDMI PHY. Signed-off-by: Gray Huang Link: https://patch.msgid.link/20260325054614.1497147-5-gray.huang@wesion.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3576-khadas-edge-2l.dts | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts b/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts index 59e5e7e25bee..c39c7f90b6fb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts @@ -4,6 +4,7 @@ #include #include +#include #include "rk3576.dtsi" / { @@ -18,6 +19,17 @@ chosen { stdout-path = "serial0:1500000n8"; }; + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + vcc_sys: regulator-vcc5v0-sys { compatible = "regulator-fixed"; regulator-name = "vcc_sys"; @@ -61,6 +73,30 @@ &gpu { status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&hdptxphy { + status = "okay"; +}; + &i2c1 { status = "okay"; @@ -447,3 +483,18 @@ &sdhci { &uart0 { status = "okay"; }; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; From 6a1405b315166dd282a78025e0ea2fc9a9a7b619 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Sun, 19 Apr 2026 18:24:15 -0500 Subject: [PATCH 025/665] dt-bindings: arm: altera: document the Agilex7-M devkit The Agilex7-M is a rebranded version of the original Agilex SoC. The Agilex7-M SoC has the same core peripherals as the Agilex device. This change is to document the Agilex7m devkit which has the Agilex7-M device. The Agilex7-M SoC supports DDR4, DDR5, LPDDR5, PCIE 5.0(x16), but not QSPI. Also, now that Altera has separated from Intel, use the "altr" company prefix. Acked-by: Conor Dooley Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/arm/altera.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 206686f3eebc..4b096e52243e 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -115,6 +115,12 @@ properties: - intel,socfpga-agilex5-socdk-nand - const: intel,socfpga-agilex5 + - description: Agilex7m boards + items: + - enum: + - altr,socfpga-agilex7m-socdk + - const: altr,socfpga-agilex7m + - description: SoCFPGA VT items: - const: altr,socfpga-vt From 66764673e09b3b9c0e9dc1f785ac9cb7b0e0183a Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Sun, 19 Apr 2026 18:24:16 -0500 Subject: [PATCH 026/665] arm64: dts: socfpga: agilex7m: Add SoCFPGA Agilex7-M devkit The Agilex7-M devkit contains an Agilex7M SoC, which is a newly branded version of the original Agilex SoC. The Agilex7M core peripherals are identical to the Agilex SoC. We can re-use the socfpga_agilex.dtsi for this devkit. The Agilex7-M devkit supports PCIE 5.0(x16), DDR4, DDR5, LPDDR5 and does not have QSPI. Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/Makefile | 1 + .../boot/dts/intel/socfpga_agilex7m_socdk.dts | 103 ++++++++++++++++++ 2 files changed, 104 insertions(+) create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex7m_socdk.dts diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile index 33fcc55d0cb9..088a03b89c99 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -8,5 +8,6 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \ socfpga_agilex5_socdk_013b.dtb \ socfpga_agilex5_socdk_modular.dtb \ socfpga_agilex5_socdk_nand.dtb \ + socfpga_agilex7m_socdk.dtb \ socfpga_n5x_socdk.dtb dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex7m_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex7m_socdk.dts new file mode 100644 index 000000000000..c1f270b9334c --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex7m_socdk.dts @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2026 Altera Corporation + +#include "socfpga_agilex.dtsi" + +/ { + model = "Altera SoCFPGA Agilex7-M SoCDK"; + compatible = "altr,socfpga-agilex7m-socdk", + "altr,socfpga-agilex7m"; + + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + led-0 { + label = "hps_led0"; + gpios = <&portb 20 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + label = "hps_led1"; + gpios = <&portb 19 GPIO_ACTIVE_HIGH>; + }; + + led-2 { + label = "hps_led2"; + gpios = <&portb 21 GPIO_ACTIVE_HIGH>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0x80000000 0 0>; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <&phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@4 { + reg = <4>; + + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <900>; /* 0ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + }; + }; +}; + +&mmc { + status = "okay"; + cap-sd-highspeed; + broken-cd; + bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; +}; + +&osc1 { + clock-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; From b5a0814a2cbb91e9376937f6b7de6ddff5eae14a Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Thu, 23 Apr 2026 12:48:47 -0500 Subject: [PATCH 027/665] ARM: dts: socfpga: remove the reg property in the pmu The Cortex-A9 PMU accesses the hardware via system coprocessor registers, not memory-mapped I/O. The driver does not parse or use a 'reg' property from the device tree, so we can remove the reg from the DTS. This change fixes this dtbs_check warning: (arm,cortex-a9-pmu): 'reg' does not match any of the regexes Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/intel/socfpga/socfpga.dtsi | 4 +--- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 4 +--- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi index 5dc8d33e8ad7..98cb4cad2a10 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi @@ -37,13 +37,11 @@ cpu1: cpu@1 { }; }; - pmu: pmu@ff111000 { + pmu: pmu { compatible = "arm,cortex-a9-pmu"; interrupt-parent = <&intc>; interrupts = <0 176 4>, <0 177 4>; interrupt-affinity = <&cpu0>, <&cpu1>; - reg = <0xff111000 0x1000>, - <0xff113000 0x1000>; }; intc: interrupt-controller@fffed000 { diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi index a53a94678df2..ba4c0ca89788 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -29,13 +29,11 @@ cpu1: cpu@1 { }; }; - pmu: pmu@ff111000 { + pmu: pmu { compatible = "arm,cortex-a9-pmu"; interrupt-parent = <&intc>; interrupts = <0 124 4>, <0 125 4>; interrupt-affinity = <&cpu0>, <&cpu1>; - reg = <0xff111000 0x1000>, - <0xff113000 0x1000>; }; intc: interrupt-controller@ffffd000 { From 47d4dc90181c8ffa9ebcbd058e312873a46aeaca Mon Sep 17 00:00:00 2001 From: Alexey Klimov Date: Wed, 25 Mar 2026 00:26:32 +0000 Subject: [PATCH 028/665] arm64: dts: exynos850: Add syscon-poweroff node Without poweroff node Exynos850-based board continue to draw current (around ~60 mA with my test setup) after poweroff. Kernel also reports different lockup problems and RCU stalls warnings continuosly after last kernel messages about hardware being switched off. Turns out we missed a write to PMU's PS_HOLD_CONTROL (PMU + 0x30c) register that actually switches the SoC off. Add poweroff node that implements this. With this change the current draw after power off is in range of few milliampers and lockup messages are no more. Signed-off-by: Alexey Klimov Link: https://patch.msgid.link/20260325-exynos850-poweroff-v1-1-34c19c06e74d@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos850.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index cb55015c8dce..3881f573ec08 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -215,6 +215,13 @@ pmu_system_controller: system-controller@11860000 { compatible = "samsung,exynos850-pmu", "syscon"; reg = <0x11860000 0x10000>; + poweroff: syscon-poweroff { + compatible = "syscon-poweroff"; + offset = <0x30c>; /* PS_HOLD_CONTROL */ + mask = <0x00000100>; + value = <0x0>; + }; + reboot: syscon-reboot { compatible = "syscon-reboot"; regmap = <&pmu_system_controller>; From 402e845f9dff3f6f4bf5ff801a07301c05d4cd83 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Wed, 25 Mar 2026 00:43:55 +0800 Subject: [PATCH 029/665] arm64: dts: allwinner: sun50i-h616: Add SRAM nodes The H616 SoC has a video engine, and two SRAM regions needed by it. Add the SRAM regions to the dtsi file. The video engine will be added in a separate change. Signed-off-by: Jernej Skrabec [wens@kernel.org: Add VE SRAM region, commit message, and split into two] Reviewed-by: Jernej Skrabec Link: https://patch.msgid.link/20260324164357.1607247-8-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 28 ++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index bf054869e78b..b116d3c12881 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -182,12 +182,38 @@ syscon: syscon@3000000 { #size-cells = <1>; ranges; - sram_c: sram@28000 { + /* SRAM C */ + sram@28000 { compatible = "mmio-sram"; reg = <0x00028000 0x30000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x00028000 0x30000>; + + /* + * 0x0 ~ 0x20000 is partial alias of VE SRAM below. + * 0x20000 ~ 0x2ffff is (partial?) alias of DE SRAM. + * However the whole region is toggled together. + */ + sram_c: sram-section@0 { + compatible = "allwinner,sun50i-h616-sram-c", + "allwinner,sun50i-a64-sram-c"; + reg = <0x00000 0x30000>; + }; + }; + + /* VE SRAM */ + sram@1a00000 { + compatible = "mmio-sram"; + reg = <0x01a00000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x01a00000 0x200000>; + + ve_sram: sram-section@0 { + compatible = "allwinner,sun50i-h616-ve-sram"; + reg = <0x000000 0x200000>; + }; }; }; From 63b35a29d7ad2cafb0076f8b002b30fb74df053a Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 25 Feb 2026 13:23:21 +0100 Subject: [PATCH 030/665] dt-bindings: net: bluetooth: qualcomm: Fix WCN6855 regulator names Commit 5f4f954bba12 ("dt-bindings: bluetooth: bring the HW description closer to reality for wcn6855") changed the vddrfa1p7-supply to 1p8 for whatever reason. The schematics footprint for this chip definitely says 7 on the input leg and the driver still expects 1p7. Bring it back. Fixes: 5f4f954bba12 ("dt-bindings: bluetooth: bring the HW description closer to reality for wcn6855") Reviewed-by: Krzysztof Kozlowski Reviewed-by: Abel Vesa Reviewed-by: Bartosz Golaszewski Acked-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260225-topic-wcn6855_pmu_dtbdings-v3-1-576ec5c4e631@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/net/bluetooth/qcom,wcn6855-bt.yaml | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/net/bluetooth/qcom,wcn6855-bt.yaml b/Documentation/devicetree/bindings/net/bluetooth/qcom,wcn6855-bt.yaml index 45630067d3c8..0beda26ae8bb 100644 --- a/Documentation/devicetree/bindings/net/bluetooth/qcom,wcn6855-bt.yaml +++ b/Documentation/devicetree/bindings/net/bluetooth/qcom,wcn6855-bt.yaml @@ -50,9 +50,6 @@ properties: description: VDD_RFA_1P7 supply regulator handle deprecated: true - vddrfa1p8-supply: - description: VDD_RFA_1P8 supply regulator handle - vddrfacmn-supply: description: VDD_RFA_CMN supply regulator handle @@ -68,7 +65,7 @@ required: - vddbtcmx-supply - vddrfa0p8-supply - vddrfa1p2-supply - - vddrfa1p8-supply + - vddrfa1p7-supply - vddrfacmn-supply - vddwlcx-supply - vddwlmx-supply @@ -91,7 +88,7 @@ examples: vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>; vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>; vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; vddwlmx-supply = <&vreg_pmu_wlmx_0p8>; From 493cb869874cd301c370adf9a3f9577942c4f0f1 Mon Sep 17 00:00:00 2001 From: Yedaya Katsman Date: Sat, 14 Mar 2026 23:46:23 +0200 Subject: [PATCH 031/665] arm64: dts: qcom: sm6125-xiaomi-laurel-sprout: Enable MDSS and add panel MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the MDSS nodes and add supplies and bindings for the Samsung S6E8FCO DSI controller for the M1906F9 panel. The ldo and iovcc gpio pins boot up with a current of 16 mA, but they work fine with 2mA, so I used that. mdss_dsi0_phy is powered by VDD_MX, see power-domains in sm6125.dtsi Co-developed-by: Kamil GoÅ‚da Signed-off-by: Kamil GoÅ‚da Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Yedaya Katsman Link: https://lore.kernel.org/r/20260314-panel-patches-v4-3-1ecbb2c0c3c8@gmail.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/sm6125-xiaomi-laurel-sprout.dts | 94 +++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts index 97f64cb5d570..b9d9439e230b 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts @@ -95,6 +95,33 @@ ts_vdd_supply: regulator-ts-vdd { pinctrl-names = "default"; }; + panel_vdd_1p8: regulator-panel-vdd { + compatible = "regulator-fixed"; + regulator-name = "panel_vdd_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + vin-supply = <&vreg_l9a>; + + enable-active-high; + gpio = <&tlmm 26 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&panel_vdd_1p8_en>; + pinctrl-names = "default"; + }; + + panel_vci_3p0: regulator-panel-vci { + compatible = "regulator-fixed"; + regulator-name = "panel_vci_3p0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + + enable-active-high; + gpio = <&tlmm 124 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&panel_vci_3p0_en>; + pinctrl-names = "default"; + }; + thermal-zones { rf-pa0-thermal { thermal-sensors = <&pm6125_adc_tm 0>; @@ -162,6 +189,45 @@ touchscreen@38 { }; }; +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l18a>; + status = "okay"; + + panel@0 { + compatible = "samsung,s6e8fco-m1906f9"; + reg = <0>; + + reset-gpios = <&tlmm 90 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&mdss_default>; + pinctrl-1 = <&mdss_sleep>; + pinctrl-names = "default", "sleep"; + + vdd-supply = <&panel_vdd_1p8>; + vci-supply = <&panel_vci_3p0>; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&panel_in>; +}; + + +&mdss_dsi0_phy { + status = "okay"; +}; + &pm6125_adc { pinctrl-names = "default"; pinctrl-0 = <&camera_flash_therm &emmc_ufs_therm>; @@ -426,6 +492,13 @@ &sdhc_2 { &tlmm { gpio-reserved-ranges = <22 2>, <28 6>; + panel_vdd_1p8_en: panel-vdd-default-state { + pins = "gpio26"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + ts_vdd_en: ts-vdd-default-state { pins = "gpio83"; function = "gpio"; @@ -460,6 +533,27 @@ ts_int_suspend: pmx-ts-int-suspend-state { drive-strength = <2>; bias-pull-down; }; + + mdss_default: mdss-default-state { + pins = "gpio90"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + mdss_sleep: mdss-sleep-state { + pins = "gpio90"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + panel_vci_3p0_en: panel-vci-default-state { + pins = "gpio124"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; }; &ufs_mem_hc { From c17e220946675232d383620ed9cff6685735ec48 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Mon, 23 Mar 2026 12:01:12 +0200 Subject: [PATCH 032/665] arm64: dts: qcom: hamoa: Fix OPP tables for all DisplayPort controllers According to internal documentation, the corners specific for each rate from the DP link clock are: - LOWSVS_D1 -> 19.2 MHz - LOWSVS -> 270 MHz - SVS -> 540 MHz (594 MHz in case of DP3) - SVS_L1 -> 594 MHz - NOM -> 810 MHz - NOM_L1 -> 810 MHz - TURBO -> 810 MHz So fix all tables for each of the four controllers according to the documentation, but since DP0 through DP2 have the same entries in their tables, lets drop the DP1 and DP2 and have all of them share the DP0 table instead. However keep a separate table for the DP3 as it is different for the SVS, compared to the rest of the controllers. The 19.2 MHz @ LOWSVS_D1 isn't needed as it's not an actual working frequency and the controller will never select it. So remove it. Cc: stable@vger.kernel.org # v6.9+ Fixes: 1940c25eaa63 ("arm64: dts: qcom: x1e80100: Add display nodes") Suggested-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20260323-hamoa-fix-dp3-opp-table-v3-1-a823776bd1b0@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 77 +++++------------------------ 1 file changed, 12 insertions(+), 65 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 051dee076416..4ba751a65142 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -5744,18 +5744,18 @@ mdss_dp0_out: endpoint { mdss_dp0_opp_table: opp-table { compatible = "operating-points-v2"; - opp-162000000 { - opp-hz = /bits/ 64 <162000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - opp-270000000 { opp-hz = /bits/ 64 <270000000>; - required-opps = <&rpmhpd_opp_svs>; + required-opps = <&rpmhpd_opp_low_svs>; }; opp-540000000 { opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-594000000 { + opp-hz = /bits/ 64 <594000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; @@ -5796,7 +5796,7 @@ mdss_dp1: displayport-controller@ae98000 { <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; - operating-points-v2 = <&mdss_dp1_opp_table>; + operating-points-v2 = <&mdss_dp0_opp_table>; power-domains = <&rpmhpd RPMHPD_MMCX>; @@ -5829,30 +5829,6 @@ mdss_dp1_out: endpoint { }; }; }; - - mdss_dp1_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-162000000 { - opp-hz = /bits/ 64 <162000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-270000000 { - opp-hz = /bits/ 64 <270000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-540000000 { - opp-hz = /bits/ 64 <540000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-810000000 { - opp-hz = /bits/ 64 <810000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; }; mdss_dp2: displayport-controller@ae9a000 { @@ -5885,7 +5861,7 @@ mdss_dp2: displayport-controller@ae9a000 { <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; - operating-points-v2 = <&mdss_dp2_opp_table>; + operating-points-v2 = <&mdss_dp0_opp_table>; power-domains = <&rpmhpd RPMHPD_MMCX>; @@ -5917,30 +5893,6 @@ mdss_dp2_out: endpoint { }; }; }; - - mdss_dp2_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-162000000 { - opp-hz = /bits/ 64 <162000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-270000000 { - opp-hz = /bits/ 64 <270000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-540000000 { - opp-hz = /bits/ 64 <540000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-810000000 { - opp-hz = /bits/ 64 <810000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; }; mdss_dp3: displayport-controller@aea0000 { @@ -6004,21 +5956,16 @@ mdss_dp3_out: endpoint { mdss_dp3_opp_table: opp-table { compatible = "operating-points-v2"; - opp-162000000 { - opp-hz = /bits/ 64 <162000000>; + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; required-opps = <&rpmhpd_opp_low_svs>; }; - opp-270000000 { - opp-hz = /bits/ 64 <270000000>; + opp-594000000 { + opp-hz = /bits/ 64 <594000000>; required-opps = <&rpmhpd_opp_svs>; }; - opp-540000000 { - opp-hz = /bits/ 64 <540000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - opp-810000000 { opp-hz = /bits/ 64 <810000000>; required-opps = <&rpmhpd_opp_nom>; From 1f820571ca7c64d3fd5bd9bf653b571cb3350703 Mon Sep 17 00:00:00 2001 From: Alexander Koskovich Date: Mon, 23 Mar 2026 13:54:42 +0000 Subject: [PATCH 033/665] arm64: dts: qcom: milos: Reduce rmtfs_mem size to 2.5MiB The rmtfs_mem region is currently sized at 6MiB but the default for milos downstream is 2.5MiB. This causes remoteproc crashes on devices that expect the smaller size: modem_ac.c:281:Access Control Error: Could not protect the region specified:Start:e1f00000 End:e2180000, PID:1 Reduce the default to 2.5MiB to match the QCOM downstream config, and override the size for FP6. Fixes: d9d59d105f98 ("arm64: dts: qcom: Add initial Milos dtsi") Reviewed-by: Luca Weiss Reviewed-by: Konrad Dybcio Signed-off-by: Alexander Koskovich Link: https://lore.kernel.org/r/20260323-asteroids-v2-1-1a35fa9e178a@pm.me Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 5 +++++ arch/arm64/boot/dts/qcom/milos.dtsi | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts index c1899db46e71..5dc7c950e60d 100644 --- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts @@ -786,6 +786,11 @@ &remoteproc_wpss { status = "okay"; }; +&rmtfs_mem { + /* Increase the size from 2.5 MiB to 6 MiB */ + reg = <0x0 0xe1f00000 0x0 0x600000>; +}; + &sdhc_2 { cd-gpios = <&tlmm 65 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi index 4a64a98a434b..347afce18924 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -642,7 +642,7 @@ cpusys_vm_mem: cpusys-vm-region@e0600000 { rmtfs_mem: rmtfs@e1f00000 { compatible = "qcom,rmtfs-mem"; - reg = <0x0 0xe1f00000 0x0 0x600000>; + reg = <0x0 0xe1f00000 0x0 0x280000>; no-map; qcom,client-id = <1>; From 93be926a7f6dc89657d3e8488f353893841039ce Mon Sep 17 00:00:00 2001 From: Alexander Koskovich Date: Mon, 23 Mar 2026 13:54:53 +0000 Subject: [PATCH 034/665] dt-bindings: arm: qcom: Add the Nothing Phone (3a) Document the Milos-based Nothing Phone (3a) smartphone. Acked-by: Krzysztof Kozlowski Signed-off-by: Alexander Koskovich Link: https://lore.kernel.org/r/20260323-asteroids-v2-2-1a35fa9e178a@pm.me Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index b4943123d2e4..24164ba70b6f 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -79,6 +79,7 @@ properties: - items: - enum: - fairphone,fp6 + - nothing,asteroids - const: qcom,milos - items: From edbf03c9fb5ff72f8e7974b35f7ee2d9ae7cb371 Mon Sep 17 00:00:00 2001 From: Alexander Koskovich Date: Mon, 23 Mar 2026 13:55:05 +0000 Subject: [PATCH 035/665] arm64: dts: qcom: Add the Nothing Phone (3a) Add a devicetree for the Nothing Phone (3a) smartphone, which is based on the Milos/SM7635 SoC. Supported functionality as of this initial submission: * Camera flash/torch LED * Debug UART * Glyph LEDs (AW20036) * PMIC-GLINK (Charger, Fuel gauge, USB-C mode switching) * Assistant Key, Power Button, Volume Keys * Regulators (PM7550, PM8550VS, PMR735B) * Remoteprocs (ADSP, CDSP, MPSS, WPSS) * USB (USB2 + FSA4480) Reviewed-by: Konrad Dybcio Signed-off-by: Alexander Koskovich Link: https://lore.kernel.org/r/20260323-asteroids-v2-3-1a35fa9e178a@pm.me Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/milos-nothing-asteroids.dts | 964 ++++++++++++++++++ 2 files changed, 965 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/milos-nothing-asteroids.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 4ba8e7306419..169cc9b9ccd3 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -56,6 +56,7 @@ lemans-evk-ifp-mezzanine-dtbs := lemans-evk.dtb lemans-evk-ifp-mezzanine.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-ifp-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) += mahua-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += milos-fairphone-fp6.dtb +dtb-$(CONFIG_ARCH_QCOM) += milos-nothing-asteroids.dtb dtb-$(CONFIG_ARCH_QCOM) += monaco-arduino-monza.dtb dtb-$(CONFIG_ARCH_QCOM) += monaco-evk.dtb diff --git a/arch/arm64/boot/dts/qcom/milos-nothing-asteroids.dts b/arch/arm64/boot/dts/qcom/milos-nothing-asteroids.dts new file mode 100644 index 000000000000..7393978926e4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/milos-nothing-asteroids.dts @@ -0,0 +1,964 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/dts-v1/; + +#define PMIV0104_SID 7 + +#include +#include +#include + +#include "milos.dtsi" +#include "pm7550.dtsi" +#include "pm8550vs.dtsi" +#include "pmiv0104.dtsi" /* PMIV0102 */ +#include "pmk8550.dtsi" /* PMK7635 */ +#include "pmr735b.dtsi" + +/ { + model = "Nothing Phone (3a)"; + compatible = "nothing,asteroids", "qcom,milos"; + chassis-type = "handset"; + + aliases { + serial0 = &uart5; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0:115200n8"; + + framebuffer0: framebuffer@e3940000 { + compatible = "simple-framebuffer"; + reg = <0x0 0xe3940000 0x0 (2392 * 1080 * 4)>; + width = <1080>; + height = <2392>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + panel = <&panel>; + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + clocks = <&gcc GCC_DISP_HF_AXI_CLK>; + + /* Dummy panel for simple-framebuffer dimension info */ + panel: dummy-panel { + compatible = "boe,bf068mwm-td0"; + height-mm = <157>; + width-mm = <71>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&assist_default>, <&volume_up_default>; + pinctrl-names = "default"; + + key-assist { + gpios = <&tlmm 71 GPIO_ACTIVE_LOW>; + label = "Assistant"; + linux,code = ; + }; + + key-volume-up { + gpios = <&pm7550_gpios 6 GPIO_ACTIVE_LOW>; + label = "Volume Up"; + linux,code = ; + }; + }; + + pmic-glink { + compatible = "qcom,milos-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 131 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + + data-role = "dual"; + power-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_sbu: endpoint { + remote-endpoint = <&fsa4480_sbu_mux>; + }; + }; + }; + }; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops@81f20000 { + compatible = "ramoops"; + reg = <0x0 0x81f20000 0x0 0x400000>; + console-size = <0x200000>; + mem-type = <2>; + pmsg-size = <0x200000>; + }; + + /* + * ABL is powering down display and controller if this node is + * not named exactly "splash_region". + */ + splash_region@e3940000 { + reg = <0x0 0xe3940000 0x0 0x2b00000>; + no-map; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm7550-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s1b>; + vdd-l2-l3-supply = <&vreg_s3b>; + vdd-l4-l5-supply = <&vreg_s2b>; + vdd-l7-supply = <&vreg_s1b>; + vdd-l8-supply = <&vreg_s1b>; + vdd-l9-l10-supply = <&vreg_s1b>; + vdd-l11-supply = <&vreg_s1b>; + vdd-l12-l14-supply = <&vreg_bob>; + vdd-l13-l16-supply = <&vreg_bob>; + vdd-l15-l17-l18-l19-l20-l21-l22-l23-supply = <&vreg_bob>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-bob-supply = <&vph_pwr>; + + qcom,pmic-id = "b"; + + vreg_s1b: smps1 { + regulator-name = "vreg_s1b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2080000>; + regulator-initial-mode = ; + }; + + vreg_s2b: smps2 { + regulator-name = "vreg_s2b"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1408000>; + regulator-initial-mode = ; + }; + + vreg_s3b: smps3 { + regulator-name = "vreg_s3b"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <1040000>; + regulator-initial-mode = ; + }; + + vreg_s4b: smps4 { + regulator-name = "vreg_s4b"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = ; + }; + + vreg_l1b: ldo1 { + regulator-name = "vreg_l1b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b: ldo2 { + regulator-name = "vreg_l2b"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l3b: ldo3 { + regulator-name = "vreg_l3b"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l4b: ldo4 { + regulator-name = "vreg_l4b"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l5b: ldo5 { + regulator-name = "vreg_l5b"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l7b: ldo7 { + regulator-name = "vreg_l7b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l8b: ldo8 { + regulator-name = "vreg_l8b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9b: ldo9 { + regulator-name = "vreg_l9b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l10b: ldo10 { + regulator-name = "vreg_l10b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l11b: ldo11 { + regulator-name = "vreg_l11b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12b: ldo12 { + regulator-name = "vreg_l12b"; + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <2952000>; + regulator-initial-mode = ; + }; + + vreg_l13b: ldo13 { + regulator-name = "vreg_l13b"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l14b: ldo14 { + regulator-name = "vreg_l14b"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l15b: ldo15 { + regulator-name = "vreg_l15b"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l16b: ldo16 { + regulator-name = "vreg_l16b"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l17b: ldo17 { + regulator-name = "vreg_l17b"; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + }; + + vreg_l18b: ldo18 { + regulator-name = "vreg_l18b"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l19b: ldo19 { + regulator-name = "vreg_l19b"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l20b: ldo20 { + regulator-name = "vreg_l20b"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l21b: ldo21 { + regulator-name = "vreg_l21b"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l22b: ldo22 { + regulator-name = "vreg_l22b"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-initial-mode = ; + }; + + vreg_l23b: ldo23 { + regulator-name = "vreg_l23b"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s3b>; + vdd-l2-supply = <&vreg_s3b>; + vdd-l3-supply = <&vreg_s3b>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + qcom,pmic-id = "c"; + + vreg_s3c: smps3 { + regulator-name = "vreg_s3c"; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1120000>; + regulator-initial-mode = ; + }; + + vreg_s4c: smps4 { + regulator-name = "vreg_s4c"; + regulator-min-microvolt = <352000>; + regulator-max-microvolt = <812000>; + regulator-initial-mode = ; + }; + + vreg_s5c: smps5 { + regulator-name = "vreg_s5c"; + regulator-min-microvolt = <540000>; + regulator-max-microvolt = <884000>; + regulator-initial-mode = ; + }; + + vreg_s6c: smps6 { + regulator-name = "vreg_s6c"; + regulator-min-microvolt = <352000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = ; + }; + + vreg_l1c: ldo1 { + regulator-name = "vreg_l1c"; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = ; + }; + + vreg_l2c: ldo2 { + regulator-name = "vreg_l2c"; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <650000>; + regulator-initial-mode = ; + }; + + vreg_l3c: ldo3 { + regulator-name = "vreg_l3c"; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmr735b-rpmh-regulators"; + + vdd-l1-l2-supply = <&vreg_s3b>; + vdd-l3-supply = <&vreg_s3b>; + vdd-l4-supply = <&vreg_s1b>; + vdd-l5-supply = <&vreg_s2b>; + vdd-l7-l8-supply = <&vreg_s2b>; + vdd-l9-supply = <&vreg_s3b>; + vdd-l10-supply = <&vreg_s1b>; + vdd-l11-supply = <&vreg_s3b>; + vdd-l12-supply = <&vreg_s3b>; + + qcom,pmic-id = "f"; + + vreg_l1f: ldo1 { + regulator-name = "vreg_l1f"; + regulator-min-microvolt = <852000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = ; + }; + + vreg_l2f: ldo2 { + regulator-name = "vreg_l2f"; + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + regulator-initial-mode = ; + }; + + vreg_l3f: ldo3 { + regulator-name = "vreg_l3f"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l4f: ldo4 { + regulator-name = "vreg_l4f"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = ; + }; + + vreg_l5f: ldo5 { + regulator-name = "vreg_l5f"; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + }; + + vreg_l7f: ldo7 { + regulator-name = "vreg_l7f"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = ; + }; + + vreg_l9f: ldo9 { + regulator-name = "vreg_l9f"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = ; + }; + + vreg_l10f: ldo10 { + regulator-name = "vreg_l10f"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l11f: ldo11 { + regulator-name = "vreg_l11f"; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <864000>; + regulator-initial-mode = ; + }; + + vreg_l12f: ldo12 { + regulator-name = "vreg_l12f"; + regulator-min-microvolt = <480000>; + regulator-max-microvolt = <884000>; + regulator-initial-mode = ; + }; + }; +}; + +&dispcc { + /* Disable for now so simple-framebuffer continues working */ + status = "disabled"; +}; + +&gcc { + protected-clocks = , , + , , + , , + , , + , , + , ; +}; + +&i2c7 { + clock-frequency = <400000>; + + status = "okay"; + + led-controller@3a { + compatible = "awinic,aw20036"; + reg = <0x3a>; + #address-cells = <1>; + #size-cells = <0>; + + enable-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>; + + led@0 { + reg = <0x0>; + color = ; + function = "glyph-1"; + function-enumerator = <0>; + led-max-microamp = <6560>; + }; + + led@1 { + reg = <0x1>; + color = ; + function = "glyph-1"; + function-enumerator = <1>; + led-max-microamp = <6560>; + }; + + led@2 { + reg = <0x2>; + color = ; + function = "glyph-1"; + function-enumerator = <2>; + led-max-microamp = <6560>; + }; + + led@3 { + reg = <0x3>; + color = ; + function = "glyph-1"; + function-enumerator = <3>; + led-max-microamp = <6560>; + }; + + led@4 { + reg = <0x4>; + color = ; + function = "glyph-1"; + function-enumerator = <4>; + led-max-microamp = <6560>; + }; + + led@5 { + reg = <0x5>; + color = ; + function = "glyph-1"; + function-enumerator = <5>; + led-max-microamp = <6560>; + }; + + led@6 { + reg = <0x6>; + color = ; + function = "glyph-1"; + function-enumerator = <6>; + led-max-microamp = <6560>; + }; + + led@7 { + reg = <0x7>; + color = ; + function = "glyph-2"; + function-enumerator = <0>; + led-max-microamp = <6560>; + }; + + led@8 { + reg = <0x8>; + color = ; + function = "glyph-3"; + function-enumerator = <0>; + led-max-microamp = <6560>; + }; + + led@9 { + reg = <0x9>; + color = ; + function = "glyph-3"; + function-enumerator = <1>; + led-max-microamp = <6560>; + }; + + led@a { + reg = <0xa>; + color = ; + function = "glyph-3"; + function-enumerator = <2>; + led-max-microamp = <6560>; + }; + + led@b { + reg = <0xb>; + color = ; + function = "glyph-3"; + function-enumerator = <3>; + led-max-microamp = <6560>; + }; + + led@c { + reg = <0xc>; + color = ; + function = "glyph-1"; + function-enumerator = <7>; + led-max-microamp = <6560>; + }; + + led@d { + reg = <0xd>; + color = ; + function = "glyph-1"; + function-enumerator = <8>; + led-max-microamp = <6560>; + }; + + led@e { + reg = <0xe>; + color = ; + function = "glyph-1"; + function-enumerator = <9>; + led-max-microamp = <6560>; + }; + + led@f { + reg = <0xf>; + color = ; + function = "glyph-1"; + function-enumerator = <10>; + led-max-microamp = <6560>; + }; + + led@10 { + reg = <0x10>; + color = ; + function = "glyph-1"; + function-enumerator = <11>; + led-max-microamp = <6560>; + }; + + led@11 { + reg = <0x11>; + color = ; + function = "glyph-1"; + function-enumerator = <12>; + led-max-microamp = <6560>; + }; + + led@12 { + reg = <0x12>; + color = ; + function = "glyph-1"; + function-enumerator = <13>; + led-max-microamp = <6560>; + }; + + led@13 { + reg = <0x13>; + color = ; + function = "glyph-2"; + function-enumerator = <1>; + led-max-microamp = <6560>; + }; + + led@14 { + reg = <0x14>; + color = ; + function = "glyph-2"; + function-enumerator = <2>; + led-max-microamp = <6560>; + }; + + led@15 { + reg = <0x15>; + color = ; + function = "glyph-3"; + function-enumerator = <4>; + led-max-microamp = <6560>; + }; + + led@16 { + reg = <0x16>; + color = ; + function = "glyph-3"; + function-enumerator = <5>; + led-max-microamp = <6560>; + }; + + led@17 { + reg = <0x17>; + color = ; + function = "glyph-3"; + function-enumerator = <6>; + led-max-microamp = <6560>; + }; + + led@18 { + reg = <0x18>; + color = ; + function = "glyph-1"; + function-enumerator = <14>; + led-max-microamp = <6560>; + }; + + led@19 { + reg = <0x19>; + color = ; + function = "glyph-1"; + function-enumerator = <15>; + led-max-microamp = <6560>; + }; + + led@1a { + reg = <0x1a>; + color = ; + function = "glyph-1"; + function-enumerator = <16>; + led-max-microamp = <6560>; + }; + + led@1b { + reg = <0x1b>; + color = ; + function = "glyph-1"; + function-enumerator = <17>; + led-max-microamp = <6560>; + }; + + led@1c { + reg = <0x1c>; + color = ; + function = "glyph-1"; + function-enumerator = <18>; + led-max-microamp = <6560>; + }; + + led@1d { + reg = <0x1d>; + color = ; + function = "glyph-1"; + function-enumerator = <19>; + led-max-microamp = <6560>; + }; + + led@1e { + reg = <0x1e>; + color = ; + function = "glyph-2"; + function-enumerator = <3>; + led-max-microamp = <6560>; + }; + + led@1f { + reg = <0x1f>; + color = ; + function = "glyph-2"; + function-enumerator = <4>; + led-max-microamp = <6560>; + }; + + led@20 { + reg = <0x20>; + color = ; + function = "glyph-3"; + function-enumerator = <7>; + led-max-microamp = <6560>; + }; + + led@21 { + reg = <0x21>; + color = ; + function = "glyph-3"; + function-enumerator = <8>; + led-max-microamp = <6560>; + }; + + led@22 { + reg = <0x22>; + color = ; + function = "glyph-3"; + function-enumerator = <9>; + led-max-microamp = <6560>; + }; + + led@23 { + reg = <0x23>; + color = ; + function = "glyph-3"; + function-enumerator = <10>; + led-max-microamp = <6560>; + }; + }; + + typec-mux@42 { + compatible = "fcs,fsa4480"; + reg = <0x42>; + + vcc-supply = <&vph_pwr>; + + mode-switch; + orientation-switch; + + port { + fsa4480_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; + }; + }; + }; +}; + +&pm7550_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <1>, <4>; + led-max-microamp = <350000>; + flash-max-microamp = <1500000>; + flash-max-timeout-us = <400000>; + }; +}; + +&pm7550_gpios { + volume_up_default: volume-up-default-state { + pins = "gpio6"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = <1>; + bias-pull-up; + }; +}; + +&pm8550vs_c { + status = "okay"; +}; + +&pmiv0104_eusb2_repeater { + vdd18-supply = <&vreg_l7b>; + vdd3-supply = <&vreg_l17b>; + + qcom,tune-res-fsdif = /bits/ 8 <0x5>; + qcom,tune-usb2-amplitude = /bits/ 8 <0x8>; + qcom,tune-usb2-disc-thres = /bits/ 8 <0x7>; + qcom,tune-usb2-preem = /bits/ 8 <0x6>; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/milos/nothing/asteroids/adsp.mbn", + "qcom/milos/nothing/asteroids/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/milos/nothing/asteroids/cdsp.mbn", + "qcom/milos/nothing/asteroids/cdsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/milos/nothing/asteroids/modem.mbn"; + + status = "okay"; +}; + +&remoteproc_wpss { + firmware-name = "qcom/milos/nothing/asteroids/wpss.mbn"; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <13 1>, /* Display */ + <63 2>; /* WLAN UART */ + + assist_default: assist-default-state { + pins = "gpio71"; + function = "gpio"; + bias-pull-up; + }; +}; + +&trusted_apps_mem { + reg = <0x0 0xe9500000 0x0 0x5500000>; +}; + +/* + * UART_RX and UART_TX are routed to test points on board, not + * available over USB. + */ +&uart5 { + status = "okay"; +}; + +&usb_1 { + /* USB 2.0 only, HW does not support USB 3.x */ + qcom,select-utmi-as-pipe-clk; + + status = "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l2b>; + vdda12-supply = <&vreg_l4b>; + + phys = <&pmiv0104_eusb2_repeater>; + + status = "okay"; +}; From 244e064bc8ce848d40fe13451b6096a66b2bbdb2 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 25 Feb 2026 13:23:22 +0100 Subject: [PATCH 036/665] arm64: dts: qcom: qcs615-ride: Fix BT RFA supply name Fix up the supply name to align with bindings. Reviewed-by: Abel Vesa Reviewed-by: Bartosz Golaszewski Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260225-topic-wcn6855_pmu_dtbdings-v3-2-576ec5c4e631@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index 7e05f873194a..831002789838 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -610,7 +610,7 @@ bluetooth { vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>; vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; }; }; From d28f68b052780b945c35996d02adf2426ed0bff7 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 25 Feb 2026 13:23:23 +0100 Subject: [PATCH 037/665] arm64: dts: qcom: sc8280xp-crd: Fix BT RFA supply name Fix up the supply name to align with bindings. Reviewed-by: Abel Vesa Reviewed-by: Bartosz Golaszewski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260225-topic-wcn6855_pmu_dtbdings-v3-3-576ec5c4e631@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index c53e00cae465..dcdeefd28728 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -787,7 +787,7 @@ bluetooth { vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>; vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; }; }; From fa99d3af7edb8acd735e861446477afd64007af7 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 25 Feb 2026 13:23:24 +0100 Subject: [PATCH 038/665] arm64: dts: qcom: sc8280xp-gaokun3: Fix BT RFA supply name Fix up the supply name to align with bindings. Reviewed-by: Abel Vesa Reviewed-by: Bartosz Golaszewski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260225-topic-wcn6855_pmu_dtbdings-v3-4-576ec5c4e631@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts index 9819454abe13..f3c00be67081 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts @@ -1122,7 +1122,7 @@ bluetooth { vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>; vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; max-speed = <3200000>; }; From de1a7dc3ccda556bef52185ae1d65ebb900b2925 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 25 Feb 2026 13:23:25 +0100 Subject: [PATCH 039/665] arm64: dts: qcom: sc8280xp-x13s: Fix BT RFA supply name Fix up the supply name to align with bindings. Reviewed-by: Abel Vesa Reviewed-by: Bartosz Golaszewski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260225-topic-wcn6855_pmu_dtbdings-v3-5-576ec5c4e631@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index d84ca010ab9d..abd9c5a67b9f 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -1331,7 +1331,7 @@ bluetooth { vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>; vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; max-speed = <3200000>; }; From a25cd984f4078cb772179787cf78790bbcc2c543 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 25 Feb 2026 13:23:26 +0100 Subject: [PATCH 040/665] arm64: dts: qcom: sc8280xp-blackrock: Fix BT RFA supply name Fix up the supply name to align with bindings. Reviewed-by: Abel Vesa Reviewed-by: Bartosz Golaszewski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260225-topic-wcn6855_pmu_dtbdings-v3-6-576ec5c4e631@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts index 00bbeeef6f14..125af356e24b 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts @@ -976,7 +976,7 @@ bluetooth { vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>; vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; max-speed = <3200000>; }; From 557a49f764306ccf8155ca19970be78d90f8d3de Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 25 Feb 2026 13:23:27 +0100 Subject: [PATCH 041/665] arm64: dts: qcom: sm8450-hdk: Fix BT RFA supply name Fix up the supply name to align with bindings. Reviewed-by: Abel Vesa Reviewed-by: Bartosz Golaszewski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260225-topic-wcn6855_pmu_dtbdings-v3-7-576ec5c4e631@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 268ae0cd642a..b37998cd9a2c 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -1172,7 +1172,7 @@ bluetooth { vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>; vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; }; }; From e5a38ea7633853433295106650d008c1428d4d0e Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 25 Feb 2026 13:23:28 +0100 Subject: [PATCH 042/665] arm64: dts: qcom: x1-omnibook-x14: Fix BT RFA supply name Fix up the supply name to align with bindings. Reviewed-by: Abel Vesa Reviewed-by: Bartosz Golaszewski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260225-topic-wcn6855_pmu_dtbdings-v3-8-576ec5c4e631@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi b/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi index b773a4976d1b..02708f23a865 100644 --- a/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi @@ -1452,7 +1452,7 @@ bluetooth { vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>; vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; }; }; From 8be58b9b8a10ac276d4058c66ebd6b2b9e5aa683 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 25 Feb 2026 13:23:29 +0100 Subject: [PATCH 043/665] arm64: dts: qcom: x1-zenbook-a14: Fix BT RFA supply name Fix up the supply name to align with bindings. Reviewed-by: Abel Vesa Reviewed-by: Bartosz Golaszewski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260225-topic-wcn6855_pmu_dtbdings-v3-9-576ec5c4e631@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi b/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi index 22470a97e1e3..7f5860d2b6cc 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi +++ b/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi @@ -128,7 +128,7 @@ bluetooth { vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>; vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>; vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; vddwlmx-supply = <&vreg_pmu_wlmx_0p8>; From d859095bcafc4c5e26c551350d2327aeb2e08e59 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 25 Feb 2026 13:23:30 +0100 Subject: [PATCH 044/665] arm64: dts: qcom: lemans-ride-common: Fix up WCN power grid Make the dt checker happy by filling out the required properties in line with the schematics. Reviewed-by: Abel Vesa Reviewed-by: Bartosz Golaszewski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260225-topic-wcn6855_pmu_dtbdings-v3-10-576ec5c4e631@oss.qualcomm.com [bjorn: Remove reference to dropped 12V supply] Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/lemans-ride-common.dtsi | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi index 31bd00546d55..679e045a6d49 100644 --- a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi @@ -53,6 +53,16 @@ vreg_3p0: vreg-3p0-regulator { regulator-max-microvolt = <3000000>; }; + vreg_3p3: vreg-3p3-regulator { + compatible = "regulator-fixed"; + regulator-name = "VREG_3P3"; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + vreg_conn_1p8: vreg_conn_1p8 { compatible = "regulator-fixed"; regulator-name = "vreg_conn_1p8"; @@ -69,6 +79,22 @@ vreg_conn_pa: vreg_conn_pa { gpio = <&pmm8654au_1_gpios 6 GPIO_ACTIVE_HIGH>; }; + /* + * TODO: These two regulators are actually part of the removable M.2 + * card and not the mainboard. Need to describe this differently. + * Functionally it works correctly, because all we need to do is to + * turn on the actual 3.3V supply above. + */ + vreg_wcn_0p95: vreg-wcn-0p95-regulator { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_3p3>; + }; + wcn6855-pmu { compatible = "qcom,wcn6855-pmu"; @@ -78,6 +104,8 @@ wcn6855-pmu { vddio-supply = <&vreg_conn_pa>; vddaon-supply = <&vreg_l2c>; vddpmu-supply = <&vreg_conn_1p8>; + vddpmumx-supply = <&vreg_wcn_0p95>; + vddpmucx-supply = <&vreg_wcn_0p95>; vddrfa0p95-supply = <&vreg_l2c>; vddrfa1p3-supply = <&vreg_l6e>; vddrfa1p9-supply = <&vreg_s5a>; @@ -956,6 +984,8 @@ bluetooth { vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; }; }; From cbdf1a61dde22c226a776d60ea5bff260b94f653 Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Tue, 31 Mar 2026 15:44:35 -0400 Subject: [PATCH 045/665] arm64: dts: qcom: sdm670: label the camss ports instead of endpoints Endpoints cannot be pre-defined since commit dcf6fb89e6f7 ("media: qcom: camss: remove a check for unavailable CAMSS endpoint") was applied, probing all endpoint nodes and requiring them to have a remote. There is no sensible remote in the SoC devicetree because camera sensors are board-specific. The ports are meant to be extended by a board devicetree in order to define fully configured endpoints and connect the ports to camera sensors. For nodes that are only meaningful if extended, labels are usually assigned. Label these ports so they can be extended directly. Reviewed-by: Vladimir Zapolskiy Reviewed-by: Bryan O'Donoghue Signed-off-by: Richard Acayan Link: https://lore.kernel.org/r/20260331194437.41041-2-mailingradian@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index c195c79c1c85..1613c66f92b3 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -1787,28 +1787,16 @@ ports { #address-cells = <1>; #size-cells = <0>; - port@0 { + camss_port0: port@0 { reg = <0>; - - camss_endpoint0: endpoint { - status = "disabled"; - }; }; - port@1 { + camss_port1: port@1 { reg = <1>; - - camss_endpoint1: endpoint { - status = "disabled"; - }; }; - port@2 { + camss_port2: port@2 { reg = <2>; - - camss_endpoint2: endpoint { - status = "disabled"; - }; }; }; }; From 86695909eab6bfa577bf68c615dbe852ba9c8197 Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Tue, 31 Mar 2026 15:44:36 -0400 Subject: [PATCH 046/665] arm64: dts: qcom: sdm670: add camera mclk pins The camera subsystem is added for the SoC common devicetree, but the mclk pins should also be common across the SoC. Add the mclk pins for the cameras. Suggested-by: Konrad Dybcio Link: https://lore.kernel.org/r/5135823c-f2e4-4873-9e3a-9d190cac0113@oss.qualcomm.com Reviewed-by: Vladimir Zapolskiy Reviewed-by: Bryan O'Donoghue Reviewed-by: David Heidelberg Reviewed-by: Konrad Dybcio Signed-off-by: Richard Acayan Link: https://lore.kernel.org/r/20260331194437.41041-3-mailingradian@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index 1613c66f92b3..e13ced9479b7 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -1207,6 +1207,34 @@ tlmm: pinctrl@3400000 { gpio-ranges = <&tlmm 0 0 151>; wakeup-parent = <&pdc>; + cam_mclk0_default: cam-mclk0-default-state { + pins = "gpio13"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam_mclk1_default: cam-mclk1-default-state { + pins = "gpio14"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam_mclk2_default: cam-mclk2-default-state { + pins = "gpio15"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam_mclk3_default: cam-mclk3-default-state { + pins = "gpio16"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + cci0_default: cci0-default-state { pins = "gpio17", "gpio18"; function = "cci_i2c"; From 8d3a34d7890faa4d968b16e29c5c80e559291fd2 Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Tue, 31 Mar 2026 15:44:37 -0400 Subject: [PATCH 047/665] arm64: dts: qcom: sdm670-google-sargo: add imx355 front camera The Sony IMX355 is the front camera on the Pixel 3a, mounted in portrait mode. It is connected to CSIPHY1 and CCI I2C1, and uses MCLK2. Add support for it. Co-developed-by: Robert Mader Signed-off-by: Robert Mader Signed-off-by: Richard Acayan Reviewed-by: Bryan O'Donoghue Reviewed-by: Vladimir Zapolskiy Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260331194437.41041-4-mailingradian@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm670-google-sargo.dts | 100 ++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts index ed55646ca419..eba2f3792dd0 100644 --- a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts +++ b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts @@ -172,6 +172,34 @@ vreg_s2b_1p05: vreg-s2b-regulator { regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; }; + + cam_front_ldo: cam-front-ldo-regulator { + compatible = "regulator-fixed"; + regulator-name = "cam_front_ldo"; + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + regulator-enable-ramp-delay = <135>; + + gpios = <&pm660l_gpios 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&cam_front_ldo_pin>; + pinctrl-names = "default"; + }; + + cam_vio_ldo: cam-vio-ldo-regulator { + compatible = "regulator-fixed"; + regulator-name = "cam_vio_ldo"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <233>; + + gpios = <&pm660_gpios 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&cam_vio_pin>; + pinctrl-names = "default"; + }; }; &apps_rsc { @@ -392,6 +420,64 @@ vreg_bob: bob { }; }; +&camss { + vdda-phy-supply = <&vreg_l1a_1p225>; + vdda-pll-supply = <&vreg_s6a_0p87>; + + status = "okay"; +}; + +&camss_port1 { + camss_endpoint1: endpoint { + data-lanes = <0 1 2 3>; + remote-endpoint = <&cam_front_endpoint>; + }; +}; + +&cci { + pinctrl-0 = <&cci1_default>; + pinctrl-1 = <&cci1_sleep>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&cci_i2c1 { + camera@1a { + compatible = "sony,imx355"; + reg = <0x1a>; + + clocks = <&camcc CAM_CC_MCLK2_CLK>; + + /* + * The sensor can accept a 24 MHz clock, but 19.2 MHz has + * better driver compatibility. + */ + assigned-clocks = <&camcc CAM_CC_MCLK2_CLK>; + assigned-clock-rates = <19200000>; + + reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; + + avdd-supply = <&cam_front_ldo>; + dvdd-supply = <&cam_front_ldo>; + dovdd-supply = <&cam_vio_ldo>; + + pinctrl-0 = <&cam_mclk2_default>; + pinctrl-names = "default"; + + rotation = <270>; + orientation = <0>; + + port { + cam_front_endpoint: endpoint { + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <360000000>; + remote-endpoint = <&camss_endpoint1>; + }; + }; + }; +}; + &gcc { protected-clocks = , , @@ -490,6 +576,14 @@ &pm660_charger { status = "okay"; }; +&pm660_gpios { + cam_vio_pin: cam-vio-state { + pins = "gpio13"; + function = "normal"; + power-source = <0>; + }; +}; + &pm660_rradc { status = "okay"; }; @@ -508,6 +602,12 @@ led-0 { }; &pm660l_gpios { + cam_front_ldo_pin: cam-front-state { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + }; + vol_up_pin: vol-up-state { pins = "gpio7"; function = "normal"; From a4f6959661f0c8542e5a89aaaef27fc4ac9408a6 Mon Sep 17 00:00:00 2001 From: Petr Hodina Date: Thu, 2 Apr 2026 00:39:35 +0200 Subject: [PATCH 048/665] arm64: dts: qcom: sdm845-xiaomi-beryllium: Introduce framebuffer Add framebuffer for early console and u-boot support. Signed-off-by: Petr Hodina Signed-off-by: David Heidelberg Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260402-beryllium-fb-v4-1-46170004da28@ixit.cz Signed-off-by: Bjorn Andersson --- .../dts/qcom/sdm845-xiaomi-beryllium-common.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index 1298485c4214..a6ee3dd171de 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -39,6 +39,22 @@ aliases { serial1 = &uart6; }; + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer { + compatible = "simple-framebuffer"; + memory-region = <&cont_splash_mem>; + + format = "a8r8g8b8"; + stride = <(1080 * 4)>; + height = <2246>; + width = <1080>; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; From b379bb1470d864659ae9522b72f241a15255dce6 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Thu, 2 Apr 2026 00:39:36 +0200 Subject: [PATCH 049/665] arm64: dts: qcom: sdm845-oneplus: Drop address from framebuffer node This node has no 'reg' property, so it shouldn't have a unit address (after '@') either Fixes: b0d5c96e860c ("arm64: dts: qcom: sdm845-oneplus: Add framebuffer") Reviewed-by: Dmitry Baryshkov Signed-off-by: David Heidelberg Link: https://lore.kernel.org/r/20260402-beryllium-fb-v4-2-46170004da28@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 6b7378cf4d49..b0b9baf01ec2 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -72,7 +72,7 @@ chosen { stdout-path = "serial0:115200n8"; - framebuffer: framebuffer@9d400000 { + framebuffer: framebuffer { compatible = "simple-framebuffer"; memory-region = <&cont_splash_mem>; From 15520f868651d6b03c603918bade78f4799df7ca Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Thu, 2 Apr 2026 00:39:37 +0200 Subject: [PATCH 050/665] arm64: dts: qcom: sdm845-shift-axolotl: Convert fb to use memory-region Instead of manually specifying reg, reuse the memory region. Reviewed-by: Dmitry Baryshkov Signed-off-by: David Heidelberg Link: https://lore.kernel.org/r/20260402-beryllium-fb-v4-3-46170004da28@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index 7d81198bc499..d248d282ef7c 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -23,7 +23,7 @@ / { qcom,board-id = <11 0>; aliases { - display0 = &framebuffer0; + display0 = &framebuffer; serial0 = &uart9; serial1 = &uart6; }; @@ -36,9 +36,9 @@ chosen { stdout-path = "serial0"; /* Use framebuffer setup by the bootloader. */ - framebuffer0: framebuffer@9d400000 { + framebuffer: framebuffer { compatible = "simple-framebuffer"; - reg = <0x0 0x9d400000 0x0 (1080 * 2160 * 4)>; + memory-region = <&framebuffer_mem>; width = <1080>; height = <2160>; stride = <(1080 * 4)>; @@ -62,7 +62,7 @@ key-vol-up { }; reserved-memory { - framebuffer@9d400000 { + framebuffer_mem: framebuffer@9d400000 { reg = <0x0 0x9d400000 0x0 (1080 * 2160 * 4)>; no-map; }; From 2eae029f7d38c5fc03a778f483b5079d0e355472 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Thu, 2 Apr 2026 00:39:38 +0200 Subject: [PATCH 051/665] arm64: dts: qcom: sdm845-samsung-starqltechn: Convert fb to use memory-region Instead of manually specifying reg, reuse the memory region. Reviewed-by: Dmitry Baryshkov Signed-off-by: David Heidelberg Link: https://lore.kernel.org/r/20260402-beryllium-fb-v4-4-46170004da28@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts index 77f5872de6f1..0d915ecb0444 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts @@ -43,9 +43,10 @@ chosen { #address-cells = <2>; #size-cells = <2>; ranges; - framebuffer: framebuffer@9d400000 { + + framebuffer { compatible = "simple-framebuffer"; - reg = <0 0x9d400000 0 (2960 * 1440 * 4)>;//2400000 + memory-region = <&framebuffer_mem>; width = <1440>; height = <2960>; stride = <(1440 * 4)>; @@ -109,7 +110,7 @@ vreg_s4a_1p8: pm8998-smps4 { }; reserved-memory { - memory@9d400000 { + framebuffer_mem: memory@9d400000 { reg = <0x0 0x9d400000 0x0 0x02400000>; no-map; }; From 66fb209e6035ed90cbff71c48c60124803da5c63 Mon Sep 17 00:00:00 2001 From: Griffin Kroah-Hartman Date: Fri, 3 Apr 2026 10:21:33 +0200 Subject: [PATCH 052/665] arm64: dts: qcom: milos-fairphone-fp6: Add vibrator support Add the required node for haptic playback (Awinic AW86938) Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Griffin Kroah-Hartman Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20260403-aw86938-driver-v5-1-0712909df423@fairphone.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/milos-fairphone-fp6.dts | 26 ++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts index 5dc7c950e60d..ebdca0e2d2f3 100644 --- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts @@ -687,7 +687,17 @@ vreg_l7p: ldo7 { }; /* VL53L3 ToF @ 0x29 */ - /* AW86938FCR vibrator @ 0x5a */ + + vibrator@5a { + compatible = "awinic,aw86938", "awinic,aw86927"; + reg = <0x5a>; + + interrupts-extended = <&tlmm 80 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 78 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&aw86938_int_default>, <&aw86938_reset_default>; + pinctrl-names = "default"; + }; }; &pm8550vs_c { @@ -829,6 +839,20 @@ hall_sensor_default: hall-sensor-default-state { bias-disable; }; + aw86938_reset_default: aw86938-reset-default-state { + pins = "gpio78"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + aw86938_int_default: aw86938-int-default-state { + pins = "gpio80"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + pm8008_int_default: pm8008-int-default-state { pins = "gpio125"; function = "gpio"; From 2552d5f2e51bd7e449b495d518e1f2e5252baf56 Mon Sep 17 00:00:00 2001 From: Aastha Pandey Date: Fri, 3 Apr 2026 17:26:33 +0530 Subject: [PATCH 053/665] arm64: dts: qcom: sm8750: Enable cpufreq cooling devices Add cooling-cells property to the CPU nodes to support cpufreq cooling devices. Signed-off-by: Aastha Pandey Reviewed-by: Dmitry Baryshkov Reviewed-by: Gaurav Kohli Link: https://lore.kernel.org/r/20260403-cpufreq-v1-1-9d465988c3f9@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 18fb52c14acd..417f28d8c919 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -42,6 +42,7 @@ cpu0: cpu@0 { next-level-cache = <&l2_0>; power-domains = <&cpu_pd0>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; l2_0: l2-cache { compatible = "cache"; @@ -58,6 +59,7 @@ cpu1: cpu@100 { next-level-cache = <&l2_0>; power-domains = <&cpu_pd1>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu2: cpu@200 { @@ -68,6 +70,7 @@ cpu2: cpu@200 { next-level-cache = <&l2_0>; power-domains = <&cpu_pd2>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu3: cpu@300 { @@ -78,6 +81,7 @@ cpu3: cpu@300 { next-level-cache = <&l2_0>; power-domains = <&cpu_pd3>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu4: cpu@400 { @@ -88,6 +92,7 @@ cpu4: cpu@400 { next-level-cache = <&l2_0>; power-domains = <&cpu_pd4>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu5: cpu@500 { @@ -98,6 +103,7 @@ cpu5: cpu@500 { next-level-cache = <&l2_0>; power-domains = <&cpu_pd5>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu6: cpu@10000 { @@ -108,6 +114,7 @@ cpu6: cpu@10000 { next-level-cache = <&l2_1>; power-domains = <&cpu_pd6>, <&scmi_dvfs 1>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; l2_1: l2-cache { compatible = "cache"; @@ -124,6 +131,7 @@ cpu7: cpu@10100 { next-level-cache = <&l2_1>; power-domains = <&cpu_pd7>, <&scmi_dvfs 1>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu-map { From cd66b6d256f94e40922941e14d7f9390d35d072b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 5 Apr 2026 15:39:28 +0200 Subject: [PATCH 054/665] arm64: dts: qcom: glymur: Fix USB simple_bus_reg warning Correct the unit address of USB node in Qualcomm Glymur SoC DTSI to fix W=1 DTC warning: glymur.dtsi:4027.23-4093.5: Warning (simple_bus_reg): /soc@0/usb@a2f8800: simple-bus unit address format error, expected "a200000" Fixes: 4eee57dd4df9 ("arm64: dts: qcom: glymur: Add USB related nodes") Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260405-dts-qcom-w-1-fixes-v2-1-1f2c7b74a93f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index f23cf81ddb77..3389103408b6 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -4024,7 +4024,7 @@ usb_2_dwc3_ss: endpoint { }; }; - usb_hs: usb@a2f8800 { + usb_hs: usb@a200000 { compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; reg = <0x0 0x0a200000 0x0 0xfc100>; From 46eccc1034c3740b07b58c125190bbb99247c9de Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 5 Apr 2026 15:39:29 +0200 Subject: [PATCH 055/665] arm64: dts: qcom: glymur: Fix cache and SRAM simple_bus_reg warnings Correct the unit address of cache controller and SRAM nodes in Qualcomm Glymur SoC DTSI to fix W=1 DTC warnings: glymur.dtsi:5876.36-5908.5: Warning (simple_bus_reg): /soc@0/system-cache-controller@20400000: simple-bus unit address format error, expected "21800000" glymur.dtsi:5917.23-5934.5: Warning (simple_bus_reg): /soc@0/sram@81e08000: simple-bus unit address format error, expected "81e08600" Fixes: 41b6e8db400c ("arm64: dts: qcom: Introduce Glymur base dtsi") Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260405-dts-qcom-w-1-fixes-v2-2-1f2c7b74a93f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 3389103408b6..0c5cb8532b20 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -5873,7 +5873,7 @@ oobm_ss_noc: interconnect@1f300000 { #interconnect-cells = <2>; }; - system-cache-controller@20400000 { + system-cache-controller@21800000 { compatible = "qcom,glymur-llcc"; reg = <0x0 0x21800000 0x0 0x100000>, <0x0 0x21a00000 0x0 0x100000>, @@ -5914,7 +5914,7 @@ nsp_noc: interconnect@320c0000 { #interconnect-cells = <2>; }; - imem: sram@81e08000 { + imem: sram@81e08600 { compatible = "mmio-sram"; reg = <0x0 0x81e08600 0x0 0x300>; From 864fde494aa1dd26c68254661f2ce973e9f03832 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 5 Apr 2026 15:39:30 +0200 Subject: [PATCH 056/665] arm64: dts: qcom: ipq5424: Fix USB simple_bus_reg warnings Correct the unit address of USB nodes in Qualcomm IPQ5424 SoC DTSI to fix W=1 DTC warnings: ipq5424.dtsi:642.22-693.5: Warning (simple_bus_reg): /soc@0/usb2@1e00000: simple-bus unit address format error, expected "1ef8800" ipq5424.dtsi:733.22-786.5: Warning (simple_bus_reg): /soc@0/usb3@8a00000: simple-bus unit address format error, expected "8af8800" Fixes: 113d52bdc820 ("arm64: dts: qcom: ipq5424: Add USB controller and phy nodes") Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260405-dts-qcom-w-1-fixes-v2-3-1f2c7b74a93f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5424.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index f20cda429094..876bf6a8b8ff 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -639,7 +639,7 @@ qusb_phy_1: phy@71000 { status = "disabled"; }; - usb2: usb2@1e00000 { + usb2: usb2@1ef8800 { compatible = "qcom,ipq5424-dwc3", "qcom,dwc3"; reg = <0 0x01ef8800 0 0x400>; #address-cells = <2>; @@ -730,7 +730,7 @@ ssphy_0: phy@7d000 { status = "disabled"; }; - usb3: usb3@8a00000 { + usb3: usb3@8af8800 { compatible = "qcom,ipq5424-dwc3", "qcom,dwc3"; reg = <0 0x08af8800 0 0x400>; From f319a5fc998e29699d325af0e461721b3768eeec Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 5 Apr 2026 15:39:31 +0200 Subject: [PATCH 057/665] arm64: dts: qcom: sc8180x: Fix phy simple_bus_reg warning Correct the unit address of phy node in Qualcomm SC8180x SoC DTSI to fix W=1 DTC warning: sc8180x.dtsi:2650.31-2695.5: Warning (simple_bus_reg): /soc@0/phy@88ee000: simple-bus unit address format error, expected "88ed000" Fixes: 35e3a9c1afce ("arm64: dts: qcom: sc8180x: switch USB+DP QMP PHYs to new bindings") Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260405-dts-qcom-w-1-fixes-v2-4-1f2c7b74a93f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index f45deb188c6c..e87e82fa73e9 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -2647,7 +2647,7 @@ usb_mp_qmpphy1: phy@88ec000 { status = "disabled"; }; - usb_sec_qmpphy: phy@88ee000 { + usb_sec_qmpphy: phy@88ed000 { compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; reg = <0 0x088ed000 0 0x3000>; From f20a82aacd7f381084391a8d1f0f58defa91974c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 5 Apr 2026 15:39:32 +0200 Subject: [PATCH 058/665] arm64: dts: qcom: sdm845-mezzanine: Fix camss ports unit_address_vs_reg warning Add necessary properties for ports node in SDM845 DB845c Navigation mezzanine overlay to fix W=1 DTC warning: sdm845-db845c-navigation-mezzanine.dtso:19.10-24.5: Warning (unit_address_vs_reg): /fragment@0/__overlay__/ports/port@0: node has a unit name, but no reg or ranges property Fixes: 30df676a31b7 ("arm64: dts: qcom: sdm845-db845c-navigation-mezzanine: Convert mezzanine riser to dtso") Reviewed-by: Dmitry Baryshkov Reviewed-by: David Heidelberg Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260405-dts-qcom-w-1-fixes-v2-5-1f2c7b74a93f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso b/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso index dbe1911d8e47..678a17c805f7 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso @@ -16,7 +16,12 @@ &camss { status = "okay"; ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + csiphy0_ep: endpoint { data-lanes = <0 1 2 3>; remote-endpoint = <&ov8856_ep>; From e8fae9152e100b4bb30d38b25bc9c81623e8e91e Mon Sep 17 00:00:00 2001 From: Kamal Wadhwa Date: Mon, 6 Apr 2026 19:05:55 +0530 Subject: [PATCH 059/665] arm64: dts: qcom: fix temp-alarm probe failure for PMH0104 on Glymur The temp-alarm driver probe is failing for the pmh0104 PMICs on glymur. [ 3.999713] spmi-temp-alarm c426000.spmi:pmic@8:temp-alarm@a00: error -ENODEV: failed to register sensor [ 4.015066] spmi-temp-alarm c426000.spmi:pmic@9:temp-alarm@a00: error -ENODEV: failed to register sensor [ 4.033908] spmi-temp-alarm c437000.spmi:pmic@b:temp-alarm@a00: error -ENODEV: failed to register sensor This happens because thermal zone associated with the temp alarm was defined under the thermal zones parent node which had a typo (used `_` in place of `-`). Correct the typo to fix probe failure. Fixes: 41b6e8db400c ("arm64: dts: qcom: Introduce Glymur base dtsi") Signed-off-by: Kamal Wadhwa Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260406-glymur-pmh0104-temp-alarm-fix-v1-1-4441b7b01f85@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi b/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi index 7a1e5f355c17..6b4747025b9f 100644 --- a/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi @@ -7,7 +7,7 @@ #include /{ - thermal_zones { + thermal-zones { pmh0104_i0_thermal: pmh0104-i0-thermal { polling-delay-passive = <100>; thermal-sensors = <&pmh0104_i_e0_temp_alarm>; From 50fc93244973f5ebc97eb06857fb6bed0e3cbd39 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Fri, 3 Apr 2026 15:58:47 +0200 Subject: [PATCH 060/665] arm64: dts: qcom: sdm845-oneplus: Enable NFC Enable NFC controller NXP PN553, which is part of the package NXP NQ330 (NFC + eSE). Based on work of biemster . Signed-off-by: David Heidelberg Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260403-oneplus-nfc-v3-2-fbdce57d63c1@ixit.cz Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm845-oneplus-common.dtsi | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index b0b9baf01ec2..04e11448b53a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -464,6 +464,26 @@ &gpu_zap_shader { firmware-name = "qcom/sdm845/OnePlus/enchilada/a630_zap.mbn"; }; +&i2c3 { + clock-frequency = <400000>; + + status = "okay"; + + nfc@28 { + compatible = "nxp,pn553", "nxp,nxp-nci-i2c"; + reg = <0x28>; + + interrupts-extended = <&tlmm 63 IRQ_TYPE_EDGE_RISING>; + + enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&tlmm 62 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&nfc_default>; + pinctrl-1 = <&nfc_sleep>; + pinctrl-names = "default", "sleep"; + }; +}; + &i2c10 { status = "okay"; clock-frequency = <100000>; @@ -674,6 +694,11 @@ &qupv3_id_0 { status = "okay"; }; +&qup_i2c3_default { + drive-strength = <2>; + bias-disable; +}; + &qup_i2c10_default { drive-strength = <2>; bias-disable; @@ -1007,6 +1032,38 @@ speaker_default: speaker-default-state { bias-pull-up; output-high; }; + + nfc_default: nfc-default-state { + enable-pins { + pins = "gpio12", "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + int-pins { + pins = "gpio63"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + nfc_sleep: nfc-sleep-state { + enable-pins { + pins = "gpio12", "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + int-pins { + pins = "gpio63"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; }; &venus { From 0689aa70fe28ba13eb1d8b10d50e08157ade9670 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Fri, 3 Apr 2026 15:58:48 +0200 Subject: [PATCH 061/665] arm64: dts: qcom: sdm845-shift-axolotl: Correct touchscreen sleep state There is no suspend state in the mainline kernel, use the sleep state intended for this purpose. Fixes: 45882459159d ("arm64: dts: qcom: sdm845: add device tree for SHIFT6mq") Signed-off-by: David Heidelberg Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260403-oneplus-nfc-v3-3-fbdce57d63c1@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index d248d282ef7c..de9ceb9d6ed4 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -448,7 +448,7 @@ touchscreen@38 { pinctrl-0 = <&ts_int_active &ts_reset_active>; pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; - pinctrl-names = "default", "suspend"; + pinctrl-names = "default", "sleep"; touchscreen-size-x = <1080>; touchscreen-size-y = <2160>; From f585772843ba6add712bbf2505055f34d07b8622 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Fri, 3 Apr 2026 15:58:49 +0200 Subject: [PATCH 062/665] arm64: dts: qcom: sdm845-shift-axolotl: Enable NFC Enable NFC controller NXP PN553. Signed-off-by: David Heidelberg Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260403-oneplus-nfc-v3-4-fbdce57d63c1@ixit.cz Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm845-shift-axolotl.dts | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index de9ceb9d6ed4..14a683ee3823 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -431,6 +431,26 @@ &gpu_zap_shader { firmware-name = "qcom/sdm845/SHIFT/axolotl/a630_zap.mbn"; }; +&i2c3 { + clock-frequency = <400000>; + + status = "okay"; + + nfc@28 { + compatible = "nxp,pn553", "nxp,nxp-nci-i2c"; + reg = <0x28>; + + interrupts-extended = <&tlmm 63 IRQ_TYPE_EDGE_RISING>; + + enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&tlmm 62 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&nfc_default>; + pinctrl-1 = <&nfc_sleep>; + pinctrl-names = "default", "sleep"; + }; +}; + &i2c5 { clock-frequency = <400000>; @@ -668,6 +688,38 @@ sdc2_card_det_n: sd-card-det-n-state { bias-disable; }; + nfc_default: nfc-default-state { + enable-pins { + pins = "gpio12", "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + int-pins { + pins = "gpio63"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + nfc_sleep: nfc-sleep-state { + enable-pins { + pins = "gpio12", "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + int-pins { + pins = "gpio63"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + sde_dsi_active: sde-dsi-active-state { pins = "gpio6", "gpio11"; function = "gpio"; From 10f91b0dfaf6008e5b4f75a3f4d8a507f4c0d5ad Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Fri, 3 Apr 2026 15:58:50 +0200 Subject: [PATCH 063/665] arm64: dts: qcom: sdm845-google-common: Enable NFC Enable NFC controller NXP PN557. Signed-off-by: David Heidelberg Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260403-oneplus-nfc-v3-5-fbdce57d63c1@ixit.cz Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm845-google-common.dtsi | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi index 693006685776..b2dc0327dff8 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi @@ -391,6 +391,23 @@ &gpu_zap_shader { firmware-name = "qcom/sdm845/Google/blueline/a630_zap.mbn"; }; +&i2c3 { + status = "okay"; + + nfc@28 { + compatible = "nxp,pn557", "nxp,nxp-nci-i2c"; + reg = <0x28>; + + interrupts-extended = <&tlmm 63 IRQ_TYPE_EDGE_RISING>; + + enable-gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&tlmm 79 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&nfc_int_default &nfc_enable_default>; + pinctrl-names = "default"; + }; +}; + &i2c12 { /* Bottom spkr (right) CS35L36 @ 40 */ @@ -459,6 +476,20 @@ &tlmm { gpio-reserved-ranges = < 0 4>, /* SPI (Intel MNH Pixel Visual Core) */ <81 4>; /* SPI (most likely Fingerprint Cards FPC1075) */ + nfc_int_default: nfc-int-default-state { + pins = "gpio63"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + nfc_enable_default: nfc-enable-default-state { + pins = "gpio25", "gpio79"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + touchscreen_reset: ts-reset-state { pins = "gpio99"; function = "gpio"; From aa7066248f1b6b2d000d3cc2f64a3fd4930e1b44 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Sun, 5 Apr 2026 12:54:55 +0200 Subject: [PATCH 064/665] dt-bindings: arm: qcom: Document Xiaomi Poco F1 Tianma variant Document the panel-specific compatible string for the Tianma variant of the Xiaomi Poco F1: - "xiaomi,beryllium-tianma" and require the generic fallback compatible: - "xiaomi,beryllium" Update the binding to clarify that all panel variants must list the variant-specific compatible first, followed by the generic device compatible, in accordance with DT matching rules. The previous binding documentation did not describe the Tianma variant and did not clearly specify the required fallback compatible, which resulted in inconsistent DTS implementations. No functional differences are currently exposed between Tianma and EBBG variants at the binding level; both rely on the same generic device compatibility for software support. Signed-off-by: David Heidelberg Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260405-beryllium-compat-string-v2-1-91149be07835@ixit.cz Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 24164ba70b6f..d2b87d5eb3d9 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -823,6 +823,14 @@ properties: - const: google,zombie-sku514 - const: qcom,sc7280 + - description: Xiaomi Poco F1 + items: + - enum: + - xiaomi,beryllium-ebbg + - xiaomi,beryllium-tianma + - const: xiaomi,beryllium + - const: qcom,sdm845 + - items: - enum: - lenovo,flex-5g @@ -973,8 +981,6 @@ properties: - sony,akatsuki-row - sony,apollo-row - thundercomm,db845c - - xiaomi,beryllium - - xiaomi,beryllium-ebbg - xiaomi,polaris - const: qcom,sdm845 From 68bfaa3fde985a227721b58b32283811d05d5c21 Mon Sep 17 00:00:00 2001 From: Jens Reidel Date: Sun, 5 Apr 2026 12:54:56 +0200 Subject: [PATCH 065/665] arm64: dts: qcom: sdm845-xiaomi-beryllium: Append compatible strings Add the generic "xiaomi,beryllium" compatible string after the panel-specific one, so the compatible list follows the required ordering from most specific to most generic. This allows userspace to fall back to the generic Poco F1 compatible when no panel-specific match is present. In particular, hexagonrpcd relies on trying all compatible entries to derive the HexagonFS path, and currently fails when the generic device string is missing. This change modifies the DT ABI: systems describing the EBBG variant will now also match on "xiaomi,beryllium", whereas previously only the panel-specific compatible was exposed. In practice, no upstream userspace distinguishes between Tianma and EBBG panel variants. All known consumers rely only on the generic device identification, and no panel-specific handling exists. Therefore, enabling the generic fallback does not change effective runtime behavior, but fixes userspace that depends on generic matching. The previous state was incomplete, as it omitted the generic device-compatible string required for proper fallback matching. Signed-off-by: Jens Reidel Signed-off-by: David Heidelberg Link: https://lore.kernel.org/r/20260405-beryllium-compat-string-v2-2-91149be07835@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-ebbg.dts | 2 +- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-ebbg.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-ebbg.dts index 2d6f0e382a6c..d157622f84d1 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-ebbg.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-ebbg.dts @@ -6,7 +6,7 @@ / { model = "Xiaomi Pocophone F1 (EBBG)"; - compatible = "xiaomi,beryllium-ebbg", "qcom,sdm845"; + compatible = "xiaomi,beryllium-ebbg", "xiaomi,beryllium", "qcom,sdm845"; }; &display_panel { diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts index b58964cde834..71816a9f33b4 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts @@ -6,7 +6,7 @@ / { model = "Xiaomi Pocophone F1 (Tianma)"; - compatible = "xiaomi,beryllium", "qcom,sdm845"; + compatible = "xiaomi,beryllium-tianma", "xiaomi,beryllium", "qcom,sdm845"; }; &display_panel { From 3d395de80a46cc2e046c106841c7aa4e1259010a Mon Sep 17 00:00:00 2001 From: Ronak Raheja Date: Mon, 6 Apr 2026 23:16:11 +0530 Subject: [PATCH 066/665] arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC Add the base USB devicetree definitions for Kaanapali platform. The overall chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY (rev. v8) and M31 eUSB2 PHY. Signed-off-by: Ronak Raheja Signed-off-by: Jingyi Wang Signed-off-by: Krishna Kurapati Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260406174613.3388987-2-krishna.kurapati@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 154 ++++++++++++++++++++++++ 1 file changed, 154 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index 7cc326aa1a1a..bab654bbd6d0 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -3138,6 +3138,77 @@ opp-202000000 { }; }; + usb_hsphy: phy@88e3000 { + compatible = "qcom,kaanapali-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + reg = <0x0 0x88e3000 0x0 0x29c>; + + clocks = <&tcsr TCSR_USB2_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_dp_qmpphy: phy@88e8000 { + compatible = "qcom,kaanapali-qmp-usb3-dp-phy", + "qcom,sm8750-qmp-usb3-dp-phy"; + reg = <0x0 0x088e8000 0x0 0x4000>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&tcsr TCSR_USB3_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe"; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; + reset-names = "phy", + "common"; + + power-domains = <&gcc GCC_USB3_PHY_GDSC>; + + #clock-cells = <1>; + #phy-cells = <1>; + + orientation-switch; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dp_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_dp_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_dp_qmpphy_dp_in: endpoint { + }; + }; + }; + }; + camcc: clock-controller@956d000 { compatible = "qcom,kaanapali-camcc"; reg = <0x0 0x0956d000 0x0 0x80000>; @@ -3422,6 +3493,89 @@ dispcc: clock-controller@9ba2000 { #reset-cells = <1>; }; + usb: usb@a600000 { + compatible = "qcom,kaanapali-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a600000 0x0 0xfc100>; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dwc_usb3", + "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + interconnects = <&aggre_noc MASTER_USB3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "usb-ddr", "apps-usb"; + iommus = <&apps_smmu 0x40 0x0>; + + phys = <&usb_hsphy>, <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", "usb3-phy"; + + snps,hird-threshold = /bits/ 8 <0x0>; + snps,usb2-gadget-lpm-disable; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,usb2-lpm-disable; + snps,has-lpm-erratum; + tx-fifo-resize; + dma-coherent; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_dwc3_ss: endpoint { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; + }; + }; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,kaanapali-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x10000>, From b2f036a675805812c475c917846320949c2b0c6c Mon Sep 17 00:00:00 2001 From: Ronak Raheja Date: Mon, 6 Apr 2026 23:16:12 +0530 Subject: [PATCH 067/665] arm64: dts: qcom: kaanpaali: Add USB support for MTP platform Enable USB support on Kaanapali MTP variant. Enable USB controller in device mode till glink node is added. Signed-off-by: Ronak Raheja Signed-off-by: Jingyi Wang Signed-off-by: Krishna Kurapati Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260406174613.3388987-3-krishna.kurapati@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts index 07247dc98b70..f9b5b5718b90 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts @@ -952,6 +952,11 @@ wifi@0 { }; }; +&pmih0108_e1_eusb2_repeater { + vdd18-supply = <&vreg_l15b_1p8>; + vdd3-supply = <&vreg_l5b_3p1>; +}; + &pmh0101_flash { status = "okay"; @@ -1321,3 +1326,25 @@ &ufs_mem_phy { status = "okay"; }; + +&usb { + dr_mode = "peripheral"; + + status = "okay"; +}; + +&usb_hsphy { + vdd-supply = <&vreg_l4f_0p8>; + vdda12-supply = <&vreg_l1d_1p2>; + + phys = <&pmih0108_e1_eusb2_repeater>; + + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&vreg_l1d_1p2>; + vdda-pll-supply = <&vreg_l4f_0p8>; + + status = "okay"; +}; From 01d15f5f69964de3d947abb5e4c550397db68c70 Mon Sep 17 00:00:00 2001 From: Ronak Raheja Date: Mon, 6 Apr 2026 23:16:13 +0530 Subject: [PATCH 068/665] arm64: dts: qcom: kaanpaali: Add USB support for QRD platform Enable USB support on Kaanapali QRD variant. Enable USB controller in device mode till glink node is added. Signed-off-by: Ronak Raheja Signed-off-by: Jingyi Wang Signed-off-by: Krishna Kurapati Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260406174613.3388987-4-krishna.kurapati@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kaanapali-qrd.dts | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts index da0e8f9091c3..55d02219ef4e 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts @@ -744,6 +744,11 @@ led@3 { }; }; +&pmih0108_e1_eusb2_repeater { + vdd18-supply = <&vreg_l15b_1p8>; + vdd3-supply = <&vreg_l5b_3p1>; +}; + &pon_resin { linux,code = ; @@ -816,3 +821,25 @@ &ufs_mem_phy { status = "okay"; }; + +&usb { + dr_mode = "peripheral"; + + status = "okay"; +}; + +&usb_hsphy { + vdd-supply = <&vreg_l4f_0p8>; + vdda12-supply = <&vreg_l1d_1p2>; + + phys = <&pmih0108_e1_eusb2_repeater>; + + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&vreg_l1d_1p2>; + vdda-pll-supply = <&vreg_l4f_0p8>; + + status = "okay"; +}; From 15bdb0e14551c53fc0f9d0e82690510c88838c3b Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Mon, 6 Apr 2026 22:18:25 +0200 Subject: [PATCH 069/665] arm64: dts: qcom: sdm845-oneplus: Enable known blocks and add placeholders We know these devices are present; most of them are supported by downstream and are close to the mainline kernels. This adds placeholders for: - front camera (imx371) - rear cameras (imx519, imx376k) - actuators This is very handy when rebasing the integration tree with support for multiple different blocks at the same time. Signed-off-by: David Heidelberg Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260406-placeholders-v2-1-9cdbe1fc9666@ixit.cz Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm845-oneplus-common.dtsi | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 04e11448b53a..a6c2519a418d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -442,6 +442,26 @@ vreg_s3c_0p6: smps3 { }; }; +&cci { + status = "okay"; +}; + +&cci_i2c0 { + /* front sony,imx371 @10 */ + + /* rear sony,imx519 @1a */ + + /* rear onnn,lc898217xc @72 */ +}; + +&cci_i2c1 { + /* sa,sa3103 @0d */ + + /* rear sony,imx376k @10 */ + + /* onnn,lc898217xc @74 */ +}; + &cdsp_pas { firmware-name = "qcom/sdm845/OnePlus/enchilada/cdsp.mbn"; From 839d20f9f3da93f65c000187ee68387598bdecb5 Mon Sep 17 00:00:00 2001 From: Val Packett Date: Fri, 3 Apr 2026 02:33:08 -0300 Subject: [PATCH 070/665] dt-bindings: arm: qcom: Add SM7325 Motorola Edge 30 (dubai) Motorola Edge 30 (motorola,dubai) is a smartphone based on the SM7325 SoC. Acked-by: Krzysztof Kozlowski Signed-off-by: Val Packett Link: https://lore.kernel.org/r/20260403054417.167917-1-val@packett.cool Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index d2b87d5eb3d9..2741c07e9f41 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1047,6 +1047,7 @@ properties: - items: - enum: + - motorola,dubai - nothing,spacewar - const: qcom,sm7325 From dd1316efdbc5a998b901b1c5f27da73d45060795 Mon Sep 17 00:00:00 2001 From: Val Packett Date: Fri, 3 Apr 2026 02:33:09 -0300 Subject: [PATCH 071/665] arm64: dts: qcom: Add Motorola Edge 30 (dubai) DTS The Motorola Edge 30 is a smartphone released in 2022. This commit has the following features working: - Display (simplefb) - Touchscreen - Power and volume buttons - Storage (UFS 3.1) - Battery (ADSP battmgr) - USB (Type-C, 2.0, dual-role) - Wi-Fi and Bluetooth (WCN6750 hw1.0) Signed-off-by: Val Packett Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260403054417.167917-2-val@packett.cool Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sm7325-motorola-dubai.dts | 1456 +++++++++++++++++ 2 files changed, 1457 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm7325-motorola-dubai.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 169cc9b9ccd3..cc42829f92eb 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -341,6 +341,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm6375-sony-xperia-murray-pdx225.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7125-xiaomi-curtana.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7125-xiaomi-joyeuse.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm7325-motorola-dubai.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7325-nothing-spacewar.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-microsoft-surface-duo.dtb diff --git a/arch/arm64/boot/dts/qcom/sm7325-motorola-dubai.dts b/arch/arm64/boot/dts/qcom/sm7325-motorola-dubai.dts new file mode 100644 index 000000000000..3c836e196b19 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm7325-motorola-dubai.dts @@ -0,0 +1,1456 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2026, Val Packett + */ + +/dts-v1/; + +/* PM7250B is configured to use SID8/9 */ +#define PM7250B_SID 8 +#define PM7250B_SID1 9 + +#include +#include +#include +#include +#include +#include +#include + +#include "sm7325.dtsi" +#include "pm7325.dtsi" +#include "pm7250b.dtsi" +#include "pm8350c.dtsi" /* PM7350C */ +#include "pmk8350.dtsi" /* PMK7325 */ + +/ { + model = "Motorola Edge 30"; + compatible = "motorola,dubai", "qcom,sm7325"; + chassis-type = "handset"; + + aliases { + bluetooth0 = &bluetooth; + serial0 = &uart5; + serial1 = &uart7; + wifi0 = &wifi; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0:115200n8"; + + framebuffer { + compatible = "simple-framebuffer"; + memory-region = <&framebuffer_mem>; + width = <1080>; + height = <2400>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&kypd_vol_up_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + pmic-glink { + compatible = "qcom,sm7325-pmic-glink", + "qcom,qcm6490-pmic-glink", + "qcom,pmic-glink"; + + #address-cells = <1>; + #size-cells = <0>; + + orientation-gpios = <&tlmm 140 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint = <&fsa4480_sbu_mux>; + }; + }; + }; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops@ae000000 { + compatible = "ramoops"; + reg = <0x0 0xae000000 0x0 0xc0000>; + console-size = <0x40000>; + mem-type = <2>; + pmsg-size = <0x40000>; + record-size = <0x3f800>; + }; + + removed@c0000000 { + reg = <0x0 0xc0000000 0x0 0x5100000>; + no-map; + }; + + framebuffer_mem: framebuffer@e1000000 { + reg = <0x0 0xe1000000 0x0 (1080 * 2400 * 4)>; + no-map; + }; + + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + thermal-zones { + cam-flash-thermal { + thermal-sensors = <&pmk8350_adc_tm 2>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + chg-skin-thermal { + thermal-sensors = <&pm7250b_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + chg-thermal { + thermal-sensors = <&pmk8350_adc_tm 4>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + conn-thermal { + thermal-sensors = <&pm7250b_adc_tm 1>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-1-thermal { + thermal-sensors = <&pmk8350_adc_tm 5>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-2-thermal { + thermal-sensors = <&pmk8350_adc_tm 6>; + + /* Reports negative temperature. */ + status = "disabled"; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + quiet-thermal { + thermal-sensors = <&pmk8350_adc_tm 1>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdm-skin-thermal { + thermal-sensors = <&pmk8350_adc_tm 3>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo-thermal { + thermal-sensors = <&pmk8350_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; + + // S2B is really ebi.lvl but it's there for supply map completeness sake. + vreg_s2b_0p7: smpb2-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_s2b_0p7"; + + regulator-min-microvolt = <65535>; + regulator-max-microvolt = <65535>; + regulator-always-on; + vin-supply = <&vph_pwr>; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + wcn6750-pmu { + compatible = "qcom,wcn6750-pmu"; + pinctrl-0 = <&bt_en>; + pinctrl-names = "default"; + vddaon-supply = <&mos_0p95_aon_s10c>; + vddasd-supply = <&vreg_l11c_2p8>; + vddpmu-supply = <&mos_0p95_dig_s10c>; + vddio-supply = <&vdd18_io>; + vddrfa0p8-supply = <&vdd09_pmu_rfa_i>; + vddrfa1p2-supply = <&vdd13_pmu_rfa_i>; + vddrfa1p7-supply = <&vdd19_pmu_rfa_i>; + vddrfa2p2-supply = <&vdd22_wlpa_s1c>; + + bt-enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p7: ldo7 { + regulator-name = "vreg_pmu_rfa_1p7"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm7325-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + + vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p952>; + vdd-l2-l7-supply = <&vreg_bob>; + vdd-l3-supply = <&vreg_s2b_0p7>; + vdd-l5-supply = <&vreg_s2b_0p7>; + vdd-l6-l9-l10-supply = <&vreg_s8b_1p256>; + vdd-l8-supply = <&vreg_s7b_0p952>; + vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p856>; + vdd-l13-supply = <&vreg_s7b_0p952>; + vdd-l14-l16-supply = <&vreg_s8b_1p256>; + + /* + * S2, L4-L5 are ARCs: + * S2 - ebi.lvl, + * L4 - lmx.lvl, + * l5 - lcx.lvl. + * + * L10 are unused. + */ + + vdd19_pmu_rfa_i: + vreg_s1b_1p856: smps1 { + regulator-name = "vreg_s1b_1p856"; + regulator-min-microvolt = <1840000>; + regulator-max-microvolt = <2040000>; + }; + + mos_0p95_aon_s10c: + mos_0p95_dig_s10c: + vdd09_pmu_rfa_i: + vreg_s7b_0p952: smps7 { + regulator-name = "vreg_s7b_0p952"; + regulator-min-microvolt = <535000>; + regulator-max-microvolt = <1120000>; + }; + + vdd13_pmu_rfa_i: + vreg_s8b_1p256: smps8 { + regulator-name = "vreg_s8b_1p256"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-initial-mode = ; + }; + + vreg_l1b_0p912: ldo1 { + regulator-name = "vreg_l1b_0p912"; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <925000>; + regulator-initial-mode = ; + }; + + vdd_a_usbhs_3p1: + vreg_l2b_3p072: ldo2 { + regulator-name = "vreg_l2b_3p072"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l3b_0p6: ldo3 { + regulator-name = "vreg_l3b_0p6"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <910000>; + regulator-initial-mode = ; + }; + + vdd_a_dsi_0_1p2: + vdd_a_ufs_0_1p2: + vreg_l6b_1p2: ldo6 { + regulator-name = "vreg_l6b_1p2"; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7b_2p96: ldo7 { + regulator-name = "vreg_l7b_2p96"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8b_0p904: ldo8 { + regulator-name = "vreg_l8b_0p904"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = ; + }; + + vreg_l9b_1p2: ldo9 { + regulator-name = "vreg_l9b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l11b_1p776: ldo11 { + regulator-name = "vreg_l11b_1p776"; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l12b_0p8: ldo12 { + regulator-name = "vreg_l12b_0p8"; + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + regulator-initial-mode = ; + }; + + vreg_l13b_0p8: ldo13 { + regulator-name = "vreg_l13b_0p8"; + regulator-min-microvolt = <530000>; + regulator-max-microvolt = <824000>; + regulator-initial-mode = ; + }; + + vreg_l14b_1p2: ldo14 { + regulator-name = "vreg_l14b_1p2"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l15b_0p88: ldo15 { + regulator-name = "vreg_l15b_0p88"; + regulator-min-microvolt = <765000>; + regulator-max-microvolt = <1020000>; + regulator-initial-mode = ; + }; + + vreg_l16b_1p2: ldo16 { + regulator-name = "vreg_l16b_1p2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + }; + + vreg_l17b_1p8: ldo17 { + regulator-name = "vreg_l17b_1p8"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + }; + + vreg_l18b_1p8: ldo18 { + regulator-name = "vreg_l18b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + regulator-always-on; + regulator-boot-on; + }; + + vdd18_io: + vreg_l19b_1p8: ldo19 { + regulator-name = "vreg_l19b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l12-supply = <&vreg_s1b_1p856>; + vdd-l2-l8-supply = <&vreg_s1b_1p856>; + vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>; + vdd-l6-l9-l11-supply = <&vreg_bob>; + vdd-l10-supply = <&vreg_s7b_0p952>; + + vdd-bob-supply = <&vph_pwr>; + + /* + * S2, S5, S7, S10 are ARCs: + * S2 - cx.lvl, + * S5 - mss.lvl, + * S7 - gfx.lvl, + * S10 - mx.lvl. + */ + + vdd22_wlpa_s1c: + vreg_s1c_2p2: smps1 { + regulator-name = "vreg_s1c_2p2"; + regulator-min-microvolt = <2190000>; + regulator-max-microvolt = <2210000>; + }; + + vreg_s9c_0p676: smps9 { + regulator-name = "vreg_s9c_0p676"; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + }; + + vdd_a_usbhs_1p8: + vdd_qfprom: + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + }; + + iovdd_ts: + vreg_l2c_1p8: ldo2 { + regulator-name = "vreg_l2c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vdd_ts: + vreg_l3c_3p0: ldo3 { + regulator-name = "vreg_l3c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l4c_1p8_3p0: ldo4 { + regulator-name = "vreg_l4c_1p8_3p0"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l5c_1p8_3p0: ldo5 { + regulator-name = "vreg_l5c_1p8_3p0"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l6c_2p96: ldo6 { + regulator-name = "vreg_l6c_2p96"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-name = "vreg_l7c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-name = "vreg_l8c_1p8"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l9c_3p3: ldo9 { + regulator-name = "vreg_l9c_2p96"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vdd_a_dsi_0_0p9: + vdd_a_ufs_0_core: + vdd_a_usbhs_core: + vreg_l10c_0p88: ldo10 { + regulator-name = "vreg_l10c_0p88"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l11c_2p8: ldo11 { + regulator-name = "vreg_l11c_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + disp_iovcc_1p8: + vreg_l12c_1p8: ldo12 { + regulator-name = "vreg_l12c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + disp_vci_3p0: + vreg_l13c_3p0: ldo13 { + regulator-name = "vreg_l13c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + audio_sw_vcc: + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + }; +}; + +&gcc { + protected-clocks = , + , + , + , + , + , + , + , + , + , + , + , + ; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/sm7325/motorola/dubai/a660_zap.mbn"; +}; + +&i2c4 { + clock-frequency = <100000>; + + status = "okay"; + + typec-mux@42 { + compatible = "fcs,fsa4480"; + reg = <0x42>; + + interrupts-extended = <&tlmm 6 IRQ_TYPE_LEVEL_LOW>; + + vcc-supply = <&audio_sw_vcc>; + + mode-switch; + orientation-switch; + + port { + fsa4480_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; + }; + }; + }; +}; + +&ipa { + firmware-name = "qcom/sm7325/motorola/dubai/yupik_ipa_fws.mbn"; + memory-region = <&ipa_fw_mem>; + + qcom,gsi-loader = "self"; + + status = "okay"; +}; + +&pm7250b_adc { + channel@4e { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "chg_skin_therm"; + }; + + channel@4f { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "conn_therm"; + }; +}; + +&pm7250b_adc_tm { + status = "okay"; + + chg-skin-therm@0 { + reg = <0>; + io-channels = <&pm7250b_adc ADC5_AMUX_THM2_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + conn-therm@1 { + reg = <1>; + io-channels = <&pm7250b_adc ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pm7250b_gpios { + gpio-line-names = "FG_ALERT_N", /* GPIO_1 */ + "SLAVECP_INT", + "NC", + "NC", + "NC", + "DOUBLER_STAT", + "NC", + "NC", + "NC", + "NC", /* GPIO_10 */ + "NC", + "NC"; +}; + +&pm7325_gpios { + gpio-line-names = "PA_THERM1", /* GPIO_1 */ + "NC", + "NC", + "PA_THERM2", + "CBL_PWR_N", + "KYPD_VOL_UP_N", + "NC", + "NC", + "NC", + "NC"; /* GPIO_10 */ + + kypd_vol_up_n: kypd-volp-n-state { + pins = "gpio6"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-pull-up; + input-enable; + power-source = <1>; + }; +}; + +&pm8350c_gpios { + gpio-line-names = "NC", /* GPIO_1 */ + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC"; /* GPIO_9 */ +}; + +&pm8350c_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <1>, <4>; + led-max-microamp = <500000>; + flash-max-microamp = <1500000>; + flash-max-timeout-us = <400000>; + }; + + led-1 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <2>, <3>; + led-max-microamp = <500000>; + flash-max-microamp = <1500000>; + flash-max-timeout-us = <400000>; + }; +}; + +&pmk8350_adc_tm { + status = "okay"; + + xo-therm@0 { + reg = <0>; + io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + quiet-therm@1 { + reg = <1>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + cam-flash-therm@2 { + reg = <2>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM2_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + sdm-skin-therm@3 { + reg = <3>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + chg-therm@4 { + reg = <4>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM4_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + pa-therm-1@5 { + reg = <5>; + io-channels = <&pmk8350_vadc PM7325_ADC7_GPIO1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + pa-therm-2@6 { + reg = <6>; + io-channels = <&pmk8350_vadc PM7325_ADC7_GPIO4_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pmk8350_gpios { + gpio-line-names = "NC", /* GPIO_0 */ + "NC", + "TP_PMK_GPIO_3", + "PMK_OPTION"; /* GPIO_4 */ +}; + +&pmk8350_rtc { + status = "okay"; +}; + +&pmk8350_vadc { + status = "okay"; + + channel@44 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pmk8350_xo_therm"; + }; + + channel@144 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_quiet_therm"; + }; + + channel@145 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_cam_flash_therm"; + }; + + channel@146 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_sdm_skin_therm"; + }; + + channel@147 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_chg_therm"; + }; + + channel@14a { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_pa_therm1"; + }; + + channel@14d { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_pa_therm2"; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + + status = "okay"; +}; + +&qfprom { + vcc-supply = <&vdd_qfprom>; +}; + +&qup_spi13_cs { + drive-strength = <6>; + bias-pull-down; +}; + +&qup_spi13_data_clk { + drive-strength = <6>; + bias-pull-down; +}; + +&qup_uart5_rx { + drive-strength = <2>; + bias-disable; +}; + +&qup_uart5_tx { + drive-strength = <2>; + bias-disable; +}; + +&qup_uart7_cts { + /* + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. + */ + bias-bus-hold; +}; + +&qup_uart7_rts { + /* We'll drive RTS, so no pull */ + drive-strength = <2>; + bias-disable; +}; + +&qup_uart7_rx { + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module is + * in tri-state (module powered off or not driving the + * signal yet). + */ + bias-pull-up; +}; + +&qup_uart7_tx { + /* We'll drive TX, so no pull */ + drive-strength = <2>; + bias-disable; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm7325/motorola/dubai/adsp.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm7325/motorola/dubai/cdsp.mbn"; + + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sm7325/motorola/dubai/modem.mbn"; + + status = "okay"; +}; + +&remoteproc_wpss { + firmware-name = "qcom/sm7325/motorola/dubai/wpss.mbn"; + + status = "okay"; +}; + +&rmtfs_mem { + qcom,vmid = , + ; +}; + +&spi13 { + status = "okay"; + + touchscreen@0 { + compatible = "goodix,gt9916"; + reg = <0>; + + interrupts-extended = <&tlmm 81 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&tlmm 105 GPIO_ACTIVE_LOW>; + + avdd-supply = <&vdd_ts>; + vddio-supply = <&iovdd_ts>; + + spi-max-frequency = <1000000>; + + touchscreen-size-x = <1080>; + touchscreen-size-y = <2400>; + + pinctrl-0 = <&ts_int_n>, <&ts_reset_n>; + pinctrl-names = "default"; + }; +}; + +&tlmm { + gpio-line-names = "NC", /* GPIO_0 */ + "NC", + "NC", + "NC", + "SMARTPA_I2C_SDA", + "SMARTPA_I2C_SCK", + "AUD_4480_DET", + "AUD_4480_INT", + "FASTCHARGE_I2C_SDA", + "FASTCHARGE_I2C_SCL", + "SM_GPSLNA_EN_GPIO10", /* GPIO_10 */ + "NC", + "PERI_I2C_SDA", + "PERI_I2C_SCL", + "NC", + "NC", + "APPS_I2C_SDA", + "APPS_I2C_SCL", + "NC", + "DISP_LDO_EN", + "CAM_FW_RST_N", /* GPIO_20 */ + "CAM_RM_RST_N", + "DBG_UART_TXD", + "DBG_UART_RXD", + "TOPSB_INT_N", + "MCAM_LDO_EN", + "HOST2WLAN_SOL", + "WLAN2HOST_SOL", + "UART_BT_RTS_AP_CTS", + "UART_BT_CTS_AP_RTS", + "UART_BT_RX_AP_TX", /* GPIO_30 */ + "UART_BT_TX_AP_RX", + "FRONT_60M_INT", + "FRONT_60M_RST", + "FP_INT", + "FP_RST", + "NFC_I2C_SDA", + "NFC_I2C_SCL", + "NFC_EN", + "NFC_CLK_REQ", + "NFC_SE_SPI_NREST", /* GPIO_40 */ + "NFC_IRQ", + "RF_LDO_GPIO42_EN", + "GOOGLE_KEY_INT", /* no such key exists */ + "DISP_RST_N", + "SB_INT_N", + "HAP_RST_N", + "HAP_INT", + "ESE_SPI_MISO", + "ESE_SPI_MOSI", + "ESE_SPI_CLK", /* GPIO_50 */ + "ESE_SPI_CS", + "TP_SPI_MISO", + "TP_SPI_MOSI", + "TP_SPI_CLK", + "TP_SPI_CS_N", + "FP_SPI_MISO", + "FP_SPI_MOSI", + "FP_SPI_CLK", + "FP_SPI_CS_N", + "HW_ID_1", /* GPIO_60 */ + "HW_ID_2", + "CAM_PMU_EN", + "WIDE_DVDD_LDO_EN", + "CAM_MCLK0", + "CAM_MCLK1", + "CAM_MCLK2", + "CAM_MCLK3", + "NC", + "CCI_I2C_SDA0", + "CCI_I2C_SCL0", /* GPIO_70 */ + "CCI_I2C_SDA1", + "CCI_I2C_SCL1", + "CCI_I2C_SDA2", + "CCI_I2C_SCL2", + "CCI_I2C_SDA3", + "CCI_I2C_SCL3", + "CAM_RT_RST_N", + "CAM_RU_RST_N", + "FCAM_LDO_EN", + "DISP_TE", /* GPIO_80 */ + "TP_INT_N", + "FORCED_USB_BOOT", + "SM_CDC_RST_N", + "WLAN_EN", + "BT_EN", + "WCN_SW_CTRL", + "PCIE0_RESET_N", + "PCIE0_CLK_REQ_N", + "PCIE0_WAKE_N", + "MOS_AS_EN", /* GPIO_90 */ + "NC", + "", + "NC", + "BT_FM_SLIMBUS_CLK", + "BT_FM_SLIMBUS_DATA", + "NC", + "RFCONN_DET_1", + "RF_CON_DET_2", + "RF_CON_DET_3", + "NC", /* GPIO_100 */ + "NC", + "NC", + "ACCEL_INT", + "NC", + "TP_RST_N", + "NC", + "NC", + "NC", + "UIM2_DATA", + "UIM2_CLK", /* GPIO_110 */ + "UIM2_RESET", + "UIM2_PRESENT", + "UIM1_DATA", + "UIM1_CLK", + "UIM1_RESET", + "UIM1_PRESENT", + "SM_RFFE0_CLK", + "SM_RFFE0_DATA", + "SM_RFFE1_CLK", + "SM_RFFE1_DATA", /* GPIO_120 */ + "PA_MUTING", + "SM_GRFC5", + "LAA_RX", + "SM_GRFC7", + "SM_RFFE4_CLK", + "SM_RFFE4_DATA", + "WLAN_COEX_UART_RX", + "WLAN_COEX_UART_TX", + "NC", + "NC", /* GPIO_130 */ + "SM_GRFC12", + "NC", + "QLINK0_REQUEST", + "QLINK0_ENABLE", + "QLINK0_WMSS_RESET_N", + "NC", + "NC", + "NC", + "NC", + "USB_CC_DIR", /* GPIO_140 */ + "SAR_INT_N", + "PROX_INT_N", + "", + "SM_SWR_TX_CLK", + "SM_SWR_TX_DATA0", + "SM_SWR_TX_DATA1", + "SM_SWR_RX_CLK", + "SM_SWR_RX_DATA0", + "SM_SWR_RX_DATA1", + "NC", /* GPIO_150 */ + "NC", + "NC", + "NC", + "SB_MI2S_SCK", + "SB_MI2S_WS", + "SB_MI2S_RXDAT_AP_TX", + "SB_MI2S_TXDAT_AP_RX", + "NC", + "SNS_I3C0_SDA", + "SNS_I3C0_SCL", /* GPIO_160 */ + "SSC_I2C4_SDA", + "SSC_I2C4_SCL", + "MAG_I2C_SDA", + "MAG_I2C_SCL", + "NC", + "NC", + "", + "", + "", + "", /* GPIO_170 */ + "SSC_BT_UART4_TX", + "SSC_BT_UART4_RX", + "NC", + "NC"; + gpio-reserved-ranges = <48 4>, /* SPI (eSE - embedded Secure Element) */ + <56 4>; /* SPI (fingerprint reader) */ + + qup_uart7_sleep_cts: qup-uart7-sleep-cts-state { + pins = "gpio28"; + function = "gpio"; + /* + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. + */ + bias-bus-hold; + }; + + qup_uart7_sleep_rts: qup-uart7-sleep-rts-state { + pins = "gpio29"; + function = "gpio"; + /* + * Configure pull-down on RTS. As RTS is active low + * signal, pull it low to indicate the BT SoC that it + * can wakeup the system anytime from suspend state by + * pulling RX low (by sending wakeup bytes). + */ + bias-pull-down; + }; + + qup_uart7_sleep_tx: qup-uart7-sleep-tx-state { + pins = "gpio30"; + function = "gpio"; + /* + * Configure pull-up on TX when it isn't actively driven + * to prevent BT SoC from receiving garbage during sleep. + */ + bias-pull-up; + }; + + qup_uart7_sleep_rx: qup-uart7-sleep-rx-state { + pins = "gpio31"; + function = "gpio"; + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module + * is floating which may cause spurious wakeups. + */ + bias-pull-up; + }; + + oled_reset_n: oled-reset-n-state { + pins = "gpio44"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + aw86224_reset_default: aw86224-reset-default-state { + pins = "gpio46"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + aw86224_int_default: aw86224-int-default-state { + pins = "gpio47"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + mdp_vsync_p: mdp-vsync-p-state { + pins = "gpio80"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + ts_int_n: ts-int-n-state { + pins = "gpio81"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + bt_en: bt-en-state { + pins = "gpio85"; + function = "gpio"; + output-low; + bias-disable; + }; + + ts_reset_n: ts-int-n-state { + pins = "gpio105"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; +}; + +&uart5 { + status = "okay"; +}; + +&uart7 { + /delete-property/ interrupts; + interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; + pinctrl-1 = <&qup_uart7_sleep_cts>, + <&qup_uart7_sleep_rts>, + <&qup_uart7_sleep_tx>, + <&qup_uart7_sleep_rx>; + pinctrl-names = "default", + "sleep"; + + status = "okay"; + + bluetooth: bluetooth { + compatible = "qcom,wcn6750-bt"; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + + max-speed = <3200000>; + + qcom,local-bd-address-broken; + }; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l7b_2p96>; + vcc-max-microamp = <800000>; + + vccq-supply = <&vreg_l9b_1p2>; + vccq-max-microamp = <900000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vdd_a_ufs_0_core>; + vdda-pll-supply = <&vdd_a_ufs_0_1p2>; + + status = "okay"; +}; + +&usb_1 { + /* USB 2.0 only */ + qcom,select-utmi-as-pipe-clk; + maximum-speed = "high-speed"; + + /* Remove USB3 phy */ + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; + + status = "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vdd_a_usbhs_core>; + vdda18-supply = <&vdd_a_usbhs_1p8>; + vdda33-supply = <&vdd_a_usbhs_3p1>; + + status = "okay"; +}; + +&venus { + firmware-name = "qcom/sm7325/motorola/dubai/vpu20_1v.mbn"; + + status = "okay"; +}; + +&wifi { + qcom,calibration-variant = "Motorola_dubai"; + + status = "okay"; +}; From 3b28947ef1f7630d272c59c0251dfa4e5ce7eb63 Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Fri, 3 Apr 2026 12:10:34 +0530 Subject: [PATCH 072/665] arm64: dts: qcom: qcs6490-rb3gen2: Enable CAN bus controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the MCP2518FD CAN controller on the QCS6490 RB3 Gen2 platform. The controller is connected via SPI3 and uses a 40 MHz oscillator. Signed-off-by: Viken Dadhaniya Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260403-can-spi-kodiak-dtsi-v1-1-4055e67dd3fc@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 22 ++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index e393ccf1884a..ceb68a890bf4 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -44,6 +44,14 @@ chosen { stdout-path = "serial0:115200n8"; }; + clocks { + mcp2518fd_osc: can-clk { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + #clock-cells = <0>; + }; + }; + dp-connector { compatible = "dp-connector"; label = "DP"; @@ -1208,6 +1216,20 @@ platform { }; }; +&spi3 { + status = "okay"; + + can@0 { + compatible = "microchip,mcp2518fd"; + reg = <0>; + interrupts-extended = <&tlmm 7 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mcp2518fd_osc>; + spi-max-frequency = <14000000>; + vdd-supply = <&vreg_l11c_2p8>; + microchip,xstbyen; + }; +}; + &swr2 { status = "okay"; From 1825ac5e2ad27ad72d1a550f6e19f8cc1ae90afe Mon Sep 17 00:00:00 2001 From: Pengyu Luo Date: Fri, 3 Apr 2026 20:07:52 +0800 Subject: [PATCH 073/665] arm64: dts: qcom: sc8280xp: Add ADSP FastRPC node Add the FastRPC node to enable offloading compute tasks to the ADSP via the FastRPC framework. Signed-off-by: Pengyu Luo Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260403120753.105869-1-mitltlatltl@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 27 ++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 761f229e8f47..ee02acd18856 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2966,6 +2966,33 @@ IPCC_MPROC_SIGNAL_GLINK_QMP label = "lpass"; qcom,remote-pid = <2>; + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + qcom,non-secure-domain; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x0c03 0x0>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x0c04 0x0>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x0c05 0x0>; + }; + }; + gpr { compatible = "qcom,gpr"; qcom,glink-channels = "adsp_apps"; From 3e6cd0c43cdf678622c19210bd1a70b04c8a79af Mon Sep 17 00:00:00 2001 From: Mani Chandana Ballary Kuntumalla Date: Thu, 2 Apr 2026 15:20:01 +0530 Subject: [PATCH 074/665] arm64: dts: qcom: lemans: add mdss1 display device nodes Add devicetree changes to enable second Mobile Display Subsystem (mdss1), Display Processing Unit(DPU), Display Port(DP), Display clock controller (dispcc1) and eDP PHYs on the Qualcomm Lemans platform. Signed-off-by: Mahadevan P Signed-off-by: Mani Chandana Ballary Kuntumalla Link: https://lore.kernel.org/r/20260402095003.3758176-2-quic_mkuntuma@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 289 ++++++++++++++++++++++++--- 1 file changed, 262 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index fe6e76351823..84a1e5ebbf5e 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -5470,7 +5470,7 @@ mdss0_dp1: displayport-controller@af5c000 { phys = <&mdss0_dp1_phy>; phy-names = "dp"; - operating-points-v2 = <&dp1_opp_table>; + operating-points-v2 = <&dp_opp_table>; power-domains = <&rpmhpd SA8775P_MMCX>; #sound-dai-cells = <0>; @@ -5495,30 +5495,6 @@ port@1 { mdss0_dp1_out: endpoint { }; }; }; - - dp1_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-162000000 { - opp-hz = /bits/ 64 <162000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-270000000 { - opp-hz = /bits/ 64 <270000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-540000000 { - opp-hz = /bits/ 64 <540000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-810000000 { - opp-hz = /bits/ 64 <810000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; }; }; @@ -7051,6 +7027,265 @@ compute-cb@3 { }; }; + mdss1: display-subsystem@22000000 { + compatible = "qcom,sa8775p-mdss"; + reg = <0x0 0x22000000 0x0 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP_CORE1_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_MDP_CORE1_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "mdp1-mem", + "cpu-cfg"; + + resets = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_BCR>; + + power-domains = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_GDSC>; + + clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP1_HF_AXI_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x1800 0x402>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + display-controller@22001000 { + compatible = "qcom,sa8775p-dpu"; + reg = <0x0 0x22001000 0x0 0x8f000>, + <0x0 0x220b0000 0x0 0x3000>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP1_HF_AXI_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdss0_mdp_opp_table>; + power-domains = <&rpmhpd SA8775P_MMCX>; + + interrupt-parent = <&mdss1>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu1_intf0_out: endpoint { + remote-endpoint = <&mdss1_dp0_in>; + }; + }; + + port@1 { + reg = <1>; + + dpu1_intf4_out: endpoint { + remote-endpoint = <&mdss1_dp1_in>; + }; + }; + }; + }; + + mdss1_dp0_phy: phy@220c2a00 { + compatible = "qcom,sa8775p-edp-phy"; + reg = <0x0 0x220c2a00 0x0 0x200>, + <0x0 0x220c2200 0x0 0xd0>, + <0x0 0x220c2600 0x0 0xd0>, + <0x0 0x220c2000 0x0 0x1c8>; + + clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; + clock-names = "aux", + "cfg_ahb", + "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss1_dp1_phy: phy@220c5a00 { + compatible = "qcom,sa8775p-edp-phy"; + reg = <0x0 0x220c5a00 0x0 0x200>, + <0x0 0x220c5200 0x0 0xd0>, + <0x0 0x220c5600 0x0 0xd0>, + <0x0 0x220c5000 0x0 0x1c8>; + + clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; + clock-names = "aux", + "cfg_ahb", + "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss1_dp0: displayport-controller@22154000 { + compatible = "qcom,sa8775p-dp"; + reg = <0x0 0x22154000 0x0 0x104>, + <0x0 0x22154200 0x0 0x0c0>, + <0x0 0x22155000 0x0 0x770>, + <0x0 0x22156000 0x0 0x09c>, + <0x0 0x22157000 0x0 0x09c>, + <0x0 0x22158000 0x0 0x09c>, + <0x0 0x22159000 0x0 0x09c>, + <0x0 0x2215a000 0x0 0x23c>, + <0x0 0x2215b000 0x0 0x23c>; + + interrupt-parent = <&mdss1>; + interrupts = <12>; + + clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel", + "stream_2_pixel", + "stream_3_pixel"; + assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; + assigned-clock-parents = <&mdss1_dp0_phy 0>, + <&mdss1_dp0_phy 1>, + <&mdss1_dp0_phy 1>, + <&mdss1_dp0_phy 1>, + <&mdss1_dp0_phy 1>; + phys = <&mdss1_dp0_phy>; + phy-names = "dp"; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd SA8775P_MMCX>; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss1_dp0_in: endpoint { + remote-endpoint = <&dpu1_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss1_dp0_out: endpoint { }; + }; + }; + }; + + mdss1_dp1: displayport-controller@2215c000 { + compatible = "qcom,sa8775p-dp"; + reg = <0x0 0x2215c000 0x0 0x104>, + <0x0 0x2215c200 0x0 0x0c0>, + <0x0 0x2215d000 0x0 0x770>, + <0x0 0x2215e000 0x0 0x09c>, + <0x0 0x2215f000 0x0 0x09c>, + <0x0 0x22160000 0x0 0x09c>, + <0x0 0x22161000 0x0 0x09c>, + <0x0 0x22162000 0x0 0x23c>, + <0x0 0x22163000 0x0 0x23c>; + + interrupt-parent = <&mdss1>; + interrupts = <13>; + + clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel"; + assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&mdss1_dp1_phy 0>, + <&mdss1_dp1_phy 1>, + <&mdss1_dp1_phy 1>; + phys = <&mdss1_dp1_phy>; + phy-names = "dp"; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd SA8775P_MMCX>; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss1_dp1_in: endpoint { + remote-endpoint = <&dpu1_intf4_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss1_dp1_out: endpoint { }; + }; + }; + + }; + }; + dispcc1: clock-controller@22100000 { compatible = "qcom,sa8775p-dispcc1"; reg = <0x0 0x22100000 0x0 0x20000>; @@ -7058,13 +7293,13 @@ dispcc1: clock-controller@22100000 { <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, - <0>, <0>, <0>, <0>, + <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>, + <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>, <0>, <0>, <0>, <0>; power-domains = <&rpmhpd SA8775P_MMCX>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - status = "disabled"; }; ethernet1: ethernet@23000000 { From fcc1a19f5bd5623c448e54b2ea6d50249abea77a Mon Sep 17 00:00:00 2001 From: Mani Chandana Ballary Kuntumalla Date: Thu, 2 Apr 2026 15:20:02 +0530 Subject: [PATCH 075/665] arm64: dts: qcom: lemans-ride: Enable mdss1 display Port This change enables DP controllers, DPTX0 and DPTX1 alongside their corresponding PHYs of mdss1 which corresponds to edp2 and edp3. Signed-off-by: Mani Chandana Ballary Kuntumalla Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260402095003.3758176-3-quic_mkuntuma@quicinc.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/lemans-ride-common.dtsi | 80 +++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi index 679e045a6d49..40f88498999b 100644 --- a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi @@ -182,6 +182,30 @@ dp1_connector_in: endpoint { }; }; + dp2-connector { + compatible = "dp-connector"; + label = "eDP2"; + type = "full-size"; + + port { + dp2_connector_in: endpoint { + remote-endpoint = <&mdss1_dp0_out>; + }; + }; + }; + + dp3-connector { + compatible = "dp-connector"; + label = "eDP3"; + type = "full-size"; + + port { + dp3_connector_in: endpoint { + remote-endpoint = <&mdss1_dp1_out>; + }; + }; + }; + dp-dsi0-connector { compatible = "dp-connector"; label = "DSI0"; @@ -641,6 +665,50 @@ &mdss0_dsi1_phy { status = "okay"; }; +&mdss1 { + status = "okay"; +}; + +&mdss1_dp0 { + pinctrl-0 = <&dp2_hot_plug_det>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&mdss1_dp0_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + remote-endpoint = <&dp2_connector_in>; +}; + +&mdss1_dp0_phy { + vdda-phy-supply = <&vreg_l1c>; + vdda-pll-supply = <&vreg_l4a>; + + status = "okay"; +}; + +&mdss1_dp1 { + pinctrl-0 = <&dp3_hot_plug_det>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&mdss1_dp1_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + remote-endpoint = <&dp3_connector_in>; +}; + +&mdss1_dp1_phy { + vdda-phy-supply = <&vreg_l1c>; + vdda-pll-supply = <&vreg_l4a>; + + status = "okay"; +}; + &pmm8654au_0_gpios { gpio-line-names = "DS_EN", "POFF_COMPLETE", @@ -818,6 +886,18 @@ dp1_hot_plug_det: dp1-hot-plug-det-state { bias-disable; }; + dp2_hot_plug_det: dp2-hot-plug-det-state { + pins = "gpio104"; + function = "edp2_hot"; + bias-disable; + }; + + dp3_hot_plug_det: dp3-hot-plug-det-state { + pins = "gpio103"; + function = "edp3_hot"; + bias-disable; + }; + io_expander_intr_active: io-expander-intr-active-state { pins = "gpio98"; function = "gpio"; From f0b64466e2896020ff2bcaa512bbcc4fea847635 Mon Sep 17 00:00:00 2001 From: Vishnu Saini Date: Thu, 2 Apr 2026 15:20:03 +0530 Subject: [PATCH 076/665] arm64: dts: qcom: lemans-evk-ifp-mezzanine: Enable mdss1 display Port Enable DP controllers, DPTX0 and DPTX1 alongside their corresponding PHYs of mdss1 which corresponds to eDP2 and eDP3. Signed-off-by: Vishnu Saini Signed-off-by: Mani Chandana Ballary Kuntumalla Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260402095003.3758176-4-quic_mkuntuma@quicinc.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/lemans-evk-ifp-mezzanine.dtso | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso index 268fc6b05d4b..44bd9b1a1765 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso @@ -11,6 +11,30 @@ &{/} { model = "Qualcomm Technologies, Inc. Lemans-evk IFP Mezzanine"; + dp2-connector { + compatible = "dp-connector"; + label = "eDP2"; + type = "full-size"; + + port { + dp2_connector_in: endpoint { + remote-endpoint = <&mdss1_dp0_out>; + }; + }; + }; + + dp3-connector { + compatible = "dp-connector"; + label = "eDP3"; + type = "full-size"; + + port { + dp3_connector_in: endpoint { + remote-endpoint = <&mdss1_dp1_out>; + }; + }; + }; + vreg_0p9: regulator-0v9 { compatible = "regulator-fixed"; regulator-name = "VREG_0P9"; @@ -141,6 +165,44 @@ mac_addr1: mac-addr@0 { }; }; +&mdss1 { + status = "okay"; +}; + +&mdss1_dp0 { + pinctrl-0 = <&dp2_hot_plug_det>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&mdss1_dp1 { + pinctrl-0 = <&dp3_hot_plug_det>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&mdss1_dp0_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + remote-endpoint = <&dp2_connector_in>; +}; + +&mdss1_dp1_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + remote-endpoint = <&dp3_connector_in>; +}; + +&mdss1_dp0_phy { + status = "okay"; +}; + +&mdss1_dp1_phy { + status = "okay"; +}; + &pcie0 { iommu-map = <0x0 &pcie_smmu 0x0 0x1>, <0x100 &pcie_smmu 0x1 0x1>, @@ -235,6 +297,18 @@ &serdes1 { }; &tlmm { + dp2_hot_plug_det: dp2-hot-plug-det-state { + pins = "gpio104"; + function = "edp2_hot"; + bias-disable; + }; + + dp3_hot_plug_det: dp3-hot-plug-det-state { + pins = "gpio103"; + function = "edp3_hot"; + bias-disable; + }; + ethernet1_default: ethernet1-default-state { ethernet1-mdc-pins { pins = "gpio20"; From 8f0cc929a4bad534c5a860a53d88912cf16d9c9c Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 1 Apr 2026 11:29:41 +0100 Subject: [PATCH 077/665] arm64: tegra: Fix Tegra234 MGBE PTP clock The Tegra MGBE PTP clock is incorrectly named as 'ptp-ref' and not 'ptp_ref' and this causing the initialisation of the PTP clock to fail. The device-tree binding doc for the device and the Tegra MGBE driver have been updated to use the correct name and so update the device-tree for Tegra234 as well. Fixes: 610cdf3186bc ("arm64: tegra: Add MGBE nodes on Tegra234") Signed-off-by: Jon Hunter Reviewed-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 04a95b6658ca..18220cdac9f9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -3605,7 +3605,7 @@ ethernet@6800000 { <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; - clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", + clock-names = "mgbe", "mac", "mac-divider", "ptp_ref", "rx-input-m", "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", "rx-pcs", "tx-pcs"; resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, @@ -3647,7 +3647,7 @@ ethernet@6900000 { <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>, <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>, <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>; - clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", + clock-names = "mgbe", "mac", "mac-divider", "ptp_ref", "rx-input-m", "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", "rx-pcs", "tx-pcs"; resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>, @@ -3689,7 +3689,7 @@ ethernet@6a00000 { <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>, <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>, <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>; - clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", + clock-names = "mgbe", "mac", "mac-divider", "ptp_ref", "rx-input-m", "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", "rx-pcs", "tx-pcs"; resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>, @@ -3731,7 +3731,7 @@ ethernet@6b00000 { <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>, <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>, <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>; - clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", + clock-names = "mgbe", "mac", "mac-divider", "ptp_ref", "rx-input-m", "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", "rx-pcs", "tx-pcs"; resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>, From d60ed99f1c9e0bdf1fcd713426f6213abe592c83 Mon Sep 17 00:00:00 2001 From: Manikanta Maddireddy Date: Wed, 25 Mar 2026 00:39:59 +0530 Subject: [PATCH 078/665] arm64: tegra: Add aspm-l1-entry-delay-ns to PCIe nodes Add the aspm-l1-entry-delay-ns device tree property to all PCIe Root Port and PCIe Endpoint nodes in tegra194.dtsi and tegra234.dtsi so that ASPM L1 entrance latency is configured from device tree. - Tegra194: 4000 ns (4 us) for both Root Port and Endpoint. - Tegra234: 8000 ns (8 us) for Root Port, 16000 ns (16 us) for Endpoint. Signed-off-by: Manikanta Maddireddy Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 9 +++++++++ arch/arm64/boot/dts/nvidia/tegra234.dtsi | 16 ++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 849694f751d9..1d659454a6f9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2382,6 +2382,7 @@ pcie@14100000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <4000>; bus-range = <0x0 0xff>; @@ -2434,6 +2435,7 @@ pcie@14120000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <4000>; bus-range = <0x0 0xff>; @@ -2486,6 +2488,7 @@ pcie@14140000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <4000>; bus-range = <0x0 0xff>; @@ -2538,6 +2541,7 @@ pcie@14160000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <4000>; bus-range = <0x0 0xff>; @@ -2583,6 +2587,7 @@ pcie-ep@14160000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <4000>; interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; @@ -2629,6 +2634,7 @@ pcie@14180000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <4000>; bus-range = <0x0 0xff>; @@ -2674,6 +2680,7 @@ pcie-ep@14180000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <4000>; interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; @@ -2723,6 +2730,7 @@ pcie@141a0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <4000>; bus-range = <0x0 0xff>; @@ -2771,6 +2779,7 @@ pcie-ep@141a0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <4000>; interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 18220cdac9f9..75bb9a0ad027 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -4532,6 +4532,7 @@ pcie@140a0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -4586,6 +4587,7 @@ pcie@140c0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -4640,6 +4642,7 @@ pcie@140e0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -4686,6 +4689,7 @@ pcie-ep@140e0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <16000>; interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; @@ -4734,6 +4738,7 @@ pcie@14100000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -4788,6 +4793,7 @@ pcie@14120000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -4842,6 +4848,7 @@ pcie@14140000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -4896,6 +4903,7 @@ pcie@14160000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -4937,6 +4945,7 @@ pcie-ep@14160000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <16000>; interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; @@ -4983,6 +4992,7 @@ pcie@14180000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -5037,6 +5047,7 @@ pcie@141a0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -5083,6 +5094,7 @@ pcie-ep@141a0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <16000>; interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; @@ -5131,6 +5143,7 @@ pcie@141c0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -5177,6 +5190,7 @@ pcie-ep@141c0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <16000>; interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; @@ -5225,6 +5239,7 @@ pcie@141e0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -5271,6 +5286,7 @@ pcie-ep@141e0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <16000>; interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; From 2bc564f46b00dc4f4331fc337277ff3f5fac8a4e Mon Sep 17 00:00:00 2001 From: Jihed Chaibi Date: Wed, 25 Mar 2026 23:34:11 +0100 Subject: [PATCH 079/665] ARM: dts: am335x-sl50: Fix audio bitclock and frame master endpoint The cpu_endpoint in mcasp0 specifies the TLV320AIC3106 codec as the bitclock and frame master, but the phandles point to the codec's port node (codec_port) rather than its endpoint node (codec_endpoint). audio-graph-card calls simple_util_parse_daifmt() with ep_codec set to the endpoint node (codec_endpoint). The function resolves the bitclock-master phandle and checks whether it equals ep_codec. Since codec_port is the parent of codec_endpoint, not the endpoint itself, the comparison always evaluates to false. This causes the mcasp0 CPU side to be silently configured as bitclock and frame master instead of the codec, which is the opposite of the intended configuration. Fix by pointing bitclock-master and frame-master to codec_endpoint. Fixes: e5f89dbdebc5 ("ARM: dts: am335x-sl50: use audio-graph-card for sound") Signed-off-by: Jihed Chaibi Link: https://patch.msgid.link/20260325223411.123666-1-jihed.chaibi.dev@gmail.com Signed-off-by: Kevin Hilman (TI) --- arch/arm/boot/dts/ti/omap/am335x-sl50.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/am335x-sl50.dts b/arch/arm/boot/dts/ti/omap/am335x-sl50.dts index 1dc4e344efd6..c5259eb7d21c 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-sl50.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-sl50.dts @@ -558,8 +558,8 @@ cpu_endpoint: endpoint { remote-endpoint = <&codec_endpoint>; dai-format = "dsp_b"; - bitclock-master = <&codec_port>; - frame-master = <&codec_port>; + bitclock-master = <&codec_endpoint>; + frame-master = <&codec_endpoint>; bitclock-inversion; clocks = <&audio_mclk>; }; From 0f63ba15dde8748ed3818fa6553c81b5296318f1 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 2 Apr 2026 13:27:05 +0200 Subject: [PATCH 080/665] dt-bindings: soc: renesas: Document MFIS IP core Document the Renesas Multifunctional Interface (MFIS) as found on the Renesas R-Car X5H (r8a78000) SoC. MFIS includes features like Mailbox/HW Spinlock/Product Register/Error Injection/Error Detection and the likes. Family-compatible values are not introduced here because MFIS is usually very different per SoC. Signed-off-by: Wolfram Sang Reviewed-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260402112709.13002-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- .../soc/renesas/renesas,r8a78000-mfis.yaml | 187 ++++++++++++++++++ .../dt-bindings/soc/renesas,r8a78000-mfis.h | 28 +++ 2 files changed, 215 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,r8a78000-mfis.yaml create mode 100644 include/dt-bindings/soc/renesas,r8a78000-mfis.h diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,r8a78000-mfis.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,r8a78000-mfis.yaml new file mode 100644 index 000000000000..eef8c0a59e9c --- /dev/null +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r8a78000-mfis.yaml @@ -0,0 +1,187 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/renesas/renesas,r8a78000-mfis.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas MFIS (Multifunctional Interface) controller + +maintainers: + - Wolfram Sang + +description: + The Renesas Multifunctional Interface (MFIS) provides various functionality + like mailboxes, hardware spinlocks, product identification, error injection, + error detection and such. Parts of it can be used for communication between + different CPU cores. Those cores can be in various domains like AP, RT, or + SCP. Often multiple domain-specific MFIS instances exist in one SoC. + +properties: + compatible: + enum: + - renesas,r8a78000-mfis # R-Car X5H (AP<->AP, with PRR) + - renesas,r8a78000-mfis-scp # R-Car X5H (AP<->SCP, without PRR) + + reg: + maxItems: 2 + + reg-names: + items: + - const: common + - const: mboxes + + interrupts: + minItems: 32 + maxItems: 128 + description: + The interrupts raised by the remote doorbells. + + interrupt-names: + minItems: 32 + maxItems: 128 + description: + An interrupt name is constructed with the prefix 'ch'. Then, the + channel number as specified in the documentation of the SoC. Finally, + the letter 'i' if the interrupt is raised by the IICR register. Or 'e' + if it is raised by the EICR register. + + "#hwlock-cells": + const: 1 + + "#mbox-cells": + const: 2 + description: + The first cell is the channel number as specified in the documentation + of the SoC. The second cell may specify flags as described in the file + . + +allOf: + - if: + properties: + compatible: + contains: + const: renesas,r8a78000-mfis + then: + properties: + interrupts: + minItems: 128 + interrupt-names: + minItems: 128 + items: + pattern: "^ch[0-9]+[ie]$" + + - if: + properties: + compatible: + contains: + const: renesas,r8a78000-mfis-scp + then: + properties: + interrupts: + maxItems: 32 + interrupt-names: + maxItems: 32 + items: + pattern: "^ch[0-9]+i$" + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - "#hwlock-cells" + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + #include + system-controller@189e0000 { + compatible = "renesas,r8a78000-mfis"; + reg = <0x189e0000 0x1000>, <0x18800000 0x40000>; + reg-names = "common", "mboxes"; + interrupts = , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , ; + interrupt-names = "ch0i", "ch0e", "ch1i", "ch1e", "ch2i", "ch2e", "ch3i", "ch3e", + "ch4i", "ch4e", "ch5i", "ch5e", "ch6i", "ch6e", "ch7i", "ch7e", + "ch8i", "ch8e", "ch9i", "ch9e", "ch10i", "ch10e", "ch11i", "ch11e", + "ch12i", "ch12e", "ch13i", "ch13e", "ch14i", "ch14e", "ch15i", "ch15e", + "ch16i", "ch16e", "ch17i", "ch17e", "ch18i", "ch18e", "ch19i", "ch19e", + "ch20i", "ch20e", "ch21i", "ch21e", "ch22i", "ch22e", "ch23i", "ch23e", + "ch24i", "ch24e", "ch25i", "ch25e", "ch26i", "ch26e", "ch27i", "ch27e", + "ch28i", "ch28e", "ch29i", "ch29e", "ch30i", "ch30e", "ch31i", "ch31e", + "ch32i", "ch32e", "ch33i", "ch33e", "ch34i", "ch34e", "ch35i", "ch35e", + "ch36i", "ch36e", "ch37i", "ch37e", "ch38i", "ch38e", "ch39i", "ch39e", + "ch40i", "ch40e", "ch41i", "ch41e", "ch42i", "ch42e", "ch43i", "ch43e", + "ch44i", "ch44e", "ch45i", "ch45e", "ch46i", "ch46e", "ch47i", "ch47e", + "ch48i", "ch48e", "ch49i", "ch49e", "ch50i", "ch50e", "ch51i", "ch51e", + "ch52i", "ch52e", "ch53i", "ch53e", "ch54i", "ch54e", "ch55i", "ch55e", + "ch56i", "ch56e", "ch57i", "ch57e", "ch58i", "ch58e", "ch59i", "ch59e", + "ch60i", "ch60e", "ch61i", "ch61e", "ch62i", "ch62e", "ch63i", "ch63e"; + #hwlock-cells = <1>; + #mbox-cells = <2>; + }; diff --git a/include/dt-bindings/soc/renesas,r8a78000-mfis.h b/include/dt-bindings/soc/renesas,r8a78000-mfis.h new file mode 100644 index 000000000000..147a8aefc643 --- /dev/null +++ b/include/dt-bindings/soc/renesas,r8a78000-mfis.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +#ifndef _DT_BINDINGS_SOC_RENESAS_R8A78000_MFIS_H +#define _DT_BINDINGS_SOC_RENESAS_R8A78000_MFIS_H + +/* + * Constants for the second mbox-cell of the Renesas MFIS IP core. To be treated + * as bit flags which can be ORed. + */ + +/* + * MFIS HW design before r8a78001 requires a channel to be marked as either + * TX or RX. + */ +#define MFIS_CHANNEL_TX (0 << 0) +#define MFIS_CHANNEL_RX (1 << 0) + +/* + * MFIS variants before r8a78001 work with pairs of IICR and EICR registers. + * Usually, it is specified in the datasheets which of the two a specific core + * should use. Then, it does not need extra description in DT. For plain MFIS + * of r8a78000, this is selectable, though. According to the system design and + * the firmware in use, these channels need to be marked. This is not needed + * with other versions of the MFIS, not even with MFIS-SCP of r8a78000. + */ +#define MFIS_CHANNEL_IICR (0 << 1) +#define MFIS_CHANNEL_EICR (1 << 1) + +#endif /* _DT_BINDINGS_SOC_RENESAS_R8A78000_MFIS_H */ From b0822a883408f32d494ce9cdc26f4266774cf3f1 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 27 Apr 2026 10:03:06 +0300 Subject: [PATCH 081/665] dt-bindings: memory: Document Tegra114 Memory Controller Add Tegra114 support into existing Tegra124 MC schema with the most notable difference in the amount of EMEM timings. Each memory client has unique hardware ID, add these IDs. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260427070312.81679-2-clamor95@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../nvidia,tegra124-mc.yaml | 31 +++------ include/dt-bindings/memory/tegra114-mc.h | 67 +++++++++++++++++++ 2 files changed, 75 insertions(+), 23 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml index 7b18b4d11e0a..f8747cebb680 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml @@ -19,7 +19,9 @@ description: | properties: compatible: - const: nvidia,tegra124-mc + enum: + - nvidia,tegra114-mc + - nvidia,tegra124-mc reg: maxItems: 1 @@ -64,29 +66,12 @@ patternProperties: nvidia,emem-configuration: $ref: /schemas/types.yaml#/definitions/uint32-array - description: | + description: Values to be written to the EMEM register block. See section - "15.6.1 MC Registers" in the TRM. - items: - - description: MC_EMEM_ARB_CFG - - description: MC_EMEM_ARB_OUTSTANDING_REQ - - description: MC_EMEM_ARB_TIMING_RCD - - description: MC_EMEM_ARB_TIMING_RP - - description: MC_EMEM_ARB_TIMING_RC - - description: MC_EMEM_ARB_TIMING_RAS - - description: MC_EMEM_ARB_TIMING_FAW - - description: MC_EMEM_ARB_TIMING_RRD - - description: MC_EMEM_ARB_TIMING_RAP2PRE - - description: MC_EMEM_ARB_TIMING_WAP2PRE - - description: MC_EMEM_ARB_TIMING_R2R - - description: MC_EMEM_ARB_TIMING_W2W - - description: MC_EMEM_ARB_TIMING_R2W - - description: MC_EMEM_ARB_TIMING_W2R - - description: MC_EMEM_ARB_DA_TURNS - - description: MC_EMEM_ARB_DA_COVERS - - description: MC_EMEM_ARB_MISC0 - - description: MC_EMEM_ARB_MISC1 - - description: MC_EMEM_ARB_RING1_THROTTLE + "20.11.1 MC Registers" in the Tegea114 TRM or + "15.6.1 MC Registers" in the Tegra124 TRM. + minItems: 18 + maxItems: 19 required: - clock-frequency diff --git a/include/dt-bindings/memory/tegra114-mc.h b/include/dt-bindings/memory/tegra114-mc.h index dfe99c8a5ba5..5e0d6a1b91f2 100644 --- a/include/dt-bindings/memory/tegra114-mc.h +++ b/include/dt-bindings/memory/tegra114-mc.h @@ -40,4 +40,71 @@ #define TEGRA114_MC_RESET_VDE 14 #define TEGRA114_MC_RESET_VI 15 +#define TEGRA114_MC_PTCR 0 +#define TEGRA114_MC_DISPLAY0A 1 +#define TEGRA114_MC_DISPLAY0AB 2 +#define TEGRA114_MC_DISPLAY0B 3 +#define TEGRA114_MC_DISPLAY0BB 4 +#define TEGRA114_MC_DISPLAY0C 5 +#define TEGRA114_MC_DISPLAY0CB 6 +#define TEGRA114_MC_DISPLAY1B 7 +#define TEGRA114_MC_DISPLAY1BB 8 +#define TEGRA114_MC_EPPUP 9 +#define TEGRA114_MC_G2PR 10 +#define TEGRA114_MC_G2SR 11 +#define TEGRA114_MC_MPEUNIFBR 12 +#define TEGRA114_MC_VIRUV 13 +#define TEGRA114_MC_AFIR 14 +#define TEGRA114_MC_AVPCARM7R 15 +#define TEGRA114_MC_DISPLAYHC 16 +#define TEGRA114_MC_DISPLAYHCB 17 +#define TEGRA114_MC_FDCDRD 18 +#define TEGRA114_MC_FDCDRD2 19 +#define TEGRA114_MC_G2DR 20 +#define TEGRA114_MC_HDAR 21 +#define TEGRA114_MC_HOST1XDMAR 22 +#define TEGRA114_MC_HOST1XR 23 +#define TEGRA114_MC_IDXSRD 24 +#define TEGRA114_MC_IDXSRD2 25 +#define TEGRA114_MC_MPE_IPRED 26 +#define TEGRA114_MC_MPEAMEMRD 27 +#define TEGRA114_MC_MPECSRD 28 +#define TEGRA114_MC_PPCSAHBDMAR 29 +#define TEGRA114_MC_PPCSAHBSLVR 30 +#define TEGRA114_MC_SATAR 31 +#define TEGRA114_MC_TEXSRD 32 +#define TEGRA114_MC_TEXSRD2 33 +#define TEGRA114_MC_VDEBSEVR 34 +#define TEGRA114_MC_VDEMBER 35 +#define TEGRA114_MC_VDEMCER 36 +#define TEGRA114_MC_VDETPER 37 +#define TEGRA114_MC_MPCORELPR 38 +#define TEGRA114_MC_MPCORER 39 +#define TEGRA114_MC_EPPU 40 +#define TEGRA114_MC_EPPV 41 +#define TEGRA114_MC_EPPY 42 +#define TEGRA114_MC_MPEUNIFBW 43 +#define TEGRA114_MC_VIWSB 44 +#define TEGRA114_MC_VIWU 45 +#define TEGRA114_MC_VIWV 46 +#define TEGRA114_MC_VIWY 47 +#define TEGRA114_MC_G2DW 48 +#define TEGRA114_MC_AFIW 49 +#define TEGRA114_MC_AVPCARM7W 50 +#define TEGRA114_MC_FDCDWR 51 +#define TEGRA114_MC_FDCDWR2 52 +#define TEGRA114_MC_HDAW 53 +#define TEGRA114_MC_HOST1XW 54 +#define TEGRA114_MC_ISPW 55 +#define TEGRA114_MC_MPCORELPW 56 +#define TEGRA114_MC_MPCOREW 57 +#define TEGRA114_MC_MPECSWR 58 +#define TEGRA114_MC_PPCSAHBDMAW 59 +#define TEGRA114_MC_PPCSAHBSLVW 60 +#define TEGRA114_MC_SATAW 61 +#define TEGRA114_MC_VDEBSEVW 62 +#define TEGRA114_MC_VDEDBGW 63 +#define TEGRA114_MC_VDEMBEW 64 +#define TEGRA114_MC_VDETPMW 65 + #endif From a4f97f9467661602bd6bf614bcee884502794d43 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 27 Apr 2026 10:03:08 +0300 Subject: [PATCH 082/665] dt-bindings: memory: Document Tegra114 External Memory Controller Include Tegra114 support into existing Tegra124 EMC schema with the most notable difference being the amount of EMC timings and a few SoC unique entries. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260427070312.81679-4-clamor95@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../nvidia,tegra124-emc.yaml | 174 +++--------------- 1 file changed, 26 insertions(+), 148 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml index f5f03bf36413..9398aae49093 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml @@ -16,7 +16,9 @@ description: | properties: compatible: - const: nvidia,tegra124-emc + enum: + - nvidia,tegra114-emc + - nvidia,tegra124-emc reg: maxItems: 1 @@ -29,6 +31,9 @@ properties: items: - const: emc + interrupts: + maxItems: 1 + "#interconnect-cells": const: 0 @@ -164,153 +169,12 @@ patternProperties: nvidia,emc-configuration: description: EMC timing characterization data. These are the registers (see - section "15.6.2 EMC Registers" in the TRM) whose values need to + section "20.11.2 EMC Registers" in the Tegra114 TRM or section + "15.6.2 EMC Registers" in the Tegra124 TRM) whose values need to be specified, according to the board documentation. $ref: /schemas/types.yaml#/definitions/uint32-array - items: - - description: EMC_RC - - description: EMC_RFC - - description: EMC_RFC_SLR - - description: EMC_RAS - - description: EMC_RP - - description: EMC_R2W - - description: EMC_W2R - - description: EMC_R2P - - description: EMC_W2P - - description: EMC_RD_RCD - - description: EMC_WR_RCD - - description: EMC_RRD - - description: EMC_REXT - - description: EMC_WEXT - - description: EMC_WDV - - description: EMC_WDV_MASK - - description: EMC_QUSE - - description: EMC_QUSE_WIDTH - - description: EMC_IBDLY - - description: EMC_EINPUT - - description: EMC_EINPUT_DURATION - - description: EMC_PUTERM_EXTRA - - description: EMC_PUTERM_WIDTH - - description: EMC_PUTERM_ADJ - - description: EMC_CDB_CNTL_1 - - description: EMC_CDB_CNTL_2 - - description: EMC_CDB_CNTL_3 - - description: EMC_QRST - - description: EMC_QSAFE - - description: EMC_RDV - - description: EMC_RDV_MASK - - description: EMC_REFRESH - - description: EMC_BURST_REFRESH_NUM - - description: EMC_PRE_REFRESH_REQ_CNT - - description: EMC_PDEX2WR - - description: EMC_PDEX2RD - - description: EMC_PCHG2PDEN - - description: EMC_ACT2PDEN - - description: EMC_AR2PDEN - - description: EMC_RW2PDEN - - description: EMC_TXSR - - description: EMC_TXSRDLL - - description: EMC_TCKE - - description: EMC_TCKESR - - description: EMC_TPD - - description: EMC_TFAW - - description: EMC_TRPAB - - description: EMC_TCLKSTABLE - - description: EMC_TCLKSTOP - - description: EMC_TREFBW - - description: EMC_FBIO_CFG6 - - description: EMC_ODT_WRITE - - description: EMC_ODT_READ - - description: EMC_FBIO_CFG5 - - description: EMC_CFG_DIG_DLL - - description: EMC_CFG_DIG_DLL_PERIOD - - description: EMC_DLL_XFORM_DQS0 - - description: EMC_DLL_XFORM_DQS1 - - description: EMC_DLL_XFORM_DQS2 - - description: EMC_DLL_XFORM_DQS3 - - description: EMC_DLL_XFORM_DQS4 - - description: EMC_DLL_XFORM_DQS5 - - description: EMC_DLL_XFORM_DQS6 - - description: EMC_DLL_XFORM_DQS7 - - description: EMC_DLL_XFORM_DQS8 - - description: EMC_DLL_XFORM_DQS9 - - description: EMC_DLL_XFORM_DQS10 - - description: EMC_DLL_XFORM_DQS11 - - description: EMC_DLL_XFORM_DQS12 - - description: EMC_DLL_XFORM_DQS13 - - description: EMC_DLL_XFORM_DQS14 - - description: EMC_DLL_XFORM_DQS15 - - description: EMC_DLL_XFORM_QUSE0 - - description: EMC_DLL_XFORM_QUSE1 - - description: EMC_DLL_XFORM_QUSE2 - - description: EMC_DLL_XFORM_QUSE3 - - description: EMC_DLL_XFORM_QUSE4 - - description: EMC_DLL_XFORM_QUSE5 - - description: EMC_DLL_XFORM_QUSE6 - - description: EMC_DLL_XFORM_QUSE7 - - description: EMC_DLL_XFORM_ADDR0 - - description: EMC_DLL_XFORM_ADDR1 - - description: EMC_DLL_XFORM_ADDR2 - - description: EMC_DLL_XFORM_ADDR3 - - description: EMC_DLL_XFORM_ADDR4 - - description: EMC_DLL_XFORM_ADDR5 - - description: EMC_DLL_XFORM_QUSE8 - - description: EMC_DLL_XFORM_QUSE9 - - description: EMC_DLL_XFORM_QUSE10 - - description: EMC_DLL_XFORM_QUSE11 - - description: EMC_DLL_XFORM_QUSE12 - - description: EMC_DLL_XFORM_QUSE13 - - description: EMC_DLL_XFORM_QUSE14 - - description: EMC_DLL_XFORM_QUSE15 - - description: EMC_DLI_TRIM_TXDQS0 - - description: EMC_DLI_TRIM_TXDQS1 - - description: EMC_DLI_TRIM_TXDQS2 - - description: EMC_DLI_TRIM_TXDQS3 - - description: EMC_DLI_TRIM_TXDQS4 - - description: EMC_DLI_TRIM_TXDQS5 - - description: EMC_DLI_TRIM_TXDQS6 - - description: EMC_DLI_TRIM_TXDQS7 - - description: EMC_DLI_TRIM_TXDQS8 - - description: EMC_DLI_TRIM_TXDQS9 - - description: EMC_DLI_TRIM_TXDQS10 - - description: EMC_DLI_TRIM_TXDQS11 - - description: EMC_DLI_TRIM_TXDQS12 - - description: EMC_DLI_TRIM_TXDQS13 - - description: EMC_DLI_TRIM_TXDQS14 - - description: EMC_DLI_TRIM_TXDQS15 - - description: EMC_DLL_XFORM_DQ0 - - description: EMC_DLL_XFORM_DQ1 - - description: EMC_DLL_XFORM_DQ2 - - description: EMC_DLL_XFORM_DQ3 - - description: EMC_DLL_XFORM_DQ4 - - description: EMC_DLL_XFORM_DQ5 - - description: EMC_DLL_XFORM_DQ6 - - description: EMC_DLL_XFORM_DQ7 - - description: EMC_XM2CMDPADCTRL - - description: EMC_XM2CMDPADCTRL4 - - description: EMC_XM2CMDPADCTRL5 - - description: EMC_XM2DQPADCTRL2 - - description: EMC_XM2DQPADCTRL3 - - description: EMC_XM2CLKPADCTRL - - description: EMC_XM2CLKPADCTRL2 - - description: EMC_XM2COMPPADCTRL - - description: EMC_XM2VTTGENPADCTRL - - description: EMC_XM2VTTGENPADCTRL2 - - description: EMC_XM2VTTGENPADCTRL3 - - description: EMC_XM2DQSPADCTRL3 - - description: EMC_XM2DQSPADCTRL4 - - description: EMC_XM2DQSPADCTRL5 - - description: EMC_XM2DQSPADCTRL6 - - description: EMC_DSR_VTTGEN_DRV - - description: EMC_TXDSRVTTGEN - - description: EMC_FBIO_SPARE - - description: EMC_ZCAL_WAIT_CNT - - description: EMC_MRS_WAIT_CNT2 - - description: EMC_CTT - - description: EMC_CTT_DURATION - - description: EMC_CFG_PIPE - - description: EMC_DYN_SELF_REF_CONTROL - - description: EMC_QPOP + minItems: 97 + maxItems: 143 required: - clock-frequency @@ -318,9 +182,7 @@ patternProperties: - nvidia,emc-auto-cal-config2 - nvidia,emc-auto-cal-config3 - nvidia,emc-auto-cal-interval - - nvidia,emc-bgbias-ctl0 - nvidia,emc-cfg - - nvidia,emc-cfg-2 - nvidia,emc-ctt-term-ctrl - nvidia,emc-mode-1 - nvidia,emc-mode-2 @@ -344,6 +206,22 @@ required: - "#interconnect-cells" - operating-points-v2 +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra124-emc + then: + patternProperties: + "^emc-timings-[0-9]+$": + patternProperties: + "^timing-[0-9]+$": + required: + - nvidia,emc-bgbias-ctl0 + - nvidia,emc-cfg-2 + additionalProperties: false examples: From 990c229608000831f435d5dbad982f710401fda1 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Tue, 24 Mar 2026 14:15:55 +0800 Subject: [PATCH 083/665] dt-bindings: arm: fsl: Add compatible for i.MX95 15x15 audio board (version 2) Introduce a new DT compatible string for the NXP i.MX95 15x15 audio board (version 2). i.MX Audio Board is a configurable and functional audio processing platform. Integrating a variety of audio input and output interfaces into the system, the i.MX Audio Board supports HDMI input, HDMI eARC, S/PDIF I/O, 2-ch ADC line-in, 24-ch DAC line-out and more. Based on these features, rich audio application cases can be realized. Signed-off-by: Shengjiu Wang Acked-by: Krzysztof Kozlowski Signed-off-by: Frank Li --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 0023cd126807..7ce4176d19f5 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1482,6 +1482,7 @@ properties: - description: i.MX95 based Boards items: - enum: + - fsl,imx95-15x15-ab2 # i.MX95 15x15 Audio Board V2 - fsl,imx95-15x15-evk # i.MX95 15x15 EVK Board - fsl,imx95-15x15-frdm # i.MX95 15x15 FRDM Board - fsl,imx95-19x19-evk # i.MX95 19x19 EVK Board From 7b5d318616888360a93cf0830705ce51b5452078 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Tue, 24 Mar 2026 14:15:56 +0800 Subject: [PATCH 084/665] arm64: dts: add support for NXP i.MX95 15x15 audio board (version 2) i.MX Audio Board is a configurable and functional audio processing platform. Integrating a variety of audio input and output interfaces into the system, the i.MX Audio Board supports HDMI input, HDMI eARC, S/PDIF I/O, 2-ch ADC line-in, 24-ch DAC line-out and more. Based on these features, rich audio application cases can be realized. This is a basic device tree supporting with i.MX95 15x15 SoC and Audio board (version 2). - Six Cortex-A55 - NXP PCAL6416 GPIO expanders - RGB LEDs via GPIO expander - LPI2C1, LPI2C2, LPI2C3 controllers - LPUART1 (console) - USDHC1 (eMMC), USDHC2 (SD) - Three DAC (AK4458) - One ADC (AK5552) Signed-off-by: Shengjiu Wang Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx95-15x15-ab2.dts | 669 ++++++++++++++++++ 2 files changed, 670 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx95-15x15-ab2.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 711e36cc2c99..cbd6c299ff81 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -502,6 +502,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx93w-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx943-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-ab2.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-frdm.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-ab2.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-ab2.dts new file mode 100644 index 000000000000..f6829145f396 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-ab2.dts @@ -0,0 +1,669 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 NXP + */ + +/dts-v1/; + +#include +#include "imx95.dtsi" + +#define BRD_SM_CTRL_SD3_WAKE 0x8000 +#define BRD_SM_CTRL_PCIE1_WAKE 0x8001 +#define BRD_SM_CTRL_BT_WAKE 0x8002 +#define BRD_SM_CTRL_PCIE2_WAKE 0x8003 +#define BRD_SM_CTRL_BUTTON 0x8004 + +/ { + compatible = "fsl,imx95-15x15-ab2", "fsl,imx95"; + model = "NXP i.MX95 CPU on AB2"; + + aliases { + ethernet0 = &enetc_port0; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + i2c3 = &lpi2c4; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &lpuart1; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + stdout-path = &lpuart1; + }; + + reg_ab2_ana_pwr: regulator-ab2-ana-pwr { + compatible = "regulator-fixed"; + regulator-name = "ab2_ana_pwr"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + gpio = <&pcal6524 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { + compatible = "regulator-fixed"; + regulator-name = "ab2_vdd_pwr_5v0"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + gpio = <&pcal6524 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VDD_SD2_3V3"; + off-on-delay-us = <12000>; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x7f000000>; + reusable; + size = <0 0x3c000000>; + linux,cma-default; + }; + + vpu_boot: vpu-boot@a0000000 { + reg = <0 0xa0000000 0 0x100000>; + no-map; + }; + }; + + sound-ak4458 { + compatible = "fsl,imx-audio-card"; + model = "ak4458-audio"; + + pri-dai-link { + format = "i2s"; + link-name = "akcodec"; + fsl,mclk-equal-bclk; + + codec { + sound-dai = <&ak4458_1>, <&ak4458_2>; + }; + + cpu { + sound-dai = <&sai2>; + }; + }; + }; + + sound-ak5552 { + compatible = "fsl,imx-audio-card"; + model = "ak5552-audio"; + + pri-dai-link { + format = "i2s"; + link-name = "akcodec"; + fsl,mclk-equal-bclk; + + codec { + sound-dai = <&ak5552>; + }; + + cpu { + sound-dai = <&sai3>; + }; + }; + }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + + pri-dai-link { + format = "i2s"; + link-name = "micfil hifi"; + + cpu { + sound-dai = <&micfil>; + }; + }; + }; + + sound-xcvr { + compatible = "fsl,imx-audio-card"; + model = "imx-audio-xcvr"; + + pri-dai-link { + link-name = "XCVR PCM"; + + cpu { + sound-dai = <&xcvr>; + }; + }; + }; + + memory@80000000 { + reg = <0x0 0x80000000 0 0x80000000>; + device_type = "memory"; + }; +}; + +&enetc_port0 { + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_enetc0>; + pinctrl-names = "default"; + status = "okay"; +}; + +&lpi2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&lpi2c2 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-names = "default"; + status = "okay"; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio5>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + pinctrl-0 = <&pinctrl_pcal6524>; + pinctrl-names = "default"; + }; +}; + +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-names = "default"; + status = "okay"; + + ak4458_1: audio-codec@10 { + compatible = "asahi-kasei,ak4458"; + reg = <0x10>; + #sound-dai-cells = <0>; + AVDD-supply = <®_ab2_ana_pwr>; + DVDD-supply = <®_ab2_ana_pwr>; + reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>; + sound-name-prefix = "0"; + }; + + ak4458_3: audio-codec@11 { + compatible = "asahi-kasei,ak4458"; + reg = <0x11>; + #sound-dai-cells = <0>; + AVDD-supply = <®_ab2_ana_pwr>; + DVDD-supply = <®_ab2_ana_pwr>; + reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>; + status = "disabled"; + }; + + ak4458_2: audio-codec@12 { + compatible = "asahi-kasei,ak4458"; + reg = <0x12>; + #sound-dai-cells = <0>; + AVDD-supply = <®_ab2_ana_pwr>; + DVDD-supply = <®_ab2_ana_pwr>; + reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>; + sound-name-prefix = "1"; + }; + + ak5552: audio-codec@13 { + compatible = "asahi-kasei,ak5552"; + reg = <0x13>; + #sound-dai-cells = <0>; + AVDD-supply = <®_ab2_ana_pwr>; + DVDD-supply = <®_ab2_ana_pwr>; + reset-gpios = <&pca6416 3 GPIO_ACTIVE_LOW>; + }; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + }; +}; + +&lpi2c4 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c4>; + pinctrl-names = "default"; + status = "okay"; +}; + +&lpuart1 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&micfil { + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_PDM>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <49152000>; + #sound-dai-cells = <0>; + pinctrl-0 = <&pinctrl_pdm>; + pinctrl-names = "default"; + status = "okay"; +}; + +&netc_blk_ctrl { + status = "okay"; +}; + +&netc_emdio { + pinctrl-0 = <&pinctrl_emdio>; + pinctrl-names = "default"; + status = "okay"; + + ethphy0: ethernet-phy@1 { + reg = <1>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&pcal6524 4 GPIO_ACTIVE_LOW>; + realtek,clkout-disable; + }; +}; + +&netcmix_blk_ctrl { + status = "okay"; +}; + +&sai2 { + clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>, <&dummy>, + <&scmi_clk IMX95_CLK_SAI2>, <&dummy>, + <&dummy>, <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI2>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <12288000>; + #sound-dai-cells = <0>; + pinctrl-0 = <&pinctrl_sai2>; + pinctrl-names = "default"; + fsl,sai-asynchronous; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&sai3 { + clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>, <&dummy>, + <&scmi_clk IMX95_CLK_SAI3>, <&dummy>, + <&dummy>, <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI3>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <12288000>; + #sound-dai-cells = <0>; + pinctrl-0 = <&pinctrl_sai3>; + pinctrl-names = "default"; + fsl,sai-asynchronous; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&sai5 { + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI5>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <12288000>; + #sound-dai-cells = <0>; + pinctrl-0 = <&pinctrl_sai5>; + pinctrl-names = "default"; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&scmi_iomuxc { + pinctrl_emdio: emdiogrp { + fsl,pins = < + IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x50e + IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e + >; + }; + + pinctrl_enetc0: enetc0grp { + fsl,pins = < + IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e + IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e + IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e + IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e + IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e + IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e + IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e + IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e + IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e + IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e + IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e + IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x40000b9e + IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e + IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = < + IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e + IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e + IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x31e + IMX95_PAD_GPIO_IO06__AONMIX_TOP_PDM_BIT_STREAM_BIT1 0x31e + IMX95_PAD_GPIO_IO12__AONMIX_TOP_PDM_BIT_STREAM_BIT2 0x31e + IMX95_PAD_GPIO_IO13__AONMIX_TOP_PDM_BIT_STREAM_BIT3 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x31e + IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK 0x31e + IMX95_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC 0x31e + IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0 0x31e + IMX95_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_BIT1 0x31e + IMX95_PAD_ENET2_TD1__NETCMIX_TOP_SAI2_RX_DATA_BIT2 0x31e + IMX95_PAD_ENET2_TD0__NETCMIX_TOP_SAI2_RX_DATA_BIT3 0x31e + IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x31e + IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x31e + IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0 0x31e + IMX95_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_BIT1 0x31e + IMX95_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_BIT2 0x31e + IMX95_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_BIT3 0x31e + IMX95_PAD_XSPI1_DATA0__NETCMIX_TOP_SAI2_TX_DATA_BIT4 0x31e + IMX95_PAD_XSPI1_DATA1__NETCMIX_TOP_SAI2_TX_DATA_BIT5 0x31e + IMX95_PAD_XSPI1_DATA2__NETCMIX_TOP_SAI2_TX_DATA_BIT6 0x31e + IMX95_PAD_XSPI1_DATA3__NETCMIX_TOP_SAI2_TX_DATA_BIT7 0x31e + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e + IMX95_PAD_GPIO_IO18__SAI3_RX_BCLK 0x31e + IMX95_PAD_GPIO_IO19__SAI3_RX_SYNC 0x31e + IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x31e + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0 0x31e + IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0 0x31e + IMX95_PAD_XSPI1_SS1_B__SAI5_RX_BCLK 0x31e + IMX95_PAD_XSPI1_DQS__SAI5_RX_SYNC 0x31e + + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + IMX95_PAD_GPIO_IO22__SPDIF_IN 0x31e + IMX95_PAD_GPIO_IO23__SPDIF_OUT 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e + IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; +}; + +&scmi_misc { + nxp,ctrl-ids = , + , + , + , + ; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + adp-disable; + dr_mode = "host"; + hnp-disable; + srp-disable; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&usdhc1 { + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc1>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + fsl,tuning-step = <1>; + status = "okay"; +}; + +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&xcvr { + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_SPDIF>, + <&dummy>, + <&scmi_clk IMX95_CLK_AUDIOXCVR>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>; + clock-names = "ipg", "phy", "spba", "pll_ipg", "pll8k", "pll11k"; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SPDIF>, + <&scmi_clk IMX95_CLK_AUDIOXCVR>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; + assigned-clock-rates = <3932160000>, <3612672000>, + <393216000>, <361267200>, + <12288000>, <0>; + #sound-dai-cells = <0>; + pinctrl-0 = <&pinctrl_spdif>; + pinctrl-names = "default"; + status = "okay"; +}; From 0372cc5776e7fd5570884aed0c1e9a8a546cad66 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 5 Mar 2026 13:06:16 -0500 Subject: [PATCH 085/665] ARM: dts: imx6ul-var-som: fix warning for non-existent dc-supply property The dc-supply property is non-existent in Linux now, nor when this DTS file was created when importing it from Variscite own kernel. Therefore remove it to fix this warning: imx6ul-var-som-concerto.dtb: cpu@0 (arm,cortex-a7): Unevaluated properties are not allowed ('dc-supply' was unexpected) from schema $id: http://devicetree.org/schemas/arm/cpus.yaml Fixes: 9d6a67d9c7a9 ("ARM: dts: imx6ul: Add Variscite VAR-SOM-MX6UL SoM support") Cc: stable@kernel.org Signed-off-by: Hugo Villeneuve Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi index 4e536e0252de..3fb5e2fb6877 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi @@ -45,10 +45,6 @@ &clks { assigned-clock-rates = <786432000>; }; -&cpu0 { - dc-supply = <®_gpio_dvfs>; -}; - &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>, <&pinctrl_enet1_mdio>; From f9abbeb3e674ff7ccee647e8dd9e43c1e1b16854 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 5 Mar 2026 13:06:17 -0500 Subject: [PATCH 086/665] ARM: dts: imx6ul-var-som: fix warning for boolean property with a value dmesg warning: OF: /soc/bus@2000000/ethernet@20b4000/mdio/ethernet-phy@3: Read of boolean property 'micrel,rmii-reference-clock-select-25-mhz' with a value. Using of_property_read_bool() for non-boolean properties is deprecated and results in a warning during runtime since commit c141ecc3cecd ("of: Warn when of_property_read_bool() is used on non-boolean properties") micrel,rmii-reference-clock-select-25-mhz is a boolean property and should not have a value, so remove it. Signed-off-by: Hugo Villeneuve Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts index 9ff3b374a2b3..085985356668 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts @@ -79,7 +79,7 @@ ethphy1: ethernet-phy@3 { reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; reset-assert-us = <100000>; micrel,led-mode = <0>; - micrel,rmii-reference-clock-select-25-mhz = <1>; + micrel,rmii-reference-clock-select-25-mhz; }; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi index 3fb5e2fb6877..30032be6fdd5 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi @@ -64,7 +64,7 @@ ethphy0: ethernet-phy@1 { reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; reset-assert-us = <100000>; micrel,led-mode = <1>; - micrel,rmii-reference-clock-select-25-mhz = <1>; + micrel,rmii-reference-clock-select-25-mhz; }; }; }; From 8ce202ed73e037175dbd31c03bed446acff72cc0 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 5 Mar 2026 13:06:18 -0500 Subject: [PATCH 087/665] ARM: dts: imx6ul-var-som: change incorrect VAR-SOM-MX6UL references There is no Variscite module named VAR-SOM-MX6UL, but there is VAR-SOM-MX6 and also VAR-SOM-6UL, so it is confusing at first to know to which one it refers to. The imx6ul-var-som* dts/dtsi supports only the VAR-SOM-6UL [1], not VAR-SOM-MX6 [2], so modify comments and model descriptions accordingly. Link https://dev.variscite.com/var-som-6ul [1] Link: https://dev.variscite.com/var-som-mx6 [2] Signed-off-by: Hugo Villeneuve Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts | 4 ++-- arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts index 085985356668..35ce647a6407 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-MX6UL + * Support for Variscite Concerto Carrier board with the VAR-SOM-6UL * Variscite SoM mounted on it * * Copyright 2019 Variscite Ltd. @@ -11,7 +11,7 @@ #include / { - model = "Variscite VAR-SOM-MX6UL Concerto Board"; + model = "Variscite VAR-SOM-6UL Concerto Board"; compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul"; chosen { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi index 30032be6fdd5..7259526e2b88 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Support for Variscite VAR-SOM-MX6UL Module + * Support for Variscite VAR-SOM-6UL Module * * Copyright 2019 Variscite Ltd. * Copyright 2025 Bootlin @@ -13,7 +13,7 @@ #include / { - model = "Variscite VAR-SOM-MX6UL module"; + model = "Variscite VAR-SOM-6UL module"; compatible = "variscite,var-som-imx6ul", "fsl,imx6ul"; memory@80000000 { From cc04ee842ce82b02485f6bd6f68b1749c2518358 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 5 Mar 2026 13:06:19 -0500 Subject: [PATCH 088/665] dt-bindings: arm: fsl: change incorrect VAR-SOM-MX6UL references There is no Variscite module named VAR-SOM-MX6UL, but there is VAR-SOM-MX6 and also VAR-SOM-6UL, so it is confusing at first to know to which one it refers to. The imx6ul-var-som* dts/dtsi supports only the VAR-SOM-6UL [1], not VAR-SOM-MX6 [2], so modify comments and model descriptions accordingly. Link https://dev.variscite.com/var-som-6ul [1] Link: https://dev.variscite.com/var-som-mx6 [2] Signed-off-by: Hugo Villeneuve Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/all/20260305180651.1827087-4-hugo@hugovil.com/ [1] Signed-off-by: Frank Li --- Documentation/devicetree/bindings/arm/fsl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 5716d701292c..99dc1b3f1ba9 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -688,7 +688,7 @@ properties: - const: phytec,imx6ul-pcl063 # PHYTEC phyCORE-i.MX 6UL - const: fsl,imx6ul - - description: i.MX6UL Variscite VAR-SOM-MX6 Boards + - description: i.MX6UL Variscite VAR-SOM-6UL Boards items: - const: variscite,mx6ulconcerto - const: variscite,var-som-imx6ul From 116f95fc84c85bc7f7c6e5665a53d825f2439710 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 5 Mar 2026 13:06:20 -0500 Subject: [PATCH 089/665] dt-bindings: arm: fsl: add variscite,var-som-imx6ull Add support for the imx6ull CPU variant of the Variscite concerto board evaluation kit with a VAR-SOM-6UL. Acked-by: Krzysztof Kozlowski Signed-off-by: Hugo Villeneuve Signed-off-by: Frank Li --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 99dc1b3f1ba9..61cda40d3187 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -797,6 +797,12 @@ properties: - const: phytec,imx6ull-pcl063 # PHYTEC phyCORE-i.MX 6ULL - const: fsl,imx6ull + - description: i.MX6ULL Variscite VAR-SOM-6UL Boards + items: + - const: variscite,mx6ullconcerto # Variscite VAR-SOM-6UL dev kit board + - const: variscite,var-som-imx6ull # Variscite VAR-SOM-6UL SoM (6ULL variant) + - const: fsl,imx6ull + - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Modules items: - enum: From e3b21b337513bab93bebea4cc6ad226281ef7ae5 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 5 Mar 2026 13:06:21 -0500 Subject: [PATCH 090/665] ARM: dts: imx6ul-var-som: Factor out common parts for all CPU variants Factor out the parts on the Variscite VAR-SOM-6UL [1] that are common to all CPU variants (6UL, 6ULL, etc). This will simplify adding future dedicated device tree files for each CPU variant. Link https://dev.variscite.com/var-som-6ul [1] Signed-off-by: Hugo Villeneuve Signed-off-by: Frank Li --- .../dts/nxp/imx/imx6ul-var-som-common.dtsi | 227 ++++++++++++++++++ arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi | 214 +---------------- .../arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi | 15 ++ 3 files changed, 243 insertions(+), 213 deletions(-) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi new file mode 100644 index 000000000000..2072e8ba4d46 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support for the common parts shared by all the different CPU options on + * Variscite VAR-SOM-6UL Module + * + * Copyright 2019 Variscite Ltd. + * Copyright 2025 Bootlin + */ + +#include +#include + +/ { + model = "Variscite VAR-SOM-6UL module"; + compatible = "variscite,var-som-imx6ul", "fsl,imx6ul"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + reg_gpio_dvfs: reg-gpio-dvfs { + compatible = "regulator-gpio"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + regulator-name = "gpio_dvfs"; + regulator-type = "voltage"; + gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + states = <1300000 0x1 + 1400000 0x0>; + }; + + rmii_ref_clk: rmii-ref-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "rmii-ref"; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>, <&pinctrl_enet1_mdio>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&rmii_ref_clk>; + clock-names = "rmii-ref"; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <100000>; + micrel,led-mode = <1>; + micrel,rmii-reference-clock-select-25-mhz; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet1_gpio: enet1-gpiogrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */ + >; + }; + + pinctrl_enet1_mdio: enet1-mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT Enable */ + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x03029 /* WLAN Enable */ + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; +}; + +&pxp { + status = "okay"; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + measure-delay-time = <0xffff>; + pre-charge-time = <0xfff>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <8>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi index 7259526e2b88..35a0c0b3603f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi @@ -9,221 +9,9 @@ /dts-v1/; #include "imx6ul.dtsi" -#include -#include +#include "imx6ul-var-som-common.dtsi" / { model = "Variscite VAR-SOM-6UL module"; compatible = "variscite,var-som-imx6ul", "fsl,imx6ul"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - reg_gpio_dvfs: reg-gpio-dvfs { - compatible = "regulator-gpio"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1400000>; - regulator-name = "gpio_dvfs"; - regulator-type = "voltage"; - gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; - states = <1300000 0x1 - 1400000 0x0>; - }; - - rmii_ref_clk: rmii-ref-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - clock-output-names = "rmii-ref"; - }; -}; - -&clks { - assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <786432000>; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>, <&pinctrl_enet1_mdio>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - clocks = <&rmii_ref_clk>; - clock-names = "rmii-ref"; - reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - reset-assert-us = <100000>; - micrel,led-mode = <1>; - micrel,rmii-reference-clock-select-25-mhz; - }; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 - >; - }; - - pinctrl_enet1_gpio: enet1-gpiogrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */ - >; - }; - - pinctrl_enet1_mdio: enet1-mdiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT Enable */ - MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x03029 /* WLAN Enable */ - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 - MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 - MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 - MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 - MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 - >; - }; - - pinctrl_tsc: tscgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 - MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 - MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 - MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 - MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 - >; - }; -}; - -&pxp { - status = "okay"; -}; - -&sai2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, - <&clks IMX6UL_CLK_SAI2>; - assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <0>, <12288000>; - fsl,sai-mclk-direction-output; - status = "okay"; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&tsc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tsc>; - xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - measure-delay-time = <0xffff>; - pre-charge-time = <0xfff>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - bus-width = <8>; - no-1-8-v; - non-removable; - keep-power-in-suspend; - wakeup-source; - status = "okay"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi new file mode 100644 index 000000000000..ba482a97623b --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support for Variscite VAR-SOM-6UL module with imx6ull CPU + * + * Copyright 2019-2024 Variscite Ltd. + * Copyright 2026 Dimonoff + */ + +#include "imx6ull.dtsi" +#include "imx6ul-var-som-common.dtsi" + +/ { + model = "Variscite VAR-SOM-6UL module"; + compatible = "variscite,var-som-imx6ull", "fsl,imx6ull"; +}; From 19435b532a13122a795454f36a6688380e1b522c Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 5 Mar 2026 13:06:22 -0500 Subject: [PATCH 091/665] ARM: dts: imx6ul-var-som-concerto: Factor out common parts for all CPU variants Export common parts to the Variscite VAR-SOM-6UL dtsi so that they can be reused on other boards and to simplify adding future dedicated device tree files for each CPU variant. Move i2c1 pinctrl to var-som dtsi pinmux, so that it can be reused by other boards. Signed-off-by: Hugo Villeneuve Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/Makefile | 1 + .../dts/nxp/imx/imx6ul-var-som-common.dtsi | 7 + .../imx/imx6ul-var-som-concerto-common.dtsi | 309 +++++++++++++++++ .../dts/nxp/imx/imx6ul-var-som-concerto.dts | 312 +----------------- .../dts/nxp/imx/imx6ull-var-som-concerto.dts | 17 + 5 files changed, 339 insertions(+), 307 deletions(-) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile index de4142e8f3ce..4f212569d2cd 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -377,6 +377,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-tqma6ull2-mba6ulx.dtb \ imx6ull-tqma6ull2l-mba6ulx.dtb \ imx6ull-uti260b.dtb \ + imx6ull-var-som-concerto.dtb \ imx6ulz-14x14-evk.dtb \ imx6ulz-bsh-smm-m2.dtb dtb-$(CONFIG_SOC_IMX7D) += \ diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi index 2072e8ba4d46..22b0c4e0725a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi @@ -104,6 +104,13 @@ MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x03029 /* WLAN Enable */ >; }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 + >; + }; + pinctrl_sai2: sai2grp { fsl,pins = < MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi new file mode 100644 index 000000000000..1cf4a4d6495f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi @@ -0,0 +1,309 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support for Variscite Concerto Carrier board with the VAR-SOM-6UL + * Variscite SoM mounted on it (all CPU variants) + * + * Copyright 2019 Variscite Ltd. + * Copyright 2025 Bootlin + */ + +#include + +/ { + chosen { + stdout-path = &uart1; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_key_back>, <&pinctrl_gpio_key_wakeup>; + + key-back { + gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-wakeup { + gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + function = LED_FUNCTION_STATUS; + color = ; + label = "gpled2"; + gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&fec1 { + status = "disabled"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_mdio>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + clocks = <&rmii_ref_clk>; + clock-names = "rmii-ref"; + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <100000>; + micrel,led-mode = <0>; + micrel,rmii-reference-clock-select-25-mhz; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + rtc@68 { + /* + * To actually use this interrupt + * connect pins J14.8 & J14.10 on the Concerto-Board. + */ + compatible = "dallas,ds1337"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&iomuxc { + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_enet2_gpio: enet2-gpiogrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* fec2 reset */ + >; + }; + + pinctrl_enet2_mdio: enet2-mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_gpio_key_back: gpio-key-backgrp { + fsl,pins = < + MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x17059 + >; + }; + + pinctrl_gpio_leds: gpio-ledsgrp { + fsl,pins = < + MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x1b0b0 /* GPLED2 */ + >; + }; + + pinctrl_gpio_key_wakeup: gpio-keys-wakeupgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x17059 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0 + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x1b0b0 /* RTC alarm IRQ */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x1b0b1 + MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x1b0b1 + MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 + MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1-gpiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x1b0b1 /* CD */ + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x78b0 + >; + }; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "disabled"; +}; + +&snvs_rtc { + status = "disabled"; +}; + +&tsc { + /* + * Conflics with wdog1 ext-reset-output & SD CD pins, + * so we keep it disabled by default. + */ + status = "disabled"; +}; + +/* Console UART */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* ttymxc4 UART */ +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; + cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + /* + * To actually use ext-reset-output + * connect pins J17.3 & J17.8 on the Concerto-Board + */ + fsl,ext-reset-output; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts index 35ce647a6407..8872bf55827e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts @@ -1,320 +1,18 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Support for Variscite Concerto Carrier board with the VAR-SOM-6UL - * Variscite SoM mounted on it + * Variscite SoM mounted on it (6UL CPU variant) * * Copyright 2019 Variscite Ltd. * Copyright 2025 Bootlin */ +/dts-v1/; + #include "imx6ul-var-som.dtsi" -#include +#include "imx6ul-var-som-concerto-common.dtsi" / { - model = "Variscite VAR-SOM-6UL Concerto Board"; + model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul"; - - chosen { - stdout-path = &uart1; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_key_back>, <&pinctrl_gpio_key_wakeup>; - - key-back { - gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - key-wakeup { - gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-0 { - function = LED_FUNCTION_STATUS; - color = ; - label = "gpled2"; - gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&fec1 { - status = "disabled"; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_mdio>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@3 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <3>; - clocks = <&rmii_ref_clk>; - clock-names = "rmii-ref"; - reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; - reset-assert-us = <100000>; - micrel,led-mode = <0>; - micrel,rmii-reference-clock-select-25-mhz; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - rtc@68 { - /* - * To actually use this interrupt - * connect pins J14.8 & J14.10 on the Concerto-Board. - */ - compatible = "dallas,ds1337"; - reg = <0x68>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc>; - interrupt-parent = <&gpio1>; - interrupts = <10 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&iomuxc { - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 - >; - }; - - pinctrl_enet2_gpio: enet2-gpiogrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* fec2 reset */ - >; - }; - - pinctrl_enet2_mdio: enet2-mdiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 - MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 - >; - }; - - pinctrl_gpio_key_back: gpio-key-backgrp { - fsl,pins = < - MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x17059 - >; - }; - - pinctrl_gpio_leds: gpio-ledsgrp { - fsl,pins = < - MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x1b0b0 /* GPLED2 */ - >; - }; - - pinctrl_gpio_key_wakeup: gpio-keys-wakeupgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x17059 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0 - >; - }; - - pinctrl_rtc: rtcgrp { - fsl,pins = < - MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x1b0b0 /* RTC alarm IRQ */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x1b0b1 - MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x1b0b1 - MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 - MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 - >; - }; - - pinctrl_usb_otg1_id: usbotg1idgrp { - fsl,pins = < - MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc1_gpio: usdhc1-gpiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x1b0b1 /* CD */ - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x78b0 - >; - }; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&snvs_pwrkey { - status = "disabled"; -}; - -&snvs_rtc { - status = "disabled"; -}; - -&tsc { - /* - * Conflics with wdog1 ext-reset-output & SD CD pins, - * so we keep it disabled by default. - */ - status = "disabled"; -}; - -/* Console UART */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* ttymxc4 UART */ -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1_id>; - dr_mode = "otg"; - disable-over-current; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; - cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - /* - * To actually use ext-reset-output - * connect pins J17.3 & J17.8 on the Concerto-Board - */ - fsl,ext-reset-output; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts new file mode 100644 index 000000000000..9413c946e2d9 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support for Variscite Concerto Carrier board with the VAR-SOM-6UL + * Variscite SoM mounted on it (6ULL CPU variant) + * + * Copyright 2026 Dimonoff + */ + +/dts-v1/; + +#include "imx6ull-var-som.dtsi" +#include "imx6ul-var-som-concerto-common.dtsi" + +/ { + model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; + compatible = "variscite,mx6ullconcerto", "variscite,var-som-imx6ull", "fsl,imx6ull"; +}; From 0d2f2cd6f4c2449d2338c8ce76a7ed73bbf0fde0 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 5 Mar 2026 13:06:23 -0500 Subject: [PATCH 092/665] ARM: dts: imx6ul-var-som-concerto: order DT properties reorder pinctrl_gpio_leds to respect alphabetical order. Signed-off-by: Hugo Villeneuve Signed-off-by: Frank Li --- .../dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi index 1cf4a4d6495f..d40264b55324 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi @@ -140,18 +140,18 @@ MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x17059 >; }; - pinctrl_gpio_leds: gpio-ledsgrp { - fsl,pins = < - MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x1b0b0 /* GPLED2 */ - >; - }; - pinctrl_gpio_key_wakeup: gpio-keys-wakeupgrp { fsl,pins = < MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x17059 >; }; + pinctrl_gpio_leds: gpio-ledsgrp { + fsl,pins = < + MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x1b0b0 /* GPLED2 */ + >; + }; + pinctrl_pwm4: pwm4grp { fsl,pins = < MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0 From f47685063daa995cbeeca871330c64e0b88442a4 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 5 Mar 2026 13:06:24 -0500 Subject: [PATCH 093/665] ARM: dts: imx6ul-var-som: factor out SD card support Move SD support to a separate dtsi, since it cannot be used at the same time as the Wifi/BT module. Also not all boards support the SD card. Move pinctrl_usdhc1* to the common imx6ul-var-som-common dtsi so that it can be used by the future Wifi/BT dtsi. Signed-off-by: Hugo Villeneuve Signed-off-by: Frank Li --- .../dts/nxp/imx/imx6ul-var-som-common.dtsi | 33 ++++++++++++ .../imx/imx6ul-var-som-concerto-common.dtsi | 51 ------------------- .../dts/nxp/imx/imx6ul-var-som-concerto.dts | 1 + .../boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi | 27 ++++++++++ .../dts/nxp/imx/imx6ull-var-som-concerto.dts | 1 + 5 files changed, 62 insertions(+), 51 deletions(-) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi index 22b0c4e0725a..dd4ecff1eb78 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi @@ -139,6 +139,39 @@ MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 >; }; + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi index d40264b55324..161b476474af 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi @@ -186,45 +186,6 @@ MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x17059 >; }; - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc1_gpio: usdhc1-gpiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x1b0b1 /* CD */ - >; - }; - pinctrl_wdog: wdoggrp { fsl,pins = < MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x78b0 @@ -286,18 +247,6 @@ &usbotg2 { status = "okay"; }; -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; - cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts index 8872bf55827e..92d98e4fc775 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts @@ -11,6 +11,7 @@ #include "imx6ul-var-som.dtsi" #include "imx6ul-var-som-concerto-common.dtsi" +#include "imx6ul-var-som-sd.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi new file mode 100644 index 000000000000..0e6d9b945eb4 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support optional SD card interface on Variscite VAR-SOM-6UL module. + * + * Copyright 2019-2024 Variscite Ltd. + * Copyright 2026 Dimonoff + */ + +&iomuxc { + pinctrl_usdhc1_gpio: usdhc1-gpiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x1b0b1 /* CD */ + >; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; + cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts index 9413c946e2d9..d33d5c5afcc2 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts @@ -10,6 +10,7 @@ #include "imx6ull-var-som.dtsi" #include "imx6ul-var-som-concerto-common.dtsi" +#include "imx6ul-var-som-sd.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; From 235c070343eb69c1a1d1b4aafb876578eb6d2c45 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 5 Mar 2026 13:06:25 -0500 Subject: [PATCH 094/665] ARM: dts: imx6ul-var-som: add proper Wifi and Bluetooth support Add proper support for the optional Wifi and Bluetooth configuration on VAR-SOM-6UL so that it works out of the box, without any custom scripts. The Wifi/BT module support is mutually exclusive with SD card interface. Signed-off-by: Hugo Villeneuve Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/Makefile | 2 + .../dts/nxp/imx/imx6ul-var-som-common.dtsi | 18 ++--- .../nxp/imx/imx6ul-var-som-concerto-full.dts | 18 +++++ .../boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi | 75 +++++++++++++++++++ arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi | 15 ++++ .../nxp/imx/imx6ull-var-som-concerto-full.dts | 18 +++++ .../arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi | 15 ++++ 7 files changed, 151 insertions(+), 10 deletions(-) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile index 4f212569d2cd..b81668dcaccf 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -339,6 +339,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-tx6ul-0011.dtb \ imx6ul-tx6ul-mainboard.dtb \ imx6ul-var-som-concerto.dtb \ + imx6ul-var-som-concerto-full.dtb \ imx6ull-14x14-evk.dtb \ imx6ull-colibri-aster.dtb \ imx6ull-colibri-emmc-aster.dtb \ @@ -378,6 +379,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-tqma6ull2l-mba6ulx.dtb \ imx6ull-uti260b.dtb \ imx6ull-var-som-concerto.dtb \ + imx6ull-var-som-concerto-full.dtb \ imx6ulz-14x14-evk.dtb \ imx6ulz-bsh-smm-m2.dtb dtb-$(CONFIG_SOC_IMX7D) += \ diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi index dd4ecff1eb78..af8c5d2db53d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi @@ -19,6 +19,14 @@ memory@80000000 { reg = <0x80000000 0x20000000>; }; + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + reg_gpio_dvfs: reg-gpio-dvfs { compatible = "regulator-gpio"; regulator-min-microvolt = <1300000>; @@ -68,9 +76,6 @@ ethphy0: ethernet-phy@1 { }; &iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - pinctrl_enet1: enet1grp { fsl,pins = < MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 @@ -97,13 +102,6 @@ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 >; }; - pinctrl_hog: hoggrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT Enable */ - MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x03029 /* WLAN Enable */ - >; - }; - pinctrl_i2c1: i2c1grp { fsl,pins = < MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts new file mode 100644 index 000000000000..519250b31db2 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL + * Variscite SoM mounted on it (6UL CPU variant). + * + * Copyright 2026 Dimonoff + */ + +/dts-v1/; + +#include "imx6ul-var-som.dtsi" +#include "imx6ul-var-som-concerto-common.dtsi" +#include "imx6ul-var-som-wifi.dtsi" + +/ { + model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; + compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi new file mode 100644 index 000000000000..6d16ff7909da --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support optional Wifi/Bluetooth on Variscite VAR-SOM-6UL module. + * + * Copyright 2019-2024 Variscite Ltd. + * Copyright 2026 Dimonoff + */ + +/ { + reg_sd1_vmmc: regulator_sd1_vmmc { + compatible = "regulator-fixed"; + regulator-name = "VMMC1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <10000>; + }; + + usdhc1_pwrseq: usdhc1-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_brcm_wifi>; + reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; + }; +}; + +&iomuxc { + pinctrl_32k_clk: 32kclkgrp { + /* + * For TP option, an additional oscillator is assembled on the + * SOM to provide 32 kHz to the WiFi module. Without TP option, + * this pin is configured to provide the 32 KHz clock to the + * WiFi module. + */ + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x03029 + >; + }; +}; + +&tsc { + status = "disabled"; +}; + +/* Bluetooth UART */ +&uart2 { + bluetooth { + compatible = "brcm,bcm43438-bt"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_brcm_bt>; + shutdown-gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; + vbat-supply = <®_3p3v>; + vddio-supply = <®_3p3v>; + }; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_32k_clk>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_32k_clk>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_32k_clk>; + no-1-8-v; + non-removable; + mmc-pwrseq = <&usdhc1_pwrseq>; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; /* LWB option: Sterling LWB5 */ + reg = <1>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi index 35a0c0b3603f..b4e6a9316dd8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi @@ -15,3 +15,18 @@ / { model = "Variscite VAR-SOM-6UL module"; compatible = "variscite,var-som-imx6ul", "fsl,imx6ul"; }; + +&iomuxc { + pinctrl_brcm_bt: brcm-bt-grp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT_REG_ON (BT_EN) */ + >; + }; + + pinctrl_brcm_wifi: brcm-wifi-grp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* WL_PWR (WIFI_PWR 5G) */ + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* WL_REG_ON (WIFI_EN) */ + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts new file mode 100644 index 000000000000..7c0e31360363 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL + * Variscite SoM mounted on it (6ULL CPU variant). + * + * Copyright 2026 Dimonoff + */ + +/dts-v1/; + +#include "imx6ull-var-som.dtsi" +#include "imx6ul-var-som-concerto-common.dtsi" +#include "imx6ul-var-som-wifi.dtsi" + +/ { + model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; + compatible = "variscite,mx6ullconcerto", "variscite,var-som-imx6ull", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi index ba482a97623b..3067ff6a1bc7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi @@ -13,3 +13,18 @@ / { model = "Variscite VAR-SOM-6UL module"; compatible = "variscite,var-som-imx6ull", "fsl,imx6ull"; }; + +&iomuxc { + pinctrl_brcm_bt: brcm-bt-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT_REG_ON (BT_EN) */ + >; + }; + + pinctrl_brcm_wifi: brcm-wifi-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* WL_PWR (WIFI_PWR 5G) */ + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* WL_REG_ON (WIFI_EN) */ + >; + }; +}; From 04b897252c5828e4cd31d92880229e26a630f2ff Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 5 Mar 2026 13:06:26 -0500 Subject: [PATCH 095/665] ARM: dts: imx6ul-var-som: factor out ENET2 ethernet support Not all boards use the ethernet ENET2 port, so factor out this functionality to a separate dtsi. On the concerto board, this uses the ethernet PHY assembled on it. Signed-off-by: Hugo Villeneuve Signed-off-by: Frank Li --- .../dts/nxp/imx/imx6ul-var-som-common.dtsi | 7 -- .../imx/imx6ul-var-som-concerto-common.dtsi | 50 -------------- .../nxp/imx/imx6ul-var-som-concerto-full.dts | 1 + .../dts/nxp/imx/imx6ul-var-som-concerto.dts | 1 + .../dts/nxp/imx/imx6ul-var-som-enet2.dtsi | 68 +++++++++++++++++++ .../nxp/imx/imx6ull-var-som-concerto-full.dts | 1 + .../dts/nxp/imx/imx6ull-var-som-concerto.dts | 1 + 7 files changed, 72 insertions(+), 57 deletions(-) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi index af8c5d2db53d..af9b92f7709b 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi @@ -37,13 +37,6 @@ reg_gpio_dvfs: reg-gpio-dvfs { states = <1300000 0x1 1400000 0x0>; }; - - rmii_ref_clk: rmii-ref-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - clock-output-names = "rmii-ref"; - }; }; &clks { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi index 161b476474af..fead54ac8c6b 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi @@ -56,30 +56,6 @@ &fec1 { status = "disabled"; }; -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_mdio>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@3 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <3>; - clocks = <&rmii_ref_clk>; - clock-names = "rmii-ref"; - reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; - reset-assert-us = <100000>; - micrel,led-mode = <0>; - micrel,rmii-reference-clock-select-25-mhz; - }; - }; -}; - &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -101,32 +77,6 @@ rtc@68 { }; &iomuxc { - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 - >; - }; - - pinctrl_enet2_gpio: enet2-gpiogrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* fec2 reset */ - >; - }; - - pinctrl_enet2_mdio: enet2-mdiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - >; - }; - pinctrl_flexcan1: flexcan1grp { fsl,pins = < MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts index 519250b31db2..3905171b47b3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts @@ -11,6 +11,7 @@ #include "imx6ul-var-som.dtsi" #include "imx6ul-var-som-concerto-common.dtsi" #include "imx6ul-var-som-wifi.dtsi" +#include "imx6ul-var-som-enet2.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts index 92d98e4fc775..7eebb5b4f5e4 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts @@ -12,6 +12,7 @@ #include "imx6ul-var-som.dtsi" #include "imx6ul-var-som-concerto-common.dtsi" #include "imx6ul-var-som-sd.dtsi" +#include "imx6ul-var-som-enet2.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi new file mode 100644 index 000000000000..334ed3bbe02c --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Ethernet ENET2 support for Variscite VAR-SOM-6UL module. + * + * Copyright 2019-2024 Variscite Ltd. + * Copyright 2026 Dimonoff + */ + +/ { + rmii_ref_clk: rmii-ref-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "rmii-ref"; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_mdio>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio_enet2: mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + clocks = <&rmii_ref_clk>; + clock-names = "rmii-ref"; + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <100000>; + micrel,led-mode = <0>; + micrel,rmii-reference-clock-select-25-mhz; + }; + }; +}; + +&iomuxc { + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_enet2_gpio: enet2-gpiogrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* fec2 reset */ + >; + }; + + pinctrl_enet2_mdio: enet2-mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts index 7c0e31360363..89b6032203a2 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts @@ -11,6 +11,7 @@ #include "imx6ull-var-som.dtsi" #include "imx6ul-var-som-concerto-common.dtsi" #include "imx6ul-var-som-wifi.dtsi" +#include "imx6ul-var-som-enet2.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts index d33d5c5afcc2..0d3e0d9b0f11 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts @@ -11,6 +11,7 @@ #include "imx6ull-var-som.dtsi" #include "imx6ul-var-som-concerto-common.dtsi" #include "imx6ul-var-som-sd.dtsi" +#include "imx6ul-var-som-enet2.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; From 38296261b071447a02eb3eb40efdb5da0a38876c Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 5 Mar 2026 13:06:27 -0500 Subject: [PATCH 096/665] ARM: dts: imx6ul-var-som: add support for EC configuration option (ENET1) ENET1 is currently disabled and not supported/working on the concerto EVK. Add support for this optional configuration in a separate dtsi, so that it can be selectively enabled/disabled. Signed-off-by: Hugo Villeneuve Signed-off-by: Frank Li --- .../dts/nxp/imx/imx6ul-var-som-common.dtsi | 50 ------------------- .../imx/imx6ul-var-som-concerto-common.dtsi | 4 -- .../nxp/imx/imx6ul-var-som-concerto-full.dts | 1 + .../dts/nxp/imx/imx6ul-var-som-enet1.dtsi | 44 ++++++++++++++++ .../dts/nxp/imx/imx6ul-var-som-enet2.dtsi | 11 ++++ arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi | 6 +++ .../nxp/imx/imx6ull-var-som-concerto-full.dts | 1 + .../arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi | 6 +++ 8 files changed, 69 insertions(+), 54 deletions(-) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi index af9b92f7709b..70d19eccddb4 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi @@ -44,57 +44,7 @@ &clks { assigned-clock-rates = <786432000>; }; -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>, <&pinctrl_enet1_mdio>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - clocks = <&rmii_ref_clk>; - clock-names = "rmii-ref"; - reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - reset-assert-us = <100000>; - micrel,led-mode = <1>; - micrel,rmii-reference-clock-select-25-mhz; - }; - }; -}; - &iomuxc { - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 - >; - }; - - pinctrl_enet1_gpio: enet1-gpiogrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */ - >; - }; - - pinctrl_enet1_mdio: enet1-mdiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 - >; - }; - pinctrl_i2c1: i2c1grp { fsl,pins = < MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi index fead54ac8c6b..f099ca5d0e8f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi @@ -52,10 +52,6 @@ &can1 { status = "okay"; }; -&fec1 { - status = "disabled"; -}; - &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts index 3905171b47b3..b5e6a3306e1c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts @@ -12,6 +12,7 @@ #include "imx6ul-var-som-concerto-common.dtsi" #include "imx6ul-var-som-wifi.dtsi" #include "imx6ul-var-som-enet2.dtsi" +#include "imx6ul-var-som-enet1.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi new file mode 100644 index 000000000000..6b1e34347bec --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Ethernet ENET1 support for Variscite VAR-SOM-6UL module with + * the EC configuration option ((ethernet PHY assembled on SOM). + * + * Copyright 2019-2024 Variscite Ltd. + * Copyright 2026 Dimonoff + */ + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; +}; + +&mdio_enet2 { + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&rmii_ref_clk>; + clock-names = "rmii-ref"; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <100000>; + micrel,led-mode = <1>; + micrel,rmii-reference-clock-select-25-mhz; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi index 334ed3bbe02c..b29fcdc079e3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi @@ -26,6 +26,17 @@ mdio_enet2: mdio { #address-cells = <1>; #size-cells = <0>; + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&rmii_ref_clk>; + clock-names = "rmii-ref"; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <100000>; + micrel,led-mode = <1>; + micrel,rmii-reference-clock-select-25-mhz; + }; + ethphy1: ethernet-phy@3 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <3>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi index b4e6a9316dd8..feea24c0e068 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi @@ -29,4 +29,10 @@ MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* WL_PWR (WIFI_PWR 5G) */ MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* WL_REG_ON (WIFI_EN) */ >; }; + + pinctrl_enet1_gpio: enet1-gpiogrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */ + >; + }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts index 89b6032203a2..86f558c76fb3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts @@ -12,6 +12,7 @@ #include "imx6ul-var-som-concerto-common.dtsi" #include "imx6ul-var-som-wifi.dtsi" #include "imx6ul-var-som-enet2.dtsi" +#include "imx6ul-var-som-enet1.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi index 3067ff6a1bc7..f120b1dca75c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi @@ -27,4 +27,10 @@ MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* WL_PWR (WIFI_PWR 5G) */ MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* WL_REG_ON (WIFI_EN) */ >; }; + + pinctrl_enet1_gpio: enet1-gpiogrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */ + >; + }; }; From 5f1733077a1a382a22260379b9ca333860bd00a1 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 5 Mar 2026 13:06:28 -0500 Subject: [PATCH 097/665] ARM: dts: imx6ul-var-som: factor out audio support Not all boards use the audio codec, so factor out this functionality to a separate dtsi. Signed-off-by: Hugo Villeneuve Signed-off-by: Frank Li --- .../dts/nxp/imx/imx6ul-var-som-audio.dtsi | 30 +++++++++++++++++++ .../dts/nxp/imx/imx6ul-var-som-common.dtsi | 21 ------------- .../nxp/imx/imx6ul-var-som-concerto-full.dts | 1 + .../dts/nxp/imx/imx6ul-var-som-concerto.dts | 1 + .../nxp/imx/imx6ull-var-som-concerto-full.dts | 1 + .../dts/nxp/imx/imx6ull-var-som-concerto.dts | 1 + 6 files changed, 34 insertions(+), 21 deletions(-) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-audio.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-audio.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-audio.dtsi new file mode 100644 index 000000000000..3c480bc7a6ad --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-audio.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Audio support for Variscite VAR-SOM-6UL module. + * + * Copyright 2019-2024 Variscite Ltd. + * Copyright 2026 Dimonoff + */ + +&iomuxc { + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + >; + }; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi index 70d19eccddb4..5600eeaa5854 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi @@ -52,16 +52,6 @@ MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 >; }; - pinctrl_sai2: sai2grp { - fsl,pins = < - MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 - MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 - MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 - MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 - MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 - >; - }; - pinctrl_tsc: tscgrp { fsl,pins = < MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 @@ -163,17 +153,6 @@ &pxp { status = "okay"; }; -&sai2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, - <&clks IMX6UL_CLK_SAI2>; - assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <0>, <12288000>; - fsl,sai-mclk-direction-output; - status = "okay"; -}; - &snvs_poweroff { status = "okay"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts index b5e6a3306e1c..64a3cbd8b7c3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts @@ -13,6 +13,7 @@ #include "imx6ul-var-som-wifi.dtsi" #include "imx6ul-var-som-enet2.dtsi" #include "imx6ul-var-som-enet1.dtsi" +#include "imx6ul-var-som-audio.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts index 7eebb5b4f5e4..9c5cb96beeb1 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts @@ -13,6 +13,7 @@ #include "imx6ul-var-som-concerto-common.dtsi" #include "imx6ul-var-som-sd.dtsi" #include "imx6ul-var-som-enet2.dtsi" +#include "imx6ul-var-som-audio.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts index 86f558c76fb3..2e1f75d5f25a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts @@ -13,6 +13,7 @@ #include "imx6ul-var-som-wifi.dtsi" #include "imx6ul-var-som-enet2.dtsi" #include "imx6ul-var-som-enet1.dtsi" +#include "imx6ul-var-som-audio.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts index 0d3e0d9b0f11..43a477db652f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts @@ -12,6 +12,7 @@ #include "imx6ul-var-som-concerto-common.dtsi" #include "imx6ul-var-som-sd.dtsi" #include "imx6ul-var-som-enet2.dtsi" +#include "imx6ul-var-som-audio.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; From fe886aec2ef0b05a2e31b3f184fbe85b6aa9743c Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 5 Mar 2026 13:06:30 -0500 Subject: [PATCH 098/665] ARM: dts: imx6ul-var-som: add support for LVDS display panel Add support for the LD configuration option (LVDS encoder assembled on SOM) so that the LVDS display panel on the concerto EVK board works properly. Not all VAR-SOM-6UL SOMs have the LD configuration option so factor out this functionality to a separate dtsi. Signed-off-by: Hugo Villeneuve Signed-off-by: Frank Li --- .../imx/imx6ul-var-som-concerto-common.dtsi | 35 ++++-- .../nxp/imx/imx6ul-var-som-concerto-full.dts | 1 + .../dts/nxp/imx/imx6ul-var-som-concerto.dts | 1 + .../nxp/imx/imx6ul-var-som-lvds-panel.dtsi | 112 ++++++++++++++++++ .../nxp/imx/imx6ull-var-som-concerto-full.dts | 1 + .../dts/nxp/imx/imx6ull-var-som-concerto.dts | 1 + 6 files changed, 139 insertions(+), 12 deletions(-) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-lvds-panel.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi index f099ca5d0e8f..e5637310ba63 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi @@ -44,6 +44,29 @@ led-0 { linux,default-trigger = "heartbeat"; }; }; + + lvds_panel: lvds-panel { + compatible = "sgd,gktw70sdae4se", "panel-lvds"; + data-mapping = "jeida-18"; + width-mm = <153>; + height-mm = <86>; + + panel-timing { + clock-frequency = <35000000>; + hactive = <800>; + vactive = <480>; + hback-porch = <40>; + hfront-porch = <40>; + vback-porch = <29>; + vfront-porch = <13>; + hsync-len = <48>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; }; &can1 { @@ -98,12 +121,6 @@ MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x1b0b0 /* GPLED2 */ >; }; - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0 - >; - }; - pinctrl_rtc: rtcgrp { fsl,pins = < MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x1b0b0 /* RTC alarm IRQ */ @@ -139,12 +156,6 @@ MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x78b0 }; }; -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - &snvs_pwrkey { status = "disabled"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts index 64a3cbd8b7c3..725f34d6b7ee 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts @@ -14,6 +14,7 @@ #include "imx6ul-var-som-enet2.dtsi" #include "imx6ul-var-som-enet1.dtsi" #include "imx6ul-var-som-audio.dtsi" +#include "imx6ul-var-som-lvds-panel.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts index 9c5cb96beeb1..c249e15772b8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts @@ -14,6 +14,7 @@ #include "imx6ul-var-som-sd.dtsi" #include "imx6ul-var-som-enet2.dtsi" #include "imx6ul-var-som-audio.dtsi" +#include "imx6ul-var-som-lvds-panel.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-lvds-panel.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-lvds-panel.dtsi new file mode 100644 index 000000000000..996b37d35d6e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-lvds-panel.dtsi @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * LVDS panel support for Variscite VAR-SOM-6UL module. + * + * Copyright 2019-2024 Variscite Ltd. + * Copyright 2026 Dimonoff + */ + +/ { + lcd_backlight: lcd-backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 2000000 0>; + pwm-names = "LCD_BKLT_PWM"; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + lvds_encoder: lvds-encoder { + compatible = "ti,sn75lvds93", "lvds-encoder"; + power-supply = <®_3p3v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_enc_in: endpoint { + remote-endpoint = <&lcdif_out>; + }; + }; + + port@1 { + reg = <1>; + + lvds_enc_out: endpoint { + remote-endpoint = <&lvds_panel_in>; + }; + }; + }; + }; +}; + +&iomuxc { + pinctrl_lcdif_ctrl: lcdif-ctrl-grp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + >; + }; + + pinctrl_lcdif_dat: lcdif-dat-grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_pwm4: pwm4-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0 /* LCD BACKLIGHT */ + >; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + status = "okay"; + + port { + lcdif_out: endpoint { + remote-endpoint = <&lvds_enc_in>; + }; + }; +}; + +&lvds_panel { + status = "okay"; + + port { + lvds_panel_in: endpoint { + remote-endpoint = <&lvds_enc_out>; + }; + }; +}; + +/* PWM LCD */ +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts index 2e1f75d5f25a..1b7c1a3383ee 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts @@ -14,6 +14,7 @@ #include "imx6ul-var-som-enet2.dtsi" #include "imx6ul-var-som-enet1.dtsi" #include "imx6ul-var-som-audio.dtsi" +#include "imx6ul-var-som-lvds-panel.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts index 43a477db652f..9c9d16eb1a11 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts @@ -13,6 +13,7 @@ #include "imx6ul-var-som-sd.dtsi" #include "imx6ul-var-som-enet2.dtsi" #include "imx6ul-var-som-audio.dtsi" +#include "imx6ul-var-som-lvds-panel.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; From 24c12ca43b12c104389d9a159207d0b25779d0af Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Thu, 30 Apr 2026 19:52:12 +0100 Subject: [PATCH 099/665] dts: spacemit: set console baud rate on bpif3 Because the default console's baud rate is not set, defconfig kernels do not have any serial output on this platform. Set the baud rate to 115200, matching what is used by U-Boot etc on this platform. Suggested-by: Vivian Wang Fixes: d60d57ab6b2a8 ("riscv: dts: spacemit: add Banana Pi BPI-F3 board device tree") Signed-off-by: Conor Dooley Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/20260430-reword-overstep-3be08b7eab25@spud Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts index 5790d927b93d..333ac8ebf3f5 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -19,7 +19,7 @@ aliases { }; chosen { - stdout-path = "serial0"; + stdout-path = "serial0:115200n8"; }; leds { From 725351152a7d0c9cdd7072724d1e4d3e7c452f9a Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 7 Apr 2026 16:36:23 +0100 Subject: [PATCH 100/665] riscv: dts: microchip: add tsu clock to macb on pic64gx In increment mode, the tsu clock for the macb is provided separately to the pck, usually the same clock as the reference to the rtc provided by an off-chip oscillator. pclk is 150 MHz typically, and the reference is either 100 MHz or 125 MHz, so having the tsu clock is required for correct rate selection. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/pic64gx.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/pic64gx.dtsi b/arch/riscv/boot/dts/microchip/pic64gx.dtsi index c164d7bc270a..e9ec376b1776 100644 --- a/arch/riscv/boot/dts/microchip/pic64gx.dtsi +++ b/arch/riscv/boot/dts/microchip/pic64gx.dtsi @@ -459,8 +459,8 @@ mac0: ethernet@20110000 { interrupts = <64>, <65>, <66>, <67>, <68>, <69>; /* Filled in by a bootloader */ local-mac-address = [00 00 00 00 00 00]; - clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; - clock-names = "pclk", "hclk"; + clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>, <&refclk>; + clock-names = "pclk", "hclk", "tsu_clk"; resets = <&mss_top_sysreg CLK_MAC0>; status = "disabled"; }; @@ -475,8 +475,8 @@ mac1: ethernet@20112000 { interrupts = <70>, <71>, <72>, <73>, <74>, <75>; /* Filled in by a bootloader */ local-mac-address = [00 00 00 00 00 00]; - clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; - clock-names = "pclk", "hclk"; + clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>, <&refclk>; + clock-names = "pclk", "hclk", "tsu_clk"; resets = <&mss_top_sysreg CLK_MAC1>; status = "disabled"; }; From 4ce4a46cdb2404bcd53ca58a18aeda673f37fbe9 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 7 Apr 2026 16:36:24 +0100 Subject: [PATCH 101/665] riscv: dts: microchip: update pic64gx gpio interrupts to better match the SoC Just like PolarFire SoC, the same issues with GPIO interrupts exist in the pic64gx, due to their similarity. Yoinking from the commit message for the same change for PolarFire SoC: There are 3 GPIO controllers on this SoC, of which: - GPIO controller 0 has 14 GPIOs - GPIO controller 1 has 24 GPIOs - GPIO controller 2 has 32 GPIOs All GPIOs are capable of generating interrupts, for a total of 70. There are only 41 IRQs available however, so a configurable mux is used to ensure all GPIOs can be used for interrupt generation. 38 of the 41 interrupts are in what the documentation calls "direct mode", as they provide an exclusive connection from a GPIO to the PLIC. The 3 remaining interrupts are used to mux the interrupts which do not have a exclusive connection, one for each GPIO controller. The mux was overlooked when the bindings and driver were originally written for the GPIO controllers on Polarfire SoC, and the interrupts property in the GPIO nodes used to try and convey what the mapping was. Instead, the mux should be a device in its own right, and the GPIO controllers should be connected to it, rather than to the PLIC. Now that a binding exists for that mux, fix the inaccurate description of the interrupt controller hierarchy. Signed-off-by: Conor Dooley --- .../dts/microchip/pic64gx-curiosity-kit.dts | 47 ++++++++++++------- arch/riscv/boot/dts/microchip/pic64gx.dtsi | 32 +++++++++++-- 2 files changed, 58 insertions(+), 21 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts b/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts index 2f2ccd77af30..ed3ff03f3b11 100644 --- a/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts +++ b/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts @@ -63,10 +63,6 @@ hss: hss-buffer@bfc00000 { }; &gpio0 { - interrupts = <13>, <14>, <15>, <16>, - <17>, <18>, <19>, <20>, - <21>, <22>, <23>, <24>, - <25>, <26>; status ="okay"; gpio-line-names = "", "", "", "", "", "", "", "", @@ -74,12 +70,6 @@ &gpio0 { }; &gpio1 { - interrupts = <27>, <28>, <29>, <30>, - <31>, <32>, <33>, <34>, - <35>, <36>, <37>, <38>, - <39>, <40>, <41>, <42>, - <43>, <44>, <45>, <46>, - <47>, <48>, <49>, <50>; status ="okay"; gpio-line-names = "", "", "LED1", "LED2", "LED3", "LED4", "LED5", "LED6", @@ -88,14 +78,6 @@ &gpio1 { }; &gpio2 { - interrupts = <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>; pinctrl-names = "default"; pinctrl-0 = <&mdio1_gpio>, <&spi0_gpio>, <&can0_gpio>, <&pcie_gpio>, <&qspi_gpio>, <&uart3_gpio>, <&uart4_gpio>, <&can1_gpio>; @@ -107,6 +89,35 @@ &gpio2 { "DIP4", "USR_IO11", "", "", "SWITCH1", "", "", ""; }; +&irqmux { + interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>, + <3 &plic 16>, <4 &plic 17>, <5 &plic 18>, + <6 &plic 19>, <7 &plic 20>, <8 &plic 21>, + <9 &plic 22>, <10 &plic 23>, <11 &plic 24>, + <12 &plic 25>, <13 &plic 26>, + + <32 &plic 27>, <33 &plic 28>, <34 &plic 29>, + <35 &plic 30>, <36 &plic 31>, <37 &plic 32>, + <38 &plic 33>, <39 &plic 34>, <40 &plic 35>, + <41 &plic 36>, <42 &plic 37>, <43 &plic 38>, + <44 &plic 39>, <45 &plic 40>, <46 &plic 41>, + <47 &plic 42>, <48 &plic 43>, <49 &plic 44>, + <50 &plic 45>, <51 &plic 46>, <52 &plic 47>, + <53 &plic 48>, <54 &plic 49>, <55 &plic 50>, + + <64 &plic 53>, <65 &plic 53>, <66 &plic 53>, + <67 &plic 53>, <68 &plic 53>, <69 &plic 53>, + <70 &plic 53>, <71 &plic 53>, <72 &plic 53>, + <73 &plic 53>, <74 &plic 53>, <75 &plic 53>, + <76 &plic 53>, <77 &plic 53>, <78 &plic 53>, + <79 &plic 53>, <80 &plic 53>, <81 &plic 53>, + <82 &plic 53>, <83 &plic 53>, <84 &plic 53>, + <85 &plic 53>, <86 &plic 53>, <87 &plic 53>, + <88 &plic 53>, <89 &plic 53>, <90 &plic 53>, + <91 &plic 53>, <92 &plic 53>, <93 &plic 53>, + <94 &plic 53>, <95 &plic 53>; +}; + &mac0 { status = "okay"; phy-mode = "sgmii"; diff --git a/arch/riscv/boot/dts/microchip/pic64gx.dtsi b/arch/riscv/boot/dts/microchip/pic64gx.dtsi index e9ec376b1776..5cf3e3de0e06 100644 --- a/arch/riscv/boot/dts/microchip/pic64gx.dtsi +++ b/arch/riscv/boot/dts/microchip/pic64gx.dtsi @@ -295,6 +295,14 @@ mss_top_sysreg: syscon@20002000 { #size-cells = <1>; #reset-cells = <1>; + irqmux: interrupt-controller@54 { + compatible = "microchip,pic64gx-irqmux", "microchip,mpfs-irqmux"; + reg = <0x54 0x4>; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0x7f>; + }; + iomux0: pinctrl@200 { compatible = "microchip,pic64gx-pinctrl-iomux0", "microchip,mpfs-pinctrl-iomux0"; @@ -484,9 +492,13 @@ mac1: ethernet@20112000 { gpio0: gpio@20120000 { compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio"; reg = <0x0 0x20120000 0x0 0x1000>; - interrupt-parent = <&plic>; + interrupt-parent = <&irqmux>; interrupt-controller; #interrupt-cells = <1>; + interrupts = <0>, <1>, <2>, <3>, + <4>, <5>, <6>, <7>, + <8>, <9>, <10>, <11>, + <12>, <13>; clocks = <&clkcfg CLK_GPIO0>; gpio-controller; #gpio-cells = <2>; @@ -497,9 +509,15 @@ gpio0: gpio@20120000 { gpio1: gpio@20121000 { compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio"; reg = <0x0 0x20121000 0x0 0x1000>; - interrupt-parent = <&plic>; + interrupt-parent = <&irqmux>; interrupt-controller; #interrupt-cells = <1>; + interrupts = <32>, <33>, <34>, <35>, + <36>, <37>, <38>, <39>, + <40>, <41>, <42>, <43>, + <44>, <45>, <46>, <47>, + <48>, <49>, <50>, <51>, + <52>, <53>, <54>, <55>; clocks = <&clkcfg CLK_GPIO1>; gpio-controller; #gpio-cells = <2>; @@ -510,9 +528,17 @@ gpio1: gpio@20121000 { gpio2: gpio@20122000 { compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio"; reg = <0x0 0x20122000 0x0 0x1000>; - interrupt-parent = <&plic>; + interrupt-parent = <&irqmux>; interrupt-controller; #interrupt-cells = <1>; + interrupts = <64>, <65>, <66>, <67>, + <68>, <69>, <70>, <71>, + <72>, <73>, <74>, <75>, + <76>, <77>, <78>, <79>, + <80>, <81>, <82>, <83>, + <84>, <85>, <86>, <87>, + <88>, <89>, <90>, <91>, + <92>, <93>, <94>, <95>; clocks = <&clkcfg CLK_GPIO2>; gpio-controller; #gpio-cells = <2>; From 58bd7ff1a1bd9f2847aa23ff94b6ab3a39717136 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 7 Apr 2026 16:36:25 +0100 Subject: [PATCH 102/665] riscv: dts: microchip: sort pic64gx i2c nodes alphanumerically The i2c nodes are out of place, sort them where they should be. Signed-off-by: Conor Dooley --- .../boot/dts/microchip/pic64gx-curiosity-kit.dts | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts b/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts index ed3ff03f3b11..ef5bff3093fc 100644 --- a/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts +++ b/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts @@ -89,6 +89,14 @@ &gpio2 { "DIP4", "USR_IO11", "", "", "SWITCH1", "", "", ""; }; +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + &irqmux { interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>, <3 &plic 16>, <4 &plic 17>, <5 &plic 18>, @@ -134,14 +142,6 @@ &mbox { status = "okay"; }; -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - &mmc { bus-width = <4>; disable-wp; From 79b731da340f1c9703e28665d49a865aa6956278 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Thu, 19 Mar 2026 16:26:35 +0000 Subject: [PATCH 103/665] riscv: dts: microchip: gpio controllers on mpfs need 2 interrupt cells The platform has variable interrupt types for GPIO interrupts, in addition to having multiple lines per GPIO controller. Two interrupt cells are required. Fixes: 528a5b1f2556d ("riscv: dts: microchip: add new peripherals to icicle kit device tree") Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index d535d4c72763..85d8df6437f2 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -499,7 +499,7 @@ gpio0: gpio@20120000 { reg = <0x0 0x20120000 0x0 0x1000>; interrupt-parent = <&irqmux>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>, <10>, <11>, @@ -516,7 +516,7 @@ gpio1: gpio@20121000 { reg = <0x0 0x20121000 0x0 0x1000>; interrupt-parent = <&irqmux>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; interrupts = <32>, <33>, <34>, <35>, <36>, <37>, <38>, <39>, <40>, <41>, <42>, <43>, @@ -535,7 +535,7 @@ gpio2: gpio@20122000 { reg = <0x0 0x20122000 0x0 0x1000>; interrupt-parent = <&irqmux>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; interrupts = <64>, <65>, <66>, <67>, <68>, <69>, <70>, <71>, <72>, <73>, <74>, <75>, From 7ab032833b2f0dd3b51d71e6756ebe7efc61eed4 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Thu, 5 Mar 2026 10:30:03 +0000 Subject: [PATCH 104/665] riscv: dts: microchip: remove gpio hogs from beaglev-fire sd-det-hog should be cd-gpios, but when the mmc-spi-slot was added, the "cd-" prefix was omitted and the collision with the hog was not noticed. vio-enable-hog is just a regulator that can be modelled as such. Fixes: 1088d49b62648 ("riscv: dts: microchip: enable qspi adc/mmc-spi-slot on BeagleV Fire") Signed-off-by: Conor Dooley --- .../boot/dts/microchip/mpfs-beaglev-fire.dts | 25 ++++++++----------- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts index 0e1b0b8d394b..6e9653827cfe 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts @@ -77,6 +77,15 @@ imx219_vddl: fixedregulator-2 { regulator-max-microvolt = <1200000>; }; + regulator-1v8-syzygy { + compatible = "regulator-fixed"; + gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + regulator-name = "syzygy_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + enable-active-high; + }; }; &gpio0 { @@ -118,20 +127,6 @@ &gpio2 { "P8_PIN27", "P8_PIN28", "P8_PIN29", "P8_PIN30", "M2_W_DISABLE1", "M2_W_DISABLE2", "VIO_ENABLE", "SD_DET"; status = "okay"; - - vio-enable-hog { - gpio-hog; - gpios = <30 30>; - output-high; - line-name = "VIO_ENABLE"; - }; - - sd-det-hog { - gpio-hog; - gpios = <31 31>; - input; - line-name = "SD_DET"; - }; }; &i2c0 { @@ -316,7 +311,7 @@ channel@7 { mmc@1 { compatible = "mmc-spi-slot"; reg = <1>; - gpios = <&gpio2 31 1>; + cd-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>; voltage-ranges = <3300 3300>; spi-max-frequency = <5000000>; disable-wp; From 044427ff277021b9f750a9addf60d13db98a2f24 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Thu, 5 Mar 2026 10:12:12 +0000 Subject: [PATCH 105/665] riscv: dts: microchip: clean up beaglev-fire regulator node names Recently the binding for regulator-fixed introduced preferred naming, in the regulator-XvY format. Change the existing regulators to match this pattern. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts index 6e9653827cfe..3adcd4b193c2 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts @@ -63,14 +63,14 @@ imx219_vana: fixedregulator-0 { regulator-max-microvolt = <2800000>; }; - imx219_vdig: fixedregulator-1 { + imx219_vdig: regulator-1v8 { compatible = "regulator-fixed"; regulator-name = "imx219_vdig"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - imx219_vddl: fixedregulator-2 { + imx219_vddl: regulator-1v2 { compatible = "regulator-fixed"; regulator-name = "imx219_vddl"; regulator-min-microvolt = <1200000>; From 11cec5d0f596d52f0d3d81851649281318f4b52a Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Thu, 5 Mar 2026 10:27:14 +0000 Subject: [PATCH 106/665] riscv: dts: microchip: add adc interrupt on beaglev-fire The mcp3464r on the beaglev-fire has its interrupt wired up, but not present in the devicetree. Add it. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts index 3adcd4b193c2..c79dc49c1ce0 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts @@ -4,6 +4,7 @@ /dts-v1/; #include +#include #include "mpfs.dtsi" #include "mpfs-beaglev-fire-fabric.dtsi" @@ -255,6 +256,7 @@ adc@0 { spi-cpha; spi-max-frequency = <5000000>; microchip,hw-device-address = <1>; + interrupts-extended = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>; #address-cells = <1>; #size-cells = <0>; status = "okay"; From bba7498491dfab3ee68ab4ce6c615e5d70cfccba Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Thu, 5 Mar 2026 10:31:05 +0000 Subject: [PATCH 107/665] riscv: dts: microchip: add gpio line names on beaglev-fire GPIO controller 2 has the gpio-line-names property, but the two other controllers do not. Add the property for these controllers too. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts index c79dc49c1ce0..7bbd400b7103 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts @@ -95,6 +95,8 @@ &gpio0 { <21>, <22>, <23>, <24>, <25>, <26>; ngpios = <14>; + gpio-line-names = "", "", "", "", "", "", "", + "", "", "", "", "", "SD_CARD_CS", "USER_BUTTON"; status = "okay"; }; @@ -106,6 +108,9 @@ &gpio1 { <43>, <44>, <45>, <46>, <47>, <48>, <49>, <50>; ngpios = <24>; + gpio-line-names = "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "ADC_IRQn", "", "", "USB_OCn"; status = "okay"; }; From c580774185426ea316396b1dc3f1737a3ad3800a Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Sat, 2 May 2026 21:30:53 -0400 Subject: [PATCH 108/665] riscv: dts: spacemit: define a SPI controller node Define a node for the fourth SoC SPI controller (number 3) on the SpacemiT K1 SoC. Enable it on the Banana Pi BPI-F3 board, which exposes this feature via its GPIO block: GPIO PIN 19: MOSI GPIO PIN 21: MISO GPIO PIN 23: SCLK GPIO PIN 24: SS (inverted) Define pincontrol configurations for the pins as used on that board. (This was tested using a GigaDevice GD25Q64E SPI NOR chip.) Reviewed-by: Yixun Lan Signed-off-by: Alex Elder Signed-off-by: Guodong Xu Link: https://lore.kernel.org/r/20260502-spi-spacemit-k1-v10-3-f412e1ae8a34@riscstar.com Signed-off-by: Yixun Lan --- .../boot/dts/spacemit/k1-bananapi-f3.dts | 7 +++++++ arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 20 +++++++++++++++++++ arch/riscv/boot/dts/spacemit/k1.dtsi | 15 ++++++++++++++ 3 files changed, 42 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts index 333ac8ebf3f5..e20daa50a152 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -14,6 +14,7 @@ aliases { ethernet0 = ð0; ethernet1 = ð1; serial0 = &uart0; + spi3 = &spi3; i2c2 = &i2c2; i2c8 = &i2c8; }; @@ -335,6 +336,12 @@ &pcie2 { status = "okay"; }; +&spi3 { + pinctrl-0 = <&ssp3_0_cfg>; + pinctrl-names = "default"; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_2_cfg>; diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi index b13dcb10f4d6..34d88334e95e 100644 --- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi @@ -570,4 +570,24 @@ pwm14-1-pins { drive-strength = <32>; }; }; + + ssp3_0_cfg: ssp3-0-cfg { + ssp3-0-pins { + pinmux = , /* SCLK */ + , /* MOSI */ + ; /* MISO */ + + bias-disable; + drive-strength = <19>; + power-source = <3300>; + }; + + ssp3-0-frm-pins { + pinmux = ; /* FRM (frame) */ + + bias-pull-up = <0>; + drive-strength = <19>; + power-source = <3300>; + }; + }; }; diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index f0bad6855c97..f8747190d2e1 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -983,6 +983,21 @@ qspi: spi@d420c000 { status = "disabled"; }; + spi3: spi@d401c000 { + compatible = "spacemit,k1-spi"; + reg = <0x0 0xd401c000 0x0 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&syscon_apbc CLK_SSP3>, + <&syscon_apbc CLK_SSP3_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_SSP3>; + interrupts = <55>; + dmas = <&pdma 20>, <&pdma 19>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + /* sec_uart1: 0xf0612000, not available from Linux */ }; From d8fe8442366ffd8306575028bda92389d0dfb674 Mon Sep 17 00:00:00 2001 From: Judith Mendez Date: Tue, 24 Mar 2026 09:02:47 -0500 Subject: [PATCH 109/665] arm64: dts: ti: k3-am62a7-sk: Add bootph-all tag to vqmmc Add bootph-all property to vqmmc voltage regulator node and its corresponding pinmux node to make it available during all boot phases. This allows to run tuning early in SPL stages of boot. Fixes: 8f023012eb4a ("arm64: dts: ti: k3-am62a: Enable UHS mode support for SD cards") Cc: stable@vger.kernel.org Signed-off-by: Judith Mendez Link: https://patch.msgid.link/20260324140247.1200631-1-jm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index c1e9067b3bdd..821a9705bb7d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -154,6 +154,7 @@ vddshv_sdio: regulator-5 { gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; states = <1800000 0x0>, <3300000 0x1>; + bootph-all; }; leds { @@ -407,6 +408,7 @@ vddshv_sdio_pins_default: vddshv-sdio-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x07c, PIN_OUTPUT, 7) /* (N22) GPMC0_CLK.GPIO0_31 */ >; + bootph-all; }; main_ecap0_pins_default: main-ecap0-default-pins { From abbc2a8235944a78f0a0003fb95cdf6ec5a150a1 Mon Sep 17 00:00:00 2001 From: Akashdeep Kaur Date: Wed, 1 Apr 2026 16:52:56 +0530 Subject: [PATCH 110/665] arm64: dts: ti: k3-am62-lp-sk: Add system-power-controller On AM62-LP-SK, the TPS65219 PMIC is the system power controller responsible for handling system poweroff. Add the "system-power-controller" property to the PMIC node to explicitly designate it as such. Among all in-tree device trees using the TPS65219 PMIC (verified via compatible string), AM62-LP-SK was the only one missing this property. This patch corrects that omission. This property will be used by the PMIC driver to conditionally register the poweroff handler, ensuring only the designated power controller registers for system poweroff operations. Signed-off-by: Akashdeep Kaur Link: https://patch.msgid.link/20260401112257.1248437-2-a-kaur@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts index 8a556fbbe08b..dfd65c00f5b9 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts @@ -206,6 +206,7 @@ tps65219: pmic@30 { interrupt-parent = <&gic500>; interrupts = ; + system-power-controller; regulators { buck1_reg: buck1 { From 92468e053476537250e750ecc9bc648b0b1aef09 Mon Sep 17 00:00:00 2001 From: Abhash Kumar Jha Date: Mon, 27 Apr 2026 16:28:59 +0200 Subject: [PATCH 111/665] arm64: dts: ti: k3-j722s: Use ti,j7200-padconf compatible The pinctrl contexts for j722s should be saved and restored during suspend-to-ram, just like it is done for j7200 and j784s4 SoCs. Use ti,j7200-padconf compatible to save and restore pinctrl contexts during suspend-to-ram. Signed-off-by: Abhash Kumar Jha Signed-off-by: Richard Genoud (TI) Link: https://patch.msgid.link/20260427142901.341861-2-richard.genoud@bootlin.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi index ddf20e44f0ea..d14caa9d8619 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -432,6 +432,10 @@ &main_bcdma_csi { /* MCU domain overrides */ +&mcu_pmx0 { + compatible = "ti,j7200-padconf", "pinctrl-single"; +}; + &mcu_r5fss0_core0 { firmware-name = "j722s-mcu-r5f0_0-fw"; }; @@ -473,6 +477,10 @@ &inta_main_dmss { ti,interrupt-ranges = <7 71 21>; }; +&main_pmx0 { + compatible = "ti,j7200-padconf", "pinctrl-single"; +}; + &main_gpio0 { gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>, <&main_pmx0 70 72 17>; From e6856de612ca8941b7435c91a0f2e770d1a981e0 Mon Sep 17 00:00:00 2001 From: "Richard Genoud (TI)" Date: Mon, 27 Apr 2026 16:29:00 +0200 Subject: [PATCH 112/665] arm64: dts: ti: k3-j722s: Add mcu domain peripherals specific to J722S Introduce the "k3-j722s-mcu.dtsi" file to contain mcu domain peripherals that are specific to J722S SoC and are not shared with AM62P. Previously, those nodes were squatting the k3-j722s-main.dtsi file which should contain only main domain peripherals. Signed-off-by: Richard Genoud (TI) Link: https://patch.msgid.link/20260427142901.341861-3-richard.genoud@bootlin.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 10 ---------- arch/arm64/boot/dts/ti/k3-j722s-mcu.dtsi | 15 +++++++++++++++ arch/arm64/boot/dts/ti/k3-j722s.dtsi | 1 + 3 files changed, 16 insertions(+), 10 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-mcu.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi index d14caa9d8619..2a8aba13bd73 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -430,16 +430,6 @@ &main_bcdma_csi { ti,sci-rm-range-tchan = <0x22>; }; -/* MCU domain overrides */ - -&mcu_pmx0 { - compatible = "ti,j7200-padconf", "pinctrl-single"; -}; - -&mcu_r5fss0_core0 { - firmware-name = "j722s-mcu-r5f0_0-fw"; -}; - /* Wakeup domain overrides */ &wkup_r5fss0_core0 { diff --git a/arch/arm64/boot/dts/ti/k3-j722s-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-mcu.dtsi new file mode 100644 index 000000000000..ab43a7e49f37 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j722s-mcu.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree file for the J722S MCU domain peripherals + * + * Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2026 Bootlin + */ + +&mcu_pmx0 { + compatible = "ti,j7200-padconf", "pinctrl-single"; +}; + +&mcu_r5fss0_core0 { + firmware-name = "j722s-mcu-r5f0_0-fw"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi index 1b36dcf37925..ad477dd66963 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi @@ -238,3 +238,4 @@ cbass_wakeup: bus@b00000 { /* Include J722S specific peripherals */ #include "k3-j722s-main.dtsi" +#include "k3-j722s-mcu.dtsi" From 6c21336acd5b2adf33ec73f43f31bd389381da5f Mon Sep 17 00:00:00 2001 From: "Richard Genoud (TI)" Date: Mon, 27 Apr 2026 16:29:01 +0200 Subject: [PATCH 113/665] arm64: dts: ti: k3-j722s: Add wakeup domain peripherals specific to J722S Introduce the "k3-j722s-mcu.dtsi" file to contain wakeup domain peripherals that are specific to J722S SoC and are not shared with AM62P. Previously, those nodes were squatting the k3-j722s-main.dtsi file which should contain only main domain peripherals. Signed-off-by: Richard Genoud (TI) Link: https://patch.msgid.link/20260427142901.341861-4-richard.genoud@bootlin.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 14 -------------- arch/arm64/boot/dts/ti/k3-j722s-wakeup.dtsi | 18 ++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j722s.dtsi | 1 + 3 files changed, 19 insertions(+), 14 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-wakeup.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi index 2a8aba13bd73..d1dbf1e24fbf 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -430,13 +430,6 @@ &main_bcdma_csi { ti,sci-rm-range-tchan = <0x22>; }; -/* Wakeup domain overrides */ - -&wkup_r5fss0_core0 { - firmware-name = "j722s-wkup-r5f0_0-fw"; -}; - -/* MAIN domain overrides */ &hsm { firmware-name = "j722s-hsm-m4f-fw"; }; @@ -451,13 +444,6 @@ serdes_ln_ctrl: mux-controller@4080 { }; }; -&wkup_conf { - pcie0_ctrl: pcie0-ctrl@4070 { - compatible = "ti,j784s4-pcie-ctrl", "syscon"; - reg = <0x4070 0x4>; - }; -}; - &oc_sram { reg = <0x00 0x70000000 0x00 0x40000>; ranges = <0x00 0x00 0x70000000 0x40000>; diff --git a/arch/arm64/boot/dts/ti/k3-j722s-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-wakeup.dtsi new file mode 100644 index 000000000000..1297813f4829 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j722s-wakeup.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree file for the J722S WAKEUP domain peripherals + * + * Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2026 Bootlin + */ + +&wkup_conf { + pcie0_ctrl: pcie0-ctrl@4070 { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x4070 0x4>; + }; +}; + +&wkup_r5fss0_core0 { + firmware-name = "j722s-wkup-r5f0_0-fw"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi index ad477dd66963..ca10c6904b69 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi @@ -239,3 +239,4 @@ cbass_wakeup: bus@b00000 { /* Include J722S specific peripherals */ #include "k3-j722s-main.dtsi" #include "k3-j722s-mcu.dtsi" +#include "k3-j722s-wakeup.dtsi" From bd9fbe2781993259ea9241be7452e1355ceffb87 Mon Sep 17 00:00:00 2001 From: "Thomas Richard (TI)" Date: Wed, 29 Apr 2026 14:19:48 +0200 Subject: [PATCH 114/665] arm64: dts: ti: k3-j721s2-som-p0: add bootph-pre-ram property to PMIC-B On j721s2, PMIC-B is needed to exit the DDR from retention after suspend-to-ram. Add bootph-pre-ram property to make PMIC-B available to the bootloader in the phase that sets up the DDR. Signed-off-by: Thomas Richard (TI) Reviewed-by: Udit Kumar Link: https://patch.msgid.link/20260429-k3-j721s2-som-bootph-pre-ram-pmic-4c-v2-1-31a0e7677216@bootlin.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi index 12a38dd1514b..a19e535f4946 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -250,6 +250,7 @@ buckb1: buck1 { regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; + bootph-pre-ram; }; buckb2: buck2 { From 79c18f417a18c3211d815d6ec5b3239d74d951ea Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Thu, 30 Apr 2026 15:01:15 +0200 Subject: [PATCH 115/665] arm64: dts: ti: am62-phyboard-lyra: Add DT overlay for Lincoln LCD185-101CT panel The panel is a Lincoln Technology Solutions LCD185-101CT [0]. It is a dual-link LVDS panel and supports WUXGA resolution (1920x1200). Furthermore, it has an I2C based touch controller: Goodix-GT928. Add an device tree overlay to support the Lincoln LCD185-101CT panel in combination with the phyBOARD-Lyra-AM62x. [0] https://lincolntechsolutions.com/wp-content/uploads/2024/09/LCD185-101CTL1ARNTT_DS_R1.3.pdf Signed-off-by: Wadim Egorov Link: https://patch.msgid.link/20260430130115.2380887-1-w.egorov@phytec.de Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 4 + .../ti/k3-am62-phyboard-lyra-oldi-lcd185.dtso | 185 ++++++++++++++++++ 2 files changed, 189 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62-phyboard-lyra-oldi-lcd185.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 5269c9619b65..6aaa4a2a7561 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-zinnia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62x-phyboard-lyra-gpio-fan.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk-nand.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62-phyboard-lyra-oldi-lcd185.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am62-pocketbeagle2.dtb dtb-$(CONFIG_ARCH_K3) += k3-am6254atl-sk.dtb @@ -183,6 +184,8 @@ k3-am625-phyboard-lyra-disable-spi-nor-dtbs := k3-am625-phyboard-lyra-rdk.dtb \ k3-am6xx-phycore-disable-spi-nor.dtbo k3-am625-phyboard-lyra-gpio-fan-dtbs := k3-am625-phyboard-lyra-rdk.dtb \ k3-am62x-phyboard-lyra-gpio-fan.dtbo +k3-am625-phyboard-lyra-oldi-lcd185-dtbs := k3-am625-phyboard-lyra-rdk.dtb \ + k3-am62-phyboard-lyra-oldi-lcd185.dtbo k3-am625-phyboard-lyra-qspi-nor-dtbs := k3-am625-phyboard-lyra-rdk.dtb \ k3-am6xx-phycore-qspi-nor.dtbo k3-am625-sk-csi2-imx219-dtbs := k3-am625-sk.dtb \ @@ -287,6 +290,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am625-phyboard-lyra-disable-rtc.dtb \ k3-am625-phyboard-lyra-disable-spi-nor.dtb \ k3-am625-phyboard-lyra-gpio-fan.dtb \ + k3-am625-phyboard-lyra-oldi-lcd185.dtb \ k3-am625-phyboard-lyra-qspi-nor.dtb \ k3-am625-sk-csi2-imx219.dtb \ k3-am625-sk-csi2-ov5640.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am62-phyboard-lyra-oldi-lcd185.dtso b/arch/arm64/boot/dts/ti/k3-am62-phyboard-lyra-oldi-lcd185.dtso new file mode 100644 index 000000000000..d9f75ff28165 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-phyboard-lyra-oldi-lcd185.dtso @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2022-2026 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include "k3-pinctrl.h" + +&{/} { + display { + compatible = "lincolntech,lcd185-101ct"; + backlight = <&backlight>; + power-supply = <&vdd_usb_5v0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-odd-pixels; + lcd_in0: endpoint { + remote-endpoint = <&oldi_0_out>; + }; + }; + + port@1 { + reg = <1>; + dual-lvds-even-pixels; + lcd_in1: endpoint { + remote-endpoint = <&oldi_1_out>; + }; + }; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + enable-gpios = <&gpio_exp 5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_pwm_pins_default>; + pwms = <&epwm0 1 50000 0>; + }; + + vdd_usb_5v0: regulator-vdd-usb5v0 { + compatible = "regulator-fixed"; + regulator-name = "vdd-usb5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&dss { + pinctrl-names = "default"; + pinctrl-0 = <&main_oldi0_pins_default>, <&main_dss0_pins_default>; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* VP1: Output to OLDI */ + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dpi0_out0: endpoint@0 { + reg = <0>; + remote-endpoint = <&oldi_0_in>; + }; + + dpi0_out1: endpoint@1 { + reg = <1>; + remote-endpoint = <&oldi_1_in>; + }; + }; +}; + +&epwm0 { + status = "okay"; +}; + +&main_i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@5d { + compatible = "goodix,gt928"; + reg = <0x5d>; + + pinctrl-names = "default"; + pinctrl-0 = <&touch_screen_pins_default>; + + interrupt-parent = <&main_gpio0>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&main_gpio0 18 GPIO_ACTIVE_HIGH>; + irq-gpios = <&main_gpio0 19 GPIO_ACTIVE_HIGH>; + }; +}; + +&main_pmx0 { + bl_pwm_pins_default: bl-pwm-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01b8, PIN_INPUT, 2) /* (C13) SPI0_CS1.EHRPWM0_B */ + >; + }; + + touch_screen_pins_default: touch-screen-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x048, PIN_OUTPUT, 7) /* (N25) GPMC0_AD3.GPIO0_18 - RST */ + AM62X_IOPAD(0x04c, PIN_INPUT, 7) /* (P24) GPMC0_AD4.GPIO0_19 - INT */ + >; + }; + + main_oldi0_pins_default: main-oldi0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0260, PIN_OUTPUT, 0) /* (AA5) OLDI0_A0N */ + AM62X_IOPAD(0x025c, PIN_OUTPUT, 0) /* (Y6) OLDI0_A0P */ + AM62X_IOPAD(0x0268, PIN_OUTPUT, 0) /* (AD3) OLDI0_A1N */ + AM62X_IOPAD(0x0264, PIN_OUTPUT, 0) /* (AB4) OLDI0_A1P */ + AM62X_IOPAD(0x0270, PIN_OUTPUT, 0) /* (Y8) OLDI0_A2N */ + AM62X_IOPAD(0x026c, PIN_OUTPUT, 0) /* (AA8) OLDI0_A2P */ + AM62X_IOPAD(0x0278, PIN_OUTPUT, 0) /* (AB6) OLDI0_A3N */ + AM62X_IOPAD(0x0274, PIN_OUTPUT, 0) /* (AA7) OLDI0_A3P */ + AM62X_IOPAD(0x0280, PIN_OUTPUT, 0) /* (AC6) OLDI0_A4N */ + AM62X_IOPAD(0x027c, PIN_OUTPUT, 0) /* (AC5) OLDI0_A4P */ + AM62X_IOPAD(0x0288, PIN_OUTPUT, 0) /* (AE5) OLDI0_A5N */ + AM62X_IOPAD(0x0284, PIN_OUTPUT, 0) /* (AD6) OLDI0_A5P */ + AM62X_IOPAD(0x0290, PIN_OUTPUT, 0) /* (AE6) OLDI0_A6N */ + AM62X_IOPAD(0x028c, PIN_OUTPUT, 0) /* (AD7) OLDI0_A6P */ + AM62X_IOPAD(0x0298, PIN_OUTPUT, 0) /* (AD8) OLDI0_A7N */ + AM62X_IOPAD(0x0294, PIN_OUTPUT, 0) /* (AE7) OLDI0_A7P */ + AM62X_IOPAD(0x02a0, PIN_OUTPUT, 0) /* (AD4) OLDI0_CLK0N */ + AM62X_IOPAD(0x029c, PIN_OUTPUT, 0) /* (AE3) OLDI0_CLK0P */ + AM62X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (AE4) OLDI0_CLK1N */ + AM62X_IOPAD(0x02a4, PIN_OUTPUT, 0) /* (AD5) OLDI0_CLK1P */ + >; + }; +}; + +&oldi0 { + ti,companion-oldi = <&oldi1>; + status = "okay"; +}; + +&oldi0_port0 { + oldi_0_in: endpoint { + remote-endpoint = <&dpi0_out0>; + }; +}; + +&oldi0_port1 { + oldi_0_out: endpoint { + remote-endpoint = <&lcd_in0>; + }; +}; + +&oldi1 { + ti,secondary-oldi; + status = "okay"; +}; + +&oldi1_port0 { + oldi_1_in: endpoint { + remote-endpoint = <&dpi0_out1>; + }; +}; + +&oldi1_port1 { + oldi_1_out: endpoint { + remote-endpoint = <&lcd_in1>; + }; +}; From d8961140aecdd68a57ac1ca11327964a709d5ae5 Mon Sep 17 00:00:00 2001 From: Nora Schiffer Date: Mon, 2 Mar 2026 11:14:58 +0100 Subject: [PATCH 116/665] dt-bindings: arm: ti: Add compatible for AM625-based TQMa62xx SOM family and carrier board The TQMa62xx is a SoM family with a pluggable connector. The MBa62xx is the matching reference/starterkit carrier board. Signed-off-by: Nora Schiffer Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/af87b54279e3d0b7dceccd2625f0ed7c5e06b83e.1772443991.git.nora.schiffer@ew.tq-group.com Signed-off-by: Nishanth Menon --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index 2a6a9441c23d..69b5441cbf1a 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -97,6 +97,13 @@ properties: - const: toradex,verdin-am62 # Verdin AM62 Module - const: ti,am625 + - description: K3 AM625 SoC on TQ-Systems TQMa62xx SoM + items: + - enum: + - tq,am625-tqma6254-mba62xx # MBa62xx base board + - const: tq,am625-tqma6254 + - const: ti,am625 + - description: K3 AM62P5 SoC Toradex Verdin Modules and Carrier Boards items: - enum: From 5b36d8c72c91d0f213c712472caf03192e373c0a Mon Sep 17 00:00:00 2001 From: Nora Schiffer Date: Mon, 2 Mar 2026 11:14:59 +0100 Subject: [PATCH 117/665] arm64: dts: ti: Add TQ-Systems TQMa62xx SoM and MBa62xx carrier board Device Trees The TQMa62xx is a SoM family with a pluggable board connector based on the TI AM62x SoCs. Add DTS(I) for the AM625 (2x Cortex-A53) variant and its combination with our MBa62xx carrier board. Signed-off-by: Nora Schiffer Link: https://patch.msgid.link/333774a1d8787810cd008e63342899ee1ec0fd9d.1772443991.git.nora.schiffer@ew.tq-group.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 1 + .../boot/dts/ti/k3-am625-tqma62xx-mba62xx.dts | 1033 +++++++++++++++++ arch/arm64/boot/dts/ti/k3-am625-tqma62xx.dtsi | 360 ++++++ 3 files changed, 1394 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-tqma62xx-mba62xx.dts create mode 100644 arch/arm64/boot/dts/ti/k3-am625-tqma62xx.dtsi diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 6aaa4a2a7561..7642c06ca834 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -14,6 +14,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay-csi2-ov5640.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay-csi2-tevi-ov5640.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-tqma62xx-mba62xx.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dev.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-ivy.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am625-tqma62xx-mba62xx.dts b/arch/arm64/boot/dts/ti/k3-am625-tqma62xx-mba62xx.dts new file mode 100644 index 000000000000..efc00d2a860a --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-tqma62xx-mba62xx.dts @@ -0,0 +1,1033 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (c) 2023-2026 TQ-Systems GmbH , D-82229 Seefeld, Germany. + * Author: Nora Schiffer + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "k3-am625-tqma62xx.dtsi" + +/ { + compatible = "tq,am625-tqma6254-mba62xx", "tq,am625-tqma6254", + "ti,am625"; + model = "TQ-Systems TQMa62xx SoM on MBa62xx carrier board"; + chassis-type = "embedded"; + + aliases { + can0 = &mcu_mcan0; + can1 = &mcu_mcan1; + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; + i2c1 = &main_i2c1; + mmc1 = &sdhci1; + mmc2 = &sdhci2; + serial0 = &main_uart0; + serial1 = &mcu_uart0; + spi1 = &main_spi0; + usb0 = &usb0; + usb1 = &usb1; + }; + + chosen { + stdout-path = &main_uart0; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&backlight_pins>; + enable-gpios = <&main_gpio0 38 GPIO_ACTIVE_HIGH>; + /* Enabled by display overlays */ + status = "disabled"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_key_pins>; + + user-button { + label = "USER_BUTTON"; + linux,code = ; + gpios = <&main_gpio0 40 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_led_pins>; + + led-1 { + gpios = <&main_gpio0 41 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_INDICATOR; + }; + + led-2 { + gpios = <&main_gpio0 42 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_INDICATOR; + }; + }; + + panel: panel { + pinctrl-names = "default"; + pinctrl-0 = <&lvds_panel_pins>; + enable-gpios = <&main_gpio0 36 GPIO_ACTIVE_HIGH>; + power-supply = <®_lvds_pwr>; + /* Completed and enabled by display overlays */ + status = "disabled"; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_fan_pins>; + fan-supply = <®_pwm_fan>; + #cooling-cells = <2>; + /* typical 25 kHz -> 40.000 nsec */ + pwms = <&epwm0 1 40000 PWM_POLARITY_INVERTED>; + cooling-levels = <0 32 64 128 196 240>; + pulses-per-revolution = <2>; + interrupt-parent = <&main_gpio1>; + interrupts = <30 IRQ_TYPE_EDGE_FALLING>; + /* + * 4-pin connector for optional fan - disabled by default, as + * PWM period may need to be adjusted for the used fan + */ + status = "disabled"; + }; + + wifi_pwrseq: pwrseq-wifi { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc2_pwrseq_pins>; + reset-gpios = <&main_gpio0 44 GPIO_ACTIVE_HIGH>; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "V_1V8_MBA"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_3v3_sd: regulator-3v3-sd { + /* TPS22963CYZTP */ + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <®_3v3_sd_pins>; + regulator-name = "V_3V3_SD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply = <®_3v3>; + gpio = <&main_gpio1 8 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + reg_lvds_pwr: regulator-lvds-pwr { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <®_lvds_pwr_pins>; + regulator-name = "LVDS0_PWR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + vin-supply = <®_3v3>; + gpio = <&main_gpio0 61 GPIO_ACTIVE_HIGH>; + }; + + reg_pwm_fan: regulator-pwm-fan { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <®_pwm_fan_pins>; + regulator-name = "FAN_PWR"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&main_gpio0 62 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "tqm-tlv320aic32"; + simple-audio-card,widgets = + "Line Out", "Line Out", + "Line In", "Line In", + "Microphone", "Microphone Jack"; + simple-audio-card,routing = + "Line Out", "LOL", + "Line Out", "LOR", + "IN1_L", "Line In", + "IN1_R", "Line In", + "IN3_L", "Microphone Jack", + "Microphone Jack", "Mic Bias"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + + simple-audio-card,cpu { + sound-dai = <&mcasp1>; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&tlv320aic32x4>; + clocks = <&audio_refclk0>; + }; + }; +}; + +&audio_refclk0 { + /* Set parent to POSTDIV1_16FFT_MAIN_1_HSDIVOUT6, for 96MHz clock output */ + assigned-clock-parents = <&k3_clks 157 7>; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&main_rgmii1_pins>, <&main_rgmii2_pins>; + status = "okay"; +}; + +&cpsw_port1 { + phy-mode = "rgmii-id"; + phy-handle = <&cpsw3g_phy0>; +}; + +&cpsw_port2 { + phy-mode = "rgmii-id"; + phy-handle = <&cpsw3g_phy3>; +}; + +&cpsw3g_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&main_mdio1_pins>; + status = "okay"; + + cpsw3g_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + reset-gpios = <&main_gpio1 11 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + ti,fifo-depth = ; + ti,clk-output-sel = ; + }; + + cpsw3g_phy3: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x3>; + reset-gpios = <&main_gpio1 12 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + ti,fifo-depth = ; + ti,clk-output-sel = ; + }; +}; + +&dss { + pinctrl-names = "default"; + pinctrl-0 = <&dss_pins>; +}; + +&epwm0 { + status = "okay"; +}; + +&epwm1 { + status = "okay"; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio0_pins>, <&main_gpio0_pr0_pins>; + gpio-line-names = + "", "", "", "", /* 0-3 */ + "", "", "", "", /* 4-7 */ + "", "", "", "", /* 8-11 */ + "ADC_SYNC", "ADC_RST#", "ADC_DATA_RDY", "", /* 12-15 */ + "", "", "", "", /* 16-19 */ + "", "", "", "", /* 20-23 */ + "", "", "", "", /* 24-27 */ + "", "", "", "", /* 28-31 */ + "", "", "", "", /* 32-35 */ + "", "", "", "BG95_PWRKEY", /* 36-39 */ + "", "", "", "BG95_RESET", /* 40-43 */ + "", "", "", "", /* 44-47 */ + "", "", "", "", /* 48-51 */ + "", "", "", "", /* 52-55 */ + "", "", "", "", /* 56-59 */ + "", "", "", "", /* 60-63 */ + "", "", "", "", /* 64-67 */ + "", "", "", "", /* 68-71 */ + "ADC_INT"; /* 72- */ + bootph-all; +}; + +&main_gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio1_pins>, <&main_gpio1_pr0_pins>; + bootph-all; + + /* No overcurrent handling in USB host driver - pin is hogged for now */ + line7-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + line-name = "USB0_VBUS_OC#"; + input; + }; +}; + +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins>; + clock-frequency = <400000>; + status = "okay"; + + tlv320aic32x4: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + pinctrl-names = "default"; + pinctrl-0 = <&audio_codec_pins>; + #sound-dai-cells = <0>; + clock-names = "mclk"; + clocks = <&audio_refclk0>; + reset-gpios = <&main_gpio0 33 GPIO_ACTIVE_LOW>; + iov-supply = <®_1v8>; + ldoin-supply = <®_3v3>; + }; +}; + +&main_spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_spi0_pins>; + ti,pindir-d0-out-d1-in; + status = "okay"; + + /* adc@0: NXP NAFE13388 */ +}; + +&main0_thermal { + trips { + main0_active0: trip-active0 { + temperature = <40000>; + hysteresis = <5000>; + type = "active"; + }; + + main0_active1: trip-active1 { + temperature = <48000>; + hysteresis = <3000>; + type = "active"; + }; + + main0_active2: trip-active2 { + temperature = <60000>; + hysteresis = <10000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + trip = <&main0_active0>; + cooling-device = <&fan0 1 1>; + }; + + map2 { + trip = <&main0_active1>; + cooling-device = <&fan0 2 2>; + }; + + map3 { + trip = <&main0_active2>; + cooling-device = <&fan0 3 3>; + }; + }; +}; + +&main1_thermal { + trips { + main1_active0: trip-active0 { + temperature = <40000>; + hysteresis = <5000>; + type = "active"; + }; + + main1_active1: trip-active1 { + temperature = <48000>; + hysteresis = <3000>; + type = "active"; + }; + + main1_active2: trip-active2 { + temperature = <60000>; + hysteresis = <10000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + trip = <&main1_active0>; + cooling-device = <&fan0 1 1>; + }; + + map2 { + trip = <&main1_active1>; + cooling-device = <&fan0 2 2>; + }; + + map3 { + trip = <&main1_active2>; + cooling-device = <&fan0 3 3>; + }; + }; +}; + +/* Main console */ +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins>; + bootph-all; + status = "okay"; +}; + +/* + * IOT module - GNSS UART + * + * Board configuration must not enable UART trace output for TIFS firmware + */ +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins>; + /* IOT module uses USB by default, UART can be enabled as fallback */ + status = "disabled"; +}; + +/* Bluetooth module */ +&main_uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart2_pins>; + /* Bluetooth module uses SDIO by default, UART can be enabled as fallback */ + status = "disabled"; +}; + +/* IOT module - main UART */ +&main_uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart5_pins>; + /* IOT module uses USB by default, UART can be enabled as fallback */ + status = "disabled"; +}; + +&mcasp1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcasp1_pins>; + #sound-dai-cells = <0>; + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 0 2 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tx-num-evt = <0>; + rx-num-evt = <0>; + status = "okay"; +}; + +&mcu_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_gpio0_pins>; + gpio-line-names = + "EN_DIG_OUT_1", "EN_DIG_OUT_2", "STATUS_OUT_1", "STATUS_OUT_2", /* 0-3 */ + "EN_DIG_OUT_3", "", "", "V_VPP_EN", /* 4-7 */ + "", "", "", "EN_DIG_OUT_4", /* 8-11 */ + "STATUS_OUT_3", "", "", "", /* 12-15 */ + "", "STATUS_OUT_4", "DIG_IN_1", "DIG_IN_2", /* 16-19 */ + "DIG_IN_3", "", "", "DIG_IN_4"; /* 20-23 */ + bootph-all; +}; + +&mcu_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_pins>; + status = "okay"; +}; + +&mcu_mcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_pins>; + status = "okay"; +}; + +&mcu_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins>; + rs485-rts-active-low; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +®_sd { + pinctrl-names = "default"; + pinctrl-0 = <®_sd_pins>; + gpios = <&main_gpio0 31 GPIO_ACTIVE_LOW>; + bootph-all; + status = "okay"; +}; + +&sdhci1 { + /* SD-card */ + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins>; + vmmc-supply = <®_3v3_sd>; + vqmmc-supply = <®_sd>; + bus-width = <4>; + disable-wp; + no-mmc; + no-sdio; + bootph-all; + ti,driver-strength-ohm = <50>; + status = "okay"; +}; + +&sdhci2 { + /* WLAN */ + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc2_pins>; + mmc-pwrseq = <&wifi_pwrseq>; + keep-power-in-suspend; + cap-power-off-card; + bus-width = <4>; + non-removable; + no-mmc; + no-sd; + ti,driver-strength-ohm = <50>; + ti,fails-without-test-cd; + status = "okay"; +}; + +&usbss0 { + bootph-all; + ti,vbus-divider; + status = "okay"; +}; + +&usbss1 { + ti,vbus-divider; + status = "okay"; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_usb0_pins>; + dr_mode = "otg"; + usb-role-switch; + bootph-all; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + id-gpios = <&main_gpio0 71 GPIO_ACTIVE_HIGH>; + type = "micro"; + }; +}; + +&usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_usb1_hub_pins>; + #address-cells = <1>; + #size-cells = <0>; + dr_mode = "host"; + + usb1_hub_2_0: hub@1 { + compatible = "usb424,2514"; + reg = <1>; + reset-gpios = <&main_gpio1 23 GPIO_ACTIVE_HIGH>; + vdd-supply = <®_3v3>; + vdda-supply = <®_3v3>; + }; +}; + +&wkup_uart0 { + /* WKUP UART0 is used by DM firmware */ + status = "reserved"; +}; + +&main_pmx0 { + audio_codec_pins: audio-codec-pins { + pinctrl-single,pins = < + /* (L24) GPMC0_OEn_REn.GPIO0_33 */ + AM62X_IOPAD(0x088, PIN_OUTPUT, 7) + /* (A15) UART0_CTSn.AUDIO_EXT_REFCLK0 */ + AM62X_IOPAD(0x1d0, PIN_OUTPUT, 5) + >; + }; + + backlight_pins: backlight-pins { + pinctrl-single,pins = < + /* (V25) GPMC0_WAIT1.GPIO0_38 */ + AM62X_IOPAD(0x009c, PIN_OUTPUT, 7) + /* (E18) MCASP0_AXR0.EHRPWM1_B */ + AM62X_IOPAD(0x01a0, PIN_OUTPUT, 6) + >; + }; + + dss_pins: dss-pins { + pinctrl-single,pins = < + /* (AA5) OLDI0_A0N */ + AM62X_IOPAD(0x0260, PIN_OUTPUT, 0) + /* (Y6) OLDI0_A0P */ + AM62X_IOPAD(0x025c, PIN_OUTPUT, 0) + /* (AD3) OLDI0_A1N */ + AM62X_IOPAD(0x0268, PIN_OUTPUT, 0) + /* (AB4) OLDI0_A1P */ + AM62X_IOPAD(0x0264, PIN_OUTPUT, 0) + /* (Y8) OLDI0_A2N */ + AM62X_IOPAD(0x0270, PIN_OUTPUT, 0) + /* (AA8) OLDI0_A2P */ + AM62X_IOPAD(0x026c, PIN_OUTPUT, 0) + /* (AB6) OLDI0_A3N */ + AM62X_IOPAD(0x0278, PIN_OUTPUT, 0) + /* (AA7) OLDI0_A3P */ + AM62X_IOPAD(0x0274, PIN_OUTPUT, 0) + /* (AC6) OLDI0_A4N */ + AM62X_IOPAD(0x0280, PIN_OUTPUT, 0) + /* (AC5) OLDI0_A4P */ + AM62X_IOPAD(0x027c, PIN_OUTPUT, 0) + /* (AE5) OLDI0_A5N */ + AM62X_IOPAD(0x0288, PIN_OUTPUT, 0) + /* (AD6) OLDI0_A5P */ + AM62X_IOPAD(0x0284, PIN_OUTPUT, 0) + /* (AE6) OLDI0_A6N */ + AM62X_IOPAD(0x0290, PIN_OUTPUT, 0) + /* (AD7) OLDI0_A6P */ + AM62X_IOPAD(0x028c, PIN_OUTPUT, 0) + /* (AD8) OLDI0_A7N */ + AM62X_IOPAD(0x0298, PIN_OUTPUT, 0) + /* (AE7) OLDI0_A7P */ + AM62X_IOPAD(0x0294, PIN_OUTPUT, 0) + /* (AD4) OLDI0_CLK0N */ + AM62X_IOPAD(0x02a0, PIN_OUTPUT, 0) + /* (AE3) OLDI0_CLK0P */ + AM62X_IOPAD(0x029c, PIN_OUTPUT, 0) + /* (AE4) OLDI0_CLK1N */ + AM62X_IOPAD(0x02a8, PIN_OUTPUT, 0) + /* (AD5) OLDI0_CLK1P */ + AM62X_IOPAD(0x02a4, PIN_OUTPUT, 0) + >; + }; + + csi_clk_pins: csi-clk-pins { + pinctrl-single,pins = < + /* (B18) MCASP0_AXR1.EHRPWM1_A */ + AM62X_IOPAD(0x019c, PIN_OUTPUT, 6) + >; + }; + + gpio_key_pins: gpio-key-pins { + pinctrl-single,pins = < + /* (M22) GPMC0_DIR.GPIO0_40 */ + AM62X_IOPAD(0x0a4, PIN_INPUT, 7) + >; + }; + + gpio_led_pins: gpio-led-pins { + pinctrl-single,pins = < + /* (M21) GPMC0_CSn0.GPIO0_41 */ + AM62X_IOPAD(0x0a8, PIN_OUTPUT, 7) + /* (L21) GPMC0_CSn1.GPIO0_42 */ + AM62X_IOPAD(0x0ac, PIN_OUTPUT, 7) + >; + }; + + lvds_panel_pins: lvds-panel-pins { + pinctrl-single,pins = < + /* (N20) GPMC0_BE1n.GPIO0_36 - LVDS0_RESET# */ + AM62X_IOPAD(0x0094, PIN_OUTPUT, 7) + >; + }; + + main_gpio0_pins: main-gpio0-pins { + pinctrl-single,pins = < + /* Control GPIOs for IOT Module */ + /* (K25) GPMC0_WPn.GPIO0_39 - BG95_PWRKEY */ + AM62X_IOPAD(0x0a0, PIN_OUTPUT, 7) + /* (K22) GPMC0_CSn2.GPIO0_43 - BG95_RESET */ + AM62X_IOPAD(0x0b0, PIN_OUTPUT, 7) + >; + }; + + main_gpio0_pr0_pins: main-gpio0-pr0-pins { + pinctrl-single,pins = < + /* (N24) GPMC0_AD2.GPIO0_17 */ + AM62X_IOPAD(0x0044, PIN_INPUT, 7) + /* (N25) GPMC0_AD3.GPIO0_18 */ + AM62X_IOPAD(0x0048, PIN_INPUT, 7) + /* (P24) GPMC0_AD4.GPIO0_19 */ + AM62X_IOPAD(0x004c, PIN_INPUT, 7) + /* (P22) GPMC0_AD5.GPIO0_20 */ + AM62X_IOPAD(0x0050, PIN_INPUT, 7) + /* (W25) VOUT0_DATA2.GPIO0_47 */ + AM62X_IOPAD(0x00c0, PIN_INPUT, 7) + /* (W24) VOUT0_DATA3.GPIO0_48 */ + AM62X_IOPAD(0x00c4, PIN_INPUT, 7) + /* (Y25) VOUT0_DATA4.GPIO0_49 */ + AM62X_IOPAD(0x00c8, PIN_INPUT, 7) + /* (Y24) VOUT0_DATA5.GPIO0_50 */ + AM62X_IOPAD(0x00cc, PIN_INPUT, 7) + >; + }; + + main_gpio1_pins: main-gpio1-pins { + pinctrl-single,pins = < + /* (B19) MCASP0_AXR3.GPIO1_7 - USB0_VBUS_OC# */ + AM62X_IOPAD(0x0194, PIN_INPUT, 7) + >; + }; + + main_gpio1_pr0_pins: main-gpio1-pr0-pins { + pinctrl-single,pins = < + /* (C15) MCAN0_TX.GPIO1_24 */ + AM62X_IOPAD(0x01d8, PIN_INPUT, 7) + /* (E15) MCAN0_RX.GPIO1_25 */ + AM62X_IOPAD(0x01dc, PIN_INPUT, 7) + >; + }; + + main_i2c1_pins: main-i2c1-pins { + pinctrl-single,pins = < + /* (B17) I2C1_SCL */ + AM62X_IOPAD(0x1e8, PIN_INPUT, 0) + /* (A17) I2C1_SDA */ + AM62X_IOPAD(0x1ec, PIN_INPUT, 0) + >; + }; + + main_mcasp1_pins: main-mcasp1-pins { + pinctrl-single,pins = < + /* (M24) GPMC0_BE0N_CLE.MCASP1_ACLKX */ + AM62X_IOPAD(0x090, PIN_INPUT, 2) + /* (U23) GPMC0_WAIT0.MCASP1_AFSX */ + AM62X_IOPAD(0x098, PIN_INPUT, 2) + /* (L25) GPMC0_WEN.MCASP1_AXR0 */ + AM62X_IOPAD(0x08c, PIN_OUTPUT, 2) + /* (L23) GPMC0_ADVN_ALE.MCASP1_AXR2 */ + AM62X_IOPAD(0x084, PIN_INPUT, 2) + >; + }; + + main_mmc1_pins: main-mmc1-pins { + pinctrl-single,pins = < + /* (A21) MMC1_CMD */ + AM62X_IOPAD(0x23c, PIN_INPUT, 0) + /* (B22) MMC1_CLK */ + AM62X_IOPAD(0x234, PIN_INPUT, 0) + /* (A22) MMC1_DAT0 */ + AM62X_IOPAD(0x230, PIN_INPUT, 0) + /* (B21) MMC1_DAT1 */ + AM62X_IOPAD(0x22c, PIN_INPUT, 0) + /* (C21) MMC1_DAT2 */ + AM62X_IOPAD(0x228, PIN_INPUT, 0) + /* (D22) MMC1_DAT3 */ + AM62X_IOPAD(0x224, PIN_INPUT, 0) + /* (D17) MMC1_SDCD */ + AM62X_IOPAD(0x240, PIN_INPUT, 0) + >; + bootph-all; + }; + + main_mmc2_pins: main-mmc2-pins { + pinctrl-single,pins = < + /* (C24) MMC2_CMD */ + AM62X_IOPAD(0x120, PIN_INPUT, 0) + /* (D25) MMC2_CLK */ + AM62X_IOPAD(0x118, PIN_INPUT, 0) + /* (B24) MMC2_DAT0 */ + AM62X_IOPAD(0x114, PIN_INPUT, 0) + /* (C25) MMC2_DAT1 */ + AM62X_IOPAD(0x110, PIN_INPUT, 0) + /* (E23) MMC2_DAT2 */ + AM62X_IOPAD(0x10c, PIN_INPUT, 0) + /* (D24) MMC2_DAT3 */ + AM62X_IOPAD(0x108, PIN_INPUT, 0) + /* (#N/A) MMC2_CLKB */ + AM62X_IOPAD(0x11c, PIN_INPUT, 0) + >; + }; + + main_mmc2_pwrseq_pins: main-mmc2-pwrseq-pins { + pinctrl-single,pins = < + /* (K24) GPMC0_CSn3.GPIO0_44 - WIFI-BT_EN */ + AM62X_IOPAD(0x00b4, PIN_OUTPUT, 7) + >; + }; + + main_mdio1_pins: main-mdio1-pins { + pinctrl-single,pins = < + /* (B20) MCASP0_ACLKX.GPIO1_11 - RESET_RGMII1# */ + AM62X_IOPAD(0x1a4, PIN_OUTPUT, 7) + /* (D20) MCASP0_AFSX.GPIO1_12 - RESET_RGMII2# */ + AM62X_IOPAD(0x1a8, PIN_OUTPUT, 7) + + /* (AD24) MDIO0_MDC */ + AM62X_IOPAD(0x160, PIN_OUTPUT, 0) + /* (AB22) MDIO0_MDIO */ + AM62X_IOPAD(0x15c, PIN_INPUT, 0) + >; + }; + + main_rgmii1_pins: main-rgmii1-pins { + pinctrl-single,pins = < + /* (AB17) RGMII1_RD0 */ + AM62X_IOPAD(0x14c, PIN_INPUT, 0) + /* (AC17) RGMII1_RD1 */ + AM62X_IOPAD(0x150, PIN_INPUT, 0) + /* (AB16) RGMII1_RD2 */ + AM62X_IOPAD(0x154, PIN_INPUT, 0) + /* (AA15) RGMII1_RD3 */ + AM62X_IOPAD(0x158, PIN_INPUT, 0) + /* (AD17) RGMII1_RXC */ + AM62X_IOPAD(0x148, PIN_INPUT, 0) + /* (AE17) RGMII1_RX_CTL */ + AM62X_IOPAD(0x144, PIN_INPUT, 0) + /* (AE20) RGMII1_TD0 */ + AM62X_IOPAD(0x134, PIN_OUTPUT, 0) + /* (AD20) RGMII1_TD1 */ + AM62X_IOPAD(0x138, PIN_OUTPUT, 0) + /* (AE18) RGMII1_TD2 */ + AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) + /* (AD18) RGMII1_TD3 */ + AM62X_IOPAD(0x140, PIN_OUTPUT, 0) + /* (AE19) RGMII1_TXC */ + AM62X_IOPAD(0x130, PIN_OUTPUT, 0) + /* (AD19) RGMII1_TX_CTL */ + AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) + >; + }; + + main_rgmii2_pins: main-rgmii2-pins { + pinctrl-single,pins = < + /* (AE23) RGMII2_RD0 */ + AM62X_IOPAD(0x184, PIN_INPUT, 0) + /* (AB20) RGMII2_RD1 */ + AM62X_IOPAD(0x188, PIN_INPUT, 0) + /* (AC21) RGMII2_RD2 */ + AM62X_IOPAD(0x18c, PIN_INPUT, 0) + /* (AE22) RGMII2_RD3 */ + AM62X_IOPAD(0x190, PIN_INPUT, 0) + /* (AD23) RGMII2_RXC */ + AM62X_IOPAD(0x180, PIN_INPUT, 0) + /* (AD22) RGMII2_RX_CTL */ + AM62X_IOPAD(0x17c, PIN_INPUT, 0) + /* (Y18) RGMII2_TD0 */ + AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) + /* (AA18) RGMII2_TD1 */ + AM62X_IOPAD(0x170, PIN_OUTPUT, 0) + /* (AD21) RGMII2_TD2 */ + AM62X_IOPAD(0x174, PIN_OUTPUT, 0) + /* (AC20) RGMII2_TD3 */ + AM62X_IOPAD(0x178, PIN_OUTPUT, 0) + /* (AE21) RGMII2_TXC */ + AM62X_IOPAD(0x168, PIN_OUTPUT, 0) + /* (AA19) RGMII2_TX_CTL */ + AM62X_IOPAD(0x164, PIN_OUTPUT, 0) + >; + }; + + main_spi0_pins: main-spi0-pins { + pinctrl-single,pins = < + /* (A14) SPI0_CLK */ + AM62X_IOPAD(0x1bc, PIN_OUTPUT, 0) + /* (A13) SPI0_CS0 */ + AM62X_IOPAD(0x1b4, PIN_OUTPUT, 0) + /* (B13) SPI0_D0 */ + AM62X_IOPAD(0x1c0, PIN_OUTPUT, 0) + /* (B14) SPI0_D1 */ + AM62X_IOPAD(0x1c4, PIN_INPUT, 0) + >; + }; + + main_spi0_adc_pins: main-spi0-adc-pins { + pinctrl-single,pins = < + /* (G21) OSPI0_CSn1.GPIO0_12 - ADC_SYNC */ + AM62X_IOPAD(0x030, PIN_INPUT, 7) + /* (H21) OSPI0_CSn2.GPIO0_13 - ADC_RST# */ + AM62X_IOPAD(0x034, PIN_OUTPUT, 7) + /* (E24) OSPI0_CSn3.GPIO0_14 - ADC_DATA_RDY */ + AM62X_IOPAD(0x038, PIN_INPUT, 7) + /* (B23) MMC2_SDWP.GPIO0_72 - ADC_INT# */ + AM62X_IOPAD(0x128, PIN_INPUT, 7) + >; + }; + + main_uart0_pins: main-uart0-pins { + pinctrl-single,pins = < + /* (D14) UART0_RXD */ + AM62X_IOPAD(0x1c8, PIN_INPUT, 0) + /* (E14) UART0_TXD */ + AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) + >; + bootph-all; + }; + + main_uart1_pins: main-uart1-pins { + pinctrl-single,pins = < + /* (E19) MCASP0_AFSR.UART1_RXD */ + AM62X_IOPAD(0x1ac, PIN_INPUT, 2) + /* (A20) MCASP0_ACLKR.UART1_TXD */ + AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) + >; + }; + + main_uart2_pins: main-uart2-pins { + pinctrl-single,pins = < + /* (U22) VOUT0_DATA0.UART2_RXD */ + AM62X_IOPAD(0x0b8, PIN_INPUT, 4) + /* (V24) VOUT0_DATA1.UART2_TXD */ + AM62X_IOPAD(0x0bc, PIN_OUTPUT, 4) + /* (AC24) VOUT0_PCLK.UART2_CTS# */ + AM62X_IOPAD(0x104, PIN_INPUT, 4) + /* (AC25) VOUT0_VSYNC.UART2_RTS# */ + AM62X_IOPAD(0x100, PIN_OUTPUT, 4) + >; + }; + + main_uart5_pins: main-uart5-pins { + pinctrl-single,pins = < + /* (Y23) VOUT0_DATA6.UART5_RXD */ + AM62X_IOPAD(0x0d0, PIN_INPUT, 4) + /* (AA25) VOUT0_DATA7.UART5_TXD */ + AM62X_IOPAD(0x0d4, PIN_OUTPUT, 4) + >; + }; + + main_usb0_pins: main-usb0-pins { + pinctrl-single,pins = < + /* (C20) USB0_DRVVBUS */ + AM62X_IOPAD(0x254, PIN_OUTPUT, 0) + /* (A23) MMC2_SDCD.GPIO0_71 */ + AM62X_IOPAD(0x124, PIN_INPUT, 7) + >; + }; + + main_usb1_hub_pins: main-usb1-hub-pins { + pinctrl-single,pins = < + /* (B15) UART0_RTSn.GPIO1_23 - USB_HUB_RESET */ + AM62X_IOPAD(0x01d4, PIN_OUTPUT, 7) + >; + }; + + pwm_fan_pins: pwm-fan-pins { + pinctrl-single,pins = < + /* (C13) SPI0_CS1.EHRPWM0_B - FAN_PWM */ + AM62X_IOPAD(0x01b8, PIN_OUTPUT, 2) + /* (A18) EXT_REFCLK1.GPIO1_30 - FAN_RPM */ + AM62X_IOPAD(0x01f0, PIN_INPUT, 7) + >; + }; + + reg_3v3_sd_pins: reg-3v3-sd-pins { + pinctrl-single,pins = < + /* (A19) MCASP0_AXR2.GPIO1_8 */ + AM62X_IOPAD(0x198, PIN_OUTPUT, 7) + >; + bootph-all; + }; + + reg_lvds_pwr_pins: reg-lvds-pwr-pins { + pinctrl-single,pins = < + /* (AB24) VOUT0_HSYNC.GPIO0_61 */ + AM62X_IOPAD(0x00f8, PIN_OUTPUT, 7) + >; + }; + + reg_pwm_fan_pins: reg-pwm-fan-pins { + pinctrl-single,pins = < + /* (Y20) VOUT0_DE.GPIO0_62 */ + AM62X_IOPAD(0x00fc, PIN_OUTPUT, 7) + >; + }; + + reg_sd_pins: reg-sd-pins { + pinctrl-single,pins = < + /* (P25) GPMC0_CLK.GPIO0_31 */ + AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) + >; + bootph-all; + }; +}; + +&mcu_pmx0 { + mcu_gpio0_pins: mcu-gpio0-pins { + pinctrl-single,pins = < + /* (E8) MCU_SPI0_CS0.MCU_GPIO0_0 - EN_DIG_OUT1 */ + AM62X_MCU_IOPAD(0x000, PIN_OUTPUT, 7) + /* (B8) MCU_SPI0_CS1.MCU_GPIO0_1 - EN_DIG_OUT2 */ + AM62X_MCU_IOPAD(0x004, PIN_OUTPUT, 7) + /* (A7) MCU_SPI0_CLK.MCU_GPIO0_2 - STATUS_OUT1 */ + AM62X_MCU_IOPAD(0x008, PIN_INPUT, 7) + /* (D9) MCU_SPI0_D0.MCU_GPIO0_3 - STATUS_OUT2 */ + AM62X_MCU_IOPAD(0x00c, PIN_INPUT, 7) + /* (C9) MCU_SPI0_D1.MCU_GPIO0_4 - EN_DIG_OUT3 */ + AM62X_MCU_IOPAD(0x010, PIN_OUTPUT, 7) + /* (C6) WKUP_UART0_CTSn.MCU_GPIO0_11 - EN_DIG_OUT4 */ + AM62X_MCU_IOPAD(0x02c, PIN_OUTPUT, 7) + /* (A4) WKUP_UART0_RTSn.MCU_GPIO0_12 - STATUS_OUT3 */ + AM62X_MCU_IOPAD(0x030, PIN_INPUT, 7) + /* (A8) MCU_I2C0_SCL.MCU_GPIO0_17 - STATUS_OUT4 */ + AM62X_MCU_IOPAD(0x044, PIN_INPUT, 7) + /* (D10) MCU_I2C0_SDA.MCU_GPIO0_18 - DIG_IN_1 */ + AM62X_MCU_IOPAD(0x048, PIN_INPUT, 7) + /* (B9) WKUP_I2C0_SCL.MCU_GPIO0_19 - DIG_IN_2 */ + AM62X_MCU_IOPAD(0x04c, PIN_INPUT, 7) + /* (A9) WKUP_I2C0_SDA.MCU_GPIO0_20 - DIG_IN_3 */ + AM62X_MCU_IOPAD(0x050, PIN_INPUT, 7) + /* (A12) WKUP_CLKOUT0.MCU_GPIO0_23 - DIG_IN_4 */ + AM62X_MCU_IOPAD(0x084, PIN_INPUT, 7) + /* (A6) MCU_UART0_CTSn.MCU_GPIO0_7 - V_VPP_EN */ + AM62X_MCU_IOPAD(0x01c, PIN_OUTPUT, 7) + >; + }; + mcu_mcan0_pins: mcu-mcan0-pins { + pinctrl-single,pins = < + /* (B3) MCU_MCAN0_RX */ + AM62X_MCU_IOPAD(0x038, PIN_INPUT, 0) + /* (D6) MCU_MCAN0_TX */ + AM62X_MCU_IOPAD(0x034, PIN_OUTPUT, 0) + >; + }; + + mcu_mcan1_pins: mcu-mcan1-pins { + pinctrl-single,pins = < + /* (D4) MCU_MCAN1_RX */ + AM62X_MCU_IOPAD(0x040, PIN_INPUT, 0) + /* (E5) MCU_MCAN1_TX */ + AM62X_MCU_IOPAD(0x03c, PIN_OUTPUT, 0) + >; + }; + + mcu_uart0_pins: mcu-uart0-pins { + pinctrl-single,pins = < + /* (B5) MCU_UART0_RXD */ + AM62X_MCU_IOPAD(0x014, PIN_INPUT, 0) + /* (A5) MCU_UART0_TXD */ + AM62X_MCU_IOPAD(0x018, PIN_OUTPUT, 0) + /* (B6) MCU_UART0_RTS# */ + AM62X_MCU_IOPAD(0x020, PIN_OUTPUT, 0) + >; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am625-tqma62xx.dtsi b/arch/arm64/boot/dts/ti/k3-am625-tqma62xx.dtsi new file mode 100644 index 000000000000..72288678cd01 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-tqma62xx.dtsi @@ -0,0 +1,360 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (c) 2023-2026 TQ-Systems GmbH , D-82229 Seefeld, Germany. + * Author: Nora Schiffer + */ + +#include "k3-am625.dtsi" + +/ { + aliases { + i2c0 = &main_i2c0; + mmc0 = &sdhci0; + spi0 = &ospi0; + }; + + memory@80000000 { + device_type = "memory"; + /* 1G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x40000000>; + bootph-pre-ram; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops@9c700000 { + compatible = "ramoops"; + reg = <0x00 0x9c700000 0x00 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x00>; + pmsg-size = <0x8000>; + }; + + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x8000000>; + linux,cma-default; + }; + + rtos_ipc_memory_region: memory@9c800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c800000 0x00 0x00300000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: memory@9da00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9da00000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: memory@9db00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9db00000 0x00 0xc00000>; + no-map; + }; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + alignment = <0x1000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_sd: regulator-sd { + /* Output of TPS6521902RSM */ + compatible = "regulator-gpio"; + regulator-name = "V_VDDSHV5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <®_ldo1>; + states = <1800000 0x0>, + <3300000 0x1>; + /* Controlling GPIO set by base board */ + status = "disabled"; + }; +}; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins>; + clock-frequency = <400000>; + bootph-pre-ram; + status = "okay"; + + tps65219: pmic@30 { + compatible = "ti,tps65219"; + reg = <0x30>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins>; + interrupt-parent = <&gic500>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + buck1-supply = <®_3v3>; + buck2-supply = <®_3v3>; + buck3-supply = <®_3v3>; + ldo1-supply = <®_3v3>; + ldo2-supply = <®_buck2>; + ldo3-supply = <®_3v3>; + ldo4-supply = <®_3v3>; + system-power-controller; + ti,power-button; + + regulators { + reg_buck1: buck1 { + regulator-name = "V_VDD_CORE"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_buck2: buck2 { + regulator-name = "V_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_buck3: buck3 { + regulator-name = "V_1V1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_ldo1: ldo1 { + /* Actual voltage of LDO1 is controlled by GPIO, see reg_sd */ + regulator-name = "V_VDDSHV5_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-allow-bypass; + regulator-boot-on; + regulator-always-on; + }; + + reg_ldo2: ldo2 { + regulator-name = "V_0V85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_ldo3: ldo3 { + regulator-name = "V_1V8A"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_ldo4: ldo4 { + /* Unused */ + regulator-name = "V_VLDO4"; + regulator-boot-on; + }; + }; + }; + + tmp1075: temperature-sensor@4a { + compatible = "ti,tmp1075"; + reg = <0x4a>; + vs-supply = <®_buck2>; + }; + + eeprom0: eeprom@50 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x50>; + vcc-supply = <®_buck2>; + pagesize = <16>; + read-only; + bootph-pre-ram; + }; + + pcf85063: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + quartz-load-femtofarads = <12500>; + }; + + eeprom1: eeprom@54 { + compatible = "st,24c64", "atmel,24c64"; + reg = <0x54>; + vcc-supply = <®_buck2>; + pagesize = <32>; + }; +}; + +&a53_opp_table { + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + opp-suspend; + clock-latency-ns = <6000000>; + /* + * Enabled by bootloader if supported. The PMIC configuration + * will be adjusted accordingly, as a higher core voltage is + * required for 1400MHz operation. + */ + status = "disabled"; + }; +}; + +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins>; + bootph-all; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + vcc-supply = <®_buck2>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <84000000>; + bootph-all; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Filled by bootloader */ + }; + }; +}; + +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins>; + non-removable; + disable-wp; + no-sd; + no-sdio; + bootph-all; + ti,driver-strength-ohm = <50>; + status = "okay"; +}; + +&wkup_rtc0 { + /* + * Erratum i2327: We can't guarantee that the TQMa62xx will boot fast + * enough for U-Boot to apply the workaround within one second after + * power-on. Keep the RTC disabled to avoid RTC interrupt issues. + * + * The external RTC of the TQMa62xx should be used instead. + * + * If needed, the RTC can be enabled in a baseboard DTS, as long as + * boot is fast enough on all relevant boot media. + */ + status = "disabled"; +}; + +&main_pmx0 { + main_i2c0_pins: main-i2c0-pins { + pinctrl-single,pins = < + /* (B16) I2C0_SCL */ + AM62X_IOPAD(0x1e0, PIN_INPUT, 0) + /* (A16) I2C0_SDA */ + AM62X_IOPAD(0x1e4, PIN_INPUT, 0) + >; + bootph-pre-ram; + }; + + main_mmc0_pins: main-mmc0-pins { + pinctrl-single,pins = < + /* (Y3) MMC0_CMD */ + AM62X_IOPAD(0x220, PIN_INPUT, 0) + /* (AB1) MMC0_CLK */ + AM62X_IOPAD(0x218, PIN_INPUT, 0) + /* (AA2) MMC0_DAT0 */ + AM62X_IOPAD(0x214, PIN_INPUT, 0) + /* (AA1) MMC0_DAT1 */ + AM62X_IOPAD(0x210, PIN_INPUT, 0) + /* (AA3) MMC0_DAT2 */ + AM62X_IOPAD(0x20c, PIN_INPUT, 0) + /* (Y4) MMC0_DAT3 */ + AM62X_IOPAD(0x208, PIN_INPUT, 0) + /* (AB2) MMC0_DAT4 */ + AM62X_IOPAD(0x204, PIN_INPUT, 0) + /* (AC1) MMC0_DAT5 */ + AM62X_IOPAD(0x200, PIN_INPUT, 0) + /* (AD2) MMC0_DAT6 */ + AM62X_IOPAD(0x1fc, PIN_INPUT, 0) + /* (AC2) MMC0_DAT7 */ + AM62X_IOPAD(0x1f8, PIN_INPUT, 0) + >; + bootph-all; + }; + + ospi0_pins: ospi0-pins { + pinctrl-single,pins = < + /* (H24) OSPI0_CLK */ + AM62X_IOPAD(0x000, PIN_OUTPUT, 0) + /* (F23) OSPI0_CSn0 */ + AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) + /* (E25) OSPI0_D0 */ + AM62X_IOPAD(0x00c, PIN_INPUT, 0) + /* (G24) OSPI0_D1 */ + AM62X_IOPAD(0x010, PIN_INPUT, 0) + /* (F25) OSPI0_D2 */ + AM62X_IOPAD(0x014, PIN_INPUT, 0) + /* (F24) OSPI0_D3 */ + AM62X_IOPAD(0x018, PIN_INPUT, 0) + /* (J23) OSPI0_D4 */ + AM62X_IOPAD(0x01c, PIN_INPUT, 0) + /* (J25) OSPI0_D5 */ + AM62X_IOPAD(0x020, PIN_INPUT, 0) + /* (H25) OSPI0_D6 */ + AM62X_IOPAD(0x024, PIN_INPUT, 0) + /* (J22) OSPI0_D7 */ + AM62X_IOPAD(0x028, PIN_INPUT, 0) + /* (J24) OSPI0_DQS */ + AM62X_IOPAD(0x008, PIN_INPUT, 0) + /* (G25) OSPI0_LBCLKO */ + AM62X_IOPAD(0x004, PIN_INPUT, 0) + >; + }; + + pmic_irq_pins: pmic-irq-pins { + pinctrl-single,pins = < + /* (D16) EXTINTn */ + AM62X_IOPAD(0x01f4, PIN_INPUT_PULLUP, 0) + >; + }; +}; + +#include "k3-am62-ti-ipc-firmware.dtsi" From 48c7771b3c792b153872a2eff67e4cbcb77e4054 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 5 May 2026 11:22:50 +0100 Subject: [PATCH 118/665] riscv: dts: microchip: fix pic64gx gpio interrupt-cells As the pic64gx devicetree files got added in parallel to the GPIO interrupt-cells being fixed for PolarFire SoC, they didn't get changed to the correct values. Fix them now. Fixes: 7219d20f9f421 ("riscv: dts: microchip: add pic64gx and its curiosity kit") Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/pic64gx.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/pic64gx.dtsi b/arch/riscv/boot/dts/microchip/pic64gx.dtsi index 5cf3e3de0e06..5addfd435711 100644 --- a/arch/riscv/boot/dts/microchip/pic64gx.dtsi +++ b/arch/riscv/boot/dts/microchip/pic64gx.dtsi @@ -494,7 +494,7 @@ gpio0: gpio@20120000 { reg = <0x0 0x20120000 0x0 0x1000>; interrupt-parent = <&irqmux>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>, <10>, <11>, @@ -511,7 +511,7 @@ gpio1: gpio@20121000 { reg = <0x0 0x20121000 0x0 0x1000>; interrupt-parent = <&irqmux>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; interrupts = <32>, <33>, <34>, <35>, <36>, <37>, <38>, <39>, <40>, <41>, <42>, <43>, @@ -530,7 +530,7 @@ gpio2: gpio@20122000 { reg = <0x0 0x20122000 0x0 0x1000>; interrupt-parent = <&irqmux>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; interrupts = <64>, <65>, <66>, <67>, <68>, <69>, <70>, <71>, <72>, <73>, <74>, <75>, From 4da515eca1b8de56c9e8a17866626f99d9bccbc7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= Date: Thu, 9 Apr 2026 23:17:24 +0200 Subject: [PATCH 119/665] arm64: dts: marvell: samsung-coreprimevelte: Increase touchscreen voltage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The old 1.9V setting was found to be insufficient in certain environments (in my case cold ones), causing the touchscreen to register ghost touches and mostly ignore actual touches. Increase the voltage to 2.5V to correct the issue. Fixes: ec958b5b18c8 ("arm64: dts: samsung,coreprimevelte: add touchscreen") Acked-by: Karel Balej Signed-off-by: Duje Mihanović --- .../boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts b/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts index b2ce5edd9c6a..bb0a99399624 100644 --- a/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts +++ b/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts @@ -460,7 +460,7 @@ pmic@30 { regulators { ldo2: ldo2 { - regulator-min-microvolt = <1900000>; + regulator-min-microvolt = <2500000>; regulator-max-microvolt = <3100000>; }; From cfb4346423eb5dab498546d617a8c444b878bff3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= Date: Thu, 9 Apr 2026 23:17:25 +0200 Subject: [PATCH 120/665] arm64: dts: marvell: samsung,coreprimevelte: Use memory-region for framebuffer MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since the framebuffer resides in system RAM, use the memory-region property preferred in that case over reg. Also, testing showed that reusing most of the region (excluding where the actual framebuffer resides) is perfectly safe, so do that and save ~22.5 MiB of RAM in the process. Signed-off-by: Duje Mihanović --- .../dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts b/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts index bb0a99399624..f71bb856f1e7 100644 --- a/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts +++ b/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts @@ -23,7 +23,7 @@ chosen { fb0: framebuffer@17177000 { compatible = "simple-framebuffer"; - reg = <0 0x17177000 0 (480 * 800 * 4)>; + memory-region = <&fb_mem>; power-domains = <&apmu PXA1908_POWER_DOMAIN_DSI>; width = <480>; height = <800>; @@ -48,8 +48,9 @@ secure-region@0 { reg = <0 0 0 0x1000000>; }; - framebuffer@17000000 { - reg = <0 0x17000000 0 0x1800000>; + /* The "active buffer" is at 0x17000000 + (size of one buffer). */ + fb_mem: framebuffer@17177000 { + reg = <0 0x17177000 0 (480 * 800 * 4)>; no-map; }; }; From e93abeef9267a9c3e063e594571d46b3d9461efc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= Date: Thu, 9 Apr 2026 23:17:26 +0200 Subject: [PATCH 121/665] arm64: dts: marvell: pxa1908: Add PSCI function IDs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add function IDs for CPU_ON and CPU_OFF from vendor kernel source. This is done for completeness and to allow PSCI to work on the occasion that the DT is used with an ancient kernel. Signed-off-by: Duje Mihanović --- arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi b/arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi index 5778bfdb8567..91022b62a39b 100644 --- a/arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi +++ b/arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi @@ -55,8 +55,11 @@ pmu { }; psci { - compatible = "arm,psci-0.2"; + compatible = "arm,psci-0.2", "arm,psci"; method = "smc"; + + cpu_off = <0x85000001>; + cpu_on = <0x85000002>; }; reserved-memory { From 52c47f734f934fdd83659e1a7b096597cca14522 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= Date: Thu, 9 Apr 2026 23:17:27 +0200 Subject: [PATCH 122/665] arm64: dts: marvell: samsung-coreprimevelte: Add missing SDIO properties MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to the vendor device tree, the WiFi+BT card must not be powered off during suspend and is capable of waking up the board. Add the respective properties to the SDIO node to reflect this. Signed-off-by: Duje Mihanović --- .../boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts b/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts index f71bb856f1e7..6ec899c427e1 100644 --- a/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts +++ b/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts @@ -524,6 +524,8 @@ &sdh1 { pinctrl-1 = <&sdh1_fast_pins_0 &sdh1_fast_pins_1 &sdh1_pins_2>; bus-width = <4>; non-removable; + keep-power-in-suspend; + wakeup-source; }; &pwm3 { From 5b80089b47f8307c2265357e4d3ae90cb40ac0d6 Mon Sep 17 00:00:00 2001 From: Adrian Ng Ho Yin Date: Tue, 5 May 2026 13:15:16 +0800 Subject: [PATCH 123/665] arm64: dts: socfpga: agilex5: set alias for i3c controllers Agilex5 SoCFPGA variants and derivatives have 2 i3c controllers, a main master and a secondary master. Setting the alias for both i3c controllers to prevent bus id contention when both controllers are enabled which results in driver probe failures. Signed-off-by: Adrian Ng Ho Yin Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts | 2 ++ arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts | 2 ++ arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts | 2 ++ arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts | 2 ++ 4 files changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts index 262bb3e8e5c7..dae0db9f8819 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts @@ -13,6 +13,8 @@ aliases { ethernet0 = &gmac0; ethernet1 = &gmac1; ethernet2 = &gmac2; + i3c0 = &i3c0; + i3c1 = &i3c1; }; chosen { diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts index f71e1280c778..86137380df04 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts @@ -11,6 +11,8 @@ / { aliases { serial0 = &uart0; ethernet2 = &gmac2; + i3c0 = &i3c0; + i3c1 = &i3c1; }; chosen { diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts index 1831402d8808..e728cedb4cbd 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts @@ -11,6 +11,8 @@ / { aliases { serial0 = &uart0; ethernet2 = &gmac2; + i3c0 = &i3c0; + i3c1 = &i3c1; }; chosen { diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts index ec4541d44c9b..21faa47681fa 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts @@ -11,6 +11,8 @@ / { aliases { serial0 = &uart0; ethernet0 = &gmac0; + i3c0 = &i3c0; + i3c1 = &i3c1; }; chosen { From 49a2a555a14920a1c9e3175c6ebb7d65eb06cf34 Mon Sep 17 00:00:00 2001 From: Adrian Ng Ho Yin Date: Tue, 5 May 2026 13:15:17 +0800 Subject: [PATCH 124/665] arm64: dts: socfpga: agilex3: set alias for i3c controller Agilex3 SoCFPGA have 2 i3c controllers, a main master and a secondary master. Setting the alias for both i3c controllers to prevent bus id contention when both controllers are enabled which results in driver probe failures. Signed-off-by: Adrian Ng Ho Yin Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts index 14b299f19f3a..25e17df0cbdb 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts @@ -12,6 +12,8 @@ / { aliases { serial0 = &uart0; ethernet2 = &gmac2; + i3c0 = &i3c0; + i3c1 = &i3c1; }; chosen { From 78efc82d617fe7164e142c399cc20f7270ceeb82 Mon Sep 17 00:00:00 2001 From: Joy Zou Date: Thu, 26 Mar 2026 15:51:37 +0800 Subject: [PATCH 125/665] dt-bindings: arm: fsl: add i.MX91 9x9 QSB board Add compatible string for i.MX91 9x9 Quick Start Board. Signed-off-by: Joy Zou Reviewed-by: Daniel Baluta Acked-by: Conor Dooley Signed-off-by: Frank Li --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 7ce4176d19f5..477d78ae729a 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1458,6 +1458,7 @@ properties: - description: i.MX91 based Boards items: - enum: + - fsl,imx91-9x9-qsb # i.MX91 9x9 QSB Board - fsl,imx91-11x11-evk # i.MX91 11x11 EVK Board - fsl,imx91-11x11-frdm # FRDM i.MX91 Development Board - fsl,imx91-11x11-frdm-s # FRDM i.MX91S Development Board From 644f6a8f1fb368dbf017688c47b2f913c8d2d35b Mon Sep 17 00:00:00 2001 From: Joy Zou Date: Thu, 26 Mar 2026 15:51:38 +0800 Subject: [PATCH 126/665] arm64: dts: imx91-11x11-evk: remove unused property clock-frequency from mdio node The clock-frequency property is not implemented. Remove it to clean up the device tree. Signed-off-by: Joy Zou Reviewed-by: Andrew Lunn Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts index c083b97476a5..de524f1921de 100644 --- a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts @@ -195,7 +195,6 @@ mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; - clock-frequency = <5000000>; ethphy1: ethernet-phy@1 { reg = <1>; From dd4d83f8a6dfce2b21a4b81c837ad3fe941c9996 Mon Sep 17 00:00:00 2001 From: Joy Zou Date: Thu, 26 Mar 2026 15:51:39 +0800 Subject: [PATCH 127/665] arm64: dts: imx93-11x11-evk: remove unused property clock-frequency from mdio node The clock-frequency property is not implemented. Remove it to clean up the device tree. Signed-off-by: Joy Zou Reviewed-by: Andrew Lunn Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx93-11x11-evk-common.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk-common.dtsi b/arch/arm64/boot/dts/freescale/imx93-11x11-evk-common.dtsi index 7d3fc4ad7b8b..f48e7947cf64 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk-common.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk-common.dtsi @@ -187,7 +187,6 @@ mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; - clock-frequency = <5000000>; ethphy1: ethernet-phy@1 { reg = <1>; From 88b82b5d2c066271a0e8ecb4ab7e38d56b19f059 Mon Sep 17 00:00:00 2001 From: Joy Zou Date: Thu, 26 Mar 2026 15:51:40 +0800 Subject: [PATCH 128/665] arm64: dts: imx93-9x9-qsb: remove unused property clock-frequency from mdio node The clock-frequency property is not implemented. Remove it to clean up the device tree. Signed-off-by: Joy Zou Reviewed-by: Andrew Lunn Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts index 7bcebd702106..01c11c517986 100644 --- a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts +++ b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts @@ -228,7 +228,6 @@ mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; - clock-frequency = <5000000>; ethphy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; From c64e79096d225454a56830ec1fb5e5a464939073 Mon Sep 17 00:00:00 2001 From: Joy Zou Date: Thu, 26 Mar 2026 15:51:41 +0800 Subject: [PATCH 129/665] arm64: dts: freescale: add i.MX91 9x9 QSB basic support Add i.MX91 9x9 Quick Start Board support. - Enable ADC1. - Enable lpuart1. - Enable network eqos. - Enable I2C bus and children nodes under I2C bus. - Enable USB and related nodes. - Enable uSDHC1 and uSDHC2. - Enable Watchdog3. The board description can refer to the following link: https://www.nxp.com/design/design-center/development-boards-and-designs/IMX91QSB Signed-off-by: Joy Zou Reviewed-by: Daniel Baluta Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx91-9x9-qsb.dts | 425 ++++++++++++++++++ 2 files changed, 426 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index cbd6c299ff81..ec2d2505d804 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -438,6 +438,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqps-mb-smarc-2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-9x9-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx91-9x9-qsb.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-frdm.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-frdm-s.dtb diff --git a/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts b/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts new file mode 100644 index 000000000000..1239bbf579da --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts @@ -0,0 +1,425 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 NXP + */ + +/dts-v1/; + +#include +#include "imx91.dtsi" + +/ { + compatible = "fsl,imx91-9x9-qsb", "fsl,imx91"; + model = "NXP i.MX91 9x9 Quick Start Board"; + + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + rtc0 = &bbnsm_rtc; + serial0 = &lpuart1; + }; + + chosen { + stdout-path = &lpuart1; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + off-on-delay-us = <12000>; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x10000000>; + linux,cma-default; + }; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&eqos { + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_eqos>; + pinctrl-names = "default"; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + realtek,clkout-disable; + }; + }; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e + MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe + MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e + MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe + MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX91_PAD_UART1_RXD__LPUART1_RX 0x31e + MX91_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582 + MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382 + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382 + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382 + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382 + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382 + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382 + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382 + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382 + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382 + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e + MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582 + MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382 + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382 + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382 + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382 + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382 + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; +}; + +&lpi2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-names = "default"; + status = "okay"; + + p3t1085: temperature-sensor@48 { + compatible = "nxp,p3t1085"; + reg = <0x48>; + }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + + typec1_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <15000000>; + power-role = "dual"; + self-powered; + sink-pdos = ; + source-pdos = ; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + }; + }; + + pcf2131: rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; + interrupt-parent = <&pcal6524>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&lpi2c2 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-names = "default"; + status = "okay"; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + pinctrl-0 = <&pinctrl_pcal6524>; + pinctrl-names = "default"; + }; + + pmic@32 { + compatible = "nxp,pf9453"; + reg = <0x32>; + interrupt-parent = <&pcal6524>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1140000>; + regulator-min-microvolt = <1060000>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <610000>; + regulator-ramp-delay = <12500>; + }; + + buck3: BUCK3 { + regulator-name = "BUCK3"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3450000>; + regulator-min-microvolt = <1650000>; + }; + + buck4: BUCK4 { + regulator-name = "BUCK4"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3450000>; + regulator-min-microvolt = <1650000>; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1650000>; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1890000>; + regulator-min-microvolt = <760000>; + }; + + ldo_snvs: LDO-SNVS { + regulator-name = "LDO-SNVS"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1950000>; + regulator-min-microvolt = <1650000>; + }; + }; + }; +}; + +&lpuart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg1 { + adp-disable; + disable-over-current; + dr_mode = "otg"; + hnp-disable; + srp-disable; + usb-role-switch; + samsung,picophy-dc-vol-level-adjust = <7>; + samsung,picophy-pre-emp-curr-control = <3>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usdhc1 { + bus-width = <8>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + fsl,tuning-step = <1>; + status = "okay"; +}; + +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + vmmc-supply = <®_usdhc2_vmmc>; + fsl,tuning-step = <1>; + status = "okay"; +}; + +&wdog3 { + fsl,ext-reset-output; + status = "okay"; +}; From 98461edf564a35ee00a97a64f5463eaece586546 Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Tue, 28 Apr 2026 13:06:54 -0700 Subject: [PATCH 130/665] ARM: dts: rockchip: Add #{address,size}-cells to Chromium-based /firmware Chromium/Depthcharge bootloaders may dynamically add a few device nodes to a system's DTB under a /firmware node. A typical DT looks something like the following: / { firmware { ranges; coreboot { compatible = "coreboot"; reg = <...>; ...; }; }; }; Notably, the /firmware node has an empty 'ranges', but does not have address/size-cells. Commit 6e5773d52f4a ("of/address: Fix WARN when attempting translating non-translatable addresses") started requiring #address-cells for a device's parent if we want to use the reg resource in a device node. This leads to errors like the following: [ 7.763870] coreboot_table firmware:coreboot: probe with driver coreboot_table failed with error -22 Add appropriate #{address,size}-cells to work around the problem. Note that Google has also patched the Depthcharge bootloader source to add {address,size}-cells [1], but bootloader updates are typically delivered only via Google OS updates. Not all users install Google software updates, and even if they do, Google may not produce updated binaries for all/older devices. [1] https://lore.kernel.org/all/20241209092809.GA3246424@google.com/ https://crrev.com/c/6051580 ("coreboot: Insert #address-cells and #size-cells for firmware node") Closes: https://lore.kernel.org/all/aeKlYzTiL0OB1y3g@google.com/ Fixes: 6e5773d52f4a ("of/address: Fix WARN when attempting translating non-translatable addresses") Signed-off-by: Brian Norris Reviewed-by: Douglas Anderson [On RK288-based Chromebooks there is no real other way than to load the DTB together with its kernel when running a mainline kernel and as the whole line is EOL, there also won't be any updates to the bootloader that could fix that issue there.] Link: https://patch.msgid.link/20260428200712.2660635-3-briannorris@chromium.org Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi index 2d6cf08d00f9..ca8e8e735078 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi @@ -18,6 +18,11 @@ chosen { stdout-path = "serial2:115200n8"; }; + firmware { + #address-cells = <1>; + #size-cells = <1>; + }; + /* * The default coreboot on veyron devices ignores memory@0 nodes * and would instead create another memory node. From 0b74f1a037672980c477bbe6b3848fb5341eb4f1 Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Tue, 28 Apr 2026 13:06:53 -0700 Subject: [PATCH 131/665] arm64: dts: rockchip: Add #{address,size}-cells to Chromium-based /firmware Chromium/Depthcharge bootloaders may dynamically add a few device nodes to a system's DTB under a /firmware node. A typical DT looks something like the following: ## From a RK3399 Gru/Kevin Chromebook: # find /sys/firmware/devicetree/base/firmware /sys/firmware/devicetree/base/firmware /sys/firmware/devicetree/base/firmware/coreboot /sys/firmware/devicetree/base/firmware/coreboot/ram-code /sys/firmware/devicetree/base/firmware/coreboot/compatible /sys/firmware/devicetree/base/firmware/coreboot/board-id /sys/firmware/devicetree/base/firmware/coreboot/reg /sys/firmware/devicetree/base/firmware/coreboot/name /sys/firmware/devicetree/base/firmware/chromeos /sys/firmware/devicetree/base/firmware/chromeos/readonly-firmware-version /sys/firmware/devicetree/base/firmware/chromeos/active-ec-firmware /sys/firmware/devicetree/base/firmware/chromeos/firmware-version /sys/firmware/devicetree/base/firmware/chromeos/nonvolatile-context-storage /sys/firmware/devicetree/base/firmware/chromeos/vboot-shared-data /sys/firmware/devicetree/base/firmware/chromeos/nonvolatile-context-size /sys/firmware/devicetree/base/firmware/chromeos/nonvolatile-context-offset /sys/firmware/devicetree/base/firmware/chromeos/hardware-id /sys/firmware/devicetree/base/firmware/chromeos/compatible /sys/firmware/devicetree/base/firmware/chromeos/firmware-type /sys/firmware/devicetree/base/firmware/chromeos/fmap-offset /sys/firmware/devicetree/base/firmware/chromeos/name /sys/firmware/devicetree/base/firmware/ranges /sys/firmware/devicetree/base/firmware/name The /firmware node has an empty 'ranges', but does not have address/size-cells. Commit 6e5773d52f4a ("of/address: Fix WARN when attempting translating non-translatable addresses") started requiring #address-cells for a device's parent if we want to use the reg resource in a device node. This leads to errors like the following: [ 7.763870] coreboot_table firmware:coreboot: probe with driver coreboot_table failed with error -22 Add appropriate #{address,size}-cells to work around the problem. Note that Google has also patched the Depthcharge bootloader source to add {address,size}-cells [1], but bootloader updates are typically delivered only via Google OS updates. Not all users install Google software updates, and even if they do, Google may not produce updated binaries for all/older devices. [1] https://lore.kernel.org/all/20241209092809.GA3246424@google.com/ https://crrev.com/c/6051580 ("coreboot: Insert #address-cells and #size-cells for firmware node") Closes: https://lore.kernel.org/all/aeKlYzTiL0OB1y3g@google.com/ Fixes: 6e5773d52f4a ("of/address: Fix WARN when attempting translating non-translatable addresses") Signed-off-by: Brian Norris Reviewed-by: Douglas Anderson Reviewed-by: Chen-Yu Tsai [On RK3399-based Chromebooks there is no real other way than to load the DTB together with its kernel when running a mainline kernel and as the whole line is EOL, there also won't be any updates to the bootloader that could fix that issue there.] Link: https://patch.msgid.link/20260428200712.2660635-2-briannorris@chromium.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi index 7eca1da78cff..2f9e39671efc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -18,6 +18,11 @@ chosen { stdout-path = "serial2:115200n8"; }; + firmware { + #address-cells = <2>; + #size-cells = <2>; + }; + /* * Power Tree * From e477eff6303b3c5cb9bdbe5f6568ce1ef74b5f66 Mon Sep 17 00:00:00 2001 From: Gray Huang Date: Wed, 29 Apr 2026 14:37:07 +0800 Subject: [PATCH 132/665] arm64: dts: rockchip: Add HYM8563 RTC for Khadas Edge 2L The Khadas Edge 2L uses an on-board HYM8563 RTC connected to I2C2. Enable it and expose its 32.768kHz clock output so later board-level patches can reference it as the LPO clock source for the AP6275P wireless module. Mark the RTC as a wakeup source as well. Signed-off-by: Gray Huang Link: https://patch.msgid.link/20260429063712.2150938-3-gray.huang@wesion.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3576-khadas-edge-2l.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts b/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts index c39c7f90b6fb..cf846b24a24a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts @@ -470,6 +470,18 @@ regulator-state-mem { }; }; +&i2c2 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + wakeup-source; + }; +}; + &sdhci { bus-width = <8>; no-sdio; From 76cf96cd9e21aa6c3846d1449aef991a32d3e13b Mon Sep 17 00:00:00 2001 From: Gray Huang Date: Wed, 29 Apr 2026 14:37:08 +0800 Subject: [PATCH 133/665] arm64: dts: rockchip: Add AP6275P wireless support for Khadas Edge 2L The Khadas Edge 2L uses an Ampak AP6275P (BCM43752) PCIe Wi-Fi 6 module. Enable combphy0 and pcie0, add the Wi-Fi regulator and reset pinctrl, and describe the PCIe Wi-Fi function so it can consume the 32.768kHz LPO clock provided by the HYM8563 RTC. Signed-off-by: Gray Huang Link: https://patch.msgid.link/20260429063712.2150938-4-gray.huang@wesion.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3576-khadas-edge-2l.dts | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts b/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts index cf846b24a24a..e7fe22eb31a3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts @@ -58,6 +58,24 @@ vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 { regulator-max-microvolt = <2000000>; vin-supply = <&vcc_sys>; }; + + vcc_wifi_reg_on: regulator-wifi-reg-on { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&wifi_reg_on>; + pinctrl-names = "default"; + regulator-name = "wifi_reg_on"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_s3>; + }; +}; + +&combphy0_ps { + status = "okay"; }; &cpu_l0 { @@ -482,6 +500,48 @@ hym8563: rtc@51 { }; }; +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_rst>; + reset-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_s3>; + status = "okay"; + + pcie@0,0 { + reg = <0x0 0 0 0 0>; + bus-range = <0x0 0xf>; + device_type = "pci"; + ranges; + #address-cells = <3>; + #size-cells = <2>; + + wifi: wifi@0,0 { + compatible = "pci14e4,449d"; + reg = <0x10000 0 0 0 0>; + clocks = <&hym8563>; + clock-names = "lpo"; + }; + }; +}; + +&pinctrl { + pcie0 { + pcie0_rst: pcie0-rst { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_reg_on: wifi-reg-on { + rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + wifi_wake_host: wifi-wake-host { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + &sdhci { bus-width = <8>; no-sdio; From 2cd97880fbc434b49a211784561586f0397499b7 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 28 Apr 2026 00:57:19 +0300 Subject: [PATCH 134/665] arm64: dts: rockchip: Add frl-enable-gpios to rk3576 boards The following RK3576 boards expose a GPIO pin to control the voltage bias on the HDMI data lines: - rk3576-100ask-dshanpi-a1 - rk3576-armsom-sige5 - rk3576-evb1-v10 - rk3576-evb2-v10 - rk3576-nanopi-m5 - rk3576-roc-pc - rk3576-rock-4d The pin must be asserted when operating in HDMI 2.1 FRL mode and deasserted for HDMI 1.4/2.0 TMDS mode. Wire up the hdmi node to its dedicated GPIO via frl-enable-gpios to allow adjusting the bias when transitioning between TMDS and FRL modes. Signed-off-by: Cristian Ciocaltea Link: https://patch.msgid.link/20260428-dts-rk-frl-enable-gpios-v2-1-924df9db884a@collabora.com Signed-off-by: Heiko Stuebner --- .../arm64/boot/dts/rockchip/rk3576-100ask-dshanpi-a1.dts | 9 +++++++++ arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts | 9 +++++++++ arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts | 9 +++++++++ arch/arm64/boot/dts/rockchip/rk3576-evb2-v10.dts | 9 +++++++++ arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts | 9 +++++++++ arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts | 9 +++++++++ arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts | 9 +++++++++ 7 files changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-100ask-dshanpi-a1.dts b/arch/arm64/boot/dts/rockchip/rk3576-100ask-dshanpi-a1.dts index b19f9b6be6bf..a9e3beb3ee5e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-100ask-dshanpi-a1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-100ask-dshanpi-a1.dts @@ -278,6 +278,9 @@ &gpu { }; &hdmi { + frl-enable-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda &hdmi_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -738,6 +741,12 @@ hp_det: hp-det { }; }; + hdmi { + hdmi_tx_on_h: hdmi-tx-on-h { + rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pcie { pcie_reset: pcie-reset { rockchip,pins = <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts index 1c100ffd1518..c3e8966c09c4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts @@ -304,6 +304,9 @@ &gpu { }; &hdmi { + frl-enable-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda &hdmi_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -819,6 +822,12 @@ hp_det_l: hp-det-l { }; }; + hdmi { + hdmi_tx_on_h: hdmi-tx-on-h { + rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hym8563 { hym8563_int: hym8563-int { rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts index fb0dd1bc5148..4c82980a9f63 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts @@ -370,6 +370,9 @@ &gpu { }; &hdmi { + frl-enable-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda &hdmi_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -895,6 +898,12 @@ host_wake_bt: host-wake-bt { }; }; + hdmi { + hdmi_tx_on_h: hdmi-tx-on-h { + rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hym8563 { rtc_int: rtc-int { rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb2-v10.dts b/arch/arm64/boot/dts/rockchip/rk3576-evb2-v10.dts index 98d5d00d63b5..dfc756d5ec5e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-evb2-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-evb2-v10.dts @@ -375,6 +375,9 @@ &gpu { }; &hdmi { + frl-enable-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda &hdmi_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -832,6 +835,12 @@ image_pwren: image-pwren { }; }; + hdmi { + hdmi_tx_on_h: hdmi-tx-on-h { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hym8563 { rtc_int: rtc-int { rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts index 7406a4adf810..227fe6f3ec7c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts @@ -327,6 +327,9 @@ &gpu { }; &hdmi { + frl-enable-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda &hdmi_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -813,6 +816,12 @@ gmac1_rst: gmac1-rst { }; }; + hdmi { + hdmi_tx_on_h: hdmi-tx-on-h { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hym8563 { hym8563_int: hym8563-int { rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts index d0ab1d1e0e11..54de3a50571f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts @@ -283,6 +283,9 @@ ð0m0_rgmii_bus }; &hdmi { + frl-enable-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda &hdmi_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -720,6 +723,12 @@ &sdmmc { }; &pinctrl { + hdmi { + hdmi_tx_on_h: hdmi-tx-on-h { + rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hym8563 { rtc_int_l: rtc-int-l { rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts index 899a84b1fbf9..cc054c837317 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts @@ -289,6 +289,9 @@ &gpu { }; &hdmi { + frl-enable-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda &hdmi_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -720,6 +723,12 @@ &pcie0 { }; &pinctrl { + hdmi { + hdmi_tx_on_h: hdmi-tx-on-h { + rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hym8563 { hym8563_int: hym8563-int { rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; From 12eb09ee67cba1e3cc0c75149d0a04a5187ca575 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 28 Apr 2026 00:57:20 +0300 Subject: [PATCH 135/665] arm64: dts: rockchip: Add frl-enable-gpios to rk3576-luckfox-core3576 The board exposes the GPIO4_C6 pin to control the voltage bias on the HDMI data lines. It must be asserted when operating in HDMI 2.1 FRL mode and deasserted for HDMI 1.4/2.0 TMDS mode. Wire up the hdmi node to its dedicated GPIO via frl-enable-gpios to allow adjusting the bias when transitioning between TMDS and FRL modes. Additionally, remove the now unnecessary workaround of using vcc_5v0_hdmi as hdmi-pwr-supply solely to drive the GPIO into its default state. Also rename the hdmi_con_en pinctrl to hdmi_tx_on_h to match the schematic naming. Signed-off-by: Cristian Ciocaltea Link: https://patch.msgid.link/20260428-dts-rk-frl-enable-gpios-v2-2-924df9db884a@collabora.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3576-luckfox-core3576.dtsi | 22 ++++--------------- 1 file changed, 4 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-luckfox-core3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576-luckfox-core3576.dtsi index 749f0a54b478..4fc8496828f8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-luckfox-core3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576-luckfox-core3576.dtsi @@ -26,7 +26,6 @@ chosen { hdmi-con { compatible = "hdmi-connector"; - hdmi-pwr-supply = <&vcc_5v0_hdmi>; type = "a"; port { @@ -138,22 +137,6 @@ regulator-state-mem { }; }; - vcc_5v0_hdmi: regulator-vcc-5v0-hdmi { - compatible = "regulator-fixed"; - enable-active-high; - gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_con_en>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-name = "vcc_5v0_hdmi"; - vin-supply = <&vcc_5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - vcc_5v0_host: regulator-vcc-5v0-host { compatible = "regulator-fixed"; enable-active-high; @@ -231,6 +214,9 @@ &gpu { }; &hdmi { + frl-enable-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda &hdmi_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -655,7 +641,7 @@ &pcie0 { &pinctrl { hdmi { - hdmi_con_en: hdmi-con-en { + hdmi_tx_on_h: hdmi-tx-on-h { rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; }; }; From ba0d7cfb9870064296a8d4d57ff2c230166ada3c Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 28 Apr 2026 00:57:21 +0300 Subject: [PATCH 136/665] arm64: dts: rockchip: Add frl-enable-gpios to rk3576-nanopi-r76s The board exposes the GPIO4_C6 pin to control the voltage bias on the HDMI data lines. It must be asserted when operating in HDMI 2.1 FRL mode and deasserted for HDMI 1.4/2.0 TMDS mode. Wire up the hdmi node to its dedicated GPIO via frl-enable-gpios to allow adjusting the bias when transitioning between TMDS and FRL modes. Additionally, drop the now unnecessary workaround of using vcc5v_hdmi_tx as hdmi-pwr-supply solely to drive the GPIO into its default state. Signed-off-by: Cristian Ciocaltea Link: https://patch.msgid.link/20260428-dts-rk-frl-enable-gpios-v2-3-924df9db884a@collabora.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3576-nanopi-r76s.dts | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts index 7ec27b05ff10..0a5cd5f6fd33 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts @@ -70,7 +70,6 @@ led-2 { hdmi-con { compatible = "hdmi-connector"; - hdmi-pwr-supply = <&vcc5v_hdmi_tx>; type = "a"; port { @@ -109,18 +108,6 @@ vcc5v_dcin: regulator-vcc5v-dcin { regulator-name = "vcc5v_dcin"; }; - vcc5v_hdmi_tx: regulator-vcc5v-hdmi-tx { - compatible = "regulator-fixed"; - enable-active-high; - gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_tx_on_h>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-name = "vcc5v_hdmi_tx"; - vin-supply = <&vcc5v0_sys_s5>; - }; - vcc5v0_device_s0: regulator-vcc5v0-device-s0 { compatible = "regulator-fixed"; regulator-always-on; @@ -252,6 +239,9 @@ &gpu { }; &hdmi { + frl-enable-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda &hdmi_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; From 643d6733e58c663b66defea758bfb8d336047456 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 28 Apr 2026 00:57:22 +0300 Subject: [PATCH 137/665] arm64: dts: rockchip: Add frl-enable-gpios to rk3588 boards The following RK3588 boards expose one or two GPIO pins to control the voltage bias on the HDMI0 and/or HDMI1 data lines: - rk3588-armsom-sige7 - rk3588-armsom-w3 - rk3588-coolpi-cm5-evb - rk3588-coolpi-cm5-genbook - rk3588-evb1-v10 - rk3588-evb2-v10 - rk3588-firefly-itx-3588j - rk3588-friendlyelec-cm3588-nas - rk3588-h96-max-v58 - rk3588-jaguar - rk3588-mnt-reform2 - rk3588-nanopc-t6 - rk3588-orangepi-5-max - rk3588-orangepi-5-plus - rk3588-orangepi-5-ultra - rk3588-roc-rt - rk3588-rock-5-itx - rk3588-rock-5b-5bp-5t - rk3588-tiger The pins must be asserted when operating in HDMI 2.1 FRL mode and deasserted for HDMI 1.4/2.0 TMDS mode. Wire up the hdmi0 and/or hdmi1 nodes to their dedicated GPIO pin(s) via frl-enable-gpios to allow adjusting the bias when transitioning between TMDS and FRL modes. While at it, also ensure that pinctrl-names is present and ordered alphabetically within the hdmi nodes. Signed-off-by: Cristian Ciocaltea Link: https://patch.msgid.link/20260428-dts-rk-frl-enable-gpios-v2-4-924df9db884a@collabora.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588-armsom-sige7.dts | 10 ++++++++++ .../boot/dts/rockchip/rk3588-armsom-w3.dts | 18 ++++++++++++++++++ .../dts/rockchip/rk3588-coolpi-cm5-evb.dts | 18 +++++++++++++++++- .../dts/rockchip/rk3588-coolpi-cm5-genbook.dts | 11 ++++++++++- .../boot/dts/rockchip/rk3588-evb1-v10.dts | 18 ++++++++++++++++++ .../boot/dts/rockchip/rk3588-evb2-v10.dts | 10 ++++++++++ .../dts/rockchip/rk3588-firefly-itx-3588j.dts | 10 ++++++++++ .../rk3588-friendlyelec-cm3588-nas.dts | 18 ++++++++++++++++++ .../boot/dts/rockchip/rk3588-h96-max-v58.dts | 10 ++++++++++ arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts | 10 +++++++++- .../boot/dts/rockchip/rk3588-mnt-reform2.dts | 10 ++++++++++ .../boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 18 ++++++++++++++++++ .../dts/rockchip/rk3588-orangepi-5-max.dts | 18 ++++++++++++++++-- .../dts/rockchip/rk3588-orangepi-5-plus.dts | 18 ++++++++++++++++++ .../dts/rockchip/rk3588-orangepi-5-ultra.dts | 11 +++++++++-- arch/arm64/boot/dts/rockchip/rk3588-roc-rt.dts | 18 ++++++++++++++++++ .../boot/dts/rockchip/rk3588-rock-5-itx.dts | 10 +++++++++- .../dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi | 18 +++++++++++++++++- .../boot/dts/rockchip/rk3588-tiger-haikou.dts | 3 ++- arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi | 11 +++++++++-- 20 files changed, 256 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts index 39197ee19837..c4854c0f22e2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts @@ -177,6 +177,10 @@ &gpu { }; &hdmi0 { + frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -347,6 +351,12 @@ &pd_gpu { }; &pinctrl { + hdmi { + hdmi0_tx_on_h: hdmi0-tx-on-h { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hym8563 { hym8563_int: hym8563-int { rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-w3.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-w3.dts index 6ad2759ddcca..3bbafdd89ede 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-w3.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-w3.dts @@ -162,6 +162,10 @@ &combphy2_psu { }; &hdmi0 { + frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -182,6 +186,10 @@ &hdmi0_sound { }; &hdmi1 { + frl-enable-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd + &hdmim1_tx1_scl &hdmim1_tx1_sda &hdmi1_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -330,6 +338,16 @@ &pcie3x4 { }; &pinctrl { + hdmi { + hdmi0_tx_on_h: hdmi0-tx-on-h { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hdmi1_tx_on_h: hdmi1-tx-on-h { + rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hym8563 { hym8563_int: hym8563-int { rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts index 3d5c8b753208..66e3c20d7b4f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts @@ -125,6 +125,10 @@ vcc5v0_usb30_otg: regulator-vcc5v0-usb30-otg { }; &hdmi0 { + frl-enable-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -145,8 +149,10 @@ hdmi0_out_con: endpoint { }; &hdmi1 { + frl-enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd &hdmim1_tx1_scl &hdmim1_tx1_sda + &hdmi1_tx_on_h>; pinctrl-names = "default"; - pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd &hdmim1_tx1_scl &hdmim1_tx1_sda>; status = "okay"; }; @@ -211,6 +217,16 @@ &pcie3x4 { }; &pinctrl { + hdmi { + hdmi0_tx_on_h: hdmi0-tx-on-h { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hdmi1_tx_on_h: hdmi1-tx-on-h { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + lcd { lcdpwr_en: lcdpwr-en { rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts index 738637ecaf55..e05e6b2d5136 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts @@ -184,7 +184,10 @@ edp_out_panel: endpoint { /* HDMI CEC is not used */ &hdmi0 { - pinctrl-0 = <&hdmim0_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda>; + frl-enable-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim0_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda + &hdmi0_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -277,6 +280,12 @@ &pcie3x4 { }; &pinctrl { + hdmi { + hdmi0_tx_on_h: hdmi0-tx-on-h { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + lcd { lcdpwr_en: lcdpwr-en { rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts index 09bc7b68dcc0..977849bfd509 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -360,6 +360,10 @@ &gpu { }; &hdmi0 { + frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -376,6 +380,10 @@ hdmi0_out_con: endpoint { }; &hdmi1 { + frl-enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd + &hdmim1_tx1_scl &hdmim1_tx1_sda &hdmi1_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -612,6 +620,16 @@ rtl8211f_rst: rtl8211f-rst { }; + hdmi { + hdmi0_tx_on_h: hdmi0-tx-on-h { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hdmi1_tx_on_h: hdmi1-tx-on-h { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hdmirx { hdmirx_hpd: hdmirx-5v-detection { rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts index 60ba6ac55b23..b7d2cb456148 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts @@ -143,6 +143,10 @@ &gpu { }; &hdmi0 { + frl-enable-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -183,6 +187,12 @@ &pd_gpu { }; &pinctrl { + hdmi { + hdmi0_tx_on_h: hdmi0-tx-on-h { + rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hym8563 { hym8563_int: hym8563-int { rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts b/arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts index e086114c7634..e43afb0c53fb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts @@ -322,6 +322,10 @@ &gpu { }; &hdmi0 { + frl-enable-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -487,6 +491,12 @@ dp1_hpd: dp1-hpd { }; }; + hdmi { + hdmi0_tx_on_h: hdmi0-tx-on-h { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hym8563 { hym8563_int: hym8563-int { rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts index 10a7d3691a26..0dce96ca8c28 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts @@ -331,6 +331,10 @@ &gpio4 { }; &hdmi0 { + frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -347,6 +351,10 @@ hdmi0_out_con: endpoint { }; &hdmi1 { + frl-enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd + &hdmim1_tx1_scl &hdmim1_tx1_sda &hdmi1_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -520,6 +528,16 @@ key1_pin: key1-pin { }; }; + hdmi { + hdmi0_tx_on_h: hdmi0-tx-on-h { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hdmi1_tx_on_h: hdmi1-tx-on-h { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hdmirx { hdmirx_hpd: hdmirx-5v-detection { rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts b/arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts index 73d8ce4fde2b..7c2a1e6bcff9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts @@ -210,6 +210,10 @@ &gpu { }; &hdmi0 { + frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -339,6 +343,12 @@ &pd_gpu { }; &pinctrl { + hdmi { + hdmi0_tx_on_h: hdmi0-tx-on-h { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hym8563 { hym8563_int: hym8563-int { rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts index 5f5d89a33a4a..05b524f682cf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts @@ -278,8 +278,10 @@ &gpu { &hdmi0 { /* No CEC on Jaguar */ + frl-enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim0_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda + &hdmi0_tx_on_h>; pinctrl-names = "default"; - pinctrl-0 = <&hdmim0_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda>; status = "okay"; }; @@ -571,6 +573,12 @@ eth_reset: eth-reset { }; }; + hdmi { + hdmi0_tx_on_h: hdmi0-tx-on-h { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + leds { led1_pin: led1-pin { rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts b/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts index 78a4e896f665..36a5977d0795 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts @@ -148,6 +148,10 @@ &gpu { }; &hdmi0 { + frl-enable-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -205,6 +209,12 @@ dp1_hpd: dp1-hpd { }; }; + hdmi { + hdmi0_tx_on_h: hdmi0-tx-on-h { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pcie2 { pcie2_0_rst: pcie2-0-rst { rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi index 84b6b53f016a..3b0903d0e3e2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi @@ -361,6 +361,10 @@ &gpu { }; &hdmi0 { + frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -381,6 +385,10 @@ &hdmi0_sound { }; &hdmi1 { + frl-enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd + &hdmim1_tx1_scl &hdmim1_tx1_sda &hdmi1_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -682,6 +690,16 @@ usr_led_pin: usr-led-pin { }; }; + hdmi { + hdmi0_tx_on_h: hdmi0-tx-on-h { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hdmi1_tx_on_h: hdmi1-tx-on-h { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hdmirx { hdmirx_hpd: hdmirx-5v-detection { rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts index 8b1d35760c3b..762f9fd966a4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts @@ -35,6 +35,10 @@ hdmi1_con_in: endpoint { }; &hdmi0 { + frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -55,9 +59,10 @@ &hdmi0_sound { }; &hdmi1 { - pinctrl-names = "default"; + frl-enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>; pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd - &hdmim1_tx1_scl &hdmim1_tx1_sda>; + &hdmim1_tx1_scl &hdmim1_tx1_sda &hdmi1_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -102,6 +107,15 @@ &led_green_pwm { }; &pinctrl { + hdmi { + hdmi0_tx_on_h: hdmi0-tx-on-h { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hdmi1_tx_on_h: hdmi1-tx-on-h { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; usb { usb_otg_pwren: usb-otg-pwren { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts index 9950d1147e12..7142938d2971 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts @@ -121,6 +121,10 @@ &fan { }; &hdmi0 { + frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -141,6 +145,10 @@ hdmi0_out_con: endpoint { }; &hdmi1 { + frl-enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd + &hdmim1_tx1_scl &hdmim1_tx1_sda &hdmi1_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -278,6 +286,16 @@ &pcie2x1l2 { }; &pinctrl { + hdmi { + hdmi0_tx_on_h: hdmi0-tx-on-h { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hdmi1_tx_on_h: hdmi1-tx-on-h { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hym8563 { hym8563_int: hym8563-int { rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-ultra.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-ultra.dts index f8c6c080e418..2b693dfb434c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-ultra.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-ultra.dts @@ -25,9 +25,10 @@ hdmi1_con_in: endpoint { }; &hdmi1 { - pinctrl-names = "default"; + frl-enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>; pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd - &hdmim1_tx1_scl &hdmim1_tx1_sda>; + &hdmim1_tx1_scl &hdmim1_tx1_sda &hdmi1_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -64,6 +65,12 @@ &led_green_pwm { }; &pinctrl { + hdmi { + hdmi1_tx_on_h: hdmi1-tx-on-h { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + usb { usb_otg_pwren: usb-otg-pwren { rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-roc-rt.dts b/arch/arm64/boot/dts/rockchip/rk3588-roc-rt.dts index 2d6fed2a84a3..c50217a7b559 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-roc-rt.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-roc-rt.dts @@ -325,6 +325,10 @@ &gpu { }; &hdmi0 { + frl-enable-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -345,6 +349,10 @@ &hdmi0_sound { }; &hdmi1 { + frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd + &hdmim1_tx1_scl &hdmim1_tx1_sda &hdmi1_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -583,6 +591,16 @@ led_pins: led-pins { }; }; + hdmi { + hdmi0_tx_on_h: hdmi0-tx-on-h { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hdmi1_tx_on_h: hdmi1-tx-on-h { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hym8563 { hym8563_int: hym8563-int { rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts index 1ff786251eb0..8473f3e90354 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts @@ -346,8 +346,10 @@ &gpu { }; &hdmi1 { + frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>; pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd - &hdmim1_tx1_scl &hdmim1_tx1_sda>; + &hdmim1_tx1_scl &hdmim1_tx1_sda &hdmi1_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -699,6 +701,12 @@ &pd_npu { }; &pinctrl { + hdmi { + hdmi1_tx_on_h: hdmi1-tx-on-h { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hym8563 { rtc_int: rtc-int { rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi index bf4a1d2e55ca..b2ca041b8e8b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi @@ -183,6 +183,10 @@ &gpu { }; &hdmi0 { + frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -203,8 +207,10 @@ &hdmi0_sound { }; &hdmi1 { + frl-enable-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>; pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd - &hdmim1_tx1_scl &hdmim1_tx1_sda>; + &hdmim1_tx1_scl &hdmim1_tx1_sda &hdmi1_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -505,6 +511,16 @@ &pd_npu { }; &pinctrl { + hdmi { + hdmi0_tx_on_h: hdmi0-tx-on-h { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hdmi1_tx_on_h: hdmi1-tx-on-h { + rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hym8563 { hym8563_int: hym8563-int { rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts index caa43d1abf17..08b7d477d8db 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts @@ -172,8 +172,9 @@ &hdmi0 { * While HDMI-CEC is present on the Q7 connector, it is not * connected on Haikou itself. */ + pinctrl-0 = <&hdmim0_tx0_hpd &hdmim1_tx0_scl &hdmim1_tx0_sda + &hdmi0_tx_on_h>; pinctrl-names = "default"; - pinctrl-0 = <&hdmim0_tx0_hpd &hdmim1_tx0_scl &hdmim1_tx0_sda>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi index a0e97481afb7..ea5c264d1537 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi @@ -148,9 +148,10 @@ &gpu { }; &hdmi0 { - pinctrl-names = "default"; + frl-enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; pinctrl-0 = <&hdmim1_tx0_cec &hdmim0_tx0_hpd &hdmim1_tx0_scl - &hdmim1_tx0_sda>; + &hdmim1_tx0_sda &hdmi0_tx_on_h>; + pinctrl-names = "default"; }; &i2c1 { @@ -349,6 +350,12 @@ eth_reset: eth-reset { }; }; + hdmi { + hdmi0_tx_on_h: hdmi0-tx-on-h { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + leds { module_led_pin: module-led-pin { rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; From 3305c44489505e98e794cacce80cb1de9f1b81ad Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 28 Apr 2026 00:57:23 +0300 Subject: [PATCH 138/665] arm64: dts: rockchip: Add frl-enable-gpios to rk3588s boards The following RK3588s boards expose a GPIO pin to control the voltage bias on the HDMI0 data lines: - rk3588s-coolpi-4b - rk3588s-indiedroid-nova - rk3588s-nanopi-r6 - rk3588s-odroid-m2 - rk3588s-orangepi-5 - rk3588s-radxa-cm5-io - rk3588s-rock-5a - rk3588s-rock-5c The pin must be asserted when operating in HDMI 2.1 FRL mode and deasserted for HDMI 1.4/2.0 TMDS mode. Wire up the hdmi0 node to its dedicated GPIO via frl-enable-gpios to allow adjusting the bias when transitioning between TMDS and FRL modes. While at it, also ensure that pinctrl-names is present and ordered alphabetically within the hdmi nodes. Signed-off-by: Cristian Ciocaltea Link: https://patch.msgid.link/20260428-dts-rk-frl-enable-gpios-v2-5-924df9db884a@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts | 10 ++++++++++ .../boot/dts/rockchip/rk3588s-indiedroid-nova.dts | 10 +++++++++- arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi | 10 ++++++++++ arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts | 10 ++++++++++ arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi | 10 ++++++++++ .../arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts | 10 ++++++++++ arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 12 ++++++++++-- arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts | 12 ++++++++++-- 8 files changed, 79 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts index 189444d20779..16f19109fca6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts @@ -251,6 +251,10 @@ &gpu { }; &hdmi0 { + frl-enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -396,6 +400,12 @@ &pd_gpu { }; &pinctrl { + hdmi { + hdmi0_tx_on_h: hdmi0-tx-on-h { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hym8563 { hym8563_int: hym8563-int { rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts index 174d299cc6bb..f9e3c0134d5f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts @@ -277,8 +277,10 @@ &gpu { }; &hdmi0 { + frl-enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>; pinctrl-0 = <&hdmim0_tx0_scl>, <&hdmim0_tx0_sda>, - <&hdmim0_tx0_hpd>, <&hdmim0_tx0_cec>; + <&hdmim0_tx0_hpd>, <&hdmim0_tx0_cec>, + <&hdmi0_tx_on_h>; pinctrl-names = "default"; status = "okay"; }; @@ -517,6 +519,12 @@ bt_wake_host: bt-wake-host { }; }; + hdmi { + hdmi0_tx_on_h: hdmi0-tx-on-h { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hym8563 { hym8563_int: hym8563-int { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi index 1b6a59f7cabc..b9c0a1a050a9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi @@ -236,6 +236,10 @@ &gpu { }; &hdmi0 { + frl-enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -404,6 +408,12 @@ lan2_led_pin: lan2-led-pin { }; }; + hdmi { + hdmi0_tx_on_h: hdmi0-tx-on-h { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hym8563 { rtc_int: rtc-int { rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts index a72063c55140..4e98fa33492c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts @@ -249,6 +249,10 @@ &gpu { }; &hdmi0 { + frl-enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -438,6 +442,12 @@ &pd_gpu { }; &pinctrl { + hdmi { + hdmi0_tx_on_h: hdmi0-tx-on-h { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + lcd { lcd_pwren: lcd-pwren { rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi index dafad29f9854..cd80cb15a405 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi @@ -181,6 +181,10 @@ &gpu { }; &hdmi0 { + frl-enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -381,6 +385,12 @@ &pd_npu { }; &pinctrl { + hdmi { + hdmi0_tx_on_h: hdmi0-tx-on-h { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hym8563 { hym8563_int: hym8563-int { rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts index f80d5a00a4bd..af4a9bc015e1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts @@ -120,6 +120,10 @@ &gmac1 { }; &hdmi0 { + frl-enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -217,6 +221,12 @@ usbc0_int: usbc0-int { }; }; + hdmi { + hdmi0_tx_on_h: hdmi0-tx-on-h { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + usb { vcc5v0_host_en: vcc5v0-host-en { rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts index 0991f6a21190..ffd26b43ae8c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts @@ -323,11 +323,13 @@ &gmac1_rgmii_clk }; &hdmi0 { - pinctrl-names = "default"; + frl-enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>; pinctrl-0 = <&hdmim0_tx0_cec &hdmim1_tx0_hpd &hdmim0_tx0_scl - &hdmim0_tx0_sda>; + &hdmim0_tx0_sda + &hdmi0_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -373,6 +375,12 @@ &pd_gpu { }; &pinctrl { + hdmi { + hdmi0_tx_on_h: hdmi0-tx-on-h { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + leds { io_led: io-led { rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts index 7fe42f4ff827..9d3d0791554d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts @@ -258,11 +258,13 @@ &gpu { }; &hdmi0 { - pinctrl-names = "default"; + frl-enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>; pinctrl-0 = <&hdmim0_tx0_cec &hdmim1_tx0_hpd &hdmim0_tx0_scl - &hdmim0_tx0_sda>; + &hdmim0_tx0_sda + &hdmi0_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -461,6 +463,12 @@ &pd_gpu { }; &pinctrl { + hdmi { + hdmi0_tx_on_h: hdmi0-tx-on-h { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + leds { led_pins: led-pins { rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, From cb3ee61e35a9d60e6410526fec7b74af9be22d88 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 28 Apr 2026 00:57:24 +0300 Subject: [PATCH 139/665] arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-gameforce-ace The board exposes the GPIO4_B3 pin to control the voltage bias on the HDMI0 data lines. It must be asserted when operating in HDMI 2.1 FRL mode and deasserted for HDMI 1.4/2.0 TMDS mode. Wire up the hdmi0 node to its dedicated GPIO via frl-enable-gpios to allow adjusting the bias when transitioning between TMDS and FRL modes. Additionally, drop the now unnecessary ddc-en-gpios property and the associated pinctrl-* entries from hdmi0-con, and rename the hdmi0_en pinmux to hdmi0_tx_on_h, in line with the naming commonly used in RK3588s-based board schematics. Signed-off-by: Cristian Ciocaltea Link: https://patch.msgid.link/20260428-dts-rk-frl-enable-gpios-v2-6-924df9db884a@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts b/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts index 89618394c0bf..b657d54c2c59 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts @@ -302,9 +302,6 @@ amp_headphone: headphone-amplifier { hdmi0-con { compatible = "hdmi-connector"; - ddc-en-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&hdmi0_en>; - pinctrl-names = "default"; type = "d"; port { @@ -514,8 +511,9 @@ &gpu { &hdmi0 { no-hpd; + frl-enable-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; pinctrl-0 = <&hdmim0_tx0_cec>, <&hdmim0_tx0_scl>, - <&hdmim0_tx0_sda>; + <&hdmim0_tx0_sda>, <&hdmi0_tx_on_h>; pinctrl-names = "default"; status = "okay"; }; @@ -893,7 +891,7 @@ charger_int_h: charger-int-h { }; hdmi { - hdmi0_en: hdmi0-en { + hdmi0_tx_on_h: hdmi0-tx-on-h { rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; }; From bb85f4f5541de9abbe7e300e94d58ea888dd3b33 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 28 Apr 2026 00:57:25 +0300 Subject: [PATCH 140/665] arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-khadas-edge2 The board exposes the GPIO4_B1 pin to control the voltage bias on the HDMI0 data lines. It must be asserted when operating in HDMI 2.1 FRL mode and deasserted for HDMI 1.4/2.0 TMDS mode. Wire up the hdmi0 node to its dedicated GPIO via frl-enable-gpios to allow adjusting the bias when transitioning between TMDS and FRL modes. While at it, remove the duplicated &hdmi0_sound node. Signed-off-by: Cristian Ciocaltea Link: https://patch.msgid.link/20260428-dts-rk-frl-enable-gpios-v2-7-924df9db884a@collabora.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588s-khadas-edge2.dts | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts index 2c22abaf40a8..5afbc593341b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts @@ -194,6 +194,10 @@ &gpu { }; &hdmi0 { + frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -217,10 +221,6 @@ &hdptxphy0 { status = "okay"; }; -&hdmi0_sound { - status = "okay"; -}; - &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0m2_xfer>; @@ -282,6 +282,12 @@ &pd_gpu { }; &pinctrl { + hdmi { + hdmi0_tx_on_h: hdmi0-tx-on-h { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + vdd_sd { vdd_sd_en: vdd-sd-en { rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; From 640c768d315b25f8e56844d1d71c8d0040dfd88b Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 28 Apr 2026 00:57:26 +0300 Subject: [PATCH 141/665] arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-orangepi-cm5-base The board exposes the GPIO4_B5 pin to control the voltage bias on the HDMI0 data lines. It must be asserted when operating in HDMI 2.1 FRL mode and deasserted for HDMI 1.4/2.0 TMDS mode. Wire up the hdmi0 node to its dedicated GPIO via frl-enable-gpios to allow adjusting the bias when transitioning between TMDS and FRL modes. While at it, rename the hdmi_frl_pin pinmux to hdmi0_tx_on_h, in line with the naming commonly used in RK3588s-bassed board schematics. Signed-off-by: Cristian Ciocaltea Link: https://patch.msgid.link/20260428-dts-rk-frl-enable-gpios-v2-8-924df9db884a@collabora.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts index 06120b2db690..20da0c2b3d92 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts @@ -143,10 +143,11 @@ &gmac1_rgmii_clk }; &hdmi0 { - pinctrl-names = "default"; + frl-enable-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda - &hdmi_frl_pin>; + &hdmi0_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -245,8 +246,8 @@ key1_pin: key1-pin { }; hdmi { - hdmi_frl_pin: hdmi-frl-pin { - rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + hdmi0_tx_on_h: hdmi0-tx-on-h { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; From 0c58a27bf04d88c979dc8ce86c62bb13d15626e4 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 28 Apr 2026 00:57:27 +0300 Subject: [PATCH 142/665] arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-roc-pc The board exposes the GPIO4_B2 line to control the voltage bias on the HDMI0 data lines. It must be asserted when operating in HDMI 2.1 FRL mode and deasserted for HDMI 1.4/2.0 TMDS mode. Wire up the hdmi0 node to its dedicated GPIO via frl-enable-gpios to allow adjusting the bias when transitioning between TMDS and FRL modes. While at it, move hym8563 down to fix the ordering of &pinctrl entries. Signed-off-by: Cristian Ciocaltea Link: https://patch.msgid.link/20260428-dts-rk-frl-enable-gpios-v2-9-924df9db884a@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts index 7e179862da6e..aa02cf510d6d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts @@ -224,6 +224,10 @@ &gpu { }; &hdmi0 { + frl-enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -367,9 +371,9 @@ &pd_gpu { }; &pinctrl { - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + hdmi { + hdmi0_tx_on_h: hdmi0-tx-on-h { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; @@ -379,6 +383,12 @@ hp_detect: hp-detect { }; }; + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + leds { led_pins: led-pins { rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, From 161e023cafaca600aa7e5d5fab437334e6e6bcca Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 28 Apr 2026 00:57:28 +0300 Subject: [PATCH 143/665] arm64: dts: rockchip: Drop unnecessary #{address,size}-cells from rk3588-jaguar Remove the unnecessary #address-cells and #size-cells properties from the usb_host0_xhci and usb_host1_xhci port nodes, as they each contain a single endpoint child with no reg property. This fixes the following dtc warnings: rk3588-jaguar.dts: Warning (avoid_unnecessary_addr_size): /usb@fc000000/port: unnecessary #address-cells/#size-cells [...] /usb@fc400000/port: unnecessary #address-cells/#size-cells [...] Signed-off-by: Cristian Ciocaltea Link: https://patch.msgid.link/20260428-dts-rk-frl-enable-gpios-v2-10-924df9db884a@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts index 05b524f682cf..033db78aff67 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts @@ -1142,9 +1142,6 @@ &usb_host0_xhci { status = "okay"; port { - #address-cells = <1>; - #size-cells = <0>; - usb_host0_xhci_drd_sw: endpoint { remote-endpoint = <&usbc0_hs>; }; @@ -1157,9 +1154,6 @@ &usb_host1_xhci { status = "okay"; port { - #address-cells = <1>; - #size-cells = <0>; - usb_host1_xhci_drd_sw: endpoint { remote-endpoint = <&usbc1_hs>; }; From 78f650c45ec342c16f80c50e7ee77272e76f179e Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 28 Apr 2026 00:57:29 +0300 Subject: [PATCH 144/665] arm64: dts: rockchip: Add missing pinctrl-names to rk3576 boards Several rk3576 board DTS files override pinctrl-0 for uart0 without re-specifying pinctrl-names. While the property is inherited from the base rk3576.dtsi, add it explicitly to the board-level overrides for consistency with other nodes. Signed-off-by: Cristian Ciocaltea Link: https://patch.msgid.link/20260428-dts-rk-frl-enable-gpios-v2-11-924df9db884a@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576-100ask-dshanpi-a1.dts | 1 + arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts | 1 + arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts | 1 + arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts | 1 + 4 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-100ask-dshanpi-a1.dts b/arch/arm64/boot/dts/rockchip/rk3576-100ask-dshanpi-a1.dts index a9e3beb3ee5e..05fb4a7f9a16 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-100ask-dshanpi-a1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-100ask-dshanpi-a1.dts @@ -815,6 +815,7 @@ &u2phy1_otg { &uart0 { pinctrl-0 = <&uart0m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts index c3e8966c09c4..4ac4465e39a5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts @@ -975,6 +975,7 @@ &u2phy1_otg { &uart0 { pinctrl-0 = <&uart0m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts index 54de3a50571f..8411c16fa471 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts @@ -776,6 +776,7 @@ wd_en: wd-en { &uart0 { pinctrl-0 = <&uart0m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts index cc054c837317..272af1012ab0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts @@ -833,6 +833,7 @@ &u2phy1_otg { &uart0 { pinctrl-0 = <&uart0m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; From 0c2c0b6cdd71c5a43f83db2e0dcffe4701d10b87 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 28 Apr 2026 00:57:30 +0300 Subject: [PATCH 145/665] arm64: dts: rockchip: Add missing pinctrl-names to rk3588 boards Several rk3588 board DTS files override pinctrl-0 for i2c, i2s, pcie, pwm, sdmmc, spdif, spi and uart nodes without re-specifying pinctrl-names. While the property is inherited from the base SoC DTSI, add it explicitly to the board-level overrides for consistency with other nodes. Signed-off-by: Cristian Ciocaltea Link: https://patch.msgid.link/20260428-dts-rk-frl-enable-gpios-v2-12-924df9db884a@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts | 1 + arch/arm64/boot/dts/rockchip/rk3588-armsom-w3.dts | 1 + .../boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts | 1 + arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi | 4 ++++ .../arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi | 1 + arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 2 ++ arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts | 1 + arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi | 1 + .../boot/dts/rockchip/rk3588-firefly-core-3588j.dtsi | 1 + .../boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi | 1 + .../arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts | 2 ++ arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts | 1 + arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts | 8 ++++++++ arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts | 2 ++ arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 3 +++ arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 2 ++ arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi | 1 + arch/arm64/boot/dts/rockchip/rk3588-roc-rt.dts | 1 + arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts | 2 ++ arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi | 1 + arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts | 1 + arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi | 9 +++++++++ arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts | 1 + arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 2 ++ 24 files changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts index c4854c0f22e2..1005b15d708a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts @@ -788,6 +788,7 @@ &u2phy3_host { &uart2 { pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-w3.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-w3.dts index 3bbafdd89ede..faeddcfdeb32 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-w3.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-w3.dts @@ -439,6 +439,7 @@ &sdio { &uart2 { pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts index e05e6b2d5136..37d7b82ad553 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts @@ -335,6 +335,7 @@ pcie_wake: pcie-wake { &pwm6 { pinctrl-0 = <&pwm6m1_pins>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi index b07543315f87..33dacaa6af4d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi @@ -143,6 +143,7 @@ &gpu { &i2c0 { pinctrl-0 = <&i2c0m2_xfer>; + pinctrl-names = "default"; status = "okay"; vdd_cpu_big0_s0: regulator@42 { @@ -219,6 +220,7 @@ hym8563: rtc@51 { &i2c7 { pinctrl-0 = <&i2c7m0_xfer>; + pinctrl-names = "default"; status = "okay"; es8316: audio-codec@10 { @@ -244,6 +246,7 @@ &i2s0_mclk &i2s0_sclk &i2s0_sdi0 &i2s0_sdo0>; + pinctrl-names = "default"; status = "okay"; i2s0_8ch_p0: port { @@ -656,5 +659,6 @@ &tsadc { &uart2 { pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi index 08920344a4b8..2751f84a4b8b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi @@ -252,6 +252,7 @@ &sdmmc { &uart2 { pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts index 977849bfd509..8969b56f3063 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -510,6 +510,7 @@ &i2s0_mclk &i2s0_sclk &i2s0_sdi0 &i2s0_sdo0>; + pinctrl-names = "default"; status = "okay"; }; @@ -1386,6 +1387,7 @@ &u2phy3_host { &uart2 { pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts index b7d2cb456148..059ab02411d9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts @@ -921,6 +921,7 @@ &u2phy3_host { &uart2 { pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi index 4331cdc70f97..d3fb2677a855 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi @@ -558,5 +558,6 @@ &tsadc { &uart2 { pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-firefly-core-3588j.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-firefly-core-3588j.dtsi index 80e16ea4154c..ecb27b4a29bd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-firefly-core-3588j.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-firefly-core-3588j.dtsi @@ -443,5 +443,6 @@ regulator-state-mem { /* rk3588 preferred debug out */ &uart2 { pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi index 6726eeb49255..80ca7e78354c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi @@ -439,5 +439,6 @@ regulator-state-mem { &uart2 { pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts b/arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts index e43afb0c53fb..8dac069f8351 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts @@ -568,11 +568,13 @@ &sata2 { /* uart/232/485 */ &uart0 { pinctrl-0 = <&uart0m2_xfer>; + pinctrl-names = "default"; status = "okay"; }; &uart1 { pinctrl-0 = <&uart1m1_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts b/arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts index 7c2a1e6bcff9..3811f9a73bb6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts @@ -784,6 +784,7 @@ &u2phy1_otg { &uart2 { pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts index 033db78aff67..41758fe7d368 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts @@ -307,6 +307,7 @@ &hdptxphy0 { &i2c0 { pinctrl-0 = <&i2c0m2_xfer>; + pinctrl-names = "default"; status = "okay"; fan@18 { @@ -417,10 +418,12 @@ regulator-state-mem { &i2c1 { pinctrl-0 = <&i2c1m4_xfer>; + pinctrl-names = "default"; }; &i2c6 { pinctrl-0 = <&i2c6m4_xfer>; + pinctrl-names = "default"; }; &i2c7 { @@ -439,6 +442,7 @@ eeprom@54 { &i2c8 { pinctrl-0 = <&i2c8m2_xfer>; + pinctrl-names = "default"; status = "okay"; typec-portc@22 { @@ -1054,18 +1058,21 @@ &u2phy3_host { /* Mule-ATtiny debug UART; typically baudrate 9600 */ &uart0 { pinctrl-0 = <&uart0m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; /* Main debug interface on P20 micro-USB B port and P21 header */ &uart2 { pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; /* RS485 on P19 */ &uart3 { pinctrl-0 = <&uart3m2_xfer &uart3_rtsn>; + pinctrl-names = "default"; linux,rs485-enabled-at-boot-time; status = "okay"; }; @@ -1073,6 +1080,7 @@ &uart3 { /* Mule-ATtiny UPDI flashing UART */ &uart7 { pinctrl-0 = <&uart7m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts b/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts index 36a5977d0795..9052e0d5494f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts @@ -185,6 +185,7 @@ rgmii_phy: ethernet-phy@0 { &pcie2x1l2 { pinctrl-0 = <&pcie2_0_rst>; + pinctrl-names = "default"; reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -236,6 +237,7 @@ eth_phy_reset: eth-phy-reset { &pwm8 { pinctrl-0 = <&pwm8m2_pins>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi index 3b0903d0e3e2..7495af5bd973 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi @@ -579,6 +579,7 @@ rt5616_p0_0: endpoint { &i2c8 { pinctrl-0 = <&i2c8m2_xfer>; + pinctrl-names = "default"; }; &i2s0_8ch { @@ -763,6 +764,7 @@ usbc0_int: usbc0-int { &pwm1 { pinctrl-0 = <&pwm1m1_pins>; + pinctrl-names = "default"; status = "okay"; }; @@ -1174,6 +1176,7 @@ &tsadc { &uart2 { pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts index 7142938d2971..145986695720 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts @@ -351,6 +351,7 @@ &pwm2 { &pwm3 { pinctrl-0 = <&pwm3m1_pins>; + pinctrl-names = "default"; status = "okay"; }; @@ -369,6 +370,7 @@ &u2phy1_otg { &uart9 { pinctrl-0 = <&uart9m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi index 3bceee948458..4e9fe872b581 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi @@ -822,6 +822,7 @@ &u2phy3_host { &uart2 { pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-roc-rt.dts b/arch/arm64/boot/dts/rockchip/rk3588-roc-rt.dts index c50217a7b559..02d532c77a26 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-roc-rt.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-roc-rt.dts @@ -1059,6 +1059,7 @@ &u2phy3_host { &uart2 { pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts index 8473f3e90354..6f25e088f318 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts @@ -927,6 +927,7 @@ spi_flash: flash@0 { &spdif_tx1 { pinctrl-0 = <&spdif1m2_tx>; + pinctrl-names = "default"; status = "okay"; }; @@ -1261,6 +1262,7 @@ &tsadc { &uart2 { pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi index b2ca041b8e8b..13aaf63ad093 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi @@ -975,6 +975,7 @@ &tsadc { &uart2 { pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts index 08b7d477d8db..873fbeb8daa1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts @@ -274,6 +274,7 @@ &sdmmc { cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; disable-wp; pinctrl-0 = <&sdmmc_bus4 &sdmmc_cmd &sdmmc_clk>; + pinctrl-names = "default"; sd-uhs-sdr12; sd-uhs-sdr25; sd-uhs-sdr50; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi index ea5c264d1537..139f70e7bbd9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi @@ -156,6 +156,7 @@ &hdmi0 { &i2c1 { pinctrl-0 = <&i2c1m0_xfer>; + pinctrl-names = "default"; }; &i2c1m0_xfer { @@ -168,6 +169,7 @@ &i2c1m0_xfer { &i2c2 { pinctrl-0 = <&i2c2m3_xfer>; + pinctrl-names = "default"; }; &i2c2m3_xfer { @@ -180,10 +182,12 @@ &i2c2m3_xfer { &i2c3 { pinctrl-0 = <&i2c3m0_xfer>; + pinctrl-names = "default"; }; &i2c4 { pinctrl-0 = <&i2c4m4_xfer>; + pinctrl-names = "default"; status = "okay"; vdd_npu_s0: regulator@42 { @@ -205,6 +209,7 @@ regulator-state-mem { &i2c5 { pinctrl-0 = <&i2c5m1_xfer>; + pinctrl-names = "default"; }; &i2c5m1_xfer { @@ -302,6 +307,7 @@ &i2c7m0_xfer { &i2c8 { pinctrl-0 = <&i2c8m2_xfer>; + pinctrl-names = "default"; }; &mdio0 { @@ -441,6 +447,7 @@ &sdmmc { &spi0 { pinctrl-0 = <&spi0m1_cs0 &spi0m1_cs1 &spi0m3_pins>; + pinctrl-names = "default"; }; &spi2 { @@ -771,10 +778,12 @@ &tsadc { /* Routed to UART0 on the Q7 connector */ &uart2 { pinctrl-0 = <&uart2m2_xfer>; + pinctrl-names = "default"; }; /* Mule-ATtiny UPDI */ &uart4 { pinctrl-0 = <&uart4m2_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts index 5a428e00ab93..85ac072f64b9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts @@ -675,6 +675,7 @@ &u2phy3_host { &uart2 { pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi index b11d24dcc180..9d5d4cfe0170 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi @@ -704,11 +704,13 @@ &tsadc { &uart2 { pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; &uart9 { pinctrl-0 = <&uart9m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; From 224aa83f3f73a8b17051c1639125260cc04617bc Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 28 Apr 2026 00:57:31 +0300 Subject: [PATCH 146/665] arm64: dts: rockchip: Add missing pinctrl-names to rk3588s boards Several rk3588s board DTS files override pinctrl-0 for i2c, i2s, pwm, spi, tsadc and uart nodes without re-specifying pinctrl-names. While the property is inherited from the base rk3588s.dtsi, add it explicitly to the board-level overrides for consistency with other nodes. Signed-off-by: Cristian Ciocaltea Link: https://patch.msgid.link/20260428-dts-rk-frl-enable-gpios-v2-13-924df9db884a@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts | 6 ++++++ arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts | 1 + arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts | 7 +++++++ arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts | 3 +++ arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 1 + arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi | 1 + arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi | 1 + arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts | 3 +++ arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5.dtsi | 3 +++ arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts | 1 + arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 1 + arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts | 1 + 12 files changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts index 16f19109fca6..2e8661ac7fcf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts @@ -276,6 +276,7 @@ &hdptxphy0 { &i2c0 { pinctrl-0 = <&i2c0m2_xfer>; + pinctrl-names = "default"; status = "okay"; vdd_cpu_big0_s0: regulator@42 { @@ -336,6 +337,7 @@ regulator-state-mem { &i2c6 { pinctrl-0 = <&i2c6m3_xfer>; + pinctrl-names = "default"; status = "okay"; hym8563: rtc@51 { @@ -352,6 +354,7 @@ hym8563: rtc@51 { &i2c7 { pinctrl-0 = <&i2c7m0_xfer>; + pinctrl-names = "default"; status = "okay"; es8316: audio-codec@10 { @@ -377,6 +380,7 @@ &i2s0_mclk &i2s0_sclk &i2s0_sdi0 &i2s0_sdo0>; + pinctrl-names = "default"; status = "okay"; i2s0_8ch_p0: port { @@ -469,6 +473,7 @@ wifi_poweren_pin: wifi-poweren-pin { &pwm2 { pinctrl-0 = <&pwm2m1_pins>; + pinctrl-names = "default"; status = "okay"; }; @@ -875,6 +880,7 @@ &u2phy3_host { &uart2 { pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts index d6b62cd1b90b..c4ddb78f9bb2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts @@ -457,6 +457,7 @@ usbc0_int: usbc0-int { &pwm12 { pinctrl-0 = <&pwm12m1_pins>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts b/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts index b657d54c2c59..230aac005e8f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts @@ -614,6 +614,7 @@ touchscreen@14 { &i2c4 { pinctrl-0 = <&i2c4m2_xfer>; + pinctrl-names = "default"; status = "okay"; ti_adc: adc@48 { @@ -650,6 +651,7 @@ imu@68 { &i2c6 { pinctrl-0 = <&i2c6m3_xfer>; + pinctrl-names = "default"; status = "okay"; fusb302: typec@22 { @@ -783,6 +785,7 @@ &i2s0_mclk &i2s0_sclk &i2s0_sdi0 &i2s0_sdo0>; + pinctrl-names = "default"; status = "okay"; }; @@ -1026,11 +1029,13 @@ wifi_host_wake_irq: wifi-host-wake-irq { &pwm12 { pinctrl-0 = <&pwm12m1_pins>; + pinctrl-names = "default"; status = "okay"; }; &pwm13 { pinctrl-0 = <&pwm13m1_pins>; + pinctrl-names = "default"; status = "okay"; }; @@ -1432,11 +1437,13 @@ &u2phy0_otg { &uart2 { pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; &uart9 { pinctrl-0 = <&uart9m2_xfer>, <&uart9m2_ctsn>, <&uart9m2_rtsn>; + pinctrl-names = "default"; uart-has-rtscts; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts index f9e3c0134d5f..ed36c27c2320 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts @@ -368,6 +368,7 @@ regulator-state-mem { &i2c6 { pinctrl-0 = <&i2c6m3_xfer>; + pinctrl-names = "default"; status = "okay"; fusb302: typec-portc@22 { @@ -440,6 +441,7 @@ rtc_hym8563: rtc@51 { &i2c7 { pinctrl-0 = <&i2c7m0_xfer>; + pinctrl-names = "default"; status = "okay"; es8388: audio-codec@11 { @@ -973,6 +975,7 @@ &u2phy3_host { &uart2 { pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts index 5afbc593341b..833f27fdd1c6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts @@ -742,6 +742,7 @@ &tsadc { &uart2 { pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi index b9c0a1a050a9..91b6eefd7abf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi @@ -851,6 +851,7 @@ &u2phy2_host { &uart2 { pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi index cd80cb15a405..9da13f96f13a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi @@ -847,6 +847,7 @@ &u2phy3_host { &uart2 { pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts index 20da0c2b3d92..0145e194841c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts @@ -173,6 +173,7 @@ &hdptxphy0 { &i2c1 { pinctrl-0 = <&i2c1m2_xfer>; + pinctrl-names = "default"; status = "okay"; rtc@51 { @@ -280,6 +281,7 @@ &pwm4 { &pwm5 { pinctrl-0 = <&pwm5m1_pins>; + pinctrl-names = "default"; status = "okay"; }; @@ -320,6 +322,7 @@ &u2phy2_host { &uart2 { pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5.dtsi index 32357eba4b78..5d3dc21c4d61 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5.dtsi @@ -64,6 +64,7 @@ &gpu { &i2c0 { pinctrl-0 = <&i2c0m2_xfer>; + pinctrl-names = "default"; status = "okay"; vdd_cpu_big0_s0: regulator@42 { @@ -142,6 +143,7 @@ &spi2 { assigned-clock-rates = <200000000>; num-cs = <1>; pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + pinctrl-names = "default"; status = "okay"; pmic@0 { @@ -468,5 +470,6 @@ &tsadc { * through the CRU. */ pinctrl-0 = <&tsadc_gpio_func>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts index aa02cf510d6d..d534d662c40f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts @@ -810,6 +810,7 @@ &uart2 { &uart7 { pinctrl-0 = <&uart7m2_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts index ffd26b43ae8c..a76734da982f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts @@ -827,6 +827,7 @@ &u2phy3_host { &uart2 { pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts index 9d3d0791554d..e4784885c267 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts @@ -930,6 +930,7 @@ &u2phy3_host { &uart2 { pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; status = "okay"; }; From 460bac478c5fe69054ffc60d607bba03bcaf909b Mon Sep 17 00:00:00 2001 From: Weixin Guo <2298701336@qq.com> Date: Mon, 27 Apr 2026 21:58:04 +0800 Subject: [PATCH 147/665] arm64: dts: rockchip: fix rk809 interrupt pin on rk3566-roc-pc The RK809 PMIC interrupt pin on the Firefly ROC-RK3566-PC (Station M2) is physically connected to GPIO0_A3 (RK_PA3) according to the board's schematic. Currently, the PMIC node incorrectly specifies RK_PA7 for the interrupt, which prevents the PMIC from correctly signaling interrupts. (Note that the pinctrl node 'pmic_int' correctly configures RK_PA3). Fix this by updating the interrupts property to use RK_PA3. Fixes: 30ac9b4e25d8 ("arm64: dts: rockchip: add dts for Firefly Station M2 rk3566") Signed-off-by: Weixin Guo <2298701336@qq.com> Link: https://patch.msgid.link/tencent_5035EEE630C845B1B51DEA4284DE23DCCE06@qq.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts index 7e499064e035..985770e3a5e2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts @@ -245,7 +245,7 @@ rk809: pmic@20 { compatible = "rockchip,rk809"; reg = <0x20>; interrupt-parent = <&gpio0>; - interrupts = ; + interrupts = ; clock-output-names = "rk808-clkout1", "rk808-clkout2"; assigned-clocks = <&cru I2S1_MCLKOUT_TX>; assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; From 0b7883ec2ff34bfd9567cd9a9a7cf7c2ccc6880a Mon Sep 17 00:00:00 2001 From: Florijan Plohl Date: Thu, 2 Apr 2026 12:56:09 +0200 Subject: [PATCH 148/665] arm64: dts: freescale: imx91-phycore-som: Add gpio-line-names Add gpio-line-names for GPIOs with a defined board-level function on the PHYTEC phyCORE-i.MX91 SoM. Signed-off-by: Florijan Plohl Signed-off-by: Frank Li --- .../boot/dts/freescale/imx91-phycore-som.dtsi | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi index 29a428a052b0..b9a453f6b290 100644 --- a/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi @@ -88,6 +88,28 @@ ethphy1: ethernet-phy@1 { }; }; +&gpio1 { + gpio-line-names = "", "USER_LED"; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", "", + "", "", "", "", "", + "", "", "", "", "", + "", "", "", "", "", + "", "", "", "", "", + "", "", "", "I2C3_SDA", "I2C3_SCL"; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", "", + "", "", "", "", "", + "", "", "", "", "", + "", "", "", "", "", + "", "", "", "RESET_PHY", "", + "", "", "PMIC_IRQ_B"; +}; + /* I2C3 */ &lpi2c3 { clock-frequency = <400000>; From eb5c0628c0e8cb34310bad33555470c2d3fa265f Mon Sep 17 00:00:00 2001 From: Florijan Plohl Date: Thu, 2 Apr 2026 12:56:10 +0200 Subject: [PATCH 149/665] arm64: dts: freescale: imx91-phyboard-segin: Add gpio-line-names Add gpio-line-names for GPIOs with a defined board-level function on the PHYTEC phyBOARD-Segin-i.MX91. Signed-off-by: Florijan Plohl Signed-off-by: Frank Li --- .../dts/freescale/imx91-phyboard-segin.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts index 7b18a58024f5..8b19fc17eacd 100644 --- a/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts +++ b/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts @@ -137,6 +137,24 @@ ethphy2: ethernet-phy@2 { }; }; +&gpio1 { + gpio-line-names = "", "USER_LED", "I2C1_SCL", "I2C1_SDA"; +}; + +&gpio3 { + gpio-line-names = "SD1_nCD", "", "", "", "", + "", "", "SD1_nRESET"; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", "", + "", "", "", "", "", + "", "", "", "", "", + "", "CAN_EN", "", "", "", + "", "", "", "RESET_PHY", "", + "", "RTC_nINT", "PMIC_IRQ_B"; +}; + /* CAN */ &flexcan1 { pinctrl-names = "default"; From ef902dc5caf4ce93d47811afa944bdba7298287e Mon Sep 17 00:00:00 2001 From: Florijan Plohl Date: Thu, 2 Apr 2026 12:56:11 +0200 Subject: [PATCH 150/665] arm64: dts: freescale: imx93-phycore-som: Add gpio-line-names Add gpio-line-names for GPIOs with a defined board-level function on the PHYTEC phyCORE-i.MX93 SoM. Signed-off-by: Florijan Plohl Signed-off-by: Frank Li --- .../boot/dts/freescale/imx93-phycore-som.dtsi | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi index ebc57841f27f..94eb04ace96e 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi @@ -90,6 +90,28 @@ ethphy1: ethernet-phy@1 { }; }; +&gpio1 { + gpio-line-names = "", "USER_LED"; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", "", + "", "", "", "", "", + "", "", "", "", "", + "", "", "", "", "", + "", "", "", "", "", + "", "", "", "I2C3_SDA", "I2C3_SCL"; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", "", + "", "", "", "", "", + "", "", "", "", "", + "", "", "", "", "", + "", "", "", "RESET_PHY", "", + "", "", "PMIC_IRQ_B"; +}; + /* I2C3 */ &lpi2c3 { clock-frequency = <400000>; From a318a8e676a1318c329057e9790453e79dae8db4 Mon Sep 17 00:00:00 2001 From: Florijan Plohl Date: Thu, 2 Apr 2026 12:56:12 +0200 Subject: [PATCH 151/665] arm64: dts: freescale: imx93-phyboard-nash: Add gpio-line-names Add gpio-line-names for GPIOs with a defined board-level function on the PHYTEC phyBOARD-Nash-i.MX93. Signed-off-by: Florijan Plohl Signed-off-by: Frank Li --- .../dts/freescale/imx93-phyboard-nash.dts | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts index eac389ed30f3..b82192f25498 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts @@ -141,6 +141,37 @@ &flexcan1 { status = "okay"; }; +&gpio1 { + gpio-line-names = "", "USER_LED", "I2C2_SCL", "I2C2_SDA"; +}; + +&gpio2 { + gpio-line-names = "SPI6_CS0", "", "", "", "", + "", "", "", "", "", + "", "", "", "", "", + "", "", "TPM_nIRQ", "", "", + "", "", "", "", "", + "", "", "", "I2C3_SDA", "I2C3_SCL"; +}; + +&gpio3 { + gpio-line-names = "SD2_nCD", "", "", "", "", + "", "", "SD2_nRESET", "", "", + "", "", "", "", "", + "", "", "", "", "", + "", "", "", "", "", + "", "nENET1_INT"; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", "", + "", "", "", "", "", + "", "", "", "", "", + "", "nCAN_EN", "", "", "", + "", "", "", "RESET_PHY", "", + "", "RTC_nINT", "PMIC_IRQ_B"; +}; + /* I2C2 */ &lpi2c2 { clock-frequency = <400000>; From 46e2e3a1c9f65f7555e19e5651cb924c3600ad3c Mon Sep 17 00:00:00 2001 From: Florijan Plohl Date: Thu, 2 Apr 2026 12:56:13 +0200 Subject: [PATCH 152/665] arm64: dts: freescale: imx93-phyboard-segin: Add gpio-line-names Add gpio-line-names for GPIOs with a defined board-level function on the PHYTEC phyBOARD-Segin-i.MX93. Signed-off-by: Florijan Plohl Signed-off-by: Frank Li --- .../dts/freescale/imx93-phyboard-segin.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts index a982606de1ee..4e4356397ba0 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts @@ -145,6 +145,24 @@ &flexcan1 { status = "okay"; }; +&gpio1 { + gpio-line-names = "", "USER_LED", "I2C1_SCL", "I2C1_SDA"; +}; + +&gpio3 { + gpio-line-names = "SD1_nCD", "", "", "", "", + "", "", "SD1_nRESET"; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", "", + "", "", "", "", "", + "", "", "", "", "", + "", "CAN_EN", "", "", "", + "", "", "", "RESET_PHY", "", + "", "RTC_nINT", "PMIC_IRQ_B"; +}; + /* I2C2 */ &lpi2c2 { clock-frequency = <400000>; From 67efe58b4ac7a088a0fe881fab368f93dc40046d Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Tue, 31 Mar 2026 11:21:12 +0200 Subject: [PATCH 153/665] arm64: dts: imx91-var-dart-sonata: add RGB enable supply for PCA6408 RGB enable pin, labeled as RGBSEL, is a board-level enable signal on the Sonata carrier board. The two PCA6408 GPIO expanders depend on this signal being asserted, so model it as a fixed regulator and use it as their vcc-supply. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts b/arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts index afa39dab240a..3f0fd321d95f 100644 --- a/arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts +++ b/arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts @@ -90,6 +90,13 @@ reg_vref_1v8: regulator-adc-vref { regulator-max-microvolt = <1800000>; }; + reg_rgb_sel: regulator-rgb-enable { + compatible = "regulator-fixed"; + regulator-name = "RGBSEL"; + gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -195,6 +202,7 @@ pca6408_1: gpio@20 { #gpio-cells = <2>; interrupt-parent = <&gpio1>; interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_rgb_sel>; }; pca6408_2: gpio@21 { @@ -204,6 +212,7 @@ pca6408_2: gpio@21 { #gpio-cells = <2>; interrupt-parent = <&gpio1>; interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_rgb_sel>; }; pca9534: gpio@22 { From 0a03ee38a262cab0d9754e9947d565e089a9f7a5 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 1 Apr 2026 14:40:56 +0800 Subject: [PATCH 154/665] arm64: dts: imx8x-colibri: Correct SODIMM PAD settings SION is BIT(30), not BIT(26). Correct it. Fixes: 7ece3cbc8b1ef ("arm64: dts: colibri-imx8x: Add atmel pinctrl groups") Signed-off-by: Peng Fan Reviewed-by: Daniel Baluta Reviewed-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index 47895ff8cb24..2415487d3a5d 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -631,12 +631,12 @@ pinctrl_adc0: adc0grp { */ pinctrl_atmel_adap: atmeladaptergrp { fsl,pins = , /* SODIMM 30 */ - ; /* SODIMM 28 */ + ; /* SODIMM 28 */ }; /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */ pinctrl_atmel_conn: atmelconnectorgrp { - fsl,pins = , /* SODIMM 107 */ + fsl,pins = , /* SODIMM 107 */ ; /* SODIMM 106 */ }; From dad7f95a1529f7a2b563d3e052968a0fc174b8e1 Mon Sep 17 00:00:00 2001 From: Guoniu Zhou Date: Fri, 27 Mar 2026 15:11:05 +0800 Subject: [PATCH 155/665] arm64: dts: imx8ulp: Add CSI and ISI Nodes The CSI-2 in the i.MX8ULP is almost identical to the version present in the i.MX8QXP/QM and is routed to the ISI. Add both the ISI and CSI nodes and mark them as disabled by default since capture is dependent on an attached camera. Reviewed-by: Frank Li Reviewed-by: Laurent Pinchart Signed-off-by: Guoniu Zhou Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 66 ++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index 1de3ad60c6aa..17caf3703fb1 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -858,6 +858,72 @@ spdif: spdif@2dab0000 { dma-names = "rx", "tx"; status = "disabled"; }; + + isi: isi@2dac0000 { + compatible = "fsl,imx8ulp-isi"; + reg = <0x2dac0000 0x10000>; + interrupts = ; + clocks = <&pcc5 IMX8ULP_CLK_ISI>, + <&cgc2 IMX8ULP_CLK_LPAV_AXI_DIV>; + clock-names = "axi", "apb"; + power-domains = <&scmi_devpd IMX8ULP_PD_ISI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + isi_in: endpoint { + remote-endpoint = <&mipi_csi_out>; + }; + }; + }; + }; + + mipi_csi: csi@2daf0000 { + compatible = "fsl,imx8ulp-mipi-csi2"; + reg = <0x2daf0000 0x10000>, + <0x2dad0000 0x10000>; + clocks = <&pcc5 IMX8ULP_CLK_CSI>, + <&pcc5 IMX8ULP_CLK_CSI_CLK_ESC>, + <&pcc5 IMX8ULP_CLK_CSI_CLK_UI>, + <&pcc5 IMX8ULP_CLK_CSI_REGS>; + clock-names = "core", "esc", "ui", "pclk"; + assigned-clocks = <&pcc5 IMX8ULP_CLK_CSI>, + <&pcc5 IMX8ULP_CLK_CSI_CLK_ESC>, + <&pcc5 IMX8ULP_CLK_CSI_CLK_UI>, + <&pcc5 IMX8ULP_CLK_CSI_REGS>; + assigned-clock-parents = <&cgc2 IMX8ULP_CLK_PLL4_PFD1_DIV1>, + <&cgc2 IMX8ULP_CLK_PLL4_PFD1_DIV2>, + <&cgc2 IMX8ULP_CLK_PLL4_PFD0_DIV1>; + assigned-clock-rates = <200000000>, + <80000000>, + <100000000>, + <79200000>; + power-domains = <&scmi_devpd IMX8ULP_PD_MIPI_CSI>; + resets = <&pcc5 5>, /* PCC5_CSI_REGS_SWRST */ + <&pcc5 6>; /* PCC5_CSI_SWRST> */ + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + mipi_csi_out: endpoint { + remote-endpoint = <&isi_in>; + }; + }; + }; + }; }; gpiod: gpio@2e200000 { From 5052c99cf05271b91fe2b4e6540f7a7d9b6db62f Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Tue, 28 Apr 2026 09:27:24 +0200 Subject: [PATCH 156/665] arm64: dts: rockchip: add mipi csi-2 receiver nodes to rk3588 The Rockchip RK3588 features six MIPI CSI-2 receiver units: - MIPI0: connected to MIPI DCPHY0 (not supported) - MIPI1: connected to MIPI DCPHY1 (not supported) - MIPI2: connected to MIPI DPHY0 - MIPI3: connected to MIPI DPHY0-1 (not supported) - MIPI4: connected to MIPI DPHY1 - MIPI5: connected to MIPI DPHY1-1 (not supported) As the MIPI DCPHYs as well as the split DPHY mode of the DPHYs are not yet supported, add only the device tree nodes for the MIPI2 and MIPI4 units. Signed-off-by: Michael Riesch Link: https://patch.msgid.link/20260305-rk3588-csi2rx-v5-2-3b7061d043ea@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index d4dc057e31f0..4535e0b6e979 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1430,6 +1430,58 @@ av1d: video-codec@fdc70000 { resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; }; + csi2: csi@fdd30000 { + compatible = "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2"; + reg = <0x0 0xfdd30000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "err1", "err2"; + clocks = <&cru PCLK_CSI_HOST_2>; + phys = <&csi_dphy0>; + power-domains = <&power RK3588_PD_VI>; + resets = <&cru SRST_P_CSI_HOST_2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_in: port@0 { + reg = <0>; + }; + + csi2_out: port@1 { + reg = <1>; + }; + }; + }; + + csi4: csi@fdd50000 { + compatible = "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2"; + reg = <0x0 0xfdd50000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "err1", "err2"; + clocks = <&cru PCLK_CSI_HOST_4>; + phys = <&csi_dphy1>; + power-domains = <&power RK3588_PD_VI>; + resets = <&cru SRST_P_CSI_HOST_4>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi4_in: port@0 { + reg = <0>; + }; + + csi4_out: port@1 { + reg = <1>; + }; + }; + }; + vop: vop@fdd90000 { compatible = "rockchip,rk3588-vop"; reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; From c1315c36141a3310723c443f6ab90a7e41ba60a0 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 3 Apr 2026 03:46:30 -0400 Subject: [PATCH 157/665] ARM: dts: imx35: remove empty clock-names for nand-controller@bb000000 clock-names is empty in nand-controller@bb000000, which is wrong. Remove it to fix below CHECK_DTBS warings: arch/arm/boot/dts/nxp/imx/imx35-pdk.dtb: nand-controller@bb000000 (fsl,imx35-nand): Unevaluated properties are not allowed ('clock-names' was unexpected) Reviewed-by: Miquel Raynal Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx35.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx35.dtsi b/arch/arm/boot/dts/nxp/imx/imx35.dtsi index 111d7c0331f5..b1e599cb28e7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx35.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx35.dtsi @@ -369,7 +369,6 @@ nfc: nand-controller@bb000000 { compatible = "fsl,imx35-nand", "fsl,imx25-nand"; reg = <0xbb000000 0x2000>; clocks = <&clks 29>; - clock-names = ""; interrupts = <33>; status = "disabled"; }; From 64b4b92f2b1650e8f6a0d142592325af2520695a Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 3 Apr 2026 03:46:31 -0400 Subject: [PATCH 158/665] ARM: dts: imx25: remove empty clock-names for nand-controller@bb000000 clock-names is empty in nand-controller@bb000000, which is wrong. Remove it to fix below CHECK_DTBS warings: arch/arm/boot/dts/nxp/imx/imx25-pdk.dtb: nand-controller@bb000000 (fsl,imx25-nand): Unevaluated properties are not allowed ('clock-names' was unexpected) Reviewed-by: Miquel Raynal Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx25.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx25.dtsi b/arch/arm/boot/dts/nxp/imx/imx25.dtsi index 82601a4b7b4b..189ba3db2e63 100644 --- a/arch/arm/boot/dts/nxp/imx/imx25.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx25.dtsi @@ -618,7 +618,6 @@ nfc: nand-controller@bb000000 { compatible = "fsl,imx25-nand"; reg = <0xbb000000 0x2000>; clocks = <&clks 50>; - clock-names = ""; interrupts = <33>; status = "disabled"; }; From da8dafc4dd394fa287def25bbce51eff3f761acb Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Thu, 26 Mar 2026 14:02:21 +0100 Subject: [PATCH 159/665] arm64: dts: freescale: add initial device tree for TQMa8x This adds support for TQMa8QM module on MBa8x board, based on i.MX8 SoC. Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8qm-tqma8qm-mba8x.dts | 910 ++++++++++++++++++ .../boot/dts/freescale/imx8qm-tqma8qm.dtsi | 318 ++++++ 3 files changed, 1229 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-tqma8qm-mba8x.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index ec2d2505d804..5dafb1b5d56f 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -408,6 +408,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-eval-v1.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.1.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-tqma8qm-mba8x.dtb imx8qm-mek-ov5640-csi0-dtbs := imx8qm-mek.dtb imx8qm-mek-ov5640-csi0.dtbo dtb-${CONFIG_ARCH_MXC} += imx8qm-mek-ov5640-csi0.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm-mba8x.dts b/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm-mba8x.dts new file mode 100644 index 000000000000..bf972010a88e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm-mba8x.dts @@ -0,0 +1,910 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2019-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +/dts-v1/; + +#include +#include +#include +#include +#include + +#include "imx8qm-tqma8qm.dtsi" + +/ { + model = "TQ-Systems i.MX8QM TQMa8QM on MBa8x"; + compatible = "tq,imx8qm-tqma8qm-mba8x", "tq,imx8qm-tqma8qm", "fsl,imx8qm"; + + adc { + compatible = "iio-hwmon"; + io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>; + }; + + aliases { + rtc0 = &pcf85063; + rtc1 = &rtc; + }; + + chosen { + stdout-path = &lpuart0; + }; + + + clk_xtal25: clk-xtal25 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + autorepeat; + + switch-1 { + label = "SWITCH_A"; + linux,code = ; + gpios = <&lsio_gpio2 11 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + switch-2 { + label = "SWITCH_B"; + linux,code = ; + gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpioled>; + + user-led0 { + color = ; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&lsio_gpio5 20 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + user-led1 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&lsio_gpio5 19 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwmfan>; + fan-supply = <®_pwm_fan>; + #cooling-cells = <2>; + /* typical 25 kHz -> 40.000 nsec */ + pwms = <&lsio_pwm3 0 40000 PWM_POLARITY_INVERTED>; + cooling-levels = <0 32 64 128 196 240>; + pulses-per-revolution = <2>; + interrupt-parent = <&lsio_gpio2>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; + status = "disabled"; + }; + + reg_mba8x_12v: regulator-mba8x-12v { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_mba8x_12v>; + regulator-name = "MBa8x-V12"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + gpio = <&lsio_gpio1 2 GPIO_ACTIVE_HIGH>; + }; + + reg_mba8x_v3v3: regulator-mba8x-v3v3 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_MB"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_pwm_fan: regulator-pwm-fan { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_regpwmfan>; + regulator-name = "FAN_PWR"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&lsio_gpio2 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_mba8x_12v>; + }; + + reg_usb_phy: regulator-usb-phy { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + regulator-name = "usb-phy-dummy"; + }; + + reg_v1v5_pcie: regulator-v1v5-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_pcie_v1v5>; + regulator-name = "V_1V5_MPCIE"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + vin-supply = <®_mba8x_v3v3>; + enable-active-high; + gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; + + reg_v1v8: regulator-v1v8 { + compatible = "regulator-fixed"; + regulator-name = "MBa8x-V1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_v3v3_pcie: regulator-v3v3-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_pcie_v3v3>; + regulator-name = "V_3V3_MPCIE"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_mba8x_v3v3>; + enable-active-high; + gpio = <&lsio_gpio1 1 GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; + + reg_v3v3_sd: regulator-v3v3-sd { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_v3v3_sd>; + regulator-name = "V3V3_SD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_mba8x_v3v3>; + gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + off-on-delay-us = <200000>; + }; + + reg_vref_v1v8: regulator-vref-v1v8 { + compatible = "regulator-fixed"; + regulator-name = "VREF_V1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * global autoconfigured region for contiguous allocations + * must not exceed memory size and region + */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x96000000 0 0x3c000000>; + linux,cma-default; + }; + + decoder_boot: decoder-boot@84000000 { + reg = <0 0x84000000 0 0x2000000>; + no-map; + }; + + encoder1_boot: encoder1-boot@86000000 { + reg = <0 0x86000000 0 0x200000>; + no-map; + }; + + encoder2_boot: encoder2-boot@86200000 { + reg = <0 0x86200000 0 0x200000>; + no-map; + }; + + decoder_rpc: decoder-rpc@92000000 { + reg = <0 0x92000000 0 0x100000>; + no-map; + }; + + encoder1_rpc: encoder1-rpc@92100000 { + reg = <0 0x92100000 0 0x700000>; + no-map; + }; + + encoder2_rpc: encoder1-rpc@92800000 { + reg = <0 0x92800000 0 0x700000>; + no-map; + }; + }; + + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + model = "tqm-tlv320aic32"; + ssi-controller = <&sai1>; + audio-codec = <&tlv320aic3x04>; + audio-routing = + "IN3_L", "Mic Jack", + "Mic Jack", "Mic Bias", + "IN1_L", "Line In Jack", + "IN1_R", "Line In Jack", + "Line Out Jack", "LOL", + "Line Out Jack", "LOR"; + }; + + sound-hdmi { + compatible = "fsl,imx-audio-hdmi"; + model = "imx-audio-dp"; + audio-cpu = <&sai5>; + hdmi-out; + }; + + thermal-zones { + cpu0-thermal { + trips { + soc_active0_0: trip-active0 { + temperature = <40000>; + hysteresis = <5000>; + type = "active"; + }; + + soc_active0_1: trip-active1 { + temperature = <48000>; + hysteresis = <3000>; + type = "active"; + }; + + soc_active0_2: trip-active2 { + temperature = <60000>; + hysteresis = <10000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + trip = <&soc_active0_0>; + cooling-device = <&fan0 1 1>; + }; + + map2 { + trip = <&soc_active0_1>; + cooling-device = <&fan0 2 2>; + }; + + map3 { + trip = <&soc_active0_2>; + cooling-device = <&fan0 3 3>; + }; + }; + }; + + cpu1-thermal { + trips { + soc_active1_0: trip-active0 { + temperature = <40000>; + hysteresis = <5000>; + type = "active"; + }; + + soc_active1_1: trip-active1 { + temperature = <48000>; + hysteresis = <3000>; + type = "active"; + }; + + soc_active1_2: trip-active2 { + temperature = <60000>; + hysteresis = <10000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + trip = <&soc_active1_0>; + cooling-device = <&fan0 1 1>; + }; + + map2 { + trip = <&soc_active1_1>; + cooling-device = <&fan0 2 2>; + }; + + map3 { + trip = <&soc_active1_2>; + cooling-device = <&fan0 3 3>; + }; + }; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + nvmem-cells = <&fec_mac0>; + nvmem-cell-names = "mac-address"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ethphy0>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + reset-gpios = <&lsio_gpio2 6 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + enet-phy-lane-no-swap; + interrupt-parent = <&lsio_gpio2>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy3>; + nvmem-cells = <&fec_mac1>; + nvmem-cell-names = "mac-address"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy3: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ethphy3>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + reset-gpios = <&lsio_gpio2 4 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + enet-phy-lane-no-swap; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&hsio_phy { + fsl,hsio-cfg = "pciea-pcieb-sata"; + fsl,refclk-pad-mode = "input"; + status = "okay"; +}; + +/* no refclock gating */ +&hsio_refa_clk { + compatible = "fixed-factor-clock"; + clocks = <&pcieclk 0>; + clock-div = <1>; + clock-mult = <1>; + /delete-property/ enable-gpios; +}; + +&hsio_refb_clk { + compatible = "fixed-factor-clock"; + clocks = <&pcieclk 0>; + clock-div = <1>; + clock-mult = <1>; + /delete-property/ enable-gpios; +}; + +&i2c1 { + tlv320aic3x04: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; + clock-names = "mclk"; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + ldoin-supply = <®_mba8x_v3v3>; + iov-supply = <®_v1v8>; + }; + + sensor1: temperature-sensor@1c { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x1c>; + }; + + eeprom2: eeprom@54 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x54>; + pagesize = <16>; + vcc-supply = <®_mba8x_v3v3>; + }; + + pcieclk: clock-generator@68 { + compatible = "renesas,9fgv0441"; + reg = <0x68>; + clocks = <&clk_xtal25>; + #clock-cells = <1>; + }; +}; + +&lpspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>; + cs-gpios = <&lsio_gpio3 5 GPIO_ACTIVE_LOW>, <&lsio_gpio3 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&lpspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi1 &pinctrl_lpspi1_cs>; + cs-gpios = <&lsio_gpio3 24 GPIO_ACTIVE_LOW>, <&lsio_gpio3 25 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&lpspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>; + cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>, <&lsio_gpio3 11 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&lpuart0 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { + /* X62 pin header */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +&lpuart2 { + /* mikroBUS */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "okay"; +}; + +&lsio_gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio2>; + gpio-line-names = "", "", "", "", + "", "PCIE0_DISABLE#", "", ""; + + pcie0-wdisable1-hog { + gpio-hog; + gpios = <5 0>; + output-high; + line-name = "PCIE0_DISABLE#"; + }; + + pcie-clk-pd-hog { + gpio-hog; + gpios = <10 0>; + output-high; + line-name = "PCIE_CLK_PD#"; + }; +}; + +&lsio_pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lsio_pwm3>; + status = "okay"; +}; + +&pciea { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy"; + reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcieb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + phys = <&hsio_phy 1 PHY_TYPE_PCIE 1>; + phy-names = "pcie-phy"; + reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai1_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + status = "okay"; +}; + +&sai5 { + status = "okay"; +}; + +&sai5_lpcg { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&usbphy1 { + phy-3p0-supply = <®_usb_phy>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + over-current-active-low; + dr_mode = "otg"; + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&usbotg3 { + /* over-current disabled by default */ + status = "okay"; +}; + +&usbotg3_cdns3 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbhub>; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb451,8142"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&lsio_gpio2 7 GPIO_ACTIVE_LOW>; + vdd-supply = <®_mba8x_v3v3>; + }; + + hub_3_0: hub@2 { + compatible = "usb451,8140"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&lsio_gpio2 7 GPIO_ACTIVE_LOW>; + vdd-supply = <®_mba8x_v3v3>; + }; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_v3v3_sd>; + no-mmc; + no-sdio; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio>; + + pinctrl_adc0: adc0grp { + fsl,pins = , + ; + }; + + pinctrl_ethphy0: ethphy0grp { + fsl,pins = , + ; + }; + + pinctrl_ethphy3: ethphy3grp { + fsl,pins = ; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins = , + ; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = , + ; + }; + + pinctrl_gpio2: gpio2grp { + fsl,pins = , + ; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = /* GPIO0_05 on X62:26 */ + , + /* GPIO1_14 on X64:21 */ + , + /* GPIO1_15 on X64:23 */ + , + /* GPIO2_17 on X63:37 */ + , + /* GPIO2_21 on X63:39 */ + , + /* GPIO4_12 on X61:24 */ + , + /* GPIO4_11 on X61:26 */ + , + /* GPIO4_10 on X61:28 */ + , + /* GPIO4_09 on X61:30 */ + , + /* GPIO5_23 on X62:24 */ + , + /* GPIO5_24 on X61:15 */ + , + /* GPIO5_25 on X61:17 */ + , + /* GPIO5_26 on X61:19 */ + , + /* GPIO5_27 on X61:21 */ + , + /* GPIO5_28 on X61:23 */ + , + /* GPIO5_29 on X61:25 */ + ; + }; + + pinctrl_gpiokeys: gpiokeysgrp { + fsl,pins = , + ; + }; + + pinctrl_gpioled: gpioledgrp { + fsl,pins = , + ; + }; + + pinctrl_lpspi0_cs: lpspi0csgrp { + fsl,pins = , + ; + }; + + pinctrl_lpspi0: lpspi0grp { + fsl,pins = , + , + ; + }; + + pinctrl_lpspi1_cs: lpspi1csgrp { + fsl,pins = , + ; + }; + + pinctrl_lpspi1: lpspi1grp { + fsl,pins = , + , + ; + }; + + pinctrl_lpspi2: lpspi2grp { + fsl,pins = , + , + ; + }; + + pinctrl_lpspi2_cs: lpspi2sgrp { + fsl,pins = , + ; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_lpuart2: lpuart2grp { + fsl,pins = , + ; + }; + + pinctrl_lsio_pwm3: lsiopwm3grp { + fsl,pins = ; + }; + + pinctrl_pciea: pcieagrp { + fsl,pins = , + , + ; + }; + + pinctrl_pcieb: pciebgrp { + fsl,pins = , + , + ; + }; + + pinctrl_pwmfan: pwmfangrp { + fsl,pins = ; + }; + + pinctrl_reg_mba8x_12v: regmba12vgrp { + fsl,pins = ; + }; + + pinctrl_reg_pcie_v1v5: regpcie1v5grp { + fsl,pins = ; + }; + + pinctrl_reg_pcie_v3v3: regpcie3v3grp { + fsl,pins = ; + }; + + pinctrl_regpwmfan: regpwmfangrp { + fsl,pins = ; + }; + + pinctrl_reg_v3v3_sd: regv3v3sdgrp { + fsl,pins = ; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = , + , + , + , + , + ; + }; + + pinctrl_usbhub: usbhubgrp { + fsl,pins = ; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = , + ; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins = , + ; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi new file mode 100644 index 000000000000..d94605c99991 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi @@ -0,0 +1,318 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2019-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +#include +#include +#include + +#include "imx8qm.dtsi" + +/ { + model = "TQ-Systems i.MX8QM TQMa8QM"; + compatible = "tq,imx8qm-tqma8qm", "fsl,imx8qm"; + + memory@80000000 { + device_type = "memory"; + /* + * DRAM base addr, size : 1024 MiB DRAM + * should be corrected by bootloader + */ + reg = <0x00000000 0x80000000 0 0x40000000>; + }; + + reg_tqma8x_v3v3: regulator-tqma8x-v3v3 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* SW7 controlled by SCU */ + reg_1v8_io1: regulator-v1v8-io1 { + compatible = "regulator-fixed"; + regulator-name = "V_1V8_IO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + /* LDO4 controlled by SCU */ + reg_3v3_emmc: regulator-v3v3-emmc { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_EMMC"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&acm { + status = "okay"; +}; + +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0>; + vref-supply = <®_vref_v1v8>; + status = "okay"; +}; + +/* TQMa8QM only uses industrial grade, reduce trip points accordingly */ +&cpu_alert0 { + temperature = <95000>; +}; + +&cpu_crit0 { + temperature = <100000>; +}; + +&cpu_alert1 { + temperature = <95000>; +}; + +&cpu_crit1 { + temperature = <100000>; +}; + +&gpu_alert0 { + temperature = <95000>; +}; + +&gpu_crit0 { + temperature = <100000>; +}; + +&gpu_alert1 { + temperature = <95000>; +}; + +&gpu_crit1 { + temperature = <100000>; +}; + +&drc_alert0 { + temperature = <95000>; +}; + +&drc_crit0 { + temperature = <100000>; +}; +/* end of temperature grade adjustments */ + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <66000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + vcc-supply = <®_1v8_io1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-1 = <&pinctrl_lpi2c1gpio>; + scl-gpios = <&lsio_gpio0 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&lsio_gpio0 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + se97: temperature-sensor@1b { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x1b>; + }; + + pcf85063: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + quartz-load-femtofarads = <7000>; + }; + + at24c02: eeprom@53 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + read-only; + vcc-supply = <®_tqma8x_v3v3>; + }; + + m24c64: eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + vcc-supply = <®_tqma8x_v3v3>; + }; +}; + +&mu_m0 { + status = "okay"; +}; + +&mu1_m0 { + status = "okay"; +}; + +&mu2_m0 { + status = "okay"; +}; + +&thermal_zones { + pmic0-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; + + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + vmmc-supply = <®_3v3_emmc>; + vqmmc-supply = <®_1v8_io1>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&vpu { + compatible = "nxp,imx8qm-vpu"; + status = "okay"; +}; + +&vpu_core0 { + memory-region = <&decoder_boot>, <&decoder_rpc>; + status = "okay"; +}; + +&vpu_core1 { + memory-region = <&encoder1_boot>, <&encoder1_rpc>; + status = "okay"; +}; + +&vpu_core2 { + memory-region = <&encoder2_boot>, <&encoder2_rpc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = , + ; + }; + + pinctrl_lpi2c1gpio: lpi2c1gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; +}; From 5d20f1ccb3393a2ccb3f3505891066ddff39167a Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Thu, 26 Mar 2026 14:02:22 +0100 Subject: [PATCH 160/665] arm64: dts: imx8qm-tqma8qm-mba8x: Disable Cortex-A72 cluster Due to missing workaround for "ERR050104: Arm/A53: Cache coherency issue" disable the whole Cortex-A72 cluster. Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- .../dts/freescale/imx8qm-tqma8qm-mba8x.dts | 39 ------------------- .../boot/dts/freescale/imx8qm-tqma8qm.dtsi | 13 +++++-- 2 files changed, 10 insertions(+), 42 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm-mba8x.dts b/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm-mba8x.dts index bf972010a88e..ab3b244b684f 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm-mba8x.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm-mba8x.dts @@ -298,45 +298,6 @@ map3 { }; }; }; - - cpu1-thermal { - trips { - soc_active1_0: trip-active0 { - temperature = <40000>; - hysteresis = <5000>; - type = "active"; - }; - - soc_active1_1: trip-active1 { - temperature = <48000>; - hysteresis = <3000>; - type = "active"; - }; - - soc_active1_2: trip-active2 { - temperature = <60000>; - hysteresis = <10000>; - type = "active"; - }; - }; - - cooling-maps { - map1 { - trip = <&soc_active1_0>; - cooling-device = <&fan0 1 1>; - }; - - map2 { - trip = <&soc_active1_1>; - cooling-device = <&fan0 2 2>; - }; - - map3 { - trip = <&soc_active1_2>; - cooling-device = <&fan0 3 3>; - }; - }; - }; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi index d94605c99991..f0e398eb2aad 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi @@ -15,6 +15,13 @@ / { model = "TQ-Systems i.MX8QM TQMa8QM"; compatible = "tq,imx8qm-tqma8qm", "fsl,imx8qm"; + /* Due to missing workaround for ERR050104 */ + cpus { + /delete-node/ cpu-map; + /delete-node/ cpu@100; + /delete-node/ cpu@101; + }; + memory@80000000 { device_type = "memory"; /* @@ -174,6 +181,8 @@ &mu2_m0 { }; &thermal_zones { + /delete-node/ cpu1-thermal; + pmic0-thermal { polling-delay-passive = <250>; polling-delay = <2000>; @@ -199,9 +208,7 @@ map0 { <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; From e11598cbbb4ad9fbc7d355d0ecc4c44e05ac3a77 Mon Sep 17 00:00:00 2001 From: Franz Schnyder Date: Thu, 26 Mar 2026 15:37:04 +0100 Subject: [PATCH 161/665] arm64: dts: freescale: imx95-toradex-smarc: Add SER2 interface The Toradex SMARC iMX95 has four exposed serial interfaces, one of these is SER2, which supports RTS/CTS. Add UART support for SMARC SER2. Signed-off-by: Franz Schnyder Signed-off-by: Frank Li --- .../dts/freescale/imx95-toradex-smarc-dev.dts | 5 +++++ .../boot/dts/freescale/imx95-toradex-smarc.dtsi | 16 ++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc-dev.dts b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc-dev.dts index 5b05f256fd52..7437e523ff63 100644 --- a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc-dev.dts +++ b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc-dev.dts @@ -210,6 +210,11 @@ &lpuart3 { status = "okay"; }; +/* SMARC SER2 */ +&lpuart6 { + status = "okay"; +}; + /* SMARC MDIO, shared between all ethernet ports */ &netc_emdio { status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi index 7a73958f6eec..1d369983cf7d 100644 --- a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi @@ -22,6 +22,7 @@ aliases { rtc1 = &scmi_bbm; serial0 = &lpuart2; serial1 = &lpuart1; + serial2 = &lpuart6; serial3 = &lpuart3; }; @@ -615,6 +616,13 @@ &lpuart3 { pinctrl-0 = <&pinctrl_uart3>; }; +/* SMARC SER2 */ +&lpuart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + uart-has-rtscts; +}; + &mu7 { status = "okay"; }; @@ -1105,6 +1113,14 @@ pinctrl_uart3: uart3grp { ; /* SMARC P141 - SER3_RX */ }; + /* SMARC SER2 */ + pinctrl_uart6: uart6grp { + fsl,pins = , /* SMARC P139 - SER2_CTS# */ + , /* SMARC P138 - SER2_RTS# */ + , /* SMARC P137 - SER2_RX */ + ; /* SMARC P136 - SER2_TX */ + }; + /* On-module eMMC */ pinctrl_usdhc1: usdhc1grp { fsl,pins = , /* SD1_CLK */ From 104a391bb6ff4cbb2bc0fafd34bc1bc06150f355 Mon Sep 17 00:00:00 2001 From: Franz Schnyder Date: Thu, 26 Mar 2026 15:37:05 +0100 Subject: [PATCH 162/665] arm64: dts: freescale: imx95-toradex-smarc: Enable bluetooth on lpuart5 The Toradex SMARC iMX95 uses the MAYA-W260 WiFi/Bluetooth module, which uses the UART interface for Bluetooth. Add UART support to enable bluetooth functionality on the MAYA-W260. Signed-off-by: Franz Schnyder Signed-off-by: Frank Li --- .../dts/freescale/imx95-toradex-smarc.dtsi | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi index 1d369983cf7d..a90edefc5197 100644 --- a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi @@ -616,6 +616,19 @@ &lpuart3 { pinctrl-0 = <&pinctrl_uart3>; }; +/* On-module Bluetooth */ +&lpuart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_uart>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + fw-init-baudrate = <3000000>; + }; +}; + /* SMARC SER2 */ &lpuart6 { pinctrl-names = "default"; @@ -830,6 +843,14 @@ &wdog3 { }; &scmi_iomuxc { + /* On-module Bluetooth, UART pins shared with JTAG */ + pinctrl_bt_uart: btuartgrp { + fsl,pins = , /* WiFI_UART_RXD */ + , /* WiFI_UART_TXD */ + , /* WiFI_UART_RTS# */ + ; /* WiFI_UART_CTS# */ + }; + /* SMARC CAM_MCK */ pinctrl_cam_mck: cammckgrp { fsl,pins = ; /* SMARC S6 - CAM_MCK */ From a05af625aa2c8e3f837c393df8abe11a6b84078d Mon Sep 17 00:00:00 2001 From: Franz Schnyder Date: Thu, 26 Mar 2026 15:37:06 +0100 Subject: [PATCH 163/665] arm64: dts: freescale: imx95-toradex-smarc: Use gpio-hog for WIFI_UART_EN On the Toradex SMARC iMX95, the WiFi UART signals are shared with the JTAG. The WIFI_UART_EN signal is used to select between these two functions. A GPIO hog is used to select the UART function by default. This DT file is going to be used by both Linux and the boot firmware, and the boot firmware will configure the GPIO hog way before the Linux kernel is booted, therefore there is no actual race condition between the Linux kernel BT UART driver and GPIO hog probe. Configure WIFI_UART_EN as a gpio-hog driven high. Signed-off-by: Franz Schnyder Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi index a90edefc5197..8eef26eb0f87 100644 --- a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi @@ -451,6 +451,13 @@ som_gpio_expander_1: gpio@21 { "", "", "SMARC_SDIO_WP"; + + wifi-uart-en-hog { + gpio-hog; + gpios = <12 GPIO_ACTIVE_HIGH>; + line-name = "WIFI_UART_EN"; + output-high; + }; }; embedded-controller@28 { From 1eb192d84674c387d50f926ca5da017d7a158de5 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Fri, 27 Mar 2026 10:08:54 +0100 Subject: [PATCH 164/665] dt-bindings: arm: fsl: add Variscite DART-MX93 Boards Add DT compatible strings for Variscite DART-MX93 SoM and Variscite development carrier Board. Acked-by: Conor Dooley Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 477d78ae729a..534a52a1ea5c 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1616,6 +1616,12 @@ properties: - const: variscite,var-dart-mx91 # Variscite DART-MX91 SOM - const: fsl,imx91 + - description: Variscite DART-MX93 based boards + items: + - const: variscite,var-dart-mx93-sonata # Variscite DART-MX93 on Sonata Development Board + - const: variscite,var-dart-mx93 # Variscite DART-MX93 SOM + - const: fsl,imx93 + - description: Variscite VAR-SOM-MX93 based boards items: - const: variscite,var-som-mx93-symphony From 5d8ca6456690ee511d56f0d7373c9a93c01068c5 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Fri, 27 Mar 2026 10:08:55 +0100 Subject: [PATCH 165/665] arm64: dts: freescale: Add support for Variscite DART-MX93 Add device tree support for the Variscite DART-MX93 system on module. This SOM is designed to be used with various carrier boards. The module includes: - NXP i.MX93 MPU processor - Up to 2GB of LPDDR4 memory - Up to 128GB of eMMC storage memory - Integrated 10/100/1000 Mbps Ethernet Transceiver - Codec audio WM8904 - WIFI6 dual-band 802.11ax/ac/a/b/g/n with optional 802.15.4 and Bluetooth Only SOM-specific peripherals are enabled by default. Carrier board specific interfaces are left disabled to be enabled in the respective carrier board device trees. Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-93/dart-mx93/ Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../boot/dts/freescale/imx93-var-dart.dtsi | 461 ++++++++++++++++++ 1 file changed, 461 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-var-dart.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx93-var-dart.dtsi b/arch/arm64/boot/dts/freescale/imx93-var-dart.dtsi new file mode 100644 index 000000000000..69495bb7fc9f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-var-dart.dtsi @@ -0,0 +1,461 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Common dtsi for Variscite DART-MX93 + * + * Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-93/dart-mx93/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include +#include "imx93.dtsi" + +/ { + model = "Variscite DART-MX93 Module"; + compatible = "variscite,var-dart-mx93", "fsl,imx93"; + + sound-wm8904 { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "wm8904-audio"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <10000>; + reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ + <&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ + }; +}; + +&cm33 { + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu1 0 1>, + <&mu1 1 1>, + <&mu1 3 1>; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; + status = "okay"; +}; + +&eqos { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_eqos>; + pinctrl-1 = <&pinctrl_eqos_sleep>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + snps,clk-csr = <5>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <100000>; + }; + }; +}; + +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "sleep", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3_gpio>; + pinctrl-2 = <&pinctrl_lpi2c3_gpio>; + scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + wm8904: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + #sound-dai-cells = <0>; + clocks = <&clk IMX93_CLK_SAI1_GATE>; + clock-names = "mclk"; + AVDD-supply = <&buck5>; + CPVDD-supply = <&buck5>; + DBVDD-supply = <&buck4>; + DCVDD-supply = <&buck5>; + MICVDD-supply = <&buck5>; + wlf,drc-cfg-names = "default", "peaklimiter", "tradition", + "soft", "music"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 + * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 + * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, + /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, + /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, + /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; + /* DMIC is connected to IN1L */ + wlf,in1l-as-dmicdat1; + }; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <2237500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +/* BT module */ +&lpuart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>, <&pinctrl_bt>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&mu1 { + status = "okay"; +}; + +&mu2 { + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sai1>; + pinctrl-1 = <&pinctrl_sai1_sleep>; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + #sound-dai-cells = <0>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +/* WiFi */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>; + pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>; + mmc-pwrseq = <&wifi_pwrseq>; + keep-power-in-suspend; + bus-width = <4>; + non-removable; + wakeup-source; + status = "okay"; +}; + +&iomuxc { + pinctrl_bt: btgrp { + fsl,pins = < + MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + MX93_PAD_UART2_TXD__GPIO1_IO07 0x51e + >; + }; + + pinctrl_eqos_sleep: eqos-sleepgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e + MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e + MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e + MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e + MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e + MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e + MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e + MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e + MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e + MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e + MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e + MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e + MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e + MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c3_gpio: lpi2c3gpiogrp { + fsl,pins = < + MX93_PAD_GPIO_IO28__GPIO2_IO28 0x40000b9e + MX93_PAD_GPIO_IO29__GPIO2_IO29 0x40000b9e + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e + MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e + MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e + MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e + MX93_PAD_I2C2_SDA__SAI1_RX_BCLK 0x31e + MX93_PAD_I2C2_SCL__SAI1_RX_SYNC 0x31e + MX93_PAD_UART2_RXD__SAI1_MCLK 0x31e + >; + }; + + pinctrl_sai1_sleep: sai1-sleepgrp { + fsl,pins = < + MX93_PAD_SAI1_TXC__GPIO1_IO12 0x31e + MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x31e + MX93_PAD_SAI1_TXD0__GPIO1_IO13 0x31e + MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x31e + MX93_PAD_UART2_RXD__GPIO1_IO06 0x31e + MX93_PAD_I2C2_SDA__GPIO1_IO03 0x31e + MX93_PAD_I2C2_SCL__GPIO1_IO02 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX93_PAD_DAP_TDI__LPUART5_RX 0x31e + MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 + MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582 + MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382 + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382 + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382 + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382 + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e + MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe + MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe + >; + }; + + pinctrl_usdhc3_sleep: usdhc3-sleepgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__GPIO3_IO20 0x400 + MX93_PAD_SD3_CMD__GPIO3_IO21 0x400 + MX93_PAD_SD3_DATA0__GPIO3_IO22 0x400 + MX93_PAD_SD3_DATA1__GPIO3_IO23 0x400 + MX93_PAD_SD3_DATA2__GPIO3_IO24 0x400 + MX93_PAD_SD3_DATA3__GPIO3_IO25 0x400 + >; + }; + + pinctrl_usdhc3_wlan: usdhc3wlangrp { + fsl,pins = < + MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x51e + >; + }; +}; From 3bfec2d4747452e130f25e8422c59a1415aca815 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Fri, 27 Mar 2026 10:08:56 +0100 Subject: [PATCH 166/665] arm64: dts: imx93-var-dart: Add support for Variscite Sonata board Add device tree support for the Variscite Sonata carrier board with the DART-MX93 system on module. The Sonata board includes - uSD Card support - USB ports and OTG - Additional Gigabit Ethernet interface - Uart, SPI and I2C interfaces - GPIO Expanders - RTC module - TPM module - CAN peripherals Link: https://variscite.com/carrier-boards/sonata-board/ Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 2 +- .../dts/freescale/imx93-var-dart-sonata.dts | 654 ++++++++++++++++++ 2 files changed, 655 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/freescale/imx93-var-dart-sonata.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 5dafb1b5d56f..12ae83304aa8 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -500,7 +500,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtb imx93-tqma9352-mba93xxla-mini-ezurio-wlan-dtbs += imx93-tqma9352-mba93xxla-mini.dtb imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtbo dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtb - +dtb-$(CONFIG_ARCH_MXC) += imx93-var-dart-sonata.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx93w-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx943-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx93-var-dart-sonata.dts b/arch/arm64/boot/dts/freescale/imx93-var-dart-sonata.dts new file mode 100644 index 000000000000..5513d3b148a2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-var-dart-sonata.dts @@ -0,0 +1,654 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Variscite Sonata carrier board for DART-MX93 + * + * Link: https://variscite.com/carrier-boards/sonata-board/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include +#include "imx93-var-dart.dtsi" + +/ { + model = "Variscite DART-MX93 on Sonata-Board"; + compatible = "variscite,var-dart-mx93-sonata", + "variscite,var-dart-mx93", + "fsl,imx93"; + + aliases { + ethernet0 = &eqos; + ethernet1 = &fec; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + i2c3 = &lpi2c4; + i2c4 = &lpi2c5; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + serial5 = &lpuart6; + serial6 = &lpuart7; + }; + + chosen { + stdout-path = &lpuart1; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-home { + label = "Home"; + linux,code = ; + gpios = <&pca6408_1 4 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-up { + label = "Up"; + linux,code = ; + gpios = <&pca6408_1 5 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-down { + label = "Down"; + linux,code = ; + gpios = <&pca6408_1 6 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-back { + label = "Back"; + linux,code = ; + gpios = <&pca6408_1 7 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds_gpio>; + + led-emmc { + gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + label = "eMMC"; + linux,default-trigger = "mmc0"; + }; + }; + + clk40m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + clock-output-names = "can_osc"; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + }; + + reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VDD_SD2_3V3"; + off-on-delay-us = <20000>; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ethosu_mem: ethosu-region@88000000 { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 0x88000000 0x0 0x8000000>; + }; + + vdev0vring0: vdev0vring0@87ee0000 { + reg = <0 0x87ee0000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@87ee8000 { + reg = <0 0x87ee8000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@87ef0000 { + reg = <0 0x87ef0000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@87ef8000 { + reg = <0 0x87ef8000 0 0x8000>; + no-map; + }; + + rsc_table: rsc-table@2021e000 { + reg = <0 0x2021e000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@87f00000 { + compatible = "shared-dma-pool"; + reg = <0 0x87f00000 0 0x100000>; + no-map; + }; + + ele_reserved: ele-reserved@87de0000 { + compatible = "shared-dma-pool"; + reg = <0 0x87de0000 0 0x100000>; + no-map; + }; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +/* Use external instead of internal RTC */ +&bbnsm_rtc { + status = "disabled"; +}; + +&eqos { + mdio { + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-assert-us = <15000>; + reset-deassert-us = <100000>; + reset-gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; + }; + }; +}; + +ðphy0 { + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; +}; + +&fec { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec>; + pinctrl-1 = <&pinctrl_fec_sleep>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&lpi2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-1 = <&pinctrl_lpi2c1_gpio>; + pinctrl-2 = <&pinctrl_lpi2c1_gpio>; + pinctrl-names = "default", "sleep", "gpio"; + scl-gpios = <&gpio1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pca9534: gpio@22 { + compatible = "nxp,pca9534"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + }; + + /* Capacitive touch controller */ + ft5x06_ts: touchscreen@38 { + compatible = "edt,edt-ft5206"; + reg = <0x38>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + pinctrl-0 = <&pinctrl_captouch>; + pinctrl-names = "default"; + reset-gpios = <&pca6408_2 4 GPIO_ACTIVE_LOW>; + touchscreen-inverted-x; + touchscreen-inverted-y; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + wakeup-source; + }; + + /* USB Type-C Controller */ + typec@3d { + compatible = "nxp,ptn5150"; + reg = <0x3d>; + interrupt-parent = <&gpio4>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&pinctrl_extcon>; + pinctrl-names = "default"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + interrupt-parent = <&gpio2>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + wakeup-source; + }; +}; + +&lpi2c5 { + clock-frequency = <400000>; + pinctrl-names = "default", "sleep", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c5>; + pinctrl-1 = <&pinctrl_lpi2c5_gpio>; + pinctrl-2 = <&pinctrl_lpi2c5_gpio>; + scl-gpios = <&gpio2 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&lpi2c7 { + clock-frequency = <400000>; + pinctrl-names = "default", "sleep", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c7>; + pinctrl-1 = <&pinctrl_lpi2c7_gpio>; + pinctrl-2 = <&pinctrl_lpi2c7_gpio>; + scl-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pca6408_1: gpio@20 { + compatible = "nxp,pcal6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + }; + + pca6408_2: gpio@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + }; + + st33ktpm2xi2c: tpm@2e { + compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + }; +}; + +&lpspi8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi8>; + cs-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + status = "okay"; + + /* CAN controller */ + can0: can@0 { + compatible = "microchip,mcp251xfd"; + reg = <0>; + clocks = <&clk40m>; + interrupt-parent = <&gpio2>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can>; + spi-max-frequency = <1000000>; + }; +}; + +/* Console (J10) */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* Header (J12.4, J12.6) */ +&lpuart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + status = "okay"; +}; + +/* Header (J12.11, J12.13) */ +&lpuart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + status = "okay"; +}; + +&tpm3 { + pinctrl-0 = <&pinctrl_tpm3>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +/* SD */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + no-sdio; + no-mmc; + status = "okay"; +}; + +&wdog3 { + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_can: cangrp { + fsl,pins = < + MX93_PAD_GPIO_IO03__GPIO2_IO03 0x31e + >; + }; + + pinctrl_captouch: captouchgrp { + fsl,pins = < + MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + >; + }; + + pinctrl_extcon: extcongrp { + fsl,pins = < + MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x31e + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x37e + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_fec_sleep: fecsleepgrp { + fsl,pins = < + MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e + MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e + MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e + MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e + MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e + MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e + MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e + MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e + MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e + MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e + MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e + MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX93_PAD_PDM_CLK__CAN1_TX 0x139e + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* GPIO Expanders shared IRQ */ + MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e + >; + }; + + pinctrl_leds_gpio: ledgrp { + fsl,pins = < + MX93_PAD_GPIO_IO11__GPIO2_IO11 0x31e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c1_gpio: lpi2c1-gpiogrp { + fsl,pins = < + MX93_PAD_I2C1_SCL__GPIO1_IO00 0x31e + MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e + >; + }; + + pinctrl_lpi2c5: lpi2c5grp { + fsl,pins = < + MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e + MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c5_gpio: lpi2c5-gpiogrp { + fsl,pins = < + MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e + MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e + >; + }; + + pinctrl_lpi2c7: lpi2c7grp { + fsl,pins = < + MX93_PAD_GPIO_IO07__LPI2C7_SCL 0x40000b9e + MX93_PAD_GPIO_IO06__LPI2C7_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c7_gpio: lpi2c7-gpiogrp { + fsl,pins = < + MX93_PAD_GPIO_IO07__GPIO2_IO07 0x31e + MX93_PAD_GPIO_IO06__GPIO2_IO06 0x31e + >; + }; + + pinctrl_lpspi8: lpspi8grp { + fsl,pins = < + MX93_PAD_GPIO_IO00__GPIO2_IO00 0x31e + MX93_PAD_GPIO_IO01__GPIO2_IO01 0x31e + MX93_PAD_GPIO_IO12__GPIO2_IO12 0x31e + MX93_PAD_GPIO_IO13__LPSPI8_SIN 0x31e + MX93_PAD_GPIO_IO14__LPSPI8_SOUT 0x31e + MX93_PAD_GPIO_IO15__LPSPI8_SCK 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x31e + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX93_PAD_GPIO_IO02__GPIO2_IO02 0x31e + >; + }; + + pinctrl_tpm3: tpm3grp { + fsl,pins = < + MX93_PAD_GPIO_IO24__TPM3_CH3 0x51e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX93_PAD_GPIO_IO05__LPUART6_RX 0x31e + MX93_PAD_GPIO_IO04__LPUART6_TX 0x31e + >; + }; + + pinctrl_uart7: uart7grp { + fsl,pins = < + MX93_PAD_GPIO_IO09__LPUART7_RX 0x31e + MX93_PAD_GPIO_IO08__LPUART7_TX 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 + MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; +}; From 895e7756cdc1ba6467eb37eba31c1358243f6ad9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Apr 2026 08:38:11 +0200 Subject: [PATCH 167/665] arm64: dts: imx8mn-vhip4-evalboard-v1: Correct interrupt flags GPIO_ACTIVE_x flags are not correct in the context of interrupt flags. These are simple defines so they could be used in DTS but they will not have the same meaning: 1. GPIO_ACTIVE_HIGH = 0 => IRQ_TYPE_NONE 2. GPIO_ACTIVE_LOW = 1 => IRQ_TYPE_EDGE_RISING Correct the interrupt flags, assuming the author of the code wanted the same logical behavior behind the name "ACTIVE_xxx", this is: ACTIVE_LOW => IRQ_TYPE_LEVEL_LOW Fixes: 5eb7405db99b ("arm64: dts: imx8mn: Add ifm VHIP4 EvalBoard v1 and v2") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Marek Vasut Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1.dts b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1.dts index 5f37065bf43f..a8f7c226a61f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1.dts @@ -112,7 +112,7 @@ &i2c3 { &ifm_pmic { interrupt-parent = <&gpio2>; - interrupts = <0 GPIO_ACTIVE_LOW>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; }; &iomuxc { From 7263f1acdd33169e1558064ee9a98758921f3bec Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Apr 2026 08:38:12 +0200 Subject: [PATCH 168/665] arm64: dts: imx8mn-vhip4-evalboard-v2: Correct interrupt flags GPIO_ACTIVE_x flags are not correct in the context of interrupt flags. These are simple defines so they could be used in DTS but they will not have the same meaning: 1. GPIO_ACTIVE_HIGH = 0 => IRQ_TYPE_NONE 2. GPIO_ACTIVE_LOW = 1 => IRQ_TYPE_EDGE_RISING Correct the interrupt flags, assuming the author of the code wanted the same logical behavior behind the name "ACTIVE_xxx", this is: ACTIVE_LOW => IRQ_TYPE_LEVEL_LOW Fixes: 5eb7405db99b ("arm64: dts: imx8mn: Add ifm VHIP4 EvalBoard v1 and v2") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Marek Vasut Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2.dts b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2.dts index 4dadfb7f78de..43fd4d0041ef 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2.dts @@ -99,7 +99,7 @@ &i2c3 { &ifm_pmic { interrupt-parent = <&gpio5>; - interrupts = <17 GPIO_ACTIVE_LOW>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; }; &iomuxc { From eb27f9b9a4b2965f8d497a3c565cfbc2473c184b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Apr 2026 08:38:13 +0200 Subject: [PATCH 169/665] arm64: dts: imx8mp-ab2: Correct interrupt flags GPIO_ACTIVE_x flags are not correct in the context of interrupt flags. These are simple defines so they could be used in DTS but they will not have the same meaning: 1. GPIO_ACTIVE_HIGH = 0 => IRQ_TYPE_NONE 2. GPIO_ACTIVE_LOW = 1 => IRQ_TYPE_EDGE_RISING Correct the interrupt flags, assuming the author of the code wanted the same logical behavior behind the name "ACTIVE_xxx", this is: ACTIVE_LOW => IRQ_TYPE_LEVEL_LOW Fixes: bf68c18150ef ("arm64: dts: imx8mp-ab2: add support for NXP i.MX8MP audio board (version 2)") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Shengjiu Wang Reviewed-by: Daniel Baluta Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-ab2.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts b/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts index dbbc0df0e3d1..443e4fd5b9bf 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts @@ -281,7 +281,7 @@ pca9450: pmic@25 { compatible = "nxp,pca9450c"; reg = <0x25>; interrupt-parent = <&gpio1>; - interrupts = <3 GPIO_ACTIVE_LOW>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; pinctrl-0 = <&pinctrl_pmic>; regulators { From e556f564a04fb6dd37887b5d098e2a0145f2bc9d Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Thu, 2 Apr 2026 20:36:26 +0200 Subject: [PATCH 170/665] arm64: dts: imx8mp-phyboard-pollux: Add HDMI support The PHYTEC phyBOARD Pollux comes with a HDMI port on the base board. Add the required device-tree nodes to enable support for it, including both the video and the audio paths. Signed-off-by: Paul Kocialkowski Signed-off-by: Frank Li --- .../freescale/imx8mp-phyboard-pollux-rdk.dts | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts index 0fe52c73fc8f..4efdc6bdfe12 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -38,6 +38,18 @@ fan0: fan { #cooling-cells = <2>; }; + hdmi-connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + }; + panel_lvds1: panel-lvds1 { /* compatible panel in overlay */ backlight = <&backlight_lvds1>; @@ -126,6 +138,13 @@ reg_vcc_1v8_exp_con: regulator-vcc-1v8 { regulator-name = "VCC_1V8_EXP_CON"; }; + sound-hdmi { + compatible = "fsl,imx-audio-hdmi"; + model = "audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + }; + thermal-zones { soc-thermal { trips { @@ -146,6 +165,10 @@ map1 { }; }; +&aud2htx { + status = "okay"; +}; + /* TPM */ &ecspi1 { #address-cells = <1>; @@ -201,6 +224,32 @@ &flexcan2 { status = "okay"; }; +&hdmi_pai { + status = "okay"; +}; + +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + status = "okay"; + + ports { + port@1 { + hdmi_tx_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + &i2c2 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; @@ -244,6 +293,10 @@ &i2c3 { scl-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; }; +&lcdif3 { + status = "okay"; +}; + &ldb_lvds_ch1 { remote-endpoint = <&panel1_in>; }; @@ -444,6 +497,15 @@ MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x154 >; }; + pinctrl_hdmi: hdmigrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c3 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c3 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x19 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x19 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 From aa907ee010e396c0c0d31d60495ace6e531ceec9 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 3 Apr 2026 17:57:01 +0800 Subject: [PATCH 171/665] Revert "arm64: dts: imx8mm-kontron: Add support for reading SD_VSEL signal" This reverts commit 8472751c4d96b558d60d0f6aede6b24b64bcb3c9. The board uses SDHC VSELECT to automatically switch between 1.8v and 3.3v. It does not use GPIO to control the PMIC SD_VSEL signal. The original commit intends to read back SD_VSEL value from GPIO, but it is wrong. When MUX is configured as SDHC VSELECT, it is impossible to read back the value from GPIO controller. Setting SION could only enable the input path for the mux function. It could not redirect the input to GPIO. And value "0x40000d0" is wrong, SION is BIT30, not BIT26. Fixes: 8472751c4d96b ("arm64: dts: imx8mm-kontron: Add support for reading SD_VSEL signal") Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts | 10 +++------- .../arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi | 7 +++---- 2 files changed, 6 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts index e756fe5db56b..dd59af0ebaae 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts @@ -254,10 +254,6 @@ &pwm2 { status = "okay"; }; -®_nvcc_sd { - sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; -}; - &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; @@ -466,7 +462,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 >; }; @@ -479,7 +475,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 >; }; @@ -492,7 +488,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 >; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi index 96987910609f..4fb13d8ecfd4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi @@ -342,7 +342,6 @@ reg_nvcc_sd: LDO5 { regulator-name = "NVCC_SD (LDO5)"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; - sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; }; }; }; @@ -795,7 +794,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 /* SDIO_A_D1 */ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 /* SDIO_A_D2 */ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 /* SDIO_A_D3 */ MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000090 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 >; }; @@ -808,7 +807,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 /* SDIO_A_D1 */ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 /* SDIO_A_D2 */ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 /* SDIO_A_D3 */ MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000090 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 >; }; @@ -821,7 +820,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 /* SDIO_A_D1 */ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 /* SDIO_A_D2 */ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 /* SDIO_A_D3 */ MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000090 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 >; }; From 22465a195af370ed6311be3adee479fb7c683685 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 3 Apr 2026 17:57:02 +0800 Subject: [PATCH 172/665] Revert "arm64: dts: imx8mp-kontron: Add support for reading SD_VSEL signal" This reverts commit 39e4189d9d63a0b6fc15458ce0136e99ecdfb1b8. The board uses SDHC VSELECT to automatically switch between 1.8v and 3.3v. It does not use GPIO to control the PMIC SD_VSEL signal. The original commit intends to read back SD_VSEL value from GPIO, but it is wrong. When MUX is configured as SDHC VSELECT, it is impossible to read back the value from GPIO controller. Setting SION could only enable the input path for the mux function. It could not redirect the input to GPIO. Fixes: 39e4189d9d63a ("arm64: dts: imx8mp-kontron: Add support for reading SD_VSEL signal") Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi index bc1a261bb000..ea69c639b30b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi @@ -311,7 +311,6 @@ reg_nvcc_sd: LDO5 { regulator-name = "NVCC_SD (LDO5)"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; - sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; }; }; }; @@ -815,7 +814,7 @@ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 /* SDIO_A_D0 */ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 /* SDIO_A_D1 */ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 /* SDIO_A_D2 */ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 /* SDIO_A_D3 */ - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x400001d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x1d0 >; }; @@ -827,7 +826,7 @@ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 /* SDIO_A_D0 */ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 /* SDIO_A_D1 */ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 /* SDIO_A_D2 */ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 /* SDIO_A_D3 */ - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x400001d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x1d0 >; }; @@ -839,7 +838,7 @@ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 /* SDIO_A_D0 */ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 /* SDIO_A_D1 */ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 /* SDIO_A_D2 */ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 /* SDIO_A_D3 */ - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x400001d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x1d0 >; }; From 05bee22e1af95f9de50b6873690952808c0ae54b Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Wed, 8 Apr 2026 19:39:44 +0200 Subject: [PATCH 173/665] dt-bindings: arm: fsl: add Variscite VAR-SOM-MX91 Boards Add DT compatible strings for Variscite VAR-SOM-MX91 SoM and Symphony development carrier Board. Signed-off-by: Stefano Radaelli Acked-by: Krzysztof Kozlowski Reviewed-by: Peng Fan Signed-off-by: Frank Li --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 534a52a1ea5c..5911b41e7a32 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1616,6 +1616,12 @@ properties: - const: variscite,var-dart-mx91 # Variscite DART-MX91 SOM - const: fsl,imx91 + - description: Variscite VAR-SOM-MX91 based boards + items: + - const: variscite,var-som-mx91-symphony # Variscite VAR-SOM-MX91 on Symphony + - const: variscite,var-som-mx91 # Variscite VAR-SOM-MX91 + - const: fsl,imx91 + - description: Variscite DART-MX93 based boards items: - const: variscite,var-dart-mx93-sonata # Variscite DART-MX93 on Sonata Development Board From 92e5a1654ebcaa5d03f26e924932ad954207f9d1 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Wed, 8 Apr 2026 19:39:45 +0200 Subject: [PATCH 174/665] arm64: dts: freescale: Add support for Variscite VAR-SOM-MX91 Add device tree support for the Variscite VAR-SOM-MX91 system on module. This SOM is designed to be used with various carrier boards. The module includes: - NXP i.MX91 MPU processor - Up to 2GB of LPDDR4 memory - Up to 128GB of eMMC storage memory - Integrated 10/100/1000 Mbps Ethernet Transceiver - Codec audio WM8904 - WIFI6 dual-band 802.11ax/ac/a/b/g/n with optional 802.15.4 and Bluetooth Only SOM-specific peripherals are enabled by default. Carrier board specific interfaces are left disabled to be enabled in the respective carrier board device trees. Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-91/var-som-mx91/ Signed-off-by: Stefano Radaelli Reviewed-by: Peng Fan Signed-off-by: Frank Li --- .../boot/dts/freescale/imx91-var-som.dtsi | 456 ++++++++++++++++++ 1 file changed, 456 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx91-var-som.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx91-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx91-var-som.dtsi new file mode 100644 index 000000000000..b30a0d8a81ba --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-var-som.dtsi @@ -0,0 +1,456 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Common dtsi for Variscite VAR-SOM-MX91 + * + * Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-91/var-som-mx91/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include "imx91.dtsi" + +/{ + model = "Variscite VAR-SOM-MX91 module"; + compatible = "variscite,var-som-mx91", "fsl,imx91"; + + usdhc3_pwrseq: mmc-pwrseq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <10000>; + reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ + <&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,name = "wm8904-audio"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + simple-audio-card,mclk-fs = <256>; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + }; +}; + +&eqos { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_eqos>; + pinctrl-1 = <&pinctrl_eqos_sleep>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + snps,clk-csr = <5>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + eee-broken-1000t; + reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + reset-assert-us = <15000>; + reset-deassert-us = <100000>; + }; + }; +}; + +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "sleep", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3_gpio>; + pinctrl-2 = <&pinctrl_lpi2c3_gpio>; + scl-gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <2237500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + wm8904: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + #sound-dai-cells = <0>; + clocks = <&clk IMX93_CLK_SAI1_GATE>; + clock-names = "mclk"; + AVDD-supply = <&buck5>; + CPVDD-supply = <&buck5>; + DBVDD-supply = <&buck4>; + DCVDD-supply = <&buck5>; + MICVDD-supply = <&buck5>; + wlf,drc-cfg-names = "default", "peaklimiter", "tradition", + "soft", "music"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 + * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 + * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, + /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, + /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, + /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; + }; +}; + +&lpspi8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi8>; + cs-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* BT module */ +&lpuart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart5>, <&pinctrl_bluetooth>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&sai1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sai1>; + pinctrl-1 = <&pinctrl_sai1_sleep>; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +/* WiFi */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>; + pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>; + bus-width = <4>; + keep-power-in-suspend; + mmc-pwrseq = <&usdhc3_pwrseq>; + non-removable; + wakeup-source; + status = "okay"; +}; + +&iomuxc { + pinctrl_bluetooth: bluetoothgrp { + fsl,pins = < + MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x51e + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e + MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe + MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e + MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe + MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + MX91_PAD_UART2_TXD__GPIO1_IO7 0x51e + >; + }; + + pinctrl_eqos_sleep: eqos-sleepgrp { + fsl,pins = < + MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e + MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e + MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e + MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e + MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e + MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e + MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e + MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e + MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e + MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e + MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e + MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e + MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e + MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c3_gpio: lpi2c3-gpiogrp { + fsl,pins = < + MX91_PAD_GPIO_IO28__GPIO2_IO28 0x40000b9e + MX91_PAD_GPIO_IO29__GPIO2_IO29 0x40000b9e + >; + }; + + pinctrl_lpspi8: lpspi8grp { + fsl,pins = < + MX91_PAD_GPIO_IO12__GPIO2_IO12 0x31e + MX91_PAD_GPIO_IO13__LPSPI8_SIN 0x31e + MX91_PAD_GPIO_IO14__LPSPI8_SOUT 0x31e + MX91_PAD_GPIO_IO15__LPSPI8_SCK 0x31e + >; + }; + + pinctrl_lpuart5: lpuart5grp { + fsl,pins = < + MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX91_PAD_DAP_TDI__LPUART5_RX 0x31e + MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e + MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e + MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x31e + MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x31e + MX91_PAD_I2C2_SDA__SAI1_RX_BCLK 0x31e + MX91_PAD_I2C2_SCL__SAI1_RX_SYNC 0x31e + MX91_PAD_UART2_RXD__SAI1_MCLK 0x31e + >; + }; + + pinctrl_sai1_sleep: sai1-sleepgrp { + fsl,pins = < + MX91_PAD_SAI1_TXC__GPIO1_IO12 0x31e + MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x31e + MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x31e + MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x31e + MX91_PAD_UART2_RXD__GPIO1_IO6 0x31e + MX91_PAD_I2C2_SDA__GPIO1_IO3 0x31e + MX91_PAD_I2C2_SCL__GPIO1_IO2 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582 + MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382 + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382 + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382 + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382 + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382 + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382 + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382 + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382 + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382 + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e + MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x1582 + MX91_PAD_SD3_CMD__USDHC3_CMD 0x1382 + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x1382 + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x1382 + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x1382 + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x1382 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x158e + MX91_PAD_SD3_CMD__USDHC3_CMD 0x138e + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x15fe + MX91_PAD_SD3_CMD__USDHC3_CMD 0x13fe + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe + >; + }; + + pinctrl_usdhc3_sleep: usdhc3-sleepgrp { + fsl,pins = < + MX91_PAD_SD3_CLK__GPIO3_IO20 0x31e + MX91_PAD_SD3_CMD__GPIO3_IO21 0x31e + MX91_PAD_SD3_DATA0__GPIO3_IO22 0x31e + MX91_PAD_SD3_DATA1__GPIO3_IO23 0x31e + MX91_PAD_SD3_DATA2__GPIO3_IO24 0x31e + MX91_PAD_SD3_DATA3__GPIO3_IO25 0x31e + >; + }; + + pinctrl_usdhc3_wlan: usdhc3-wlangrp { + fsl,pins = < + MX91_PAD_ENET2_MDC__GPIO4_IO14 0x51e + MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x51e + >; + }; +}; From b3292129dcef91ce4a4df878a9286a39fed0c811 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Wed, 8 Apr 2026 19:39:46 +0200 Subject: [PATCH 175/665] arm64: dts: imx91-var-som: Add support for Variscite Symphony board Add device tree support for the Variscite Symphony carrier board with the VAR-SOM-MX91 system on module. The Symphony board includes - uSD Card support - USB ports and OTG - Additional Gigabit Ethernet interface - Uart, ADC and I2C interfaces - GPIO Expanders - RTC module - TPM module - CAN peripheral Link: https://variscite.com/carrier-boards/symphony-board/ Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx91-var-som-symphony.dts | 527 ++++++++++++++++++ 2 files changed, 528 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx91-var-som-symphony.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 12ae83304aa8..6c4a0a6a7eba 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -451,6 +451,7 @@ imx91-tqma9131-mba91xxca-rgb-cdtech-dc44-dtbs := imx91-tqma9131-mba91xxca.dtb im dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca-rgb-cdtech-dc44.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-var-dart-sonata.dtb +dtb-$(CONFIG_ARCH_MXC) += imx91-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb diff --git a/arch/arm64/boot/dts/freescale/imx91-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx91-var-som-symphony.dts new file mode 100644 index 000000000000..ac9fed58357e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-var-som-symphony.dts @@ -0,0 +1,527 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Variscite Symphony carrier board for VAR-SOM-MX91 + * + * Link: https://variscite.com/carrier-boards/symphony-board/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include +#include "imx91-var-som.dtsi" + +/{ + model = "Variscite VAR-SOM-MX91 on Symphony evaluation board"; + compatible = "variscite,var-som-mx91-symphony", + "variscite,var-som-mx91", "fsl,imx91"; + + aliases { + ethernet0 = &eqos; + ethernet1 = &fec; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &pca9534; + gpio5 = &pca6408; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + }; + + chosen { + stdout-path = &lpuart1; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-back { + label = "Back"; + gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-home { + label = "Home"; + gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-menu { + label = "Menu"; + gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-hearthbeat { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + /* + * Needed only for Symphony <= v1.5 + */ + reg_fec_phy: regulator-fec-phy { + compatible = "regulator-fixed"; + regulator-name = "fec-phy"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <20000>; + gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_rgb_sel: regulator-rgb-enable { + compatible = "regulator-fixed"; + regulator-name = "RGBSEL"; + gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6408 6 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; + enable-active-high; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + ele_reserved: ele-reserved@87de0000 { + compatible = "shared-dma-pool"; + reg = <0 0x87de0000 0 0x100000>; + no-map; + }; + + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x40000000>; + reusable; + size = <0 0x10000000>; + linux,cma-default; + }; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +/* Use external instead of internal RTC*/ +&bbnsm_rtc { + status = "disabled"; +}; + +&eqos { + mdio { + ethphy1: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <5>; + eee-broken-1000t; + reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <20000>; + vddio-supply = <&vddio1>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; + + vddio1: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; +}; + +ðphy0 { + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; +}; + +&fec { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec>; + pinctrl-1 = <&pinctrl_fec_sleep>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + phy-supply = <®_fec_phy>; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&lpi2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "sleep", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-1 = <&pinctrl_lpi2c1_gpio>; + pinctrl-2 = <&pinctrl_lpi2c1_gpio>; + scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pca9534: gpio@20 { + compatible = "nxp,pca9534"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca9534>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; + + pca6408: gpio@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca6408>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio2>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + vcc-supply = <®_rgb_sel>; + wakeup-source; + + tpm-enable-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "tpm_en"; + }; + }; + + /* USB Type-C Controller */ + ptn5150: typec@3d { + compatible = "nxp,ptn5150"; + reg = <0x3d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ptn5150>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_NONE>; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + + st33ktpm2xi2c: tpm@2e { + compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + }; + + /* Capacitive touch controller */ + ft5x06_ts: touchscreen@38 { + compatible = "edt,edt-ft5206"; + reg = <0x38>; + interrupt-parent = <&pca6408>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + wakeup-source; + }; + + /* DS1337 RTC module */ + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; +}; + +/* pins conflict */ +&lpspi8 { + status = "disabled"; +}; + +/* Console */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&tpm4 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_tpm4>; + pinctrl-1 = <&pinctrl_tpm4_sleep>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +/* SD */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; + bus-width = <4>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +/* Watchdog */ +&wdog3 { + status = "okay"; +}; + +&iomuxc { + pinctrl_fec: fecgrp { + fsl,pins = < + MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x57e + MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x57e + MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x57e + MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x57e + MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x5fe + MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e + MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x57e + MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x57e + MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x57e + MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x57e + MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x5fe + MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_fec_sleep: fecsleepgrp { + fsl,pins = < + MX91_PAD_ENET2_RD0__GPIO4_IO24 0x51e + MX91_PAD_ENET2_RD1__GPIO4_IO25 0x51e + MX91_PAD_ENET2_RD2__GPIO4_IO26 0x51e + MX91_PAD_ENET2_RD3__GPIO4_IO27 0x51e + MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e + MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e + MX91_PAD_ENET2_TD0__GPIO4_IO19 0x51e + MX91_PAD_ENET2_TD1__GPIO4_IO18 0x51e + MX91_PAD_ENET2_TD2__GPIO4_IO17 0x51e + MX91_PAD_ENET2_TD3__GPIO4_IO16 0x51e + MX91_PAD_ENET2_TXC__GPIO4_IO21 0x51e + MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX91_PAD_PDM_CLK__CAN1_TX 0x139e + MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c1_gpio: lpi2c1gpiogrp { + fsl,pins = < + MX91_PAD_I2C1_SCL__GPIO1_IO0 0x31e + MX91_PAD_I2C1_SDA__GPIO1_IO1 0x31e + >; + }; + + pinctrl_pca6408: pca6408grp { + fsl,pins = < + MX91_PAD_GPIO_IO04__GPIO2_IO4 0x31e + >; + }; + + pinctrl_pca9534: pca9534grp { + fsl,pins = < + MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x31e + >; + }; + + pinctrl_ptn5150: ptn5150grp { + fsl,pins = < + MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX91_PAD_UART1_RXD__LPUART1_RX 0x31e + MX91_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_tpm4: tpm4grp { + fsl,pins = < + MX91_PAD_GPIO_IO05__TPM4_CH0 0x51e + >; + }; + + pinctrl_tpm4_sleep: tpm4sleepgrp { + fsl,pins = < + MX91_PAD_GPIO_IO05__GPIO2_IO5 0x51e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582 + MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382 + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382 + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382 + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382 + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382 + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_sleep: usdhc2sleep-grp { + fsl,pins = < + MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e + MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e + MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e + MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e + MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e + MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e + MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e + >; + }; + + pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleep-grp { + fsl,pins = < + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e + >; + }; +}; From 3ae6b04598bb3ea5ef859d96b37bb47ca395d3c3 Mon Sep 17 00:00:00 2001 From: Guangliu Ding Date: Tue, 7 Apr 2026 11:15:03 +0800 Subject: [PATCH 176/665] arm64: dts: imx952: Describe Mali G310 GPU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Support Mali G310 GPU on i.MX952 board. Describe this GPU in the DT. Include dummy GPU voltage regulator and OPP tables. A hardware GPU auto clock‑gating mechanism has been introduced, enabling GPUMIX to automatically manage the GPU clock. This improves overall response time. Signed-off-by: Guangliu Ding Reviewed-by: Liviu Dudau Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx952.dtsi | 36 +++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx952.dtsi b/arch/arm64/boot/dts/freescale/imx952.dtsi index b30707837f35..8d65c380e1c4 100644 --- a/arch/arm64/boot/dts/freescale/imx952.dtsi +++ b/arch/arm64/boot/dts/freescale/imx952.dtsi @@ -318,6 +318,28 @@ usbphynop2: usbphynop2 { clock-names = "main_clk"; }; + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-hz-real = /bits/ 64 <500000000>; + opp-microvolt = <920000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-hz-real = /bits/ 64 <800000000>; + opp-microvolt = <920000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-hz-real = /bits/ 64 <1000000000>; + opp-microvolt = <920000>; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -1484,5 +1506,19 @@ sai2: sai@4c880000 { power-domains = <&scmi_devpd IMX952_PD_NETC>; status = "disabled"; }; + + gpu: gpu@4d900000 { + compatible = "nxp,imx95-mali", "arm,mali-valhall-csf"; + reg = <0 0x4d900000 0 0x480000>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + clocks = <&scmi_clk IMX952_CLK_GPU>; + clock-names = "core"; + power-domains = <&scmi_devpd IMX952_PD_GPU>; + operating-points-v2 = <&gpu_opp_table>; + dynamic-power-coefficient = <1013>; + }; }; }; From 8e14bf7be3b296f074de0d4b35f267c27120aeb5 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 9 Apr 2026 20:00:01 +0800 Subject: [PATCH 177/665] arm64: dts: imx95: Correct SMMU reg Update SMMU reg size to 0x40000, because MMU-700 TCU occupies 4 pages with each page 64KB and the last page is reserved. Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 71394871d8dd..28b19a47a59d 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -1761,7 +1761,7 @@ aips4: bus@49000000 { smmu: iommu@490d0000 { compatible = "arm,smmu-v3"; - reg = <0x490d0000 0x100000>; + reg = <0x490d0000 0x40000>; interrupts = , , , From ff0f8a2c2aadc467a61a664c7a81ededc2bb46bc Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 9 Apr 2026 20:00:02 +0800 Subject: [PATCH 178/665] arm64: dts: imx95: Add SMMU PMU nodes MMU-700 supports TCU PMU and TBU PMU. There are one TCU PMU and 11 TBU PMUs, add them all. Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95.dtsi | 84 ++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 28b19a47a59d..3e35c956a4d7 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -1770,6 +1770,90 @@ smmu: iommu@490d0000 { #iommu-cells = <1>; status = "disabled"; }; + + pmu@490d2000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x490d2000 0x1000>, + <0x490f2000 0x1000>; + interrupts = ; + }; + + pmu@49112000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x49112000 0x1000>, + <0x49122000 0x1000>; + interrupts = ; + }; + + pmu@49132000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x49132000 0x1000>, + <0x49142000 0x1000>; + interrupts = ; + }; + + pmu@49152000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x49152000 0x1000>, + <0x49162000 0x1000>; + interrupts = ; + }; + + pmu@49172000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x49172000 0x1000>, + <0x49182000 0x1000>; + interrupts = ; + }; + + pmu@49192000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x49192000 0x1000>, + <0x491a2000 0x1000>; + interrupts = ; + }; + + pmu@491b2000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x491b2000 0x1000>, + <0x491c2000 0x1000>; + interrupts = ; + }; + + pmu@491d2000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x491d2000 0x1000>, + <0x491e2000 0x1000>; + interrupts = ; + }; + + pmu@491f2000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x491f2000 0x1000>, + <0x49202000 0x1000>; + interrupts = ; + }; + + pmu@49212000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x49212000 0x1000>, + <0x49222000 0x1000>; + interrupts = ; + }; + + pmu@49232000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x49232000 0x1000>, + <0x49242000 0x1000>; + interrupts = ; + }; + + pmu@49252000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x49252000 0x1000>, + <0x49262000 0x1000>; + interrupts = ; + }; }; usb3: usb@4c010010 { From a2407a8a42784f90732351dc9982ec3f6f67a6d8 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Thu, 9 Apr 2026 13:10:59 +0200 Subject: [PATCH 179/665] ARM: dts: imx6ul: add #io-channel-cells to ADC Add #io-channel-cells property to the ADC node. This property is required for an IIO consumer driver to work. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx6ul.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi index 6eb80f867f50..a66af8116a06 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi @@ -944,6 +944,7 @@ adc1: adc@2198000 { interrupts = ; clocks = <&clks IMX6UL_CLK_ADC1>; clock-names = "adc"; + #io-channel-cells = <1>; fsl,adck-max-frequency = <30000000>, <40000000>, <20000000>; status = "disabled"; From 90d083b05f057c3107a7344f652d3a1ae1a2536e Mon Sep 17 00:00:00 2001 From: Adrian Ng Ho Yin Date: Wed, 6 May 2026 14:21:49 +0800 Subject: [PATCH 180/665] arm64: dts: socfpga: agilex5: update data-width for dmac Update data-width property for dmac to 3 which is 64 bits to match value configured in the hardware register. Signed-off-by: Adrian Ng Ho Yin Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index 02e62d954e94..b06c6d5d60ee 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -343,7 +343,7 @@ dmac0: dma-controller@0 { #dma-cells = <1>; dma-channels = <4>; snps,dma-masters = <1>; - snps,data-width = <2>; + snps,data-width = <3>; snps,block-size = <32767 32767 32767 32767>; snps,priority = <0 1 2 3>; snps,axi-max-burst-len = <8>; @@ -362,7 +362,7 @@ dmac1: dma-controller@10000 { #dma-cells = <1>; dma-channels = <4>; snps,dma-masters = <1>; - snps,data-width = <2>; + snps,data-width = <3>; snps,block-size = <32767 32767 32767 32767>; snps,priority = <0 1 2 3>; snps,axi-max-burst-len = <8>; From e0abb8a515cdb7613a15ce54910405ce8110e4f5 Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Wed, 31 Dec 2025 22:14:17 +0100 Subject: [PATCH 181/665] ARM: dts: ti/omap: omap4-epson-embt2ws: fix typo in iio device property Define interrupts properly. Unfortunately, this hides a bug in the linux driver, so it needs to be used with the driver fixed only. Signed-off-by: Andreas Kemnade Reviewed-by: Jonathan Cameron Link: https://patch.msgid.link/20251231-mpu9150-v1-2-08ecf085c4ae@kernel.org Signed-off-by: Kevin Hilman (TI) --- arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts b/arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts index 673df1b693f2..e253e0775ea9 100644 --- a/arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts +++ b/arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts @@ -351,7 +351,7 @@ mpu9150h: imu@68 { pinctrl-names = "default"; pinctrl-0 = <&mpu9150h_pins>; interrupt-parent = <&gpio2>; - interrupt = <19 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -413,7 +413,7 @@ mpu9150: imu@68 { pinctrl-names = "default"; pinctrl-0 = <&mpu9150_pins>; interrupt-parent = <&gpio2>; - interrupt = <7 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; vddio-supply = <&cb_v18>; vdd-supply = <&cb_v33>; invensense,level-shifter; From 009f64641db3fbfecf92dee910c57a41c3e77a4b Mon Sep 17 00:00:00 2001 From: Ivaylo Dimitrov Date: Wed, 22 Jan 2025 18:41:25 +0200 Subject: [PATCH 182/665] arch: arm: dts: cpcap-mapphone: Set VAUDIO regulator always-on VAUDIO regulator is used by cpcap codec and currently is enabled/disabled by dapm logic, however, when regulator is turned off, various cpcap functions (like jack detection) do not work. Configure VAUDIO regulator-allowed-modes property while at it to enable low-power regulator mode being set. Signed-off-by: Ivaylo Dimitrov Link: https://patch.msgid.link/20250122164129.807247-2-ivo.g.dimitrov.75@gmail.com Signed-off-by: Kevin Hilman (TI) --- arch/arm/boot/dts/ti/omap/motorola-cpcap-mapphone.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ti/omap/motorola-cpcap-mapphone.dtsi b/arch/arm/boot/dts/ti/omap/motorola-cpcap-mapphone.dtsi index ea02fd403a9b..83fd58157579 100644 --- a/arch/arm/boot/dts/ti/omap/motorola-cpcap-mapphone.dtsi +++ b/arch/arm/boot/dts/ti/omap/motorola-cpcap-mapphone.dtsi @@ -267,6 +267,8 @@ vaudio: VAUDIO { regulator-min-microvolt = <2775000>; regulator-max-microvolt = <2775000>; regulator-enable-ramp-delay = <1000>; - regulator-initial-mode = <0x00>; /* NORMAL */ + regulator-allowed-modes = <0x00>, <0x40>; /* ON, LOW_PWR */ + regulator-initial-mode = <0x00>; /* ON */ + regulator-always-on; }; }; From 164f88cd7e0c0fcb950e8b4ba5d8c26404334c88 Mon Sep 17 00:00:00 2001 From: Ivaylo Dimitrov Date: Wed, 22 Jan 2025 18:41:28 +0200 Subject: [PATCH 183/665] arch: arm: dts: cpcap-mapphone: Add audio-codec jack detection interrupts cpcap audio-codec supports headset/micrphone detect interrupts, configure them. Signed-off-by: Ivaylo Dimitrov Link: https://patch.msgid.link/20250122164129.807247-5-ivo.g.dimitrov.75@gmail.com Signed-off-by: Kevin Hilman (TI) --- arch/arm/boot/dts/ti/omap/motorola-cpcap-mapphone.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/ti/omap/motorola-cpcap-mapphone.dtsi b/arch/arm/boot/dts/ti/omap/motorola-cpcap-mapphone.dtsi index 83fd58157579..73e27b95105e 100644 --- a/arch/arm/boot/dts/ti/omap/motorola-cpcap-mapphone.dtsi +++ b/arch/arm/boot/dts/ti/omap/motorola-cpcap-mapphone.dtsi @@ -69,6 +69,8 @@ cpcap_regulators: regulators { cpcap_audio: audio-codec { #sound-dai-cells = <1>; + interrupts-extended = <&cpcap 9 0>, <&cpcap 10 0>; + interrupt-names = "hs", "mb2"; port@0 { cpcap_audio_codec0: endpoint { From b6aefeea7b4aa9158c1dcec8c050a678af7bf9b0 Mon Sep 17 00:00:00 2001 From: Christopher Obbard Date: Sat, 2 May 2026 03:13:18 +0100 Subject: [PATCH 184/665] ARM: dts: dm8168-evm: Set stdout-path to uart3 Specify the board's default console UART by setting chosen/stdout-path to uart3, so that early console output and /dev/console map to the expected serial port by default. Signed-off-by: Christopher Obbard Link: https://patch.msgid.link/20260502-wip-obbardc-omap-dm8168-evm-stdout-path-v1-1-d1e69c295c21@linaro.org Signed-off-by: Kevin Hilman (TI) --- arch/arm/boot/dts/ti/omap/dm8168-evm.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/ti/omap/dm8168-evm.dts b/arch/arm/boot/dts/ti/omap/dm8168-evm.dts index 6130b9a5f660..81450e15b889 100644 --- a/arch/arm/boot/dts/ti/omap/dm8168-evm.dts +++ b/arch/arm/boot/dts/ti/omap/dm8168-evm.dts @@ -8,6 +8,10 @@ / { model = "DM8168 EVM"; compatible = "ti,dm8168-evm", "ti,dm8168", "ti,dm816"; + chosen { + stdout-path = &uart3; + }; + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000 /* 1 GB */ From eb24b60553e0692cbbec2863ca31d2a56bff098d Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 6 May 2026 11:28:04 +0200 Subject: [PATCH 185/665] arm64: dts: rockchip: Add watchdog node for RK3528 Add the node describing the watchdog on the RK3528 SoC. Signed-off-by: Jonas Karlman Signed-off-by: Heiko Stuebner Link: https://patch.msgid.link/20260506092804.3320931-1-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index 806b8109f67d..77d314716b43 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -983,6 +983,14 @@ pwm7: pwm@ffa98030 { status = "disabled"; }; + wdt: watchdog@ffac0000 { + compatible = "rockchip,rk3528-wdt", "snps,dw-wdt"; + reg = <0x0 0xffac0000 0x0 0x100>; + clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; + clock-names = "tclk", "pclk"; + interrupts = ; + }; + saradc: adc@ffae0000 { compatible = "rockchip,rk3528-saradc"; reg = <0x0 0xffae0000 0x0 0x10000>; From c5637e5ceb4b4bbe80fceec77f5e663c4ff7b508 Mon Sep 17 00:00:00 2001 From: Nazim Amirul Date: Wed, 6 May 2026 20:32:02 -0700 Subject: [PATCH 186/665] arm64: dts: socfpga: agilex5: Fix phy-mode to rgmii as HW provides clock delay The Agilex5 SoC provides RGMII TX/RX clock delay compensation through its integrated I/O hardware. Using phy-mode = "rgmii-id" instructs the MAC driver to additionally insert internal TX/RX delays, resulting in double delay being applied and causing Ethernet link timing issues. Change phy-mode to "rgmii" across all Agilex5 device tree files to reflect that the clock delay is already handled by the hardware and no additional software-inserted delay is required. Add an inline comment to satisfy checkpatch and document the hardware-provided delay. Signed-off-by: Nazim Amirul Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts | 2 +- arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts | 2 +- arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts | 2 +- arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts index dae0db9f8819..57d3c5807c65 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts @@ -44,7 +44,7 @@ &gpio0 { &gmac2 { status = "okay"; - phy-mode = "rgmii-id"; + phy-mode = "rgmii"; /* TX/RX clock delays provided by Agilex5 I/O hardware */ phy-handle = <&emac2_phy0>; max-frame-size = <9000>; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts index 86137380df04..82cd4115746e 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts @@ -43,7 +43,7 @@ memory@80000000 { &gmac2 { status = "okay"; - phy-mode = "rgmii-id"; + phy-mode = "rgmii"; /* TX/RX clock delays provided by Agilex5 I/O hardware */ phy-handle = <&emac2_phy0>; max-frame-size = <9000>; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts index e728cedb4cbd..4d32b6928ce1 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts @@ -46,7 +46,7 @@ &gpio1 { &gmac2 { status = "okay"; - phy-mode = "rgmii-id"; + phy-mode = "rgmii"; /* TX/RX clock delays provided by Agilex5 I/O hardware */ phy-handle = <&emac2_phy0>; max-frame-size = <9000>; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts index 21faa47681fa..81443096cf99 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts @@ -41,7 +41,7 @@ memory@80000000 { &gmac0 { status = "okay"; - phy-mode = "rgmii-id"; + phy-mode = "rgmii"; /* TX/RX clock delays provided by Agilex5 I/O hardware */ phy-handle = <&emac0_phy0>; max-frame-size = <9000>; From f8874bc5792134b7bdda9706e2a48e6285da3664 Mon Sep 17 00:00:00 2001 From: Dikshita Agarwal Date: Thu, 7 May 2026 09:42:16 +0300 Subject: [PATCH 187/665] arm64: dts: qcom: agatti: add higher OPP levels Add additional OPP entries for the Agatti platform to support higher operating frequencies as specified in the hardware documentation. Reviewed-by: Dmitry Baryshkov Signed-off-by: Dikshita Agarwal Link: https://lore.kernel.org/r/20260507-iris-ar50lt-v1-16-d22cccedc3e2@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/agatti.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/agatti.dtsi b/arch/arm64/boot/dts/qcom/agatti.dtsi index 8a7337239b1e..fd40aa59878a 100644 --- a/arch/arm64/boot/dts/qcom/agatti.dtsi +++ b/arch/arm64/boot/dts/qcom/agatti.dtsi @@ -2455,6 +2455,16 @@ opp-240000000 { opp-hz = /bits/ 64 <240000000>; required-opps = <&rpmpd_opp_svs>; }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmpd_opp_nom>; + }; }; }; From 5a95bd4771ffd591e810717e1c6dcc568ebf45d8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 7 Apr 2026 15:51:43 +0200 Subject: [PATCH 188/665] arm64: dts: qcom: eliza: Add QCE crypto Add nodes for the BAM DAM and QCE crypto engine. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Kuldeep Singh Reviewed-by: Konrad Dybcio Reviewed-by: Harshal Dev Link: https://lore.kernel.org/r/20260407-crypto-qcom-eliza-v1-2-40f61a1454a2@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza.dtsi | 32 +++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi index 4a7a0ac40ce6..24c680795481 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -846,6 +846,38 @@ ice: crypto@1d88000 { clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x0 0x01dc4000 0x0 0x28000>; + + interrupts = ; + + #dma-cells = <1>; + + iommus = <&apps_smmu 0x480 0>, + <&apps_smmu 0x481 0>; + + qcom,ee = <0>; + qcom,num-ees = <4>; + num-channels = <20>; + qcom,controlled-remotely; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,eliza-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0x0 0x01dfa000 0x0 0x6000>; + + interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "memory"; + + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + + iommus = <&apps_smmu 0x480 0>, + <&apps_smmu 0x481 0>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>; From 208af18362e01f59bfe4a71a8606b09acb673cd0 Mon Sep 17 00:00:00 2001 From: Alexander Koskovich Date: Mon, 6 Apr 2026 02:10:15 +0000 Subject: [PATCH 189/665] arm64: dts: qcom: milos: Add QCrypto nodes Add the QCE and Crypto BAM DMA nodes. Signed-off-by: Alexander Koskovich Reviewed-by: Kuldeep Singh Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260405-milos-qce-v1-2-6996fb0b8a9c@pm.me Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/milos.dtsi | 32 +++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi index 347afce18924..f09b30ea96ee 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -1278,6 +1278,38 @@ ice: crypto@1d88000 { clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x0 0x01dc4000 0x0 0x28000>; + + interrupts = ; + + #dma-cells = <1>; + + iommus = <&apps_smmu 0x480 0>, + <&apps_smmu 0x481 0>; + + qcom,ee = <0>; + qcom,num-ees = <4>; + num-channels = <20>; + qcom,controlled-remotely; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,milos-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0x0 0x01dfa000 0x0 0x6000>; + + interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "memory"; + + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + + iommus = <&apps_smmu 0x480 0>, + <&apps_smmu 0x481 0>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>; From 93e08fdc55f227847dc9b249fd5eb43403e7e8b9 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Tue, 5 May 2026 13:10:04 +0530 Subject: [PATCH 190/665] arm64: dts: qcom: glymur: Add crypto engine and BAM On almost all Qualcomm platforms, including Glymur, there is a Crypto engine IP block to which the CPU can off-load cryptographic computations for achieving acceleration. The engine is also DMA capable due to the presence of an associated Bus Access Manager (BAM) module. Describe the Crypto engine and its BAM. Signed-off-by: Harshal Dev Link: https://lore.kernel.org/r/20260505-glymur_crypto_enablement-v2-2-bf115aeb1459@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 0c5cb8532b20..c8f7eab29606 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -3675,6 +3675,32 @@ pcie3b_phy: phy@f10000 { status = "disabled"; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x0 0x01dc4000 0x0 0x28000>; + interrupts = ; + #dma-cells = <1>; + iommus = <&apps_smmu 0x80 0x0>, + <&apps_smmu 0x81 0x0>; + qcom,ee = <0>; + qcom,controlled-remotely; + num-channels = <20>; + qcom,num-ees = <4>; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,glymur-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0x0 0x01dfa000 0x0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", + "tx"; + iommus = <&apps_smmu 0x80 0x0>, + <&apps_smmu 0x81 0x0>; + interconnects = <&aggre1_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "memory"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>; From ef4d269e5566ec8d32de149c91f1c907ec9b9511 Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Wed, 29 Apr 2026 22:31:39 +0530 Subject: [PATCH 191/665] arm64: dts: qcom: talos: Add QSPI support The Talos (QCS615) platform includes a QSPI controller used for accessing external flash storage. Add the QSPI OPP table, TLMM pinmux entries, and the QSPI controller node to enable support for this hardware. Reviewed-by: Konrad Dybcio Signed-off-by: Viken Dadhaniya Link: https://lore.kernel.org/r/20260429-spi-nor-v5-4-993016c9711e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/talos.dtsi | 80 +++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index ff5afbfce2a4..8c7ea369a332 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -531,6 +531,25 @@ cdsp_smp2p_in: slave-kernel { }; + qspi_opp_table: opp-table-qspi { + compatible = "operating-points-v2"; + + opp-60000000 { + opp-hz = /bits/ 64 <60000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-133250000 { + opp-hz = /bits/ 64 <133250000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-266500000 { + opp-hz = /bits/ 64 <266500000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + qup_opp_table: opp-table-qup { compatible = "operating-points-v2"; @@ -1610,6 +1629,34 @@ cci_i2c1_default: cci-i2c1-default-state { bias-pull-up; }; + qspi_cs0: qspi-cs0-state { + pins = "gpio44"; + function = "qspi"; + bias-disable; + drive-strength = <6>; + }; + + qspi_data0123: qspi-data0123-state { + pins = "gpio45", "gpio46", "gpio47", "gpio49"; + function = "qspi"; + bias-pull-down; + drive-strength = <6>; + }; + + qspi_clk: qspi-clk-state { + pins = "gpio48"; + function = "qspi"; + bias-pull-down; + drive-strength = <6>; + }; + + qspi_cs1: qspi-cs1-state { + pins = "gpio50"; + function = "qspi"; + bias-pull-down; + drive-strength = <6>; + }; + qup_i2c1_data_clk: qup-i2c1-data-clk-state { pins = "gpio4", "gpio5"; function = "qup0"; @@ -3896,6 +3943,39 @@ opp-202000000 { }; }; + qspi: spi@88df000 { + compatible = "qcom,qcs615-qspi", + "qcom,qspi-v1"; + reg = <0x0 0x088df000 0x0 0x1000>; + + interrupts = ; + + clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, + <&gcc GCC_QSPI_CORE_CLK>; + clock-names = "iface", + "core"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QSPI QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QSPI QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qspi-config", + "qspi-memory"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qspi_opp_table>; + + iommus = <&apps_smmu 0x160 0x0>; + + pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0123>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + dc_noc: interconnect@9160000 { reg = <0x0 0x09160000 0x0 0x3200>; compatible = "qcom,qcs615-dc-noc"; From d2ed3f777f81989a7af6029dee59decad9f488d2 Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Wed, 29 Apr 2026 22:31:40 +0530 Subject: [PATCH 192/665] arm64: dts: qcom: qcs615-ride: Enable QSPI and NOR flash The QCS615 Ride board has a SPI-NOR flash connected to the QSPI controller on CS0. Enable the QSPI controller and add the corresponding SPI-NOR flash node to allow the system to access it. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Viken Dadhaniya Link: https://lore.kernel.org/r/20260429-spi-nor-v5-5-993016c9711e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index 831002789838..51b13b492472 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -498,6 +498,18 @@ &pon_resin { status = "okay"; }; +&qspi { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; +}; + &qupv3_id_0 { status = "okay"; }; From 45287b9e5e28f10ec910480635d4f239154d4120 Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Wed, 29 Apr 2026 22:31:41 +0530 Subject: [PATCH 193/665] arm64: dts: qcom: kodiak: Add QSPI memory interconnect path Add the missing QSPI-to-memory interconnect path alongside the existing configuration path. Without it, the interconnect framework cannot vote for the bandwidth required by QSPI DMA data transfers. Reviewed-by: Konrad Dybcio Signed-off-by: Viken Dadhaniya Link: https://lore.kernel.org/r/20260429-spi-nor-v5-6-993016c9711e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index 988ca5f7c8a0..2dbeb15c84b7 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -4418,9 +4418,12 @@ qspi: spi@88dc000 { clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <&gcc GCC_QSPI_CORE_CLK>; clock-names = "iface", "core"; - interconnects = <&gem_noc MASTER_APPSS_PROC 0 - &cnoc2 SLAVE_QSPI_0 0>; - interconnect-names = "qspi-config"; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc2 SLAVE_QSPI_0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QSPI_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qspi-config", + "qspi-memory"; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qspi_opp_table>; status = "disabled"; From 8289feadbcbc1b0458a9e81d0eca42f97b28bbe3 Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Wed, 29 Apr 2026 22:31:42 +0530 Subject: [PATCH 194/665] arm64: dts: qcom: sc7180: Add QSPI memory interconnect path Add the missing QSPI-to-memory interconnect path alongside the existing configuration path. Without this path, the interconnect framework cannot correctly vote for the bandwidth required by QSPI DMA data transfers. Reviewed-by: Konrad Dybcio Signed-off-by: Viken Dadhaniya Link: https://lore.kernel.org/r/20260429-spi-nor-v5-7-993016c9711e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index a4b17564469e..8341a7c4a4c6 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2866,9 +2866,12 @@ qspi: spi@88dc000 { clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <&gcc GCC_QSPI_CORE_CLK>; clock-names = "iface", "core"; - interconnects = <&gem_noc MASTER_APPSS_PROC 0 - &config_noc SLAVE_QSPI_0 0>; - interconnect-names = "qspi-config"; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QSPI_0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QSPI QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qspi-config", + "qspi-memory"; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qspi_opp_table>; status = "disabled"; From 0ce60cd362a0a01bd439e85bc93e6a61434e63da Mon Sep 17 00:00:00 2001 From: Adrian Ng Ho Yin Date: Fri, 8 May 2026 18:57:47 +0800 Subject: [PATCH 195/665] dt-bindings: altera: add compatible for agilex5 socdk debug daughter card Agilex5 devkit supports a debug daughter card that inherits the configurations from socdk but disables gpio0 and gmac2 and enables gmac0 and spi0. Signed-off-by: Adrian Ng Ho Yin Acked-by: Conor Dooley Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/arm/altera.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 4b096e52243e..0b418d9d60db 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -111,6 +111,7 @@ properties: - enum: - intel,socfpga-agilex5-socdk - intel,socfpga-agilex5-socdk-013b + - intel,socfpga-agilex5-socdk-debug - intel,socfpga-agilex5-socdk-modular - intel,socfpga-agilex5-socdk-nand - const: intel,socfpga-agilex5 From 3c350f6284d8ea5e7a9648241b2e9604f2262d42 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Tue, 28 Apr 2026 10:57:29 +0000 Subject: [PATCH 196/665] dts: riscv: spacemit: correct 32k clock frequency The 32k oscillator's clock frequency is actually 32768Hz, so correct it. Fixes: 67072c8cd48c ("riscv: dts: spacemit: k3: add clock tree") Fixes: a6fafa64b03a ("riscv: dts: spacemit: Add clock tree for SpacemiT K1") Link: https://patch.msgid.link/20260428-06-k3-clk-osc32k-v1-1-e2378da7cb9b@kernel.org Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1.dtsi | 2 +- arch/riscv/boot/dts/spacemit/k3.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index f8747190d2e1..24becab4c959 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -333,7 +333,7 @@ vctcxo_3m: clock-3m { osc_32k: clock-32k { compatible = "fixed-clock"; - clock-frequency = <32000>; + clock-frequency = <32768>; clock-output-names = "osc_32k"; #clock-cells = <0>; }; diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index 815debd16409..e6faf8d8759e 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -424,7 +424,7 @@ vctcxo_3m: clock-3m { osc_32k: clock-32k { compatible = "fixed-clock"; - clock-frequency = <32000>; + clock-frequency = <32768>; clock-output-names = "osc_32k"; #clock-cells = <0>; }; From f068b204555ad62d6a841a49feb4ea8c4f45b25c Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sat, 9 May 2026 18:00:00 +0800 Subject: [PATCH 197/665] riscv: dts: spacemit: enable eMMC for OrangePi RV2 The OrangePi RV2 board has one eMMC slot, so enable eMMC. Tested using a 16 GiB AJTD4R eMMC module. Signed-off-by: Chukun Pan Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260509100000.3315109-1-amadeus@jmu.edu.cn Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts index 3a829e3c9cbc..c95ca38e3d4a 100644 --- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts @@ -78,6 +78,16 @@ &combo_phy { status = "okay"; }; +&emmc { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + ð0 { phy-handle = <&rgmii0>; phy-mode = "rgmii-id"; From db6ae6650cfdf085e21a477c25386125075b2351 Mon Sep 17 00:00:00 2001 From: Nickolay Goppen Date: Wed, 29 Apr 2026 12:30:08 +0300 Subject: [PATCH 198/665] dt-bindings: firmware: qcom: scm: add CP_ADSP_SHARED VMID CP_ADSP_SHARED is used in FastRPC driver for older SoC's such as sdm660 for interacting with ADSP memory region [1] [1]: https://github.com/xiaomi-sdm660/android_kernel_xiaomi_sdm660/blob/11-EAS/drivers/char/adsprpc.c#L3602 Acked-by: Krzysztof Kozlowski Signed-off-by: Nickolay Goppen Link: https://lore.kernel.org/r/20260429-qcom-sdm660-cdsp-adsp-fastrpc-dts-fix-v5-1-16bc82e622ad@mainlining.org Signed-off-by: Bjorn Andersson --- include/dt-bindings/firmware/qcom,scm.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/firmware/qcom,scm.h b/include/dt-bindings/firmware/qcom,scm.h index 6de8b08e1e79..0d29d8d4829c 100644 --- a/include/dt-bindings/firmware/qcom,scm.h +++ b/include/dt-bindings/firmware/qcom,scm.h @@ -35,5 +35,6 @@ #define QCOM_SCM_VMID_NAV 0x2B #define QCOM_SCM_VMID_TVM 0x2D #define QCOM_SCM_VMID_OEMVM 0x31 +#define QCOM_SCM_VMID_CP_ADSP_SHARED 0x33 #endif From 708ab9d3bc5b74eeee767c678366624d3c02a4ec Mon Sep 17 00:00:00 2001 From: Nickolay Goppen Date: Wed, 29 Apr 2026 12:30:09 +0300 Subject: [PATCH 199/665] arm64: dts: qcom: sdm660: set cdsp compute-cbs' regs properly Changing FastRPC compute-cbs' reg values to matching iommu streams solves SMMU translation errors when trying to use FastRPC on CDSP so change FastRPC compute-cbs' reg values that way Fixes: c0c32a9e3493 ("arm64: dts: qcom: sdm630/660: Add CDSP-related nodes") Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Ekansh Gupta Signed-off-by: Nickolay Goppen Link: https://lore.kernel.org/r/20260429-qcom-sdm660-cdsp-adsp-fastrpc-dts-fix-v5-2-16bc82e622ad@mainlining.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm660.dtsi | 36 ++++++++++++++-------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi index 3fd6dd82a992..0fca9662c64a 100644 --- a/arch/arm64/boot/dts/qcom/sdm660.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi @@ -350,57 +350,57 @@ fastrpc { #address-cells = <1>; #size-cells = <0>; + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&cdsp_smmu 3>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&cdsp_smmu 4>; + }; + compute-cb@5 { compatible = "qcom,fastrpc-compute-cb"; reg = <5>; - iommus = <&cdsp_smmu 3>; + iommus = <&cdsp_smmu 5>; }; compute-cb@6 { compatible = "qcom,fastrpc-compute-cb"; reg = <6>; - iommus = <&cdsp_smmu 4>; + iommus = <&cdsp_smmu 6>; }; compute-cb@7 { compatible = "qcom,fastrpc-compute-cb"; reg = <7>; - iommus = <&cdsp_smmu 5>; + iommus = <&cdsp_smmu 7>; }; compute-cb@8 { compatible = "qcom,fastrpc-compute-cb"; reg = <8>; - iommus = <&cdsp_smmu 6>; + iommus = <&cdsp_smmu 8>; }; compute-cb@9 { compatible = "qcom,fastrpc-compute-cb"; reg = <9>; - iommus = <&cdsp_smmu 7>; + iommus = <&cdsp_smmu 9>; }; compute-cb@10 { compatible = "qcom,fastrpc-compute-cb"; reg = <10>; - iommus = <&cdsp_smmu 8>; + iommus = <&cdsp_smmu 10>; }; compute-cb@11 { compatible = "qcom,fastrpc-compute-cb"; reg = <11>; - iommus = <&cdsp_smmu 9>; - }; - - compute-cb@12 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <12>; - iommus = <&cdsp_smmu 10>; - }; - - compute-cb@13 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <13>; iommus = <&cdsp_smmu 11>; }; }; From e8e1fb5c703fc6962103ffdc60830df99351c139 Mon Sep 17 00:00:00 2001 From: Nickolay Goppen Date: Wed, 29 Apr 2026 12:30:10 +0300 Subject: [PATCH 200/665] arm64: dts: qcom: sdm630: set adsp compute-cbs' regs properly Changing FastRPC compute-cbs' reg values to matching iommu streams solves SMMU translation errors when trying to use FastRPC on ADSP so change FastRPC compute-cbs' reg values that way Fixes: af2ce7296643 ("arm64: dts: qcom: sdm630: Add FastRPC nodes to ADSP") Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Ekansh Gupta Signed-off-by: Nickolay Goppen Link: https://lore.kernel.org/r/20260429-qcom-sdm660-cdsp-adsp-fastrpc-dts-fix-v5-3-16bc82e622ad@mainlining.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index bef3213165d6..4b47efdb57b2 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -2459,27 +2459,27 @@ fastrpc { #address-cells = <1>; #size-cells = <0>; - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&lpass_smmu 3>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&lpass_smmu 7>; - }; - compute-cb@3 { compatible = "qcom,fastrpc-compute-cb"; reg = <3>; + iommus = <&lpass_smmu 3>; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&lpass_smmu 7>; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; iommus = <&lpass_smmu 8>; }; - compute-cb@4 { + compute-cb@9 { compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; + reg = <9>; iommus = <&lpass_smmu 9>; }; }; From ce414263e9ebe5080381a50cbdf9065c29816202 Mon Sep 17 00:00:00 2001 From: Nickolay Goppen Date: Wed, 29 Apr 2026 12:30:11 +0300 Subject: [PATCH 201/665] arm64: dts: qcom: sdm630: describe adsp_mem region properly Downstream [1] this region is marked as shared, reusable and dynamic so describe it that way. [1]: https://github.com/xiaomi-sdm660/android_kernel_xiaomi_sdm660/blob/11-EAS/arch/arm/boot/dts/qcom/sdm660.dtsi#L448 Fixes: b190fb010664 ("arm64: dts: qcom: sdm630: Add sdm630 dts file") Cc: stable@vger.kernel.org Reviewed-by: Ekansh Gupta Reviewed-by: Dmitry Baryshkov Signed-off-by: Nickolay Goppen Link: https://lore.kernel.org/r/20260429-qcom-sdm660-cdsp-adsp-fastrpc-dts-fix-v5-4-16bc82e622ad@mainlining.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 4b47efdb57b2..252c301f0156 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -494,9 +494,12 @@ venus_region: venus@9f800000 { no-map; }; - adsp_mem: adsp-region@f6000000 { - reg = <0x0 0xf6000000 0x0 0x800000>; - no-map; + adsp_mem: adsp-region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x80000000 0x0 0x80000000>; + alignment = <0x0 0x400000>; + size = <0x0 0x800000>; + reusable; }; qseecom_mem: qseecom-region@f6800000 { From dc11a2824f059de67f499d2b9be82b602433b848 Mon Sep 17 00:00:00 2001 From: Nickolay Goppen Date: Wed, 29 Apr 2026 12:30:12 +0300 Subject: [PATCH 202/665] arm64: dts: qcom: sdm630: assign adsp_mem region to ADSP FastRPC node Downstream [1] ADSP FastRPC node has the adsp_mem region assigned, so assign it to the ADSP FastRPC node. [1]: https://github.com/xiaomi-sdm660/android_kernel_xiaomi_sdm660/blob/11-EAS/arch/arm/boot/dts/qcom/sdm660.dtsi#L1693 Reviewed-by: Dmitry Baryshkov Reviewed-by: Ekansh Gupta Reviewed-by: Konrad Dybcio Signed-off-by: Nickolay Goppen Link: https://lore.kernel.org/r/20260429-qcom-sdm660-cdsp-adsp-fastrpc-dts-fix-v5-5-16bc82e622ad@mainlining.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 252c301f0156..a41ba0da380b 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -2458,6 +2458,9 @@ fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "adsp"; + memory-region = <&adsp_mem>; + qcom,vmids = ; qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; From 113343d57607937102d843775560fea0ce5cbe6f Mon Sep 17 00:00:00 2001 From: Amit Pundir Date: Tue, 7 Apr 2026 08:43:56 +0200 Subject: [PATCH 203/665] arm64: dts: qcom: sdm845-xiaomi-beryllium: Enable ath10k host-cap skip quirk The Wi-Fi firmware used on Xiaomi Poco F1 (beryllium) phone doesn't support the host-capability QMI request, so add a quirk to skip it on this device. Signed-off-by: Amit Pundir Reviewed-by: Dmitry Baryshkov Signed-off-by: David Heidelberg Link: https://lore.kernel.org/r/20260407-skip-host-cam-qmi-req-v5-3-dfa8a05c6538@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index a6ee3dd171de..9b7fdbca9e1c 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -677,5 +677,6 @@ &wifi { vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; qcom,calibration-variant = "xiaomi_beryllium"; + qcom,snoc-host-cap-skip-quirk; }; From 08569936a11b8ed20f95783d80d1ba2f4e93fa93 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 7 Apr 2026 22:18:40 +0200 Subject: [PATCH 204/665] arm64: dts: qcom: Use GIC_SPI macro for interrupt-map Make the complicated interrupt-map property (with multiple '0' entries) a bit more readable by using known define for GIC_SPI. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260407201839.25759-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 32 ++++++++++++------------- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 8 +++---- arch/arm64/boot/dts/qcom/msm8998.dtsi | 8 +++---- arch/arm64/boot/dts/qcom/sm8750.dtsi | 8 +++---- 4 files changed, 28 insertions(+), 28 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index c8f7eab29606..2378b7a4a30d 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -2776,10 +2776,10 @@ pcie4: pci@1bf0000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 513 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 514 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 515 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 516 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_4_AUX_CLK>, <&gcc GCC_PCIE_4_CFG_AHB_CLK>, @@ -2986,10 +2986,10 @@ pcie5: pci@1b40000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 526 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 428 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 429 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_5_AUX_CLK>, <&gcc GCC_PCIE_5_CFG_AHB_CLK>, @@ -3252,10 +3252,10 @@ pcie6: pci@1c00000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 472 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 473 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 474 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 475 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_6_AUX_CLK>, <&gcc GCC_PCIE_6_CFG_AHB_CLK>, @@ -3462,10 +3462,10 @@ pcie3b: pci@1b80000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 831 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 832 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 833 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 834 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index bab654bbd6d0..bcd1cee31356 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -2313,10 +2313,10 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, iommu-map = <0 &apps_smmu 0x1400 0x1>, <0x100 &apps_smmu 0x1401 0x1>; - interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; interrupt-map-mask = <0 0 0 0x7>; #interrupt-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index d41b5c470c48..347706011637 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -955,10 +955,10 @@ pcie0: pcie@1c00000 { "msi7", "global"; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, <&gcc GCC_PCIE_0_AUX_CLK>, diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 417f28d8c919..5921f83aafac 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -5210,10 +5210,10 @@ pcie0: pcie@1c00000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, From d962cd7c49fa210e53dfeed04028ac9ef112ae70 Mon Sep 17 00:00:00 2001 From: Le Qi Date: Thu, 9 Apr 2026 11:01:55 +0800 Subject: [PATCH 205/665] arm64: dts: qcom: talos: Add GPR node, audio services, and MI2S1 TLMM pins This patch adds the Generic Pack Router (GPR) node together with Audio Process Manager (APM) and Proxy Resource Manager (PRM) audio service nodes to the Talos device tree description. It also introduces MI2S1 pinctrl states for data0, data1, sck, and ws lines, grouped into a single entry at the SoC-level DTSI for better reuse and clarity. Reviewed-by: Konrad Dybcio Signed-off-by: Le Qi Link: https://lore.kernel.org/r/20260409030156.155455-2-le.qi@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/talos.dtsi | 54 +++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 8c7ea369a332..fb1bbc51bb8a 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -1657,6 +1658,20 @@ qspi_cs1: qspi-cs1-state { drive-strength = <6>; }; + mi2s1_pins: mi2s1-state { + pins = "gpio108", "gpio109", "gpio110", "gpio111"; + function = "mi2s_1"; + drive-strength = <8>; + bias-disable; + }; + + mi2s_mclk: mi2s-mclk-state { + pins = "gpio122"; + function = "mclk2"; + drive-strength = <8>; + bias-disable; + }; + qup_i2c1_data_clk: qup-i2c1-data-clk-state { pins = "gpio4", "gpio5"; function = "qup0"; @@ -5212,6 +5227,45 @@ compute-cb@6 { dma-coherent; }; }; + + gpr: gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,domain = ; + qcom,intents = <512 20>; + #address-cells = <1>; + #size-cells = <0>; + + q6apm: service@1 { + compatible = "qcom,q6apm"; + reg = ; + #sound-dai-cells = <0>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6apmbedai: bedais { + compatible = "qcom,q6apm-lpass-dais"; + #sound-dai-cells = <1>; + }; + + q6apmdai: dais { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x1721 0x0>; + }; + }; + + q6prm: service@2 { + compatible = "qcom,q6prm"; + reg = ; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + #clock-cells = <2>; + }; + }; + }; }; }; From 141d7ea5036e70f670aba1e6704be74552a3c964 Mon Sep 17 00:00:00 2001 From: Le Qi Date: Thu, 9 Apr 2026 11:01:56 +0800 Subject: [PATCH 206/665] arm64: dts: qcom: talos-evk: Add sound card support with DA7212 codec Add the sound card node for QCS615 Talos EVK with DA7212 codec connected over the Primary MI2S interface. The configuration enables headphone playback and headset microphone capture, both of which have been tested to work. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Le Qi Link: https://lore.kernel.org/r/20260409030156.155455-3-le.qi@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/talos-evk.dts | 56 ++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos-evk.dts b/arch/arm64/boot/dts/qcom/talos-evk.dts index af100e22beee..b7f514fbc7b2 100644 --- a/arch/arm64/boot/dts/qcom/talos-evk.dts +++ b/arch/arm64/boot/dts/qcom/talos-evk.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "talos-evk-som.dtsi" +#include / { model = "Qualcomm QCS615 IQ 615 EVK"; @@ -40,6 +41,46 @@ hdmi_con_out: endpoint { }; }; + sound { + compatible = "qcom,qcs615-sndcard"; + model = "TALOS-EVK"; + + pinctrl-0 = <&mi2s1_pins>, <&mi2s_mclk>; + pinctrl-names = "default"; + + pri-mi2s-capture-dai-link { + link-name = "Primary MI2S Capture"; + + codec { + sound-dai = <&codec_da7212>; + }; + + cpu { + sound-dai = <&q6apmbedai PRIMARY_MI2S_TX>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + pri-mi2s-playback-dai-link { + link-name = "Primary MI2S Playback"; + + codec { + sound-dai = <&codec_da7212>; + }; + + cpu { + sound-dai = <&q6apmbedai PRIMARY_MI2S_RX>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + vreg_v1p8_out: regulator-v1p8-out { compatible = "regulator-fixed"; regulator-name = "vreg-v1p8-out"; @@ -109,6 +150,21 @@ adv7535_out: endpoint { }; }; +&i2c5 { + status = "okay"; + + codec_da7212: codec@1a { + compatible = "dlg,da7212"; + reg = <0x1a>; + #sound-dai-cells = <0>; + clocks = <&q6prmcc LPASS_CLK_ID_MCLK_2 LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk"; + VDDA-supply = <&vreg_v1p8_out>; + VDDIO-supply = <&vreg_v1p8_out>; + VDDMIC-supply = <&vreg_v3p3_out>; + }; +}; + &mdss_dsi0_out { remote-endpoint = <&adv7535_in>; data-lanes = <0 1 2 3>; From 8222873cd4698627c08bffb2e40ba6f5a008fe32 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 31 Mar 2026 17:01:47 +0800 Subject: [PATCH 207/665] arm64: dts: qcom: lemans: Move PCIe devices into soc node These PCIe devices with MMIO address should be inside soc node rather than outside. Fixes: 489f14be0e0a ("arm64: dts: qcom: sa8775p: Add pcie0 and pcie1 nodes") Signed-off-by: Shawn Guo Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260331090147.18522-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 692 +++++++++++++-------------- 1 file changed, 346 insertions(+), 346 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 84a1e5ebbf5e..bc7b4f65ad5e 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -2694,6 +2694,352 @@ mmss_noc: interconnect@17a0000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + pcie0: pcie@1c00000 { + compatible = "qcom,pcie-sa8775p"; + reg = <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf20>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x4000>, + <0x0 0x40100000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <0>; + num-lanes = <2>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; + + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, + <0x100 &pcie_smmu 0x0001 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + power-domains = <&gcc PCIE_0_GDSC>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55>; + + status = "disabled"; + + pcieport0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie0_ep: pcie-ep@1c00000 { + compatible = "qcom,sa8775p-pcie-ep"; + reg = <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf20>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x4000>, + <0x0 0x40200000 0x0 0x1fe00000>, + <0x0 0x01c03000 0x0 0x1000>, + <0x0 0x40005000 0x0 0x2000>; + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + "mmio", "dma"; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; + + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + interrupts = , + , + ; + + interrupt-names = "global", "doorbell", "dma"; + + interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + dma-coherent; + iommus = <&pcie_smmu 0x0000 0x7f>; + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE_0_GDSC>; + phys = <&pcie0_phy>; + phy-names = "pciephy"; + num-lanes = <2>; + linux,pci-domain = <0>; + + status = "disabled"; + }; + + pcie0_phy: phy@1c04000 { + compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; + reg = <0x0 0x1c04000 0x0 0x2000>; + + clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + #clock-cells = <0>; + clock-output-names = "pcie_0_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + pcie1: pcie@1c10000 { + compatible = "qcom,pcie-sa8775p"; + reg = <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x60000000 0x0 0xf20>, + <0x0 0x60000f20 0x0 0xa8>, + <0x0 0x60001000 0x0 0x4000>, + <0x0 0x60100000 0x0 0x100000>, + <0x0 0x01c13000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <1>; + num-lanes = <4>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; + + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, + <0x100 &pcie_smmu 0x0081 0x1>; + + resets = <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + power-domains = <&gcc PCIE_1_GDSC>; + + phys = <&pcie1_phy>; + phy-names = "pciephy"; + + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; + + status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie1_ep: pcie-ep@1c10000 { + compatible = "qcom,sa8775p-pcie-ep"; + reg = <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x60000000 0x0 0xf20>, + <0x0 0x60000f20 0x0 0xa8>, + <0x0 0x60001000 0x0 0x4000>, + <0x0 0x60200000 0x0 0x1fe00000>, + <0x0 0x01c13000 0x0 0x1000>, + <0x0 0x60005000 0x0 0x2000>; + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + "mmio", "dma"; + + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; + + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + interrupts = , + , + ; + + interrupt-names = "global", "doorbell", "dma"; + + interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + dma-coherent; + iommus = <&pcie_smmu 0x80 0x7f>; + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE_1_GDSC>; + phys = <&pcie1_phy>; + phy-names = "pciephy"; + num-lanes = <4>; + linux,pci-domain = <1>; + + status = "disabled"; + }; + + pcie1_phy: phy@1c14000 { + compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; + reg = <0x0 0x1c14000 0x0 0x4000>; + + clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "phy"; + + #clock-cells = <0>; + clock-output-names = "pcie_1_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0x0 0x01d84000 0x0 0x3000>; @@ -8836,350 +9182,4 @@ turing_llm_tpdm_out: endpoint { }; }; }; - - pcie0: pcie@1c00000 { - compatible = "qcom,pcie-sa8775p"; - reg = <0x0 0x01c00000 0x0 0x3000>, - <0x0 0x40000000 0x0 0xf20>, - <0x0 0x40000f20 0x0 0xa8>, - <0x0 0x40001000 0x0 0x4000>, - <0x0 0x40100000 0x0 0x100000>, - <0x0 0x01c03000 0x0 0x1000>; - reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, - <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; - bus-range = <0x00 0xff>; - - dma-coherent; - - linux,pci-domain = <0>; - num-lanes = <2>; - - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-names = "msi0", - "msi1", - "msi2", - "msi3", - "msi4", - "msi5", - "msi6", - "msi7", - "global"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; - - clock-names = "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a"; - - assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; - assigned-clock-rates = <19200000>; - - interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; - interconnect-names = "pcie-mem", "cpu-pcie"; - - iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, - <0x100 &pcie_smmu 0x0001 0x1>; - - resets = <&gcc GCC_PCIE_0_BCR>, - <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; - reset-names = "pci", - "link_down"; - - power-domains = <&gcc PCIE_0_GDSC>; - - phys = <&pcie0_phy>; - phy-names = "pciephy"; - - eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; - eq-presets-16gts = /bits/ 8 <0x55 0x55>; - - status = "disabled"; - - pcieport0: pcie@0 { - device_type = "pci"; - reg = <0x0 0x0 0x0 0x0 0x0>; - bus-range = <0x01 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - }; - }; - - pcie0_ep: pcie-ep@1c00000 { - compatible = "qcom,sa8775p-pcie-ep"; - reg = <0x0 0x01c00000 0x0 0x3000>, - <0x0 0x40000000 0x0 0xf20>, - <0x0 0x40000f20 0x0 0xa8>, - <0x0 0x40001000 0x0 0x4000>, - <0x0 0x40200000 0x0 0x1fe00000>, - <0x0 0x01c03000 0x0 0x1000>, - <0x0 0x40005000 0x0 0x2000>; - reg-names = "parf", "dbi", "elbi", "atu", "addr_space", - "mmio", "dma"; - - clocks = <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; - - clock-names = "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a"; - - interrupts = , - , - ; - - interrupt-names = "global", "doorbell", "dma"; - - interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; - interconnect-names = "pcie-mem", "cpu-pcie"; - - dma-coherent; - iommus = <&pcie_smmu 0x0000 0x7f>; - resets = <&gcc GCC_PCIE_0_BCR>; - reset-names = "core"; - power-domains = <&gcc PCIE_0_GDSC>; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - num-lanes = <2>; - linux,pci-domain = <0>; - - status = "disabled"; - }; - - pcie0_phy: phy@1c04000 { - compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; - reg = <0x0 0x1c04000 0x0 0x2000>; - - clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_CLKREF_EN>, - <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, - <&gcc GCC_PCIE_0_PIPE_CLK>, - <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; - clock-names = "aux", - "cfg_ahb", - "ref", - "rchng", - "pipe", - "pipediv2"; - - assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; - assigned-clock-rates = <100000000>; - - resets = <&gcc GCC_PCIE_0_PHY_BCR>; - reset-names = "phy"; - - #clock-cells = <0>; - clock-output-names = "pcie_0_pipe_clk"; - - #phy-cells = <0>; - - status = "disabled"; - }; - - pcie1: pcie@1c10000 { - compatible = "qcom,pcie-sa8775p"; - reg = <0x0 0x01c10000 0x0 0x3000>, - <0x0 0x60000000 0x0 0xf20>, - <0x0 0x60000f20 0x0 0xa8>, - <0x0 0x60001000 0x0 0x4000>, - <0x0 0x60100000 0x0 0x100000>, - <0x0 0x01c13000 0x0 0x1000>; - reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, - <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; - bus-range = <0x00 0xff>; - - dma-coherent; - - linux,pci-domain = <1>; - num-lanes = <4>; - - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-names = "msi0", - "msi1", - "msi2", - "msi3", - "msi4", - "msi5", - "msi6", - "msi7", - "global"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&gcc GCC_PCIE_1_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; - - clock-names = "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a"; - - assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; - assigned-clock-rates = <19200000>; - - interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; - interconnect-names = "pcie-mem", "cpu-pcie"; - - iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, - <0x100 &pcie_smmu 0x0081 0x1>; - - resets = <&gcc GCC_PCIE_1_BCR>, - <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; - reset-names = "pci", - "link_down"; - - power-domains = <&gcc PCIE_1_GDSC>; - - phys = <&pcie1_phy>; - phy-names = "pciephy"; - - eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; - eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; - - status = "disabled"; - - pcie@0 { - device_type = "pci"; - reg = <0x0 0x0 0x0 0x0 0x0>; - bus-range = <0x01 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - }; - }; - - pcie1_ep: pcie-ep@1c10000 { - compatible = "qcom,sa8775p-pcie-ep"; - reg = <0x0 0x01c10000 0x0 0x3000>, - <0x0 0x60000000 0x0 0xf20>, - <0x0 0x60000f20 0x0 0xa8>, - <0x0 0x60001000 0x0 0x4000>, - <0x0 0x60200000 0x0 0x1fe00000>, - <0x0 0x01c13000 0x0 0x1000>, - <0x0 0x60005000 0x0 0x2000>; - reg-names = "parf", "dbi", "elbi", "atu", "addr_space", - "mmio", "dma"; - - clocks = <&gcc GCC_PCIE_1_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; - - clock-names = "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a"; - - interrupts = , - , - ; - - interrupt-names = "global", "doorbell", "dma"; - - interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; - interconnect-names = "pcie-mem", "cpu-pcie"; - - dma-coherent; - iommus = <&pcie_smmu 0x80 0x7f>; - resets = <&gcc GCC_PCIE_1_BCR>; - reset-names = "core"; - power-domains = <&gcc PCIE_1_GDSC>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - num-lanes = <4>; - linux,pci-domain = <1>; - - status = "disabled"; - }; - - pcie1_phy: phy@1c14000 { - compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; - reg = <0x0 0x1c14000 0x0 0x4000>; - - clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_CLKREF_EN>, - <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, - <&gcc GCC_PCIE_1_PIPE_CLK>, - <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; - clock-names = "aux", - "cfg_ahb", - "ref", - "rchng", - "pipe", - "pipediv2"; - - assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; - assigned-clock-rates = <100000000>; - - resets = <&gcc GCC_PCIE_1_PHY_BCR>; - reset-names = "phy"; - - #clock-cells = <0>; - clock-output-names = "pcie_1_pipe_clk"; - - #phy-cells = <0>; - - status = "disabled"; - }; }; From 4eacad2d8e3bd1115a65fd62ce5e08825706fa52 Mon Sep 17 00:00:00 2001 From: Paul Sajna Date: Wed, 8 Apr 2026 19:41:12 -0700 Subject: [PATCH 208/665] arm64: dts: qcom: sdm845-lg-common: Add camera flash Camera doesn't work yet (imx351), but we can use the flash as a flashlight. Reviewed-by: Konrad Dybcio Signed-off-by: Paul Sajna Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260408-judyln-followup-v1-1-823467519b59@postmarketos.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi index 71d070619ad7..9d82961d527e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi @@ -496,6 +496,19 @@ &pm8998_resin { status = "okay"; }; +&pmi8998_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <1>, <2>; + led-max-microamp = <100000>; + flash-max-microamp = <500000>; + flash-max-timeout-us = <500000>; + }; +}; + &pmi8998_lpg { status = "okay"; From d2735f569053092ca2a47367dce1594b985409e5 Mon Sep 17 00:00:00 2001 From: Paul Sajna Date: Wed, 8 Apr 2026 19:41:13 -0700 Subject: [PATCH 209/665] arm64: dts: qcom: sdm845-lg-common: Change ipa gsi-loader to 'self', add memory-region The modem firmware for this device doesn't preload the IPA firmware and requires the OS handles that instead. Set qcom,gsi-loader = "self" to reflect that. Ensure the ipa uses the correct memory. ipa 1e40000.ipa: channel 4 limited to 256 TREs ipa 1e40000.ipa: IPA driver initialized ipa 1e40000.ipa: received modem starting event ipa 1e40000.ipa: received modem running event Reviewed-by: Konrad Dybcio Signed-off-by: Paul Sajna Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260408-judyln-followup-v1-2-823467519b59@postmarketos.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi index 9d82961d527e..85dc4468b6c4 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi @@ -473,7 +473,9 @@ &gpu { }; &ipa { - qcom,gsi-loader = "modem"; + qcom,gsi-loader = "self"; + memory-region = <&ipa_fw_mem>; + status = "okay"; }; From 3f779220c64796df483c4cd47154d4ff1104a2e2 Mon Sep 17 00:00:00 2001 From: Paul Sajna Date: Wed, 8 Apr 2026 19:41:14 -0700 Subject: [PATCH 210/665] arm64: dts: qcom: sdm845-lg-{judyln, judyp}: Reference memory region in fb To prevent duplicating the framebuffer address and size point out the existing framebuffer memory region instead of specifying the address manually. Reviewed-by: Konrad Dybcio Signed-off-by: Paul Sajna Reviewed-by: David Heidelberg Link: https://lore.kernel.org/r/20260408-judyln-followup-v1-3-823467519b59@postmarketos.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi | 3 +-- arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts | 4 ++-- arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts | 4 ++-- 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi index 85dc4468b6c4..86cf4eb44084 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi @@ -98,8 +98,7 @@ spss_mem: memory@99000000 { no-map; }; - /* Framebuffer region */ - memory@9d400000 { + framebuffer_mem: memory@9d400000 { reg = <0x0 0x9d400000 0x0 0x2400000>; no-map; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts b/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts index adf41aa0146a..349faa123ff1 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts @@ -14,9 +14,9 @@ / { compatible = "lg,judyln", "qcom,sdm845"; chosen { - framebuffer@9d400000 { + framebuffer { compatible = "simple-framebuffer"; - reg = <0x0 0x9d400000 0x0 (1440 * 3120 * 4)>; + memory-region = <&framebuffer_mem>; width = <1440>; height = <3120>; stride = <(1440 * 4)>; diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts b/arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts index d244ebdd17be..44e762f78e95 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts @@ -14,9 +14,9 @@ / { compatible = "lg,judyp", "qcom,sdm845"; chosen { - framebuffer@9d400000 { + framebuffer { compatible = "simple-framebuffer"; - reg = <0x0 0x9d400000 0x0 (1440 * 2880 * 4)>; + memory-region = <&framebuffer_mem>; width = <1440>; height = <2880>; stride = <(1440 * 4)>; From 0f7c65c11f59332ec6d02bf0482a283510efd03a Mon Sep 17 00:00:00 2001 From: Paul Sajna Date: Wed, 8 Apr 2026 19:41:15 -0700 Subject: [PATCH 211/665] arm64: dts: qcom: sdm845-lg: Enable qcom,snoc-host-cap-skip-quirk The WCN3990 firmware for judyln does not respond to the request for host capabilities. Add the devicetree quirk to skip this request. Signed-off-by: Paul Sajna Reviewed-by: David Heidelberg Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260408-judyln-followup-v1-4-823467519b59@postmarketos.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi index 86cf4eb44084..e0c3566761bf 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi @@ -694,5 +694,7 @@ &wifi { vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; + qcom,snoc-host-cap-skip-quirk; + status = "okay"; }; From bde860892c92a43624a7bcf932a1d375b1ad43eb Mon Sep 17 00:00:00 2001 From: Xin Liu Date: Thu, 16 Apr 2026 22:42:00 -0700 Subject: [PATCH 212/665] arm64: dts: qcom: purwa: Add EL2 overlay for purwa-iot-evk Add support for building an EL2 combined DTB for the purwa-iot-evk in the Qualcomm DTS Makefile. The new purwa-iot-evk-el2.dtb is generated by combining the base purwa-iot-evk.dtb with the x1-el2.dtbo overlay, enabling EL2-specific configurations required by the platform. Signed-off-by: Xin Liu Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260417054200.2402281-1-xin.liu@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index cc42829f92eb..35252ea586a5 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -158,6 +158,10 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-maple.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-xiaomi-sagit.dtb dtb-$(CONFIG_ARCH_QCOM) += purwa-iot-evk.dtb + +purwa-iot-evk-el2-dtbs := purwa-iot-evk.dtb x1-el2.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += purwa-iot-evk-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += qcm6490-fairphone-fp5.dtb dtb-$(CONFIG_ARCH_QCOM) += qcm6490-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += qcm6490-particle-tachyon.dtb From 630398127110753474576cbc0cd4ad102b18005e Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 30 Apr 2026 09:10:44 +0200 Subject: [PATCH 213/665] arm64: dts: qcom: sm6350: add LPASS LPI pin controller Add LPASS LPI pinctrl node required for audio functionality on SM6350. Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20260430-sm6350-lpi-tlmm-v2-4-81d068025b97@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 66 ++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 034545d2af2d..d6adf68563cb 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1450,6 +1450,72 @@ compute-cb@5 { }; }; + lpass_tlmm: pinctrl@33c0000 { + compatible = "qcom,sm6350-lpass-lpi-pinctrl"; + reg = <0x0 0x033c0000 0x0 0x20000>, + <0x0 0x03550000 0x0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 15>; + + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", + "audio"; + + i2s1_active: i2s1-active-state { + clk-pins { + pins = "gpio6"; + function = "i2s1_clk"; + drive-strength = <8>; + bias-disable; + output-high; + }; + + ws-pins { + pins = "gpio7"; + function = "i2s1_ws"; + drive-strength = <8>; + bias-disable; + output-high; + }; + + data-pins { + pins = "gpio8", "gpio9"; + function = "i2s1_data"; + drive-strength = <8>; + bias-disable; + output-high; + }; + }; + + i2s1_sleep: i2s1-sleep-state { + clk-pins { + pins = "gpio6"; + function = "i2s1_clk"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + + ws-pins { + pins = "gpio7"; + function = "i2s1_ws"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + + data-pins { + pins = "gpio8", "gpio9"; + function = "i2s1_data"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + }; + gpu: gpu@3d00000 { compatible = "qcom,adreno-619.0", "qcom,adreno"; reg = <0x0 0x03d00000 0x0 0x40000>, From b1b08554e3be97712febad9d4d9ad617a1a32af1 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 30 Apr 2026 09:10:45 +0200 Subject: [PATCH 214/665] arm64: defconfig: Enable LPASS LPI pin controller for SM6350 Build the LPASS LPI pin controller driver for SM6350 as module, which is required for audio functionality on boards such as the Fairphone 4. Reviewed-by: Dmitry Baryshkov Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20260430-sm6350-lpi-tlmm-v2-5-81d068025b97@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index d905a0777f93..1f0cd5c22537 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -703,6 +703,7 @@ CONFIG_PINCTRL_LPASS_LPI=m CONFIG_PINCTRL_MILOS_LPASS_LPI=m CONFIG_PINCTRL_SC7280_LPASS_LPI=m CONFIG_PINCTRL_SM6115_LPASS_LPI=m +CONFIG_PINCTRL_SM6350_LPASS_LPI=m CONFIG_PINCTRL_SM8250_LPASS_LPI=m CONFIG_PINCTRL_SM8450_LPASS_LPI=m CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m From 627aab9bfe03613c9f0142d5a70faa7ff9634569 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Tue, 28 Apr 2026 15:32:29 +0300 Subject: [PATCH 215/665] arm64: dts: qcom: glymur-crd: Enable LID sensor The Glymur CRD has a Hall-effect sensor used for detecting when the lid is opened or closed. Describe it as an SW_LID gpio-key switch. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260428-glymur-dts-add-lid-sensor-v1-1-470cc168e70a@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi index 2852d257ac8c..357d4ad8380a 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -10,6 +10,8 @@ #include "pmk8850.dtsi" /* SPMI0: SID-0 */ #include "smb2370.dtsi" /* SPMI2: SID-9/10/11 */ +#include + / { model = "Qualcomm Technologies, Inc. Glymur CRD"; compatible = "qcom,glymur-crd", "qcom,glymur"; @@ -44,7 +46,7 @@ sleep_clk: sleep-clk { gpio-keys { compatible = "gpio-keys"; - pinctrl-0 = <&key_vol_up_default>; + pinctrl-0 = <&key_vol_up_default>, <&hall_int_n_default>; pinctrl-names = "default"; key-volume-up { @@ -55,6 +57,15 @@ key-volume-up { linux,can-disable; wakeup-source; }; + + switch-lid { + label = "lid"; + gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-source; + wakeup-event-action = ; + }; }; vreg_nvme: regulator-nvme { @@ -565,6 +576,12 @@ &tlmm { <10 2>, /* OOB UART */ <44 4>; /* Security SPI (TPM) */ + hall_int_n_default: hall-int-n-state { + pins = "gpio92"; + function = "gpio"; + bias-disable; + }; + pcie4_default: pcie4-default-state { clkreq-n-pins { pins = "gpio147"; From f5fb358c7d9161a6abfd2c619b2999c7e51cd2fe Mon Sep 17 00:00:00 2001 From: Haritha S K Date: Thu, 7 May 2026 11:59:50 +0530 Subject: [PATCH 216/665] arm64: dts: qcom: glymur: Enable cpufreq cooling devices Add cooling-cells property to the CPU nodes to support cpufreq cooling devices. Signed-off-by: Haritha S K Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260507-glymur_cpu_freq-v1-1-d566cc1d32c3@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 2378b7a4a30d..65c8e9233354 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -39,6 +39,7 @@ cpu0: cpu@0 { power-domains = <&cpu_pd0>, <&scmi_perf 0>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_0>; + #cooling-cells = <2>; l2_0: l2-cache { compatible = "cache"; @@ -55,6 +56,7 @@ cpu1: cpu@100 { power-domains = <&cpu_pd1>, <&scmi_perf 0>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_0>; + #cooling-cells = <2>; }; cpu2: cpu@200 { @@ -65,6 +67,7 @@ cpu2: cpu@200 { power-domains = <&cpu_pd2>, <&scmi_perf 0>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_0>; + #cooling-cells = <2>; }; cpu3: cpu@300 { @@ -75,6 +78,7 @@ cpu3: cpu@300 { power-domains = <&cpu_pd3>, <&scmi_perf 0>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_0>; + #cooling-cells = <2>; }; cpu4: cpu@400 { @@ -85,6 +89,7 @@ cpu4: cpu@400 { power-domains = <&cpu_pd4>, <&scmi_perf 0>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_0>; + #cooling-cells = <2>; }; cpu5: cpu@500 { @@ -95,6 +100,7 @@ cpu5: cpu@500 { power-domains = <&cpu_pd5>, <&scmi_perf 0>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_0>; + #cooling-cells = <2>; }; cpu6: cpu@10000 { @@ -105,6 +111,7 @@ cpu6: cpu@10000 { power-domains = <&cpu_pd6>, <&scmi_perf 1>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_1>; + #cooling-cells = <2>; l2_1: l2-cache { compatible = "cache"; @@ -121,6 +128,7 @@ cpu7: cpu@10100 { power-domains = <&cpu_pd7>, <&scmi_perf 1>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_1>; + #cooling-cells = <2>; }; cpu8: cpu@10200 { @@ -131,6 +139,7 @@ cpu8: cpu@10200 { power-domains = <&cpu_pd8>, <&scmi_perf 1>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_1>; + #cooling-cells = <2>; }; cpu9: cpu@10300 { @@ -141,6 +150,7 @@ cpu9: cpu@10300 { power-domains = <&cpu_pd9>, <&scmi_perf 1>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_1>; + #cooling-cells = <2>; }; cpu10: cpu@10400 { @@ -151,6 +161,7 @@ cpu10: cpu@10400 { power-domains = <&cpu_pd10>, <&scmi_perf 1>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_1>; + #cooling-cells = <2>; }; cpu11: cpu@10500 { @@ -161,6 +172,7 @@ cpu11: cpu@10500 { power-domains = <&cpu_pd11>, <&scmi_perf 1>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_1>; + #cooling-cells = <2>; }; cpu12: cpu@20000 { @@ -171,6 +183,7 @@ cpu12: cpu@20000 { power-domains = <&cpu_pd12>, <&scmi_perf 2>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_2>; + #cooling-cells = <2>; l2_2: l2-cache { compatible = "cache"; @@ -187,6 +200,7 @@ cpu13: cpu@20100 { power-domains = <&cpu_pd13>, <&scmi_perf 2>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_2>; + #cooling-cells = <2>; }; cpu14: cpu@20200 { @@ -197,6 +211,7 @@ cpu14: cpu@20200 { power-domains = <&cpu_pd14>, <&scmi_perf 2>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_2>; + #cooling-cells = <2>; }; cpu15: cpu@20300 { @@ -207,6 +222,7 @@ cpu15: cpu@20300 { power-domains = <&cpu_pd15>, <&scmi_perf 2>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_2>; + #cooling-cells = <2>; }; cpu16: cpu@20400 { @@ -217,6 +233,7 @@ cpu16: cpu@20400 { power-domains = <&cpu_pd16>, <&scmi_perf 2>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_2>; + #cooling-cells = <2>; }; cpu17: cpu@20500 { @@ -227,6 +244,7 @@ cpu17: cpu@20500 { power-domains = <&cpu_pd17>, <&scmi_perf 2>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_2>; + #cooling-cells = <2>; }; cpu-map { From aa771fbe696a8f9d7884409a271558217be08d32 Mon Sep 17 00:00:00 2001 From: Devin Li Date: Wed, 6 May 2026 10:52:54 +0800 Subject: [PATCH 217/665] arm64: dts: cix: Add SCMI performance domains for CPUFreq on Sky1 Add SCMI Protocol 13 (Performance) node under ap_to_pm_scmi with domains. Define SKY1_PERF_* macros in sky1-power.h for all performance domain IDs (CPU L/B0/B1/M0/M1, GPU, DSU, NPU, VPU, CI700, NI700), and wire each CPU node to its corresponding performance domain using power-domains and power-domain-names properties. Signed-off-by: Devin Li Link: https://lore.kernel.org/r/20260506025254.3602623-1-Devin.Li@cixtech.com Signed-off-by: Peter Chen --- arch/arm64/boot/dts/cix/sky1-power.h | 13 +++++++++++++ arch/arm64/boot/dts/cix/sky1.dtsi | 29 ++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/cix/sky1-power.h b/arch/arm64/boot/dts/cix/sky1-power.h index 53f4a3af36b3..144567579b71 100644 --- a/arch/arm64/boot/dts/cix/sky1-power.h +++ b/arch/arm64/boot/dts/cix/sky1-power.h @@ -30,4 +30,17 @@ #define SKY1_PD_ISP0 20 #define SKY1_PD_GPU 21 +#define SKY1_PERF_GPU_CORE 0 +#define SKY1_PERF_GPU_TOP 1 +#define SKY1_PERF_CPU_L 2 +#define SKY1_PERF_CPU_B0 3 +#define SKY1_PERF_CPU_B1 4 +#define SKY1_PERF_CPU_M0 5 +#define SKY1_PERF_CPU_M1 6 +#define SKY1_PERF_DSU 7 +#define SKY1_PERF_NPU 8 +#define SKY1_PERF_VPU 9 +#define SKY1_PERF_CI700 10 +#define SKY1_PERF_NI700 11 + #endif diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi index bb5cfb1f2113..9f80e1aa070a 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -22,6 +22,8 @@ cpu0: cpu@0 { enable-method = "psci"; reg = <0x0 0x0>; device_type = "cpu"; + power-domains = <&scmi_dvfs SKY1_PERF_CPU_L>; + power-domain-names = "perf"; capacity-dmips-mhz = <403>; }; @@ -30,6 +32,8 @@ cpu1: cpu@100 { enable-method = "psci"; reg = <0x0 0x100>; device_type = "cpu"; + power-domains = <&scmi_dvfs SKY1_PERF_CPU_L>; + power-domain-names = "perf"; capacity-dmips-mhz = <403>; }; @@ -38,6 +42,8 @@ cpu2: cpu@200 { enable-method = "psci"; reg = <0x0 0x200>; device_type = "cpu"; + power-domains = <&scmi_dvfs SKY1_PERF_CPU_L>; + power-domain-names = "perf"; capacity-dmips-mhz = <403>; }; @@ -46,6 +52,8 @@ cpu3: cpu@300 { enable-method = "psci"; reg = <0x0 0x300>; device_type = "cpu"; + power-domains = <&scmi_dvfs SKY1_PERF_CPU_L>; + power-domain-names = "perf"; capacity-dmips-mhz = <403>; }; @@ -54,6 +62,8 @@ cpu4: cpu@400 { enable-method = "psci"; reg = <0x0 0x400>; device_type = "cpu"; + power-domains = <&scmi_dvfs SKY1_PERF_CPU_M0>; + power-domain-names = "perf"; capacity-dmips-mhz = <1024>; }; @@ -62,6 +72,8 @@ cpu5: cpu@500 { enable-method = "psci"; reg = <0x0 0x500>; device_type = "cpu"; + power-domains = <&scmi_dvfs SKY1_PERF_CPU_M0>; + power-domain-names = "perf"; capacity-dmips-mhz = <1024>; }; @@ -70,6 +82,8 @@ cpu6: cpu@600 { enable-method = "psci"; reg = <0x0 0x600>; device_type = "cpu"; + power-domains = <&scmi_dvfs SKY1_PERF_CPU_M1>; + power-domain-names = "perf"; capacity-dmips-mhz = <1024>; }; @@ -78,6 +92,8 @@ cpu7: cpu@700 { enable-method = "psci"; reg = <0x0 0x700>; device_type = "cpu"; + power-domains = <&scmi_dvfs SKY1_PERF_CPU_M1>; + power-domain-names = "perf"; capacity-dmips-mhz = <1024>; }; @@ -86,6 +102,8 @@ cpu8: cpu@800 { enable-method = "psci"; reg = <0x0 0x800>; device_type = "cpu"; + power-domains = <&scmi_dvfs SKY1_PERF_CPU_B0>; + power-domain-names = "perf"; capacity-dmips-mhz = <1024>; }; @@ -94,6 +112,8 @@ cpu9: cpu@900 { enable-method = "psci"; reg = <0x0 0x900>; device_type = "cpu"; + power-domains = <&scmi_dvfs SKY1_PERF_CPU_B0>; + power-domain-names = "perf"; capacity-dmips-mhz = <1024>; }; @@ -102,6 +122,8 @@ cpu10: cpu@a00 { enable-method = "psci"; reg = <0x0 0xa00>; device_type = "cpu"; + power-domains = <&scmi_dvfs SKY1_PERF_CPU_B1>; + power-domain-names = "perf"; capacity-dmips-mhz = <1024>; }; @@ -110,6 +132,8 @@ cpu11: cpu@b00 { enable-method = "psci"; reg = <0x0 0xb00>; device_type = "cpu"; + power-domains = <&scmi_dvfs SKY1_PERF_CPU_B1>; + power-domain-names = "perf"; capacity-dmips-mhz = <1024>; }; @@ -164,6 +188,11 @@ ap_to_pm_scmi: scmi { #address-cells = <1>; #size-cells = <0>; + scmi_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + scmi_clk: protocol@14 { reg = <0x14>; #clock-cells = <1>; From 89d0ad7f3a60d3076da2d90ece8d78d0eb60bb91 Mon Sep 17 00:00:00 2001 From: Devin Li Date: Thu, 7 May 2026 14:59:56 +0800 Subject: [PATCH 218/665] arm64: dts: cix: Add CPU idle states for Sky1 Add PSCI-based CPU idle state definitions for the Sky1 SoC, enabling core and cluster level power management through ARM PSCI firmware. Three idle states are defined: - CPU_SLEEP_0: Core idle state for A520 cores (psci-suspend-param 0x0010000), entry-latency 34us, exit-latency 100us - CPU_SLEEP_1: Core idle state for A720 cores (psci-suspend-param 0x10000), entry-latency 31us, exit-latency 79us - CLUSTER_SLEEP_0: Cluster idle state shared by all cores (psci-suspend-param 0x1010000), entry-latency 41us, exit-latency 104us A520 cores (cpu0-3) reference CPU_SLEEP_0 and CLUSTER_SLEEP_0, while A720 cores (cpu4-11) reference CPU_SLEEP_1 and CLUSTER_SLEEP_0. Signed-off-by: Devin Li Link: https://lore.kernel.org/r/20260507065956.3900087-1-Devin.Li@cixtech.com Signed-off-by: Peter Chen --- arch/arm64/boot/dts/cix/sky1.dtsi | 41 +++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi index 9f80e1aa070a..a77c52296ebd 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -25,6 +25,7 @@ cpu0: cpu@0 { power-domains = <&scmi_dvfs SKY1_PERF_CPU_L>; power-domain-names = "perf"; capacity-dmips-mhz = <403>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu1: cpu@100 { @@ -35,6 +36,7 @@ cpu1: cpu@100 { power-domains = <&scmi_dvfs SKY1_PERF_CPU_L>; power-domain-names = "perf"; capacity-dmips-mhz = <403>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu2: cpu@200 { @@ -45,6 +47,7 @@ cpu2: cpu@200 { power-domains = <&scmi_dvfs SKY1_PERF_CPU_L>; power-domain-names = "perf"; capacity-dmips-mhz = <403>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu3: cpu@300 { @@ -55,6 +58,7 @@ cpu3: cpu@300 { power-domains = <&scmi_dvfs SKY1_PERF_CPU_L>; power-domain-names = "perf"; capacity-dmips-mhz = <403>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu4: cpu@400 { @@ -65,6 +69,7 @@ cpu4: cpu@400 { power-domains = <&scmi_dvfs SKY1_PERF_CPU_M0>; power-domain-names = "perf"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; }; cpu5: cpu@500 { @@ -75,6 +80,7 @@ cpu5: cpu@500 { power-domains = <&scmi_dvfs SKY1_PERF_CPU_M0>; power-domain-names = "perf"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; }; cpu6: cpu@600 { @@ -85,6 +91,7 @@ cpu6: cpu@600 { power-domains = <&scmi_dvfs SKY1_PERF_CPU_M1>; power-domain-names = "perf"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; }; cpu7: cpu@700 { @@ -95,6 +102,7 @@ cpu7: cpu@700 { power-domains = <&scmi_dvfs SKY1_PERF_CPU_M1>; power-domain-names = "perf"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; }; cpu8: cpu@800 { @@ -105,6 +113,7 @@ cpu8: cpu@800 { power-domains = <&scmi_dvfs SKY1_PERF_CPU_B0>; power-domain-names = "perf"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; }; cpu9: cpu@900 { @@ -115,6 +124,7 @@ cpu9: cpu@900 { power-domains = <&scmi_dvfs SKY1_PERF_CPU_B0>; power-domain-names = "perf"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; }; cpu10: cpu@a00 { @@ -125,6 +135,7 @@ cpu10: cpu@a00 { power-domains = <&scmi_dvfs SKY1_PERF_CPU_B1>; power-domain-names = "perf"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; }; cpu11: cpu@b00 { @@ -135,6 +146,7 @@ cpu11: cpu@b00 { power-domains = <&scmi_dvfs SKY1_PERF_CPU_B1>; power-domain-names = "perf"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; }; cpu-map { @@ -177,6 +189,35 @@ core11 { }; }; }; + + idle-states { + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <34>; + exit-latency-us = <100>; + min-residency-us = <3000>; + }; + + CPU_SLEEP_1: cpu-sleep-1 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <31>; + exit-latency-us = <79>; + min-residency-us = <3000>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1010000>; + local-timer-stop; + entry-latency-us = <41>; + exit-latency-us = <104>; + min-residency-us = <4000>; + }; + }; }; firmware { From 003ff312269cc9defdd6b12462b1e89f4c9423d7 Mon Sep 17 00:00:00 2001 From: Michal Piekos Date: Wed, 6 May 2026 17:10:28 +0200 Subject: [PATCH 219/665] riscv: dts: allwinner: d1s-t113: add hstimer node Describe high speed timer block on Allwinner D1S-T113. Tested on LCPI-PC-T113/F113: - hstimer is registered as clocksource - switching clocksource at runtime works - after rating increase hstimer operates as a broadcast clockevent device Signed-off-by: Michal Piekos Reviewed-by: Chen-Yu Tsai Link: https://patch.msgid.link/20260506-h616-t113s-hstimer-v4-3-591d425863d6@mmpsystems.pl [wens@kernel.org: change subject prefix from "arm" to "riscv"] [wens@kernel.org: fix interrupt representation] Signed-off-by: Chen-Yu Tsai --- arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index 82cc85acccb1..a810ad3eb2a2 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -295,6 +295,15 @@ timer: timer@2050000 { clocks = <&dcxo>; }; + hstimer@3008000 { + compatible = "allwinner,sun20i-d1-hstimer"; + reg = <0x03008000 0x1000>; + interrupts = , + ; + clocks = <&ccu CLK_BUS_HSTIMER>; + resets = <&ccu RST_BUS_HSTIMER>; + }; + wdt: watchdog@20500a0 { compatible = "allwinner,sun20i-d1-wdt-reset", "allwinner,sun20i-d1-wdt"; From 2d2c7e532ec325240068ac8d53d94cc0133c06f6 Mon Sep 17 00:00:00 2001 From: Michal Piekos Date: Wed, 6 May 2026 17:10:29 +0200 Subject: [PATCH 220/665] arm64: dts: allwinner: h616: add hstimer node Describe high speed timer block on Allwinner H616. Tested on Orange Pi Zero 3: - hstimer is registered as clocksource - switching clocksource at runtime works - after rating increase hstimer operates as a broadcast clockevent device Signed-off-by: Michal Piekos Reviewed-by: Chen-Yu Tsai Link: https://patch.msgid.link/20260506-h616-t113s-hstimer-v4-4-591d425863d6@mmpsystems.pl Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index b116d3c12881..1598e86259ab 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -263,6 +263,16 @@ timer0: timer@3009000 { clocks = <&osc24M>; }; + hstimer@3005000 { + compatible = "allwinner,sun50i-h616-hstimer", + "allwinner,sun20i-d1-hstimer"; + reg = <0x03005000 0x1000>; + interrupts = , + ; + clocks = <&ccu CLK_BUS_HSTIMER>; + resets = <&ccu RST_BUS_HSTIMER>; + }; + watchdog: watchdog@30090a0 { compatible = "allwinner,sun50i-h616-wdt", "allwinner,sun6i-a31-wdt"; From cb8eba42e31854c07f7891a0c9955e7ae8be2d93 Mon Sep 17 00:00:00 2001 From: Michal Piekos Date: Wed, 6 May 2026 12:14:31 +0200 Subject: [PATCH 221/665] arm: dts: allwinner: t113s: enable watchdog for reboot Reboot hangs on T113s boards because no restart handler is available. Enable the SoC watchdog whose driver registers a restart handler. Tested on LCPI-PC-T113/F113. Signed-off-by: Michal Piekos Link: https://patch.msgid.link/20260506-t113-mangopi-reboot-hang-v3-1-fa15a360a520@mmpsystems.pl Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi index 424f4a2487e2..3ca0897353be 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi @@ -90,3 +90,7 @@ cpu-crit { }; }; }; + +&wdt { + status = "okay"; +}; From 83cd5b94773c11192c4eef4ad51cadac218b357d Mon Sep 17 00:00:00 2001 From: Yu-Chun Lin Date: Tue, 5 May 2026 18:58:36 +0800 Subject: [PATCH 222/665] arm64: dts: realtek: Add pinctrl support for RTD1625 Add the pinctrl nodes for the Realtek RTD1625 SoC. Reviewed-by: Linus Walleij Signed-off-by: Yu-Chun Lin Link: https://lore.kernel.org/r/20260505105838.1014771-1-eleanor.lin@realtek.com Signed-off-by: Arnd Bergmann --- arch/arm64/boot/dts/realtek/kent.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/realtek/kent.dtsi b/arch/arm64/boot/dts/realtek/kent.dtsi index ae006ce24420..8d4293cd4c03 100644 --- a/arch/arm64/boot/dts/realtek/kent.dtsi +++ b/arch/arm64/boot/dts/realtek/kent.dtsi @@ -150,6 +150,26 @@ uart0: serial@7800 { reg-shift = <2>; status = "disabled"; }; + + iso_pinctrl: pinctrl@4e000 { + compatible = "realtek,rtd1625-iso-pinctrl"; + reg = <0x4e000 0x1a4>; + }; + + main2_pinctrl: pinctrl@4f200 { + compatible = "realtek,rtd1625-main2-pinctrl"; + reg = <0x4f200 0x50>; + }; + + isom_pinctrl: pinctrl@146200 { + compatible = "realtek,rtd1625-isom-pinctrl"; + reg = <0x146200 0x34>; + }; + + ve4_pinctrl: pinctrl@14e000 { + compatible = "realtek,rtd1625-ve4-pinctrl"; + reg = <0x14e000 0x84>; + }; }; gic: interrupt-controller@ff100000 { From b133e22edd5c4d43398b0656063457e7ccf32778 Mon Sep 17 00:00:00 2001 From: Mohamed Ayman Date: Tue, 5 May 2026 11:36:07 +0200 Subject: [PATCH 223/665] ARM: dts: ixp4xx: use phandle-based GPIOs in mi424wr Convert remaining legacy integer GPIO specifiers to phandle-based descriptors in intel-ixp42x-actiontec-mi424wr.dtsi. All other GPIOs in this file already use &gpio0/&gpio1. These are the last remaining legacy users in the IXP4xx DTS files. Signed-off-by: Mohamed Ayman Link: https://lore.kernel.org/20260428191029.809462-1-mohamedaymanworkspace@gmail.com Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20260505-ixp4xx-dts-v1-1-02f4a92a9697@kernel.org Signed-off-by: Arnd Bergmann --- .../boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi index 9b54e3c01a34..3043ae7232dd 100644 --- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi @@ -195,19 +195,19 @@ gpio1: gpio@1,0 { pci-reset-hog { gpio-hog; - gpios = <7 GPIO_ACTIVE_HIGH>; + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; output-high; line-name = "PCI reset"; }; pstn-relay-hog-1 { gpio-hog; - gpios = <11 GPIO_ACTIVE_HIGH>; + gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; output-low; line-name = "PSTN relay control 1"; }; pstn-relay-hog-2 { gpio-hog; - gpios = <12 GPIO_ACTIVE_HIGH>; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; output-low; line-name = "PSTN relay control 2"; }; From 9c45ef9a84bd18cbd2052d5e64b2144018f5bb32 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 17 Mar 2026 10:16:14 +0000 Subject: [PATCH 224/665] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Document reset-names All SoCs have multiple resets. Document the reset-names property. Acked-by: Conor Dooley Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260317101627.174491-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index 00c05243b9a4..1a94e396b1b0 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -78,6 +78,16 @@ properties: - description: PFC main reset - description: Reset for the control register related to WDTUDFCA and WDTUDFFCM pins + reset-names: + oneOf: + - items: + - const: rstn + - const: port + - const: spare + - items: + - const: main + - const: error + additionalProperties: anyOf: - type: object @@ -152,10 +162,14 @@ allOf: properties: resets: maxItems: 2 + reset-names: + maxItems: 2 else: properties: resets: minItems: 3 + reset-names: + minItems: 3 required: - compatible @@ -187,6 +201,7 @@ examples: resets = <&cpg R9A07G044_GPIO_RSTN>, <&cpg R9A07G044_GPIO_PORT_RESETN>, <&cpg R9A07G044_GPIO_SPARE_RESETN>; + reset-names = "rstn", "port", "spare"; power-domains = <&cpg>; scif0_pins: serial0 { From 43d2cd6f61ffc04be19f4c7542554e4d28786a17 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 30 Apr 2026 10:34:06 +0100 Subject: [PATCH 225/665] dt-bindings: pinctrl: renesas: Document RZ/G3L SoC Add documentation for the pin controller found on the Renesas RZ/G3L (R9A08G046) SoC. The RZ/G3L PFC is similar to the RZ/G3S SoC but has more pins. Also add header file similar to RZ/G3E and RZ/V2H as it has alpha numeric ports. Document renesas,clonech property for controlling clone channel control register located on SYSC IP block on RZ/G3L SoC. Acked-by: Conor Dooley Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260430093422.74812-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../pinctrl/renesas,rzg2l-pinctrl.yaml | 20 ++++++++++ .../pinctrl/renesas,r9a08g046-pinctrl.h | 38 +++++++++++++++++++ 2 files changed, 58 insertions(+) create mode 100644 include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index 1a94e396b1b0..fb1fe1ea759f 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -26,6 +26,7 @@ properties: - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} - renesas,r9a08g045-pinctrl # RZ/G3S + - renesas,r9a08g046-pinctrl # RZ/G3L - renesas,r9a09g047-pinctrl # RZ/G3E - renesas,r9a09g056-pinctrl # RZ/V2N - renesas,r9a09g057-pinctrl # RZ/V2H(P) @@ -88,6 +89,16 @@ properties: - const: main - const: error + renesas,clonech: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to system controller + - description: offset of clone channel control register + description: + Phandle and offset to the system controller containing the clone channel + control values. + additionalProperties: anyOf: - type: object @@ -150,6 +161,15 @@ additionalProperties: allOf: - $ref: pinctrl.yaml# + - if: + properties: + compatible: + contains: + const: renesas,r9a08g046-pinctrl + then: + required: + - renesas,clonech + - if: properties: compatible: diff --git a/include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h b/include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h new file mode 100644 index 000000000000..5ec5bfc27c7d --- /dev/null +++ b/include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * This header provides constants for Renesas RZ/G3L family pinctrl bindings. + * + * Copyright (C) 2026 Renesas Electronics Corp. + * + */ + +#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__ +#define __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__ + +#include + +/* RZG3L_Px = Offset address of PFC_P_mn - 0x22 */ +#define RZG3L_P2 2 +#define RZG3L_P3 3 +#define RZG3L_P5 5 +#define RZG3L_P6 6 +#define RZG3L_P7 7 +#define RZG3L_P8 8 +#define RZG3L_PA 10 +#define RZG3L_PB 11 +#define RZG3L_PC 12 +#define RZG3L_PD 13 +#define RZG3L_PE 14 +#define RZG3L_PF 15 +#define RZG3L_PG 16 +#define RZG3L_PH 17 +#define RZG3L_PJ 19 +#define RZG3L_PK 20 +#define RZG3L_PL 21 +#define RZG3L_PM 22 +#define RZG3L_PS 28 + +#define RZG3L_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZG3L_P##b, p, f) +#define RZG3L_GPIO(port, pin) RZG2L_GPIO(RZG3L_P##port, pin) + +#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__ */ From 2a5d54507c68c2a8de9d6f6746f23771d38f4dbc Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Wed, 25 Mar 2026 23:45:00 +0900 Subject: [PATCH 226/665] arm: dts: mediatek: mt6589: Add Arm Generic Timer node Add the Arm Generic Timer node to the MT6589 SoC. "arm,cpu-registers-not-fw-configured;" is required because the bootloader does not initialize the Arm Generic Timer. Signed-off-by: Akari Tsuyukusa Signed-off-by: AngeloGioacchino Del Regno --- arch/arm/boot/dts/mediatek/mt6589.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index c6babc8ad2ba..46dea445742b 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -42,6 +42,17 @@ cpu@3 { }; + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + clock-frequency = <13000000>; + arm,cpu-registers-not-fw-configured; + }; + clocks { #address-cells = <1>; #size-cells = <1>; From 23d304b97e8e20b8d786b82b4d56257dde95139c Mon Sep 17 00:00:00 2001 From: David Lechner Date: Thu, 5 Mar 2026 15:03:16 -0600 Subject: [PATCH 227/665] arm: dts: mediatek: mt7623: fix pinctrl child node names Fix the pinctrl child node names to adhere to the bindings. The main pin node is supposed to be named like "something-pins" and the pinmux node named like "pins-something". Signed-off-by: David Lechner Signed-off-by: AngeloGioacchino Del Regno --- arch/arm/boot/dts/mediatek/mt7623.dtsi | 62 +++++++++++++------------- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/arch/arm/boot/dts/mediatek/mt7623.dtsi b/arch/arm/boot/dts/mediatek/mt7623.dtsi index 71ac2b94c6ba..f34f60cde594 100644 --- a/arch/arm/boot/dts/mediatek/mt7623.dtsi +++ b/arch/arm/boot/dts/mediatek/mt7623.dtsi @@ -1017,14 +1017,14 @@ bdpsys: syscon@1c000000 { }; &pio { - cir_pins_a:cir-default { + cir_pins_a: cir-default-pins { pins-cir { pinmux = ; bias-disable; }; }; - i2c0_pins_a: i2c0-default { + i2c0_pins_a: i2c0-default-pins { pins-i2c0 { pinmux = , ; @@ -1032,40 +1032,40 @@ pins-i2c0 { }; }; - i2c1_pins_a: i2c1-default { - pin-i2c1 { + i2c1_pins_a: i2c1-default-pins { + pins-i2c1 { pinmux = , ; bias-disable; }; }; - i2c1_pins_b: i2c1-alt { - pin-i2c1 { + i2c1_pins_b: i2c1-alt-pins { + pins-i2c1 { pinmux = , ; bias-disable; }; }; - i2c2_pins_a: i2c2-default { - pin-i2c2 { + i2c2_pins_a: i2c2-default-pins { + pins-i2c2 { pinmux = , ; bias-disable; }; }; - i2c2_pins_b: i2c2-alt { - pin-i2c2 { + i2c2_pins_b: i2c2-alt-pins { + pins-i2c2 { pinmux = , ; bias-disable; }; }; - i2s0_pins_a: i2s0-default { - pin-i2s0 { + i2s0_pins_a: i2s0-default-pins { + pins-i2s0 { pinmux = , , , @@ -1076,8 +1076,8 @@ pin-i2s0 { }; }; - i2s1_pins_a: i2s1-default { - pin-i2s1 { + i2s1_pins_a: i2s1-default-pins { + pins-i2s1 { pinmux = , , , @@ -1088,7 +1088,7 @@ pin-i2s1 { }; }; - key_pins_a: keys-alt { + key_pins_a: keys-alt-pins { pins-keys { pinmux = , ; @@ -1096,7 +1096,7 @@ pins-keys { }; }; - led_pins_a: leds-alt { + led_pins_a: leds-alt-pins { pins-leds { pinmux = , , @@ -1104,7 +1104,7 @@ pins-leds { }; }; - mmc0_pins_default: mmc0default { + mmc0_pins_default: mmc0-default-pins { pins-cmd-dat { pinmux = , , @@ -1130,7 +1130,7 @@ pins-rst { }; }; - mmc0_pins_uhs: mmc0 { + mmc0_pins_uhs: mmc0-uhs-pins { pins-cmd-dat { pinmux = , , @@ -1158,7 +1158,7 @@ pins-rst { }; }; - mmc1_pins_default: mmc1default { + mmc1_pins_default: mmc1-default-pins { pins-cmd-dat { pinmux = , , @@ -1188,7 +1188,7 @@ pins-insert { }; }; - mmc1_pins_uhs: mmc1 { + mmc1_pins_uhs: mmc1-uhs-pins { pins-cmd-dat { pinmux = , , @@ -1207,7 +1207,7 @@ pins-clk { }; }; - nand_pins_default: nanddefault { + nand_pins_default: nand-default-pins { pins-ale { pinmux = ; drive-strength = <8>; @@ -1236,15 +1236,15 @@ pins-we { }; }; - pcie_default: pcie_pin_default { - pins_cmd_dat { + pcie_default: pcie-default-pins { + pins-cmd-dat { pinmux = , ; bias-disable; }; }; - pwm_pins_a: pwm-default { + pwm_pins_a: pwm-default-pins { pins-pwm { pinmux = , , @@ -1254,7 +1254,7 @@ pins-pwm { }; }; - spi0_pins_a: spi0-default { + spi0_pins_a: spi0-default-pins { pins-spi { pinmux = , , @@ -1264,7 +1264,7 @@ pins-spi { }; }; - spi1_pins_a: spi1-default { + spi1_pins_a: spi1-default-pins { pins-spi { pinmux = , , @@ -1273,7 +1273,7 @@ pins-spi { }; }; - spi2_pins_a: spi2-default { + spi2_pins_a: spi2-default-pins { pins-spi { pinmux = , , @@ -1282,28 +1282,28 @@ pins-spi { }; }; - uart0_pins_a: uart0-default { + uart0_pins_a: uart0-default-pins { pins-dat { pinmux = , ; }; }; - uart1_pins_a: uart1-default { + uart1_pins_a: uart1-default-pins { pins-dat { pinmux = , ; }; }; - uart2_pins_a: uart2-default { + uart2_pins_a: uart2-default-pins { pins-dat { pinmux = , ; }; }; - uart2_pins_b: uart2-alt { + uart2_pins_b: uart2-alt-pins { pins-dat { pinmux = , ; From 85fdc6458535d234e54d0968cc816dec9003d341 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Thu, 5 Mar 2026 15:03:17 -0600 Subject: [PATCH 228/665] arm: dts: mediatek: mt7623: fix pinctrl controller node name Correct the pinctrl controller node name to use the same address as the reg property. Signed-off-by: David Lechner Signed-off-by: AngeloGioacchino Del Regno --- arch/arm/boot/dts/mediatek/mt7623.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/mediatek/mt7623.dtsi b/arch/arm/boot/dts/mediatek/mt7623.dtsi index f34f60cde594..aa42377b47da 100644 --- a/arch/arm/boot/dts/mediatek/mt7623.dtsi +++ b/arch/arm/boot/dts/mediatek/mt7623.dtsi @@ -249,7 +249,7 @@ pericfg: syscon@10003000 { #reset-cells = <1>; }; - pio: pinctrl@10005000 { + pio: pinctrl@1000b000 { compatible = "mediatek,mt7623-pinctrl"; reg = <0 0x1000b000 0 0x1000>; mediatek,pctl-regmap = <&syscfg_pctl_a>; From ba6afff1d9b70028a5fc3df2d3acbee501c20a53 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Thu, 5 Mar 2026 15:03:18 -0600 Subject: [PATCH 229/665] arm: dts: mediatek: mt8135: fix pinctrl node name Correct the pinctrl node name to use the same address as the reg property. Signed-off-by: David Lechner Signed-off-by: AngeloGioacchino Del Regno --- arch/arm/boot/dts/mediatek/mt8135.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/mediatek/mt8135.dtsi b/arch/arm/boot/dts/mediatek/mt8135.dtsi index 0f291ad22d3a..b03bd980ec37 100644 --- a/arch/arm/boot/dts/mediatek/mt8135.dtsi +++ b/arch/arm/boot/dts/mediatek/mt8135.dtsi @@ -148,7 +148,7 @@ pericfg: pericfg@10003000 { * Pinctrl access register at 0x10005000 and 0x1020c000 through * regmap. Register 0x1000b000 is used by EINT. */ - pio: pinctrl@10005000 { + pio: pinctrl@1000b000 { compatible = "mediatek,mt8135-pinctrl"; reg = <0 0x1000b000 0 0x1000>; mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>; From d7428ca5569bdc238a40f81ac5b1fdd349352648 Mon Sep 17 00:00:00 2001 From: Louis-Alexis Eyraud Date: Wed, 29 Apr 2026 11:44:19 +0200 Subject: [PATCH 230/665] arm64: dts: mediatek: add MT6365 PMIC include The MT6365 PMIC, compatible with MT6359 PMIC, never had its own include file so the boards that integrates this PMIC used mt6359.dtsi in their devicetree to enable its support. So, add the mt6365 include file for the MT6365 definitions and labels. In order not to duplicate all of them, make it include mt6359.dtsi and override the compatible strings for the MFD main and sub devices with the MT6365 ones. Signed-off-by: Louis-Alexis Eyraud [Angelo: Fixed regulators node label] Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6365.dtsi | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt6365.dtsi diff --git a/arch/arm64/boot/dts/mediatek/mt6365.dtsi b/arch/arm64/boot/dts/mediatek/mt6365.dtsi new file mode 100644 index 000000000000..8d16f53c8c6b --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6365.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2026 MediaTek Inc. + */ + +#include "mt6359.dtsi" + +&pmic { + compatible = "mediatek,mt6365", "mediatek,mt6359"; + + mt6365regulators: regulators { + compatible = "mediatek,mt6365-regulator", "mediatek,mt6359-regulator"; + }; +}; + +&pmic_adc { + compatible = "mediatek,mt6365-auxadc", "mediatek,mt6359-auxadc"; +}; + +mt6365codec: &mt6359codec { + compatible = "mediatek,mt6365-codec", "mediatek,mt6359-codec"; +}; + +mt6365rtc: &mt6359rtc { + compatible = "mediatek,mt6365-rtc", "mediatek,mt6358-rtc"; +}; From 0ca0b18071dbdd19ea2aab042572ac261c7f0cfb Mon Sep 17 00:00:00 2001 From: Louis-Alexis Eyraud Date: Wed, 29 Apr 2026 11:44:20 +0200 Subject: [PATCH 231/665] arm64: dts: mediatek: mt8390-genio-common: use MT6365 PMIC definitions Mediatek Genio 510 and 700 EVK boards integrate a MT6365 PMIC, compatible with MT6359, but the board common definition include file used the mt6359.dtsi to enable its support since the board support was introduced. Now that mt6365.dtsi has been created, include it instead of mt6359.dtsi and use MT6365 labels and pmic key compatible too. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi index 2062506f6cc5..5303add717bf 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi @@ -10,7 +10,7 @@ * AngeloGioacchino Del Regno */ -#include "mt6359.dtsi" +#include "mt6365.dtsi" #include #include #include @@ -695,7 +695,7 @@ &mt6359_vufs_ldo_reg { regulator-always-on; }; -&mt6359codec { +&mt6365codec { mediatek,mic-type-0 = <1>; /* ACC */ mediatek,mic-type-1 = <3>; /* DCC */ }; @@ -1281,8 +1281,8 @@ &pmic { interrupt-parent = <&pio>; interrupts = <222 IRQ_TYPE_LEVEL_HIGH>; - mt6359keys: keys { - compatible = "mediatek,mt6359-keys"; + mt6365keys: keys { + compatible = "mediatek,mt6365-keys", "mediatek,mt6359-keys"; mediatek,long-press-mode = <1>; power-off-time-sec = <0>; From 4a4b565268bc0f87a69474341102a684774b4e83 Mon Sep 17 00:00:00 2001 From: Louis-Alexis Eyraud Date: Wed, 29 Apr 2026 11:44:21 +0200 Subject: [PATCH 232/665] arm64: dts: mediatek: mt8395-genio-common: use MT6365 PMIC definitions Mediatek Genio 1200 EVK board integrates a MT6365 PMIC, compatible with MT6359, but the board common definition include file (for the eMMC and UFS configurations) used the mt6359.dtsi to enable its support since the board support was introduced. Now that mt6365.dtsi has been created, include it instead of mt6359.dtsi and use MT6365 labels and pmic key compatible too. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi index 62c336e21500..6df614c471fc 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi @@ -7,7 +7,7 @@ /dts-v1/; #include "mt8195.dtsi" -#include "mt6359.dtsi" +#include "mt6365.dtsi" #include #include #include @@ -728,7 +728,7 @@ &mt6359_vsram_others_ldo_reg { regulator-max-microvolt = <750000>; }; -&mt6359codec { +&mt6365codec { mediatek,mic-type-0 = <1>; /* ACC */ mediatek,mic-type-1 = <3>; /* DCC */ mediatek,mic-type-2 = <1>; /* ACC */ @@ -1151,8 +1151,8 @@ pins { &pmic { interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; - mt6359keys: keys { - compatible = "mediatek,mt6359-keys"; + mt6365keys: keys { + compatible = "mediatek,mt6365-keys", "mediatek,mt6359-keys"; mediatek,long-press-mode = <1>; power-off-time-sec = <0>; From f5ba6b257d934d02b7b56aeff7c65131f05f6a39 Mon Sep 17 00:00:00 2001 From: Louis-Alexis Eyraud Date: Wed, 29 Apr 2026 11:44:22 +0200 Subject: [PATCH 233/665] arm64: dts: mediatek: mt8395-radxa-nio-12l: use MT6365 PMIC definitions Radxa NIO-12L EVK board integrates a MT6365 PMIC, compatible with MT6359, but its devicetree used mt6359.dtsi to enable its support since the board support was introduced. Now that mt6365.dtsi has been created, include it instead of mt6359.dtsi and use MT6365 labels and pmic key compatible too. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index bf91305e8e4a..8bd3b3250b87 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -6,7 +6,7 @@ */ #include "mt8195.dtsi" -#include "mt6359.dtsi" +#include "mt6365.dtsi" #include #include #include @@ -1034,8 +1034,8 @@ &pciephy { &pmic { interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; - mt6359keys: keys { - compatible = "mediatek,mt6359-keys"; + mt6365keys: keys { + compatible = "mediatek,mt6365-keys", "mediatek,mt6359-keys"; mediatek,long-press-mode = <1>; power-off-time-sec = <0>; From 2e5bfbff390beba28b9526b8eca9e63a3881a309 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Sun, 12 Apr 2026 11:23:29 +0200 Subject: [PATCH 234/665] arm64: dts: mediatek: mt7988a-bpi-r4pro: rename mgmt port to lan5 It turns out that the label mgmt confuses users and now official case is released where the port is labeled with number 5. So just rename it to lan5 to follow naming convension (lan1-4 from mxl switch and lan6 for lan- combo). Signed-off-by: Frank Wunderlich Reviewed-by: Daniel Golle Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi index a48132f09411..1175ee156cb3 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi @@ -207,7 +207,7 @@ &gsw_phy0_led0 { }; &gsw_port0 { - label = "mgmt"; + label = "lan5"; }; /* R4Pro has only port 0 connected, so disable the others */ From 99b09353644a8211423515642805e66e19d8d58a Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Sun, 12 Apr 2026 11:23:30 +0200 Subject: [PATCH 235/665] arm64: dts: mediatek: mt7988a-bpi-r4pro: drop duplicate fan properties These properties are already set in the original node and do not need to be defined again. Signed-off-by: Frank Wunderlich Signed-off-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi index 1175ee156cb3..759f608d1081 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi @@ -185,13 +185,6 @@ ð { status = "okay"; }; -&fan { - pinctrl-0 = <&pwm0_pins>; - pinctrl-names = "default"; - pwms = <&pwm 0 50000>; - status = "okay"; -}; - &gmac0 { status = "okay"; }; From 52869bbbcfbde006948c0fe1f8f08d650a9b0093 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Sun, 12 Apr 2026 11:23:31 +0200 Subject: [PATCH 236/665] arm64: dts: mediatek: mt7988a-bpi-r4pro: update gpio-leds MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On the official case the red LED is named ERR, the blue LED is named ACT.​​​​​​​​​​​​​​​​ Reflect these labels in function and set them default off. Signed-off-by: Frank Wunderlich Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi index 759f608d1081..bbd6c16a8cb0 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi @@ -61,14 +61,14 @@ gpio-leds { led_red: sys-led-red { color = ; + function = LED_FUNCTION_FAULT; gpios = <&pca9555 15 GPIO_ACTIVE_HIGH>; - default-state = "on"; }; led_blue: sys-led-blue { color = ; + function = LED_FUNCTION_ACTIVITY; gpios = <&pca9555 14 GPIO_ACTIVE_HIGH>; - default-state = "on"; }; }; From e309fa232d12b969afac43a4b7d83dee025cfe63 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Sun, 12 Apr 2026 11:23:32 +0200 Subject: [PATCH 237/665] arm64: dts: mediatek: mt7988a-bpi-r4pro: rework pcie gpio-hog handling The active-high property in base-dt cannot be overwritten and must be set in separate overlay. Fixes: f397471a6a8c ("arm64: dts: mediatek: mt7988: Add devicetree for BananaPi R4 Pro") Signed-off-by: Frank Wunderlich Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 8 ++++++++ .../mt7988a-bananapi-bpi-r4-pro-cn13.dtso | 20 +++++++++++++++++++ .../mt7988a-bananapi-bpi-r4-pro-cn14.dtso | 20 +++++++++++++++++++ .../mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi | 2 -- 4 files changed, 48 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn13.dtso create mode 100644 arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn14.dtso diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 387faa9c2a09..a86fb313b1a9 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -47,6 +47,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-2g5.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-emmc.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-4e.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-cn13.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-cn14.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-cn15.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-cn18.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-emmc.dtbo @@ -70,18 +72,24 @@ mt7988a-bananapi-bpi-r4-2g5-sd-dtbs := \ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-2g5-sd.dtb mt7988a-bananapi-bpi-r4-pro-8x-emmc-dtbs := \ mt7988a-bananapi-bpi-r4-pro-8x.dtb \ + mt7988a-bananapi-bpi-r4-pro-cn13.dtbo \ + mt7988a-bananapi-bpi-r4-pro-cn14.dtbo \ mt7988a-bananapi-bpi-r4-pro-emmc.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x-emmc.dtb mt7988a-bananapi-bpi-r4-pro-8x-sd-dtbs := \ mt7988a-bananapi-bpi-r4-pro-8x.dtb \ + mt7988a-bananapi-bpi-r4-pro-cn13.dtbo \ + mt7988a-bananapi-bpi-r4-pro-cn14.dtbo \ mt7988a-bananapi-bpi-r4-pro-sd.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x-sd.dtb mt7988a-bananapi-bpi-r4-pro-8x-sd-cn15-dtbs := \ mt7988a-bananapi-bpi-r4-pro-8x-sd.dtb \ + mt7988a-bananapi-bpi-r4-pro-cn14.dtbo \ mt7988a-bananapi-bpi-r4-pro-cn15.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x-sd-cn15.dtb mt7988a-bananapi-bpi-r4-pro-8x-sd-cn18-dtbs := \ mt7988a-bananapi-bpi-r4-pro-8x-sd.dtb \ + mt7988a-bananapi-bpi-r4-pro-cn13.dtbo \ mt7988a-bananapi-bpi-r4-pro-cn18.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x-sd-cn18.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn13.dtso b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn13.dtso new file mode 100644 index 000000000000..973b76ba0cbf --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn13.dtso @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Frank Wunderlich + */ + +/* This enables key-m slot CN13 on pcie2(11280000 1L0) on BPI-R4-Pro */ + +/dts-v1/; +/plugin/; + +#include + +/ { + compatible = "bananapi,bpi-r4-pro", "mediatek,mt7988a"; +}; + +&{/soc/pinctrl@1001f000/pcie-2-hog} { + output-high; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn14.dtso b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn14.dtso new file mode 100644 index 000000000000..90b2a64459c3 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn14.dtso @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Frank Wunderlich + */ + +/* This enables key-m slot CN14 on pcie3(11290000 1L1) on BPI-R4-Pro */ + +/dts-v1/; +/plugin/; + +#include + +/ { + compatible = "bananapi,bpi-r4-pro", "mediatek,mt7988a"; +}; + +&{/soc/pinctrl@1001f000/pcie-3-hog} { + output-high; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi index bbd6c16a8cb0..1eeb72108b9b 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi @@ -430,14 +430,12 @@ mux { pcie-2-hog { gpio-hog; gpios = <79 GPIO_ACTIVE_HIGH>; - output-high; }; /* 1L1 0=key-b (CN18), 1=key-m (CN14) */ pcie-3-hog { gpio-hog; gpios = <63 GPIO_ACTIVE_HIGH>; - output-high; }; pwm0_pins: pwm0-pins { From 7cb323d33590da5f4b72b9bd9151ddc59bab19a5 Mon Sep 17 00:00:00 2001 From: Louis-Alexis Eyraud Date: Tue, 14 Apr 2026 12:33:31 +0200 Subject: [PATCH 238/665] arm64: dts: mediatek: mt8390-genio-common: add MT6319 PMIC support Mediatek Genio 510 and 700-EVK boards integrate a MT6319 PMIC, powered by the board system power rail (VSYS) and connected to the SPMI interface. It provides buck regulators for CPU core power supplies in particular. Add the needed nodes in the board common dtsi to enable its support. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- .../dts/mediatek/mt8390-genio-common.dtsi | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi index 5303add717bf..af859a7504b8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi @@ -1364,6 +1364,50 @@ &spi2 { status = "okay"; }; +&spmi { + #address-cells = <2>; + #size-cells = <0>; + + pmic@6 { + compatible = "mediatek,mt6319-regulator", "mediatek,mt6315-regulator"; + reg = <0x6 SPMI_USID>; + + pvdd1-supply = <®_vsys>; + pvdd2-supply = <®_vsys>; + pvdd3-supply = <®_vsys>; + pvdd4-supply = <®_vsys>; + + regulators { + mt6319_vbuck1: vbuck1 { + regulator-name = "dvdd_proc_b"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + + vbuck3 { + regulator-name = "avdd2_emi"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + + vbuck4 { + regulator-name = "avddq_emi"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + }; + }; +}; + &uart0 { pinctrl-0 = <&uart0_pins>; pinctrl-names = "default"; From e04e7ad8c8d8abe74b05ee0c526eb8989d7a2744 Mon Sep 17 00:00:00 2001 From: Louis-Alexis Eyraud Date: Tue, 14 Apr 2026 12:33:32 +0200 Subject: [PATCH 239/665] arm64: dts: mediatek: mt8390-genio-common: add CPU power supplies Mediatek Genio 510-EVK (MT8370) and 700-EVK (MT8390) devicetrees are missing power supply definitions for all their CPU cores. On the boards, the big core power is supplied by a MT6319 (sub PMIC), and little core power by a MT6365 (main PMIC). MT8370 and MT8390 SoC have the same core type (little cores are ARM Cortex A55, big ones are A78), the same big core number (2) but MT8390 SoC has more little cores (6) than MT8370 SoC (only 4). To handle the little core number difference, add in the board common dtsi the power supply definitions for the common CPU core nodes (0-3, 6 and 7). The power supplies for the additional MT8390 CPU core nodes (4 and 5) will be added for the Genio 700 in a separate commit. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- .../dts/mediatek/mt8390-genio-common.dtsi | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi index af859a7504b8..eb58001bf5d5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi @@ -285,6 +285,30 @@ &afe { status = "okay"; }; +&cpu0 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu1 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu2 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu3 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu6 { + cpu-supply = <&mt6319_vbuck1>; +}; + +&cpu7 { + cpu-supply = <&mt6319_vbuck1>; +}; + &disp_dsi0 { #address-cells = <1>; #size-cells = <0>; From f060f4b922975d3dcc770a6e97886f3f57717c6e Mon Sep 17 00:00:00 2001 From: Louis-Alexis Eyraud Date: Tue, 14 Apr 2026 12:33:33 +0200 Subject: [PATCH 240/665] arm64: dts: mediatek: mt8390-genio-700-evk: add specific CPU power supplies Add power supply definitions for the additional little CPU core nodes, that cannot be factorized in the board common dtsi due to little core number difference between MT8390 SoC (used by this board) and MT8370 SoC (used by Genio 510-EVK). Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts index 612336713a64..0d5a75efb2ee 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts @@ -21,3 +21,10 @@ memory@40000000 { }; }; +&cpu4 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu5 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; From 137d714393640ce026cd2255ba1f3aa4130fa233 Mon Sep 17 00:00:00 2001 From: Louis-Alexis Eyraud Date: Tue, 14 Apr 2026 13:44:11 +0200 Subject: [PATCH 241/665] arm64: dts: mediatek: mt8395-genio-common: add MT6315 PMIC supplies Mediatek Genio 1200-EVK board has two MT6315 PMICs, powered by the board system power rail (VSYS) and connected to the SPMI interface. Add VSYS regulator node for system power rail and the supply inputs of these two PMICs. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8395-genio-common.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi index 6df614c471fc..30acf2845960 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi @@ -201,6 +201,14 @@ wifi_fixed_3v3: regulator-2 { enable-active-high; regulator-always-on; }; + + /* system wide 4.2V power rail */ + reg_vsys: regulator-vsys { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-always-on; + regulator-boot-on; + }; }; &adsp { @@ -1238,6 +1246,11 @@ mt6315_6: pmic@6 { compatible = "mediatek,mt6315-regulator"; reg = <0x6 SPMI_USID>; + pvdd1-supply = <®_vsys>; + pvdd2-supply = <®_vsys>; + pvdd3-supply = <®_vsys>; + pvdd4-supply = <®_vsys>; + regulators { mt6315_6_vbuck1: vbuck1 { regulator-name = "Vbcpu"; @@ -1254,6 +1267,11 @@ mt6315_7: pmic@7 { compatible = "mediatek,mt6315-regulator"; reg = <0x7 SPMI_USID>; + pvdd1-supply = <®_vsys>; + pvdd2-supply = <®_vsys>; + pvdd3-supply = <®_vsys>; + pvdd4-supply = <®_vsys>; + regulators { mt6315_7_vbuck1: vbuck1 { regulator-name = "Vgpu"; From 241d4c163c774c567a33bd15c3f933e11f652600 Mon Sep 17 00:00:00 2001 From: Louis-Alexis Eyraud Date: Tue, 14 Apr 2026 13:44:12 +0200 Subject: [PATCH 242/665] arm64: dts: mediatek: mt8395-genio-common: add MT6360 PMIC supplies The Mediatek Genio 1200-EVK board has a MT6360 PMIC, powered by the board system power rail (VSYS) and an additional system power rail (VSYS_BUCK). In the board devicetree, the power supply inputs for its buck and ldo regulators are either incorrect (LDO_VIN3) or missing (LDO_VIN1/2, BUCK_VIN1/2). So, add VSYS_BUCK regulator node and the proper supply inputs for this PMIC. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8395-genio-common.dtsi | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi index 30acf2845960..95955a210d80 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi @@ -209,6 +209,14 @@ reg_vsys: regulator-vsys { regulator-always-on; regulator-boot-on; }; + + reg_vsys_buck: regulator-vsys-buck { + compatible = "regulator-fixed"; + regulator-name = "vsys_buck"; + regulator-always-on; + regulator-boot-on; + vin-supply = <®_vsys>; + }; }; &adsp { @@ -486,7 +494,11 @@ otg_vbus_regulator: usb-otg-vbus-regulator { regulator { compatible = "mediatek,mt6360-regulator"; - LDO_VIN3-supply = <&mt6360_buck2>; + BUCK1_VIN-supply = <®_vsys>; + BUCK2_VIN-supply = <®_vsys>; + LDO_VIN1-supply = <®_vsys_buck>; + LDO_VIN2-supply = <®_vsys_buck>; + LDO_VIN3-supply = <®_vsys>; mt6360_buck1: buck1 { regulator-name = "emi_vdd2"; From 916bd9d55b4a9f3496eee86028cede20a3c3ff9a Mon Sep 17 00:00:00 2001 From: Aleksander Jan Bajkowski Date: Wed, 29 Apr 2026 00:47:43 +0200 Subject: [PATCH 243/665] arm64: dts: mediatek: add crypto offload support on MT7981 The MT7981 as well as the MT7986 have a built-in EIP-97 rev 2.3p0 crypto accelerator. This commit adds the missing entry in the dts. Signed-off-by: Aleksander Jan Bajkowski Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 1bbe219380f9..e63ba3ae395e 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -150,6 +150,21 @@ sgmiisys1: syscon@10070000 { #clock-cells = <1>; }; + crypto@10320000 { + compatible = "mediatek,mt7981-crypto", + "inside-secure,safexcel-eip97ies"; + reg = <0 0x10320000 0 0x40000>; + interrupts = , + , + , + ; + interrupt-names = "ring0", "ring1", "ring2", "ring3"; + clocks = <&topckgen CLK_TOP_EIP97B>; + clock-names = "core"; + assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>; + }; + uart0: serial@11002000 { compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x100>; From 533275a4b5240a2bf2c592bd4536560388306d26 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 30 Apr 2026 20:07:24 +0800 Subject: [PATCH 244/665] arm64: dts: mediatek: mt8192-asurada: Move PCIe DMA bounce buffer to host The DMA bounce buffer is attached to the PCIe host controller, i.e. all PCIe DMA transfers should use it. Move it from the PCIe (WiFi) device node down to the PCIe host controller node. Fixes: 0dca9f0b3e63 ("arm64: dts: mediatek: asurada: Enable PCIe and add WiFi") Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index eadf1b2d156f..95d4db2b7979 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -525,6 +525,7 @@ flash@0 { &pcie { pinctrl-names = "default"; pinctrl-0 = <&pcie_pins>; + memory-region = <&wifi_restricted_dma_region>; pcie0: pcie@0,0 { device_type = "pci"; @@ -539,7 +540,6 @@ pcie0: pcie@0,0 { wifi: wifi@0,0 { reg = <0x10000 0 0 0 0x100000>, <0x10000 0 0x100000 0 0x100000>; - memory-region = <&wifi_restricted_dma_region>; }; }; }; From 4216839375ff45d792b8b4f8b1093781b05ce47e Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 5 May 2026 18:13:51 +0800 Subject: [PATCH 245/665] arm64: dts: mediatek: mt8186-corsola-voltorb: Add MT6315 PMIC supplies The MT8186 Voltorb device has one MT6315 PMIC. The first 2 outputs ganged together, and the other two unused. Add supplies for this PMIC. Even though the outputs are unused, the inputs are still connected. Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dtsi b/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dtsi index b495a241b443..0250b4eeadd4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dtsi @@ -73,6 +73,10 @@ &spmi { pmic@6 { compatible = "mediatek,mt6319-regulator", "mediatek,mt6315-regulator"; reg = <0x6 SPMI_USID>; + pvdd1-supply = <&pp4200_z2>; + pvdd2-supply = <&pp4200_z2>; + pvdd3-supply = <&pp4200_z2>; + pvdd4-supply = <&pp4200_z2>; regulators { mt6319_buck1: vbuck1 { From c991e458a4a51588c436d47cf447b64e97ffc7af Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 5 May 2026 18:13:52 +0800 Subject: [PATCH 246/665] arm64: dts: mediatek: mt6359: Switch to proper ldo_vcn33_[12] regulators The ldo_vcn33_[12]_wifi and ldo_vcn33_[12]_bt are just two regulator outputs instead of four. The wifi and bt parts refer to separate enable bits that are OR-ed together to affect the actual regulator output. The separate bits allow the wifi and bt stacks to enable their power without coordination between them. These have been deprecated in favor of proper nodes matching the output. Add proper ldo_vcn33_[12] nodes and drop the old ones. No default voltage ranges are given as they don't make sense, and the existing ranges are about to be removed. In-tree users of the existing *_(wifi|bt) regulator nodes are converted over to use the new ones. Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6359.dtsi | 22 ++++--------------- .../dts/mediatek/mt8390-genio-common.dtsi | 4 ++-- .../dts/mediatek/mt8390-grinn-genio-som.dtsi | 2 +- .../dts/mediatek/mt8390-tungsten-smarc.dtsi | 6 ++--- .../dts/mediatek/mt8395-genio-common.dtsi | 6 ++--- .../mt8395-radxa-nio-12l-8-hd-panel.dtso | 4 ++-- .../dts/mediatek/mt8395-radxa-nio-12l.dts | 2 +- 7 files changed, 16 insertions(+), 30 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6359.dtsi b/arch/arm64/boot/dts/mediatek/mt6359.dtsi index 45ad69ee49ed..a953fb527b69 100644 --- a/arch/arm64/boot/dts/mediatek/mt6359.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6359.dtsi @@ -164,15 +164,8 @@ mt6359_vcn13_ldo_reg: ldo_vcn13 { regulator-min-microvolt = <900000>; regulator-max-microvolt = <1300000>; }; - mt6359_vcn33_1_bt_ldo_reg: ldo_vcn33_1_bt { - regulator-name = "vcn33_1_bt"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3500000>; - }; - mt6359_vcn33_1_wifi_ldo_reg: ldo_vcn33_1_wifi { - regulator-name = "vcn33_1_wifi"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3500000>; + mt6359_vcn33_1_ldo_reg: ldo_vcn33_1 { + regulator-name = "vcn33_1"; }; mt6359_vaux18_ldo_reg: ldo_vaux18 { regulator-name = "vaux18"; @@ -231,15 +224,8 @@ mt6359_vemc_1_ldo_reg: ldo_vemc_1 { regulator-min-microvolt = <2500000>; regulator-max-microvolt = <3300000>; }; - mt6359_vcn33_2_bt_ldo_reg: ldo_vcn33_2_bt { - regulator-name = "vcn33_2_bt"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3500000>; - }; - mt6359_vcn33_2_wifi_ldo_reg: ldo_vcn33_2_wifi { - regulator-name = "vcn33_2_wifi"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3500000>; + mt6359_vcn33_2_ldo_reg: ldo_vcn33_2 { + regulator-name = "vcn33_2"; }; mt6359_va12_ldo_reg: ldo_va12 { regulator-name = "va12"; diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi index eb58001bf5d5..b0c97930a0e6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi @@ -469,7 +469,7 @@ typec-mux@48 { mode-switch; orientation-switch; - vcc-supply = <&mt6359_vcn33_1_bt_ldo_reg>; + vcc-supply = <&mt6359_vcn33_1_ldo_reg>; port { it5205_sbu_mux: endpoint { @@ -661,7 +661,7 @@ &mt6359_vcn18_ldo_reg { regulator-always-on; }; -&mt6359_vcn33_2_bt_ldo_reg { +&mt6359_vcn33_2_ldo_reg { regulator-name = "vcn33_2_pmu"; regulator-always-on; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi index 8da47c916313..84064511fa0d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi @@ -58,7 +58,7 @@ &mt6359_vcn18_ldo_reg { regulator-always-on; }; -&mt6359_vcn33_2_bt_ldo_reg { +&mt6359_vcn33_2_ldo_reg { regulator-name = "vcn33_2_pmu"; regulator-always-on; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi index 40b381d4cc35..2e68e997dff3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi @@ -592,7 +592,7 @@ &mmc2 { interrupt-names = "msdc", "sdio_wakeup"; interrupts-extended = <&gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>, <&pio 172 IRQ_TYPE_LEVEL_LOW>; - vmmc-supply = <&mt6359_vcn33_2_bt_ldo_reg>; + vmmc-supply = <&mt6359_vcn33_2_ldo_reg>; vqmmc-supply = <&mt6359_vcn18_ldo_reg>; mmc-pwrseq = <&wifi_pwrseq>; status = "okay"; @@ -617,12 +617,12 @@ &mt6359_vcn18_ldo_reg { regulator-boot-on; }; -&mt6359_vcn33_1_bt_ldo_reg { +&mt6359_vcn33_1_ldo_reg { regulator-name = "vcn33_1_pmu"; regulator-always-on; }; -&mt6359_vcn33_2_bt_ldo_reg { +&mt6359_vcn33_2_ldo_reg { regulator-name = "vcn33_2_pmu"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi index 95955a210d80..edc5539bebde 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi @@ -721,7 +721,7 @@ &mt6359_vcamio_ldo_reg { regulator-always-on; }; -&mt6359_vcn33_2_bt_ldo_reg { +&mt6359_vcn33_2_ldo_reg { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; @@ -1236,8 +1236,8 @@ can0: can@0 { clocks = <&can_clk>; spi-max-frequency = <20000000>; interrupts-extended = <&pio 16 IRQ_TYPE_LEVEL_LOW>; - vdd-supply = <&mt6359_vcn33_2_bt_ldo_reg>; - xceiver-supply = <&mt6359_vcn33_2_bt_ldo_reg>; + vdd-supply = <&mt6359_vcn33_2_ldo_reg>; + xceiver-supply = <&mt6359_vcn33_2_ldo_reg>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l-8-hd-panel.dtso b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l-8-hd-panel.dtso index 0389c9cb8581..ecc9fd27b82d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l-8-hd-panel.dtso +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l-8-hd-panel.dtso @@ -29,7 +29,7 @@ panel@0 { compatible = "radxa,display-8hd-ad002", "jadard,jd9365da-h3"; reg = <0>; backlight = <&backlight>; - vdd-supply = <&mt6359_vcn33_2_bt_ldo_reg>; + vdd-supply = <&mt6359_vcn33_2_ldo_reg>; vccio-supply = <&mt6360_ldo2>; reset-gpios = <&pio 108 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; @@ -57,7 +57,7 @@ touchscreen@14 { interrupts-extended = <&pio 132 IRQ_TYPE_EDGE_RISING>; irq-gpios = <&pio 132 GPIO_ACTIVE_HIGH>; reset-gpios = <&pio 133 GPIO_ACTIVE_HIGH>; - VDDIO-supply = <&mt6359_vcn33_2_bt_ldo_reg>; + VDDIO-supply = <&mt6359_vcn33_2_ldo_reg>; pinctrl-names = "default"; pinctrl-0 = <&touch_pins>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index 8bd3b3250b87..b279eed1bfc3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -614,7 +614,7 @@ &mt6359_vcamio_ldo_reg { regulator-always-on; }; -&mt6359_vcn33_2_bt_ldo_reg { +&mt6359_vcn33_2_ldo_reg { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; From f240a914ca56faaf2cbbcf4967aa0844beb5a23b Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 5 May 2026 18:13:53 +0800 Subject: [PATCH 247/665] arm64: dts: mediatek: mt8192-asurada: Add MT6359 PMIC supplies The MT6359 PMIC has a number of power inputs for its various buck and LDO regulators. The binding recently gained property definitions for them. Add the supplies for the PMIC regulators to the common design dtsi file. Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- .../arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 95d4db2b7979..11b404bc6d42 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -1306,6 +1306,23 @@ pins-miso-on { &pmic { interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>; + vsys-smps-supply = <&pp4200_g>; + vsys-vcore-supply = <&pp4200_g>; + vsys-vgpu11-supply = <&pp4200_g>; + vsys-vgpu12-supply = <&pp4200_g>; + vsys-vpa-supply = <&pp4200_g>; + vsys-vproc1-supply = <&pp4200_g>; + vsys-vproc2-supply = <&pp4200_g>; + vsys-vpu-supply = <&pp4200_g>; + vsys-vs1-supply = <&pp4200_g>; + vsys-vs2-supply = <&pp4200_g>; + vsys-vmodem-supply = <&pp4200_g>; + vsys-ldo1-supply = <&pp4200_g>; + vsys-ldo2-supply = <&pp4200_g>; + vs1-ldo1-supply = <&mt6359_vs1_buck_reg>; + vs1-ldo2-supply = <&mt6359_vs1_buck_reg>; + vs2-ldo1-supply = <&mt6359_vs2_buck_reg>; + vs2-ldo2-supply = <&mt6359_vs2_buck_reg>; }; &pwm0 { From 9945dd30790e68ccfa0de9560aa120585ebb8260 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 5 May 2026 18:13:54 +0800 Subject: [PATCH 248/665] arm64: dts: mediatek: mt8192-asurada: Add MT6315 PMIC supplies There are two MT6315 PMICs in the MT8192 Asurada design. One has two outputs ganged together and two outputs unused. The other has three outputs ganged together, and one left independent. Add supplies for all the used regulators. In the case of ganged outputs, add the supply for just the first output. Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8192-asurada.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 11b404bc6d42..3171cbb2ec50 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -175,6 +175,17 @@ pp3300_wlan: regulator-3v3-wlan { gpio = <&pio 143 GPIO_ACTIVE_HIGH>; }; + /* system wide switching 4.2V power rail */ + pp4200_g: regulator-4v2-g { + compatible = "regulator-fixed"; + regulator-name = "pp4200_g"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + vin-supply = <&ppvar_sys>; + }; + /* system wide switching 5.0V power rail */ pp5000_a: regulator-5v0-a { compatible = "regulator-fixed"; @@ -1444,6 +1455,10 @@ &spmi { mt6315_6: pmic@6 { compatible = "mediatek,mt6315-regulator"; reg = <0x6 SPMI_USID>; + pvdd1-supply = <&pp4200_g>; + pvdd2-supply = <&pp4200_g>; + pvdd3-supply = <&pp4200_g>; + pvdd4-supply = <&pp4200_g>; regulators { mt6315_6_vbuck1: vbuck1 { @@ -1469,6 +1484,10 @@ mt6315_6_vbuck3: vbuck3 { mt6315_7: pmic@7 { compatible = "mediatek,mt6315-regulator"; reg = <0x7 SPMI_USID>; + pvdd1-supply = <&pp4200_g>; + pvdd2-supply = <&pp4200_g>; + pvdd3-supply = <&pp4200_g>; + pvdd4-supply = <&pp4200_g>; regulators { mt6315_7_vbuck1: vbuck1 { From 7efcf389329c15c94e78225c3a81a7e8eb05c000 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 5 May 2026 18:13:55 +0800 Subject: [PATCH 249/665] arm64: dts: mediatek: mt8192-asurada: Add supplies for ChromeOS EC regulators The ChromeOS Embedded Controller exposes two regulators to the system in the MT8192 Asurada design. Both these regulators also have power inputs. Add supplies for these two regulators. Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 3171cbb2ec50..b5939ad7fdcf 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -1395,6 +1395,7 @@ mt6360_ldo3_reg: regulator@0 { reg = <0>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; + vin-supply = <&pp4200_g>; }; mt6360_ldo5_reg: regulator@1 { @@ -1402,6 +1403,7 @@ mt6360_ldo5_reg: regulator@1 { reg = <1>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + vin-supply = <&pp4200_g>; }; typec { From 72f4c72e283c5a6d1301f5d0b30fbe551de5b7b3 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 5 May 2026 18:13:56 +0800 Subject: [PATCH 250/665] arm64: dts: mediatek: mt8192-asurada: Add CPU power supplies The device tree for the MT8192 Asurada is missing power supplies for all the CPU cores. Add supplies to the CPU cores. The big and little clusters each have their own regulator. Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8192-asurada.dtsi | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index b5939ad7fdcf..bfb09dc974a7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -298,6 +298,38 @@ &afe { memory-region = <&afe_dma_mem>; }; +&cpu0 { + cpu-supply = <&mt6315_6_vbuck3>; +}; + +&cpu1 { + cpu-supply = <&mt6315_6_vbuck3>; +}; + +&cpu2 { + cpu-supply = <&mt6315_6_vbuck3>; +}; + +&cpu3 { + cpu-supply = <&mt6315_6_vbuck3>; +}; + +&cpu4 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + +&cpu5 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + +&cpu6 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + +&cpu7 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + &dsi0 { status = "okay"; }; From 8b16d2b66464e649c44894e65dd8c3111949d308 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 5 May 2026 18:13:57 +0800 Subject: [PATCH 251/665] arm64: dts: mediatek: mt8192-asurada: Add SPI NOR flash power supply The device tree for the MT8192 Asurada is missing a power supply for the SPI NOR flash chip. Add the supply for the SPI NOR flash chip. Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index bfb09dc974a7..94bc800ba217 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -562,6 +562,7 @@ flash@0 { spi-max-frequency = <52000000>; spi-rx-bus-width = <2>; spi-tx-bus-width = <2>; + vcc-supply = <&mt6359_vio18_ldo_reg>; }; }; From b9160d7b34ef6e79a1e536485f0852ddf75ba706 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 5 May 2026 18:13:58 +0800 Subject: [PATCH 252/665] arm64: dts: mediatek: mt8192-asurada: Fix WiFi regulator description The WiFi supply regulator is a current-limiting switch. It does not have voltage regulation capabilities. The description is also missing a power input. Drop the voltage constraints, and add a supply input. Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 94bc800ba217..15660f6c8fa5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -167,12 +167,11 @@ pp3300_wlan: regulator-3v3-wlan { regulator-name = "pp3300_wlan"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; pinctrl-names = "default"; pinctrl-0 = <&pp3300_wlan_pins>; enable-active-high; gpio = <&pio 143 GPIO_ACTIVE_HIGH>; + vin-supply = <&pp3300_g>; }; /* system wide switching 4.2V power rail */ From d33c57501113476e72a0d37f2ae0805f7ff38cb6 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 5 May 2026 18:13:59 +0800 Subject: [PATCH 253/665] arm64: dts: mediatek: mt8195-cherry: Add MT6359 PMIC supplies The MT6359 PMIC has a number of power inputs for its various buck and LDO regulators. The binding recently gained property definitions for them. Add the supplies for the PMIC regulators to the common design dtsi file. Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index f1ff64a84267..0b9fedac842c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -1312,6 +1312,23 @@ pins-report-sw { &pmic { interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; + vsys-smps-supply = <&pp4200_z2>; + vsys-vcore-supply = <&pp4200_z2>; + vsys-vgpu11-supply = <&pp4200_z2>; + vsys-vgpu12-supply = <&pp4200_z2>; + vsys-vpa-supply = <&pp4200_z2>; + vsys-vproc1-supply = <&pp4200_z2>; + vsys-vproc2-supply = <&pp4200_z2>; + vsys-vpu-supply = <&pp4200_z2>; + vsys-vs1-supply = <&pp4200_z2>; + vsys-vs2-supply = <&pp4200_z2>; + vsys-vmodem-supply = <&pp4200_z2>; + vsys-ldo1-supply = <&pp4200_z2>; + vsys-ldo2-supply = <&pp4200_z2>; + vs1-ldo1-supply = <&mt6359_vs1_buck_reg>; + vs1-ldo2-supply = <&mt6359_vs1_buck_reg>; + vs2-ldo1-supply = <&mt6359_vs2_buck_reg>; + vs2-ldo2-supply = <&mt6359_vs2_buck_reg>; }; &scp { From e55bab157e1362ffd8321db07aced7b6d1948c05 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 5 May 2026 18:14:00 +0800 Subject: [PATCH 254/665] arm64: dts: mediatek: mt8195-cherry: Add MT6315 PMIC supplies The MT8195 Cherry design has two MT6315 PMICs. One has 4 outputs ganged together; the other has 2 outputs ganged together, and the other two unused. Add supplies for these two PMICs. Since the outputs are ganged together, just add the supply for the first one. Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index 0b9fedac842c..cf9855618494 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -1472,6 +1472,10 @@ &spmi { mt6315@6 { compatible = "mediatek,mt6315-regulator"; reg = <0x6 SPMI_USID>; + pvdd1-supply = <&pp4200_z2>; + pvdd2-supply = <&pp4200_z2>; + pvdd3-supply = <&pp4200_z2>; + pvdd4-supply = <&pp4200_z2>; regulators { mt6315_6_vbuck1: vbuck1 { @@ -1489,6 +1493,10 @@ mt6315_6_vbuck1: vbuck1 { mt6315@7 { compatible = "mediatek,mt6315-regulator"; reg = <0x7 SPMI_USID>; + pvdd1-supply = <&pp4200_z2>; + pvdd2-supply = <&pp4200_z2>; + pvdd3-supply = <&pp4200_z2>; + pvdd4-supply = <&pp4200_z2>; regulators { mt6315_7_vbuck1: vbuck1 { From 0fdf2b2a3ed1bbfe3200d3889db0baaecd35b529 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 5 May 2026 18:14:01 +0800 Subject: [PATCH 255/665] arm64: dts: mediatek: mt8195-cherry: Add supplies for ChromeOS EC regulators The two regulators that are exposed by the EC are supplied by the system 4.2V power rail. Add supply properties for them. Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index cf9855618494..bda1b0f9f72a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -1431,6 +1431,7 @@ mt_pmic_vmc_ldo_reg: regulator@0 { regulator-name = "mt_pmic_vmc_ldo"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <3600000>; + vin-supply = <&pp4200_z2>; }; mt_pmic_vmch_ldo_reg: regulator@1 { @@ -1439,6 +1440,7 @@ mt_pmic_vmch_ldo_reg: regulator@1 { regulator-name = "mt_pmic_vmch_ldo"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3600000>; + vin-supply = <&pp4200_z2>; }; typec { From 76c8b915988f699a68e59698bf92e571de1e3c9b Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 5 May 2026 18:14:02 +0800 Subject: [PATCH 256/665] arm64: dts: mediatek: mt8195-cherry: Fix VBUS regulator description The VBUS regulator is a current-limiting switch. It does not have voltage regulation capabilities. The description is also missing a power input. Drop the voltage constraints, and add a supply input. Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index bda1b0f9f72a..dc1ba143ccf2 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -212,10 +212,9 @@ tboard_thermistor2: thermal-sensor-t2 { usb_vbus: regulator-5v0-usb-vbus { compatible = "regulator-fixed"; regulator-name = "usb-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; enable-active-high; regulator-always-on; + vin-supply = <&pp5000_s5>; }; reserved_memory: reserved-memory { From 66e5674f0e048d0f192afd2be36725e0bf084d90 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 5 May 2026 18:14:03 +0800 Subject: [PATCH 257/665] arm64: dts: mediatek: mt8195-cherry: Add supply for SPI NOR flash The SPI NOR flash is powered by a separate "always on" 1.8V LDO regulated power rail. This rail is fed from the system 3.3V rail. Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index dc1ba143ccf2..62e2d7616f20 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -47,6 +47,17 @@ memory@40000000 { reg = <0 0x40000000 0 0x80000000>; }; + /* system critical LDO 1.8V power rail */ + pp1800_ldo_z2: regulator-pp1800-ldo-z2 { + compatible = "regulator-fixed"; + regulator-name = "pp1800_ldo_z2"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&pp3300_z2>; + }; + pp3300_disp_x: regulator-pp3300-disp-x { compatible = "regulator-fixed"; regulator-name = "pp3300_disp_x"; @@ -762,6 +773,7 @@ flash@0 { spi-max-frequency = <52000000>; spi-rx-bus-width = <2>; spi-tx-bus-width = <2>; + vcc-supply = <&pp1800_ldo_z2>; }; }; From c8ae7e17ea741f4821861da51168c0cdd3fffb36 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 5 May 2026 18:14:04 +0800 Subject: [PATCH 258/665] arm64: dts: mediatek: mt8195-cherry: Add vusb33 supplies for XHCI controllers Like the dual-role SSUSB controller block that encompasses the XHCI controller, the latter also takes a vusb33 supply. Add the supply for each XHCI controller. Also fix up any property ordering according to DT styles, i.e. move "status" property to the end. Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index 62e2d7616f20..ca2bb367ee68 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -1622,21 +1622,23 @@ vdosys1_ep_ext: endpoint@1 { }; &xhci0 { - status = "okay"; - rx-fifo-depth = <3072>; vbus-supply = <&usb_vbus>; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; }; &xhci2 { - status = "okay"; vbus-supply = <&usb_vbus>; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; }; &xhci3 { /* MT7921's USB Bluetooth has issues with USB2 LPM */ usb2-lpm-disable; vbus-supply = <&pp3300_wlan>; + vusb33-supply = <&mt6359_vusb_ldo_reg>; status = "okay"; }; From 0948625a2d85c660891e2e1dca5fcf04e31e2563 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 5 May 2026 18:14:05 +0800 Subject: [PATCH 259/665] arm64: dts: mediatek: mt8188-geralt: Add MT6359 PMIC supplies The MT6359 PMIC has a number of power inputs for its various buck and LDO regulators. The binding recently gained property definitions for them. Add the supplies for the PMIC regulators to the common design dtsi file. Reviewed-by: Fei Shao Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi index 8e423504ec05..d57e0eec676a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi @@ -1149,6 +1149,23 @@ pins-en-pp3300-wlan { &pmic { interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; + vsys-smps-supply = <&pp4200_s5>; + vsys-vcore-supply = <&pp4200_s5>; + vsys-vgpu11-supply = <&pp4200_s5>; + vsys-vgpu12-supply = <&pp4200_s5>; + vsys-vpa-supply = <&pp4200_s5>; + vsys-vproc1-supply = <&pp4200_s5>; + vsys-vproc2-supply = <&pp4200_s5>; + vsys-vpu-supply = <&pp4200_s5>; + vsys-vs1-supply = <&pp4200_s5>; + vsys-vs2-supply = <&pp4200_s5>; + vsys-vmodem-supply = <&pp4200_s5>; + vsys-ldo1-supply = <&pp4200_s5>; + vsys-ldo2-supply = <&pp4200_s5>; + vs1-ldo1-supply = <&mt6359_vs1_buck_reg>; + vs1-ldo2-supply = <&mt6359_vs1_buck_reg>; + vs2-ldo1-supply = <&mt6359_vs2_buck_reg>; + vs2-ldo2-supply = <&mt6359_vs2_buck_reg>; }; &postmask0_in { From 760c4db1e921ad482cf96bf9c57ebdb3be0cbb39 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 5 May 2026 18:14:06 +0800 Subject: [PATCH 260/665] arm64: dts: mediatek: mt8188-geralt: Add little core CPU power supplies The device tree for the MT8188 Geralt is missing power supplies for all the CPU cores. Power for the little cores is fed from the MT6359 PMIC. Power for the big cores is fed from an MT6319 PMIC on SPMI. The latter is currently not working in Linux. Add the power supplies for the little cores. Supplies for the big cores will be added once the issue with SPMI is resolved. Reviewed-by: Fei Shao Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8188-geralt.dtsi | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi index d57e0eec676a..4cb23595d17b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi @@ -217,6 +217,30 @@ &cam_vcore { domain-supply = <&mt6359_vproc1_buck_reg>; }; +&cpu0 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu1 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu2 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu3 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu4 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu5 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + /* * Geralt is the reference design and doesn't have target TDP. * Ciri is (currently) the only device following Geralt, and its From 7264d37c63139f2ce8c073ead1ed4409fbba12d6 Mon Sep 17 00:00:00 2001 From: Gary Bisson Date: Tue, 10 Mar 2026 16:20:13 +0100 Subject: [PATCH 261/665] arm64: dts: mediatek: mt8390-tungsten-smarc: add HDMI support Add HDMI display out support to both Tungsten510 & Tungsten700 platforms. HDMI audio is not covered by this patch, audio (HDMI & I2S) will be added as a follow-up patch. Signed-off-by: Gary Bisson Signed-off-by: AngeloGioacchino Del Regno --- .../dts/mediatek/mt8390-tungsten-smarc.dtsi | 116 ++++++++++++++++++ 1 file changed, 116 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi index 2e68e997dff3..9f5a0ec563e8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi @@ -46,6 +46,20 @@ chosen { stdout-path = "serial0:115200n8"; }; + connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + ddc-i2c-bus = <&hdmi_ddc>; + hdmi-pwr-supply = <&hdmi_phy>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi0_out>; + }; + }; + }; + firmware { optee { compatible = "linaro,optee-tz"; @@ -283,6 +297,18 @@ &dither0_out { remote-endpoint = <&dsi0_in>; }; +&dpi1 { + status = "okay"; +}; + +&dpi1_in { + remote-endpoint = <&merge5_out>; +}; + +&dpi1_out { + remote-endpoint = <&hdmi0_in>; +}; + ð { phy-mode ="rgmii-id"; phy-handle = <ðernet_phy0>; @@ -304,6 +330,35 @@ ethernet_phy0: ethernet-phy@7 { }; }; +ðdr0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ethdr0_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&vdosys1_ep_ext>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ethdr0_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&merge5_in>; + }; + }; + }; +}; + &gamma0_out { remote-endpoint = <&postmask0_in>; }; @@ -313,6 +368,26 @@ &gpu { status = "okay"; }; +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins>; + status = "okay"; +}; + +&hdmi0_in { + remote-endpoint = <&dpi1_out>; +}; + +&hdmi0_out { + remote-endpoint = <&hdmi_connector_in>; +}; + +&hdmi_phy { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_vreg_pins>; + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; @@ -531,6 +606,35 @@ touchscren@5d { }; }; +&merge5 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + merge5_in: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + merge5_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&dpi1_in>; + }; + }; + }; +}; + &mfg0 { domain-supply = <&mt6359_vproc2_buck_reg>; }; @@ -977,6 +1081,18 @@ vdosys0_ep_main: endpoint@0 { }; }; +&vdosys1 { + port { + #address-cells = <1>; + #size-cells = <0>; + + vdosys1_ep_ext: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_in>; + }; + }; +}; + &watchdog { pinctrl-names = "default"; pinctrl-0 = <&watchdog_pins>; From f92b778251ada37dc433a7f9547c5d2e5ebcdf7d Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Thu, 7 May 2026 22:38:27 +0530 Subject: [PATCH 262/665] dt-bindings: clock: add Qualcomm IPQ9650 GCC Add binding for the Qualcomm IPQ9650 Global Clock Controller. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Kathiravan Thirumoorthy Link: https://lore.kernel.org/r/20260507-ipq9650_boot_to_shell-v3-1-62742b49c991@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,ipq9650-gcc.yaml | 68 ++++++ include/dt-bindings/clock/qcom,ipq9650-gcc.h | 172 ++++++++++++++ include/dt-bindings/reset/qcom,ipq9650-gcc.h | 215 ++++++++++++++++++ 3 files changed, 455 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9650-gcc.yaml create mode 100644 include/dt-bindings/clock/qcom,ipq9650-gcc.h create mode 100644 include/dt-bindings/reset/qcom,ipq9650-gcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9650-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9650-gcc.yaml new file mode 100644 index 000000000000..f33105217a06 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9650-gcc.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq9650-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on IPQ9650 + +maintainers: + - Bjorn Andersson + - Kathiravan Thirumoorthy + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on IPQ9650 + + See also: + include/dt-bindings/clock/qcom,ipq9650-gcc.h + include/dt-bindings/reset/qcom,ipq9650-gcc.h + +properties: + compatible: + const: qcom,ipq9650-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIE30 PHY0 pipe clock source + - description: PCIE30 PHY1 pipe clock source + - description: PCIE30 PHY2 pipe clock source + - description: PCIE30 PHY3 pipe clock source + - description: PCIE30 PHY4 pipe clock source + - description: USB PCIE wrapper pipe clock source + - description: NSS common clock source + + '#power-domain-cells': false + + '#interconnect-cells': + const: 1 + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + clock-controller@1800000 { + compatible = "qcom,ipq9650-gcc"; + reg = <0x01800000 0x40000>; + clocks = <&xo_board_clk>, + <&sleep_clk>, + <&pcie30_phy0_pipe_clk>, + <&pcie30_phy1_pipe_clk>, + <&pcie30_phy2_pipe_clk>, + <&pcie30_phy3_pipe_clk>, + <&pcie30_phy4_pipe_clk>, + <&usb3phy_0_cc_pipe_clk>, + <&nss_cmn_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,ipq9650-gcc.h b/include/dt-bindings/clock/qcom,ipq9650-gcc.h new file mode 100644 index 000000000000..afd17c00d96e --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq9650-gcc.h @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ9650_H +#define _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ9650_H + +#define GCC_ADSS_PWM_CLK 0 +#define GCC_ADSS_PWM_CLK_SRC 1 +#define GCC_ANOC_PCIE0_1LANE_M_CLK 2 +#define GCC_ANOC_PCIE0_1LANE_S_CLK 3 +#define GCC_ANOC_PCIE1_2LANE_M_CLK 4 +#define GCC_ANOC_PCIE1_2LANE_S_CLK 5 +#define GCC_ANOC_PCIE2_2LANE_M_CLK 6 +#define GCC_ANOC_PCIE2_2LANE_S_CLK 7 +#define GCC_ANOC_PCIE3_2LANE_M_CLK 8 +#define GCC_ANOC_PCIE3_2LANE_S_CLK 9 +#define GCC_ANOC_PCIE4_1LANE_M_CLK 10 +#define GCC_ANOC_PCIE4_1LANE_S_CLK 11 +#define GCC_CMN_12GPLL_AHB_CLK 12 +#define GCC_CMN_12GPLL_APU_CLK 13 +#define GCC_CMN_12GPLL_SYS_CLK 14 +#define GCC_CMN_LDO_CLK 15 +#define GCC_MDIO_AHB_CLK 16 +#define GCC_NSSCC_CLK 17 +#define GCC_NSSCFG_CLK 18 +#define GCC_NSSNOC_ATB_CLK 19 +#define GCC_NSSNOC_MEMNOC_1_CLK 20 +#define GCC_NSSNOC_MEMNOC_BFDCD_CLK_SRC 21 +#define GCC_NSSNOC_MEMNOC_CLK 22 +#define GCC_NSSNOC_MEMNOC_DIV_CLK_SRC 23 +#define GCC_NSSNOC_NSSCC_CLK 24 +#define GCC_NSSNOC_PCNOC_1_CLK 25 +#define GCC_NSSNOC_QOSGEN_REF_CLK 26 +#define GCC_NSSNOC_SNOC_1_CLK 27 +#define GCC_NSSNOC_SNOC_CLK 28 +#define GCC_NSSNOC_TIMEOUT_REF_CLK 29 +#define GCC_NSSNOC_XO_DCD_CLK 30 +#define GCC_NSS_TS_CLK 31 +#define GCC_NSS_TS_CLK_SRC 32 +#define GCC_PCIE0_AHB_CLK 33 +#define GCC_PCIE0_AUX_CLK 34 +#define GCC_PCIE0_AXI_M_CLK 35 +#define GCC_PCIE0_AXI_M_CLK_SRC 36 +#define GCC_PCIE0_AXI_S_BRIDGE_CLK 37 +#define GCC_PCIE0_AXI_S_CLK 38 +#define GCC_PCIE0_AXI_S_CLK_SRC 39 +#define GCC_PCIE0_PIPE_CLK 40 +#define GCC_PCIE0_PIPE_CLK_SRC 41 +#define GCC_PCIE0_RCHNG_CLK 42 +#define GCC_PCIE0_RCHNG_CLK_SRC 43 +#define GCC_PCIE1_AHB_CLK 44 +#define GCC_PCIE1_AUX_CLK 45 +#define GCC_PCIE1_AXI_M_CLK 46 +#define GCC_PCIE1_AXI_M_CLK_SRC 47 +#define GCC_PCIE1_AXI_S_BRIDGE_CLK 48 +#define GCC_PCIE1_AXI_S_CLK 49 +#define GCC_PCIE1_AXI_S_CLK_SRC 50 +#define GCC_PCIE1_PIPE_CLK 51 +#define GCC_PCIE1_PIPE_CLK_SRC 52 +#define GCC_PCIE1_RCHNG_CLK 53 +#define GCC_PCIE1_RCHNG_CLK_SRC 54 +#define GCC_PCIE2_AHB_CLK 55 +#define GCC_PCIE2_AUX_CLK 56 +#define GCC_PCIE2_AXI_M_CLK 57 +#define GCC_PCIE2_AXI_M_CLK_SRC 58 +#define GCC_PCIE2_AXI_S_BRIDGE_CLK 59 +#define GCC_PCIE2_AXI_S_CLK 60 +#define GCC_PCIE2_AXI_S_CLK_SRC 61 +#define GCC_PCIE2_PIPE_CLK 62 +#define GCC_PCIE2_PIPE_CLK_SRC 63 +#define GCC_PCIE2_RCHNG_CLK 64 +#define GCC_PCIE2_RCHNG_CLK_SRC 65 +#define GCC_PCIE3_AHB_CLK 66 +#define GCC_PCIE3_AUX_CLK 67 +#define GCC_PCIE3_AXI_M_CLK 68 +#define GCC_PCIE3_AXI_M_CLK_SRC 69 +#define GCC_PCIE3_AXI_S_BRIDGE_CLK 70 +#define GCC_PCIE3_AXI_S_CLK 71 +#define GCC_PCIE3_AXI_S_CLK_SRC 72 +#define GCC_PCIE3_PIPE_CLK 73 +#define GCC_PCIE3_PIPE_CLK_SRC 74 +#define GCC_PCIE3_RCHNG_CLK 75 +#define GCC_PCIE3_RCHNG_CLK_SRC 76 +#define GCC_PCIE4_AHB_CLK 77 +#define GCC_PCIE4_AUX_CLK 78 +#define GCC_PCIE4_AXI_M_CLK 79 +#define GCC_PCIE4_AXI_M_CLK_SRC 80 +#define GCC_PCIE4_AXI_S_BRIDGE_CLK 81 +#define GCC_PCIE4_AXI_S_CLK 82 +#define GCC_PCIE4_AXI_S_CLK_SRC 83 +#define GCC_PCIE4_PIPE_CLK 84 +#define GCC_PCIE4_PIPE_CLK_SRC 85 +#define GCC_PCIE4_RCHNG_CLK 86 +#define GCC_PCIE4_RCHNG_CLK_SRC 87 +#define GCC_PCIE_AUX_CLK_SRC 88 +#define GCC_PCNOC_BFDCD_CLK_SRC 89 +#define GCC_QDSS_AT_CLK 90 +#define GCC_QDSS_AT_CLK_SRC 91 +#define GCC_QDSS_DAP_CLK 92 +#define GCC_QDSS_TSCTR_CLK_SRC 93 +#define GCC_QPIC_AHB_CLK 94 +#define GCC_QPIC_CLK 95 +#define GCC_QPIC_CLK_SRC 96 +#define GCC_QPIC_IO_MACRO_CLK 97 +#define GCC_QPIC_IO_MACRO_CLK_SRC 98 +#define GCC_QPIC_SLEEP_CLK 99 +#define GCC_QUPV3_2X_CORE_CLK 100 +#define GCC_QUPV3_2X_CORE_CLK_SRC 101 +#define GCC_QUPV3_AHB_MST_CLK 102 +#define GCC_QUPV3_AHB_SLV_CLK 103 +#define GCC_QUPV3_CORE_CLK 104 +#define GCC_QUPV3_SLEEP_CLK 105 +#define GCC_QUPV3_WRAP_SE0_CLK 106 +#define GCC_QUPV3_WRAP_SE0_CLK_SRC 107 +#define GCC_QUPV3_WRAP_SE1_CLK 108 +#define GCC_QUPV3_WRAP_SE1_CLK_SRC 109 +#define GCC_QUPV3_WRAP_SE2_CLK 110 +#define GCC_QUPV3_WRAP_SE2_CLK_SRC 111 +#define GCC_QUPV3_WRAP_SE3_CLK 112 +#define GCC_QUPV3_WRAP_SE3_CLK_SRC 113 +#define GCC_QUPV3_WRAP_SE4_CLK 114 +#define GCC_QUPV3_WRAP_SE4_CLK_SRC 115 +#define GCC_QUPV3_WRAP_SE5_CLK 116 +#define GCC_QUPV3_WRAP_SE5_CLK_SRC 117 +#define GCC_QUPV3_WRAP_SE6_CLK 118 +#define GCC_QUPV3_WRAP_SE6_CLK_SRC 119 +#define GCC_QUPV3_WRAP_SE7_CLK 120 +#define GCC_QUPV3_WRAP_SE7_CLK_SRC 121 +#define GCC_SDCC1_AHB_CLK 122 +#define GCC_SDCC1_APPS_CLK 123 +#define GCC_SDCC1_APPS_CLK_SRC 124 +#define GCC_SDCC1_ICE_CORE_CLK 125 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 126 +#define GCC_SLEEP_CLK_SRC 127 +#define GCC_SNOC_USB_CLK 128 +#define GCC_SYSTEM_NOC_BFDCD_CLK_SRC 129 +#define GCC_TLMM_AHB_CLK 130 +#define GCC_TLMM_CLK 131 +#define GCC_UNIPHY0_AHB_CLK 132 +#define GCC_UNIPHY0_SYS_CLK 133 +#define GCC_UNIPHY1_AHB_CLK 134 +#define GCC_UNIPHY1_SYS_CLK 135 +#define GCC_UNIPHY2_AHB_CLK 136 +#define GCC_UNIPHY2_SYS_CLK 137 +#define GCC_UNIPHY_SYS_CLK_SRC 138 +#define GCC_USB0_AUX_CLK 139 +#define GCC_USB0_AUX_CLK_SRC 140 +#define GCC_USB0_EUD_AT_CLK 141 +#define GCC_USB0_MASTER_CLK 142 +#define GCC_USB0_MASTER_CLK_SRC 143 +#define GCC_USB0_MOCK_UTMI_CLK 144 +#define GCC_USB0_MOCK_UTMI_CLK_SRC 145 +#define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC 146 +#define GCC_USB0_PHY_CFG_AHB_CLK 147 +#define GCC_USB0_PIPE_CLK 148 +#define GCC_USB0_PIPE_CLK_SRC 149 +#define GCC_USB0_SLEEP_CLK 150 +#define GCC_USB1_MASTER_CLK 151 +#define GCC_USB1_MOCK_UTMI_CLK 152 +#define GCC_USB1_MOCK_UTMI_CLK_SRC 153 +#define GCC_USB1_MOCK_UTMI_DIV_CLK_SRC 154 +#define GCC_USB1_PHY_CFG_AHB_CLK 155 +#define GCC_USB1_SLEEP_CLK 156 +#define GCC_XO_CLK_SRC 157 +#define GPLL0 158 +#define GPLL0_MAIN 159 +#define GPLL2 160 +#define GPLL2_OUT_MAIN 161 +#define GPLL4 162 +#endif diff --git a/include/dt-bindings/reset/qcom,ipq9650-gcc.h b/include/dt-bindings/reset/qcom,ipq9650-gcc.h new file mode 100644 index 000000000000..a2cbb114addd --- /dev/null +++ b/include/dt-bindings/reset/qcom,ipq9650-gcc.h @@ -0,0 +1,215 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_RESET_IPQ_GCC_IPQ9650_H +#define _DT_BINDINGS_RESET_IPQ_GCC_IPQ9650_H + +#define GCC_ADSS_BCR 0 +#define GCC_ADSS_PWM_CLK_ARES 1 +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 2 +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES 3 +#define GCC_APSS_AHB_CLK_ARES 4 +#define GCC_APSS_ATB_CLK_ARES 5 +#define GCC_APSS_AXI_CLK_ARES 6 +#define GCC_APSS_TS_CLK_ARES 7 +#define GCC_BOOT_ROM_AHB_CLK_ARES 8 +#define GCC_BOOT_ROM_BCR 9 +#define GCC_CMN_12GPLL_AHB_CLK_ARES 10 +#define GCC_CMN_12GPLL_APU_CLK_ARES 11 +#define GCC_CMN_12GPLL_SYS_CLK_ARES 12 +#define GCC_CMN_BLK_BCR 13 +#define GCC_CMN_LDO_CLK_ARES 14 +#define GCC_CPUSS_TRIG_CLK_ARES 15 +#define GCC_GP1_CLK_ARES 16 +#define GCC_GP2_CLK_ARES 17 +#define GCC_GP3_CLK_ARES 18 +#define GCC_MDIO_AHB_CLK_ARES 19 +#define GCC_MDIO_BCR 20 +#define GCC_NSSCC_CLK_ARES 21 +#define GCC_NSSCFG_CLK_ARES 22 +#define GCC_NSSNOC_ATB_CLK_ARES 23 +#define GCC_NSSNOC_MEMNOC_1_CLK_ARES 24 +#define GCC_NSSNOC_MEMNOC_CLK_ARES 25 +#define GCC_NSSNOC_NSSCC_CLK_ARES 26 +#define GCC_NSSNOC_PCNOC_1_CLK_ARES 27 +#define GCC_NSSNOC_QOSGEN_REF_CLK_ARES 28 +#define GCC_NSSNOC_SNOC_1_CLK_ARES 29 +#define GCC_NSSNOC_SNOC_CLK_ARES 30 +#define GCC_NSSNOC_TIMEOUT_REF_CLK_ARES 31 +#define GCC_NSSNOC_XO_DCD_CLK_ARES 32 +#define GCC_NSS_BCR 33 +#define GCC_NSS_TS_CLK_ARES 34 +#define GCC_PCIE0PHY_PHY_BCR 35 +#define GCC_PCIE0_AHB_CLK_ARES 36 +#define GCC_PCIE0_AHB_RESET 37 +#define GCC_PCIE0_AUX_CLK_ARES 38 +#define GCC_PCIE0_AUX_RESET 39 +#define GCC_PCIE0_AXI_M_CLK_ARES 40 +#define GCC_PCIE0_AXI_M_RESET 41 +#define GCC_PCIE0_AXI_M_STICKY_RESET 42 +#define GCC_PCIE0_AXI_S_BRIDGE_CLK_ARES 43 +#define GCC_PCIE0_AXI_S_CLK_ARES 44 +#define GCC_PCIE0_AXI_S_RESET 45 +#define GCC_PCIE0_AXI_S_STICKY_RESET 46 +#define GCC_PCIE0_BCR 47 +#define GCC_PCIE0_CORE_STICKY_RESET 48 +#define GCC_PCIE0_LINK_DOWN_BCR 49 +#define GCC_PCIE0_PHY_BCR 50 +#define GCC_PCIE0_PIPE_CLK_ARES 51 +#define GCC_PCIE0_PIPE_RESET 52 +#define GCC_PCIE1PHY_PHY_BCR 53 +#define GCC_PCIE1_AHB_CLK_ARES 54 +#define GCC_PCIE1_AHB_RESET 55 +#define GCC_PCIE1_AUX_CLK_ARES 56 +#define GCC_PCIE1_AUX_RESET 57 +#define GCC_PCIE1_AXI_M_CLK_ARES 58 +#define GCC_PCIE1_AXI_M_RESET 59 +#define GCC_PCIE1_AXI_M_STICKY_RESET 60 +#define GCC_PCIE1_AXI_S_BRIDGE_CLK_ARES 61 +#define GCC_PCIE1_AXI_S_CLK_ARES 62 +#define GCC_PCIE1_AXI_S_RESET 63 +#define GCC_PCIE1_AXI_S_STICKY_RESET 64 +#define GCC_PCIE1_BCR 65 +#define GCC_PCIE1_CORE_STICKY_RESET 66 +#define GCC_PCIE1_LINK_DOWN_BCR 67 +#define GCC_PCIE1_PHY_BCR 68 +#define GCC_PCIE1_PIPE_CLK_ARES 69 +#define GCC_PCIE1_PIPE_RESET 70 +#define GCC_PCIE2PHY_PHY_BCR 71 +#define GCC_PCIE2_AHB_CLK_ARES 72 +#define GCC_PCIE2_AHB_RESET 73 +#define GCC_PCIE2_AUX_CLK_ARES 74 +#define GCC_PCIE2_AUX_RESET 75 +#define GCC_PCIE2_AXI_M_CLK_ARES 76 +#define GCC_PCIE2_AXI_M_RESET 77 +#define GCC_PCIE2_AXI_M_STICKY_RESET 78 +#define GCC_PCIE2_AXI_S_BRIDGE_CLK_ARES 79 +#define GCC_PCIE2_AXI_S_CLK_ARES 80 +#define GCC_PCIE2_AXI_S_RESET 81 +#define GCC_PCIE2_AXI_S_STICKY_RESET 82 +#define GCC_PCIE2_BCR 83 +#define GCC_PCIE2_CORE_STICKY_RESET 84 +#define GCC_PCIE2_LINK_DOWN_BCR 85 +#define GCC_PCIE2_PHY_BCR 86 +#define GCC_PCIE2_PIPE_CLK_ARES 87 +#define GCC_PCIE2_PIPE_RESET 88 +#define GCC_PCIE3PHY_PHY_BCR 89 +#define GCC_PCIE3_AHB_CLK_ARES 90 +#define GCC_PCIE3_AHB_RESET 91 +#define GCC_PCIE3_AUX_CLK_ARES 92 +#define GCC_PCIE3_AUX_RESET 93 +#define GCC_PCIE3_AXI_M_CLK_ARES 94 +#define GCC_PCIE3_AXI_M_RESET 95 +#define GCC_PCIE3_AXI_M_STICKY_RESET 96 +#define GCC_PCIE3_AXI_S_BRIDGE_CLK_ARES 97 +#define GCC_PCIE3_AXI_S_CLK_ARES 98 +#define GCC_PCIE3_AXI_S_RESET 99 +#define GCC_PCIE3_AXI_S_STICKY_RESET 100 +#define GCC_PCIE3_BCR 101 +#define GCC_PCIE3_CORE_STICKY_RESET 102 +#define GCC_PCIE3_LINK_DOWN_BCR 103 +#define GCC_PCIE3_PHY_BCR 104 +#define GCC_PCIE3_PIPE_CLK_ARES 105 +#define GCC_PCIE3_PIPE_RESET 106 +#define GCC_PCIE4PHY_PHY_BCR 107 +#define GCC_PCIE4_AHB_CLK_ARES 108 +#define GCC_PCIE4_AHB_RESET 109 +#define GCC_PCIE4_AUX_CLK_ARES 110 +#define GCC_PCIE4_AUX_RESET 111 +#define GCC_PCIE4_AXI_M_CLK_ARES 112 +#define GCC_PCIE4_AXI_M_RESET 113 +#define GCC_PCIE4_AXI_M_STICKY_RESET 114 +#define GCC_PCIE4_AXI_S_BRIDGE_CLK_ARES 115 +#define GCC_PCIE4_AXI_S_CLK_ARES 116 +#define GCC_PCIE4_AXI_S_RESET 117 +#define GCC_PCIE4_AXI_S_STICKY_RESET 118 +#define GCC_PCIE4_BCR 119 +#define GCC_PCIE4_CORE_STICKY_RESET 120 +#define GCC_PCIE4_LINK_DOWN_BCR 121 +#define GCC_PCIE4_PHY_BCR 122 +#define GCC_PCIE4_PIPE_CLK_ARES 123 +#define GCC_PCIE4_PIPE_RESET 124 +#define GCC_QDSS_APB2JTAG_CLK_ARES 125 +#define GCC_QDSS_AT_CLK_ARES 126 +#define GCC_QDSS_BCR 127 +#define GCC_QDSS_CFG_AHB_CLK_ARES 128 +#define GCC_QDSS_DAP_AHB_CLK_ARES 129 +#define GCC_QDSS_DAP_CLK_ARES 130 +#define GCC_QDSS_ETR_USB_CLK_ARES 131 +#define GCC_QDSS_EUD_AT_CLK_ARES 132 +#define GCC_QDSS_STM_CLK_ARES 133 +#define GCC_QDSS_TRACECLKIN_CLK_ARES 134 +#define GCC_QDSS_TSCTR_DIV16_CLK_ARES 135 +#define GCC_QDSS_TSCTR_DIV2_CLK_ARES 136 +#define GCC_QDSS_TSCTR_DIV3_CLK_ARES 137 +#define GCC_QDSS_TSCTR_DIV4_CLK_ARES 138 +#define GCC_QDSS_TSCTR_DIV8_CLK_ARES 139 +#define GCC_QDSS_TS_CLK_ARES 140 +#define GCC_QPIC_AHB_CLK_ARES 141 +#define GCC_QPIC_BCR 142 +#define GCC_QPIC_CLK_ARES 143 +#define GCC_QPIC_IO_MACRO_CLK_ARES 144 +#define GCC_QPIC_SLEEP_CLK_ARES 145 +#define GCC_QUPV3_2X_CORE_CLK_ARES 146 +#define GCC_QUPV3_AHB_MST_CLK_ARES 147 +#define GCC_QUPV3_AHB_SLV_CLK_ARES 148 +#define GCC_QUPV3_BCR 149 +#define GCC_QUPV3_CORE_CLK_ARES 150 +#define GCC_QUPV3_WRAP_SE0_BCR 151 +#define GCC_QUPV3_WRAP_SE0_CLK_ARES 152 +#define GCC_QUPV3_WRAP_SE1_BCR 153 +#define GCC_QUPV3_WRAP_SE1_CLK_ARES 154 +#define GCC_QUPV3_WRAP_SE2_BCR 155 +#define GCC_QUPV3_WRAP_SE2_CLK_ARES 156 +#define GCC_QUPV3_WRAP_SE3_BCR 157 +#define GCC_QUPV3_WRAP_SE3_CLK_ARES 158 +#define GCC_QUPV3_WRAP_SE4_BCR 159 +#define GCC_QUPV3_WRAP_SE4_CLK_ARES 160 +#define GCC_QUPV3_WRAP_SE5_BCR 161 +#define GCC_QUPV3_WRAP_SE5_CLK_ARES 162 +#define GCC_QUPV3_WRAP_SE6_BCR 163 +#define GCC_QUPV3_WRAP_SE6_CLK_ARES 164 +#define GCC_QUPV3_WRAP_SE7_BCR 165 +#define GCC_QUPV3_WRAP_SE7_CLK_ARES 166 +#define GCC_QUSB2_0_PHY_BCR 167 +#define GCC_QUSB2_1_PHY_BCR 168 +#define GCC_SDCC1_APPS_CLK_ARES 169 +#define GCC_SDCC1_ICE_CORE_CLK_ARES 170 +#define GCC_SDCC_BCR 171 +#define GCC_TLMM_AHB_CLK_ARES 172 +#define GCC_TLMM_BCR 173 +#define GCC_TLMM_CLK_ARES 174 +#define GCC_UNIPHY0_AHB_CLK_ARES 175 +#define GCC_UNIPHY0_BCR 176 +#define GCC_UNIPHY0_PMA_BCR 177 +#define GCC_UNIPHY0_SYS_CLK_ARES 178 +#define GCC_UNIPHY0_XPCS_ARES 179 +#define GCC_UNIPHY1_AHB_CLK_ARES 180 +#define GCC_UNIPHY1_BCR 181 +#define GCC_UNIPHY1_PMA_BCR 182 +#define GCC_UNIPHY1_SYS_CLK_ARES 183 +#define GCC_UNIPHY1_XPCS_ARES 184 +#define GCC_UNIPHY2_AHB_CLK_ARES 185 +#define GCC_UNIPHY2_BCR 186 +#define GCC_UNIPHY2_PMA_BCR 187 +#define GCC_UNIPHY2_SYS_CLK_ARES 188 +#define GCC_UNIPHY2_XPCS_ARES 189 +#define GCC_USB0_AUX_CLK_ARES 190 +#define GCC_USB0_MASTER_CLK_ARES 191 +#define GCC_USB0_MOCK_UTMI_CLK_ARES 192 +#define GCC_USB0_PHY_BCR 193 +#define GCC_USB0_PHY_CFG_AHB_CLK_ARES 194 +#define GCC_USB0_PIPE_CLK_ARES 195 +#define GCC_USB0_SLEEP_CLK_ARES 196 +#define GCC_USB1_BCR 197 +#define GCC_USB1_MASTER_CLK_ARES 198 +#define GCC_USB1_MOCK_UTMI_CLK_ARES 199 +#define GCC_USB1_PHY_CFG_AHB_CLK_ARES 200 +#define GCC_USB1_SLEEP_CLK_ARES 201 +#define GCC_USB3PHY_0_PHY_BCR 202 +#define GCC_USB_BCR 203 +#define GCC_UNIPHY1_XLGPCS_ARES 204 +#define GCC_UNIPHY2_XLGPCS_ARES 205 +#endif From 5bfa2c53c675610110c797e1f17c87ce25424407 Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Thu, 7 May 2026 22:38:29 +0530 Subject: [PATCH 263/665] dt-bindings: qcom: add IPQ9650 boards Document the new IPQ9650 SoC/board device tree bindings. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Kathiravan Thirumoorthy Link: https://lore.kernel.org/r/20260507-ipq9650_boot_to_shell-v3-3-62742b49c991@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 2741c07e9f41..af266d584fae 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -366,6 +366,11 @@ properties: - qcom,ipq9574-ap-al02-c9 - const: qcom,ipq9574 + - items: + - enum: + - qcom,ipq9650-rdp488 + - const: qcom,ipq9650 + - items: - enum: - qcom,kaanapali-mtp From 8cef25a0044d3e7caef56a43bf316336fe39b5d8 Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Thu, 7 May 2026 22:38:30 +0530 Subject: [PATCH 264/665] arm64: dts: qcom: add IPQ9650 SoC and rdp488 board support Add initial device tree support for the Qualcomm IPQ9650 SoC and rdp488 board. Signed-off-by: Kathiravan Thirumoorthy Link: https://lore.kernel.org/r/20260507-ipq9650_boot_to_shell-v3-4-62742b49c991@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq9650-rdp488.dts | 79 ++++ arch/arm64/boot/dts/qcom/ipq9650.dtsi | 377 ++++++++++++++++++++ 3 files changed, 457 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq9650-rdp488.dts create mode 100644 arch/arm64/boot/dts/qcom/ipq9650.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 35252ea586a5..795cee4757ab 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -39,6 +39,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb ipq9574-rdp433-emmc.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp453.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq9650-rdp488.dtb dtb-$(CONFIG_ARCH_QCOM) += kaanapali-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += kaanapali-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += lemans-evk.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq9650-rdp488.dts b/arch/arm64/boot/dts/qcom/ipq9650-rdp488.dts new file mode 100644 index 000000000000..6871f3dc4eaf --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq9650-rdp488.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "ipq9650.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ9650 RDP488"; + compatible = "qcom,ipq9650-rdp488", "qcom,ipq9650"; + + aliases { + serial0 = &uart1; + }; + + chosen { + stdout-path = "serial0"; + }; +}; + +&sdhc { + max-frequency = <192000000>; + bus-width = <4>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + pinctrl-0 = <&sdhc_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + qup_uart1_default_state: qup-uart1-default-state { + pins = "gpio43", "gpio44"; + function = "qup_se6"; + drive-strength = <8>; + bias-pull-down; + }; + + sdhc_default_state: sdhc-default-state { + clk-pins { + pins = "gpio5"; + function = "sdc_clk"; + drive-strength = <8>; + bias-disable; + }; + + cmd-pins { + pins = "gpio4"; + function = "sdc_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + data-pins { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "sdc_data"; + drive-strength = <8>; + bias-pull-up; + }; + }; +}; + +&uart1 { + pinctrl-0 = <&qup_uart1_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&xo_board { + clock-frequency = <24000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq9650.dtsi b/arch/arm64/boot/dts/qcom/ipq9650.dtsi new file mode 100644 index 000000000000..a1bea8e648cd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq9650.dtsi @@ -0,0 +1,377 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&intc>; + + clocks { + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + xo_board: xo-board-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + next-level-cache = <&l2_0>; + + l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + + l3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-unified; + }; + }; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + next-level-cache = <&l2_100>; + + l2_100: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + + l2_200: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + + l2_300: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x400>; + enable-method = "psci"; + next-level-cache = <&l2_400>; + + l2_400: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + + core4 { + cpu = <&cpu4>; + }; + }; + }; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + scm { + compatible = "qcom,scm-ipq9650", "qcom,scm"; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupts = ; + }; + + pmu-a78 { + compatible = "arm,cortex-a78-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + bootloader@8a100000 { + reg = <0x0 0x8a100000 0x0 0x400000>; + no-map; + }; + + smem@8a500000 { + compatible = "qcom,smem"; + reg = <0x0 0x8a500000 0x0 0x40000>; + no-map; + + hwlocks = <&tcsr_mutex 3>; + }; + + tfa@8a600000 { + reg = <0x0 0x8a600000 0x0 0x80000>; + no-map; + }; + + optee@8a680000 { + reg = <0x0 0x8a680000 0x0 0x280000>; + no-map; + }; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0 0 0 0 0x10 0>; + ranges = <0 0 0 0 0x10 0>; + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq9650-tlmm"; + reg = <0x0 0x01000000 0x0 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 54>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gcc: clock-controller@1800000 { + compatible = "qcom,ipq9650-gcc"; + reg = <0x0 0x01800000 0x0 0x40000>; + clocks = <&xo_board>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + tcsr_mutex: hwlock@1917000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01917000 0x0 0x57000>; + #hwlock-cells = <1>; + }; + + qupv3: geniqup@1ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x01ac0000 0x0 0x2000>; + clocks = <&gcc GCC_QUPV3_AHB_MST_CLK>, + <&gcc GCC_QUPV3_AHB_SLV_CLK>; + clock-names = "m-ahb", "s-ahb"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + uart1: serial@1a98000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x01a98000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP_SE6_CLK>; + clock-names = "se"; + interrupts = ; + + status = "disabled"; + }; + }; + + sdhc: mmc@7804000 { + compatible = "qcom,ipq9650-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x07804000 0x0 0x1000>, + <0x0 0x07805000 0x0 0x1000>; + reg-names = "hc", + "cqhci"; + + interrupts = , + ; + interrupt-names = "hc_irq", + "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>; + clock-names = "iface", + "core", + "xo"; + non-removable; + + status = "disabled"; + }; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x0f200000 0x0 0x10000>, + <0x0 0x0f240000 0x0 0xa0000>; + #interrupt-cells = <0x4>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + interrupts = ; + mbi-ranges = <800 160>; + msi-controller; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu4>; + }; + }; + }; + + timer@f420000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x0f420000 0x0 0x1000>; + ranges = <0 0 0 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + + frame@f421000 { + reg = <0x0f421000 0x1000>, + <0x0f422000 0x1000>; + interrupts = , + ; + frame-number = <0>; + }; + + frame@f423000 { + reg = <0x0f423000 0x1000>; + interrupts = ; + frame-number = <1>; + + status = "disabled"; + }; + + frame@f425000 { + reg = <0x0f425000 0x1000>, + <0x0f426000 0x1000>; + interrupts = ; + frame-number = <2>; + + status = "disabled"; + }; + + frame@f427000 { + reg = <0x0f427000 0x1000>; + interrupts = ; + frame-number = <3>; + + status = "disabled"; + }; + + frame@f429000 { + reg = <0x0f429000 0x1000>; + interrupts = ; + frame-number = <4>; + + status = "disabled"; + }; + + frame@f42b000 { + reg = <0x0f42b000 0x1000>; + interrupts = ; + frame-number = <5>; + + status = "disabled"; + }; + + frame@f42d000 { + reg = <0x0f42d000 0x1000>; + interrupts = ; + frame-number = <6>; + + status = "disabled"; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + , + ; + }; +}; From c50080d313d35a54c7847536ce9e27ad62546251 Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Mon, 11 May 2026 22:24:54 +0530 Subject: [PATCH 265/665] arm64: dts: qcom: ipq9650: add watchdog node Add the watchdog device node for IPQ9650 SoC. Signed-off-by: Kathiravan Thirumoorthy Link: https://lore.kernel.org/r/20260511-ipq9650_wdt-v1-1-1948934c1e12@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq9650.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9650.dtsi b/arch/arm64/boot/dts/qcom/ipq9650.dtsi index a1bea8e648cd..3d3b317c6a3c 100644 --- a/arch/arm64/boot/dts/qcom/ipq9650.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9650.dtsi @@ -300,6 +300,13 @@ ppi_cluster1: interrupt-partition-1 { }; }; + watchdog@f410000 { + compatible = "qcom,apss-wdt-ipq9650", "qcom,kpss-wdt"; + reg = <0x0 0x0f410000 0x0 0x1000>; + interrupts = ; + clocks = <&sleep_clk>; + }; + timer@f420000 { compatible = "arm,armv7-timer-mem"; reg = <0x0 0x0f420000 0x0 0x1000>; From d9dc254945756b44fa6f61b9cbd4adf0413c6a6f Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 15 Apr 2026 10:52:57 +0300 Subject: [PATCH 266/665] arm64: dts: qcom: glymur-crd: Drop forced host mode for USB SS0 and SS1 The two USB Type-C ports on Glymur CRD are dual-role capable. Do not force their controllers into host mode. Drop the explicit 'dr_mode = "host"' properties so they can use their default OTG mode instead. Fixes: c8b63029455b ("arm64: dts: qcom: glymur-crd: Enable USB support") Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20260415-dts-qcom-glymur-usb-role-switch-fix-v1-2-409e1a257f1f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts index 35aaf09e4e2b..c98dfb3941fa 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -322,8 +322,6 @@ reset-n-pins { }; &usb_0 { - dr_mode = "host"; - status = "okay"; }; @@ -353,8 +351,6 @@ &usb_0_qmpphy_out { }; &usb_1 { - dr_mode = "host"; - status = "okay"; }; From 347fa2fa64e1cef0c7897522896c0c66e734c82b Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 15 Apr 2026 10:52:56 +0300 Subject: [PATCH 267/665] arm64: dts: qcom: glymur: Mark USB SS1 and SS2 as role-switch capable Like USB SS0, the USB SS1 and SS2 controllers on Glymur also support USB role switching. Describe this by adding the 'usb-role-switch' property to both controllers. Fixes: 4eee57dd4df9 ("arm64: dts: qcom: glymur: Add USB related nodes") Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20260415-dts-qcom-glymur-usb-role-switch-fix-v1-1-409e1a257f1f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 65c8e9233354..8a239dc359b0 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -3972,6 +3972,8 @@ usb_1: usb@a800000 { snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; + usb-role-switch; + status = "disabled"; ports { @@ -4045,6 +4047,8 @@ usb_2: usb@a000000 { snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; + usb-role-switch; + status = "disabled"; ports { From 675fec65df73b525c12cb7a1c1ef54fcc3296d7c Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 10 Apr 2026 09:19:04 +0530 Subject: [PATCH 268/665] arm64: dts: qcom: Add support for MM clock controllers for Glymur Add the device nodes for the multimedia clock controllers videocc, gpucc and gxclkctl. Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das Link: https://lore.kernel.org/r/20260410-glymur_mmcc_dt_config_v2-v3-1-acce9d106e72@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 47 ++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 8a239dc359b0..5e7c5320dc20 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -5,7 +5,10 @@ #include #include +#include #include +#include +#include #include #include #include @@ -3742,6 +3745,34 @@ hsc_noc: interconnect@2000000 { #interconnect-cells = <2>; }; + gxclkctl: clock-controller@3d64000 { + compatible = "qcom,glymur-gxclkctl"; + reg = <0x0 0x03d64000 0x0 0x6000>; + + power-domains = <&rpmhpd RPMHPD_GFX>, + <&rpmhpd RPMHPD_GMXC>, + <&gpucc GPU_CC_CX_GDSC>; + + #power-domain-cells = <1>; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,glymur-gpucc"; + reg = <0x0 0x03d90000 0x0 0x9800>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + power-domains = <&rpmhpd RPMHPD_MX>, + <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + ipcc: mailbox@3e04000 { compatible = "qcom,glymur-ipcc", "qcom,ipcc"; reg = <0x0 0x03e04000 0x0 0x1000>; @@ -4637,6 +4668,22 @@ mdss_dp3_out: endpoint { }; }; + videocc: clock-controller@aaf0000 { + compatible = "qcom,glymur-videocc"; + reg = <0x0 0x0aaf0000 0x0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>; + + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + dispcc: clock-controller@af00000 { compatible = "qcom,glymur-dispcc"; reg = <0x0 0x0af00000 0x0 0x20000>; From cd1d174c75f70fb0d7204802551aeaeb84689b59 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Fri, 13 Mar 2026 17:38:13 +0530 Subject: [PATCH 269/665] arm64: dts: qcom: glymur: Add ADSP and CDSP for Glymur SoC Add remoteproc PAS loader for ADSP and CDSP with its fastrpc nodes. Signed-off-by: Sibi Sankar Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260313120814.1312410-5-sibi.sankar@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 286 +++++++++++++++++++++++++++ 1 file changed, 286 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 5e7c5320dc20..376fdb3cc8ad 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -3784,6 +3784,122 @@ ipcc: mailbox@3e04000 { #mbox-cells = <2>; }; + remoteproc_adsp: remoteproc@6800000 { + compatible = "qcom,glymur-adsp-pas", "qcom,sm8550-adsp-pas"; + reg = <0x0 0x06800000 0x0 0x10000>; + + iommus = <&apps_smmu 0x1000 0x0>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; + power-domain-names = "lcx", + "lmx"; + + memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + remoteproc_adsp_glink: glink-edge { + interrupts-extended = <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + qcom,remote-pid = <2>; + + label = "lpass"; + + fastrpc { + compatible = "qcom,glymur-fastrpc", "qcom,kaanapali-fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + + iommus = <&apps_smmu 0x1003 0x80>, + <&apps_smmu 0x1063 0x20>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + + iommus = <&apps_smmu 0x1004 0x80>, + <&apps_smmu 0x1064 0x20>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + + iommus = <&apps_smmu 0x1005 0x80>, + <&apps_smmu 0x1065 0x20>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + + iommus = <&apps_smmu 0x1006 0x80>, + <&apps_smmu 0x1066 0x20>; + dma-coherent; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + + iommus = <&apps_smmu 0x1007 0x40>, + <&apps_smmu 0x1067 0x0>, + <&apps_smmu 0x1087 0x0>; + dma-coherent; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + + iommus = <&apps_smmu 0x1008 0x80>, + <&apps_smmu 0x1068 0x20>; + dma-coherent; + }; + }; + }; + }; + lpass_lpiaon_noc: interconnect@7400000 { compatible = "qcom,glymur-lpass-lpiaon-noc"; reg = <0x0 0x07400000 0x0 0x19080>; @@ -6002,6 +6118,176 @@ system-cache-controller@21800000 { interrupts = ; }; + remoteproc_cdsp: remoteproc@32300000 { + compatible = "qcom,glymur-cdsp-pas", "qcom,sm8550-cdsp-pas"; + reg = <0x0 0x32300000 0x0 0x10000>; + + iommus = <&apps_smmu 0x2400 0x400>; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_NSP>; + power-domain-names = "cx", + "mxc", + "nsp"; + + memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&smp2p_cdsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + qcom,remote-pid = <5>; + label = "cdsp"; + + fastrpc { + compatible = "qcom,glymur-fastrpc", "qcom,kaanapali-fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + + iommus = <&apps_smmu 0x2401 0x440>, + <&apps_smmu 0x1961 0x0>, + <&apps_smmu 0x19c1 0x0>; + dma-coherent; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + + iommus = <&apps_smmu 0x2402 0x440>, + <&apps_smmu 0x1962 0x0>, + <&apps_smmu 0x19c2 0x0>; + dma-coherent; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + + iommus = <&apps_smmu 0x2403 0x440>, + <&apps_smmu 0x1963 0x0>, + <&apps_smmu 0x19c3 0x0>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + + iommus = <&apps_smmu 0x2404 0x440>, + <&apps_smmu 0x1964 0x0>, + <&apps_smmu 0x19c4 0x0>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + + iommus = <&apps_smmu 0x2405 0x440>, + <&apps_smmu 0x1965 0x0>, + <&apps_smmu 0x19c5 0x0>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + + iommus = <&apps_smmu 0x2406 0x440>, + <&apps_smmu 0x1966 0x0>, + <&apps_smmu 0x19c6 0x0>; + dma-coherent; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + + iommus = <&apps_smmu 0x2407 0x440>, + <&apps_smmu 0x1967 0x0>, + <&apps_smmu 0x19c7 0x0>; + dma-coherent; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + + iommus = <&apps_smmu 0x2408 0x440>, + <&apps_smmu 0x1968 0x0>, + <&apps_smmu 0x19c8 0x0>; + dma-coherent; + }; + + /* note: compute-cb@9 is secure */ + + compute-cb@10 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <10>; + + iommus = <&apps_smmu 0x240c 0x440>, + <&apps_smmu 0x196c 0x0>, + <&apps_smmu 0x19cc 0x0>; + dma-coherent; + }; + + compute-cb@11 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <11>; + + iommus = <&apps_smmu 0x240d 0x440>, + <&apps_smmu 0x196d 0x0>, + <&apps_smmu 0x19cd 0x0>; + dma-coherent; + }; + + compute-cb@12 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <12>; + + iommus = <&apps_smmu 0x240e 0x440>, + <&apps_smmu 0x196e 0x0>, + <&apps_smmu 0x19ce 0x0>; + dma-coherent; + }; + }; + }; + }; + nsp_noc: interconnect@320c0000 { compatible = "qcom,glymur-nsp-noc"; reg = <0x0 0x320c0000 0x0 0x21280>; From 377665c6078d1aa18d29d56a39d70ed8185cd2d1 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Fri, 13 Mar 2026 17:38:14 +0530 Subject: [PATCH 270/665] arm64: dts: qcom: glymur-crd: Enable ADSP and CDSP Enable ADSP and CDSP on Glymur CRD board. Signed-off-by: Sibi Sankar Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260313120814.1312410-6-sibi.sankar@oss.qualcomm.com [bjorn: Moved snippet to common glymur-crd.dtsi] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi index 357d4ad8380a..e784b538f42e 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -571,6 +571,20 @@ &pon_resin { status = "okay"; }; +&remoteproc_adsp { + firmware-name = "qcom/glymur/adsp.mbn", + "qcom/glymur/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/glymur/cdsp.mbn", + "qcom/glymur/cdsp_dtb.mbn"; + + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */ <10 2>, /* OOB UART */ From 3bee9d4854f2ce24d0a8febed6de94271b135c60 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 27 Oct 2025 22:12:17 +0100 Subject: [PATCH 271/665] arm64: dts: renesas: r8a77960-ulcb: Enable GPU support Enable GPU on M3ULCB with R-Car M3-W. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251027211249.95826-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77960-ulcb.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77960-ulcb.dts b/arch/arm64/boot/dts/renesas/r8a77960-ulcb.dts index 4bfeb1df0488..c3282593346b 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960-ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a77960-ulcb.dts @@ -36,3 +36,7 @@ &du { clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1", "dclkin.2"; }; + +&gpu { + status = "okay"; +}; From 1f07cd3bcc57f87c33ce89e50f7a310834009a3e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 27 Oct 2025 22:12:18 +0100 Subject: [PATCH 272/665] arm64: dts: renesas: r8a77960-salvator-x: Enable GPU support Enable GPU on Salvator-X with R-Car M3-W. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251027211249.95826-2-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77960-salvator-x.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77960-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a77960-salvator-x.dts index d5543f26c472..0d5c754a7f0e 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a77960-salvator-x.dts @@ -35,3 +35,7 @@ &du { clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1", "dclkin.2"; }; + +&gpu { + status = "okay"; +}; From 27f6150e18c97d9aeb50c805f45377b9865bd08b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 27 Oct 2025 22:12:19 +0100 Subject: [PATCH 273/665] arm64: dts: renesas: r8a77960-salvator-xs: Enable GPU support Enable GPU on Salvator-X 2nd version with R-Car M3-W. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251027211249.95826-3-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77960-salvator-xs.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77960-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77960-salvator-xs.dts index 9ebb47b6bf2d..115cc47bb072 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a77960-salvator-xs.dts @@ -35,3 +35,7 @@ &du { clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1", "dclkin.2"; }; + +&gpu { + status = "okay"; +}; From 5de368c91cb58f9f984ecbcde5145431d1a5adcc Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 27 Oct 2025 22:12:20 +0100 Subject: [PATCH 274/665] arm64: dts: renesas: r8a77961-ulcb: Enable GPU support Enable GPU on M3ULCB with R-Car M3-W+. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251027211249.95826-4-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77961-ulcb.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77961-ulcb.dts b/arch/arm64/boot/dts/renesas/r8a77961-ulcb.dts index 70cf926667a6..0c0806cec698 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961-ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a77961-ulcb.dts @@ -40,3 +40,7 @@ &du { clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1", "dclkin.2"; }; + +&gpu { + status = "okay"; +}; From 96da5423288904f50c97e48e1d31a39d21c00ecb Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 27 Oct 2025 22:12:21 +0100 Subject: [PATCH 275/665] arm64: dts: renesas: r8a77961-salvator-xs: Enable GPU support Enable GPU on Salvator-X 2nd version with R-Car M3-W+. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251027211249.95826-5-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts index c7f14177f7b9..b35de49406a0 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts @@ -40,3 +40,7 @@ &du { clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1", "dclkin.2"; }; + +&gpu { + status = "okay"; +}; From a357a31c3436ee90a991f1111e7c1ae93ed84f75 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 26 Mar 2026 11:19:49 +0000 Subject: [PATCH 276/665] arm64: dts: renesas: r9a08g046: Add GBETH nodes Renesas RZ/G3L SoC is equipped with 2x Synopsys DesignWare Ethernet (10/100/1000 BASE) with TSN, IP block version 5.30. Add GBETH nodes to R9A08G046 RZ/G3L SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260326111953.31024-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 241 +++++++++++++++++++++ 1 file changed, 241 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi index 28b0c7558748..236a675231e5 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -171,6 +171,240 @@ sdhi1: mmc@11c10000 { /* placeholder */ }; + eth0: ethernet@11c30000 { + compatible = "renesas,r9a08g046-gbeth", "snps,dwmac-5.30a"; + reg = <0 0x11c30000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", + "rx-queue-0", "rx-queue-1", "rx-queue-2", + "rx-queue-3", "tx-queue-0", "tx-queue-1", + "tx-queue-2", "tx-queue-3", "ptp-pps-0", + "ptp-pps-1", "ptp-pps-2", "ptp-pps-3"; + clocks = <&cpg CPG_MOD R9A08G046_ETH0_CLK_AXI>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_CHI>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_PTP_REF_I>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_TX_I>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_RX_I>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_TX_180_I>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_RX_180_I>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_RMII_I>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_TX_I_RMII>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_RX_I_RMII>; + clock-names = "stmmaceth", "pclk", "ptp_ref", + "tx", "rx", "tx-180", "rx-180", + "rmii", "rmii_tx", "rmii_rx"; + resets = <&cpg R9A08G046_ETH0_ARESET_N>; + power-domains = <&cpg>; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + rx-fifo-depth = <8192>; + tx-fifo-depth = <8192>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup0>; + snps,mtl-tx-config = <&mtl_tx_setup0>; + snps,txpbl = <32>; + snps,rxpbl = <32>; + status = "disabled"; + + mdio0: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mtl_rx_setup0: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + }; + + mtl_tx_setup0: tx-queues-config { + snps,tx-queues-to-use = <4>; + snps,tx-sched-wrr; + + queue0 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,weight = <0x12>; + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,weight = <0x14>; + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,weight = <0x18>; + snps,dcb-algorithm; + snps,priority = <0x8>; + }; + }; + }; + + eth1: ethernet@11c40000 { + compatible = "renesas,r9a08g046-gbeth", "snps,dwmac-5.30a"; + reg = <0 0x11c40000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", + "rx-queue-0", "rx-queue-1", "rx-queue-2", + "rx-queue-3", "tx-queue-0", "tx-queue-1", + "tx-queue-2", "tx-queue-3", "ptp-pps-0", + "ptp-pps-1", "ptp-pps-2", "ptp-pps-3"; + clocks = <&cpg CPG_MOD R9A08G046_ETH1_CLK_AXI>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_CHI>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_PTP_REF_I>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_TX_I>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_RX_I>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_TX_180_I>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_RX_180_I>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_RMII_I>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_TX_I_RMII>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_RX_I_RMII>; + clock-names = "stmmaceth", "pclk", "ptp_ref", + "tx", "rx", "tx-180", "rx-180", + "rmii", "rmii_tx", "rmii_rx"; + resets = <&cpg R9A08G046_ETH1_ARESET_N>; + power-domains = <&cpg>; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + rx-fifo-depth = <8192>; + tx-fifo-depth = <8192>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup1>; + snps,mtl-tx-config = <&mtl_tx_setup1>; + snps,txpbl = <32>; + snps,rxpbl = <32>; + status = "disabled"; + + mdio1: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mtl_rx_setup1: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + }; + + mtl_tx_setup1: tx-queues-config { + snps,tx-queues-to-use = <4>; + snps,tx-sched-wrr; + + queue0 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,weight = <0x12>; + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,weight = <0x14>; + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,weight = <0x18>; + snps,dcb-algorithm; + snps,priority = <0x8>; + }; + }; + }; + pcie: pcie@11e40000 { reg = <0 0x11e40000 0 0x10000>; ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>; @@ -200,6 +434,13 @@ gic: interrupt-controller@12400000 { }; }; + stmmac_axi_setup: stmmac-axi-config { + snps,lpi_en; + snps,wr_osr_lmt = <0xf>; + snps,rd_osr_lmt = <0xf>; + snps,blen = <16 8 4 0 0 0 0>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , From ab47929332551a4b2a9d38f5e31e1d9ab6a99c1a Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 26 Mar 2026 11:19:50 +0000 Subject: [PATCH 277/665] arm64: dts: renesas: rzg3l-smarc-som: Enable eth0 (GBETH0) interface Enable the Gigabit Ethernet Interfaces (GBETH0) populated on the RZ/G3L SMARC EVK. The eth1, pincontrol definitions and hotplug support will be added later. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260326111953.31024-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/rzg3l-smarc-som.dtsi | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi index ab4950671c7c..fb781d9035aa 100644 --- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi @@ -8,6 +8,10 @@ / { compatible = "renesas,rzg3l-smarcm", "renesas,r9a08g046l48", "renesas,r9a08g046"; + aliases { + ethernet0 = ð0; + }; + memory@48000000 { device_type = "memory"; /* First 128MiB is reserved for secure area. */ @@ -15,6 +19,36 @@ memory@48000000 { }; }; +ð0 { + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + + status = "okay"; +}; + +ð0_rxc_rx_clk { + clock-frequency = <125000000>; +}; + &extal_clk { clock-frequency = <24000000>; }; + +&mdio0 { + phy0: ethernet-phy@7 { + compatible = "ethernet-phy-id0022.1640"; + reg = <7>; + rxc-skew-psec = <1400>; + txc-skew-psec = <1400>; + rxdv-skew-psec = <0>; + txen-skew-psec = <0>; + rxd0-skew-psec = <0>; + rxd1-skew-psec = <0>; + rxd2-skew-psec = <0>; + rxd3-skew-psec = <0>; + txd0-skew-psec = <0>; + txd1-skew-psec = <0>; + txd2-skew-psec = <0>; + txd3-skew-psec = <0>; + }; +}; From 1d4bed0d9cb25ea40852a782973b821af520f73a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 23 Apr 2026 01:36:29 +0200 Subject: [PATCH 278/665] ARM: dts: renesas: r8a7740: Add ZT/ZTR trace clocks Add ZT trace bus and ZTR trace clocks on R-Mobile A1. These clocks supply the coresight tracing modules, PTM, TPIU, ETB and replicator. Without these clock, coresight tracing can not be operated. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260422233744.149872-4-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/renesas/r8a7740.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/renesas/r8a7740.dtsi b/arch/arm/boot/dts/renesas/r8a7740.dtsi index d13ab86c3ab4..f7136db7a2ea 100644 --- a/arch/arm/boot/dts/renesas/r8a7740.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7740.dtsi @@ -553,7 +553,7 @@ cpg_clocks: cpg_clocks@e6150000 { "usb24s", "i", "zg", "b", "m1", "hp", "hpp", "usbp", "s", "zb", "m3", - "cp"; + "cp", "ztr", "zt"; }; /* Variable factor clocks (DIV6) */ From dfe6b60d5898730b2ea99e61564d17feedee25ad Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 23 Apr 2026 01:36:30 +0200 Subject: [PATCH 279/665] ARM: dts: renesas: r8a7740: Describe coresight Describe the coresight topology on R-Mobile A1. Extend the current PTM node with connection funnel, TPIU, ETB and replicator. Coresight on this hardware is clocked from the ZT/ZTR trace clocks. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260422233744.149872-5-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/renesas/r8a7740.dtsi | 114 ++++++++++++++++++++++++- 1 file changed, 111 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/renesas/r8a7740.dtsi b/arch/arm/boot/dts/renesas/r8a7740.dtsi index f7136db7a2ea..c7056b96ec0b 100644 --- a/arch/arm/boot/dts/renesas/r8a7740.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7740.dtsi @@ -18,7 +18,7 @@ / { cpus { #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0x0>; @@ -59,9 +59,117 @@ pmu { interrupts = ; }; - ptm { - compatible = "arm,coresight-etm3x"; + replicator { + compatible = "arm,coresight-static-replicator"; + clocks = <&cpg_clocks R8A7740_CLK_ZTR>; + clock-names = "atclk"; power-domains = <&pd_d4>; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + port@1 { + reg = <1>; + + replicator_out_port1: endpoint { + remote-endpoint = <&etb_in_port>; + }; + }; + }; + + in-ports { + /* replicator input port */ + port { + replicator_in_port0: endpoint { + remote-endpoint = <&funnel_out_port>; + }; + }; + }; + }; + + etb@e6fa1000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0xe6fa1000 0x1000>; + clocks = <&cpg_clocks R8A7740_CLK_ZT>, <&cpg_clocks R8A7740_CLK_ZTR>; + clock-names = "apb_pclk", "atclk"; + power-domains = <&pd_d4>; + + in-ports { + port { + etb_in_port: endpoint { + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + }; + + tpiu@e6fa3000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0xe6fa3000 0x1000>; + clocks = <&cpg_clocks R8A7740_CLK_ZT>, <&cpg_clocks R8A7740_CLK_ZTR>; + clock-names = "apb_pclk", "atclk"; + power-domains = <&pd_d4>; + + in-ports { + port { + tpiu_in_port: endpoint { + remote-endpoint = <&replicator_out_port0>; + }; + }; + }; + }; + + funnel { + compatible = "arm,coresight-static-funnel"; + + /* funnel output ports */ + out-ports { + port { + funnel_out_port: endpoint { + remote-endpoint = + <&replicator_in_port0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* funnel input ports */ + port@0 { + reg = <0>; + funnel0_in_port0: endpoint { + remote-endpoint = <&ptm0_out_port>; + }; + }; + }; + }; + + ptm@e6fbc000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0xe6fbc000 0x1000>; + clocks = <&cpg_clocks R8A7740_CLK_ZT>, <&cpg_clocks R8A7740_CLK_ZTR>; + clock-names = "apb_pclk", "atclk"; + cpu = <&cpu0>; + power-domains = <&pd_d4>; + + out-ports { + port { + ptm0_out_port: endpoint { + remote-endpoint = <&funnel0_in_port0>; + }; + }; + }; }; ceu0: ceu@fe910000 { From 998dd840cc7a54df214bc1a3751d5ad334e7dad1 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 17 Mar 2026 10:16:16 +0000 Subject: [PATCH 280/665] arm64: dts: renesas: Add pinctrl reset-names for RZ/G2L and RZ/V2H family SoCs Add reset-names properties to the pin control nodes for RZ/{G2L,G2UL,G3E,G3S} and RZ/{V2H,V2L,V2N} SoCs. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260317101627.174491-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 1 + 7 files changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 593c66b27ad1..ded4f1f11d60 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -604,6 +604,7 @@ pinctrl: pinctrl@11030000 { resets = <&cpg R9A07G043_GPIO_RSTN>, <&cpg R9A07G043_GPIO_PORT_RESETN>, <&cpg R9A07G043_GPIO_SPARE_RESETN>; + reset-names = "rstn", "port", "spare"; }; dmac: dma-controller@11820000 { diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 29273da81995..cb0c9550aa03 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -1017,6 +1017,7 @@ pinctrl: pinctrl@11030000 { resets = <&cpg R9A07G044_GPIO_RSTN>, <&cpg R9A07G044_GPIO_PORT_RESETN>, <&cpg R9A07G044_GPIO_SPARE_RESETN>; + reset-names = "rstn", "port", "spare"; }; irqc: interrupt-controller@110a0000 { diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 0dee48c4f1e4..7a3e5b6a685f 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -1025,6 +1025,7 @@ pinctrl: pinctrl@11030000 { resets = <&cpg R9A07G054_GPIO_RSTN>, <&cpg R9A07G054_GPIO_PORT_RESETN>, <&cpg R9A07G054_GPIO_SPARE_RESETN>; + reset-names = "rstn", "port", "spare"; }; irqc: interrupt-controller@110a0000 { diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 997e6cf0bb82..3a69bb246bab 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -533,6 +533,7 @@ pinctrl: pinctrl@11030000 { resets = <&cpg R9A08G045_GPIO_RSTN>, <&cpg R9A08G045_GPIO_PORT_RESETN>, <&cpg R9A08G045_GPIO_SPARE_RESETN>; + reset-names = "rstn", "port", "spare"; }; irqc: interrupt-controller@11050000 { diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 95a4e30a064d..4267b10937f3 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -265,6 +265,7 @@ pinctrl: pinctrl@10410000 { interrupt-parent = <&icu>; power-domains = <&cpg>; resets = <&cpg 0xa5>, <&cpg 0xa6>; + reset-names = "main", "error"; }; cpg: clock-controller@10420000 { diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index 7ccddd6a4a9a..dc5b116679c0 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -288,6 +288,7 @@ pinctrl: pinctrl@10410000 { gpio-ranges = <&pinctrl 0 0 96>; power-domains = <&cpg>; resets = <&cpg 0xa5>, <&cpg 0xa6>; + reset-names = "main", "error"; }; cpg: clock-controller@10420000 { diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 6f6fe5f36bef..1e94366bb7ee 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -270,6 +270,7 @@ pinctrl: pinctrl@10410000 { interrupt-parent = <&icu>; power-domains = <&cpg>; resets = <&cpg 0xa5>, <&cpg 0xa6>; + reset-names = "main", "error"; }; cpg: clock-controller@10420000 { From 60f8dfd33c1c7daade9846207be735c7f4fd802d Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 30 Apr 2026 13:53:05 +0100 Subject: [PATCH 281/665] arm64: dts: renesas: r9a08g046: Add OPP table Add OPP table for RZ/G3L SoC. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260430125342.439755-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi index 236a675231e5..e52498b3a745 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -14,6 +14,42 @@ / { #size-cells = <2>; interrupt-parent = <&gic>; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + + opp-37500000 { + opp-hz = /bits/ 64 <37500000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -24,6 +60,8 @@ cpu0: cpu@0 { device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A08G046_CLK_IC0>; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@100 { @@ -32,6 +70,8 @@ cpu1: cpu@100 { device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A08G046_CLK_IC1>; + operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@200 { @@ -40,6 +80,8 @@ cpu2: cpu@200 { device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A08G046_CLK_IC2>; + operating-points-v2 = <&cluster0_opp>; }; cpu3: cpu@300 { @@ -48,6 +90,8 @@ cpu3: cpu@300 { device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A08G046_CLK_IC3>; + operating-points-v2 = <&cluster0_opp>; }; L3_CA55: cache-controller-0 { From b3eea87822b799051745fff61b2e8d0313901ea1 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 30 Apr 2026 13:53:06 +0100 Subject: [PATCH 282/665] arm64: dts: renesas: r9a08g046: Add ICU node Add interrupt control node to RZ/G3L ("R9A08G046") SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260430125342.439755-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 90 ++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi index e52498b3a745..232a0e299df7 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -210,6 +210,96 @@ pinctrl: pinctrl@11030000 { /* placeholder */ }; + icu: interrupt-controller@11050000 { + compatible = "renesas,r9a08g046-irqc"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x11050000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "nmi", + "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "irq8", "irq9", "irq10", "irq11", + "irq12", "irq13", "irq14", "irq15", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "bus-err", "ec7tie1-0", "ec7tie2-0", "ec7tiovf-0", + "ovfunf0", "ovfunf1", "ovfunf2", "ovfunf3", + "ovfunf4", "ovfunf5", "ovfunf6", "ovfunf7"; + clocks = <&cpg CPG_MOD R9A08G046_IA55_CLK>, + <&cpg CPG_MOD R9A08G046_IA55_PCLK>; + clock-names = "clk", "pclk"; + power-domains = <&cpg>; + resets = <&cpg R9A08G046_IA55_RESETN>; + }; + sdhi1: mmc@11c10000 { reg = <0x0 0x11c10000 0 0x10000>; /* placeholder */ From ea82a68bb33691ea16188b6b9bef15cde874a193 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 30 Apr 2026 13:53:07 +0100 Subject: [PATCH 283/665] arm64: dts: renesas: r9a08g046: Add pincontrol node Add pincontrol node to RZ/G3L ("R9A08G046") SoC DTSI and set the icu as the interrupt-parent of the pin controller to route GPIO interrupts through the IA55 interrupt controller. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260430125342.439755-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi index 232a0e299df7..0cedf5a38291 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -204,10 +204,21 @@ sysc: system-controller@11020000 { }; pinctrl: pinctrl@11030000 { + compatible = "renesas,r9a08g046-pinctrl"; reg = <0 0x11030000 0 0x10000>; gpio-controller; #gpio-cells = <2>; - /* placeholder */ + gpio-ranges = <&pinctrl 0 0 232>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&icu>; + clocks = <&cpg CPG_MOD R9A08G046_GPIO_HCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A08G046_GPIO_RSTN>, + <&cpg R9A08G046_GPIO_PORT_RESETN>, + <&cpg R9A08G046_GPIO_SPARE_RESETN>; + reset-names = "rstn", "port", "spare"; + renesas,clonech = <&sysc 0xe2c>; }; icu: interrupt-controller@11050000 { From cdc8ef62ae6d04d2ba6a9226bc432168d06ad9a5 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 30 Apr 2026 13:53:08 +0100 Subject: [PATCH 284/665] arm64: dts: renesas: r9a08g046l48-smarc: Add SCIF0 pincontrol Add device node for SCIF0 pincontrol. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260430125342.439755-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts index 86db86335d5e..acead2b1c842 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts @@ -35,3 +35,15 @@ &keys { /delete-node/ key-2; /delete-node/ key-3; }; + +&pinctrl { + scif0_pins: scif0 { + pins = "SCIF0_TXD", "SCIF0_RXD"; + power-source = <1800>; + }; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; +}; From 72411a23c3942a2d5462f1695f0bceaf1c018bf7 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 30 Apr 2026 13:53:09 +0100 Subject: [PATCH 285/665] arm64: dts: renesas: rzg3l-smarc-som: Add pinctrl configuration for ETH0 Add pin control configuration for the ETH0 Ethernet interface on the RZ/G3L SMARC SoM board and also enable hotplug support. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260430125342.439755-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a08g046l48-smarc.dts | 1 + .../boot/dts/renesas/rzg3l-smarc-som.dtsi | 32 +++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts index acead2b1c842..0ae052238b3b 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts @@ -14,6 +14,7 @@ #include #include +#include #include "r9a08g046l48.dtsi" #include "rzg3l-smarc-som.dtsi" #include "renesas-smarc2.dtsi" diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi index fb781d9035aa..c7227a865fa4 100644 --- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi @@ -23,6 +23,8 @@ ð0 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; + pinctrl-0 = <ð0_pins>; + pinctrl-names = "default"; status = "okay"; }; @@ -38,6 +40,7 @@ &mdio0 { phy0: ethernet-phy@7 { compatible = "ethernet-phy-id0022.1640"; reg = <7>; + interrupts-extended = <&icu 3 IRQ_TYPE_LEVEL_LOW>; rxc-skew-psec = <1400>; txc-skew-psec = <1400>; rxdv-skew-psec = <0>; @@ -52,3 +55,32 @@ phy0: ethernet-phy@7 { txd3-skew-psec = <0>; }; }; + +&pinctrl { + eth0_pins: eth0 { + txc { + pinmux = ; /* ETH0_TXC_REF_CLK */ + power-source = <1800>; + output-enable; + drive-strength-microamp = <5200>; + }; + + ctrl { + pinmux = , /* MDIO */ + , /* MDC */ + , /* RX_CTL */ + , /* TX_CTL */ + , /* RXC */ + , /* TXD0 */ + , /* TXD1 */ + , /* TXD2 */ + , /* TXD3 */ + , /* RXD0 */ + , /* RXD1 */ + , /* RXD2 */ + , /* RXD3 */ + ; /* PHY_INTR */ + power-source = <1800>; + }; + }; +}; From 8a59e4f535a876fe94034f3a1e44b371d1fe363f Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 30 Apr 2026 13:53:10 +0100 Subject: [PATCH 286/665] arm64: dts: renesas: rzg3l-smarc-som: Enable eth1 (GBETH1) interface Enable the Gigabit Ethernet Interface (GBETH1) populated on the RZ/G3L SMARC EVK. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260430125342.439755-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/rzg3l-smarc-som.dtsi | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi index c7227a865fa4..f53e6332e2f4 100644 --- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi @@ -10,6 +10,7 @@ / { aliases { ethernet0 = ð0; + ethernet1 = ð1; }; memory@48000000 { @@ -32,6 +33,19 @@ ð0_rxc_rx_clk { clock-frequency = <125000000>; }; +ð1 { + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + + pinctrl-0 = <ð1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +ð1_rxc_rx_clk { + clock-frequency = <125000000>; +}; + &extal_clk { clock-frequency = <24000000>; }; @@ -56,6 +70,26 @@ phy0: ethernet-phy@7 { }; }; +&mdio1 { + phy1: ethernet-phy@7 { + compatible = "ethernet-phy-id0022.1640"; + reg = <7>; + interrupts-extended = <&icu 16 IRQ_TYPE_LEVEL_LOW>; + rxc-skew-psec = <1400>; + txc-skew-psec = <1400>; + rxdv-skew-psec = <0>; + txen-skew-psec = <0>; + rxd0-skew-psec = <0>; + rxd1-skew-psec = <0>; + rxd2-skew-psec = <0>; + rxd3-skew-psec = <0>; + txd0-skew-psec = <0>; + txd1-skew-psec = <0>; + txd2-skew-psec = <0>; + txd3-skew-psec = <0>; + }; +}; + &pinctrl { eth0_pins: eth0 { txc { @@ -83,4 +117,31 @@ ctrl { power-source = <1800>; }; }; + + eth1_pins: eth1 { + txc { + pinmux = ; /* ETH1_TXC_REF_CLK */ + power-source = <1800>; + output-enable; + drive-strength-microamp = <5200>; + }; + + ctrl { + pinmux = , /* MDIO */ + , /* MDC */ + , /* RX_CTL */ + , /* TX_CTL */ + , /* RXC */ + , /* TXD0 */ + , /* TXD1 */ + , /* TXD2 */ + , /* TXD3 */ + , /* RXD0 */ + , /* RXD1 */ + , /* RXD2 */ + , /* RXD3 */ + ; /* PHY_INTR */ + power-source = <1800>; + }; + }; }; From 7f951abdd4274fedf1b011ff5e7d97fcdab20f03 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 5 May 2026 00:54:11 +0200 Subject: [PATCH 287/665] arm64: dts: renesas: gray-hawk-single: Fix AVB0 PHY node alignment Trivially fix PHY node alignment. No functional change. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260504225428.114959-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/gray-hawk-single.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/gray-hawk-single.dtsi b/arch/arm64/boot/dts/renesas/gray-hawk-single.dtsi index 2edb5cb3407b..792a4aa8f4a9 100644 --- a/arch/arm64/boot/dts/renesas/gray-hawk-single.dtsi +++ b/arch/arm64/boot/dts/renesas/gray-hawk-single.dtsi @@ -208,11 +208,11 @@ mdio { avb0_phy: ethernet-phy@0 { compatible = "ethernet-phy-id0022.1622", - "ethernet-phy-ieee802.3-c22"; - rxc-skew-ps = <1500>; - reg = <0>; - interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; + "ethernet-phy-ieee802.3-c22"; + rxc-skew-ps = <1500>; + reg = <0>; + interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; }; }; }; From 3065cc03532fc218d290f5812b24408425ad8a28 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 5 May 2026 00:54:42 +0200 Subject: [PATCH 288/665] arm64: dts: renesas: ebisu: Sort sound node Sort /sound {} node in the correct order alphabetically. No functional change. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260504225515.114986-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/ebisu.dtsi | 34 +++++++++++++------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/ebisu.dtsi b/arch/arm64/boot/dts/renesas/ebisu.dtsi index aaedb1fb51ae..ba564aa09866 100644 --- a/arch/arm64/boot/dts/renesas/ebisu.dtsi +++ b/arch/arm64/boot/dts/renesas/ebisu.dtsi @@ -186,23 +186,6 @@ reg_12p0v: regulator-12p0v { regulator-always-on; }; - rsnd_ak4613: sound { - compatible = "simple-audio-card"; - - simple-audio-card,name = "rsnd-ak4613"; - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&sndcpu>; - simple-audio-card,frame-master = <&sndcpu>; - - sndcodec: simple-audio-card,codec { - sound-dai = <&ak4613>; - }; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - }; - vbus0_usb2: regulator-vbus0-usb2 { compatible = "regulator-fixed"; @@ -260,6 +243,23 @@ vccq_sdhi1: regulator-vccq-sdhi1 { states = <3300000 1>, <1800000 0>; }; + rsnd_ak4613: sound { + compatible = "simple-audio-card"; + + simple-audio-card,name = "rsnd-ak4613"; + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&sndcpu>; + simple-audio-card,frame-master = <&sndcpu>; + + sndcodec: simple-audio-card,codec { + sound-dai = <&ak4613>; + }; + + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + }; + vga { compatible = "vga-connector"; From 89b67a16a59b66b0dfb26307c5858e9cddcbb242 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 5 May 2026 00:54:43 +0200 Subject: [PATCH 289/665] arm64: dts: renesas: salvator-common: Sort sound node Sort /sound {} node in the correct order alphabetically. No functional change. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260504225515.114986-2-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/salvator-common.dtsi | 26 +++++++++---------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index e505161caa67..0b29bf9564eb 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -211,19 +211,6 @@ reg_12v: regulator-12v { regulator-always-on; }; - sound_card: sound { - compatible = "audio-graph-card"; - - label = "rcar-sound"; - - dais = <&rsnd_port0 /* ak4613 */ - &rsnd_port1 /* HDMI0 */ -#ifdef SOC_HAS_HDMI1 - &rsnd_port2 /* HDMI1 */ -#endif - >; - }; - vbus0_usb2: regulator-vbus0-usb2 { compatible = "regulator-fixed"; @@ -281,6 +268,19 @@ vccq_sdhi3: regulator-vccq-sdhi3 { states = <3300000 1>, <1800000 0>; }; + sound_card: sound { + compatible = "audio-graph-card"; + + label = "rcar-sound"; + + dais = <&rsnd_port0 /* ak4613 */ + &rsnd_port1 /* HDMI0 */ +#ifdef SOC_HAS_HDMI1 + &rsnd_port2 /* HDMI1 */ +#endif + >; + }; + vga { compatible = "vga-connector"; From 8e46bc6370d08a21cc43bb747aef8ffae45df7d7 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 5 May 2026 13:59:16 +0100 Subject: [PATCH 290/665] arm64: dts: renesas: r9a08g046: Add wdt device node The RZ/G3L SOC has 3 watchdog timer channels: - channel0 (wdt0) for Cortex-A55-CPU Non-Secure, - channel1 (wdt1) for Cortex-A55 CPU Secure, - channel2 (wdt2) for Cortex-M33 CPU. Add wdt0 node to RZ/G3L ("R9A08G046") SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260505125921.149682-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi index 0cedf5a38291..02a3029c058e 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -577,6 +577,20 @@ gic: interrupt-controller@12400000 { interrupt-controller; interrupts = ; }; + + wdt0: watchdog@12800800 { + compatible = "renesas,r9a08g046-wdt", "renesas,rzg2l-wdt"; + reg = <0 0x12800800 0 0x400>; + clocks = <&cpg CPG_MOD R9A08G046_WDT0_PCLK>, + <&cpg CPG_MOD R9A08G046_WDT0_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = , + ; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A08G046_WDT0_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; + }; }; stmmac_axi_setup: stmmac-axi-config { From 5a5dcb6a52feeef07bc6ad4e32f8276b1093b8f6 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 5 May 2026 13:59:17 +0100 Subject: [PATCH 291/665] arm64: dts: renesas: rzg3l-smarc-som: Enable watchdog Enable watchdog timer channel0 on RZ/G3L SoM DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260505125921.149682-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi index f53e6332e2f4..b28e59a65259 100644 --- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi @@ -145,3 +145,8 @@ ctrl { }; }; }; + +&wdt0 { + timeout-sec = <60>; + status = "okay"; +}; From 4a1779f42e21962381a9696d182a2620c830ff10 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Mon, 11 May 2026 15:45:43 +0530 Subject: [PATCH 292/665] arm64: dts: qcom: sm8750: Add camera clock controller The camera clock controller is split into cambistmclk and camcc. The cambist clock controller handles the mclks and the rest of the clocks of camera are part of the camcc clock controller. Add the camcc clock controller device node for SM8750 SoC. Reviewed-by: Abel Vesa Signed-off-by: Taniya Das Link: https://lore.kernel.org/r/20260511-sm8750_camcc_dt-v4-1-eab4b6c3eaea@oss.qualcomm.com [bjorn: Fixed include file order] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 36 ++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 5921f83aafac..49d4a9a34c04 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -5,6 +5,8 @@ #include #include +#include +#include #include #include #include @@ -2082,6 +2084,23 @@ aggre2_noc: interconnect@1700000 { clocks = <&rpmhcc RPMH_IPA_CLK>; }; + cambistmclkcc: clock-controller@1760000 { + compatible = "qcom,sm8750-cambistmclkcc"; + reg = <0x0 0x1760000 0x0 0x6000>; + clocks = <&gcc GCC_CAM_BIST_MCLK_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MX>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mmss_noc: interconnect@1780000 { compatible = "qcom,sm8750-mmss-noc"; reg = <0x0 0x01780000 0x0 0x5b800>; @@ -3444,6 +3463,23 @@ dispcc: clock-controller@af00000 { #power-domain-cells = <1>; }; + camcc: clock-controller@ade0000 { + compatible = "qcom,sm8750-camcc"; + reg = <0x0 0xade0000 0x0 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8750-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; From 9c633eec37782b2d31281a0289882bb419b5ad18 Mon Sep 17 00:00:00 2001 From: Wojciech Slenska Date: Tue, 10 Mar 2026 12:22:31 +0100 Subject: [PATCH 293/665] arm64: dts: qcom: agatti: Add IPA nodes Added IPA nodes and definitions. Signed-off-by: Wojciech Slenska Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260310112309.79261-3-wojciech.slenska@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/agatti.dtsi | 53 ++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/agatti.dtsi b/arch/arm64/boot/dts/qcom/agatti.dtsi index fd40aa59878a..f0b6ae9b8152 100644 --- a/arch/arm64/boot/dts/qcom/agatti.dtsi +++ b/arch/arm64/boot/dts/qcom/agatti.dtsi @@ -433,6 +433,18 @@ wlan_smp2p_in: wlan-wpss-to-ap { interrupt-controller; #interrupt-cells = <2>; }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; soc: soc@0 { @@ -1641,6 +1653,47 @@ usb_dwc3_ss: endpoint { }; }; + ipa: ipa@5840000 { + compatible = "qcom,qcm2290-ipa", "qcom,sc7180-ipa"; + + iommus = <&apps_smmu 0x140 0x0>; + reg = <0x0 0x05840000 0x0 0x7000>, + <0x0 0x05847000 0x0 0x2000>, + <0x0 0x05804000 0x0 0x2c000>; + reg-names = "ipa-reg", + "ipa-shared", + "gsi"; + + interrupts-extended = <&intc GIC_SPI 257 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, + <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ipa", + "gsi", + "ipa-clock-query", + "ipa-setup-ready"; + + clocks = <&rpmcc RPM_SMD_IPA_CLK>; + clock-names = "core"; + + interconnects = <&system_noc MASTER_IPA RPM_ALWAYS_TAG + &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, + <&system_noc MASTER_IPA RPM_ALWAYS_TAG + &system_noc SLAVE_IMEM RPM_ALWAYS_TAG>, + <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG + &config_noc SLAVE_IPA_CFG RPM_ACTIVE_TAG>; + interconnect-names = "memory", + "imem", + "config"; + + qcom,smem-states = <&ipa_smp2p_out 0>, + <&ipa_smp2p_out 1>; + qcom,smem-state-names = "ipa-clock-enabled-valid", + "ipa-clock-enabled"; + + status = "disabled"; + }; + gpu: gpu@5900000 { compatible = "qcom,adreno-07000200", "qcom,adreno"; reg = <0x0 0x05900000 0x0 0x40000>, From 3f5dcc05cd33e85e897571b4e44feb06f5399b68 Mon Sep 17 00:00:00 2001 From: Aaron Kling Date: Mon, 30 Mar 2026 16:50:20 -0500 Subject: [PATCH 294/665] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths Add the OPP tables for each CPU clusters (cpu0-1-2, cpu3-4-5-6 & cpu7) to permit scaling the Last Level Cache Controller (LLCC), DDR and L3 cache frequency by aggregating bandwidth requests of all CPU core with referenc to the current OPP they are configured in by the LMH/EPSS hardware. The effect is a proper caches & DDR frequency scaling when CPU cores changes frequency. The OPP tables were built using the downstream memlat ddr, llcc & l3 tables for each cluster types with the actual EPSS cpufreq LUT tables from running a QCS8550 device. Also add the OSC L3 Cache controller node. Also add the interconnect entry for each cpu, with 3 different paths: - CPU to Last Level Cache Controller (LLCC) - Last Level Cache Controller (LLCC) to DDR - L3 Cache from CPU to DDR interface Tested-by: Neil Armstrong # on SM8550-HDK Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Aaron Kling Link: https://lore.kernel.org/r/20260330-sm8550-ddr-bw-scaling-v4-1-5020c06983a0@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 367 +++++++++++++++++++++++++++ 1 file changed, 367 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 912525e9bca6..b7a7c49db077 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -78,6 +79,13 @@ cpu0: cpu@0 { qcom,freq-domain = <&cpufreq_hw 0>; capacity-dmips-mhz = <326>; dynamic-power-coefficient = <251>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; l2_0: l2-cache { compatible = "cache"; @@ -104,6 +112,13 @@ cpu1: cpu@100 { qcom,freq-domain = <&cpufreq_hw 0>; capacity-dmips-mhz = <326>; dynamic-power-coefficient = <251>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; l2_100: l2-cache { compatible = "cache"; @@ -125,6 +140,13 @@ cpu2: cpu@200 { qcom,freq-domain = <&cpufreq_hw 0>; capacity-dmips-mhz = <326>; dynamic-power-coefficient = <251>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; l2_200: l2-cache { compatible = "cache"; @@ -146,6 +168,13 @@ cpu3: cpu@300 { qcom,freq-domain = <&cpufreq_hw 1>; capacity-dmips-mhz = <693>; dynamic-power-coefficient = <447>; + operating-points-v2 = <&cpu3_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; l2_300: l2-cache { compatible = "cache"; @@ -167,6 +196,13 @@ cpu4: cpu@400 { qcom,freq-domain = <&cpufreq_hw 1>; capacity-dmips-mhz = <693>; dynamic-power-coefficient = <447>; + operating-points-v2 = <&cpu3_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; l2_400: l2-cache { compatible = "cache"; @@ -188,6 +224,13 @@ cpu5: cpu@500 { qcom,freq-domain = <&cpufreq_hw 1>; capacity-dmips-mhz = <693>; dynamic-power-coefficient = <447>; + operating-points-v2 = <&cpu3_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; l2_500: l2-cache { compatible = "cache"; @@ -209,6 +252,13 @@ cpu6: cpu@600 { qcom,freq-domain = <&cpufreq_hw 1>; capacity-dmips-mhz = <693>; dynamic-power-coefficient = <447>; + operating-points-v2 = <&cpu3_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; l2_600: l2-cache { compatible = "cache"; @@ -230,6 +280,13 @@ cpu7: cpu@700 { qcom,freq-domain = <&cpufreq_hw 2>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <1057>; + operating-points-v2 = <&cpu7_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; l2_700: l2-cache { compatible = "cache"; @@ -397,6 +454,306 @@ memory@a0000000 { reg = <0 0xa0000000 0 0>; }; + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-307200000 { + opp-hz = /bits/ 64 <307200000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-441600000 { + opp-hz = /bits/ 64 <441600000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (384000 * 32)>; + }; + + opp-556800000 { + opp-hz = /bits/ 64 <556800000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-672000000 { + opp-hz = /bits/ 64 <672000000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-787200000 { + opp-hz = /bits/ 64 <787200000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (729600 * 32)>; + }; + + opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (844800 * 32)>; + }; + + opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (940800 * 32)>; + }; + + opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1056000 * 32)>; + }; + + opp-1228800000 { + opp-hz = /bits/ 64 <1228800000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1152000 * 32)>; + }; + + opp-1344000000 { + opp-hz = /bits/ 64 <1344000000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1267200 * 32)>; + }; + + opp-1459200000 { + opp-hz = /bits/ 64 <1459200000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1267200 * 32)>; + }; + + opp-1555200000 { + opp-hz = /bits/ 64 <1555200000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>; + }; + + opp-1670400000 { + opp-hz = /bits/ 64 <1670400000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>; + }; + + opp-1785600000 { + opp-hz = /bits/ 64 <1785600000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>; + }; + + opp-1900800000 { + opp-hz = /bits/ 64 <1900800000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1689600 * 32)>; + }; + + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1804800 * 32)>; + }; + }; + + cpu3_opp_table: opp-table-cpu3 { + compatible = "operating-points-v2"; + opp-shared; + + opp-499200000 { + opp-hz = /bits/ 64 <499200000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-614400000 { + opp-hz = /bits/ 64 <614400000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-729600000 { + opp-hz = /bits/ 64 <729600000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-844800000 { + opp-hz = /bits/ 64 <844800000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>; + }; + + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>; + }; + + opp-1171200000 { + opp-hz = /bits/ 64 <1171200000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>; + }; + + opp-1286400000 { + opp-hz = /bits/ 64 <1286400000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>; + }; + + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>; + }; + + opp-1536000000 { + opp-hz = /bits/ 64 <1536000000>; + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>; + }; + + opp-1651200000 { + opp-hz = /bits/ 64 <1651200000>; + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>; + }; + + opp-1785600000 { + opp-hz = /bits/ 64 <1785600000>; + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>; + }; + + opp-1920000000 { + opp-hz = /bits/ 64 <1920000000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1267200 * 32)>; + }; + + opp-2054400000 { + opp-hz = /bits/ 64 <2054400000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2188800000 { + opp-hz = /bits/ 64 <2188800000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2323200000 { + opp-hz = /bits/ 64 <2323200000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2457600000 { + opp-hz = /bits/ 64 <2457600000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2592000000 { + opp-hz = /bits/ 64 <2592000000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2707200000 { + opp-hz = /bits/ 64 <2707200000>; + opp-peak-kBps = <(933000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2803200000 { + opp-hz = /bits/ 64 <2803200000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>; + }; + }; + + cpu7_opp_table: opp-table-cpu7 { + compatible = "operating-points-v2"; + opp-shared; + + opp-595200000 { + opp-hz = /bits/ 64 <595200000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-729600000 { + opp-hz = /bits/ 64 <729600000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-864000000 { + opp-hz = /bits/ 64 <864000000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-998400000 { + opp-hz = /bits/ 64 <998400000>; + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>; + }; + + opp-1132800000 { + opp-hz = /bits/ 64 <1132800000>; + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>; + }; + + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>; + }; + + opp-1363200000 { + opp-hz = /bits/ 64 <1363200000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>; + }; + + opp-1478400000 { + opp-hz = /bits/ 64 <1478400000>; + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>; + }; + + opp-1593600000 { + opp-hz = /bits/ 64 <1593600000>; + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>; + }; + + opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>; + }; + + opp-1843200000 { + opp-hz = /bits/ 64 <1843200000>; + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>; + }; + + opp-1977600000 { + opp-hz = /bits/ 64 <1977600000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1267200 * 32)>; + }; + + opp-2092800000 { + opp-hz = /bits/ 64 <2092800000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2227200000 { + opp-hz = /bits/ 64 <2227200000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2342400000 { + opp-hz = /bits/ 64 <2342400000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2476800000 { + opp-hz = /bits/ 64 <2476800000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2592000000 { + opp-hz = /bits/ 64 <2592000000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2726400000 { + opp-hz = /bits/ 64 <2726400000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1478400 * 32)>; + }; + + opp-2841600000 { + opp-hz = /bits/ 64 <2841600000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>; + }; + + opp-2956800000 { + opp-hz = /bits/ 64 <2956800000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>; + }; + + opp-3187200000 { + opp-hz = /bits/ 64 <3187200000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>; + }; + }; + pmu-a510 { compatible = "arm,cortex-a510-pmu"; interrupts = ; @@ -5482,6 +5839,16 @@ rpmhpd_opp_turbo_l1: opp-416 { }; }; + epss_l3: interconnect@17d90000 { + compatible = "qcom,sm8550-epss-l3", "qcom,epss-l3"; + reg = <0 0x17d90000 0 0x1000>; + + clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@17d91000 { compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss"; reg = <0 0x17d91000 0 0x1000>, From f4d7c5875a215cd3989b59d13a9c30cec9f0a33b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 31 Mar 2026 18:56:46 +0200 Subject: [PATCH 295/665] arm64: dts: qcom: sm8750: Fix DSI1 phy reference clock rate The DSI PHY CXO clock input is the SoC CXO divided by two. DSI0 already uses correct one, but DSI1 got copy-paste from SM8650. Wrong clock parent will cause incorrect DSI1 PHY PLL frequencies to be used making the DSI panel non-working, although there is no upstream user of DSI1. Fixes: 818ae2b389bc ("arm64: dts: qcom: sm8750: Add display (MDSS) with Display CC") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260331165645.233965-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 49d4a9a34c04..70830cb49e73 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -3340,7 +3340,7 @@ mdss_dsi1_phy: phy@ae97000 { "dsi_pll"; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>; + <&bi_tcxo_div2>; clock-names = "iface", "ref"; From fa9c7403af64d3e56a6c20dedc60e0a55b527509 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Thu, 2 Apr 2026 00:05:09 +0530 Subject: [PATCH 296/665] arm64: dts: qcom: kodiak: Fix ICE reg size The ICE register region on Kodiak is currently defined as 0x8000 bytes. According to the hardware specification, the correct register size is 0x18000. Update the ICE node reg property to match the hardware. Fixes: dfd5ee7b34bb ("arm64: dts: qcom: sc7280: Add inline crypto engine") Signed-off-by: Kuldeep Singh Reviewed-by: Harshal Dev Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260402-ice_dt_reg_fix-v1-1-74e4c2129238@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index 2dbeb15c84b7..c51beada8c7d 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -2578,7 +2578,7 @@ ufs_mem_phy: phy@1d87000 { ice: crypto@1d88000 { compatible = "qcom,sc7280-inline-crypto-engine", "qcom,inline-crypto-engine"; - reg = <0 0x01d88000 0 0x8000>; + reg = <0 0x01d88000 0 0x18000>; clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; From 7fb3d0512dacc0d09217eb45057357f00298203d Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Thu, 2 Apr 2026 00:05:10 +0530 Subject: [PATCH 297/665] arm64: dts: qcom: sm8450: Fix ICE reg size The ICE register region size was originally described incorrectly when the ICE hardware was first introduced. The same value was later carried over unchanged when the ICE node was split out from the UFS node into its own DT entry. Correct the register size to match the hardware specification. Fixes: 276ee34a40c1 ("arm64: dts: qcom: sm8450: add Inline Crypto Engine registers and clock") Signed-off-by: Kuldeep Singh Reviewed-by: Harshal Dev Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260402-ice_dt_reg_fix-v1-2-74e4c2129238@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 03bf30b53f28..e0c37ce3042a 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -5373,7 +5373,7 @@ ufs_mem_phy: phy@1d87000 { ice: crypto@1d88000 { compatible = "qcom,sm8450-inline-crypto-engine", "qcom,inline-crypto-engine"; - reg = <0 0x01d88000 0 0x8000>; + reg = <0 0x01d88000 0 0x18000>; clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; From c4b423835ee7529854ab39b50cf766bc4c6b4d66 Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Tue, 31 Mar 2026 16:06:58 -0400 Subject: [PATCH 298/665] arm64: dts: qcom: sdm670: add lpi pinctrl The Snapdragon 670 has a separate TLMM for audio pins. Add the device node for it. Also add reserved GPIOs for the Pixel 3a, which blocks access to the sensor GPIOs. Signed-off-by: Richard Acayan Reviewed-by: Konrad Dybcio Acked-by: Linus Walleij Link: https://lore.kernel.org/r/20260331200658.1306-5-mailingradian@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 73 ++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index e13ced9479b7..30844b150c80 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -2300,5 +2300,78 @@ cpufreq_hw: cpufreq@17d43000 { #freq-domain-cells = <1>; }; + + lpi_tlmm: pinctrl@62b40000 { + compatible = "qcom,sdm670-lpass-lpi-pinctrl"; + reg = <0 0x62b40000 0 0x20000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpi_tlmm 0 0 32>; + + cdc_pdm_default: cdc-pdm-default-state { + clk-pins { + pins = "gpio18"; + function = "slimbus_clk"; + drive-strength = <4>; + output-low; + }; + + sync-pins { + pins = "gpio19"; + function = "pdm_sync"; + drive-strength = <4>; + output-low; + }; + + tx-pins { + pins = "gpio20"; + function = "pdm_tx"; + drive-strength = <8>; + }; + + rx-pins { + pins = "gpio21", "gpio23", "gpio25"; + function = "pdm_rx"; + drive-strength = <4>; + output-low; + }; + }; + + cdc_comp_default: cdc-comp-default-state { + pins = "gpio22", "gpio24"; + function = "comp_rx"; + drive-strength = <4>; + }; + + cdc_dmic_default: cdc-dmic-default-state { + clk1-pins { + pins = "gpio26"; + function = "dmic1_clk"; + drive-strength = <8>; + output-high; + }; + + clk2-pins { + pins = "gpio28"; + function = "dmic2_clk"; + drive-strength = <8>; + output-high; + }; + + data1-pins { + pins = "gpio27"; + function = "dmic1_data"; + drive-strength = <8>; + input-enable; + }; + + data2-pins { + pins = "gpio29"; + function = "dmic2_data"; + drive-strength = <8>; + input-enable; + }; + }; + }; }; }; From d3bd58f3060f28ecd30df51925a9b1f62e5e8c9b Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Mon, 30 Mar 2026 22:15:21 +0000 Subject: [PATCH 299/665] riscv: dts: spacemit: k3: Add USB2.0 support There is one USB2.0 host in K3 SoC which use DWC3 IP but only provide USB2.0 functionality, and with only one USB2 PHY connected. The USB2.0 controller on Pico-ITX board connects to a Terminus FE1.1 Hub which fully USB2.0 protocol compliant and provides 4 ports. Link: https://patch.msgid.link/20260330-02-k3-usb20-dts-v2-1-46af262fb4a9@kernel.org Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 24 +++++++++++++++ arch/riscv/boot/dts/spacemit/k3.dtsi | 31 ++++++++++++++++++++ 2 files changed, 55 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts index 4486dc1fe114..b89c1521e664 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -26,6 +26,14 @@ memory@100000000 { reg = <0x1 0x00000000 0x4 0x00000000>; }; + reg_aux_vcc3v3: regulator-aux-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "AUX_VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + reg_aux_vcc5v: regulator-aux-vcc5v { compatible = "regulator-fixed"; regulator-name = "AUX_VCC5V"; @@ -197,3 +205,19 @@ &uart0 { pinctrl-0 = <&uart0_0_cfg>; status = "okay"; }; + +&usb2_host { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + hub@1 { + compatible = "usb1a40,0101"; + reg = <1>; + vdd-supply = <®_aux_vcc3v3>; + }; +}; + +&usb2_phy { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index e6faf8d8759e..23cca70f796b 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -438,6 +438,37 @@ soc: soc { dma-noncoherent; ranges; + usb2_host: usb@c0a00000 { + compatible = "spacemit,k3-dwc3"; + reg = <0x0 0xc0a00000 0x0 0x10000>; + clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; + clock-names = "usbdrd30"; + resets = <&syscon_apmu RESET_APMU_USB2_AHB>, + <&syscon_apmu RESET_APMU_USB2_VCC>, + <&syscon_apmu RESET_APMU_USB2_PHY>; + reset-names = "ahb", "vcc", "phy"; + interrupts = <105 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&saplic>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + phy_type = "utmi"; + snps,dis_enblslpm_quirk; + snps,dis_u2_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + dr_mode = "host"; + maximum-speed = "high-speed"; + status = "disabled"; + }; + + usb2_phy: phy@c0a20000 { + compatible = "spacemit,k3-usb2-phy"; + reg = <0x0 0xc0a20000 0x0 0x200>; + clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; + #phy-cells = <0>; + status = "disabled"; + }; + eth0: ethernet@cac80000 { compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; reg = <0x0 0xcac80000 0x0 0x2000>; From 2a2a7b9701a7972dc663d233c65f423088dd316b Mon Sep 17 00:00:00 2001 From: Ronald Claveau Date: Thu, 26 Mar 2026 10:59:15 +0100 Subject: [PATCH 300/665] arm64: dts: amlogic: t7: Add PWM pinctrl nodes These pinctrl nodes are required by the PWM drivers to configure pin muxing at runtime. Reviewed-by: Neil Armstrong Signed-off-by: Ronald Claveau Link: https://patch.msgid.link/20260326-add-emmc-t7-vim4-v5-4-d3f182b48e9d@aliel.fr Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 144 ++++++++++++++++++++ 1 file changed, 144 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi index 4a2220e59743..a54fa2bd5c78 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi @@ -309,6 +309,150 @@ mux { }; }; + pwm_a_pins: pwm-a { + mux { + groups = "pwm_a"; + function = "pwm_a"; + bias-disable; + }; + }; + + pwm_ao_a_pins: pwm-ao-a { + mux { + groups = "pwm_ao_a"; + function = "pwm_ao_a"; + bias-disable; + }; + }; + + pwm_ao_b_pins: pwm-ao-b { + mux { + groups = "pwm_ao_b"; + function = "pwm_ao_b"; + bias-disable; + }; + }; + + pwm_ao_c_d_pins: pwm-ao-c-d { + mux { + groups = "pwm_ao_c_d"; + function = "pwm_ao_c"; + bias-disable; + }; + }; + + pwm_ao_c_e_pins: pwm-ao-c-e { + mux { + groups = "pwm_ao_c_e"; + function = "pwm_ao_c"; + bias-disable; + }; + }; + + pwm_ao_c_hiz_pins: pwm-ao-c-hiz { + mux { + groups = "pwm_ao_c_hiz"; + function = "pwm_ao_c_hiz"; + bias-disable; + }; + }; + + pwm_ao_d_pins: pwm-ao-d { + mux { + groups = "pwm_ao_d"; + function = "pwm_ao_d"; + bias-disable; + }; + }; + + pwm_ao_e_pins: pwm-ao-e { + mux { + groups = "pwm_ao_e"; + function = "pwm_ao_e"; + bias-disable; + }; + }; + + pwm_ao_f_pins: pwm-ao-f { + mux { + groups = "pwm_ao_f"; + function = "pwm_ao_f"; + bias-disable; + }; + }; + + pwm_ao_g_pins: pwm-ao-g { + mux { + groups = "pwm_ao_g"; + function = "pwm_ao_g"; + bias-disable; + }; + }; + + pwm_ao_g_hiz_pins: pwm-ao-g-hiz { + mux { + groups = "pwm_ao_g_hiz"; + function = "pwm_ao_g_hiz"; + bias-disable; + }; + }; + + pwm_ao_h_pins: pwm-ao-h { + mux { + groups = "pwm_ao_h"; + function = "pwm_ao_h"; + bias-disable; + }; + }; + + pwm_b_pins: pwm-b { + mux { + groups = "pwm_b"; + function = "pwm_b"; + bias-disable; + }; + }; + + pwm_c_pins: pwm-c { + mux { + groups = "pwm_c"; + function = "pwm_c"; + bias-disable; + }; + }; + + pwm_d_pins: pwm-d { + mux { + groups = "pwm_d"; + function = "pwm_d"; + bias-disable; + }; + }; + + pwm_e_pins: pwm-e { + mux { + groups = "pwm_e"; + function = "pwm_e"; + bias-disable; + }; + }; + + pwm_f_pins: pwm-f { + mux { + groups = "pwm_f"; + function = "pwm_f"; + bias-disable; + }; + }; + + pwm_vs_pins: pwm-vs { + mux { + groups = "pwm_vs"; + function = "pwm_vs"; + bias-disable; + }; + }; + sdcard_pins: sdcard { mux { groups = "sdcard_d0", From 69442723f38a338962bee877243e7c1ff86039b8 Mon Sep 17 00:00:00 2001 From: Harrison Vanderbyl Date: Tue, 12 May 2026 00:40:50 +1000 Subject: [PATCH 301/665] dt-bindings: arm: qcom: Add Microsoft Surface Pro 12in Document the compatible string for the Microsoft Surface Pro 12-inch, 1st Edition with Snapdragon, based on the Qualcomm X1P42100 SoC. Signed-off-by: Harrison Vanderbyl Link: https://lore.kernel.org/r/627a1e2506fbed99e971250dbba64902af54232c.1778498477.git.harrison.vanderbyl@gmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index af266d584fae..50cc18a6ec5e 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1181,6 +1181,10 @@ properties: - const: microsoft,denali - const: qcom,x1e80100 + - items: + - const: microsoft,surface-pro-12in + - const: qcom,x1p42100 + - items: - enum: - qcom,purwa-iot-evk From 765958cd82321740b908c89783bccd4b094a1d05 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Stefan=20D=C3=B6singer?= Date: Wed, 28 Jan 2026 22:12:44 +0300 Subject: [PATCH 302/665] dt-bindings: arm: zte: Add D-Link DWR932M board based on zx297520v3 SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds a new binding file for ZTE, containing their zx297520v3 SoC and one board (D-Link DWR-932M) based on it. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Stefan Dösinger --- Changelog: v6: Removed extra boards, I'll add them when submitting their individual DTS files. Rephrase the subject to add "zte" and remove the redundant use of "binding". Moved the devicetree bindings patch ahead of the implementation patches. Moved the MAINTAINERS section from "ZX29" to "ARM/ZTE". --- .../devicetree/bindings/arm/zte.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/zte.yaml diff --git a/Documentation/devicetree/bindings/arm/zte.yaml b/Documentation/devicetree/bindings/arm/zte.yaml new file mode 100644 index 000000000000..f028d2cec7ab --- /dev/null +++ b/Documentation/devicetree/bindings/arm/zte.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/zte.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ZTE zx platforms + +maintainers: + - Stefan Dösinger + +description: | + ARM platforms using SoCs designed by ZTE. Currently this supports devices + based on the zx297520v3 SoC which is found in LTE routers. + +properties: + $nodename: + const: "/" + compatible: + oneOf: + - items: + - enum: + - dlink,dwr932m + - const: zte,zx297520v3 + +additionalProperties: true From 7d1f68e87b7302d0bd22c001e6c0511d0e827875 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Stefan=20D=C3=B6singer?= Date: Wed, 28 Jan 2026 22:13:17 +0300 Subject: [PATCH 303/665] ARM: dts: zte: Add D-Link DWR-932M support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds base DT definition for zx297520v3 and one board that consumes it. The stock kernel does not use the armv7 timer, but it seems to work fine. The board has other board-specific timers that would need a driver and I see no reason to bother with them since the arm standard timer works. The caveat is the non-standard GIC setup needed to handle the timer's level-low PPI. This is the responsibility of the boot loader and documented in Documentation/arch/arm/zte/zx297520v3.rst. Reviewed-by: Linus Walleij Signed-off-by: Stefan Dösinger --- Changes in v8: Remove redundant label, use "arm,pl011" for uart0 and 2 too. v6: Squash board + timer + uart patches into one v5: Prepend the SoC name in the device specific DTS filename. v4: Declare all uarts Remove the UART aliases for now. I can revisit this when I get my hands on a board that exposes two UARTs. --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/zte/Makefile | 3 + .../boot/dts/zte/zx297520v3-dlink-dwr932m.dts | 22 ++++ arch/arm/boot/dts/zte/zx297520v3.dtsi | 103 ++++++++++++++++++ 4 files changed, 129 insertions(+) create mode 100644 arch/arm/boot/dts/zte/Makefile create mode 100644 arch/arm/boot/dts/zte/zx297520v3-dlink-dwr932m.dts create mode 100644 arch/arm/boot/dts/zte/zx297520v3.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index efe38eb25301..28fba538d552 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -39,3 +39,4 @@ subdir-y += unisoc subdir-y += vt8500 subdir-y += xen subdir-y += xilinx +subdir-y += zte diff --git a/arch/arm/boot/dts/zte/Makefile b/arch/arm/boot/dts/zte/Makefile new file mode 100644 index 000000000000..f052cfbd636c --- /dev/null +++ b/arch/arm/boot/dts/zte/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only +dtb-$(CONFIG_SOC_ZX297520V3) += \ + zx297520v3-dlink-dwr932m.dtb diff --git a/arch/arm/boot/dts/zte/zx297520v3-dlink-dwr932m.dts b/arch/arm/boot/dts/zte/zx297520v3-dlink-dwr932m.dts new file mode 100644 index 000000000000..1700f46aba86 --- /dev/null +++ b/arch/arm/boot/dts/zte/zx297520v3-dlink-dwr932m.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2026 Stefan Dösinger + */ + +/dts-v1/; + +#include "zx297520v3.dtsi" + +/ { + model = "D-Link DWR-932M"; + compatible = "dlink,dwr932m", "zte,zx297520v3"; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x04000000>; + }; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/zte/zx297520v3.dtsi b/arch/arm/boot/dts/zte/zx297520v3.dtsi new file mode 100644 index 000000000000..a16c30a164bb --- /dev/null +++ b/arch/arm/boot/dts/zte/zx297520v3.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2026 Stefan Dösinger + */ + +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0>; + }; + }; + + /* Base bus clock and default for the UART. It will be replaced once a clock driver has + * been added. + */ + uartclk: uartclk-26000000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <26000000>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <26000000>; + interrupt-parent = <&gic>; + /* I don't think uboot sets CNTVOFF and the stock kernel doesn't use the + * arm timer at all. Since this is a single CPU system I don't think it + * really matters that the offset is random though. + */ + arm,cpu-registers-not-fw-configured; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + /* The GIC has a non-standard way of configuring ints between level-low/level + * high or rising edge/falling edge at 0xf2202070 and onwards. See AP_INT_MODE_BASE + * and AP_PPI_MODE_REG in the ZTE kernel, although the offsets in the kernel source + * seem wrong. + * + * Everything defaults to active-high/rising edge, but the timer is active-low. We + * currently rely on the boot loader to change timer IRQs to active-low for us for + * now. + */ + gic: interrupt-controller@f2000000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf2000000 0x10000>, + <0xf2040000 0x20000>; + }; + + uart0: serial@131000 { + compatible = "arm,pl011", "arm,primecell"; + arm,primecell-periphid = <0x0018c011>; + reg = <0x00131000 0x1000>; + interrupts = ; + clocks = <&uartclk>, <&uartclk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart1: serial@1408000 { + compatible = "arm,pl011", "arm,primecell"; + arm,primecell-periphid = <0x0018c011>; + reg = <0x01408000 0x1000>; + interrupts = ; + clocks = <&uartclk>, <&uartclk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart2: serial@140d000 { + compatible = "arm,pl011", "arm,primecell"; + arm,primecell-periphid = <0x0018c011>; + reg = <0x0140d000 0x1000>; + interrupts = ; + clocks = <&uartclk>, <&uartclk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; From 7557d67a6057362a65ad03a03cbefe7f03523003 Mon Sep 17 00:00:00 2001 From: Niravkumar L Rabara Date: Mon, 11 May 2026 01:15:19 -0700 Subject: [PATCH 304/665] ARM: dts: socfpga: arria10: Increase JFFS2 rootfs partition size Increase the JFFS2 partition size to support larger root filesystem. Also fix the partition label to match the actual start address. Signed-off-by: Niravkumar L Rabara Signed-off-by: Nazim Amirul Signed-off-by: Dinh Nguyen --- .../arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_nand.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_nand.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_nand.dts index a662df319a84..5f9b98b0b393 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_nand.dts +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_nand.dts @@ -18,9 +18,9 @@ partition@0 { label = "Boot and fpga data"; reg = <0x0 0x02500000>; }; - partition@1c00000 { + partition@2500000 { label = "Root Filesystem - JFFS2"; - reg = <0x02500000 0x05500000>; + reg = <0x02500000 0x3db00000>; }; }; }; From 14b0c168c7038f1d9e50f27e47d8e285f52cd2a3 Mon Sep 17 00:00:00 2001 From: Alim Akhtar Date: Fri, 17 Apr 2026 17:44:49 +0530 Subject: [PATCH 305/665] arm64: dts: exynosautov920: Add syscon hsi2 node Syscon HSI2 block has system configuration settings for HSI IPs, like ufs, usb etc. Add a syscon_hsi2 node entry so that related HSI controller can make use of the same. Signed-off-by: Sowon Na Signed-off-by: Alim Akhtar Link: https://patch.msgid.link/20260417121452.827054-2-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynosautov920.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi index 0bf7c4cb9846..0eb853770732 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -1426,6 +1426,12 @@ cmu_hsi2: clock-controller@16b00000 { "ethernet"; }; + syscon_hsi2: syscon@16c00000 { + compatible = "samsung,exynosautov920-hsi2-sysreg", + "syscon"; + reg = <0x16c00000 0x800>; + }; + pinctrl_hsi2: pinctrl@16c10000 { compatible = "samsung,exynosautov920-pinctrl"; reg = <0x16c10000 0x10000>; From ae326b14b2a5a5e426bea0210b984ee8dc5ed0bb Mon Sep 17 00:00:00 2001 From: Sowon Na Date: Fri, 17 Apr 2026 17:44:52 +0530 Subject: [PATCH 306/665] arm64: dts: exynosautov920: enable support for ufs controller Add ufs node for ExynosAutov920 SoC. Also enable ufs_phy and ufs controller nodes. Signed-off-by: Sowon Na Signed-off-by: Alim Akhtar Link: https://patch.msgid.link/20260417121452.827054-5-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski --- .../boot/dts/exynos/exynosautov920-sadk.dts | 8 +++++++ .../arm64/boot/dts/exynos/exynosautov920.dtsi | 21 +++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts index a397f068ed53..5873720c213e 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts +++ b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts @@ -83,6 +83,14 @@ &usi_0 { status = "okay"; }; +&ufs_0 { + status = "okay"; +}; + +&ufs_0_phy { + status = "okay"; +}; + &xtcxo { clock-frequency = <38400000>; }; diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi index 0eb853770732..f1f5efcdb91e 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -1444,6 +1444,27 @@ pinctrl_hsi2ufs: pinctrl@16d20000 { interrupts = ; }; + ufs_0: ufs@16e00000 { + compatible = "samsung,exynosautov920-ufs"; + reg = <0x16e00000 0x100>, + <0x16e01100 0x400>, + <0x16e80000 0x8000>, + <0x16d08000 0x800>; + reg-names = "hci", "vs_hci", "unipro", "ufsp"; + interrupts = ; + clocks = <&cmu_hsi2 CLK_MOUT_HSI2_UFS_EMBD_USER>, + <&cmu_hsi2 CLK_MOUT_HSI2_NOC_UFS_USER>; + clock-names = "core_clk", "sclk_unipro_main"; + freq-table-hz = <0 0>, <0 0>; + pinctrl-names = "default"; + pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; + phys = <&ufs_0_phy>; + phy-names = "ufs-phy"; + samsung,sysreg = <&syscon_hsi2 0x710>; + dma-coherent; + status = "disabled"; + }; + ufs_0_phy: phy@16e04000 { compatible = "samsung,exynosautov920-ufs-phy"; reg = <0x16e04000 0x4000>; From 2abdc3dcf9780d070e55a99fdf8f93440c798b84 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 2 May 2026 20:55:42 +0200 Subject: [PATCH 307/665] dt-bindings: clock: renesas,cpg-clocks: Document ZT/ZTR trace clock on R-Mobile APE6 Document the ZT trace bus and ZTR trace clocks on R-Mobile APE6. These clocks supply the coresight tracing modules, PTM, TPIU, ETB and replicator. Without these clocks, coresight tracing can not be operated. While this does change the ABI, it does so by extending the existing clock-output-names, therefore if old software is used with new DT, the coresight tracing parts will likely fail to probe, otherwise if new software is used with an old DT, there is no impact. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260502185557.93061-2-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml | 2 ++ include/dt-bindings/clock/r8a73a4-clock.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml index 925ed35d6658..703b5bf26717 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml @@ -90,6 +90,8 @@ allOf: - const: zx - const: zs - const: hp + - const: ztr + - const: zt - if: properties: diff --git a/include/dt-bindings/clock/r8a73a4-clock.h b/include/dt-bindings/clock/r8a73a4-clock.h index 655440a3e7c6..028ecef81451 100644 --- a/include/dt-bindings/clock/r8a73a4-clock.h +++ b/include/dt-bindings/clock/r8a73a4-clock.h @@ -23,6 +23,8 @@ #define R8A73A4_CLK_ZX 13 #define R8A73A4_CLK_ZS 14 #define R8A73A4_CLK_HP 15 +#define R8A73A4_CLK_ZTR 16 +#define R8A73A4_CLK_ZT 17 /* MSTP1 */ #define R8A73A4_CLK_TMU0 25 From dde06a5a809141c6c304241a0f78ff6e60191b87 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 2 May 2026 20:55:44 +0200 Subject: [PATCH 308/665] ARM: dts: renesas: r8a73a4: Add ZT/ZTR trace clock on R-Mobile APE6 Add ZT trace bus and ZTR trace clock on the R-Mobile APE6. These clock supply the coresight tracing modules, PTM, TPIU, ETB and replicator. Without these clock, the coresight tracing can not be operated. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260502185557.93061-4-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/renesas/r8a73a4.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/renesas/r8a73a4.dtsi b/arch/arm/boot/dts/renesas/r8a73a4.dtsi index 2e19ebf9e2ba..a70a0dc402a5 100644 --- a/arch/arm/boot/dts/renesas/r8a73a4.dtsi +++ b/arch/arm/boot/dts/renesas/r8a73a4.dtsi @@ -512,7 +512,7 @@ cpg_clocks: cpg_clocks@e6150000 { clock-output-names = "main", "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b", "m1", "m2", - "zx", "zs", "hp"; + "zx", "zs", "hp", "ztr", "zt"; }; /* Variable factor clocks (DIV6) */ From 44f1ef06ceec55b7704c7d773d6136ca8b90f8b7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 2 May 2026 20:55:45 +0200 Subject: [PATCH 309/665] ARM: dts: renesas: r8a73a4: Describe coresight on R-Mobile APE6 Describe coresight topology on R-Mobile APE6. Extend the current PTM node with connection funnel, TPIU, ETB and replicator. The coresight on this hardware is clocked from the ZT/ZTR trace clock. Note that only core 0 part of the topology is described, because the other cores are still not present in the DT. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260502185557.93061-5-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/renesas/r8a73a4.dtsi | 112 ++++++++++++++++++++++++- 1 file changed, 110 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/renesas/r8a73a4.dtsi b/arch/arm/boot/dts/renesas/r8a73a4.dtsi index a70a0dc402a5..c3427dc7cf7d 100644 --- a/arch/arm/boot/dts/renesas/r8a73a4.dtsi +++ b/arch/arm/boot/dts/renesas/r8a73a4.dtsi @@ -47,9 +47,117 @@ L2_CA7: cache-controller-1 { }; }; - ptm { - compatible = "arm,coresight-etm3x"; + replicator { + compatible = "arm,coresight-static-replicator"; + clocks = <&cpg_clocks R8A73A4_CLK_ZTR>; + clock-names = "atclk"; power-domains = <&pd_d4>; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + port@1 { + reg = <1>; + + replicator_out_port1: endpoint { + remote-endpoint = <&etb_in_port>; + }; + }; + }; + + in-ports { + /* replicator input port */ + port { + replicator_in_port0: endpoint { + remote-endpoint = <&funnel_out_port>; + }; + }; + }; + }; + + etb@e6f81000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0 0xe6f81000 0 0x1000>; + clocks = <&cpg_clocks R8A73A4_CLK_ZT>, <&cpg_clocks R8A73A4_CLK_ZTR>; + clock-names = "apb_pclk", "atclk"; + power-domains = <&pd_d4>; + + in-ports { + port { + etb_in_port: endpoint { + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + }; + + tpiu@e6f83000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0 0xe6f83000 0 0x1000>; + clocks = <&cpg_clocks R8A73A4_CLK_ZT>, <&cpg_clocks R8A73A4_CLK_ZTR>; + clock-names = "apb_pclk", "atclk"; + power-domains = <&pd_d4>; + + in-ports { + port { + tpiu_in_port: endpoint { + remote-endpoint = <&replicator_out_port0>; + }; + }; + }; + }; + + funnel { + compatible = "arm,coresight-static-funnel"; + + /* funnel output ports */ + out-ports { + port { + funnel_out_port: endpoint { + remote-endpoint = + <&replicator_in_port0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* funnel input ports */ + port@0 { + reg = <0>; + funnel0_in_port0: endpoint { + remote-endpoint = <&ptm0_out_port>; + }; + }; + }; + }; + + ptm@e6fbc000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe6fbc000 0 0x1000>; + clocks = <&cpg_clocks R8A73A4_CLK_ZT>, <&cpg_clocks R8A73A4_CLK_ZTR>; + clock-names = "apb_pclk", "atclk"; + cpu = <&cpu0>; + power-domains = <&pd_d4>; + + out-ports { + port { + ptm0_out_port: endpoint { + remote-endpoint = <&funnel0_in_port0>; + }; + }; + }; }; timer { From 48f1f6f480741f014f3774096236fff91cdcc297 Mon Sep 17 00:00:00 2001 From: Vitor Soares Date: Wed, 6 May 2026 15:34:26 +0100 Subject: [PATCH 310/665] arm64: dts: ti: k3-am62-verdin: Add DSI to HDMI adapter overlay Add a device-tree overlay for the Toradex DSI to HDMI Adapter, an accessory that connects to the Verdin DSI_1 interface and provides a full-size HDMI Type-A output. The adapter is based on the Lontium LT8912B DSI-to-HDMI bridge. The overlay is also combined with the Verdin AM62 carrier board device trees to provide ready-to-use DTBs for the Dahlia and Development Board carriers, in both WiFi and non-WiFi SoM variants. Link: https://developer.toradex.com/hardware/accessories/add-ons/dsi-hdmi-adapter Signed-off-by: Vitor Soares Link: https://patch.msgid.link/20260506143427.348806-2-ivitro@gmail.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 13 +++ .../dts/ti/k3-am625-verdin-dsi-to-hdmi.dtso | 94 +++++++++++++++++++ 2 files changed, 107 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-dsi-to-hdmi.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 7642c06ca834..21db60cd19de 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -9,19 +9,32 @@ # alphabetically. # Boards with AM62x SoC +k3-am625-verdin-nonwifi-dahlia-dsi-to-hdmi-dtbs := k3-am625-verdin-nonwifi-dahlia.dtb \ + k3-am625-verdin-dsi-to-hdmi.dtbo +k3-am625-verdin-nonwifi-dev-dsi-to-hdmi-dtbs := k3-am625-verdin-nonwifi-dev.dtb \ + k3-am625-verdin-dsi-to-hdmi.dtbo +k3-am625-verdin-wifi-dahlia-dsi-to-hdmi-dtbs := k3-am625-verdin-wifi-dahlia.dtb \ + k3-am625-verdin-dsi-to-hdmi.dtbo +k3-am625-verdin-wifi-dev-dsi-to-hdmi-dtbs := k3-am625-verdin-wifi-dev.dtb \ + k3-am625-verdin-dsi-to-hdmi.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay-csi2-ov5640.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay-csi2-tevi-ov5640.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-tqma62xx-mba62xx.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dsi-to-hdmi.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dahlia-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dahlia.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dev-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dev.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-ivy.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-mallow.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-yavia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-zinnia.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dev-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-ivy.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-mallow.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-dsi-to-hdmi.dtso b/arch/arm64/boot/dts/ti/k3-am625-verdin-dsi-to-hdmi.dtso new file mode 100644 index 000000000000..a219faf0dcc6 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-dsi-to-hdmi.dtso @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Toradex DSI to HDMI Adapter on Verdin DSI_1 + * + * https://developer.toradex.com/hardware/accessories/add-ons/dsi-hdmi-adapter + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + hdmi-connector { + compatible = "hdmi-connector"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3_dsi_gpio>; + ddc-i2c-bus = <&main_i2c2>; + /* Verdin PWM_3_DSI (SODIMM 19) */ + hpd-gpios = <&main_gpio1 17 GPIO_ACTIVE_HIGH>; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&dsi_hdmi_bridge_out>; + }; + }; + }; +}; + +&dsi_bridge { + status = "okay"; +}; + +&dsi_bridge_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi_bridge_out: endpoint { + remote-endpoint = <&dsi_hdmi_bridge_in>; + }; + }; +}; + +&dss { + status = "okay"; +}; + +/* Verdin PWM_3_DSI (SODIMM 19) repurposed as HDMI HPD GPIO */ +&epwm1 { + status = "disabled"; +}; + +/* Verdin I2C_1 */ +&main_i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + hdmi@48 { + compatible = "lontium,lt8912b"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dsi1_bkl_en>; + /* Verdin GPIO_10_DSI (SODIMM 21) */ + reset-gpios = <&main_gpio0 30 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_hdmi_bridge_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&dsi_bridge_out>; + }; + }; + + port@1 { + reg = <1>; + + dsi_hdmi_bridge_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; From 3869417f8996fb076998342d0db560fdd795a3a6 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Fri, 15 May 2026 17:16:31 +0100 Subject: [PATCH 311/665] riscv: dts: microchip: remove redudant enabling of syscontroller The system controller is never disabled, there's no need to ever enable it. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts | 1 - arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts | 4 ---- arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi | 4 ---- arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts | 4 ---- arch/riscv/boot/dts/microchip/mpfs-polarberry.dts | 4 ---- arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts | 4 ---- arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts | 4 ---- arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts | 4 ---- 8 files changed, 29 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts index 7bbd400b7103..6d7037c9528d 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts @@ -328,7 +328,6 @@ mmc@1 { &syscontroller { microchip,bitstream-flash = <&sys_ctrl_flash>; - status = "okay"; }; &syscontroller_qspi { diff --git a/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts index f769c9d5d7b4..da2fcde263e3 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts @@ -199,7 +199,3 @@ &spi0 { &spi1 { status = "okay"; }; - -&syscontroller { - status = "okay"; -}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi index 7816408343a3..a11e3103b8f2 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi @@ -238,10 +238,6 @@ &spi1 { status = "okay"; }; -&syscontroller { - status = "okay"; -}; - &syscontroller_qspi { /* * The flash *is* there, but Icicle kits that have engineering sample diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts index 86234968df48..973e34b74be4 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts @@ -179,10 +179,6 @@ &spi1 { status = "okay"; }; -&syscontroller { - status = "okay"; -}; - &usb { status = "okay"; dr_mode = "host"; diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts index 510d59153cd0..cad0871a62a5 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts @@ -112,7 +112,3 @@ &refclk { &rtc { status = "okay"; }; - -&syscontroller { - status = "okay"; -}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts index 8f1908a10567..46ded8a4fc36 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts @@ -149,10 +149,6 @@ &rtc { status = "okay"; }; -&syscontroller { - status = "okay"; -}; - &usb { status = "okay"; dr_mode = "otg"; diff --git a/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts index bc15530a2979..c6950410e918 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts @@ -171,10 +171,6 @@ flash@0 { }; }; -&syscontroller { - status = "okay"; -}; - &usb { status = "okay"; dr_mode = "host"; diff --git a/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts b/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts index ef5bff3093fc..180fd8891903 100644 --- a/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts +++ b/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts @@ -170,7 +170,3 @@ &refclk { &rtc { status = "okay"; }; - -&syscontroller { - status = "okay"; -}; From 2d77e577109967ef65f269c1fc1d6a659d4260fb Mon Sep 17 00:00:00 2001 From: Iker Pedrosa Date: Fri, 15 May 2026 12:48:59 +0200 Subject: [PATCH 312/665] riscv: dts: spacemit: k1: add SD card controller and pinctrl support Add SD card controller infrastructure for SpacemiT K1 SoC with complete pinctrl support for both standard and UHS modes. - Add sdhci0 controller definition with clocks, resets and interrupts - Add mmc1_cfg pinctrl for 3.3V standard SD operation - Add mmc1_uhs_cfg pinctrl for 1.8V UHS high-speed operation - Configure appropriate drive strength and power-source properties This provides complete SD card infrastructure that K1-based boards can enable. Tested-by: Anand Moon Tested-by: Trevor Gamblin Tested-by: Vincent Legoll Reviewed-by: Troy Mitchell Signed-off-by: Iker Pedrosa Link: https://patch.msgid.link/20260515-orangepi-sd-card-uhs-v10-1-094af27e310d@gmail.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 40 ++++++++++++++++++++ arch/riscv/boot/dts/spacemit/k1.dtsi | 13 +++++++ 2 files changed, 53 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi index 34d88334e95e..4e9a62d0e85b 100644 --- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi @@ -590,4 +590,44 @@ ssp3-0-frm-pins { power-source = <3300>; }; }; + + mmc1_cfg: mmc1-cfg { + mmc1-data-cmd-pins { + pinmux = , /* mmc1_d3 */ + , /* mmc1_d2 */ + , /* mmc1_d1 */ + , /* mmc1_d0 */ + ; /* mmc1_cmd */ + bias-pull-up = <1>; + drive-strength = <19>; + power-source = <3300>; + }; + + mmc1-clk-pins { + pinmux = ; /* mmc1_clk */ + bias-pull-down = <1>; + drive-strength = <19>; + power-source = <3300>; + }; + }; + + mmc1_uhs_cfg: mmc1-uhs-cfg { + mmc1-data-cmd-pins { + pinmux = , /* mmc1_d3 */ + , /* mmc1_d2 */ + , /* mmc1_d1 */ + , /* mmc1_d0 */ + ; /* mmc1_cmd */ + bias-pull-up = <1>; + drive-strength = <42>; + power-source = <1800>; + }; + + mmc1-clk-pins { + pinmux = ; /* mmc1_clk */ + bias-pull-down = <1>; + drive-strength = <42>; + power-source = <1800>; + }; + }; }; diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index 24becab4c959..06469c364eef 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -1214,6 +1214,19 @@ usb_dwc3: usb@c0a00000 { status = "disabled"; }; + sdhci0: mmc@d4280000 { + compatible = "spacemit,k1-sdhci"; + reg = <0x0 0xd4280000 0x0 0x200>; + clocks = <&syscon_apmu CLK_SDH_AXI>, + <&syscon_apmu CLK_SDH0>; + clock-names = "core", "io"; + resets = <&syscon_apmu RESET_SDH_AXI>, + <&syscon_apmu RESET_SDH0>; + reset-names = "axi", "sdh"; + interrupts = <99>; + status = "disabled"; + }; + emmc: mmc@d4281000 { compatible = "spacemit,k1-sdhci"; reg = <0x0 0xd4281000 0x0 0x200>; From 2585c60ce2f977b13f14a67d1e3ed9c73fd7f381 Mon Sep 17 00:00:00 2001 From: Iker Pedrosa Date: Fri, 15 May 2026 12:49:00 +0200 Subject: [PATCH 313/665] riscv: dts: spacemit: k1-orangepi-rv2: add SD card support with UHS modes Add complete SD card controller support with UHS high-speed modes. - Enable sdhci0 controller with 4-bit bus width - Configure card detect GPIO with GPIO_ACTIVE_LOW logic - Connect vmmc-supply to buck4 for 3.3V card power - Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching - Add dual pinctrl states for voltage-dependent pin configuration - Support UHS-I SDR25, SDR50, and SDR104 modes - Add stable MMC device aliases (mmc0 = eMMC, mmc1 = SD card) This enables full SD card functionality including high-speed UHS modes for improved performance. Tested-by: Anand Moon Tested-by: Trevor Gamblin Tested-by: Michael Opdenacker Tested-by: Vincent Legoll Signed-off-by: Iker Pedrosa Link: https://patch.msgid.link/20260515-orangepi-sd-card-uhs-v10-2-094af27e310d@gmail.com Signed-off-by: Yixun Lan --- .../boot/dts/spacemit/k1-orangepi-rv2.dts | 22 ++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts index c95ca38e3d4a..bd40bc9011e2 100644 --- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts @@ -17,6 +17,8 @@ aliases { serial0 = &uart0; ethernet0 = ð0; ethernet1 = ð1; + mmc0 = &emmc; + mmc1 = &sdhci0; }; chosen { @@ -202,7 +204,7 @@ buck6 { regulator-always-on; }; - aldo1 { + aldo1: aldo1 { regulator-min-microvolt = <500000>; regulator-max-microvolt = <3400000>; regulator-boot-on; @@ -319,3 +321,21 @@ hub_3_0: hub@2 { vdd-supply = <&vcc_5v0>; }; }; + +&sdhci0 { + pinctrl-names = "default", "uhs"; + pinctrl-0 = <&mmc1_cfg>; + pinctrl-1 = <&mmc1_uhs_cfg>; + bus-width = <4>; + cd-gpios = <&gpio K1_GPIO(80) GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + disable-wp; + cap-sd-highspeed; + vmmc-supply = <&buck4_3v3>; + vqmmc-supply = <&aldo1>; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; From c76e2f058cbcab84e4a703f26857a58bdf6a0042 Mon Sep 17 00:00:00 2001 From: Iker Pedrosa Date: Fri, 15 May 2026 12:49:01 +0200 Subject: [PATCH 314/665] riscv: dts: spacemit: k1-bananapi-f3: add SD card support with UHS modes Add complete SD card controller support with UHS high-speed modes. - Enable sdhci0 controller with 4-bit bus width - Configure card detect GPIO with GPIO_ACTIVE_LOW and internal pull-up support - Connect vmmc-supply to buck4 for 3.3V card power - Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching - Add dual pinctrl states for voltage-dependent pin configuration - Support UHS-I SDR25, SDR50, and SDR104 modes - Add stable MMC device aliases (mmc0 = eMMC, mmc1 = SD card) This enables full SD card functionality including high-speed UHS modes for improved performance. Suggested-by: Anand Moon Tested-by: Anand Moon Tested-by: Margherita Milani Tested-by: Aurelien Jarno Reviewed-by: Aurelien Jarno Signed-off-by: Iker Pedrosa Link: https://patch.msgid.link/20260515-orangepi-sd-card-uhs-v10-3-094af27e310d@gmail.com Signed-off-by: Yixun Lan --- .../boot/dts/spacemit/k1-bananapi-f3.dts | 24 +++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts index e20daa50a152..72f77e9edd63 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -17,6 +17,8 @@ aliases { spi3 = &spi3; i2c2 = &i2c2; i2c8 = &i2c8; + mmc0 = &emmc; + mmc1 = &sdhci0; }; chosen { @@ -221,7 +223,7 @@ buck3_1v8: buck3 { regulator-always-on; }; - buck4 { + buck4: buck4 { regulator-min-microvolt = <500000>; regulator-max-microvolt = <3300000>; regulator-ramp-delay = <5000>; @@ -242,7 +244,7 @@ buck6 { regulator-always-on; }; - aldo1 { + aldo1: aldo1 { regulator-min-microvolt = <500000>; regulator-max-microvolt = <3400000>; regulator-boot-on; @@ -374,3 +376,21 @@ hub_3_0: hub@2 { reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; }; }; + +&sdhci0 { + pinctrl-names = "default", "uhs"; + pinctrl-0 = <&mmc1_cfg>; + pinctrl-1 = <&mmc1_uhs_cfg>; + bus-width = <4>; + cd-gpios = <&gpio K1_GPIO(80) (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + no-mmc; + no-sdio; + disable-wp; + cap-sd-highspeed; + vmmc-supply = <&buck4>; + vqmmc-supply = <&aldo1>; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; From e2dac7c7a3a8970feeeb758f782ce86b89625ebd Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Wed, 13 May 2026 09:19:49 +0200 Subject: [PATCH 315/665] riscv: dts: spacemit: k1-musepi-pro: add PMIC and power infrastructure Enable i2c8 and add the connected SpacemiT P1 PMIC with its related regulators for the board's power infrastructure and voltage regulation support. Signed-off-by: Andre Heider Link: https://patch.msgid.link/20260513071958.29574-2-a.heider@gmail.com Signed-off-by: Yixun Lan --- .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 134 ++++++++++++++++++ 1 file changed, 134 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts index 29e333b670cf..653e5a1bf41b 100644 --- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts @@ -17,6 +17,7 @@ / { aliases { ethernet0 = ð0; serial0 = &uart0; + i2c8 = &i2c8; }; chosen { @@ -33,6 +34,15 @@ led1 { default-state = "on"; }; }; + + reg_vcc_4v: regulator-vcc-4v { + compatible = "regulator-fixed"; + regulator-name = "VCC4V0"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; + regulator-boot-on; + regulator-always-on; + }; }; &emmc { @@ -72,6 +82,130 @@ &pdma { status = "okay"; }; +&i2c8 { + pinctrl-0 = <&i2c8_cfg>; + pinctrl-names = "default"; + status = "okay"; + + pmic@41 { + compatible = "spacemit,p1"; + reg = <0x41>; + interrupts = <64>; + vin1-supply = <®_vcc_4v>; + vin2-supply = <®_vcc_4v>; + vin3-supply = <®_vcc_4v>; + vin4-supply = <®_vcc_4v>; + vin5-supply = <®_vcc_4v>; + vin6-supply = <®_vcc_4v>; + aldoin-supply = <®_vcc_4v>; + dldoin1-supply = <&buck5>; + dldoin2-supply = <&buck5>; + + regulators { + buck1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck3_1v8: buck3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck4_3v3: buck4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck5: buck5 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck6 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + aldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + + aldo2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + aldo3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + aldo4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + + dldo2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-always-on; + }; + + dldo5 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo6 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-always-on; + }; + + dldo7 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + }; + }; +}; + &uart0 { pinctrl-0 = <&uart0_2_cfg>; pinctrl-names = "default"; From 6bc75cfa56e885c2eab80e215f0a610075505846 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Wed, 13 May 2026 09:19:50 +0200 Subject: [PATCH 316/665] riscv: dts: spacemit: k1-musepi-pro: add 24c02 eeprom Enable i2c2 and add the connected GT24C02B EEPROM. It contains an ONIE TLV table: => tlv_eeprom TLV: 0 [ 12.162] TlvInfo Header: [ 12.162] Id String: TlvInfo [ 12.165] Version: 1 [ 12.168] Total Length: 58 [ 12.171] TLV Name Code Len Value [ 12.175] -------------------- ---- --- ----- [ 12.179] Product Name 0x21 16 k1-x_MUSE-Pi-Pro [ 12.184] Serial Number 0x23 17 BPMIMXXXXXXXXXXXX [ 12.189] Unknown 0x41 1 0x02 [ 12.194] Base MAC Address 0x24 6 FE:FE:FE:XX:XX:XX [ 12.199] MAC Addresses 0x2A 2 2 [ 12.203] CRC-32 0xFE 4 0x395ECD34 [ 12.207] Checksum is valid. (With 0x41 as TLV_CODE_DDR_CSNUM) Signed-off-by: Andre Heider Link: https://patch.msgid.link/20260513071958.29574-3-a.heider@gmail.com Signed-off-by: Yixun Lan --- .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts index 653e5a1bf41b..b8e73eed8e62 100644 --- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts @@ -17,6 +17,7 @@ / { aliases { ethernet0 = ð0; serial0 = &uart0; + i2c2 = &i2c2; i2c8 = &i2c8; }; @@ -82,6 +83,38 @@ &pdma { status = "okay"; }; +&i2c2 { + pinctrl-0 = <&i2c2_0_cfg>; + pinctrl-names = "default"; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + vcc-supply = <&buck3_1v8>; /* EEPROM_VCC1V8 */ + pagesize = <8>; + read-only; + size = <256>; + + nvmem-layout { + compatible = "onie,tlv-layout"; + + product-name { + }; + + serial-number { + }; + + mac-address { + #nvmem-cell-cells = <1>; + }; + + num-macs { + }; + }; + }; +}; + &i2c8 { pinctrl-0 = <&i2c8_cfg>; pinctrl-names = "default"; From 735b1b205d07bf7bfa55b1f50f5485b9cc42a251 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Wed, 13 May 2026 09:19:51 +0200 Subject: [PATCH 317/665] riscv: dts: spacemit: k1-musepi-pro: enable QSPI and add SPI NOR Add the QSPI controller node and describe the attached SPI NOR flash (Winbond W25Q64FWSSAQ). Add a corresponding vendor flash partition layout. Signed-off-by: Andre Heider Link: https://patch.msgid.link/20260513071958.29574-4-a.heider@gmail.com Signed-off-by: Yixun Lan --- .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts index b8e73eed8e62..74841cffd5f5 100644 --- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts @@ -44,6 +44,15 @@ reg_vcc_4v: regulator-vcc-4v { regulator-boot-on; regulator-always-on; }; + + reg_qspi_vcc1v833: regulator-qspi-vcc1v833 { + compatible = "regulator-fixed"; + regulator-name = "QSPI_VCC1833"; + regulator-min-microvolt = <1833000>; + regulator-max-microvolt = <1833000>; + regulator-always-on; + vin-supply = <&buck4_3v3>; + }; }; &emmc { @@ -239,6 +248,47 @@ dldo7 { }; }; +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&qspi_cfg>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <26500000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + vcc-supply = <®_qspi_vcc1v833>; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootinfo@0 { + reg = <0x0 0x10000>; + }; + private@10000 { + reg = <0x10000 0x10000>; + }; + fsbl@20000 { + reg = <0x20000 0x40000>; + }; + env@60000 { + reg = <0x60000 0x10000>; + }; + opensbi@70000 { + reg = <0x70000 0x30000>; + }; + uboot@a0000 { + reg = <0xa0000 0x760000>; + }; + }; + }; +}; + &uart0 { pinctrl-0 = <&uart0_2_cfg>; pinctrl-names = "default"; From 83c658c7a82304a2bc944cdd4a5b4f98d19322f0 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Wed, 13 May 2026 09:19:52 +0200 Subject: [PATCH 318/665] riscv: dts: spacemit: k1-musepi-pro: enable USB 3 ports Enable the DWC3 USB 3.0 controller, its associated combo_phy (USB 3 PHY) and usbphy2 (USB 2 PHY) on the MusePi Pro board. The board uses a VLI VL817 hub, providing four ports. Signed-off-by: Andre Heider Link: https://patch.msgid.link/20260513071958.29574-5-a.heider@gmail.com Signed-off-by: Yixun Lan --- .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts index 74841cffd5f5..b284bf416880 100644 --- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts @@ -53,6 +53,26 @@ reg_qspi_vcc1v833: regulator-qspi-vcc1v833 { regulator-always-on; vin-supply = <&buck4_3v3>; }; + + reg_5v_vbus: regulator-5v-vbus { + compatible = "regulator-fixed"; + regulator-name = "5V_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + gpio = <&gpio K1_GPIO(79) GPIO_ACTIVE_HIGH>; /* USB3_PWREN */ + enable-active-high; + }; + + reg_vcc5v_hub: regulator-vcc5v-hub { + compatible = "regulator-fixed"; + regulator-name = "VCC5V0_HUB"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + gpio = <&gpio K1_GPIO(127) GPIO_ACTIVE_HIGH>; /* HUB_PWREN */ + enable-active-high; + }; }; &emmc { @@ -65,6 +85,10 @@ &emmc { status = "okay"; }; +&combo_phy { + status = "okay"; +}; + ð0 { phy-handle = <&rgmii0>; phy-mode = "rgmii-id"; @@ -294,3 +318,31 @@ &uart0 { pinctrl-names = "default"; status = "okay"; }; + +&usbphy2 { + status = "okay"; +}; + +&usb_dwc3 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + vbus-supply = <®_5v_vbus>; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb2109,2817"; + reg = <0x1>; + vdd-supply = <®_vcc5v_hub>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_LOW>; /* HUB_RST */ + }; + + hub_3_0: hub@2 { + compatible = "usb2109,817"; + reg = <0x2>; + vdd-supply = <®_vcc5v_hub>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_LOW>; /* HUB_RST */ + }; +}; From d9ab0a855ba13f1db3ae16539348714c74010a22 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Wed, 13 May 2026 09:19:53 +0200 Subject: [PATCH 319/665] riscv: dts: spacemit: k1-musepi-pro: enable PCIe ports Enable the two PCIe controllers along with their associated PHYs. They are routed to the M.2 M-key connector and to the PCIe slot. Signed-off-by: Andre Heider Link: https://patch.msgid.link/20260513071958.29574-6-a.heider@gmail.com Signed-off-by: Yixun Lan --- .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts index b284bf416880..898b537ba0bc 100644 --- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts @@ -36,6 +36,14 @@ led1 { }; }; + reg_pcie_vcc_3v3: regulator-pcie-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "PCIE_VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + reg_vcc_4v: regulator-vcc-4v { compatible = "regulator-fixed"; regulator-name = "VCC4V0"; @@ -272,6 +280,36 @@ dldo7 { }; }; +&pcie1_phy { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_3_cfg>; + status = "okay"; +}; + +&pcie1_port { + phys = <&pcie1_phy>; + vpcie3v3-supply = <®_pcie_vcc_3v3>; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie2_phy { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_4_cfg>; + status = "okay"; +}; + +&pcie2_port { + phys = <&pcie2_phy>; + vpcie3v3-supply = <®_pcie_vcc_3v3>; +}; + +&pcie2 { + status = "okay"; +}; + &qspi { pinctrl-names = "default"; pinctrl-0 = <&qspi_cfg>; From f125c6085fd775f09a316f61cc89a0ae86826895 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Wed, 13 May 2026 09:19:54 +0200 Subject: [PATCH 320/665] riscv: dts: spacemit: k1-musepi-pro: set default console baud rate Allow serial output with the same uboot/opensbi settings so the console works without providing a cmdline. Signed-off-by: Andre Heider Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260513071958.29574-7-a.heider@gmail.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts index 898b537ba0bc..4aef287353ca 100644 --- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts @@ -22,7 +22,7 @@ aliases { }; chosen { - stdout-path = "serial0"; + stdout-path = "serial0:115200n8"; }; leds { From 32fbd42e6b56aae4587c76f53a51d187add4eec7 Mon Sep 17 00:00:00 2001 From: Ekansh Gupta Date: Wed, 15 Apr 2026 12:10:46 +0530 Subject: [PATCH 321/665] arm64: dts: qcom: monaco: add GDSP fastrpc-compute-cb nodes Add GDSP fastrpc compute-cb nodes for monaco SoC. Signed-off-by: Ekansh Gupta Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260415-monacogdsp-v1-1-077ded36c7fc@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco.dtsi | 29 ++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 7b1d57460f1e..ce6ff259cb4a 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -7615,6 +7615,35 @@ IPCC_MPROC_SIGNAL_GLINK_QMP label = "gpdsp"; qcom,remote-pid = <17>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "gdsp0"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x28a1 0x0>; + dma-coherent; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x28a2 0x0>; + dma-coherent; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x28a3 0x0>; + dma-coherent; + }; + }; }; }; From 487c97b671e4f224adb9d74b9f14372e283bea32 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Wed, 15 Apr 2026 13:56:08 +0200 Subject: [PATCH 322/665] arm64: dts: qcom: sdm845-shift-axolotl: describe WiFi/BT properly The onboard WiFi / BT device, WCN3990, has a simple on-chip PMU, which further spreads generated voltage. Describe the PMU in the device tree. Signed-off-by: David Heidelberg Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260415-axolotl-wifi-v1-1-07df39cfc0a4@ixit.cz Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm845-shift-axolotl.dts | 65 ++++++++++++++++--- 1 file changed, 55 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index 14a683ee3823..f21b914f22b5 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -105,6 +105,43 @@ vreg_s4a_1p8: pm8998-smps4 { vin-supply = <&vph_pwr>; }; + + wcn3990-pmu { + compatible = "qcom,wcn3990-pmu"; + + pinctrl-0 = <&sw_ctrl_default>; + pinctrl-names = "default"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l17a_1p3>; + vddch0-supply = <&vreg_l25a_3p3>; + vddch1-supply = <&vreg_l23a_3p3>; + + swctrl-gpios = <&pm8998_gpios 3 GPIO_ACTIVE_HIGH>; + + regulators { + vreg_pmu_io: ldo0 { + regulator-name = "vreg_pmu_io"; + }; + + vreg_pmu_xo: ldo1 { + regulator-name = "vreg_pmu_xo"; + }; + + vreg_pmu_rf: ldo2 { + regulator-name = "vreg_pmu_rf"; + }; + + vreg_pmu_ch0: ldo3 { + regulator-name = "vreg_pmu_ch0"; + }; + + vreg_pmu_ch1: ldo4 { + regulator-name = "vreg_pmu_ch1"; + }; + }; + }; }; &adsp_pas { @@ -546,6 +583,13 @@ &mss_pil { }; &pm8998_gpios { + sw_ctrl_default: sw-ctrl-default-state { + pins = "gpio3"; + function = "normal"; + input-enable; + bias-pull-down; + }; + volume_up_gpio: pm8998-gpio6-state { pinconf { pins = "gpio6"; @@ -784,10 +828,11 @@ bluetooth { */ firmware-name = "SHIFT/axolotl/crnv21.bin"; - vddio-supply = <&vreg_s4a_1p8>; - vddxo-supply = <&vreg_l7a_1p8>; - vddrf-supply = <&vreg_l17a_1p3>; - vddch0-supply = <&vreg_l25a_3p3>; + vddio-supply = <&vreg_pmu_io>; + vddxo-supply = <&vreg_pmu_xo>; + vddrf-supply = <&vreg_pmu_rf>; + vddch0-supply = <&vreg_pmu_ch0>; + max-speed = <3200000>; }; }; @@ -842,14 +887,14 @@ &venus { }; &wifi { - status = "okay"; - vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; - vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; - vdd-1.8-xo-supply = <&vreg_l7a_1p8>; - vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; - vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; + vdd-1.8-xo-supply = <&vreg_pmu_xo>; + vdd-1.3-rfa-supply = <&vreg_pmu_rf>; + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>; + vdd-3.3-ch1-supply = <&vreg_pmu_ch1>; qcom,calibration-variant = "shift_axolotl"; qcom,snoc-host-cap-8bit-quirk; + + status = "okay"; }; From e2518e8cb1dde64af2d1bb246639bb7ef7523f7a Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sat, 16 May 2026 16:00:30 +0800 Subject: [PATCH 323/665] riscv: dts: spacemit: enable QSPI for OrangePi RV2 Enable the QSPI controller and the XM25QU128C SPI NOR flash on the OrangePi RV2 board. Add a flash partition layout from vendor UBoot. Signed-off-by: Chukun Pan Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260516080030.1736836-1-amadeus@jmu.edu.cn Signed-off-by: Yixun Lan --- .../boot/dts/spacemit/k1-orangepi-rv2.dts | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts index bd40bc9011e2..7c49bce427f3 100644 --- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts @@ -290,6 +290,51 @@ &pcie2 { status = "okay"; }; +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&qspi_cfg>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <26500000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + vcc-supply = <&buck3_1v8>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootinfo@0 { + reg = <0x00000 0x010000>; + }; + + private@10000 { + reg = <0x10000 0x010000>; + }; + + fsbl@20000 { + reg = <0x20000 0x040000>; + }; + + env@60000 { + reg = <0x60000 0x010000>; + }; + + opensbi@70000 { + reg = <0x70000 0x030000>; + }; + + uboot@a0000 { + reg = <0xa0000 0x760000>; + }; + }; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_2_cfg>; From 46ed8942abf52f5929945419ae25be43d50afb1d Mon Sep 17 00:00:00 2001 From: Dawid Glazik Date: Fri, 24 Apr 2026 22:20:59 +0200 Subject: [PATCH 324/665] ARM: dts: aspeed-g6: move i2c controllers directly into apb node We currently have the apb's mapping of the i2c controller space as a labelled mostly-empty node: apb { i2c: bus@1e78a000 { ranges = <...>; }; } ... and then define the contents of the i2c block later: i2c: { i2c0: i2c-bus@80 { reg = <0x80 0x80>; }; i2c1: i2c-bus@100 { reg = <0x100 0x80>; }; } Krzysztof mentions[1] that isn't convention though, with the top-level simple-bus being empty and linked via the label. So, drop the label usage and move the i2c bus definition into the simple-bus node directly under the apb: apb { bus@1e78a000 { ranges = <...>; i2c0: i2c-bus@80 { reg = <0x80 0x80>; }; i2c1: i2c-bus@100 { reg = <0x100 0x80>; }; }; } This will allow us to be consistent when we add new definitions for the i3c nodes, which would require the latter format. Link: https://lore.kernel.org/linux-devicetree/c5331cf8-7295-4e6a-ba39-e0751a2c357e@kernel.org/ [1] Suggested-by: Jeremy Kerr Signed-off-by: Dawid Glazik Link: https://patch.msgid.link/7c7010a87bb70b9e2abdadfea76d41cdcb88a82f.1777058942.git.dawid.glazik@linux.intel.com Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 452 ++++++++++++------------ 1 file changed, 225 insertions(+), 227 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi index 189bc3bbb47c..f5641128614f 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -835,11 +835,235 @@ uart9: serial@1e790300 { status = "disabled"; }; - i2c: bus@1e78a000 { + bus@1e78a000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1e78a000 0x1000>; + + i2c0: i2c@80 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + status = "disabled"; + }; + + i2c1: i2c@100 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x100 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_default>; + status = "disabled"; + }; + + i2c2: i2c@180 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x180 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_default>; + status = "disabled"; + }; + + i2c3: i2c@200 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x200 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4_default>; + status = "disabled"; + }; + + i2c4: i2c@280 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x280 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c5_default>; + status = "disabled"; + }; + + i2c5: i2c@300 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x300 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c6_default>; + status = "disabled"; + }; + + i2c6: i2c@380 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x380 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c7_default>; + status = "disabled"; + }; + + i2c7: i2c@400 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x400 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c8_default>; + status = "disabled"; + }; + + i2c8: i2c@480 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x480 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c9_default>; + status = "disabled"; + }; + + i2c9: i2c@500 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x500 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c10_default>; + status = "disabled"; + }; + + i2c10: i2c@580 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x580 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c11_default>; + status = "disabled"; + }; + + i2c11: i2c@600 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x600 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c12_default>; + status = "disabled"; + }; + + i2c12: i2c@680 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x680 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c13_default>; + status = "disabled"; + }; + + i2c13: i2c@700 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x700 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c14_default>; + status = "disabled"; + }; + + i2c14: i2c@780 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x780 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c15_default>; + status = "disabled"; + }; + + i2c15: i2c@800 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x800 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c16_default>; + status = "disabled"; + }; }; fsim0: fsi@1e79b000 { @@ -870,229 +1094,3 @@ fsim1: fsi@1e79b100 { }; #include "aspeed-g6-pinctrl.dtsi" - -&i2c { - i2c0: i2c@80 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x80 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_default>; - status = "disabled"; - }; - - i2c1: i2c@100 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x100 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2_default>; - status = "disabled"; - }; - - i2c2: i2c@180 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x180 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3_default>; - status = "disabled"; - }; - - i2c3: i2c@200 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x200 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4_default>; - status = "disabled"; - }; - - i2c4: i2c@280 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x280 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c5_default>; - status = "disabled"; - }; - - i2c5: i2c@300 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x300 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c6_default>; - status = "disabled"; - }; - - i2c6: i2c@380 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x380 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c7_default>; - status = "disabled"; - }; - - i2c7: i2c@400 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x400 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c8_default>; - status = "disabled"; - }; - - i2c8: i2c@480 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x480 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c9_default>; - status = "disabled"; - }; - - i2c9: i2c@500 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x500 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c10_default>; - status = "disabled"; - }; - - i2c10: i2c@580 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x580 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c11_default>; - status = "disabled"; - }; - - i2c11: i2c@600 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x600 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c12_default>; - status = "disabled"; - }; - - i2c12: i2c@680 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x680 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c13_default>; - status = "disabled"; - }; - - i2c13: i2c@700 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x700 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c14_default>; - status = "disabled"; - }; - - i2c14: i2c@780 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x780 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c15_default>; - status = "disabled"; - }; - - i2c15: i2c@800 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x800 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c16_default>; - status = "disabled"; - }; -}; From 91b9aed7381c898758d70fac5aaa4bfa6173761a Mon Sep 17 00:00:00 2001 From: Dawid Glazik Date: Fri, 24 Apr 2026 22:21:01 +0200 Subject: [PATCH 325/665] ARM: dts: aspeed-g6: Add nodes for i3c controllers Add the i3c controller devices to the ast2600 g6 common dts. We add all 6 busses to the common g6 definition, but leave disabled through the status property, to be enabled per-platform. Suggested-by: Jeremy Kerr Signed-off-by: Dawid Glazik Link: https://patch.msgid.link/7a94a5f4cf84c11c7fba7485e666ecbaddfbe5cf.1777058942.git.dawid.glazik@linux.intel.com Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 91 +++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi index f5641128614f..51a6a4157f1b 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -1066,6 +1066,97 @@ i2c15: i2c@800 { }; }; + bus@1e7a0000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1e7a0000 0x8000>; + + i3c_global: syscon@0 { + compatible = "aspeed,ast2600-i3c-global", "syscon"; + reg = <0x0 0x1000>; + resets = <&syscon ASPEED_RESET_I3C_DMA>; + }; + + i3c0: i3c@2000 { + compatible = "aspeed,ast2600-i3c"; + reg = <0x2000 0x1000>; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&syscon ASPEED_CLK_GATE_I3C0CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i3c1_default>; + interrupts = ; + aspeed,global-regs = <&i3c_global 0>; + status = "disabled"; + }; + + i3c1: i3c@3000 { + compatible = "aspeed,ast2600-i3c"; + reg = <0x3000 0x1000>; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&syscon ASPEED_CLK_GATE_I3C1CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i3c2_default>; + interrupts = ; + aspeed,global-regs = <&i3c_global 1>; + status = "disabled"; + }; + + i3c2: i3c@4000 { + compatible = "aspeed,ast2600-i3c"; + reg = <0x4000 0x1000>; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&syscon ASPEED_CLK_GATE_I3C2CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i3c3_default>; + interrupts = ; + aspeed,global-regs = <&i3c_global 2>; + status = "disabled"; + }; + + i3c3: i3c@5000 { + compatible = "aspeed,ast2600-i3c"; + reg = <0x5000 0x1000>; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&syscon ASPEED_CLK_GATE_I3C3CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i3c4_default>; + interrupts = ; + aspeed,global-regs = <&i3c_global 3>; + status = "disabled"; + }; + + i3c4: i3c@6000 { + compatible = "aspeed,ast2600-i3c"; + reg = <0x6000 0x1000>; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&syscon ASPEED_CLK_GATE_I3C4CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i3c5_default>; + interrupts = ; + aspeed,global-regs = <&i3c_global 4>; + status = "disabled"; + }; + + i3c5: i3c@7000 { + compatible = "aspeed,ast2600-i3c"; + reg = <0x7000 0x1000>; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&syscon ASPEED_CLK_GATE_I3C5CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i3c6_default>; + interrupts = ; + aspeed,global-regs = <&i3c_global 5>; + status = "disabled"; + }; + }; + fsim0: fsi@1e79b000 { #interrupt-cells = <1>; compatible = "aspeed,ast2600-fsi-master"; From 79fb6e46a92003b9aed5391218e1e27b12147b94 Mon Sep 17 00:00:00 2001 From: Colin Huang Date: Mon, 11 May 2026 17:47:56 +0800 Subject: [PATCH 326/665] ARM: dts: aspeed: anacapa: Add JTAG CPLD TRST pin to SGPIO map Add JTAG_CPLD_TRST_R_N to the sgpiom0 pin name table on Facebook Anacapa BMC. This exposes the CPLD JTAG TRST signal through SGPIO, allowing proper JTAG reset control during debug. [arj: Minor tidying of commit message formatting] Signed-off-by: Colin Huang Link: https://patch.msgid.link/20260511-add-jtag-trst-pin-v1-1-b0be2f7b2da5@gmail.com Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts index 2cb7bd128d24..9a43e0c87257 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts @@ -882,7 +882,7 @@ &sgpiom0 { /* C0-C7 line 32-47 */ "RSVD_RMC_GPIO3", "", "", "", "", "", "", "", - "LEAK_DETECT_RMC_N", "", "", "", + "LEAK_DETECT_RMC_N", "JTAG_CPLD_TRST_R_N", "", "", "", "", "", "", /* D0-D7 line 48-63 */ From ae326783b7777b87d1722c4a9d280b6e64b37815 Mon Sep 17 00:00:00 2001 From: Ender Hsieh Date: Tue, 5 May 2026 14:05:41 +0900 Subject: [PATCH 327/665] ARM: dts: aspeed: msx4: enable BMC networking via MAC0 Add &mac0, &mdio3, and the ethphy3 PHY node to enable BMC networking on the AST2600-based NVIDIA MSX4 board. The PHY is attached to MDIO3 at address 2 and uses RGMII with PHY-internal delays. These nodes were intentionally omitted in commit f28674fab34f ("ARM: dts: aspeed: Add NVIDIA MSX4 HPM") at Andrew Lunn's request, pending clarification of the RGMII delay handling. Following his guidance on linux-aspeed, the bootloader has been modified to stop enabling MAC clock delays on the SoC side, so phy-mode = "rgmii-id" correctly results in the PHY adding the required ~2ns delay without any double-delay from the MAC controller. The corresponding U-Boot change has been submitted to openbmc/u-boot. Link: https://patch.msgid.link/eac09481-0ba1-4ac2-ad8c-d859822ff0d5@lunn.ch Link: https://patch.msgid.link/20260504044702.2613879-1-andhsieh@nvidia.com Cc: Andrew Lunn Cc: Marc Olberding Signed-off-by: Ender Hsieh Signed-off-by: Andrew Jeffery --- .../dts/aspeed/aspeed-bmc-nvidia-msx4-bmc.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-msx4-bmc.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-msx4-bmc.dts index a12d4164de4a..29f56176e2ca 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-msx4-bmc.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-msx4-bmc.dts @@ -208,6 +208,21 @@ &lpc_reset { status = "okay"; }; +&mac0 { + phy-mode = "rgmii-id"; + phy-handle = <ðphy3>; + status = "okay"; +}; + +&mdio3 { + status = "okay"; + + ethphy3: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; +}; + &rtc { status = "okay"; }; From 95937cbb6d51e0c6f8ac937bd043fb3b442391ec Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 14 May 2026 18:12:49 +0800 Subject: [PATCH 328/665] arm64: dts: mediatek: mt8192-asurada: Fix SPI-NOR flash compatible For JEDEC compatible SPI NOR chips, there should be a single generic "jedec,spi-nor" compatible. Drop the model-specific compatible from the flash node. Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 15660f6c8fa5..f71880940cd0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -556,7 +556,7 @@ &nor_flash { assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D8>; flash@0 { - compatible = "winbond,w25q64jwm", "jedec,spi-nor"; + compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <52000000>; spi-rx-bus-width = <2>; From c42235145c52955ab20fcb648bb8c7818f58282b Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 14 May 2026 18:12:50 +0800 Subject: [PATCH 329/665] arm64: dts: mediatek: mt8192-asurada: Add (BT|WIFI)_KILL_1V8_L GPIO line names GPIO lines 59 and 61 are named BT_KILL_1V8_L and WIFI_KILL_1V8_L in the hardware design. Add them to the gpio-line-names property to make the names available to users and developers. Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index f71880940cd0..40d34b16dc80 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -652,9 +652,9 @@ &pio { "SD_DATA1", "", "", + "BT_KILL_1V8_L", "", - "", - "", + "WIFI_KILL_1V8_L", "", "PCIE_WAKE_ODL", "PCIE_RST_L", From 2066ac078402301d9aa50026dee017182d316eac Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 14 May 2026 18:12:51 +0800 Subject: [PATCH 330/665] arm64: dts: mediatek: mt8195-cherry: Fix names for EC controlled regulators The names currently given to the EC controlled regulators do not match what is used in the hardware design. Fix the names and the labels. Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index ca2bb367ee68..538c46ada32b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -717,8 +717,8 @@ &mmc1 { pinctrl-1 = <&mmc1_pins_default>; sd-uhs-sdr50; sd-uhs-sdr104; - vmmc-supply = <&mt_pmic_vmch_ldo_reg>; - vqmmc-supply = <&mt_pmic_vmc_ldo_reg>; + vmmc-supply = <&pp3000_sd>; + vqmmc-supply = <&pp3000_vmc_pmu>; }; &mt6359codec { @@ -1436,19 +1436,19 @@ i2c_tunnel: i2c-tunnel { #size-cells = <0>; }; - mt_pmic_vmc_ldo_reg: regulator@0 { + pp3000_vmc_pmu: regulator@0 { compatible = "google,cros-ec-regulator"; reg = <0>; - regulator-name = "mt_pmic_vmc_ldo"; + regulator-name = "pp3000_vmc_pmu"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <3600000>; vin-supply = <&pp4200_z2>; }; - mt_pmic_vmch_ldo_reg: regulator@1 { + pp3000_sd: regulator@1 { compatible = "google,cros-ec-regulator"; reg = <1>; - regulator-name = "mt_pmic_vmch_ldo"; + regulator-name = "pp3000_sd"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3600000>; vin-supply = <&pp4200_z2>; From 559b8b1524760ad8dc18d52c4415d40ee24d02fc Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 14 May 2026 18:12:52 +0800 Subject: [PATCH 331/665] arm64: dts: mediatek: mt8195-cherry: Sort top level nodes correctly The thermistor device nodes were added before the vbus regulator and reserved memory nodes, when they should be after them, based on alphabetical order of the device node _name_. Move them to the correct position. No functional changes intended. Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8195-cherry.dtsi | 94 +++++++++---------- 1 file changed, 47 insertions(+), 47 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index 538c46ada32b..ef7afc436aef 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -149,6 +149,53 @@ ppvar_sys: regulator-ppvar-sys { regulator-boot-on; }; + usb_vbus: regulator-5v0-usb-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb-vbus"; + enable-active-high; + regulator-always-on; + vin-supply = <&pp5000_s5>; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scp_mem: memory@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x2900000>; + no-map; + }; + + adsp_mem: memory@60000000 { + compatible = "shared-dma-pool"; + reg = <0 0x60000000 0 0xd80000>; + no-map; + }; + + afe_mem: memory@60d80000 { + compatible = "shared-dma-pool"; + reg = <0 0x60d80000 0 0x100000>; + no-map; + }; + + adsp_device_mem: memory@60e80000 { + compatible = "shared-dma-pool"; + reg = <0 0x60e80000 0 0x280000>; + no-map; + }; + }; + + spk_amplifier: rt1019p { + compatible = "realtek,rt1019p"; + label = "rt1019p"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&rt1019p_pins_default>; + sdb-gpios = <&pio 100 GPIO_ACTIVE_HIGH>; + }; + /* Murata NCP03WF104F05RL */ tboard_thermistor1: thermal-sensor-t1 { compatible = "generic-adc-thermal"; @@ -219,53 +266,6 @@ tboard_thermistor2: thermal-sensor-t2 { 120000 51 125000 44>; }; - - usb_vbus: regulator-5v0-usb-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb-vbus"; - enable-active-high; - regulator-always-on; - vin-supply = <&pp5000_s5>; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - scp_mem: memory@50000000 { - compatible = "shared-dma-pool"; - reg = <0 0x50000000 0 0x2900000>; - no-map; - }; - - adsp_mem: memory@60000000 { - compatible = "shared-dma-pool"; - reg = <0 0x60000000 0 0xd80000>; - no-map; - }; - - afe_mem: memory@60d80000 { - compatible = "shared-dma-pool"; - reg = <0 0x60d80000 0 0x100000>; - no-map; - }; - - adsp_device_mem: memory@60e80000 { - compatible = "shared-dma-pool"; - reg = <0 0x60e80000 0 0x280000>; - no-map; - }; - }; - - spk_amplifier: rt1019p { - compatible = "realtek,rt1019p"; - label = "rt1019p"; - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&rt1019p_pins_default>; - sdb-gpios = <&pio 100 GPIO_ACTIVE_HIGH>; - }; }; &adsp { From e4768ff3c6e2bc939938be5d51a756856f7b9dd2 Mon Sep 17 00:00:00 2001 From: Rex Fu Date: Fri, 17 Apr 2026 14:41:49 +0800 Subject: [PATCH 332/665] ARM: dts: aspeed: anacapa: Add interrupt properties for PDB PCA9555 Add interrupt-parent and interrupts properties to the PDB PCA9555 nodes in the anacapa DTS. [arj: Tweak commit subject capitalisation] Signed-off-by: Rex Fu Link: https://patch.msgid.link/20260417-anacapa-pca9555-irq-v1-1-9a6d28b1b656@amd.com Signed-off-by: Andrew Jeffery --- .../boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts index 9a43e0c87257..58d0651124e6 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts @@ -481,6 +481,9 @@ gpio@22 { gpio-controller; #gpio-cells = <2>; + interrupt-parent = <&sgpiom0>; + interrupts = <174 IRQ_TYPE_LEVEL_LOW>; + gpio-line-names = "RPDB_FAN_FULL_SPEED_R_N", "RPDB_I2C_TEMP75_U8_ALERT_R_N", "RPDB_I2C_TMP432_U29_ALERT_R_N", "RPDB_GLOBAL_WP", @@ -500,6 +503,9 @@ gpio@24 { gpio-controller; #gpio-cells = <2>; + interrupt-parent = <&sgpiom0>; + interrupts = <174 IRQ_TYPE_LEVEL_LOW>; + gpio-line-names = "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", "RPDB_PWRGD_P50V_HSC4_SYS_R", @@ -529,6 +535,9 @@ gpio@22 { gpio-controller; #gpio-cells = <2>; + interrupt-parent = <&sgpiom0>; + interrupts = <174 IRQ_TYPE_LEVEL_LOW>; + gpio-line-names = "LPDB_FAN_FULL_SPEED_R_N","LPDB_I2C_TEMP75_U8_ALERT_R_N", "LPDB_I2C_TMP432_U29_ALERT_R_N","LPDB_GLOBAL_WP", @@ -546,6 +555,9 @@ gpio@24 { gpio-controller; #gpio-cells = <2>; + interrupt-parent = <&sgpiom0>; + interrupts = <174 IRQ_TYPE_LEVEL_LOW>; + gpio-line-names = "LPDB_P50V_FAN1_R2_PG","LPDB_P50V_FAN2_R2_PG", "LPDB_P50V_FAN3_R2_PG","LPDB_P50V_FAN4_R2_PG", From 9e09b7eddd3a6cdec4d071de9203a135260e0708 Mon Sep 17 00:00:00 2001 From: Daniel Hsu Date: Tue, 31 Mar 2026 20:07:34 +0800 Subject: [PATCH 333/665] ARM: dts: aspeed: yosemite5: Add MP5998 power monitor Add an MP5998 power monitor used to monitor the power consumption of the Paddle_P12V_HSC rail on the Yosemite5 paddle board. [arj: Remove changelog from commit message] Signed-off-by: Daniel Hsu Link: https://patch.msgid.link/20260331120734.39260-1-Daniel-Hsu@quantatw.com Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite5.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite5.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite5.dts index 2486981f3d6b..6287f80d70d9 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite5.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite5.dts @@ -422,6 +422,11 @@ power-sensor@45 { shunt-resistor = <1000>; }; + power-monitor@46 { + compatible = "mps,mp5998"; + reg = <0x46>; + }; + power-monitor@47 { compatible = "ti,tps25990"; reg = <0x47>; From 6cf976b2728f2494215c51c7339dd50b154125ce Mon Sep 17 00:00:00 2001 From: Billy Tsai Date: Thu, 26 Mar 2026 18:29:22 +0800 Subject: [PATCH 334/665] ARM: dts: aspeed: g6: Add PWM/Tach controller node Introduce a device tree node for the AST2600 PWM/Tach controller. Describe register range, clock, reset, and cell configuration. Set status to "disabled" by default. Prepares for enabling PWM and tachometer support on platforms utilizing this SoC. Signed-off-by: Billy Tsai Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi index 51a6a4157f1b..56bb3b0444f7 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -102,6 +102,15 @@ ahbc: bus@1e600000 { reg = <0x1e600000 0x100>; }; + pwm_tach: pwm-tach-controller@1e610000 { + compatible = "aspeed,ast2600-pwm-tach"; + reg = <0x1e610000 0x100>; + clocks = <&syscon ASPEED_CLK_AHB>; + resets = <&syscon ASPEED_RESET_PWM>; + #pwm-cells = <3>; + status = "disabled"; + }; + fmc: spi@1e620000 { reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>; #address-cells = <1>; From eae82b6e8c2399892e145195cae9aaa0b960fdaf Mon Sep 17 00:00:00 2001 From: Joey Lu Date: Mon, 23 Mar 2026 18:17:55 +0800 Subject: [PATCH 335/665] arm64: dts: nuvoton: Add Ethernet nodes Add GMAC nodes for our MA35D1 development boards: two RGMII interfaces for SOM board, and one RGMII and one RMII interface for IoT board. Signed-off-by: Joey Lu Signed-off-by: Andrew Jeffery --- .../boot/dts/nuvoton/ma35d1-iot-512m.dts | 25 +++++++++ .../boot/dts/nuvoton/ma35d1-som-256m.dts | 24 +++++++++ arch/arm64/boot/dts/nuvoton/ma35d1.dtsi | 52 +++++++++++++++++++ 3 files changed, 101 insertions(+) diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts index 9482bec1aa57..78534d613486 100644 --- a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts @@ -18,6 +18,8 @@ aliases { serial12 = &uart12; serial13 = &uart13; serial14 = &uart14; + ethernet0 = &gmac0; + ethernet1 = &gmac1; }; chosen { @@ -126,3 +128,26 @@ &uart14 { pinctrl-0 = <&pinctrl_uart14>; status = "okay"; }; + +&gmac0 { + status = "okay"; + phy-handle = <ð_phy0>; +}; + +&mdio0 { + eth_phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rmii"; + phy-handle = <ð_phy1>; +}; + +&mdio1 { + eth_phy1: ethernet-phy@1 { + reg = <1>; + }; +}; diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts index f6f20a17e501..a029b660e8dc 100644 --- a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts @@ -18,6 +18,8 @@ aliases { serial12 = &uart12; serial14 = &uart14; serial16 = &uart16; + ethernet0 = &gmac0; + ethernet1 = &gmac1; }; chosen { @@ -129,3 +131,25 @@ &uart16 { pinctrl-0 = <&pinctrl_uart16>; status = "okay"; }; + +&gmac0 { + status = "okay"; + phy-handle = <ð_phy0>; +}; + +&mdio0 { + eth_phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&gmac1 { + status = "okay"; + phy-handle = <ð_phy1>; +}; + +&mdio1 { + eth_phy1: ethernet-phy@1 { + reg = <1>; + }; +}; diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi index e51b98f5bdce..7228ad4735b5 100644 --- a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi +++ b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi @@ -379,5 +379,57 @@ uart16: serial@40880000 { clocks = <&clk UART16_GATE>; status = "disabled"; }; + + gmac0: ethernet@40120000 { + compatible = "nuvoton,ma35d1-dwmac", "snps,dwmac-3.70a"; + reg = <0x0 0x40120000 0x0 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&clk EMAC0_GATE>, <&clk EPLL_DIV8>; + clock-names = "stmmaceth", "ptp_ref"; + + nuvoton,sys = <&sys 0>; + resets = <&sys MA35D1_RESET_GMAC0>; + reset-names = "stmmaceth"; + snps,multicast-filter-bins = <0>; + snps,perfect-filter-entries = <8>; + rx-fifo-depth = <4096>; + tx-fifo-depth = <2048>; + + phy-mode = "rgmii-id"; + status = "disabled"; + + mdio0: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + gmac1: ethernet@40130000 { + compatible = "nuvoton,ma35d1-dwmac", "snps,dwmac-3.70a"; + reg = <0x0 0x40130000 0x0 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&clk EMAC1_GATE>, <&clk EPLL_DIV8>; + clock-names = "stmmaceth", "ptp_ref"; + + nuvoton,sys = <&sys 1>; + resets = <&sys MA35D1_RESET_GMAC1>; + reset-names = "stmmaceth"; + snps,multicast-filter-bins = <0>; + snps,perfect-filter-entries = <8>; + rx-fifo-depth = <4096>; + tx-fifo-depth = <2048>; + + phy-mode = "rgmii-id"; + status = "disabled"; + + mdio1: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; }; From a8af0f311dceec20eb359aded2d30743549af9a2 Mon Sep 17 00:00:00 2001 From: Potin Lai Date: Mon, 23 Mar 2026 20:41:05 +0800 Subject: [PATCH 336/665] dt-bindings: arm: aspeed: add Meta SanMiguel BMC Add Meta (Facebook) SanMiguel BMC board compatible. Acked-by: Conor Dooley Signed-off-by: Potin Lai Signed-off-by: Andrew Jeffery --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index 8ec7a3e74a21..b553e3415ce9 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -95,6 +95,7 @@ properties: - facebook,greatlakes-bmc - facebook,harma-bmc - facebook,minerva-cmc + - facebook,sanmiguel-bmc - facebook,santabarbara-bmc - facebook,yosemite4-bmc - facebook,yosemite5-bmc From 68b44988df9a5c25c1dbd92e898b25c4b19d924d Mon Sep 17 00:00:00 2001 From: Potin Lai Date: Mon, 23 Mar 2026 20:41:06 +0800 Subject: [PATCH 337/665] ARM: dts: aspeed: Add Meta SanMiguel BMC Add linux device tree entry for Meta (Facebook) SanMiguel compute-tray BMC using AT2620 SoC. Reviewed-by: Andrew Lunn Signed-off-by: Potin Lai Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/Makefile | 1 + .../aspeed/aspeed-bmc-facebook-sanmiguel.dts | 668 ++++++++++++++++++ 2 files changed, 669 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile index 767f7c7652d5..7d70f08e436c 100644 --- a/arch/arm/boot/dts/aspeed/Makefile +++ b/arch/arm/boot/dts/aspeed/Makefile @@ -34,6 +34,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-facebook-harma.dtb \ aspeed-bmc-facebook-minerva.dtb \ aspeed-bmc-facebook-minipack.dtb \ + aspeed-bmc-facebook-sanmiguel.dtb \ aspeed-bmc-facebook-santabarbara.dtb \ aspeed-bmc-facebook-tiogapass.dtb \ aspeed-bmc-facebook-wedge40.dtb \ diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts new file mode 100644 index 000000000000..74c8c1772109 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts @@ -0,0 +1,668 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2025 Facebook Inc. + +/dts-v1/; +#include "aspeed-g6.dtsi" +#include +#include +#include +#include +#include +#include + +/ { + model = "Facebook SanMiguel BMC"; + compatible = "facebook,sanmiguel-bmc", "aspeed,ast2600"; + + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + i2c16 = &imux16; + i2c17 = &imux17; + i2c18 = &imux18; + i2c19 = &imux19; + }; + + chosen { + stdout-path = "serial4:57600n8"; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>; + }; + + leds-fio { + compatible = "gpio-leds"; + led-0 { + label = "power_blue"; + gpios = <&fio_ioexp 4 GPIO_ACTIVE_HIGH>; + }; + led-1 { + label = "power_amber"; + gpios = <&fio_ioexp 5 GPIO_ACTIVE_LOW>; + }; + led-2 { + label = "id_blue"; + gpios = <&fio_ioexp 6 GPIO_ACTIVE_HIGH>; + }; + led-3 { + label = "id_amber"; + gpios = <&fio_ioexp 7 GPIO_ACTIVE_LOW>; + }; + }; + + leds-smm { + compatible = "gpio-leds"; + led-0 { + label = "bmc_heartbeat_amber"; + gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + spi2_gpio: spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + sck-gpios = <&gpio0 ASPEED_GPIO(X, 3) GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio0 ASPEED_GPIO(X, 4) GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio0 ASPEED_GPIO(X, 5) GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio0 ASPEED_GPIO(X, 2) GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + spi-max-frequency = <33000000>; + reg = <0>; + }; + }; + + standby_power_regulator: standby-power-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 ASPEED_GPIO(M, 3) GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "standby_power"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + + status = "okay"; + }; +}; + +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default>; + aspeed,int-vref-microvolt = <2500000>; + + status = "okay"; +}; + +&fmc { + status = "okay"; + + flash@0 { + label = "bmc"; + spi-max-frequency = <50000000>; + m25p,fast-read; + + status = "okay"; +#include "openbmc-flash-layout-128.dtsi" + }; + + flash@1 { + label = "alt-bmc"; + spi-max-frequency = <50000000>; + m25p,fast-read; + + status = "okay"; +#include "openbmc-flash-layout-128-alt.dtsi" + }; +}; + +&gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiom4_unbiased_default + &pinctrl_gpiom5_unbiased_default + &pinctrl_gpiov4_unbiased_default + &pinctrl_gpiov7_unbiased_default>; + + gpio-line-names = + /*A0-A7*/ "", "", "", "", "", "", "", "", + /*B0-B7*/ "", "", "", "", "", "", "", "", + /*C0-C7*/ "", "", "", "", "", "", "", "", + /*D0-D7*/ "", "", "", "", "", "FPGA_PEX_RST_L", "", "", + /*E0-E7*/ "RTL8221_PHY_RST_L-O", "RTL8211_PHY_INT_L-I", "", "", + "", "", "", "MUX_SGPIO_SEL-O", + /*F0-F7*/ "", "", "", "", "", "", "", "", + /*G0-G7*/ "", "", "", "", "", "", "", "", + /*H0-H7*/ "", "", "", "", "", "", "", "", + /*I0-I7*/ "", "", "", "", + "", "QSPI2_RST_L-O", + "GLOBAL_WP_BMC-I", "BMC_DDR4_TEN-O", + /*J0-J7*/ "", "", "", "", "", "", "", "", + /*K0-K7*/ "", "", "", "", "", "", "", "", + /*L0-L7*/ "", "", "", "", "", "", "", "", + /*M0-M7*/ "USB_HUB_RST_N-O", "BMC_FRU_WP-O", + "", "HMC_STBY_POWER_EN-O", + "STBY_POWER_PG-I", "PCIE_EP_RST_L-O", "", "", + /*N0-N7*/ "", "", "", "", "", "", "", "", + /*O0-O7*/ "", "", "", "", "", "", "", "", + /*P0-P7*/ "", "", "", "", "", "", "", "", + /*Q0-Q7*/ "", "", "", "", "", "", "", "", + /*R0-R7*/ "", "SP0_AP_INTR_N-I", "", "", "", "", "", "", + /*S0-S7*/ "", "", "", "", "", "", "", "", + /*T0-T7*/ "", "", "", "", "", "", "", "", + /*U0-U7*/ "", "", "", "", "", "", "", "", + /*V0-V7*/ "", "", "", "", "PCB_TEMP_ALERT-I", "", "", "", + /*W0-W7*/ "", "", "", "", "", "", "", "CPU_RST_L-I", + /*X0-X7*/ "", "", "", "", "", "", "", "", + /*Y0-Y7*/ "", "", "", "EMMC_RST-O", "", "", "", "", + /*Z0-Z7*/ "HMC_EROT_SPI_INT_L-I", "", "", "", "", "", "", ""; +}; + +&gpio1 { + /* 36 1.8V GPIOs */ + gpio-line-names = + /*A0-A7*/ "", "", "", "", "", "", "", "", + /*B0-B7*/ "", "", "", "", + "AP_EROT_REQ-O", "EROT_AP_GNT-I", + "IO_EXPANDER_INT_L-I", "", + /*C0-C7*/ "", "", "", "", "", "", "", "", + /*D0-D7*/ "", "", "", "", "", "", "", "I2C_SSIF_ALERT_L-I", + /*E0-E7*/ "", "", "", "", "", "", "", ""; +}; + +&i2c0 { + status = "okay"; + + ssif-bmc@10 { + compatible = "ssif-bmc"; + reg = <0x10>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + hpm0_ioexp_20: gpio@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = ; + vcc-supply = <&standby_power_regulator>; + + gpio-line-names = + "B0_M0_SHDN_FORCE_L-O", + "B0_M0_STBY_POWER_PG-I", + "B0_M0_THERM_OVERT_L-I", + "B0_M0_THERM_WARN_L-I", + "B0_M0_GLOBAL_WP-O", + "B0_M0_USB_HUB0_RST_L-O", + "B0_M0_PRE_SYS_RST_L-O", + "B0_M0_LEAK_DETECT_ALERT_L-I", + "B0_M0_RUN_POWER_EN-O", + "B0_M0_RUN_POWER_PG-I", + "B0_M0_CPU_CHIPTHROT_L-O", + "B0_M0_SHDN_REQ_L-O", + "B0_M0_CPU_SHDN_OK_L-I", + "B0_M0_CPLD_READY-I", + "B0_M0_PWR_BRAKE_L-O", + "B0_M0_PWR_BRAKE_STATUS_L-I"; + }; + + hpm0_ioexp_21: gpio@21 { + compatible = "nxp,pca9555"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = ; + vcc-supply = <&standby_power_regulator>; + + gpio-line-names = + "B0_M0_I2C_BUS_MUX_RESET_L-O", + "B0_M0_HPM_MCU_OK-I", + "B0_M0_CPU_L0_RST_IND_L-O", + "B0_M0_C0_SOCAMM_DAC_SEL0-O", + "B0_M0_C1_SOCAMM_DAC_SEL1-O", + "B0_M0_C0_SOCAMM_I2C_SEL_R-O", + "B0_M0_C1_SOCAMM_I2C_SEL_R-O", + "B0_M0_EEPROM_POWER_DISABLE-O", + "B0_M0_L0L1_RST_L-I", + "B0_M0_L2_RST_L-I", + "B0_M0_BRD_ID_0-I", + "B0_M0_BRD_ID_1-I", + "B0_M0_BMC_LEAK_TEST_L-O", + "B0_M0_MCU_BMC_ALERT_L-I", + "B0_M0_CPU_BOOT_COMPLETE_3V3-I", + "B0_M0_BMC_TO_GPU_MCU_I2C_EN-O"; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; + + smm_ioexp_20: gpio@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = ; + + gpio-line-names = + "HMC_RST_R_L-O", "HMC_RECOVERY_R-O", + "HMC_SPI_MUX_R_SEL-O", "GLOBAL_WP-O", + "HMC_READY-I", "HMC_PRSNT_R-I", + "BMC_SELF_PWR_CYCLE-O", "EEDO_LED2-O", + "PWR_LED_L-O", "PWR_BTN_L-I", + "UID_LED_L-O", "UID_BTN_L-I", + "FAULT_LED_L-O", "USB2_HUB_RST_L-O", + "USB2_BMC_HUB2_RST_L-O", "WARN_LED_L-O"; + }; + + smm_ioexp_21: gpio@21 { + compatible = "nxp,pca9555"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = ; + + gpio-line-names = + "BMC_HMC_MUX_SEL-O", "BMC_TPM_MUX_SEL-O", + "BMC_USB2_MUX_SEL-O", "HMC_PGOOD_3V3-I", + "", "HDR_SPI_PRSNT_L-I", + "SW_NRESET_R_L-O", "MUX_I2C_ESPI_SEL-O", + "I2C_BUS_MUX_RESET_L-O", "USB_MUX_EN-O", + "PDB_TRAY_RST-O", "USB_PWR_EN-O", + "RTC_CLR_L-O", "I2C_RTC_ALERT_L-I", + "X86_TPM_RST_SEL_L-O", "BMC_MUX_PI3DP_SEL-O"; + }; + + smm_temp: temperature-sensor@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + smm_fru: eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + + rtc@6f { + compatible = "nuvoton,nct3018y"; + reg = <0x6f>; + }; +}; + +&i2c6 { + status = "okay"; + + hmc_ioexp: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "", "", "HMC_EROT_FATAL_ERROR_L-I", "", + "", "HMC_EROT_RECOVERY_L-O", "HMC_EROT_RESET_L-O", ""; + }; + + i2c-mux@70 { + compatible = "nxp,pca9546"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux16: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux17: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux18: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux19: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c7 { + status = "okay"; + + hpm1_ioexp_20: gpio@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = ; + vcc-supply = <&standby_power_regulator>; + + gpio-line-names = + "B1_M0_SHDN_FORCE_L-O", + "B1_M0_STBY_POWER_PG-I", + "B1_M0_THERM_OVERT_L-I", + "B1_M0_THERM_WARN_L-I", + "B1_M0_GLOBAL_WP-O", + "B1_M0_USB_HUB0_RST_L-O", + "B1_M0_PRE_SYS_RST_L-O", + "B1_M0_LEAK_DETECT_ALERT_L-I", + "B1_M0_RUN_POWER_EN-O", + "B1_M0_RUN_POWER_PG-I", + "B1_M0_CPU_CHIPTHROT_L-O", + "B1_M0_SHDN_REQ_L-O", + "B1_M0_CPU_SHDN_OK_L-I", + "B1_M0_CPLD_READY-I", + "B1_M0_PWR_BRAKE_L-O", + "B1_M0_PWR_BRAKE_STATUS_L-I"; + }; + + hpm1_ioexp_21: gpio@21 { + compatible = "nxp,pca9555"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = ; + vcc-supply = <&standby_power_regulator>; + + gpio-line-names = + "B1_M0_I2C_BUS_MUX_RESET_L-O", + "B1_M0_HPM_MCU_OK-I", + "B1_M0_CPU_L0_RST_IND_L-O", + "B1_M0_C0_SOCAMM_DAC_SEL0-O", + "B1_M0_C1_SOCAMM_DAC_SEL1-O", + "B1_M0_C0_SOCAMM_I2C_SEL_R-O", + "B1_M0_C1_SOCAMM_I2C_SEL_R-O", + "B1_M0_EEPROM_POWER_DISABLE-O", + "B1_M0_L0L1_RST_L-I", + "B1_M0_L2_RST_L-I", + "B1_M0_BRD_ID_0-I", + "B1_M0_BRD_ID_1-I", + "B1_M0_BMC_LEAK_TEST_L-O", + "B1_M0_MCU_BMC_ALERT_L-I", + "B1_M0_CPU_BOOT_COMPLETE_3V3-I", + "B1_M0_BMC_TO_GPU_MCU_I2C_EN-O"; + }; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; + + pdb_mps_hsc1: power-monitor@10 { + compatible = "mps,mp5926"; + reg = <0x10>; + }; + + pdb_ti_hsc1: power-monitor@11 { + compatible = "ti,lm5066i"; + reg = <0x11>; + shunt-resistor-micro-ohms = <763>; + }; + + pdb_mps_hsc2: power-monitor@12 { + compatible = "mps,mp5926"; + reg = <0x12>; + }; + + pdb_ti_hsc2: power-monitor@13 { + compatible = "ti,lm5066i"; + reg = <0x13>; + shunt-resistor-micro-ohms = <294>; + }; + + pdb_mps_hsc3: power-monitor@14 { + compatible = "mps,mp5926"; + reg = <0x14>; + }; + + pdb_ti_hsc3: power-monitor@15 { + compatible = "ti,lm5066i"; + reg = <0x15>; + shunt-resistor-micro-ohms = <294>; + }; + + pdb_mps_hsc4: power-monitor@16 { + compatible = "mps,mp5926"; + reg = <0x16>; + }; + + pdb_ti_hsc4: power-monitor@17 { + compatible = "ti,lm5066i"; + reg = <0x17>; + shunt-resistor-micro-ohms = <381>; + }; + + pdb_ioexp_20: gpio@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = ; + + gpio-line-names = + "PDB_STRAP-I", "STBY_POWER_EN-O", "STBY_PWR_OK-I", "", + "", "MAIN_PWR_EN-O", "MAIN_PWR_OK-I", "GLOBAL_WP-O", + "PDB_PWR_BRK_L-I", "FAN_PRSNT-I", "", "", + "HSC4_S5_OR_S0_N-O", "", "", ""; + }; + + pdb_temp: temperature-sensor@4e { + compatible = "national,lm75"; + reg = <0x4e>; + }; + + pdb_fru: eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; +}; + +&i2c10 { + status = "okay"; + + scm_temp: temperature-sensor@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + scm_fru: eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; +}; + +&i2c11 { + status = "okay"; + + sw_config: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; + mctp-controller; + multi-master; + + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + smm_ext_ioexp: gpio@38 { + compatible = "nxp,pca9554"; + reg = <0x38>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SSD0_PRSNT_L-I", "E1S_PWR_EN-O", + "SSD0_PWRDIS-O", "I2C_PDB_ALERT_L-I", + "BMC_SSD0_RST_L-O", "GLOBAL_WP_E1S-O", + "12V_SSD0_PGD-I", "SSD0_LED-O"; + }; + + smm_ext_fru: eeprom@55 { + compatible = "atmel,24c128"; + reg = <0x55>; + }; +}; + +&i2c14 { + status = "okay"; + + fio_ioexp: gpio@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = ; + + gpio-line-names = + "", "", "", "", + "PWR_LED_BLUE", "PWR_LED_AMBER_R_N", + "BEEP_ID_LED_BLUE", "BEEP_ID_LED_AMBER_R_N", + "", "", "", "", + "FM_MAIN_PWREN_RMC_ISO_EN_N", "LEAK_DETECT_RMC_N", + "PWRGD_RMC_N", "SMALL_LEAK_RMC_N"; + + pwrgd-rmc-hog { + gpio-hog; + gpios = <14 GPIO_ACTIVE_LOW>; + output-low; + }; + }; + + fio_fru: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; +}; + +&i2c15 { + status = "okay"; +}; + +&mdio0 { + status = "okay"; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + +&mac0 { + pinctrl-names = "default"; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + pinctrl-0 = <&pinctrl_rgmii1_default>; + + status = "okay"; +}; + +&pinctrl { + pinctrl_gpiom4_unbiased_default: gpiom4 { + pins = "B12"; + bias-disable; + }; + pinctrl_gpiom5_unbiased_default: gpiom5 { + pins = "C12"; + bias-disable; + }; + pinctrl_gpiov4_unbiased_default: gpiov4 { + pins = "AE15"; + bias-disable; + }; + pinctrl_gpiov7_unbiased_default: gpiov7 { + pins = "AF15"; + bias-disable; + }; +}; + +&uart1 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&uart_routing { + status = "okay"; +}; + +&wdt1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; + aspeed,reset-type = "soc"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + aspeed,ext-pulse-duration = <256>; + + status = "okay"; +}; From f2f38921c755c2be0599b0a76264e69a1b2e8873 Mon Sep 17 00:00:00 2001 From: Rex Fu Date: Mon, 18 May 2026 18:00:40 +0800 Subject: [PATCH 338/665] ARM: dts: aspeed: anacapa: Correct SGPIO names for monitoring Update several Anacapa SGPIO line names to match the existing platform hardware design and the signal names consumed by userspace monitoring. The previous names did not match the actual Anacapa SGPIO usage. Some lines were named as CPU or CPU power-good signals, but they are wired and used on Anacapa for EDSFF presence, EDSFF power-good, boot EDSFF presence, and thermal-trip assertion monitoring. Correct the mappings as follows: PWRGD_PVDDCR_SOC_P0 -> L_PRSNT_EDSFF0_N PWRGD_PVDDIO_P0 -> L_PRSNT_EDSFF1_N PWRGD_PVDDIO_MEM_S3_P0 -> R_PRSNT_EDSFF2_N PWRGD_CHMP_CPU0_FPGA -> R_PRSNT_EDSFF3_N PWRGD_CHIL_CPU0_FPGA -> HPM_EDSFF_PG EAM2_CPU_MOD_PWR_GD_R -> PRSNT_EDSFF_BOOT_N CPU0_SP7R1 -> L_EDSFF0_PG CPU0_SP7R2 -> L_EDSFF1_PG CPU0_SP7R3 -> R_EDSFF2_PG CPU0_SP7R4 -> R_EDSFF3_PG HPM_AMC_THERMTRIP_R_L -> AMC_THERMTRIP_ASSERT FM_CPU0_THERMTRIP_N -> CPU_THERMTRIP_ASSERT The left-side EDSFF slots are numbered as EDSFF0 and EDSFF1 to match the platform slot numbering used by userspace. The thermtrip names are also updated to describe the asserted condition monitored by userspace instead of the raw active-low signal names. This is a naming correction for the existing Anacapa hardware design. There is no new board revision or underlying hardware change involved. [arj: Tweak capitalisation in commit subject, rewrap paragraph] Signed-off-by: Rex Fu Link: https://patch.msgid.link/20260518-anacapa-sgpio-edsff-thermtrip-v2-1-e43b1847b2dc@amd.com Signed-off-by: Andrew Jeffery --- .../aspeed/aspeed-bmc-facebook-anacapa.dts | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts index 58d0651124e6..1fddf3a5d138 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts @@ -920,11 +920,11 @@ &sgpiom0 { "", "", "", "", /* G0-G7 line 96-111 */ - "PWRGD_PVDDCR_SOC_P0", "", - "PWRGD_PVDDIO_P0", "", - "PWRGD_PVDDIO_MEM_S3_P0", "", - "PWRGD_CHMP_CPU0_FPGA", "", - "PWRGD_CHIL_CPU0_FPGA", "", + "L_PRSNT_EDSFF0_N", "", + "L_PRSNT_EDSFF1_N", "", + "R_PRSNT_EDSFF2_N", "", + "R_PRSNT_EDSFF3_N", "", + "HPM_EDSFF_PG", "", "PWRGD_CHEH_CPU0_FPGA", "", "PWRGD_CHAD_CPU0_FPGA", "FM_BMC_READY_PLD", "", "", @@ -946,7 +946,7 @@ &sgpiom0 { "EAM3_BRD_PRSNT_R_L", "", "EAM0_CPU_MOD_PWR_GD_R", "", "EAM1_CPU_MOD_PWR_GD_R", "", - "EAM2_CPU_MOD_PWR_GD_R", "", + "PRSNT_EDSFF_BOOT_N", "", "EAM3_CPU_MOD_PWR_GD_R", "", /* J0-J7 line 144-159 */ @@ -969,8 +969,8 @@ &sgpiom0 { "PDB_ALERT_R_N", "", /* L0-L7 line 176-191 */ - "CPU0_SP7R1", "", "CPU0_SP7R2", "", - "CPU0_SP7R3", "", "CPU0_SP7R4", "", + "L_EDSFF0_PG", "", "L_EDSFF1_PG", "", + "R_EDSFF2_PG", "", "R_EDSFF3_PG", "", "CPU0_CORETYPE0", "", "CPU0_CORETYPE1", "", "CPU0_CORETYPE2", "", "FM_BIOS_POST_CMPLT_R_N", "", @@ -996,8 +996,8 @@ &sgpiom0 { "HPM_PWR_FAIL", "Port80_b0", "FM_DIMM_IP_FAIL", "Port80_b1", "FM_DIMM_AH_FAIL", "Port80_b2", - "HPM_AMC_THERMTRIP_R_L", "Port80_b3", - "FM_CPU0_THERMTRIP_N", "Port80_b4", + "AMC_THERMTRIP_ASSERT", "Port80_b3", + "CPU_THERMTRIP_ASSERT", "Port80_b4", "PVDDCR_SOC_P0_OCP_L", "Port80_b5", "CPLD_SGPIO_RDY", "Port80_b6", "", "Port80_b7", From 7ebbcbbee79e66da142dad678ee4b17e730e2b1f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 11 Apr 2026 15:03:24 +0200 Subject: [PATCH 339/665] ARM: dts: stm32: Enable PHY SSC on DH STM32MP13xx DHCOR DHSBC board Add realtek,rxc-ssc-enable and realtek,sysclk-ssc-enable to both PHY DT nodes to enable PHY Spread Spectrum on RXC and SYSCLK, CLKOUT is disabled and therefore does not need SSC enabled. Signed-off-by: Marek Vasut Link: https://lore.kernel.org/r/20260411130355.19670-1-marex@nabladev.com Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts index 9902849ed040..70d85af46735 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts @@ -97,6 +97,8 @@ ethphy1: ethernet-phy@1 { interrupts = <12 IRQ_TYPE_LEVEL_LOW>; reg = <1>; realtek,clkout-disable; + realtek,rxc-ssc-enable; + realtek,sysclk-ssc-enable; reset-assert-us = <15000>; reset-deassert-us = <55000>; reset-gpios = <&gpioa 11 GPIO_ACTIVE_LOW>; @@ -146,6 +148,8 @@ ethphy2: ethernet-phy@1 { interrupts = <15 IRQ_TYPE_LEVEL_LOW>; reg = <1>; realtek,clkout-disable; + realtek,rxc-ssc-enable; + realtek,sysclk-ssc-enable; reset-assert-us = <15000>; reset-deassert-us = <55000>; reset-gpios = <&gpiog 8 GPIO_ACTIVE_LOW>; From 9c2be60e829e6661ebfaccef7fd6381387789265 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 20 Apr 2026 22:46:48 +0200 Subject: [PATCH 340/665] ARM: dts: stm32: add board pin documentation stm32mp135f-dk MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relate the devices defined in the device tree to the SoC ports and pins and labels available on the board. Signed-off-by: Uwe Kleine-König Link: https://lore.kernel.org/r/20260420204647.1713944-2-u.kleine-koenig@baylibre.com Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp135f-dk.dts | 28 +++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts index 4d4cec8b86ac..6022e73f58af 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -64,6 +64,7 @@ gpio-keys { compatible = "gpio-keys"; button-user { + /* GPIO on PA13 "User button 2 (B2)" */ label = "User-PA13"; linux,code = ; gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; @@ -74,6 +75,7 @@ leds { compatible = "gpio-leds"; led_blue: led-blue { + /* GPIO on PA14 "User LED (LD3)" */ function = LED_FUNCTION_HEARTBEAT; color = ; gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; @@ -82,6 +84,7 @@ led_blue: led-blue { }; led-red { + /* GPIO on PA13 "User LED (LD4)" */ function = LED_FUNCTION_STATUS; color = ; gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; @@ -252,6 +255,7 @@ phy0_eth1: ethernet-phy@0 { &i2c1 { pinctrl-names = "default", "sleep"; + /* SDA on PE8 = CN8.27, SCL on PD12 = CN8.28 */ pinctrl-0 = <&i2c1_pins_a>; pinctrl-1 = <&i2c1_sleep_pins_a>; i2c-scl-rising-time-ns = <96>; @@ -486,7 +490,10 @@ counter { status = "okay"; }; pwm { - /* PWM output on pin 7 of the expansion connector (CN8.7) using TIM3_CH4 func */ + /* + * CH4 on PB1 = CN8.7; + * CH3 on PB0 = CN8.10 is possible (conflicting with usart1) + */ pinctrl-0 = <&pwm3_pins_a>; pinctrl-1 = <&pwm3_sleep_pins_a>; pinctrl-names = "default", "sleep"; @@ -505,7 +512,10 @@ counter { status = "okay"; }; pwm { - /* PWM output on pin 31 of the expansion connector (CN8.31) using TIM4_CH2 func */ + /* + * CH2 on PD13 = CN8.31; + * CH1 on PD12 = CN8.28 is possible (conflicting with &i2c1) + */ pinctrl-0 = <&pwm4_pins_a>; pinctrl-1 = <&pwm4_sleep_pins_a>; pinctrl-names = "default", "sleep"; @@ -524,7 +534,12 @@ counter { status = "okay"; }; pwm { - /* PWM output on pin 32 of the expansion connector (CN8.32) using TIM8_CH3 func */ + /* + * CH3 on PE5 = CN8.32 + * CH1N on PA7 = CN8.36 is possible (conflicting with &usart1) + * CH2N on PB0 = CN8.10 is possible (conflicting with &usart1) + * CH3N on PB1 = CN8.7 is possible (conflicting with &timers3) + */ pinctrl-0 = <&pwm8_pins_a>; pinctrl-1 = <&pwm8_sleep_pins_a>; pinctrl-names = "default", "sleep"; @@ -541,7 +556,7 @@ counter { status = "okay"; }; pwm { - /* PWM output on pin 33 of the expansion connector (CN8.33) using TIM14_CH1 func */ + /* CH1 on PF9 = CN8.33 (alternatively on PA7 = CN8.36 (conflicting with &usart1)) */ pinctrl-0 = <&pwm14_pins_a>; pinctrl-1 = <&pwm14_sleep_pins_a>; pinctrl-names = "default", "sleep"; @@ -553,6 +568,7 @@ timer@13 { }; &uart4 { + /* Accessible via micro USB ST-LINK USB (CN10) */ pinctrl-names = "default", "sleep", "idle"; pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; @@ -564,6 +580,7 @@ &uart4 { &uart8 { pinctrl-names = "default", "sleep", "idle"; + /* TX on PE1 = CN8.37, RX on PF9 = CN8.33 */ pinctrl-0 = <&uart8_pins_a>; pinctrl-1 = <&uart8_sleep_pins_a>; pinctrl-2 = <&uart8_idle_pins_a>; @@ -574,6 +591,7 @@ &uart8 { &usart1 { pinctrl-names = "default", "sleep", "idle"; + /* TX on PC0 = CN8.8, RX on PB0 = CN8.10, RTS on PC2 = CN8.11, CTS on PA7 = CN8.36 */ pinctrl-0 = <&usart1_pins_a>; pinctrl-1 = <&usart1_sleep_pins_a>; pinctrl-2 = <&usart1_idle_pins_a>; @@ -584,6 +602,7 @@ &usart1 { /* Bluetooth */ &usart2 { pinctrl-names = "default", "sleep", "idle"; + /* TX on PH12, RX on PD15, RTS on PD4, CTS on PE11 */ pinctrl-0 = <&usart2_pins_a>; pinctrl-1 = <&usart2_sleep_pins_a>; pinctrl-2 = <&usart2_idle_pins_a>; @@ -613,6 +632,7 @@ hub@1 { }; &usbotg_hs { + /* USB Type-C DRP (CN7) */ phys = <&usbphyc_port1 0>; phy-names = "usb2-phy"; usb-role-switch; From c84f22405085d91cd5f0c5b967318371c07904ba Mon Sep 17 00:00:00 2001 From: David Jander Date: Wed, 18 Mar 2026 11:51:17 +0100 Subject: [PATCH 341/665] ARM: dts: stm32: stm32mp15x-mecio1-io: Enable internal ADC reference Switch the ADC reference supply from the general 3.3V rail to the internal 2.5V VREFBUF regulator. The ADC circuits on this board are designed for the internal 2.5V reference. Without this change, all ADC measurement values are incorrect. Fixes: 8267753c891c ("ARM: dts: stm32: Add MECIO1 and MECT1S board variants") Co-developed-by: Oleksij Rempel Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Cc: Link: https://lore.kernel.org/r/20260318105123.819807-2-o.rempel@pengutronix.de Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi b/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi index 915ba2526f45..1ce01bac9814 100644 --- a/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi @@ -95,7 +95,7 @@ &adc { pinctrl-names = "default"; vdd-supply = <&v3v3>; vdda-supply = <&v3v3>; - vref-supply = <&v3v3>; + vref-supply = <&vrefbuf>; status = "okay"; }; @@ -412,6 +412,13 @@ &usbphyc_port1 { phy-supply = <&v3v3>; }; +&vrefbuf { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vdda-supply = <&v3v3>; + status = "okay"; +}; + &pinctrl { adc12_pins_mecsbc: adc12-ain-mecsbc-0 { pins { From 8407e611faf80ce790a393addf7b44cc595742af Mon Sep 17 00:00:00 2001 From: David Jander Date: Wed, 18 Mar 2026 11:51:18 +0100 Subject: [PATCH 342/665] ARM: dts: stm32: stm32mp15x-mecio1-io: Fix ADC sampling times Increase the minimum ADC sample times for all configured channels on ADC1 and ADC2 to ensure measurement accuracy meets specifications. The default 5us sample time is insufficient for the internal sampling capacitor to fully charge. Increase the default time to 20us to relax the input impedance requirements. Additionally, the phint0_ain and phint1_ain channels require a much longer sampling period due to their specific circuit design. Increase their sample times to 200us. Remove stale comments regarding clock cycles that no longer match the updated timings. Fixes: 8267753c891c ("ARM: dts: stm32: Add MECIO1 and MECT1S board variants") Co-developed-by: Oleksij Rempel Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Cc: Link: https://lore.kernel.org/r/20260318105123.819807-3-o.rempel@pengutronix.de Signed-off-by: Alexandre Torgue --- .../arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi | 32 +++++++++---------- 1 file changed, 15 insertions(+), 17 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi b/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi index 1ce01bac9814..1b1299770ca0 100644 --- a/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi @@ -104,80 +104,79 @@ &adc1 { channel@0 { reg = <0>; - /* 16.5 ck_cycles sampling time */ - st,min-sample-time-ns = <5000>; + st,min-sample-time-ns = <20000>; label = "p24v_stp"; }; channel@1 { reg = <1>; - st,min-sample-time-ns = <5000>; + st,min-sample-time-ns = <20000>; label = "p24v_hpdcm"; }; channel@2 { reg = <2>; - st,min-sample-time-ns = <5000>; + st,min-sample-time-ns = <20000>; label = "ain0"; }; channel@3 { reg = <3>; - st,min-sample-time-ns = <5000>; + st,min-sample-time-ns = <20000>; label = "hpdcm1_i2"; }; channel@5 { reg = <5>; - st,min-sample-time-ns = <5000>; + st,min-sample-time-ns = <20000>; label = "hpout1_i"; }; channel@6 { reg = <6>; - st,min-sample-time-ns = <5000>; + st,min-sample-time-ns = <20000>; label = "ain1"; }; channel@9 { reg = <9>; - st,min-sample-time-ns = <5000>; + st,min-sample-time-ns = <20000>; label = "hpout0_i"; }; channel@10 { reg = <10>; - st,min-sample-time-ns = <5000>; + st,min-sample-time-ns = <200000>; label = "phint0_ain"; }; channel@13 { reg = <13>; - st,min-sample-time-ns = <5000>; + st,min-sample-time-ns = <200000>; label = "phint1_ain"; }; channel@15 { reg = <15>; - st,min-sample-time-ns = <5000>; + st,min-sample-time-ns = <20000>; label = "hpdcm0_i1"; }; channel@16 { reg = <16>; - st,min-sample-time-ns = <5000>; + st,min-sample-time-ns = <20000>; label = "lsin"; }; channel@18 { reg = <18>; - st,min-sample-time-ns = <5000>; + st,min-sample-time-ns = <20000>; label = "hpdcm0_i2"; }; channel@19 { reg = <19>; - st,min-sample-time-ns = <5000>; + st,min-sample-time-ns = <20000>; label = "hpdcm1_i1"; }; }; @@ -187,14 +186,13 @@ &adc2 { channel@2 { reg = <2>; - /* 16.5 ck_cycles sampling time */ - st,min-sample-time-ns = <5000>; + st,min-sample-time-ns = <20000>; label = "ain2"; }; channel@6 { reg = <6>; - st,min-sample-time-ns = <5000>; + st,min-sample-time-ns = <20000>; label = "ain3"; }; }; From 70f1d8fcbd121a40f51b6c846d41e8cbb38ba210 Mon Sep 17 00:00:00 2001 From: David Jander Date: Wed, 18 Mar 2026 11:51:19 +0100 Subject: [PATCH 343/665] ARM: dts: stm32: stm32mp15x-mecio1-io: Move divergent mecio1 ADC channels to board files Move the divergent adc1 channel definitions out of the common mecio1-io.dtsi file and into the specific Revision 0 and Revision 1 board files. The original common file contained incorrect schematic labels for the Revision 0 hardware (e.g., labeling ana0 as p24v_hpdcm instead of ain_aux0) and failed to account for physical signal routing changes between the board revisions. Retain only the strictly shared channels in the common include file. Map the correct channels and schematic labels directly within stm32mp151c-mecio1r0.dts and stm32mp153c-mecio1r1.dts. Crucially, ensure that the required 200us sample time follows the phint1_ain signal to its new physical location on channel 3 for the Revision 1 hardware. Fixes: 8267753c891c ("ARM: dts: stm32: Add MECIO1 and MECT1S board variants") Co-developed-by: Oleksij Rempel Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Cc: Link: https://lore.kernel.org/r/20260318105123.819807-4-o.rempel@pengutronix.de Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts | 50 +++++++++++++++++++ arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts | 50 +++++++++++++++++++ .../arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi | 50 +------------------ 3 files changed, 101 insertions(+), 49 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts b/arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts index a5ea1431c399..4e795ad42928 100644 --- a/arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts +++ b/arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts @@ -36,6 +36,56 @@ led-1 { }; }; +&adc1 { + channel@0 { + reg = <0>; + st,min-sample-time-ns = <20000>; + label = "ain_aux0"; + }; + + channel@1 { + reg = <1>; + st,min-sample-time-ns = <20000>; + label = "ain_aux1"; + }; + + channel@3 { + reg = <3>; + st,min-sample-time-ns = <20000>; + label = "hpdcm1_i2"; + }; + + channel@5 { + reg = <5>; + st,min-sample-time-ns = <20000>; + label = "pout1_i"; + }; + + channel@9 { + reg = <9>; + st,min-sample-time-ns = <20000>; + label = "pout0_i"; + }; + + channel@13 { + reg = <13>; + st,min-sample-time-ns = <200000>; + label = "phint1_ain"; + }; + + channel@15 { + reg = <15>; + st,min-sample-time-ns = <20000>; + label = "hpdcm0_i1"; + }; + + channel@18 { + reg = <18>; + st,min-sample-time-ns = <20000>; + label = "hpdcm0_i2"; + }; +}; + &clk_hse { clock-frequency = <25000000>; }; diff --git a/arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts b/arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts index 16b814c19350..d32816093e47 100644 --- a/arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts +++ b/arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts @@ -36,6 +36,56 @@ led-1 { }; }; +&adc1 { + channel@0 { + reg = <0>; + st,min-sample-time-ns = <20000>; + label = "p24v_hpdcm"; + }; + + channel@1 { + reg = <1>; + st,min-sample-time-ns = <20000>; + label = "p24v_stp"; + }; + + channel@3 { + reg = <3>; + st,min-sample-time-ns = <200000>; + label = "phint1_ain"; + }; + + channel@5 { + reg = <5>; + st,min-sample-time-ns = <20000>; + label = "hpout1_i"; + }; + + channel@9 { + reg = <9>; + st,min-sample-time-ns = <20000>; + label = "hpout0_i"; + }; + + channel@13 { + reg = <13>; + st,min-sample-time-ns = <20000>; + label = "hpdcm0_i2"; + }; + + channel@15 { + reg = <15>; + st,min-sample-time-ns = <20000>; + label = "hpdcm1_i2"; + }; + + channel@18 { + reg = <18>; + st,min-sample-time-ns = <20000>; + label = "hpdcm0_i1"; + }; +}; + &clk_hse { clock-frequency = <24000000>; }; diff --git a/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi b/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi index 1b1299770ca0..f91b3d1f037b 100644 --- a/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi @@ -90,7 +90,7 @@ v5v: regulator-v5v { }; &adc { - /* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */ + /* ANA0, ANA1 are dedicated pins and don't need pinctrl. */ pinctrl-0 = <&adc12_pins_mecsbc>; pinctrl-names = "default"; vdd-supply = <&v3v3>; @@ -102,78 +102,30 @@ &adc { &adc1 { status = "okay"; - channel@0 { - reg = <0>; - st,min-sample-time-ns = <20000>; - label = "p24v_stp"; - }; - - channel@1 { - reg = <1>; - st,min-sample-time-ns = <20000>; - label = "p24v_hpdcm"; - }; - channel@2 { reg = <2>; st,min-sample-time-ns = <20000>; label = "ain0"; }; - channel@3 { - reg = <3>; - st,min-sample-time-ns = <20000>; - label = "hpdcm1_i2"; - }; - - channel@5 { - reg = <5>; - st,min-sample-time-ns = <20000>; - label = "hpout1_i"; - }; - channel@6 { reg = <6>; st,min-sample-time-ns = <20000>; label = "ain1"; }; - channel@9 { - reg = <9>; - st,min-sample-time-ns = <20000>; - label = "hpout0_i"; - }; - channel@10 { reg = <10>; st,min-sample-time-ns = <200000>; label = "phint0_ain"; }; - channel@13 { - reg = <13>; - st,min-sample-time-ns = <200000>; - label = "phint1_ain"; - }; - - channel@15 { - reg = <15>; - st,min-sample-time-ns = <20000>; - label = "hpdcm0_i1"; - }; - channel@16 { reg = <16>; st,min-sample-time-ns = <20000>; label = "lsin"; }; - channel@18 { - reg = <18>; - st,min-sample-time-ns = <20000>; - label = "hpdcm0_i2"; - }; - channel@19 { reg = <19>; st,min-sample-time-ns = <20000>; From b04ccecb714de913e360f0866c66f38e1606e89b Mon Sep 17 00:00:00 2001 From: David Jander Date: Wed, 18 Mar 2026 11:51:20 +0100 Subject: [PATCH 344/665] ARM: dts: stm32: stm32mp15x-mecio1-io: Fix GPIO names typo The reset pins for the LPOUT lines were incorrectly prefixed with "GPOUT" instead of "LPOUT" in the gpio-line-names array. Fix these typos so the pin names consistently match the LPOUT0-4 signals they belong to. Fixes: 8267753c891c ("ARM: dts: stm32: Add MECIO1 and MECT1S board variants") Co-developed-by: Oleksij Rempel Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Cc: Link: https://lore.kernel.org/r/20260318105123.819807-5-o.rempel@pengutronix.de Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi b/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi index f91b3d1f037b..e50e9ae085e8 100644 --- a/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi @@ -185,14 +185,14 @@ &gpiod { &gpioe { gpio-line-names = "HPOUT0_RESETN", "HPOUT1", "HPOUT1_ALERTN", "", "", "", "HPOUT1_RESETN", - "LPOUT0", "LPOUT0_ALERTN", "GPOUT0_RESETN", - "LPOUT1", "LPOUT1_ALERTN", "GPOUT1_RESETN", - "LPOUT2", "LPOUT2_ALERTN", "GPOUT2_RESETN"; + "LPOUT0", "LPOUT0_ALERTN", "LPOUT0_RESETN", + "LPOUT1", "LPOUT1_ALERTN", "LPOUT1_RESETN", + "LPOUT2", "LPOUT2_ALERTN", "LPOUT2_RESETN"; }; &gpiof { - gpio-line-names = "LPOUT3", "LPOUT3_ALERTN", "GPOUT3_RESETN", - "LPOUT4", "LPOUT4_ALERTN", "GPOUT4_RESETN", + gpio-line-names = "LPOUT3", "LPOUT3_ALERTN", "LPOUT3_RESETN", + "LPOUT4", "LPOUT4_ALERTN", "LPOUT4_RESETN", "", "", "", "", "", "", "", "", "", ""; From 4f5069609ac99894c0632d8b8c4c016f85199de9 Mon Sep 17 00:00:00 2001 From: David Jander Date: Wed, 18 Mar 2026 11:51:21 +0100 Subject: [PATCH 345/665] ARM: dts: stm32: stm32mp15x-mecio1-io: Move gpio-line-names to board files Move the gpio-line-names properties out of the common mecio1-io.dtsi file and into the specific board dts files. The pinout originally defined in the common include file belonged to the mecio1r0 (Revision 0) hardware. This is moved 1:1 into the stm32mp151c-mecio1r0.dts file without any modifications. A large number of GPIO pins are swapped on the mecio1r1 (Revision 1) hardware, so a new, board-specific gpio-line-names mapping is added to stm32mp153c-mecio1r1.dts to reflect those hardware changes. Fixes: 8267753c891c ("ARM: dts: stm32: Add MECIO1 and MECT1S board variants") Co-developed-by: Oleksij Rempel Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Cc: Link: https://lore.kernel.org/r/20260318105123.819807-6-o.rempel@pengutronix.de Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts | 64 +++++++++++++++ arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts | 80 +++++++++++++++++++ .../arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi | 63 --------------- 3 files changed, 144 insertions(+), 63 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts b/arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts index 4e795ad42928..06ab77465816 100644 --- a/arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts +++ b/arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts @@ -96,3 +96,67 @@ ðernet0 { assigned-clock-rates = <125000000>; /* Clock PLL3 to 625Mhz in tf-a. */ st,eth-clk-sel; }; + +&gpiod { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "STP_RESETN", "STP_ENABLEN", "HPOUT0", "HPOUT0_ALERTN"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_d_mecsbc>; +}; + +&gpioe { + gpio-line-names = "HPOUT0_RESETN", "HPOUT1", "HPOUT1_ALERTN", "", + "", "", "HPOUT1_RESETN", + "LPOUT0", "LPOUT0_ALERTN", "LPOUT0_RESETN", + "LPOUT1", "LPOUT1_ALERTN", "LPOUT1_RESETN", + "LPOUT2", "LPOUT2_ALERTN", "LPOUT2_RESETN"; +}; + +&gpiof { + gpio-line-names = "LPOUT3", "LPOUT3_ALERTN", "LPOUT3_RESETN", + "LPOUT4", "LPOUT4_ALERTN", "LPOUT4_RESETN", + "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpiog { + gpio-line-names = "LPOUT5", "LPOUT5_ALERTN", "", "LPOUT5_RESETN", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpioh { + gpio-line-names = "", "", "", "", + "", "", "", "", + "GPIO0_RESETN", "", "", "", + "", "", "", ""; +}; + +&gpioi { + gpio-line-names = "", "", "", "", + "", "", "", "", + "HPDCM0_SLEEPN", "HPDCM1_SLEEPN", "GPIO1_RESETN", "", + "", "", "", ""; +}; + +&gpioj { + gpio-line-names = "HSIN10", "HSIN11", "HSIN12", "HSIN13", + "HSIN14", "HSIN15", "", "", + "", "", "", "", + "", "RTD_RESETN", "", ""; +}; + +&gpiok { + gpio-line-names = "", "", "HSIN0", "HSIN1", + "HSIN2", "HSIN3", "HSIN4", "HSIN5"; +}; + +&gpioz { + gpio-line-names = "", "", "", "HSIN6", + "HSIN7", "HSIN8", "HSIN9", ""; +}; + diff --git a/arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts b/arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts index d32816093e47..2b3989303cd1 100644 --- a/arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts +++ b/arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts @@ -90,6 +90,86 @@ &clk_hse { clock-frequency = <24000000>; }; +&gpioa { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "GPIO1_RESETN", "", + "", "", "", "LPOUT5"; +}; + +&gpiob { + gpio-line-names = "", "", "", "", + "LPOUT4_RESETN", "", "", "", + "", "LPOUT4_ALERTN", "", "", + "", "", "", ""; +}; + +&gpioc { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "LPOUT4", "", "", + "", "", "", ""; +}; + +&gpiod { + gpio-line-names = "LPOUT2", "", "LPOUT3_RESETN", "", + "LPOUT2_ALERTN", "", "MECIO_ADDR0", "", + "HPOUT1_ALERTN", "HPOUT1_RESETN", "", "", + "", "", "HPOUT0", "HPOUT1"; +}; + +&gpioe { + gpio-line-names = "LPOUT0_RESETN", "", "", "", + "", "LPOUT3", "LPOUT5_ALERTN", "", + "", "", "", "", + "", "", "", "HSIN_RESETN"; +}; + +&gpiof { + gpio-line-names = "LPOUT5_RESETN", "", "", "HPOUT0_ALERTN", + "", "LPOUT1", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpiog { + gpio-line-names = "", "", "", "HPOUT0_RESETN", + "", "", "LPOUT3_ALERTN", "", + "", "", "GPIO0_RESETN", "", + "", "", "", "LPOUT2_RESETN"; +}; + +&gpioh { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "LPOUT0", "", "", + "", "LPOUT0_ALERTN", "STP_ENABLEN", "STP_RESETN"; +}; + +&gpioi { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "SPE_RESETN", "", + "HPDCM0_SLEEPN", "", "", ""; +}; + +&gpioj { + gpio-line-names = "", "", "", "", + "", "", "", "MECIO_ADDR1", + "", "", "", "", + "", "", "", "LPOUT1_RESETN"; +}; + +&gpiok { + gpio-line-names = "", "", "RTD_RESETN", "", + "", "LPOUT1_ALERTN", "", ""; +}; + +&gpioz { + gpio-line-names = "", "", "", "", + "HPDCM1_SLEEPN", "", "", ""; +}; + &m_can1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&m_can1_pins_b>; diff --git a/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi b/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi index e50e9ae085e8..69a502ec36d4 100644 --- a/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi @@ -173,69 +173,6 @@ phy0: ethernet-phy@8 { }; }; -&gpiod { - gpio-line-names = "", "", "", "", - "", "", "", "", - "", "", "", "", - "STP_RESETN", "STP_ENABLEN", "HPOUT0", "HPOUT0_ALERTN"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog_d_mecsbc>; -}; - -&gpioe { - gpio-line-names = "HPOUT0_RESETN", "HPOUT1", "HPOUT1_ALERTN", "", - "", "", "HPOUT1_RESETN", - "LPOUT0", "LPOUT0_ALERTN", "LPOUT0_RESETN", - "LPOUT1", "LPOUT1_ALERTN", "LPOUT1_RESETN", - "LPOUT2", "LPOUT2_ALERTN", "LPOUT2_RESETN"; -}; - -&gpiof { - gpio-line-names = "LPOUT3", "LPOUT3_ALERTN", "LPOUT3_RESETN", - "LPOUT4", "LPOUT4_ALERTN", "LPOUT4_RESETN", - "", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpiog { - gpio-line-names = "LPOUT5", "LPOUT5_ALERTN", "", "LPOUT5_RESETN", - "", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpioh { - gpio-line-names = "", "", "", "", - "", "", "", "", - "GPIO0_RESETN", "", "", "", - "", "", "", ""; -}; - -&gpioi { - gpio-line-names = "", "", "", "", - "", "", "", "", - "HPDCM0_SLEEPN", "HPDCM1_SLEEPN", "GPIO1_RESETN", "", - "", "", "", ""; -}; - -&gpioj { - gpio-line-names = "HSIN10", "HSIN11", "HSIN12", "HSIN13", - "HSIN14", "HSIN15", "", "", - "", "", "", "", - "", "RTD_RESETN", "", ""; -}; - -&gpiok { - gpio-line-names = "", "", "HSIN0", "HSIN1", - "HSIN2", "HSIN3", "HSIN4", "HSIN5"; -}; - -&gpioz { - gpio-line-names = "", "", "", "HSIN6", - "HSIN7", "HSIN8", "HSIN9", ""; -}; - &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins_a>; From dfb93c4acce8ad9c4f573128b2cf7ddb936e0de7 Mon Sep 17 00:00:00 2001 From: David Jander Date: Wed, 18 Mar 2026 11:51:22 +0100 Subject: [PATCH 346/665] ARM: dts: stm32: stm32mp15x-mecio1-io: Fix expander gpio line typo Fix a copy-paste error in the GPIO line names for the TCA6416 expander (gpio@20). The common mecio1-io include file was originally defined using the mecio1r1 (Revision 1) hardware layout, but incorrectly labeled pin 13 as "HSIN9_BIAS" instead of the actual "HSIN7_BIAS" present in the schematics. Fixes: 8267753c891c ("ARM: dts: stm32: Add MECIO1 and MECT1S board variants") Co-developed-by: Oleksij Rempel Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20260318105123.819807-7-o.rempel@pengutronix.de Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi b/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi index 69a502ec36d4..1808289f8193 100644 --- a/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi @@ -186,7 +186,7 @@ gpio0: gpio@20 { #gpio-cells = <2>; gpio-line-names = "HSIN0_BIAS", "HSIN1_BIAS", "HSIN2_BIAS", "HSIN3_BIAS", "", "", "HSIN_VREF0_LVL", "HSIN_VREF1_LVL", - "HSIN4_BIAS", "HSIN5_BIAS", "HSIN6_BIAS", "HSIN9_BIAS", + "HSIN4_BIAS", "HSIN5_BIAS", "HSIN6_BIAS", "HSIN7_BIAS", "", "", "", ""; }; From a0d6c2a06fffff47bcca4d5bfdab4cc428a315fc Mon Sep 17 00:00:00 2001 From: David Jander Date: Wed, 18 Mar 2026 11:51:23 +0100 Subject: [PATCH 347/665] ARM: dts: stm32: stm32mp15x-mecio1-io: Move expander gpio-line-names to board files Move the gpio-line-names properties for the I2C GPIO expanders (gpio0 and gpio1) out of the common mecio1-io.dtsi file and into the specific board dts files. The layout originally defined in the common include file belonged to the mecio1r1 (Revision 1) hardware. This layout is moved 1:1 into the stm32mp153c-mecio1r1.dts file. The mecio1r0 (Revision 0) hardware utilizes a completely different pinout for these expanders. A new, accurate mapping reflecting the Revision 0 schematics is added to stm32mp151c-mecio1r0.dts. Fixes: 8267753c891c ("ARM: dts: stm32: Add MECIO1 and MECT1S board variants") Co-developed-by: Oleksij Rempel Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20260318105123.819807-8-o.rempel@pengutronix.de Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts | 14 ++++++++++++++ arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts | 14 ++++++++++++++ arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi | 8 -------- 3 files changed, 28 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts b/arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts index 06ab77465816..862782d20d10 100644 --- a/arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts +++ b/arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts @@ -97,6 +97,20 @@ ðernet0 { st,eth-clk-sel; }; +&gpio0 { + gpio-line-names = "HSIN0_BIAS", "HSIN1_BIAS", "HSIN2_BIAS", "HSIN3_BIAS", + "HSIN4_BIAS", "", "STP_VREF0_LVL", "HSIN_VREF0_LVL", + "STP0_FB_BIAS", "STP1_FB_BIAS", "STP2_FB_BIAS", "STP3_FB_BIAS", + "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = "HSIN5_BIAS", "HSIN6_BIAS", "HSIN7_BIAS", "HSIN8_BIAS", + "HSIN9_BIAS", "", "STP_VREF1_LVL", "HSIN_VREF1_LVL", + "STP4_FB_BIAS", "STP5_FB_BIAS", "STP6_FB_BIAS", "", + "", "", "LSIN8_BIAS", "LSIN9_BIAS"; +}; + &gpiod { gpio-line-names = "", "", "", "", "", "", "", "", diff --git a/arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts b/arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts index 2b3989303cd1..739cc18c3d3a 100644 --- a/arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts +++ b/arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts @@ -90,6 +90,20 @@ &clk_hse { clock-frequency = <24000000>; }; +&gpio0 { + gpio-line-names = "HSIN0_BIAS", "HSIN1_BIAS", "HSIN2_BIAS", "HSIN3_BIAS", + "", "", "HSIN_VREF0_LVL", "HSIN_VREF1_LVL", + "HSIN4_BIAS", "HSIN5_BIAS", "HSIN6_BIAS", "HSIN7_BIAS", + "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = "HSIN8_BIAS", "HSIN9_BIAS", "HSIN10_BIAS", "HSIN11_BIAS", + "", "", "HSIN_VREF2_LVL", "HSIN_VREF3_LVL", + "HSIN12_BIAS", "HSIN13_BIAS", "HSIN14_BIAS", "HSIN15_BIAS", + "", "", "LSIN8_BIAS", "LSIN9_BIAS"; +}; + &gpioa { gpio-line-names = "", "", "", "", "", "", "", "", diff --git a/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi b/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi index 1808289f8193..1a4f5a523eb3 100644 --- a/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi @@ -184,10 +184,6 @@ gpio0: gpio@20 { reg = <0x20>; gpio-controller; #gpio-cells = <2>; - gpio-line-names = "HSIN0_BIAS", "HSIN1_BIAS", "HSIN2_BIAS", "HSIN3_BIAS", - "", "", "HSIN_VREF0_LVL", "HSIN_VREF1_LVL", - "HSIN4_BIAS", "HSIN5_BIAS", "HSIN6_BIAS", "HSIN7_BIAS", - "", "", "", ""; }; gpio1: gpio@21 { @@ -195,10 +191,6 @@ gpio1: gpio@21 { reg = <0x21>; gpio-controller; #gpio-cells = <2>; - gpio-line-names = "HSIN8_BIAS", "HSIN9_BIAS", "HSIN10_BIAS", "HSIN11_BIAS", - "", "", "HSIN_VREF2_LVL", "HSIN_VREF3_LVL", - "HSIN12_BIAS", "HSIN13_BIAS", "HSIN14_BIAS", "HSIN15_BIAS", - "", "", "LSIN8_BIAS", "LSIN9_BIAS"; }; }; From b4f5c46163b3fe3ec7ed8a76dff8b7e80a776a1f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 13 Apr 2026 11:07:24 +0200 Subject: [PATCH 348/665] arm64: dts: imx8ulp-evk: Correct Type-C int GPIO flags IRQ_TYPE_xxx flags are not correct in the context of GPIO flags. These are simple defines so they could be used in DTS but they will not have the same meaning: IRQ_TYPE_EDGE_FALLING = 2 = GPIO_SINGLE_ENDED. Correct the Type-C int-gpios to use proper flags, assuming the author of the code wanted similar logical behavior: IRQ_TYPE_EDGE_FALLING => GPIO_ACTIVE_LOW Fixes: c4b4593ecb0b ("arm64: dts: imx8ulp-evk: enable usb nodes and add ptn5150 nodes") Cc: stable@vger.kernel.org Signed-off-by: Krzysztof Kozlowski Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts index 290a49bea2f7..5dea66c1e7aa 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts @@ -166,7 +166,7 @@ &lpi2c7 { ptn5150_1: typec@1d { compatible = "nxp,ptn5150"; reg = <0x1d>; - int-gpios = <&gpiof 3 IRQ_TYPE_EDGE_FALLING>; + int-gpios = <&gpiof 3 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_typec1>; status = "disabled"; @@ -182,7 +182,7 @@ pcal6408: gpio@21 { ptn5150_2: typec@3d { compatible = "nxp,ptn5150"; reg = <0x3d>; - int-gpios = <&gpiof 5 IRQ_TYPE_EDGE_FALLING>; + int-gpios = <&gpiof 5 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_typec2>; status = "disabled"; From ca6371cdd9cf3c0d40f05a3ea6494646eaefb15c Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Thu, 9 Apr 2026 11:58:47 +0200 Subject: [PATCH 349/665] dt-bindings: arm: fsl: Add verdin imx8m[mp] and imx95 zinnia board Add Toradex Verdin Zinnia carrier board mated with Verdin iMX8M Plus, Verdin iMX8M Mini and Verdin iMX95. Link: https://www.toradex.com/products/carrier-board/zinnia-carrier-board Signed-off-by: Francesco Dolcini Acked-by: Krzysztof Kozlowski Signed-off-by: Frank Li --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 5911b41e7a32..59f7f168bf7c 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1025,6 +1025,7 @@ properties: - toradex,verdin-imx8mm-nonwifi-ivy # Verdin iMX8M Mini Module on Ivy - toradex,verdin-imx8mm-nonwifi-mallow # Verdin iMX8M Mini Module on Mallow - toradex,verdin-imx8mm-nonwifi-yavia # Verdin iMX8M Mini Module on Yavia + - toradex,verdin-imx8mm-nonwifi-zinnia # Verdin iMX8M Mini Module on Zinnia - const: toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Module without Wi-Fi / BT - const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module - const: fsl,imx8mm @@ -1037,6 +1038,7 @@ properties: - toradex,verdin-imx8mm-wifi-ivy # Verdin iMX8M Mini Wi-Fi / BT Module on Ivy - toradex,verdin-imx8mm-wifi-mallow # Verdin iMX8M Mini Wi-Fi / BT Module on Mallow - toradex,verdin-imx8mm-wifi-yavia # Verdin iMX8M Mini Wi-Fi / BT Module on Yavia + - toradex,verdin-imx8mm-wifi-zinnia # Verdin iMX8M Mini Wi-Fi / BT Module on Zinnia - const: toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Module - const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module - const: fsl,imx8mm @@ -1271,6 +1273,7 @@ properties: - toradex,verdin-imx8mp-nonwifi-ivy # Verdin iMX8M Plus Module on Ivy - toradex,verdin-imx8mp-nonwifi-mallow # Verdin iMX8M Plus Module on Mallow - toradex,verdin-imx8mp-nonwifi-yavia # Verdin iMX8M Plus Module on Yavia + - toradex,verdin-imx8mp-nonwifi-zinnia # Verdin iMX8M Plus Module on Zinnia - const: toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Module without Wi-Fi / BT - const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module - const: fsl,imx8mp @@ -1283,6 +1286,7 @@ properties: - toradex,verdin-imx8mp-wifi-ivy # Verdin iMX8M Plus Wi-Fi / BT Module on Ivy - toradex,verdin-imx8mp-wifi-mallow # Verdin iMX8M Plus Wi-Fi / BT Module on Mallow - toradex,verdin-imx8mp-wifi-yavia # Verdin iMX8M Plus Wi-Fi / BT Module on Yavia + - toradex,verdin-imx8mp-wifi-zinnia # Verdin iMX8M Plus Wi-Fi / BT Module on Zinnia - const: toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Module - const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module - const: fsl,imx8mp @@ -1517,6 +1521,7 @@ properties: - toradex,verdin-imx95-nonwifi-ivy # Verdin iMX95 Module on Ivy - toradex,verdin-imx95-nonwifi-mallow # Verdin iMX95 Module on Mallow - toradex,verdin-imx95-nonwifi-yavia # Verdin iMX95 Module on Yavia + - toradex,verdin-imx95-nonwifi-zinnia # Verdin iMX95 Module on Zinnia - const: toradex,verdin-imx95-nonwifi # Verdin iMX95 Module without Wi-Fi / BT - const: toradex,verdin-imx95 # Verdin iMX95 Module - const: fsl,imx95 @@ -1529,6 +1534,7 @@ properties: - toradex,verdin-imx95-wifi-ivy # Verdin iMX95 Wi-Fi / BT Module on Ivy - toradex,verdin-imx95-wifi-mallow # Verdin iMX95 Wi-Fi / BT Module on Mallow - toradex,verdin-imx95-wifi-yavia # Verdin iMX95 Wi-Fi / BT Module on Yavia + - toradex,verdin-imx95-wifi-zinnia # Verdin iMX95 Wi-Fi / BT Module on Zinnia - const: toradex,verdin-imx95-wifi # Verdin iMX95 Wi-Fi / BT Module - const: toradex,verdin-imx95 # Verdin iMX95 Module - const: fsl,imx95 From 64819436679b7991d17fe498539b41eb2aacd05b Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Thu, 9 Apr 2026 11:58:48 +0200 Subject: [PATCH 350/665] arm64: dts: freescale: imx8mm-verdin: Split UART_2 pinctrl group Some carrier board reuse the UART_2 control signals as GPIO, split the pinctrl RTS/CTS in separated nodes to maximize flexibility. Signed-off-by: Francesco Dolcini Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index 1594ce9182a5..5fc177f589cb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -735,7 +735,7 @@ &uart2 { /* Verdin UART_2 */ &uart3 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; + pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_cts>, <&pinctrl_uart3_rts>; uart-has-rtscts; }; @@ -1144,12 +1144,20 @@ pinctrl_uart2: uart2grp { ; /* SODIMM 129 */ }; + pinctrl_uart3_cts: uart3ctsgrp { + fsl,pins = + ; /* SODIMM 143 */ + }; + + pinctrl_uart3_rts: uart3rtsgrp { + fsl,pins = + ; /* SODIMM 141 */ + }; + pinctrl_uart3: uart3grp { fsl,pins = - , /* SODIMM 141 */ , /* SODIMM 139 */ - , /* SODIMM 137 */ - ; /* SODIMM 143 */ + ; /* SODIMM 137 */ }; pinctrl_uart4: uart4grp { From de2e5e6c695a6fe5cfa780cd63ade651a6508d00 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Thu, 9 Apr 2026 11:58:49 +0200 Subject: [PATCH 351/665] arm64: dts: freescale: imx8mm-verdin: Add Zinnia Add Zinnia Carrier Board mated with Verdin iMX8M Mini. It features 1 x RS232, 1 x RS485, 1 x CAN, 3 x isolated digital I/O, 1 x GBit/s Ethernet, a mini PCIe slot with USB / SIM card connector for a modem, USB and SD card interfaces. Link: https://www.toradex.com/products/carrier-board/zinnia-carrier-board Signed-off-by: Francesco Dolcini Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../imx8mm-verdin-nonwifi-zinnia.dts | 21 + .../freescale/imx8mm-verdin-wifi-zinnia.dts | 21 + .../dts/freescale/imx8mm-verdin-zinnia.dtsi | 383 ++++++++++++++++++ 4 files changed, 427 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-zinnia.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-zinnia.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-zinnia.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 6c4a0a6a7eba..7bdaccd1a864 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -177,11 +177,13 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-ivy.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-mallow.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-yavia.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-zinnia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-ivy.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-mallow.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-yavia.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-zinnia.dtb imx8mm-tqma8mqml-mba8mx-lvds-g133han01-dtbs += imx8mm-tqma8mqml-mba8mx.dtb imx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtbo imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33-dtbs += imx8mm-tqma8mqml-mba8mx.dtb imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-zinnia.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-zinnia.dts new file mode 100644 index 000000000000..07b4daf916c2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-zinnia.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini-nano + * https://www.toradex.com/products/carrier-board/zinnia-carrier-board + */ + +/dts-v1/; + +#include "imx8mm-verdin.dtsi" +#include "imx8mm-verdin-nonwifi.dtsi" +#include "imx8mm-verdin-zinnia.dtsi" + +/ { + model = "Toradex Verdin iMX8M Mini on Zinnia"; + compatible = "toradex,verdin-imx8mm-nonwifi-zinnia", + "toradex,verdin-imx8mm-nonwifi", + "toradex,verdin-imx8mm", + "fsl,imx8mm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-zinnia.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-zinnia.dts new file mode 100644 index 000000000000..01a254dc1e6c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-zinnia.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini-nano + * https://www.toradex.com/products/carrier-board/zinnia-carrier-board + */ + +/dts-v1/; + +#include "imx8mm-verdin.dtsi" +#include "imx8mm-verdin-wifi.dtsi" +#include "imx8mm-verdin-zinnia.dtsi" + +/ { + model = "Toradex Verdin iMX8M Mini WB on Zinnia"; + compatible = "toradex,verdin-imx8mm-wifi-zinnia", + "toradex,verdin-imx8mm-wifi", + "toradex,verdin-imx8mm", + "fsl,imx8mm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-zinnia.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-zinnia.dtsi new file mode 100644 index 000000000000..686486e03178 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-zinnia.dtsi @@ -0,0 +1,383 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Common dtsi for Verdin IMX8MM SoM on Zinnia carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini-nano + * https://www.toradex.com/products/carrier-board/zinnia-carrier-board + */ + +#include + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_zinnia_leds>; + + /* LED1 Red - SODIMM 48 - LED1_R */ + led-0 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + }; + + /* LED1 Blue - SODIMM 46 - LED1_B */ + led-1 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; + }; + + /* LED3 Red - SODIMM 44 - LED3_R */ + led-2 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <3>; + gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; + }; + + /* LED3 Green - SODIMM 54 - LED3_G */ + led-3 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <3>; + gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; + }; + + /* LED3 Blue - SODIMM 36 - LED3_B */ + led-4 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <3>; + gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; + }; + + /* LED4 Red - SODIMM 34 - LED4_R */ + led-5 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <4>; + gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; + }; + + /* LED4 Green - SODIMM 32 - LED4_G */ + led-6 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <4>; + gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + }; + + /* LED4 Blue - SODIMM 30 - LED4_B */ + led-7 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <4>; + gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; + }; + }; + + zinnia-1v8-voltage { + compatible = "voltage-divider"; + full-ohms = <39000>; /* 12k + 27k */ + /* Verdin ADC_4 */ + io-channels = <&verdin_som_adc 4>; + output-ohms = <27000>; + }; + + zinnia-3v3-voltage { + compatible = "voltage-divider"; + full-ohms = <54000>; /* 27k + 27k */ + /* Verdin ADC_3 */ + io-channels = <&verdin_som_adc 5>; + output-ohms = <27000>; + }; + + zinnia-5v-voltage { + compatible = "voltage-divider"; + full-ohms = <39000>; /* 27k + 12k */ + /* Verdin ADC_2 */ + io-channels = <&verdin_som_adc 6>; + output-ohms = <12000>; + }; + + /* Zinnia Power Supply Input Voltage */ + zinnia-input-voltage { + compatible = "voltage-divider"; + full-ohms = <204700>; /* 200k + 4.7k */ + /* Verdin ADC_1 */ + io-channels = <&verdin_som_adc 7>; + output-ohms = <4700>; + }; +}; + +/* Verdin SPI_1 */ +&ecspi2 { + pinctrl-0 = <&pinctrl_ecspi2>, <&pinctrl_uart3_cts_gpio>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, <&gpio5 13 GPIO_ACTIVE_LOW>; + + status = "okay"; + + tpm@1 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <1>; + spi-max-frequency = <18500000>; + }; +}; + +/* EEPROM on Zinnia */ +&eeprom_carrier_board { + status = "okay"; +}; + +/* Verdin ETH_1 */ +&fec1 { + status = "okay"; +}; + +&gpio1 { + gpio-line-names = + "DI2_RB", /* SODIMM 216 */ /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "DO3_EN", /* SODIMM 220 */ + "DI3_EN", /* SODIMM 222 */ + "", /* 10 */ + "DI2_EN", /* SODIMM 218 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 20 */ + "", + "", + "", + "", + ""; +}; + +&gpio2 { + gpio-line-names = + "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + ""; /* 20 */ +}; + +&gpio3 { + gpio-line-names = + "", /* 0 */ + "", + "", + "", + "DO1_EN", /* SODIMM 206 */ + "", + "DI3_RB", /* SODIMM 56 */ + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 20 */ + "", + "", + "", + "", + ""; +}; + +&gpio4 { + gpio-line-names = + "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 20 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + ""; +}; + +&gpio5 { + gpio-line-names = + "", /* 0 */ + "", + "", + "", + "", + "DI1_EN", /* SODIMM 208 */ + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 20 */ + "", + "", + "", + "", + "", + "DI1_RB", /* SODIMM 210 */ + "DO2_EN", /* SODIMM 212 */ + "", + ""; +}; + +/* Temperature sensor on Zinnia */ +&hwmon_temp { + compatible = "ti,tmp1075"; + + status = "okay"; +}; + +/* Verdin I2C_1 */ +&i2c4 { + status = "okay"; +}; + +/* Verdin UART_3 */ +&uart1 { + status = "okay"; +}; + +/* Verdin UART_1 */ +&uart2 { + status = "okay"; +}; + +/* Verdin UART_2 */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_rts>; + rs485-rx-during-tx; + linux,rs485-enabled-at-boot-time; + + status = "okay"; +}; + +/* Verdin USB_1 */ +&usbotg1 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usbotg2 { + status = "okay"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>, + <&pinctrl_gpio2>, + <&pinctrl_gpio3>, + <&pinctrl_gpio4>, + <&pinctrl_gpio5>, + <&pinctrl_gpio6>, + <&pinctrl_gpio7>, + <&pinctrl_gpio8>, + <&pinctrl_qspi1_io0_gpio>; + + pinctrl_qspi1_io0_gpio: gpio3io6grp { + fsl,pins = ; /* SODIMM 56 */ + }; + + pinctrl_uart3_cts_gpio: gpio5io9grp { + fsl,pins = ; /* SODIMM 143 */ + }; + + pinctrl_zinnia_leds: zinnialedsgrp { + fsl,pins = + , /* SODIMM 30 */ + , /* SODIMM 32 */ + , /* SODIMM 34 */ + , /* SODIMM 36 */ + , /* SODIMM 44 */ + , /* SODIMM 46 */ + , /* SODIMM 48 */ + ; /* SODIMM 54 */ + }; +}; From 097418652e6ab85d4c737c01f3e024fb2399b289 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Thu, 9 Apr 2026 11:58:50 +0200 Subject: [PATCH 352/665] arm64: dts: freescale: imx8mp-verdin: Split UART_2 pinctrl group Some carrier board reuse the UART_2 control signals as GPIO, split the pinctrl RTS/CTS in separated nodes to maximize flexibility. Signed-off-by: Francesco Dolcini Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi index d31f8082394f..9fee2cf9ef54 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -846,7 +846,7 @@ &uart1 { /* Verdin UART_2 */ &uart2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; + pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart2_cts>, <&pinctrl_uart2_rts>; uart-has-rtscts; }; @@ -1277,10 +1277,18 @@ pinctrl_uart1: uart1grp { ; /* SODIMM 131 */ }; + pinctrl_uart2_cts: uart2ctsgrp { + fsl,pins = + ; /* SODIMM 143 */ + }; + + pinctrl_uart2_rts: uart2rtsgrp { + fsl,pins = + ; /* SODIMM 141 */ + }; + pinctrl_uart2: uart2grp { fsl,pins = - , /* SODIMM 143 */ - , /* SODIMM 141 */ , /* SODIMM 137 */ ; /* SODIMM 139 */ }; From e3177171b6e90850623436e9eb3bcbf9915dcc1a Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Thu, 9 Apr 2026 11:58:51 +0200 Subject: [PATCH 353/665] arm64: dts: freescale: imx8mp-verdin: Add Zinnia Add Zinnia Carrier Board mated with Verdin iMX8M Plus. It features 1 x RS232, 1 x RS485, 1 x CAN, 3 x isolated digital I/O, 2 x GBit/s Ethernet, a mini PCIe slot with USB / SIM card connector for a modem, USB and SD card interfaces. Link: https://www.toradex.com/products/carrier-board/zinnia-carrier-board Signed-off-by: Francesco Dolcini Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../imx8mp-verdin-nonwifi-zinnia.dts | 21 + .../freescale/imx8mp-verdin-wifi-zinnia.dts | 21 + .../dts/freescale/imx8mp-verdin-zinnia.dtsi | 422 ++++++++++++++++++ 4 files changed, 466 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-zinnia.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-zinnia.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-verdin-zinnia.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 7bdaccd1a864..0fb1a7584ee8 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -347,11 +347,13 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-ivy.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-mallow.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-yavia.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-zinnia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-ivy.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-mallow.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-yavia.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-zinnia.dtb imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtbo imx8mp-evk-lvds0-imx-lvds-hdmi-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds0-imx-lvds-hdmi.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-zinnia.dts b/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-zinnia.dts new file mode 100644 index 000000000000..e78b25d65c94 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-zinnia.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-plus + * https://www.toradex.com/products/carrier-board/zinnia-carrier-board + */ + +/dts-v1/; + +#include "imx8mp-verdin.dtsi" +#include "imx8mp-verdin-nonwifi.dtsi" +#include "imx8mp-verdin-zinnia.dtsi" + +/ { + model = "Toradex Verdin iMX8M Plus on Zinnia"; + compatible = "toradex,verdin-imx8mp-nonwifi-zinnia", + "toradex,verdin-imx8mp-nonwifi", + "toradex,verdin-imx8mp", + "fsl,imx8mp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-zinnia.dts b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-zinnia.dts new file mode 100644 index 000000000000..85eb56524314 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-zinnia.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-plus + * https://www.toradex.com/products/carrier-board/zinnia-carrier-board + */ + +/dts-v1/; + +#include "imx8mp-verdin.dtsi" +#include "imx8mp-verdin-wifi.dtsi" +#include "imx8mp-verdin-zinnia.dtsi" + +/ { + model = "Toradex Verdin iMX8M Plus WB on Zinnia"; + compatible = "toradex,verdin-imx8mp-wifi-zinnia", + "toradex,verdin-imx8mp-wifi", + "toradex,verdin-imx8mp", + "fsl,imx8mp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-zinnia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-zinnia.dtsi new file mode 100644 index 000000000000..6beb2f2f4548 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-zinnia.dtsi @@ -0,0 +1,422 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Common dtsi for Verdin IMX8MP SoM on Zinnia carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-plus + * https://www.toradex.com/products/carrier-board/zinnia-carrier-board + */ + +#include +#include + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_zinnia_leds>; + + /* LED1 Red - SODIMM 48 - LED1_R */ + led-1 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; + }; + + /* LED1 Blue - SODIMM 46 - LED1_B */ + led-2 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + gpios = <&gpio5 01 GPIO_ACTIVE_HIGH>; + }; + + /* LED3 Red - SODIMM 44 - LED3_R */ + led-3 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <3>; + gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; + }; + + /* LED3 Green - SODIMM 54 - LED3_G */ + led-4 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <3>; + gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; + }; + + /* LED3 Blue - SODIMM 36 - LED3_B */ + led-5 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <3>; + gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>; + }; + + /* LED4 Red - SODIMM 34 - LED4_R */ + led-6 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <4>; + gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + }; + + /* LED4 Green - SODIMM 32 - LED4_G */ + led-7 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <4>; + gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; + }; + + /* LED4 Blue - SODIMM 30 - LED4_B */ + led-8 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <4>; + gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; + }; + }; + + zinnia-1v8-voltage { + compatible = "voltage-divider"; + full-ohms = <39000>; /* 12k + 27k */ + /* Verdin ADC_4 */ + io-channels = <&verdin_som_adc 4>; + output-ohms = <27000>; + }; + + zinnia-3v3-voltage { + compatible = "voltage-divider"; + full-ohms = <54000>; /* 27k + 27k */ + /* Verdin ADC_3 */ + io-channels = <&verdin_som_adc 5>; + output-ohms = <27000>; + }; + + zinnia-5v-voltage { + compatible = "voltage-divider"; + full-ohms = <39000>; /* 27k + 12k */ + /* Verdin ADC_2 */ + io-channels = <&verdin_som_adc 6>; + output-ohms = <12000>; + }; + + /* Zinnia Power Supply Input Voltage */ + zinnia-input-voltage { + compatible = "voltage-divider"; + full-ohms = <204700>; /* 200k + 4.7k */ + /* Verdin ADC_1 */ + io-channels = <&verdin_som_adc 7>; + output-ohms = <4700>; + }; +}; + +/* Verdin SPI_1 */ +&ecspi1 { + pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_uart2_cts_gpio>; + cs-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>, <&gpio5 9 GPIO_ACTIVE_LOW>; + + status = "okay"; + + tpm@1 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <1>; + spi-max-frequency = <18500000>; + }; +}; + +/* EEPROM on Zinnia */ +&eeprom_carrier_board { + status = "okay"; +}; + +/* Verdin ETH_1 */ +&eqos { + status = "okay"; +}; + +/* Verdin ETH_2 */ +&fec { + phy-handle = <ðphy2>; + phy-mode = "rgmii-id"; + + status = "okay"; +}; + +&verdin_eth2_mdio { + ethphy2: ethernet-phy@2 { + reg = <2>; + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + }; +}; + +/* Verdin CAN_1 */ +&flexcan1 { + status = "okay"; +}; + +&gpio1 { + gpio-line-names = + "DO1_EN", /* 0 */ /* SODIMM 206 */ + "DI1_EN", /* SODIMM 208 */ + "", + "", + "", + "DI1_RB", /* SODIMM 210 */ + "DO2_EN", /* SODIMM 212 */ + "DI2_RB", /* SODIMM 216 */ + "DI2_EN", /* SODIMM 218 */ + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 20 */ + "", + "", + "", + "", + "", + "", + "", + "", + ""; +}; + +&gpio2 { + gpio-line-names = + "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + ""; /* 20 */ +}; + +&gpio3 { + gpio-line-names = + "", /* 0 */ + "", + "", + "", + "", + "", + "DI3_RB", /* SODIMM 56 */ + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 20 */ + "", + "", + "", + "", + "", + "", + "", + "", + ""; +}; + +&gpio4 { + gpio-line-names = + "", /* 0 */ + "DI3_EN", /* SODIMM 222 */ + "", + "DO3_EN", /* SODIMM 220 */ + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 20 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 30 */ + ""; +}; + +&gpio5 { + gpio-line-names = + "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 20 */ + "", + "", + "", + "", + "", + "", + "", + "", + ""; +}; + +/* Temperature sensor on Zinnia */ +&hwmon_temp { + compatible = "ti,tmp1075"; + + status = "okay"; +}; + +/* Verdin I2C_1 */ +&i2c4 { + status = "okay"; +}; + +/* Verdin UART_1 */ +&uart1 { + status = "okay"; +}; + +/* Verdin UART_2 */ +&uart2 { + pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart2_rts>; + linux,rs485-enabled-at-boot-time; + rs485-rx-during-tx; + + status = "okay"; +}; + +/* Verdin UART_3 */ +&uart3 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usb3_0 { + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usb3_1 { + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>, + <&pinctrl_gpio2>, + <&pinctrl_gpio3>, + <&pinctrl_gpio4>, + <&pinctrl_gpio5>, + <&pinctrl_gpio6>, + <&pinctrl_gpio7>, + <&pinctrl_gpio8>, + <&pinctrl_qspi1_io0_gpio>; + + pinctrl_uart2_cts_gpio: gpio2io6grp { + fsl,pins = ; /* SODIMM 143 */ + }; + + pinctrl_qspi1_io0_gpio: gpio3io6grp { + fsl,pins = ; /* SODIMM 56 */ + }; + + pinctrl_zinnia_leds: zinnialedsgrp { + fsl,pins = + , /* SODIMM 30 */ + , /* SODIMM 32 */ + , /* SODIMM 34 */ + , /* SODIMM 36 */ + , /* SODIMM 44 */ + , /* SODIMM 46 */ + , /* SODIMM 48 */ + ; /* SODIMM 54 */ + }; +}; From 13d4890ca951d8aa6b43e1f03d5f44fe5451d6ec Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Thu, 9 Apr 2026 11:58:52 +0200 Subject: [PATCH 354/665] arm64: dts: freescale: imx95-verdin: Split UART_2 pinctrl group Some carrier board reuse the UART_2 control signals as GPIO, split the pinctrl RTS/CTS in separated nodes to maximize flexibility. Signed-off-by: Francesco Dolcini Signed-off-by: Frank Li --- .../arm64/boot/dts/freescale/imx95-verdin.dtsi | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx95-verdin.dtsi index d3737956e2f9..72e7f1e88409 100644 --- a/arch/arm64/boot/dts/freescale/imx95-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95-verdin.dtsi @@ -541,7 +541,7 @@ &lpuart7 { /* Verdin UART_2 */ &lpuart8 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart8>; + pinctrl-0 = <&pinctrl_uart8>, <&pinctrl_uart8_cts>, <&pinctrl_uart8_rts>; uart-has-rtscts; }; @@ -1058,12 +1058,20 @@ pinctrl_uart7: uart7grp { ; /* SODIMM 133 */ }; - /* Verdin UART_2 */ + /* Verdin UART_2 CTS */ + pinctrl_uart8_cts: uart8ctsgrp { + fsl,pins = ; /* SODIMM 143 */ + }; + + /* Verdin UART_2 RTS */ + pinctrl_uart8_rts: uart8rtsgrp { + fsl,pins = ; /* SODIMM 141 */ + }; + + /* Verdin UART_2 RX/TX */ pinctrl_uart8: uart8grp { fsl,pins = , /* SODIMM 139 */ - , /* SODIMM 137 */ - , /* SODIMM 143 */ - ; /* SODIMM 141 */ + ; /* SODIMM 137 */ }; /* On-module eMMC */ From 828a9ac30954667fe3053a0ead51a97023c37829 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Thu, 9 Apr 2026 11:58:53 +0200 Subject: [PATCH 355/665] arm64: dts: freescale: imx95-verdin: Add Zinnia Add Zinnia Carrier Board mated with Verdin iMX95. It features 1 x RS232, 1 x RS485, 1 x CAN, 3 x isolated digital I/O, 2 x GBit/s Ethernet, a mini PCIe slot with USB / SIM card connector for a modem, USB and SD card interfaces. Link: https://www.toradex.com/products/carrier-board/zinnia-carrier-board Signed-off-by: Francesco Dolcini Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../freescale/imx95-verdin-nonwifi-zinnia.dts | 21 + .../freescale/imx95-verdin-wifi-zinnia.dts | 21 + .../dts/freescale/imx95-verdin-zinnia.dtsi | 429 ++++++++++++++++++ 4 files changed, 473 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-zinnia.dts create mode 100644 arch/arm64/boot/dts/freescale/imx95-verdin-wifi-zinnia.dts create mode 100644 arch/arm64/boot/dts/freescale/imx95-verdin-zinnia.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 0fb1a7584ee8..576daf6727ed 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -522,11 +522,13 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-ivy.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-mallow.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-yavia.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-zinnia.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-ivy.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-mallow.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-yavia.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-zinnia.dtb imx95-15x15-evk-pcie0-ep-dtbs = imx95-15x15-evk.dtb imx-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk-pcie0-ep.dtb diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-zinnia.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-zinnia.dts new file mode 100644 index 000000000000..b9fa18f34e9a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-zinnia.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/zinnia-carrier-board + */ + +/dts-v1/; + +#include "imx95-verdin.dtsi" +#include "imx95-verdin-nonwifi.dtsi" +#include "imx95-verdin-zinnia.dtsi" + +/ { + model = "Toradex Verdin iMX95 on Zinnia Board"; + compatible = "toradex,verdin-imx95-nonwifi-zinnia", + "toradex,verdin-imx95-nonwifi", + "toradex,verdin-imx95", + "fsl,imx95"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-zinnia.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-zinnia.dts new file mode 100644 index 000000000000..789614796370 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-zinnia.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/zinnia-carrier-board + */ + +/dts-v1/; + +#include "imx95-verdin.dtsi" +#include "imx95-verdin-wifi.dtsi" +#include "imx95-verdin-zinnia.dtsi" + +/ { + model = "Toradex Verdin iMX95 WB on Zinnia Board"; + compatible = "toradex,verdin-imx95-wifi-zinnia", + "toradex,verdin-imx95-wifi", + "toradex,verdin-imx95", + "fsl,imx95"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-zinnia.dtsi b/arch/arm64/boot/dts/freescale/imx95-verdin-zinnia.dtsi new file mode 100644 index 000000000000..6409a6ead713 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-zinnia.dtsi @@ -0,0 +1,429 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Common dtsi for Verdin iMX95 SoM on Zinnia carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/zinnia-carrier-board + */ + +#include +#include + +/ { + aliases { + eeprom1 = &carrier_eeprom; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_zinnia_leds>; + + /* LED1 Red - SODIMM 48 - LED1_R */ + led-1 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>; + }; + + /* LED1 Blue - SODIMM 46 - LED1_B */ + led-2 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; + }; + + /* LED3 Red - SODIMM 44 - LED3_R */ + led-3 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <3>; + gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; + }; + + /* LED3 Green - SODIMM 54 - LED3_G */ + led-4 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <3>; + gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; + }; + + /* LED3 Blue - SODIMM 36 - LED3_B */ + led-5 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <3>; + gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + }; + + /* LED4 Red - SODIMM 34 - LED4_R */ + led-6 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <4>; + gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; + }; + + /* LED4 Green - SODIMM 32 - LED4_G */ + led-7 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <4>; + gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + }; + + /* LED4 Blue - SODIMM 30 - LED4_B */ + led-8 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <4>; + gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; + }; + }; + + /* Zinnia Power Supply Input Voltage */ + zinnia-1v8-voltage { + compatible = "voltage-divider"; + full-ohms = <39000>; /* 12k + 27k */ + /* Verdin ADC_4 */ + io-channels = <&adc1 3>; + output-ohms = <27000>; + }; + + zinnia-3v3-voltage { + compatible = "voltage-divider"; + full-ohms = <54000>; /* 27k + 27k */ + /* Verdin ADC_3 */ + io-channels = <&adc1 2>; + output-ohms = <27000>; + }; + + zinnia-5v-voltage { + compatible = "voltage-divider"; + full-ohms = <39000>; /* 27k + 12k */ + /* Verdin ADC_2 */ + io-channels = <&adc1 1>; + output-ohms = <12000>; + }; + + zinnia-input-voltage { + compatible = "voltage-divider"; + full-ohms = <204700>; /* 200k + 4.7k */ + /* Verdin ADC_1 */ + io-channels = <&adc1 0>; + output-ohms = <4700>; + }; +}; + +/* Verdin ADC_1, ADC_2, ADC_3 and ADC_4 */ +&adc1 { + status = "okay"; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&enetc_port0 { + status = "okay"; +}; + +/* Verdin ETH_2_RGMII */ +&enetc_port1 { + phy-handle = <ðphy2>; + phy-mode = "rgmii-id"; + + status = "okay"; +}; + +/* Verdin CAN_1 */ +&flexcan1 { + status = "okay"; +}; + +&gpio1 { + gpio-line-names = + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + ""; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, <&pinctrl_gpio3>; + gpio-line-names = + "DO1_EN", /* SODIMM 206 */ /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "DI1_EN", /* SODIMM 208 */ + "", + "", /* 20 */ + "", + "", + "", + "DI1_RB", /* SODIMM 210 */ + "", + "", + "", + "", + "", + "", /* 30 */ + ""; +}; + +&gpio3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio6>; + gpio-line-names = + "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 20 */ + "", + "", + "", + "", + "", + "", + "DI2_EN", /* SODIMM 218 */ + "", + "", + "", /* 30 */ + ""; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio5>; + gpio-line-names = + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 20 */ + "", + "", + "", + "", + "", + "", + "", + "DI2_RB", /* SODIMM 216 */ + ""; +}; + +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio4>, <&pinctrl_qspi1_io0_gpio>; + gpio-line-names = + "DI3_RB", /* SODIMM 56 */ /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "DO2_EN", /* SODIMM 212 */ + "", + "", + "", + "", + ""; +}; + +/* Verdin I2C_1 */ +&lpi2c4 { + status = "okay"; + + temperature-sensor@4f { + compatible = "ti,tmp1075"; + reg = <0x4f>; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin SPI_1 */ +&lpspi6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi6>, + <&pinctrl_spi1_cs>, + <&pinctrl_uart8_cts_gpio>; + cs-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>, + <&som_gpio_expander 13 GPIO_ACTIVE_LOW>, + <&gpio4 29 GPIO_ACTIVE_LOW>; + + tpm@2 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <2>; + spi-max-frequency = <18500000>; + }; +}; + +/* Verdin UART_3, used as the Linux console */ +&lpuart1 { + status = "okay"; +}; + +/* Verdin UART_1 */ +&lpuart7 { + status = "okay"; +}; + +/* Verdin UART_2, through RS485 transceiver */ +&lpuart8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8>, <&pinctrl_uart8_rts>; + rs485-rx-during-tx; + linux,rs485-enabled-at-boot-time; + + status = "okay"; +}; + +&netc_emdio { + ethphy2: ethernet-phy@2 { + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth2_rgmii_int>; + interrupt-parent = <&gpio1>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + }; +}; + +&som_gpio_expander { + gpio-line-names = + "DO3_EN", /* SODIMM 220 */ + "DI3_EN", /* SODIMM 222 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + ""; +}; + +/* Verdin USB_1 */ +&usb2 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usb3 { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + status = "okay"; +}; + +&scmi_iomuxc { + pinctrl_uart8_cts_gpio: uart8ctsgrp { + fsl,pins = ; /* SODIMM 143 */ + }; + + pinctrl_zinnia_leds: zinnialedsgrp { + fsl,pins = , /* SODIMM 30 */ + , /* SODIMM 32 */ + , /* SODIMM 34 */ + , /* SODIMM 36 */ + , /* SODIMM 44 */ + , /* SODIMM 46 */ + , /* SODIMM 48 */ + ; /* SODIMM 54 */ + }; +}; From 9f004f2afded2870838c0ae4906c2fa9307286bb Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Thu, 9 Apr 2026 11:33:04 +0200 Subject: [PATCH 356/665] arm64: dts: freescale: imx95-verdin-ivy: fix RS485 RTS polarity Fix the RS485 functionality, the RS485 RTS signal is active high on Ivy. Fixes: f33a1f9a942c ("arm64: dts: freescale: imx95-verdin: Add Ivy carrier board") Signed-off-by: Francesco Dolcini Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95-verdin-ivy.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-ivy.dtsi b/arch/arm64/boot/dts/freescale/imx95-verdin-ivy.dtsi index 8337c8b25f05..ff31f7c48cfb 100644 --- a/arch/arm64/boot/dts/freescale/imx95-verdin-ivy.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-ivy.dtsi @@ -452,7 +452,6 @@ &lpuart7 { /* Verdin UART_2, through RS485 transceiver */ &lpuart8 { - rs485-rts-active-low; rs485-rx-during-tx; linux,rs485-enabled-at-boot-time; From 8a7c502c1e6e8dee65186698c198174a026f2ec2 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 22 Apr 2026 23:09:23 +0200 Subject: [PATCH 357/665] arm64: dts: imx8mn: Sort ifm VHIP4 EvalBoard Makefile entries Sort the Makefile entries alphabetically. No functional change. Signed-off-by: Marek Vasut Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 576daf6727ed..d8378ae07093 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -208,10 +208,10 @@ imx8mn-vhip4-evalboard-v1-overlay-ksz8794-dtbs := imx8mn-vhip4-evalboard-v1.dtb imx8mn-vhip4-evalboard-v1-overlay-ksz8794.dtbo imx8mn-vhip4-evalboard-v1-overlay-ksz9031-dtbs := imx8mn-vhip4-evalboard-v1.dtb \ imx8mn-vhip4-evalboard-v1-overlay-ksz9031.dtbo -imx8mn-vhip4-evalboard-v2-overlay-ksz8794-dtbs := imx8mn-vhip4-evalboard-v2.dtb \ - imx8mn-vhip4-evalboard-v2-overlay-ksz8794.dtbo imx8mn-vhip4-evalboard-v2-overlay-adin1300-dtbs := imx8mn-vhip4-evalboard-v2.dtb \ imx8mn-vhip4-evalboard-v2-overlay-adin1300.dtbo +imx8mn-vhip4-evalboard-v2-overlay-ksz8794-dtbs := imx8mn-vhip4-evalboard-v2.dtb \ + imx8mn-vhip4-evalboard-v2-overlay-ksz8794.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mn-vhip4-evalboard-v1.dtb \ imx8mn-vhip4-evalboard-v1-overlay-ksz8794.dtb \ imx8mn-vhip4-evalboard-v1-overlay-ksz8794.dtbo \ From 8cd439f177589ca754ab27056905f57261048f9f Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Wed, 6 May 2026 13:53:14 +0800 Subject: [PATCH 358/665] arm64: dts: imx94: Add pcie0 and pcie0-ep supports Add pcie0 and pcie0-ep supports. Signed-off-by: Richard Zhu Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx94.dtsi | 88 ++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi index c460ece6070f..589f4aadc742 100644 --- a/arch/arm64/boot/dts/freescale/imx94.dtsi +++ b/arch/arm64/boot/dts/freescale/imx94.dtsi @@ -67,6 +67,13 @@ sai4_mclk: clock-sai4-mclk1 { clock-output-names = "sai4_mclk"; }; + clk_sys100m: clock-sys100m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "clk_sys100m"; + }; + firmware { scmi { compatible = "arm,scmi"; @@ -1286,6 +1293,14 @@ wdog3: watchdog@49220000 { }; }; + hsio_blk_ctl: syscon@4c0100c0 { + compatible = "nxp,imx95-hsio-blk-ctl", "syscon"; + reg = <0x0 0x4c0100c0 0x0 0x1>; + #clock-cells = <1>; + clocks = <&clk_sys100m>; + power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>; + }; + usb3: usb@4c100000 { compatible = "nxp,imx94-dwc3", "nxp,imx8mp-dwc3"; reg = <0x0 0x4c100000 0x0 0x10000>, @@ -1340,6 +1355,79 @@ usbmisc: usbmisc@4c200200 { #index-cells = <1>; }; + pcie0: pcie@4c300000 { + compatible = "fsl,imx94-pcie", "fsl,imx95-pcie"; + reg = <0 0x4c300000 0 0x10000>, + <0 0x60100000 0 0xfe00000>, + <0 0x4c360000 0 0x10000>, + <0 0x4c340000 0 0x4000>; + reg-names = "dbi", "config", "atu", "app"; + ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>, + <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x80000000>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + linux,pci-domain = <2>; + msi-map = <0x0 &its 0x10 0x1>, + <0x100 &its 0x11 0x7>; + msi-map-mask = <0x1ff>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + num-viewport = <8>; + interrupts = , + ; + interrupt-names = "msi", "dma"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX94_CLK_HSIO>, + <&scmi_clk IMX94_CLK_HSIOPLL>, + <&scmi_clk IMX94_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX94_CLK_HSIOPCIEAUX>, + <&hsio_blk_ctl 0>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; + assigned-clocks = <&scmi_clk IMX94_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX94_CLK_HSIOPLL>, + <&scmi_clk IMX94_CLK_HSIOPCIEAUX>; + assigned-clock-rates = <3600000000>, <100000000>, <10000000>; + assigned-clock-parents = <0>, <0>, + <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>; + power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>; + fsl,max-link-speed = <3>; + status = "disabled"; + }; + + pcie0_ep: pcie-ep@4c300000 { + compatible = "fsl,imx94-pcie-ep", "fsl,imx95-pcie-ep"; + reg = <0 0x4c300000 0 0x10000>, + <0 0x4c360000 0 0x1000>, + <0 0x4c320000 0 0x1000>, + <0 0x4c340000 0 0x4000>, + <0 0x4c370000 0 0x10000>, + <0x9 0 1 0>; + reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space"; + num-lanes = <1>; + interrupts = ; + interrupt-names = "dma"; + clocks = <&scmi_clk IMX94_CLK_HSIO>, + <&scmi_clk IMX94_CLK_HSIOPLL>, + <&scmi_clk IMX94_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX94_CLK_HSIOPCIEAUX>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + assigned-clocks = <&scmi_clk IMX94_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX94_CLK_HSIOPLL>, + <&scmi_clk IMX94_CLK_HSIOPCIEAUX>; + assigned-clock-rates = <3600000000>, <100000000>, <10000000>; + assigned-clock-parents = <0>, <0>, + <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>; + msi-map = <0x0 &its 0x10 0x1>; + power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>; + status = "disabled"; + }; + netc_blk_ctrl: system-controller@4ceb0000 { compatible = "nxp,imx94-netc-blk-ctrl"; reg = <0x0 0x4ceb0000 0x0 0x10000>, From fa6067fd8ea7b5a287863d160841b76c7ace9019 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Wed, 6 May 2026 13:53:15 +0800 Subject: [PATCH 359/665] arm64: dts: imx943: Add pcie1 and pcie1-ep supports Add pcie1 and pcie1-ep supports. Signed-off-by: Richard Zhu Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx943.dtsi | 75 +++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi index dfd956ece2e3..ed030d4bc7bd 100644 --- a/arch/arm64/boot/dts/freescale/imx943.dtsi +++ b/arch/arm64/boot/dts/freescale/imx943.dtsi @@ -209,4 +209,79 @@ map0 { }; }; }; + + soc { + pcie1: pcie@4c380000 { + compatible = "fsl,imx943-pcie", "fsl,imx95-pcie"; + reg = <0 0x4c380000 0 0x10000>, + <8 0x80100000 0 0xfe00000>, + <0 0x4c3e0000 0 0x10000>, + <0 0x4c3c0000 0 0x4000>; + reg-names = "dbi", "config", "atu", "app"; + ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>, + <0x82000000 0 0x10000000 0xa 0x10000000 0 0x80000000>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + linux,pci-domain = <3>; + msi-map = <0x0 &its 0x98 0x1>, + <0x100 &its 0x99 0x7>; + msi-map-mask = <0x1ff>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + num-viewport = <8>; + interrupts = , + ; + interrupt-names = "msi", "dma"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX94_CLK_HSIO>, + <&scmi_clk IMX94_CLK_HSIOPLL>, + <&scmi_clk IMX94_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX94_CLK_HSIOPCIEAUX>, + <&hsio_blk_ctl 0>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; + assigned-clocks = <&scmi_clk IMX94_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX94_CLK_HSIOPLL>, + <&scmi_clk IMX94_CLK_HSIOPCIEAUX>; + assigned-clock-rates = <3600000000>, <100000000>, <10000000>; + assigned-clock-parents = <0>, <0>, + <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>; + power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>; + fsl,max-link-speed = <3>; + status = "disabled"; + }; + + pcie1_ep: pcie-ep@4c380000 { + compatible = "fsl,imx943-pcie-ep", "fsl,imx95-pcie-ep"; + reg = <0 0x4c380000 0 0x10000>, + <0 0x4c3e0000 0 0x1000>, + <0 0x4c3a0000 0 0x1000>, + <0 0x4c3c0000 0 0x4000>, + <0 0x4c3f0000 0 0x10000>, + <0xa 0 1 0>; + reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space"; + num-lanes = <1>; + interrupts = ; + interrupt-names = "dma"; + clocks = <&scmi_clk IMX94_CLK_HSIO>, + <&scmi_clk IMX94_CLK_HSIOPLL>, + <&scmi_clk IMX94_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX94_CLK_HSIOPCIEAUX>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + assigned-clocks = <&scmi_clk IMX94_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX94_CLK_HSIOPLL>, + <&scmi_clk IMX94_CLK_HSIOPCIEAUX>; + assigned-clock-rates = <3600000000>, <100000000>, <10000000>; + assigned-clock-parents = <0>, <0>, + <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>; + msi-map = <0x0 &its 0x98 0x1>; + power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>; + status = "disabled"; + }; + }; }; From 9a8f11f6f786f42b35c9b0944a2b87052d28cd48 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Wed, 6 May 2026 13:53:16 +0800 Subject: [PATCH 360/665] arm64: dts: imx943-evk: Add pcie[0,1] and pcie-ep[0,1] support Add pcie[0,1] and pcie-ep[0,1] support. Signed-off-by: Richard Zhu Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 5 ++ arch/arm64/boot/dts/freescale/imx943-evk.dts | 83 ++++++++++++++++++++ 2 files changed, 88 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index d8378ae07093..48fbf9c33b65 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -509,6 +509,11 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-var-dart-sonata.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx93w-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx943-evk.dtb + +imx943-evk-pcie0-ep-dtbs += imx943-evk.dtb imx-pcie0-ep.dtbo +imx943-evk-pcie1-ep-dtbs += imx943-evk.dtb imx-pcie1-ep.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx943-evk-pcie0-ep.dtb imx943-evk-pcie1-ep.dtb + dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-ab2.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-frdm.dtb diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts index 52f7ef7dbf27..fe4fc512d95d 100644 --- a/arch/arm64/boot/dts/freescale/imx943-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts @@ -58,6 +58,20 @@ chosen { stdout-path = &lpuart1; }; + pcie_ref_clk: clock-pcie-ref { + compatible = "gpio-gate-clock"; + clocks = <&xtal25m>; + #clock-cells = <0>; + enable-gpios = <&pca9670_i2c3 7 GPIO_ACTIVE_LOW>; + }; + + xtal25m: clock-xtal25m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "xtal_25MHz"; + }; + dmic: dmic { compatible = "dmic-codec"; #sound-dai-cells = <0>; @@ -79,6 +93,15 @@ reg_m2_pwr: regulator-m2-pwr { startup-delay-us = <5000>; }; + reg_slot_pwr: regulator-slot-pwr { + compatible = "regulator-fixed"; + regulator-name = "PCIe slot-power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6416_i2c3_u46 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_m2_wlan: regulator-wlan { compatible = "regulator-fixed"; regulator-name = "WLAN_EN"; @@ -725,6 +748,18 @@ IMX94_PAD_GPIO_IO28__LPI2C6_SCL 0x40000b9e >; }; + pinctrl_pcie0: pcie0grp { + fsl,pins = < + IMX94_PAD_GPIO_IO20__PCIE1_CLKREQ_B 0x4000031e + >; + }; + + pinctrl_pcie1: pcie1grp { + fsl,pins = < + IMX94_PAD_GPIO_IO23__PCIE2_CLKREQ_B 0x4000031e + >; + }; + pinctrl_pdm: pdmgrp { fsl,pins = < IMX94_PAD_PDM_CLK__PDM_CLK 0x31e @@ -988,6 +1023,54 @@ pf5302_crit: trip1 { }; }; +&pcie0 { + pinctrl-0 = <&pinctrl_pcie0>; + pinctrl-names = "default"; + clocks = <&scmi_clk IMX94_CLK_HSIO>, + <&scmi_clk IMX94_CLK_HSIOPLL>, + <&scmi_clk IMX94_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX94_CLK_HSIOPCIEAUX>, + <&hsio_blk_ctl 0>, + <&pcie_ref_clk>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", + "ref", "extref"; + reset-gpio = <&pcal6416_i2c3_u46 3 GPIO_ACTIVE_LOW>; + vpcie3v3aux-supply = <®_m2_wlan>; + supports-clkreq; + status = "okay"; +}; + +&pcie0_ep { + pinctrl-0 = <&pinctrl_pcie0>; + pinctrl-names = "default"; + vpcie-supply = <®_m2_wlan>; + status = "disabled"; +}; + +&pcie1 { + pinctrl-0 = <&pinctrl_pcie1>; + pinctrl-names = "default"; + clocks = <&scmi_clk IMX94_CLK_HSIO>, + <&scmi_clk IMX94_CLK_HSIOPLL>, + <&scmi_clk IMX94_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX94_CLK_HSIOPCIEAUX>, + <&hsio_blk_ctl 0>, + <&pcie_ref_clk>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", + "ref", "extref"; + reset-gpio = <&pcal6416_i2c3_u46 1 GPIO_ACTIVE_LOW>; + vpcie3v3aux-supply = <®_slot_pwr>; + supports-clkreq; + status = "okay"; +}; + +&pcie1_ep { + pinctrl-0 = <&pinctrl_pcie1>; + pinctrl-names = "default"; + vpcie-supply = <®_slot_pwr>; + status = "disabled"; +}; + &usb2 { dr_mode = "otg"; disable-over-current; From 0549cdb08a846babf44ea97a03d866dbcfc17873 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Thu, 7 May 2026 14:53:28 +0800 Subject: [PATCH 361/665] arm64: dts: imx8mp-evk: Disable PCIe bus in the default dts Disable the PCIe bus in the default device tree to avoid shared regulator conflicts between SDIO and PCIe buses. The non-deterministic probe order between these two buses can break the PCIe initialization sequence, causing PCIe devices to fail detection intermittently. On i.MX8MP EVK board, the M.2 connector is physically wired to both USDHC1 and PCIe0, however the out-of-box module is SDIO IW612 WiFi, so enable the SDIO WiFi in the default imx8mp-evk.dts. Add 'm2_usdhc' label to USDHC1 to support device tree overlay for PCIe modules. Users who need PCIe can use imx8mp-evk-pcie.dtb (added in a follow-up patch) which applies an overlay to enable PCIe and disable USDHC1. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index d0a2bd975a18..2feb5b18645c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -774,7 +774,7 @@ &pcie0 { vpcie-supply = <®_pcie0>; vpcie3v3aux-supply = <®_pcie0>; supports-clkreq; - status = "okay"; + status = "disabled"; }; &pcie0_ep { @@ -870,7 +870,7 @@ &uart3 { status = "okay"; }; -&usdhc1 { +m2_usdhc: &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; pinctrl-1 = <&pinctrl_usdhc1_100mhz>; From bb97f6f67cc9c7d82aaee7eee9b9c0273050264e Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Thu, 7 May 2026 14:53:29 +0800 Subject: [PATCH 362/665] arm64: dts: imx95-15x15-evk: Disable PCIe bus in the default dts Disable the PCIe bus in the default device tree to avoid shared regulator conflicts between SDIO and PCIe buses. The non-deterministic probe order between these two buses can break the PCIe initialization sequence, causing PCIe devices to fail detection intermittently. On i.MX95-15x15 EVK board, the M.2 connector is physically wired to both USDHC3 and PCIe0, however the out-of-box module is SDIO IW612 WiFi, so enable SDIO WiFi in the default imx95-15x15-evk.dts. Add 'm2_usdhc' label to USDHC3 to support device tree overlay for PCIe modules. Users who need PCIe can use imx95-15x15-evk-pcie.dtb (added in a follow-up patch) which applies an overlay to enable PCIe and disable USDHC3. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts index 7eb12e7d5014..e4649d7f9122 100644 --- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts @@ -557,7 +557,7 @@ &pcie0 { vpcie-supply = <®_m2_pwr>; vpcie3v3aux-supply = <®_m2_pwr>; supports-clkreq; - status = "okay"; + status = "disabled"; }; &pcie0_ep { @@ -1137,7 +1137,7 @@ &usdhc2 { status = "okay"; }; -&usdhc3 { +m2_usdhc: &usdhc3 { bus-width = <4>; keep-power-in-suspend; mmc-pwrseq = <&usdhc3_pwrseq>; From 56cf0c79f598a5c24ec32d6ade206b9c62b1fcf8 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Thu, 7 May 2026 14:53:30 +0800 Subject: [PATCH 363/665] arm64: dts: imx: Add common imx-m2-pcie.dtso to enable PCIe on M.2 connector Some i.MX boards (i.MX8MP EVK and i.MX95-15x15 EVK) have M.2 connectors that are physically wired to both USDHC and PCIe controllers. The default device tree enables USDHC for SDIO WiFi modules and disables PCIe to avoid regulator conflicts. Add a common imx-m2-pcie.dtso that can be applied to enable PCIe and disable USDHC when a PCIe module is installed in the M.2 connector. This creates the following DTB files: - imx8mp-evk-pcie.dtb: i.MX8MP EVK with PCIe enabled - imx95-15x15-evk-pcie.dtb: i.MX95-15x15 EVK with PCIe enabled Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 9 +++++++-- arch/arm64/boot/dts/freescale/imx-m2-pcie.dtso | 15 +++++++++++++++ 2 files changed, 22 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/imx-m2-pcie.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 48fbf9c33b65..0a4dabac5de4 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -360,12 +360,14 @@ imx8mp-evk-lvds0-imx-lvds-hdmi-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds0-imx-lvds- imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtbo imx8mp-evk-lvds1-imx-lvds-hdmi-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds1-imx-lvds-hdmi.dtbo imx8mp-evk-mx8-dlvds-lcd1-dtbs += imx8mp-evk.dtb imx8mp-evk-mx8-dlvds-lcd1.dtbo -imx8mp-evk-pcie-ep-dtbs += imx8mp-evk.dtb imx-pcie0-ep.dtbo +imx8mp-evk-pcie-dtbs += imx8mp-evk.dtb imx-m2-pcie.dtbo +imx8mp-evk-pcie-ep-dtbs += imx8mp-evk-pcie.dtb imx-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds0-imx-lvds-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds1-imx-lvds-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-mx8-dlvds-lcd1.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-pcie.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-pcie-ep.dtb imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33-dtbs += imx8mp-tqma8mpql-mba8mpxl.dtb imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtbo @@ -535,7 +537,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-mallow.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-yavia.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-zinnia.dtb -imx95-15x15-evk-pcie0-ep-dtbs = imx95-15x15-evk.dtb imx-pcie0-ep.dtbo +imx95-15x15-evk-pcie-dtbs += imx95-15x15-evk.dtb imx-m2-pcie.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk-pcie.dtb + +imx95-15x15-evk-pcie0-ep-dtbs = imx95-15x15-evk-pcie.dtb imx-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk-pcie0-ep.dtb imx95-19x19-evk-pcie0-ep-dtbs += imx95-19x19-evk.dtb imx-pcie0-ep.dtbo imx95-19x19-evk-pcie1-ep-dtbs += imx95-19x19-evk.dtb imx-pcie1-ep.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx-m2-pcie.dtso b/arch/arm64/boot/dts/freescale/imx-m2-pcie.dtso new file mode 100644 index 000000000000..1930de058a08 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx-m2-pcie.dtso @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 NXP + */ + +/dts-v1/; +/plugin/; + +&pcie0 { + status = "okay"; +}; + +&m2_usdhc { + status = "disabled"; +}; From 54d60132995b7c516c7a531975d8bc5d9187ce04 Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Tue, 7 Apr 2026 17:15:31 +0800 Subject: [PATCH 364/665] arm64: dts: imx93-9x9-qsb: Add tianma,tm050rdh03 panel Support tianma,tm050rdh03 DPI panel on i.MX93 9x9 QSB. Move the common parts from imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtso into imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtsi for reuse by the tm050rdh03 overlay file. The panel connects with the QSB board through an adapter board[1] designed by NXP. Link: https://www.nxp.com/design/design-center/development-boards-and-designs/parallel-lcd-display:TM050RDH03-41 [1] Signed-off-by: Liu Ying Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtsi | 110 ++++++++++++++++++ .../imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtso | 106 +---------------- .../imx93-9x9-qsb-tianma-tm050rdh03.dtso | 14 +++ 4 files changed, 127 insertions(+), 105 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx93-9x9-qsb-tianma-tm050rdh03.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 0a4dabac5de4..513f61eb27b8 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -464,9 +464,11 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb imx93-9x9-qsb-can1-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-can1.dtbo imx93-9x9-qsb-i3c-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-i3c.dtbo imx93-9x9-qsb-ontat-kd50g21-40nt-a1-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtbo +imx93-9x9-qsb-tianma-tm050rdh03-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-tianma-tm050rdh03.dtbo dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-can1.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-i3c.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-tianma-tm050rdh03.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-frdm.dtb diff --git a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtsi b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtsi new file mode 100644 index 000000000000..d167c9fc3b8f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtsi @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 NXP + */ + +/dts-v1/; +/plugin/; + +#include +#include "imx93-pinfunc.h" + +&{/} { + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&pcal6524 2 GPIO_ACTIVE_HIGH>; + }; + + panel { + compatible = "ontat,kd50g21-40nt-a1"; + backlight = <&backlight>; + power-supply = <®_rpi_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&dpi_to_panel>; + }; + }; + }; +}; + +&dpi_bridge { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dpi_to_panel: endpoint { + remote-endpoint = <&panel_in>; + bus-width = <18>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x31e + MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x31e + MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x31e + MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x31e + MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x31e + MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x31e + MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x31e + MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x31e + MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x31e + MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x31e + MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x31e + MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x31e + MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x31e + MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x31e + MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x31e + MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x31e + MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x31e + MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x31e + MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x31e + MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x31e + MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x31e + MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x31e + >; + }; +}; + +&lcdif { + status = "okay"; +}; + +&media_blk_ctrl { + status = "okay"; +}; + +&pcal6524 { + /* + * exp-sel-hog has property 'output-low' while DT overlay doesn't + * support /delete-property/. Both 'output-low' and 'output-high' + * will exist under hog nodes if DT overlay file sets 'output-high'. + * Workaround is to disable this hog and create new hog with + * 'output-high'. + */ + exp-sel-hog { + status = "disabled"; + }; + + exp-high-sel-hog { + gpio-hog; + gpios = <22 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&sai3 { + /* disable due to GPIO12 and GPIO17~20 pin conflicts with LCDIF */ + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtso b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtso index d167c9fc3b8f..356533a7b513 100644 --- a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtso +++ b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtso @@ -3,108 +3,4 @@ * Copyright 2026 NXP */ -/dts-v1/; -/plugin/; - -#include -#include "imx93-pinfunc.h" - -&{/} { - backlight: backlight { - compatible = "gpio-backlight"; - gpios = <&pcal6524 2 GPIO_ACTIVE_HIGH>; - }; - - panel { - compatible = "ontat,kd50g21-40nt-a1"; - backlight = <&backlight>; - power-supply = <®_rpi_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&dpi_to_panel>; - }; - }; - }; -}; - -&dpi_bridge { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - dpi_to_panel: endpoint { - remote-endpoint = <&panel_in>; - bus-width = <18>; - }; - }; - }; -}; - -&iomuxc { - pinctrl_lcdif: lcdifgrp { - fsl,pins = < - MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x31e - MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x31e - MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x31e - MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x31e - MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x31e - MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x31e - MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x31e - MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x31e - MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x31e - MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x31e - MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x31e - MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x31e - MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x31e - MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x31e - MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x31e - MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x31e - MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x31e - MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x31e - MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x31e - MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x31e - MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x31e - MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x31e - >; - }; -}; - -&lcdif { - status = "okay"; -}; - -&media_blk_ctrl { - status = "okay"; -}; - -&pcal6524 { - /* - * exp-sel-hog has property 'output-low' while DT overlay doesn't - * support /delete-property/. Both 'output-low' and 'output-high' - * will exist under hog nodes if DT overlay file sets 'output-high'. - * Workaround is to disable this hog and create new hog with - * 'output-high'. - */ - exp-sel-hog { - status = "disabled"; - }; - - exp-high-sel-hog { - gpio-hog; - gpios = <22 GPIO_ACTIVE_HIGH>; - output-high; - }; -}; - -&sai3 { - /* disable due to GPIO12 and GPIO17~20 pin conflicts with LCDIF */ - status = "disabled"; -}; +#include "imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-tianma-tm050rdh03.dtso b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-tianma-tm050rdh03.dtso new file mode 100644 index 000000000000..c233797ec28c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-tianma-tm050rdh03.dtso @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 NXP + */ + +#include +#include "imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtsi" + +&{/} { + panel { + compatible = "tianma,tm050rdh03"; + enable-gpios = <&pcal6524 8 GPIO_ACTIVE_HIGH>; + }; +}; From 3c862bdf2e2ecd30683fe0b1e8871194845fc171 Mon Sep 17 00:00:00 2001 From: Maud Spierings Date: Tue, 7 Apr 2026 16:41:44 +0200 Subject: [PATCH 365/665] arm64: dts: freescale: moduline-display-av101hdt-a10: add backlight Add the missing backlight driver. Signed-off-by: Maud Spierings Signed-off-by: Frank Li --- ...l81-moduline-display-106-av101hdt-a10.dtso | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtso b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtso index c6fc5d5b1e5f..23e4bf64b28b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtso @@ -17,6 +17,7 @@ panel { compatible = "boe,av101hdt-a10"; + backlight = <&backlight>; enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; pinctrl-0 = <&pinctrl_panel>; pinctrl-names = "default"; @@ -40,7 +41,30 @@ reg_vbus: regulator-vbus { }; }; +&i2c4 { + #address-cells = <1>; + #size-cells = <0>; + + backlight: backlight@6f { + compatible = "maxim,max25014"; + reg = <0x6f>; + default-brightness = <50>; + enable-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + maxim,iset = <7>; + maxim,strings = <1 1 1 0>; + }; +}; + &iomuxc { + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 + (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + >; + }; + pinctrl_panel: panelgrp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 From 85794a56afe9c580136424c375e46e40c7326dce Mon Sep 17 00:00:00 2001 From: Maud Spierings Date: Tue, 7 Apr 2026 16:41:45 +0200 Subject: [PATCH 366/665] arm64: dts: freescale: moduline-display-av123z7m-n17: add backlight Add the missing backlight. Signed-off-by: Maud Spierings Signed-off-by: Frank Li --- ...l81-moduline-display-106-av123z7m-n17.dtso | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17.dtso b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17.dtso index 3eb665ce9d5d..0b969c8c04db 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17.dtso @@ -16,6 +16,7 @@ panel { compatible = "boe,av123z7m-n17"; + backlight = <&backlight>; enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; pinctrl-0 = <&pinctrl_panel>; pinctrl-names = "default"; @@ -91,10 +92,26 @@ lvds1_out: endpoint { }; }; - /* max25014 @ 0x6f */ + backlight: backlight@6f { + compatible = "maxim,max25014"; + reg = <0x6f>; + default-brightness = <50>; + enable-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + maxim,iset = <7>; + maxim,strings = <1 1 1 1>; + }; }; &iomuxc { + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 + (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + >; + }; + pinctrl_lvds_bridge: lvdsbridgegrp { fsl,pins = < MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 From 5601ee1b64da17d2df2e657a7f1582ad468ed4d2 Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Thu, 7 May 2026 08:20:56 +0200 Subject: [PATCH 367/665] arm64: dts: freescale: imx{91,93}-phycore-som: Set BUCK5 in FPWM mode Set PMIC BUCK5 mode to forced PWM (Pulse Width Modulation) mode instead of the default automatic PFM and PWM transition mode. FPWM mode produces less ripple on the output voltage rail under light load conditions. And since BUCK5 supplies SoC internal ADC reference voltage we need to keep voltage ripple to a minimum. This solves issues with the occasional ADC calibration procedure failures on phyCORE-i.MX91/93 SoM based boards. Signed-off-by: Primoz Fiser Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi | 2 ++ arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi index b9a453f6b290..95a6a0b1dd75 100644 --- a/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi @@ -8,6 +8,7 @@ */ #include +#include #include "imx91.dtsi" @@ -160,6 +161,7 @@ buck5: BUCK5 { regulator-min-microvolt = <1800000>; regulator-boot-on; regulator-always-on; + regulator-initial-mode = ; }; buck6: BUCK6 { diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi index 94eb04ace96e..d59a89254623 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi @@ -9,6 +9,7 @@ */ #include +#include #include "imx93.dtsi" @@ -162,6 +163,7 @@ buck5: BUCK5 { regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; + regulator-initial-mode = ; }; buck6: BUCK6 { From e1b256ccc5cc3fc59a67a261d711bbbb989d7512 Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Thu, 7 May 2026 08:20:57 +0200 Subject: [PATCH 368/665] arm64: dts: freescale: imx{91,93}-phycore-som: Adjust PHY RST drive-strength According to measurements, the PHY reset signal shows an overshoot on the rising edge that exceeds the specified limits (max 2.1V) when using X4 strength on ENET2_RXC. Reduce drive-strength to X1 to decrease the overshoot and bring signal within specification limits. Signed-off-by: Primoz Fiser Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi index 95a6a0b1dd75..1d8adfd34e92 100644 --- a/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi @@ -242,7 +242,7 @@ MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x50e MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x50e MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x50e MX91_PAD_ENET2_TD2__ENET2_TX_CLK2 0x4000050e - MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e + MX91_PAD_ENET2_RXC__GPIO4_IO23 0x502 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi index d59a89254623..5148101def31 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi @@ -244,7 +244,7 @@ MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x50e MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x50e MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x50e MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x4000050e - MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e + MX93_PAD_ENET2_RXC__GPIO4_IO23 0x502 >; }; From a6254c90e14b5b9d0b2222b2121598fe12f55ca5 Mon Sep 17 00:00:00 2001 From: Christoph Stoidner Date: Thu, 7 May 2026 08:20:58 +0200 Subject: [PATCH 369/665] arm64: dts: freescale: imx{91,93}-phycore-som: Improve USDHC signals Apply improved drive-strength values and pull-up/down configurations as devised from hardware measurements to improve signal quality on PHYTEC phyCORE-i.MX 91/93 SoM based boards. Also improve eMMC HS400 mode by setting property "fsl,strobe-dll-delay-target" which shifts the strobe DLL sampling window to the optimal position. Signed-off-by: Christoph Stoidner Signed-off-by: Primoz Fiser Signed-off-by: Frank Li --- .../boot/dts/freescale/imx91-phyboard-segin.dts | 6 +++--- .../arm64/boot/dts/freescale/imx91-phycore-som.dtsi | 13 +++++++------ .../boot/dts/freescale/imx93-phyboard-nash.dts | 8 ++++---- .../boot/dts/freescale/imx93-phyboard-segin.dts | 6 +++--- .../arm64/boot/dts/freescale/imx93-phycore-som.dtsi | 13 +++++++------ 5 files changed, 24 insertions(+), 22 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts index 8b19fc17eacd..022e9c6841ef 100644 --- a/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts +++ b/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts @@ -327,7 +327,7 @@ MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e pinctrl_usdhc2_default: usdhc2grp { fsl,pins = < - MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX91_PAD_SD2_CLK__USDHC2_CLK 0x118e MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382 MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1386 MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e @@ -339,7 +339,7 @@ MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < - MX91_PAD_SD2_CLK__USDHC2_CLK 0x159e + MX91_PAD_SD2_CLK__USDHC2_CLK 0x119e MX91_PAD_SD2_CMD__USDHC2_CMD 0x139e MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e @@ -351,7 +351,7 @@ MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < - MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX91_PAD_SD2_CLK__USDHC2_CLK 0x118e MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x139e MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x139e diff --git a/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi index 1d8adfd34e92..8b8cb3daecbb 100644 --- a/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi @@ -216,6 +216,7 @@ &usdhc1 { bus-width = <8>; non-removable; no-1-8-v; + fsl,strobe-dll-delay-target = <1>; status = "okay"; }; @@ -274,7 +275,7 @@ MX91_PAD_ENET2_RD3__GPIO4_IO27 0x31e pinctrl_usdhc1: usdhc1grp { fsl,pins = < - MX91_PAD_SD1_CLK__USDHC1_CLK 0x179e + MX91_PAD_SD1_CLK__USDHC1_CLK 0x119e MX91_PAD_SD1_CMD__USDHC1_CMD 0x1386 MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1386 @@ -284,13 +285,13 @@ MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1386 MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1386 MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1386 MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1386 - MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x179e + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x159e >; }; pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < - MX91_PAD_SD1_CLK__USDHC1_CLK 0x17be + MX91_PAD_SD1_CLK__USDHC1_CLK 0x11be MX91_PAD_SD1_CMD__USDHC1_CMD 0x139e MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x139e @@ -300,13 +301,13 @@ MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x139e MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x139e MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x139e MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x139e - MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x179e + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x159e >; }; pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < - MX91_PAD_SD1_CLK__USDHC1_CLK 0x17be + MX91_PAD_SD1_CLK__USDHC1_CLK 0x11be MX91_PAD_SD1_CMD__USDHC1_CMD 0x139e MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x139e MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13be @@ -316,7 +317,7 @@ MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13be MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13be MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13be MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13be - MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x179e + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x159e >; }; diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts index b82192f25498..f868ed5c2c29 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts @@ -370,8 +370,8 @@ MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc2_default: usdhc2grp { fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e - MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000178e + MX93_PAD_SD2_CLK__USDHC2_CLK 0x119e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001386 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001386 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001386 @@ -383,7 +383,7 @@ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e + MX93_PAD_SD2_CLK__USDHC2_CLK 0x119e MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e @@ -396,7 +396,7 @@ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e + MX93_PAD_SD2_CLK__USDHC2_CLK 0x119e MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts index 4e4356397ba0..d929aa9ff255 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts @@ -328,7 +328,7 @@ MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc2_default: usdhc2grp { fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e + MX93_PAD_SD2_CLK__USDHC2_CLK 0x119e MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e @@ -341,7 +341,7 @@ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e + MX93_PAD_SD2_CLK__USDHC2_CLK 0x119e MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e @@ -354,7 +354,7 @@ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX93_PAD_SD2_CLK__USDHC2_CLK 0x118e MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi index 5148101def31..325e465d0056 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi @@ -218,6 +218,7 @@ &usdhc1 { bus-width = <8>; non-removable; no-1-8-v; + fsl,strobe-dll-delay-target = <1>; status = "okay"; }; @@ -277,7 +278,7 @@ MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc1: usdhc1grp { fsl,pins = < - MX93_PAD_SD1_CLK__USDHC1_CLK 0x179e + MX93_PAD_SD1_CLK__USDHC1_CLK 0x119e MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001386 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001386 @@ -287,14 +288,14 @@ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001386 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001386 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001386 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001386 - MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x159e >; }; /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < - MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be + MX93_PAD_SD1_CLK__USDHC1_CLK 0x11be MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e @@ -304,14 +305,14 @@ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e - MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x159e >; }; /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < - MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be + MX93_PAD_SD1_CLK__USDHC1_CLK 0x11be MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013be @@ -321,7 +322,7 @@ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013be MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013be MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013be MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013be - MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x159e >; }; From f68aa04e6eda5c1c673c6bd1cd76447bee1d03f2 Mon Sep 17 00:00:00 2001 From: Antoine Gouby Date: Fri, 8 May 2026 13:26:36 +0200 Subject: [PATCH 370/665] arm64: dts: freescale: imx95-toradex-smarc: replace deprecated gpio property Replace deprecated "gpio" property with "gpios" in regulator-vmmc-usdhc2 fixed regulator node. Signed-off-by: Antoine Gouby Reviewed-by: Francesco Dolcini Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi index 8eef26eb0f87..7d760470201f 100644 --- a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi @@ -113,7 +113,7 @@ reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { compatible = "regulator-fixed"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; - gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; enable-active-high; off-on-delay-us = <100000>; regulator-max-microvolt = <3300000>; From 538525f34158deb21b782164bde23ec07a353e4a Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Sat, 9 May 2026 09:54:09 +0800 Subject: [PATCH 371/665] arm64: dts: imx8dxl-evk: Remove unnecessary PCIe EP properties For PCIe endpoint mode, only M.2 power supply needs to be ensured. On imx8dxl-evk, the M.2 power is always on and cannot be controlled, while reg_pcieb only controls the M.2 W_DISABLE1# signal. Remove the unnecessary vpcie-supply property from pcie0_ep node. Also remove reset-gpio as PCIe endpoint mode doesn't require reset control. Fixes: c1c4820b60d7 ("arm64: dts: imx8dxl-evk: Add pcie0-ep node and use unified pcie0 label") Signed-off-by: Sherry Sun Reviewed-by: Richard Zhu Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index bc62ae5ca812..441e00903029 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -686,8 +686,6 @@ &pcie0_ep { phy-names = "pcie-phy"; pinctrl-0 = <&pinctrl_pcieb>; pinctrl-names = "default"; - reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; - vpcie-supply = <®_pcieb>; status = "disabled"; }; From b5ba136d535f1060322af31c0cf74d85ea19892d Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Sat, 9 May 2026 09:54:10 +0800 Subject: [PATCH 372/665] arm64: dts: imx8qxp-mek: Remove unnecessary PCIe EP vpcie-supply For PCIe endpoint mode, only M.2 power supply needs to be ensured. On imx8qxp-mek, the M.2 power is always on and cannot be controlled, while reg_pcieb only controls the M.2 W_DISABLE1# signal. Remove the unnecessary vpcie-supply property from pcie0_ep node. Fixes: 1c9b0c6044c2 ("arm64: dts: imx8: use common imx-pcie0-ep.dtso to enable PCI ep function") Signed-off-by: Sherry Sun Reviewed-by: Richard Zhu Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 623169f7ddb5..c07138055229 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -742,7 +742,6 @@ &pcie0_ep { phy-names = "pcie-phy"; pinctrl-0 = <&pinctrl_pcieb>; pinctrl-names = "default"; - vpcie-supply = <®_pcieb>; status = "disabled"; }; From 596d0f9f4fefffbf783ab26cfa90cf50f5dd6bb0 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Sat, 9 May 2026 09:54:11 +0800 Subject: [PATCH 373/665] arm64: dts: imx95-19x19-evk: Fix PCIe EP vpcie-supply The vpcie-supply property should reference the regulator that controls the actual M.2 power supply, not the W_DISABLE1# signal. On imx95-19x19-evk: - reg_pcie0 controls M.2 W_DISABLE1# signal - reg_m2_pwr controls the actual M.2 power supply Fix the vpcie-supply to use reg_m2_pwr for proper power control in PCIe endpoint mode. Fixes: 58bea81052d0 ("arm64: dts: imx95: add pcie1 ep overlay file and create pcie-ep dtb files") Signed-off-by: Sherry Sun Reviewed-by: Richard Zhu Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts index 041fd838fabb..49400bc9ba91 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -550,7 +550,7 @@ &pcie0 { &pcie0_ep { pinctrl-0 = <&pinctrl_pcie0>; pinctrl-names = "default"; - vpcie-supply = <®_pcie0>; + vpcie-supply = <®_m2_pwr>; status = "disabled"; }; From 3f47ca8bb3c3f4a71688451a0cb7350d3e1e1059 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Mon, 18 May 2026 11:32:44 +0800 Subject: [PATCH 374/665] riscv: dts: spacemit: Add PDMA controller node for K3 SoC Add the Peripheral DMA (PDMA) controller node for the SpacemiT K3 SoC. The PDMA controller provides general-purpose DMA capabilities for various peripheral devices across the system to offload CPU data transfers. Unlike the previous K1 SoC, where some DMA masters had memory addressing limitations (e.g. restricted to the 0-4GB space) requiring a dedicated dma-bus with dma-ranges to restrict memory allocations, the K3 DMA masters have full memory addressing capabilities. Therefore, the PDMA node is now instantiated directly under the main soc bus. Signed-off-by: Troy Mitchell Link: https://patch.msgid.link/20260518-k3-pdma-v6-4-67fdf319a8f8@linux.spacemit.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index 23cca70f796b..d4be8de8fc6c 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -586,6 +586,17 @@ gmac2_axi_setup: stmmac-axi-config { }; }; + pdma: dma-controller@d4000000 { + compatible = "spacemit,k3-pdma"; + reg = <0x0 0xd4000000 0x0 0x4000>; + clocks = <&syscon_apmu CLK_APMU_DMA>; + resets = <&syscon_apmu RESET_APMU_DMA>; + interrupts = <72 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <16>; + #dma-cells = <1>; + status = "disabled"; + }; + i2c0: i2c@d4010800 { compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; reg = <0x0 0xd4010800 0x0 0x38>; From 247c77ff5806bcd6a5ff802718de1f0aa2bcba6c Mon Sep 17 00:00:00 2001 From: Shuwei Wu Date: Mon, 27 Apr 2026 15:15:17 +0800 Subject: [PATCH 375/665] riscv: dts: spacemit: Add thermal sensor for K1 SoC Include the Thermal Sensor node in the SpacemiT K1 dtsi with definitions for registers, clocks, and interrupts. Additionally, configure thermal zones for the soc, package, gpu, and clusters to enable temperature monitoring via the thermal framework. Tested-by: Vincent Legoll # OrangePi-RV2 Tested-by: Gong Shuai Signed-off-by: Shuwei Wu Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260427-k1-thermal-v5-3-df39187480ed@mailbox.org Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1.dtsi | 101 +++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index 06469c364eef..08a0f28d011f 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -339,6 +339,96 @@ osc_32k: clock-32k { }; }; + thermal-zones { + soc-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&thermal 0>; + + trips { + soc-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + package-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&thermal 1>; + + trips { + package-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpu-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&thermal 2>; + + trips { + gpu-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cluster0-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&thermal 3>; + + trips { + cluster0-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cluster0-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cluster1-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&thermal 4>; + + trips { + cluster1-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cluster1-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>; @@ -494,6 +584,17 @@ syscon_apbc: system-controller@d4015000 { #reset-cells = <1>; }; + thermal: thermal@d4018000 { + compatible = "spacemit,k1-tsensor"; + reg = <0x0 0xd4018000 0x0 0x100>; + clocks = <&syscon_apbc CLK_TSEN>, + <&syscon_apbc CLK_TSEN_BUS>; + clock-names = "core", "bus"; + interrupts = <61>; + resets = <&syscon_apbc RESET_TSEN>; + #thermal-sensor-cells = <1>; + }; + i2c6: i2c@d4018800 { compatible = "spacemit,k1-i2c"; reg = <0x0 0xd4018800 0x0 0x38>; From c5ad6737df88bd3c3e83145edb25737cb19f9a1f Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 18 May 2026 18:00:30 +0800 Subject: [PATCH 376/665] riscv: dts: spacemit: enable USB3 on OrangePi R2S Enable the DWC3 USB3.0 controller and its associated PHY on the OrangePi R2S. The USB regulator provides VBUS for USB2 and USB3 ports, but the USB2 ports are handled by a separate controller. Signed-off-by: Chukun Pan Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260518100030.2354606-1-amadeus@jmu.edu.cn Signed-off-by: Yixun Lan --- .../boot/dts/spacemit/k1-orangepi-r2s.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts index de75f6aac740..1ecc40749e5a 100644 --- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts @@ -21,6 +21,19 @@ aliases { chosen { stdout-path = "serial0"; }; + + vcc5v0_usb: regulator-vcc5v0-usb { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio K1_GPIO(126) GPIO_ACTIVE_HIGH>; + regulator-name = "vcc5v0_usb"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&combo_phy { + status = "okay"; }; &emmc { @@ -90,3 +103,13 @@ &uart0 { pinctrl-0 = <&uart0_2_cfg>; status = "okay"; }; + +&usbphy2 { + status = "okay"; +}; + +&usb_dwc3 { + dr_mode = "host"; + vbus-supply = <&vcc5v0_usb>; + status = "okay"; +}; From 4f97acb4f744f516bbe976da8282c0fe213216ff Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 19 May 2026 06:12:35 +0200 Subject: [PATCH 377/665] riscv: dts: spacemit: set console baud rate on Milk-V Jupiter Because the default console's baud rate is not set, defconfig kernels do not have any serial output on this platform. Set the baud rate to 115200, matching what is used by U-Boot etc on this platform. See-also: 24c12ca43b12c ("dts: spacemit: set console baud rate on bpif3") Fixes: 5b90a3d6092d9 ("riscv: dts: spacemit: Add Milk-V Jupiter board device tree") Signed-off-by: Aurelien Jarno Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260519041458.3287843-2-aurelien@aurel32.net Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts index afaad59e6bce..db98dbfadf00 100644 --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -20,7 +20,7 @@ aliases { }; chosen { - stdout-path = "serial0"; + stdout-path = "serial0:115200n8"; }; leds { From 9cdeba29d65b10e7bdb1491167141ff2df238ab8 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 19 May 2026 06:12:36 +0200 Subject: [PATCH 378/665] riscv: dts: spacemit: sort aliases on Milk-V Jupiter Before adding more aliases, just sort them. Signed-off-by: Aurelien Jarno Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260519041458.3287843-3-aurelien@aurel32.net Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts index db98dbfadf00..fbba33992347 100644 --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -14,9 +14,9 @@ / { aliases { ethernet0 = ð0; ethernet1 = ð1; - serial0 = &uart0; i2c2 = &i2c2; i2c8 = &i2c8; + serial0 = &uart0; }; chosen { From 4bc9f44d581be66718cf7cf6e649fb92b3c2e6c6 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 19 May 2026 06:12:37 +0200 Subject: [PATCH 379/665] riscv: dts: spacemit: enable eMMC on Milk-V Jupiter The Milk-V Jupiter board has a connector for an eMMC module. Add an entry for it in the device tree and alias it mmc0. Mark the device as non-removable as eMMC modules have no CD pin and are not supposed to be inserted or removed while the system is running. On systems without an eMMC module installed, the kernel emits the following informational message during boot: mmc0: SDHCI controller on d4281000.mmc [d4281000.mmc] using ADMA mmc0: Failed to initialize a non-removable card Signed-off-by: Aurelien Jarno Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260519041458.3287843-4-aurelien@aurel32.net Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts index fbba33992347..1a833e716cb6 100644 --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -16,6 +16,7 @@ aliases { ethernet1 = ð1; i2c2 = &i2c2; i2c8 = &i2c8; + mmc0 = &emmc; serial0 = &uart0; }; @@ -105,6 +106,16 @@ &combo_phy { status = "okay"; }; +&emmc { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + ð0 { phy-handle = <&rgmii0>; phy-mode = "rgmii-id"; From 60b5e027c8c8cab69ad9cc7cab71ee795963e7b1 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 19 May 2026 06:12:38 +0200 Subject: [PATCH 380/665] riscv: dts: spacemit: enable SD card support on Milk-V Jupiter Add complete SD card controller support with UHS high-speed modes. - Enable sdhci0 controller with 4-bit bus width - Configure card detect GPIO with pull-up - Connect vmmc-supply to buck4 for 3.3V card power - Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching - Add dual pinctrl states for voltage-dependent pin configuration - Support UHS-I SDR25, SDR50, and SDR104 modes - Alias it as mmc1 Signed-off-by: Aurelien Jarno Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260519041458.3287843-5-aurelien@aurel32.net Signed-off-by: Yixun Lan --- .../boot/dts/spacemit/k1-milkv-jupiter.dts | 21 ++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts index 1a833e716cb6..beebf804197e 100644 --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -17,6 +17,7 @@ aliases { i2c2 = &i2c2; i2c8 = &i2c8; mmc0 = &emmc; + mmc1 = &sdhci0; serial0 = &uart0; }; @@ -250,7 +251,7 @@ buck6 { regulator-always-on; }; - aldo1 { + aldo1: aldo1 { regulator-min-microvolt = <500000>; regulator-max-microvolt = <3400000>; regulator-boot-on; @@ -385,6 +386,24 @@ uboot@a00000 { }; }; +&sdhci0 { + pinctrl-names = "default", "uhs"; + pinctrl-0 = <&mmc1_cfg>; + pinctrl-1 = <&mmc1_uhs_cfg>; + bus-width = <4>; + cd-gpios = <&gpio K1_GPIO(80) (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + no-mmc; + no-sdio; + disable-wp; + cap-sd-highspeed; + vmmc-supply = <&buck4_3v3>; + vqmmc-supply = <&aldo1>; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_2_cfg>; From 6edd9a0d32e1ef81133b8cb5b3bb3157a44da4d1 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 19 May 2026 06:12:39 +0200 Subject: [PATCH 381/665] riscv: dts: spacemit: fix uboot partition offset on Milk-V Jupiter Correct the uboot partition node name to match its actual offset. Fixes: 2829823956f0 ("riscv: dts: spacemit: enable QSPI and add SPI NOR on Milk-V Jupiter") Signed-off-by: Aurelien Jarno Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260519041458.3287843-6-aurelien@aurel32.net Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts index beebf804197e..2fc8d6533786 100644 --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -379,7 +379,7 @@ env@60000 { opensbi@70000 { reg = <0x70000 0x30000>; }; - uboot@a00000 { + uboot@a0000 { reg = <0xa0000 0x760000>; }; }; From d7b3f4a4eb23d82ef923cf17509292b719340378 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Wed, 29 Apr 2026 22:16:12 -0700 Subject: [PATCH 382/665] ARM: dts: NSP: Move MX6X pinctrl config to PWM node On boot there is this warning: /axi@18000000/pinctrl@3f1c0: Fixed dependency cycle(s) with /axi@18000000/pinctrl@3f1c0/pwm_leds Fix by moving the pinctrl configuration to pwm, which is the actual consumer. Signed-off-by: Rosen Penev Link: https://lore.kernel.org/r/20260430051612.700050-1-rosenp@gmail.com Signed-off-by: Florian Fainelli --- .../arm/boot/dts/broadcom/bcm958625-meraki-mx6x-common.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx6x-common.dtsi b/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx6x-common.dtsi index 7e71aecb7251..0ab2ed32be2a 100644 --- a/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx6x-common.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx6x-common.dtsi @@ -121,9 +121,6 @@ &ohci0 { }; &pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&pwm_leds>; - pwm_leds: pwm_leds { function = "pwm"; groups = "pwm1_grp", "pwm2_grp", "pwm3_grp"; @@ -131,6 +128,9 @@ pwm_leds: pwm_leds { }; &pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_leds>; + status = "okay"; }; From 1dd3a357b8c1b51b26422b742223f10db648118b Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Mon, 6 Apr 2026 15:04:53 -0700 Subject: [PATCH 383/665] ARM: dts: BCM5301X: R6300v2: fix USB3 USB3 needs GPIO to be pulled HIGH in order to function. Add vcc-gpio to do so. Signed-off-by: Rosen Penev Link: https://lore.kernel.org/r/20260406220453.101185-1-rosenp@gmail.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/broadcom/bcm4708-netgear-r6300-v2.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/broadcom/bcm4708-netgear-r6300-v2.dts b/arch/arm/boot/dts/broadcom/bcm4708-netgear-r6300-v2.dts index 77396730bdd3..55f0d9e90d5f 100644 --- a/arch/arm/boot/dts/broadcom/bcm4708-netgear-r6300-v2.dts +++ b/arch/arm/boot/dts/broadcom/bcm4708-netgear-r6300-v2.dts @@ -86,3 +86,7 @@ &spi_nor { &usb3_phy { status = "okay"; }; + +&usb3 { + vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; +}; From f6c6b4d1c833bf18a8ba929576736f7dbd34a8a1 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Mon, 6 Apr 2026 15:05:28 -0700 Subject: [PATCH 384/665] ARM: dts: BCM5301X: EA6500v2: fix USB3 USB3 needs to have a GPIO pulled HIGH in order to function. Add vcc-gpio to do so. Signed-off-by: Rosen Penev Link: https://lore.kernel.org/r/20260406220528.101340-1-rosenp@gmail.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6500-v2.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6500-v2.dts b/arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6500-v2.dts index 0454423fe166..ad246f9a734a 100644 --- a/arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6500-v2.dts +++ b/arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6500-v2.dts @@ -43,3 +43,7 @@ button-restart { &usb3_phy { status = "okay"; }; + +&usb3 { + vcc-gpio = <&chipcommon 10 GPIO_ACTIVE_HIGH>; +}; From 88ddafb01ec05bb3cd1ffb51b740bfbc989ab955 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Thu, 14 May 2026 16:54:13 +0300 Subject: [PATCH 385/665] arm64: dts: qcom: eliza: Describe the ADSP and USB related nodes Describe the ADSP remoteproc node along with its dependencies, including the IPCC mailbox, AOSS QMP and SMP2P links used for communication. The Eliza SoC features a USB 3.1 Gen 2 controller connected to a QMP combo PHY and an SNPS eUSB2 PHY. Describe them. Reviewed-by: Krzysztof Kozlowski Tested-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20260514-eliza-adsp-usb-v5-1-a21056ffd892@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza.dtsi | 260 ++++++++++++++++++++++++++++ 1 file changed, 260 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi index 24c680795481..9fc07b6146e5 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -6,10 +6,13 @@ #include #include #include +#include #include #include #include #include +#include +#include #include #include @@ -596,6 +599,30 @@ llcc_lpi_mem: llcc-lpi@ff800000 { }; }; + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc@0 { compatible = "simple-bus"; @@ -624,6 +651,17 @@ gcc: clock-controller@100000 { #power-domain-cells = <1>; }; + ipcc: mailbox@406000 { + compatible = "qcom,eliza-ipcc", "qcom,ipcc"; + reg = <0x0 0x00406000 0x0 0x1000>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + + #mbox-cells = <2>; + }; + qupv3_2: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x008c0000 0x0 0x2000>; @@ -894,6 +932,55 @@ tcsr: clock-controller@1fbf000 { #reset-cells = <1>; }; + remoteproc_adsp: remoteproc@3000000 { + compatible = "qcom,eliza-adsp-pas"; + reg = <0x0 0x03000000 0x0 0x10000>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; + power-domain-names = "lcx", + "lmx"; + + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + }; + }; + lpass_ag_noc: interconnect@7e40000 { compatible = "qcom,eliza-lpass-ag-noc"; reg = <0x0 0x07e40000 0x0 0xe080>; @@ -915,6 +1002,167 @@ lpass_lpicx_noc: interconnect@7420000 { #interconnect-cells = <2>; }; + usb_hsphy: phy@88e3000 { + compatible = "qcom,eliza-snps-eusb2-phy", + "qcom,sm8550-snps-eusb2-phy"; + reg = <0x0 0x088e3000 0x0 0x154>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB2_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + status = "disabled"; + }; + + usb_dp_qmpphy: phy@88e8000 { + compatible = "qcom,eliza-qmp-usb3-dp-phy", + "qcom,sm8650-qmp-usb3-dp-phy"; + reg = <0x0 0x088e8000 0x0 0x4000>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&tcsr TCSR_USB3_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe"; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; + reset-names = "phy", + "common"; + + power-domains = <&gcc GCC_USB3_PHY_GDSC>; + + #clock-cells = <1>; + #phy-cells = <1>; + + orientation-switch; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dp_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_dp_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_dp_qmpphy_dp_in: endpoint { + }; + }; + }; + }; + + usb: usb@a600000 { + compatible = "qcom,eliza-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a600000 0x0 0xfc100>; + + interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dwc_usb3", + "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, + <200000000>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + phys = <&usb_hsphy>, + <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "usb-ddr", "apps-usb"; + + iommus = <&apps_smmu 0x40 0x0>; + + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + snps,hird-threshold = /bits/ 8 <0x0>; + snps,usb2-gadget-lpm-disable; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,usb2-lpm-disable; + snps,has-lpm-erratum; + tx-fifo-resize; + + dma-coherent; + usb-role-switch; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_dwc3_ss: endpoint { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; + }; + }; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,eliza-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x40000>, @@ -989,6 +1237,18 @@ tsens2: thermal-sensor@c22a000 { #thermal-sensor-cells = <1>; }; + aoss_qmp: power-management@c300000 { + compatible = "qcom,eliza-aoss-qmp", "qcom,aoss-qmp"; + reg = <0x0 0x0c300000 0x0 0x400>; + + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + }; + spmi: arbiter@c400000 { compatible = "qcom,eliza-spmi-pmic-arb", "qcom,x1e80100-spmi-pmic-arb"; From 59703108a0c00321f181d021cb83e0d7b610ed61 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Thu, 14 May 2026 16:54:14 +0300 Subject: [PATCH 386/665] arm64: dts: qcom: Add Eliza-specific PM7550BA dtsi On Eliza, the SPMI arbiter supports multiple bus masters, requiring explicit selection of the master for each PMIC. The existing PM7550BA dtsi does not provide a way to describe this, so introduce an Eliza-specific variant with the appropriate bus configuration. This duplication is required due to hardware differences in how the SPMI bus is exposed on this platform. Reviewed-by: Dmitry Baryshkov Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260514-eliza-adsp-usb-v5-2-a21056ffd892@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm7550ba-eliza.dtsi | 70 ++++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm7550ba-eliza.dtsi diff --git a/arch/arm64/boot/dts/qcom/pm7550ba-eliza.dtsi b/arch/arm64/boot/dts/qcom/pm7550ba-eliza.dtsi new file mode 100644 index 000000000000..18692893ca41 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm7550ba-eliza.dtsi @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +/ { + thermal-zones { + pm7550ba-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pm7550ba_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus0 { + pm7550ba: pmic@7 { + compatible = "qcom,pm7550ba", "qcom,spmi-pmic"; + reg = <7 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm7550ba_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm7550ba_gpios: gpio@8800 { + compatible = "qcom,pm7550ba-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm7550ba_gpios 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm7550ba_eusb2_repeater: phy@fd00 { + compatible = "qcom,pm7550ba-eusb2-repeater", + "qcom,pm8550b-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; + }; +}; From 49dab7311f57e0ba81bdcd3bcf6d763cca13532b Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Thu, 14 May 2026 16:54:15 +0300 Subject: [PATCH 387/665] arm64: dts: qcom: eliza-mtp: Enable USB and ADSP support The Eliza MTP features a single USB Type-C port. Its USB 2.0 lines are routed through an eUSB2 repeater provided by the PM7550BA PMIC. Describe the port and repeater, and enable the USB controller and PHYs. Also specify the ADSP firmware and enable the remoteproc. Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Tested-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20260514-eliza-adsp-usb-v5-3-a21056ffd892@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza-mtp.dts | 81 ++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza-mtp.dts b/arch/arm64/boot/dts/qcom/eliza-mtp.dts index 90f629800cb0..3e41c95edb28 100644 --- a/arch/arm64/boot/dts/qcom/eliza-mtp.dts +++ b/arch/arm64/boot/dts/qcom/eliza-mtp.dts @@ -6,9 +6,12 @@ /dts-v1/; #include +#include #include #include "eliza.dtsi" +#include "pm7550ba-eliza.dtsi" + / { model = "Qualcomm Technologies, Inc. Eliza MTP"; compatible = "qcom,eliza-mtp", "qcom,eliza"; @@ -54,6 +57,44 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { }; }; + pmic-glink { + compatible = "qcom,eliza-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 122 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + }; + }; + }; + vph_pwr: regulator-vph-pwr { compatible = "regulator-fixed"; @@ -376,6 +417,18 @@ vreg_l7k: ldo7 { }; }; +&pm7550ba_eusb2_repeater { + vdd18-supply = <&vreg_l7b>; + vdd3-supply = <&vreg_l17b>; +}; + +&remoteproc_adsp { + firmware-name = "qcom/eliza/adsp.mbn", + "qcom/eliza/adsp_dtb.mbn"; + + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <20 4>, /* NFC SPI */ <111 2>, /* WCN UART1 */ @@ -405,3 +458,31 @@ &ufs_mem_phy { status = "okay"; }; + +&usb { + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&vreg_l3g>; + vdda-pll-supply = <&vreg_l7k>; + + status = "okay"; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_hsphy { + vdd-supply = <&vreg_l7k>; + vdda12-supply = <&vreg_l4b>; + + phys = <&pm7550ba_eusb2_repeater>; + + status = "okay"; +}; From 159d252ed80025cfdc218dd38cdcbdc7eb4beddf Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 6 May 2026 14:30:26 +0200 Subject: [PATCH 388/665] arm64: dts: qcom: eliza: Add display (MDSS) with Display CC Add device nodes for almost entire display: MDSS, DPU, DSI, DSI PHYs, DisplayPort and Display Clock Controller. Missing pieces are HDMI PHY and HDMI controller. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260506-dts-qcom-eliza-display-v3-1-9e46401f467a@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza.dtsi | 443 ++++++++++++++++++++++++++++ 1 file changed, 443 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi index 9fc07b6146e5..dc0d605a2125 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -3,6 +3,8 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ +#include +#include #include #include #include @@ -1067,6 +1069,7 @@ port@2 { reg = <2>; usb_dp_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; }; }; }; @@ -1163,6 +1166,446 @@ usb_dwc3_ss: endpoint { }; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,eliza-mdss"; + reg = <0x0 0x0ae00000 0x0 0x1000>; + reg-names = "mdss"; + ranges; + + interrupts = ; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; + + power-domains = <&dispcc MDSS_GDSC>; + + iommus = <&apps_smmu 0x800 0x2>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <2>; + #size-cells = <2>; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,eliza-dpu"; + reg = <0x0 0x0ae01000 0x0 0x93000>, + <0x0 0x0aeb0000 0x0 0x3000>; + reg-names = "mdp", + "vbif"; + + interrupts-extended = <&mdss 0>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + + power-domains = <&rpmhpd RPMHPD_CX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + + port@2 { + reg = <2>; + + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; + }; + }; + /* TODO: HDMI */ + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-207000000 { + opp-hz = /bits/ 64 <207000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-342000000 { + opp-hz = /bits/ 64 <342000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-417000000 { + opp-hz = /bits/ 64 <417000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-532000000 { + opp-hz = /bits/ 64 <532000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + }; + + opp-660000000 { + opp-hz = /bits/ 64 <660000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,eliza-dsi-ctrl", "qcom,sm8750-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0x0 0x0ae94000 0x0 0x400>; + reg-names = "dsi_ctrl"; + + interrupts-extended = <&mdss 4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&dispcc DISP_CC_ESYNC0_CLK>, + <&dispcc DISP_CC_OSC_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus", + "dsi_pll_pixel", + "dsi_pll_byte", + "esync", + "osc", + "byte_src", + "pixel_src"; + + operating-points-v2 = <&mdss_dsi_opp_table>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-140630000 { + opp-hz = /bits/ 64 <140630000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae95000 { + compatible = "qcom,eliza-dsi-phy-4nm", "qcom,sm8650-dsi-phy-4nm"; + reg = <0x0 0x0ae95000 0x0 0x200>, + <0x0 0x0ae95200 0x0 0x300>, + <0x0 0x0ae95500 0x0 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&bi_tcxo_div2>; + clock-names = "iface", + "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible = "qcom,eliza-dsi-ctrl", "qcom,sm8750-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0x0 0x0ae96000 0x0 0x400>; + reg-names = "dsi_ctrl"; + + interrupts-extended = <&mdss 5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&dispcc DISP_CC_ESYNC1_CLK>, + <&dispcc DISP_CC_OSC_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus", + "dsi_pll_pixel", + "dsi_pll_byte", + "esync", + "osc", + "byte_src", + "pixel_src"; + + operating-points-v2 = <&mdss_dsi_opp_table>; + + phys = <&mdss_dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae97000 { + compatible = "qcom,eliza-dsi-phy-4nm", "qcom,sm8650-dsi-phy-4nm"; + reg = <0x0 0x0ae97000 0x0 0x200>, + <0x0 0x0ae97200 0x0 0x300>, + <0x0 0x0ae97500 0x0 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss_dp0: displayport-controller@af54000 { + compatible = "qcom,eliza-dp", "qcom,sm8650-dp"; + reg = <0x0 0x0af54000 0x0 0x200>, + <0x0 0x0af54200 0x0 0x200>, + <0x0 0x0af55000 0x0 0xc00>, + <0x0 0x0af56000 0x0 0x400>, + <0x0 0x0af57000 0x0 0x400>, + <0x0 0x0af58000 0x0 0x400>, + <0x0 0x0af59000 0x0 0x400>, + <0x0 0x0af5a000 0x0 0x600>, + <0x0 0x0af5b000 0x0 0x600>; + + interrupts-extended = <&mdss 12>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&dp_opp_table>; + + power-domains = <&rpmhpd RPMHPD_CX>; + + phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp0_out: endpoint { + data-lanes = <0 1 2 3>; + remote-endpoint = <&usb_dp_qmpphy_dp_in>; + }; + }; + }; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,eliza-dispcc"; + reg = <0x0 0x0af00000 0x0 0x20000>; + + clocks = <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&gcc GCC_DISP_AHB_CLK>, + <&sleep_clk>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <0>, /* dp1 */ + <0>, + <0>, /* dp2 */ + <0>, + <0>, /* dp3 */ + <0>, + <0>; /* HDMI phy */ + + power-domains = <&rpmhpd RPMHPD_MX>; + required-opps = <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,eliza-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x40000>, From 72f758277a4400be7c459653f709ce5fc70a9dcd Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 6 May 2026 14:30:27 +0200 Subject: [PATCH 389/665] arm64: dts: qcom: eliza-mtp: Enable DSI display panel Enable display on Eliza MTP board with Visionox VTDR6130 panel. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260506-dts-qcom-eliza-display-v3-2-9e46401f467a@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza-mtp.dts | 63 ++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza-mtp.dts b/arch/arm64/boot/dts/qcom/eliza-mtp.dts index 3e41c95edb28..f0a390107d5d 100644 --- a/arch/arm64/boot/dts/qcom/eliza-mtp.dts +++ b/arch/arm64/boot/dts/qcom/eliza-mtp.dts @@ -417,6 +417,48 @@ vreg_l7k: ldo7 { }; }; +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l4b>; + + status = "okay"; + + panel@0 { + compatible = "visionox,vtdr6130"; + reg = <0>; + + reset-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>; + + vci-supply = <&vreg_l19b>; + vdd-supply = <&vreg_l1g>; + vddio-supply = <&vreg_l8b>; + + pinctrl-0 = <&disp0_reset_n_active>, <&mdp_vsync>; + pinctrl-1 = <&disp0_reset_n_suspend>, <&mdp_vsync>; + pinctrl-names = "default", "sleep"; + + port { + panel0_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel0_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l2b>; + + status = "okay"; +}; + &pm7550ba_eusb2_repeater { vdd18-supply = <&vreg_l7b>; vdd3-supply = <&vreg_l17b>; @@ -433,6 +475,27 @@ &tlmm { gpio-reserved-ranges = <20 4>, /* NFC SPI */ <111 2>, /* WCN UART1 */ <118 1>; /* NFC Secure I/O */ + + disp0_reset_n_active: disp0-reset-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + disp0_reset_n_suspend: disp0-reset-n-suspend-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + mdp_vsync: mdp-vsync-state { + pins = "gpio17"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; }; &uart14 { From 193fd5f1aadf464c5e2a2fe2dfcbfe51d9dee645 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 6 May 2026 14:30:28 +0200 Subject: [PATCH 390/665] arm64: dts: qcom: eliza-mtp: Enable DisplayPort on USB Enable display on USB DisplayPort on MTP board with Eliza SoC. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260506-dts-qcom-eliza-display-v3-3-9e46401f467a@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza-mtp.dts | 8 ++++++++ arch/arm64/boot/dts/qcom/eliza.dtsi | 1 + 2 files changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza-mtp.dts b/arch/arm64/boot/dts/qcom/eliza-mtp.dts index f0a390107d5d..912cfbee552e 100644 --- a/arch/arm64/boot/dts/qcom/eliza-mtp.dts +++ b/arch/arm64/boot/dts/qcom/eliza-mtp.dts @@ -421,6 +421,14 @@ &mdss { status = "okay"; }; +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + &mdss_dsi0 { vdda-supply = <&vreg_l4b>; diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi index dc0d605a2125..1fe217f636e8 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -1042,6 +1042,7 @@ usb_dp_qmpphy: phy@88e8000 { #clock-cells = <1>; #phy-cells = <1>; + mode-switch; orientation-switch; status = "disabled"; From 179d11c1c0cfaddcfc984edc3c1863ab600f679f Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 15 May 2026 16:22:38 +0300 Subject: [PATCH 391/665] arm64: dts: qcom: eliza-mtp: Fix the debug UART index The Eliza MTP debug UART is QUPv3 WRAP2 SE5. The existing DTS labels it as uart14, but the serial-engine index for this block is actually 13. Rename the SoC UART label and pinctrl state to uart13 and update the MTP alias and node reference accordingly. Fixes: af20af39fc09 ("arm64: dts: qcom: Introduce Eliza Soc base dtsi") Fixes: 2a5d4fc6f3f7 ("arm64: dts: qcom: eliza: Enable Eliza MTP board support") Reviewed-by: Konrad Dybcio Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20260515-eliza-dts-fix-debug-uart-and-more-support-v2-1-5ad3da81b9d3@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza-mtp.dts | 4 ++-- arch/arm64/boot/dts/qcom/eliza.dtsi | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/eliza-mtp.dts b/arch/arm64/boot/dts/qcom/eliza-mtp.dts index 912cfbee552e..1374afd9d14e 100644 --- a/arch/arm64/boot/dts/qcom/eliza-mtp.dts +++ b/arch/arm64/boot/dts/qcom/eliza-mtp.dts @@ -18,7 +18,7 @@ / { chassis-type = "handset"; aliases { - serial0 = &uart14; + serial0 = &uart13; }; chosen { @@ -506,7 +506,7 @@ mdp_vsync: mdp-vsync-state { }; }; -&uart14 { +&uart13 { compatible = "qcom,geni-debug-uart"; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi index 1fe217f636e8..9c520ee5036f 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -679,7 +679,7 @@ qupv3_2: geniqup@8c0000 { #size-cells = <2>; ranges; - uart14: serial@894000 { + uart13: serial@894000 { compatible = "qcom,geni-uart"; reg = <0x0 0x00894000 0x0 0x4000>; @@ -695,7 +695,7 @@ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, interconnect-names = "qup-core", "qup-config"; - pinctrl-0 = <&qup_uart14_default>; + pinctrl-0 = <&qup_uart13_default>; pinctrl-names = "default"; status = "disabled"; @@ -2070,7 +2070,7 @@ tlmm: pinctrl@f100000 { gpio-ranges = <&tlmm 0 0 184>; wakeup-parent = <&pdc>; - qup_uart14_default: qup-uart14-default-state { + qup_uart13_default: qup-uart13-default-state { /* TX, RX */ pins = "gpio18", "gpio19"; function = "qup2_se5"; From 844807e1f89d8852d570b4be5297a79ea674fc47 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 15 May 2026 16:22:39 +0300 Subject: [PATCH 392/665] arm64: dts: qcom: eliza: Add QUPv3, GPI DMA, SDHCI and LLCC nodes Describe the missing Eliza SoC nodes for the QUPv3 WRAP1 and WRAP2 serial engines, add the matching GPI DMA controllers, the SDHCI controllers and the LLCC system cache controller. Also add the TLMM pinctrl states for the QUPv3 serial engines and the SD card/eMMC interfaces, plus OPP tables for the SDHCI controllers. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260515-eliza-dts-fix-debug-uart-and-more-support-v2-2-5ad3da81b9d3@oss.qualcomm.com [bjorn: Temporarily replaced SLAVE_SDCC_1 with the constant] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza.dtsi | 1527 +++++++++++++++++++++++++++ 1 file changed, 1527 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi index 9c520ee5036f..d465b384e223 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -664,6 +665,32 @@ ipcc: mailbox@406000 { #mbox-cells = <2>; }; + gpi_dma2: dma-controller@800000 { + compatible = "qcom,eliza-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x00800000 0x0 0x60000>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels = <12>; + dma-channel-mask = <0x3f>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0x436 0>; + + dma-coherent; + }; + qupv3_2: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x008c0000 0x0 0x2000>; @@ -679,6 +706,336 @@ qupv3_2: geniqup@8c0000 { #size-cells = <2>; ranges; + i2c8: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00880000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c8_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi8: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00880000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c9: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00884000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c9_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi9: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00884000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c10: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00888000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c10_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi10: spi@888000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00888000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c11: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x0088c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c11_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi11: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x0088c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, + <&gpi_dma2 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c12: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00890000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c12_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi12: spi@890000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00890000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, + <&gpi_dma2 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + uart13: serial@894000 { compatible = "qcom,geni-uart"; reg = <0x0 0x00894000 0x0 0x4000>; @@ -700,6 +1057,679 @@ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, status = "disabled"; }; + + i2c14: i2c@898000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00898000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, + <&gpi_dma2 1 6 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c14_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi14: spi@898000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00898000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, + <&gpi_dma2 1 6 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c15: i2c@89c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x0089c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, + <&gpi_dma2 1 7 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c15_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi15: spi@89c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x0089c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, + <&gpi_dma2 1 7 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + gpi_dma1: dma-controller@a00000 { + compatible = "qcom,eliza-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x00a00000 0x0 0x60000>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels = <12>; + dma-channel-mask = <0x3f>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0xb6 0x0>; + + dma-coherent; + }; + + qupv3_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00ac0000 0x0 0x2000>; + + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + + iommus = <&apps_smmu 0xa3 0x0>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + i2c0: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a80000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c0_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi0: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a80000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c1: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a84000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c1_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi1: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a84000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c2: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a88000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c2_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi2: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a88000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c3: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c3_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi3: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c4: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a90000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c4_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi4: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a90000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi4_clk>, <&qup_spi4_cs>, + <&qup_spi4_data>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart5: serial@a94000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a94000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart5_default>, <&qup_uart5_cts_rts>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + uart6: serial@a98000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a98000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart6_default>, <&qup_uart6_cts_rts>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c7: i2c@a9c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a9c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, + <&gpi_dma1 1 7 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c7_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi7: spi@a9c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a9c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, + <&gpi_dma1 1 7 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + sdhc_1: mmc@f44000 { + compatible = "qcom,eliza-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x00f44000 0x0 0x1000>, + <0x0 0x00f45000 0x0 0x1000>; + reg-names = "hc", + "cqhci"; + + interrupts = , + ; + interrupt-names = "hc_irq", + "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "core", + "xo"; + + interconnects = <&aggre2_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc 30 /*TODO: SLAVE_SDCC_1*/ QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "sdhc-ddr", + "cpu-sdhc"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&sdhc1_opp_table>; + + qcom,dll-config = <0x000f44ec>; + qcom,ddr-config = <0x80040868>; + + iommus = <&apps_smmu 0x520 0x0>; + dma-coherent; + + bus-width = <8>; + + resets = <&gcc GCC_SDCC1_BCR>; + + status = "disabled"; + + sdhc1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; }; config_noc: interconnect@1600000 { @@ -1004,6 +2034,59 @@ lpass_lpicx_noc: interconnect@7420000 { #interconnect-cells = <2>; }; + sdhc_2: mmc@8804000 { + compatible = "qcom,eliza-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x08804000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", + "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "core", + "xo"; + + interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "sdhc-ddr", + "cpu-sdhc"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + + qcom,dll-config = <0x0007442c>; + qcom,ddr-config = <0x80040868>; + + iommus = <&apps_smmu 0x540 0x0>; + dma-coherent; + + bus-width = <4>; + + resets = <&gcc GCC_SDCC2_BCR>; + + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + usb_hsphy: phy@88e3000 { compatible = "qcom,eliza-snps-eusb2-phy", "qcom,sm8550-snps-eusb2-phy"; @@ -2070,6 +3153,280 @@ tlmm: pinctrl@f100000 { gpio-ranges = <&tlmm 0 0 184>; wakeup-parent = <&pdc>; + qup_i2c0_data_clk: qup-i2c0-data-clk-state { + pins = "gpio28", "gpio29"; + function = "qup1_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi0_cs: qup-spi0-cs-state { + pins = "gpio31"; + function = "qup1_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi0_data_clk: qup-spi0-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio28", "gpio29", "gpio30"; + function = "qup1_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + pins = "gpio32", "gpio33"; + function = "qup1_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi1_cs: qup-spi1-cs-state { + pins = "gpio35"; + function = "qup1_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi1_data_clk: qup-spi1-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio32", "gpio33", "gpio34"; + function = "qup1_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk-state { + pins = "gpio52", "gpio53"; + function = "qup1_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi2_cs: qup-spi2-cs-state { + pins = "gpio55"; + function = "qup1_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi2_data_clk: qup-spi2-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio52", "gpio53", "gpio54"; + function = "qup1_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + pins = "gpio44", "gpio45"; + function = "qup1_se3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi3_cs: qup-spi3-cs-state { + pins = "gpio47"; + function = "qup1_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi3_data_clk: qup-spi3-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio44", "gpio45", "gpio46"; + function = "qup1_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk-state { + pins = "gpio36", "gpio37"; + function = "qup1_se4_01"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi4_clk: qup-spi4-clk-state { + pins = "gpio37"; + function = "qup1_se4_23"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi4_cs: qup-spi4-cs-state { + pins = "gpio36"; + function = "qup1_se4_23"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi4_data: qup-spi4-data-state { + pins = "gpio36", "gpio37"; + function = "qup1_se4_01"; + drive-strength = <6>; + bias-disable; + }; + + qup_uart5_default: qup-uart5-default-state { + /* TX, RX */ + pins = "gpio134", "gpio135"; + function = "qup1_se5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_uart5_cts_rts: qup-uart5-cts-rts-state { + /* CTS, RTS */ + pins = "gpio132", "gpio133"; + function = "qup1_se5"; + drive-strength = <2>; + bias-pull-down; + }; + + qup_uart6_default: qup-uart6-default-state { + /* TX, RX */ + pins = "gpio42", "gpio40"; + function = "qup1_se6"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_uart6_cts_rts: qup-uart6-cts-rts-state { + /* CTS, RTS */ + pins = "gpio40", "gpio42"; + function = "qup1_se6"; + drive-strength = <2>; + bias-pull-down; + }; + + qup_i2c7_data_clk: qup-i2c7-data-clk-state { + pins = "gpio81", "gpio80"; + function = "qup1_se7"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi7_cs: qup-spi7-cs-state { + pins = "gpio78"; + function = "qup1_se7"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi7_data_clk: qup-spi7-data-clk-state { + pins = "gpio81", "gpio80", "gpio114"; + function = "qup1_se7"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c8_data_clk: qup-i2c8-data-clk-state { + pins = "gpio0", "gpio1"; + function = "qup2_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi8_cs: qup-spi8-cs-state { + pins = "gpio3"; + function = "qup2_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi8_data_clk: qup-spi8-data-clk-state { + pins = "gpio0", "gpio1", "gpio2"; + function = "qup2_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c9_data_clk: qup-i2c9-data-clk-state { + pins = "gpio4", "gpio5"; + function = "qup2_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi9_cs: qup-spi9-cs-state { + pins = "gpio7"; + function = "qup2_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi9_data_clk: qup-spi9-data-clk-state { + pins = "gpio4", "gpio5", "gpio6"; + function = "qup2_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c10_data_clk: qup-i2c10-data-clk-state { + pins = "gpio8", "gpio9"; + function = "qup2_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi10_cs: qup-spi10-cs-state { + pins = "gpio11"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi10_data_clk: qup-spi10-data-clk-state { + pins = "gpio8", "gpio9", "gpio10"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c11_data_clk: qup-i2c11-data-clk-state { + pins = "gpio79", "gpio97"; + function = "qup2_se3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi11_cs: qup-spi11-cs-state { + pins = "gpio116"; + function = "qup2_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi11_data_clk: qup-spi11-data-clk-state { + pins = "gpio79", "gpio97", "gpio100"; + function = "qup2_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c12_data_clk: qup-i2c12-data-clk-state { + pins = "gpio12", "gpio13"; + function = "qup2_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi12_cs: qup-spi12-cs-state { + pins = "gpio27"; + function = "qup2_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi12_data_clk: qup-spi12-data-clk-state { + pins = "gpio12", "gpio13", "gpio26"; + function = "qup2_se4"; + drive-strength = <6>; + bias-disable; + }; + qup_uart13_default: qup-uart13-default-state { /* TX, RX */ pins = "gpio18", "gpio19"; @@ -2077,6 +3434,162 @@ qup_uart13_default: qup-uart13-default-state { drive-strength = <2>; bias-pull-up; }; + + qup_i2c14_data_clk: qup-i2c14-data-clk-state { + pins = "gpio20", "gpio21"; + function = "qup2_se6"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi14_cs: qup-spi14-cs-state { + pins = "gpio23"; + function = "qup2_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi14_data_clk: qup-spi14-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio20", "gpio21", "gpio22"; + function = "qup2_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c15_data_clk: qup-i2c15-data-clk-state { + pins = "gpio27", "gpio26"; + function = "qup2_se7"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi15_cs: qup-spi15-cs-state { + pins = "gpio12"; + function = "qup2_se7"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi15_data_clk: qup-spi15-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio27", "gpio26", "gpio13"; + function = "qup2_se7"; + drive-strength = <6>; + bias-disable; + }; + + sdc1_default: sdc1-default-state { + clk-pins { + pins = "gpio121"; + function = "sdc1"; + drive-strength = <12>; + bias-disable; + }; + + cmd-pins { + pins = "gpio123"; + function = "sdc1"; + drive-strength = <12>; + bias-pull-up; + }; + + data-pins { + pins = "gpio124", "gpio125", + "gpio126", "gpio127", + "gpio128", "gpio129", + "gpio130", "gpio131"; + function = "sdc1"; + drive-strength = <12>; + bias-pull-up; + }; + + rclk-pins { + pins = "gpio120"; + function = "sdc1"; + bias-pull-down; + }; + }; + + sdc1_sleep: sdc1-sleep-state { + clk-pins { + pins = "gpio121"; + function = "sdc1"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "gpio123"; + function = "sdc1"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "gpio124", "gpio125", + "gpio126", "gpio127", + "gpio128", "gpio129", + "gpio130", "gpio131"; + function = "sdc1"; + drive-strength = <2>; + bias-pull-up; + }; + + rclk-pins { + pins = "gpio120"; + function = "sdc1"; + bias-pull-down; + }; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins = "gpio62"; + function = "sdc2"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "gpio51"; + function = "sdc2"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "gpio38", "gpio39", + "gpio48", "gpio49"; + function = "sdc2"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins = "gpio62"; + function = "sdc2"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "gpio51"; + function = "sdc2"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "gpio38", "gpio39", + "gpio48", "gpio49"; + function = "sdc2"; + drive-strength = <2>; + bias-pull-up; + }; + }; }; gem_noc: interconnect@24100000 { @@ -2086,6 +3599,20 @@ gem_noc: interconnect@24100000 { #interconnect-cells = <2>; }; + system-cache-controller@24800000 { + compatible = "qcom,eliza-llcc"; + reg = <0x0 0x24800000 0x0 0x200000>, + <0x0 0x24c00000 0x0 0x200000>, + <0x0 0x26800000 0x0 0x200000>, + <0x0 0x26c00000 0x0 0x200000>; + reg-names = "llcc0_base", + "llcc2_base", + "llcc_broadcast_base", + "llcc_broadcast_and_base"; + + interrupts = ; + }; + nsp_noc: interconnect@320c0000 { compatible = "qcom,eliza-nsp-noc"; reg = <0x0 0x320c0000 0x0 0xe080>; From 853a3ead458c409ffcfd7ff6a33ddc994b9a444d Mon Sep 17 00:00:00 2001 From: Alexander Koskovich Date: Sat, 18 Apr 2026 10:39:45 +0000 Subject: [PATCH 393/665] arm64: dts: qcom: eliza: Sort nodes by unit address Qualcomm DTS uses sorting of MMIO nodes by the unit address, so move few nodes in Eliza DTSI to fix that. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Alexander Koskovich Link: https://lore.kernel.org/r/20260418-eliza-imem-v3-1-bfbd499b6e77@pm.me [bjorn: Rebased on top of branch] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza.dtsi | 654 ++++++++++++++-------------- 1 file changed, 327 insertions(+), 327 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi index d465b384e223..abfaea2f6b75 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -1732,16 +1732,16 @@ opp-384000000 { }; }; - config_noc: interconnect@1600000 { - compatible = "qcom,eliza-cnoc-cfg"; - reg = <0x0 0x01600000 0x0 0x5200>; + cnoc_main: interconnect@1500000 { + compatible = "qcom,eliza-cnoc-main"; + reg = <0x0 0x01500000 0x0 0x16080>; qcom,bcm-voters = <&apps_bcm_voter>; #interconnect-cells = <2>; }; - cnoc_main: interconnect@1500000 { - compatible = "qcom,eliza-cnoc-main"; - reg = <0x0 0x01500000 0x0 0x16080>; + config_noc: interconnect@1600000 { + compatible = "qcom,eliza-cnoc-cfg"; + reg = <0x0 0x01600000 0x0 0x5200>; qcom,bcm-voters = <&apps_bcm_voter>; #interconnect-cells = <2>; }; @@ -2013,13 +2013,6 @@ IPCC_MPROC_SIGNAL_GLINK_QMP }; }; - lpass_ag_noc: interconnect@7e40000 { - compatible = "qcom,eliza-lpass-ag-noc"; - reg = <0x0 0x07e40000 0x0 0xe080>; - qcom,bcm-voters = <&apps_bcm_voter>; - #interconnect-cells = <2>; - }; - lpass_lpiaon_noc: interconnect@7400000 { compatible = "qcom,eliza-lpass-lpiaon-noc"; reg = <0x0 0x07400000 0x0 0x19080>; @@ -2690,6 +2683,13 @@ dispcc: clock-controller@af00000 { #power-domain-cells = <1>; }; + lpass_ag_noc: interconnect@7e40000 { + compatible = "qcom,eliza-lpass-ag-noc"; + reg = <0x0 0x07e40000 0x0 0xe080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,eliza-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x40000>, @@ -2824,320 +2824,6 @@ spmi_bus1: spmi@c432000 { }; }; - apps_smmu: iommu@15000000 { - compatible = "qcom,eliza-smmu-500", "qcom,smmu-500", "arm,mmu-500"; - reg = <0x0 0x15000000 0x0 0x100000>; - - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - - #iommu-cells = <2>; - #global-interrupts = <1>; - - dma-coherent; - }; - - intc: interrupt-controller@17100000 { - compatible = "arm,gic-v3"; - reg = <0x0 0x17100000 0x0 0x10000>, - <0x0 0x17180000 0x0 0x200000>; - - interrupts = ; - - #interrupt-cells = <3>; - interrupt-controller; - - #redistributor-regions = <1>; - redistributor-stride = <0x0 0x40000>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gic_its: msi-controller@17140000 { - compatible = "arm,gic-v3-its"; - reg = <0x0 0x17140000 0x0 0x40000>; - - msi-controller; - #msi-cells = <1>; - }; - }; - - apps_rsc: rsc@17a00000 { - compatible = "qcom,rpmh-rsc"; - reg = <0x0 0x17a00000 0x0 0x10000>, - <0x0 0x17a10000 0x0 0x10000>, - <0x0 0x17a20000 0x0 0x10000>; - reg-names = "drv-0", - "drv-1", - "drv-2"; - - interrupts = , - , - ; - - power-domains = <&cluster_pd>; - label = "apps_rsc"; - - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = , - , - , - ; - - apps_bcm_voter: bcm-voter { - compatible = "qcom,bcm-voter"; - }; - - rpmhcc: clock-controller { - compatible = "qcom,eliza-rpmh-clk"; - #clock-cells = <1>; - clocks = <&xo_board>; - clock-names = "xo"; - }; - - rpmhpd: power-controller { - compatible = "qcom,eliza-rpmhpd"; - - operating-points-v2 = <&rpmhpd_opp_table>; - - #power-domain-cells = <1>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp-16 { - opp-level = ; - }; - - rpmhpd_opp_min_svs: opp-48 { - opp-level = ; - }; - - rpmhpd_opp_low_svs_d3: opp-50 { - opp-level = ; - }; - - rpmhpd_opp_low_svs_d2: opp-52 { - opp-level = ; - }; - - rpmhpd_opp_low_svs_d1: opp-56 { - opp-level = ; - }; - - rpmhpd_opp_low_svs_d0: opp-60 { - opp-level = ; - }; - - rpmhpd_opp_low_svs: opp-64 { - opp-level = ; - }; - - rpmhpd_opp_low_svs_l1: opp-80 { - opp-level = ; - }; - - rpmhpd_opp_svs: opp-128 { - opp-level = ; - }; - - rpmhpd_opp_svs_l0: opp-144 { - opp-level = ; - }; - - rpmhpd_opp_svs_l1: opp-192 { - opp-level = ; - }; - - rpmhpd_opp_svs_l2: opp-224 { - opp-level = ; - }; - - rpmhpd_opp_nom: opp-256 { - opp-level = ; - }; - - rpmhpd_opp_nom_l1: opp-320 { - opp-level = ; - }; - - rpmhpd_opp_nom_l2: opp-336 { - opp-level = ; - }; - - rpmhpd_opp_turbo: opp-384 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l1: opp-416 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l2: opp-432 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l3: opp-448 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l4: opp-452 { - opp-level = ; - }; - - rpmhpd_opp_super_turbo_no_cpr: opp-480 { - opp-level = ; - }; - }; - }; - }; - - epss_l3: interconnect@17d90000 { - compatible = "qcom,eliza-epss-l3", "qcom,epss-l3"; - reg = <0x0 0x17d90000 0x0 0x1000>; - - clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; - clock-names = "xo", "alternate"; - - #interconnect-cells = <1>; - }; - - cpufreq_hw: cpufreq@17d91000 { - compatible = "qcom,eliza-cpufreq-epss", "qcom,cpufreq-epss"; - reg = <0x0 0x17d91000 0x0 0x1000>, - <0x0 0x17d92000 0x0 0x1000>, - <0x0 0x17d93000 0x0 0x1000>; - reg-names = "freq-domain0", - "freq-domain1", - "freq-domain2"; - - interrupts = , - , - ; - interrupt-names = "dcvsh-irq-0", - "dcvsh-irq-1", - "dcvsh-irq-2"; - - clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; - clock-names = "xo", "alternate"; - - #freq-domain-cells = <1>; - #clock-cells = <1>; - }; - tlmm: pinctrl@f100000 { compatible = "qcom,eliza-tlmm"; reg = <0x0 0x0f100000 0x0 0xf00000>; @@ -3592,6 +3278,320 @@ data-pins { }; }; + apps_smmu: iommu@15000000 { + compatible = "qcom,eliza-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x15000000 0x0 0x100000>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + #iommu-cells = <2>; + #global-interrupts = <1>; + + dma-coherent; + }; + + intc: interrupt-controller@17100000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x17100000 0x0 0x10000>, + <0x0 0x17180000 0x0 0x200000>; + + interrupts = ; + + #interrupt-cells = <3>; + interrupt-controller; + + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x40000>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic_its: msi-controller@17140000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x17140000 0x0 0x40000>; + + msi-controller; + #msi-cells = <1>; + }; + }; + + apps_rsc: rsc@17a00000 { + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x17a00000 0x0 0x10000>, + <0x0 0x17a10000 0x0 0x10000>, + <0x0 0x17a20000 0x0 0x10000>; + reg-names = "drv-0", + "drv-1", + "drv-2"; + + interrupts = , + , + ; + + power-domains = <&cluster_pd>; + label = "apps_rsc"; + + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,eliza-rpmh-clk"; + #clock-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; + }; + + rpmhpd: power-controller { + compatible = "qcom,eliza-rpmhpd"; + + operating-points-v2 = <&rpmhpd_opp_table>; + + #power-domain-cells = <1>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp-16 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp-48 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_d3: opp-50 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_d2: opp-52 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_d1: opp-56 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_d0: opp-60 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp-64 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_l1: opp-80 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp-128 { + opp-level = ; + }; + + rpmhpd_opp_svs_l0: opp-144 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp-192 { + opp-level = ; + }; + + rpmhpd_opp_svs_l2: opp-224 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp-256 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp-320 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp-336 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp-384 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp-416 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l2: opp-432 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l3: opp-448 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l4: opp-452 { + opp-level = ; + }; + + rpmhpd_opp_super_turbo_no_cpr: opp-480 { + opp-level = ; + }; + }; + }; + }; + + epss_l3: interconnect@17d90000 { + compatible = "qcom,eliza-epss-l3", "qcom,epss-l3"; + reg = <0x0 0x17d90000 0x0 0x1000>; + + clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; + + cpufreq_hw: cpufreq@17d91000 { + compatible = "qcom,eliza-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0x0 0x17d91000 0x0 0x1000>, + <0x0 0x17d92000 0x0 0x1000>, + <0x0 0x17d93000 0x0 0x1000>; + reg-names = "freq-domain0", + "freq-domain1", + "freq-domain2"; + + interrupts = , + , + ; + interrupt-names = "dcvsh-irq-0", + "dcvsh-irq-1", + "dcvsh-irq-2"; + + clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + #clock-cells = <1>; + }; + gem_noc: interconnect@24100000 { compatible = "qcom,eliza-gem-noc"; reg = <0x0 0x24100000 0x0 0x163080>; From 9b31a0c535433e02acc9e9719f4eb797fd155f83 Mon Sep 17 00:00:00 2001 From: Alexander Koskovich Date: Sat, 18 Apr 2026 10:40:00 +0000 Subject: [PATCH 394/665] arm64: dts: qcom: eliza: Add IMEM node Add a node for the IMEM found on Eliza, which contains pil-reloc-info and the modem tables for IPA, among others. Reviewed-by: Konrad Dybcio Signed-off-by: Alexander Koskovich Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260418-eliza-imem-v3-3-bfbd499b6e77@pm.me Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi index abfaea2f6b75..466d49e421bf 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -3278,6 +3278,26 @@ data-pins { }; }; + sram@14680000 { + compatible = "qcom,eliza-imem", "mmio-sram"; + reg = <0x0 0x14680000 0x0 0x2c000>; + ranges = <0x0 0x0 0x14680000 0x2c000>; + + no-memory-wc; + + #address-cells = <1>; + #size-cells = <1>; + + pil-reloc-sram@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + + ipa_modem_tables: modem-tables-sram@3000 { + reg = <0x3000 0x2000>; + }; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,eliza-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0 0x15000000 0x0 0x100000>; From 2597338625b4e391d4d1aecbe2356f43cdacc057 Mon Sep 17 00:00:00 2001 From: Alexander Koskovich Date: Sun, 12 Apr 2026 15:38:43 +0000 Subject: [PATCH 395/665] arm64: dts: qcom: eliza: Fix reserved memory addresses & sizes Update cpusys_vm_mem from 256KiB to 4MiB, cpucp_mem from 2MiB to 1MiB and fix cpucp_scandump_mem node name to match actual reg address. This matches the downstream memmap and kera-reserved-memory.dtsi. Signed-off-by: Alexander Koskovich Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260412-eliza-reserved-memory-fix-v1-1-05cb3e33a9fe@pm.me Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi index 466d49e421bf..efac6cb6bb3b 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -411,12 +411,12 @@ gunyah_hyp_mem: gunyah-hyp@80000000 { }; cpusys_vm_mem: cpusys-vm-mem@80e00000 { - reg = <0x0 0x80e00000 0x0 0x40000>; + reg = <0x0 0x80e00000 0x0 0x400000>; no-map; }; cpucp_mem: cpucp@81200000 { - reg = <0x0 0x81200000 0x0 0x200000>; + reg = <0x0 0x81200000 0x0 0x100000>; no-map; }; @@ -450,7 +450,7 @@ smem_mem: smem@81d00000 { no-map; }; - cpucp_scandump_mem: cpucp-scandump@82000000 { + cpucp_scandump_mem: cpucp-scandump@82200000 { reg = <0x0 0x82200000 0x0 0x180000>; no-map; }; From 11b48f6d5ed505ced9cd3645d6615279198a7a54 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Thu, 16 Apr 2026 17:29:20 +0530 Subject: [PATCH 396/665] arm64: dts: qcom: kaanapali: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for kaanapali. Fixes: 2eeb5767d53f4 ("arm64: dts: qcom: Introduce Kaanapali SoC") Reviewed-by: Konrad Dybcio Reviewed-by: Kuldeep Singh Signed-off-by: Harshal Dev Link: https://lore.kernel.org/r/20260416-qcom_ice_power_and_clk_vote-v5-3-5ccf5d7e2846@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index bcd1cee31356..370c9af7c37d 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -2538,7 +2538,11 @@ ice: crypto@1d88000 { "qcom,inline-crypto-engine"; reg = <0x0 0x01d88000 0x0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc GCC_UFS_PHY_GDSC>; }; tcsr_mutex: hwlock@1f40000 { From 04566e287b35fde9fd129db5fdf6a96e336af55c Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Thu, 16 Apr 2026 17:29:21 +0530 Subject: [PATCH 397/665] arm64: dts: qcom: lemans: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for lemans. Fixes: 96272ba7103d4 ("arm64: dts: qcom: sa8775p: enable the inline crypto engine") Reviewed-by: Konrad Dybcio Reviewed-by: Kuldeep Singh Signed-off-by: Harshal Dev Reviewed-by: Bartosz Golaszewski Link: https://lore.kernel.org/r/20260416-qcom_ice_power_and_clk_vote-v5-4-5ccf5d7e2846@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index bc7b4f65ad5e..dffbe1f5250a 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -3104,7 +3104,11 @@ ice: crypto@1d88000 { compatible = "qcom,sa8775p-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0x0 0x01d88000 0x0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc UFS_PHY_GDSC>; }; cryptobam: dma-controller@1dc4000 { From 68d5d9701a7ab1b1f9c76feaa3a24ca716f03f0b Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Thu, 16 Apr 2026 17:29:22 +0530 Subject: [PATCH 398/665] arm64: dts: qcom: monaco: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for monaco. Fixes: cc9d29aad876d ("arm64: dts: qcom: qcs8300: enable the inline crypto engine") Reviewed-by: Konrad Dybcio Reviewed-by: Kuldeep Singh Signed-off-by: Harshal Dev Link: https://lore.kernel.org/r/20260416-qcom_ice_power_and_clk_vote-v5-5-5ccf5d7e2846@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index ce6ff259cb4a..2660c161c3d7 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -2737,7 +2737,11 @@ ice: crypto@1d88000 { compatible = "qcom,qcs8300-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0x0 0x01d88000 0x0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc GCC_UFS_PHY_GDSC>; }; crypto: crypto@1dfa000 { From 7cd7271ac525e4eadd22734f418219f247638f43 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Thu, 16 Apr 2026 17:29:23 +0530 Subject: [PATCH 399/665] arm64: dts: qcom: sc7180: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sc7180. Fixes: 858536d9dc946 ("arm64: dts: qcom: sc7180: Add UFS nodes") Reviewed-by: Konrad Dybcio Reviewed-by: Kuldeep Singh Signed-off-by: Harshal Dev Link: https://lore.kernel.org/r/20260416-qcom_ice_power_and_clk_vote-v5-6-5ccf5d7e2846@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 8341a7c4a4c6..fa65c485172f 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1605,7 +1605,11 @@ ice: crypto@1d90000 { compatible = "qcom,sc7180-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0 0x01d90000 0 0x8000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc UFS_PHY_GDSC>; }; ipa: ipa@1e40000 { From cca53c338ad87edc4b46d2d82730fd8ca01a164f Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Thu, 16 Apr 2026 17:29:24 +0530 Subject: [PATCH 400/665] arm64: dts: qcom: kodiak: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for kodiak. Fixes: dfd5ee7b34bb7 ("arm64: dts: qcom: sc7280: Add inline crypto engine") Reviewed-by: Konrad Dybcio Reviewed-by: Kuldeep Singh Tested-by: Kuldeep Singh Signed-off-by: Harshal Dev Link: https://lore.kernel.org/r/20260416-qcom_ice_power_and_clk_vote-v5-7-5ccf5d7e2846@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index c51beada8c7d..fa540d8c2615 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -2579,7 +2579,11 @@ ice: crypto@1d88000 { compatible = "qcom,sc7280-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc GCC_UFS_PHY_GDSC>; }; cryptobam: dma-controller@1dc4000 { From 3a5cb1ccbfb3141862b28f24cd5050083233aae7 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Thu, 16 Apr 2026 17:29:25 +0530 Subject: [PATCH 401/665] arm64: dts: qcom: sm8450: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sm8450. Fixes: 86b0aef435851 ("arm64: dts: qcom: sm8450: Use standalone ICE node for UFS") Reviewed-by: Konrad Dybcio Reviewed-by: Kuldeep Singh Signed-off-by: Harshal Dev Link: https://lore.kernel.org/r/20260416-qcom_ice_power_and_clk_vote-v5-8-5ccf5d7e2846@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index e0c37ce3042a..47b028259d91 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -5374,7 +5374,11 @@ ice: crypto@1d88000 { compatible = "qcom,sm8450-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc UFS_PHY_GDSC>; }; cryptobam: dma-controller@1dc4000 { From 52696dbbe7bbe0c8fc8c17133ffb5133b8cf37a6 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Thu, 16 Apr 2026 17:29:26 +0530 Subject: [PATCH 402/665] arm64: dts: qcom: sm8550: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sm8550. Fixes: b8630c48b43fc ("arm64: dts: qcom: sm8550: Add the Inline Crypto Engine node") Reviewed-by: Konrad Dybcio Reviewed-by: Kuldeep Singh Signed-off-by: Harshal Dev Link: https://lore.kernel.org/r/20260416-qcom_ice_power_and_clk_vote-v5-9-5ccf5d7e2846@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index b7a7c49db077..1bdd740039b0 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2822,7 +2822,11 @@ ice: crypto@1d88000 { "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc UFS_PHY_GDSC>; }; tcsr_mutex: hwlock@1f40000 { From c62b084d5d1564f808408a2f7d4c514e57cd4106 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Thu, 16 Apr 2026 17:29:27 +0530 Subject: [PATCH 403/665] arm64: dts: qcom: sm8650: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sm8650. Fixes: 10e0246712951 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes") Reviewed-by: Konrad Dybcio Reviewed-by: Kuldeep Singh Signed-off-by: Harshal Dev Link: https://lore.kernel.org/r/20260416-qcom_ice_power_and_clk_vote-v5-10-5ccf5d7e2846@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 1604bc8cff37..e2d98cf6adca 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -4081,7 +4081,11 @@ ice: crypto@1d88000 { "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc UFS_PHY_GDSC>; }; cryptobam: dma-controller@1dc4000 { From 081ac792f0ea6d27a4b130c70cfd7544efee8137 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Thu, 16 Apr 2026 17:29:28 +0530 Subject: [PATCH 404/665] arm64: dts: qcom: sm8750: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sm8750. Fixes: b1dac789c650a ("arm64: dts: qcom: sm8750: Add ICE nodes") Reviewed-by: Konrad Dybcio Reviewed-by: Kuldeep Singh Signed-off-by: Harshal Dev Link: https://lore.kernel.org/r/20260416-qcom_ice_power_and_clk_vote-v5-11-5ccf5d7e2846@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 70830cb49e73..5a5761e5ce2c 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -2113,7 +2113,11 @@ ice: crypto@1d88000 { "qcom,inline-crypto-engine"; reg = <0x0 0x01d88000 0x0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc GCC_UFS_PHY_GDSC>; }; cryptobam: dma-controller@1dc4000 { From 4bd073e00fd79c0aead74ad64ade48c904221245 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Wed, 28 Jan 2026 17:18:50 +0530 Subject: [PATCH 405/665] arm64: dts: qcom: lemans: Add eDP ref clock for eDP PHYs The eDP PHY nodes on lemans were missing the reference clock voting. This initially went unnoticed because the clock was implicitly enabled by the UFS PHY driver, and the eDP PHY happened to rely on that. After commit 77d2fa54a945 ("scsi: ufs: qcom : Refactor phy_power_on/off calls"), the UFS driver no longer keeps the reference clock enabled. As a result, the eDP PHY fails to power on. To fix this, add eDP reference clock for eDP PHYs on lemans chipset ensuring reference clock is enabled. Fixes: e1e3e5673f8d7 ("arm64: dts: qcom: sa8775p: add DisplayPort device nodes") Signed-off-by: Ritesh Kumar Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260128114853.2543416-3-quic_riteshk@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index dffbe1f5250a..522ba43836a2 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -5658,9 +5658,11 @@ mdss0_dp0_phy: phy@aec2a00 { <0x0 0x0aec2000 0x0 0x1c8>; clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; clock-names = "aux", - "cfg_ahb"; + "cfg_ahb", + "ref"; #clock-cells = <1>; #phy-cells = <0>; @@ -5677,9 +5679,11 @@ mdss0_dp1_phy: phy@aec5a00 { <0x0 0x0aec5000 0x0 0x1c8>; clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; clock-names = "aux", - "cfg_ahb"; + "cfg_ahb", + "ref"; #clock-cells = <1>; #phy-cells = <0>; From 85abff1549515c453dd113c4a4e3dd75ef3cd30d Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 9 Apr 2026 23:43:29 +0530 Subject: [PATCH 406/665] arm64: dts: qcom: Drop unused remoteproc_adsp_glink label The remoteproc_adsp_glink label on the ADSP glink-edge node has no users in the upstream tree across all affected SoCs. The only user of this label is qcs6490-audioreach.dtsi which references the label defined in its own SoC dtsi and is left untouched. Remove the label from kaanapali, lemans, monaco, sar2130p, sc8180x, sc8280xp, sm8450, sm8550, sm8650 and sm8750. Signed-off-by: Mukesh Ojha Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260409181329.556899-1-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 2 +- arch/arm64/boot/dts/qcom/lemans.dtsi | 2 +- arch/arm64/boot/dts/qcom/monaco.dtsi | 2 +- arch/arm64/boot/dts/qcom/sar2130p.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8750.dtsi | 2 +- 10 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index 370c9af7c37d..7aa9653bd456 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -2638,7 +2638,7 @@ remoteproc_adsp: remoteproc@6800000 { status = "disabled"; - remoteproc_adsp_glink: glink-edge { + glink-edge { interrupts-extended = <&ipcc IPCC_MPROC_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 522ba43836a2..353a6e6fd3ac 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -8072,7 +8072,7 @@ remoteproc_adsp: remoteproc@30000000 { status = "disabled"; - remoteproc_adsp_glink: glink-edge { + glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 2660c161c3d7..e4c8466f941b 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -2799,7 +2799,7 @@ remoteproc_adsp: remoteproc@3000000 { status = "disabled"; - remoteproc_adsp_glink: glink-edge { + glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi index d65ad0df6865..3c9529bb2f76 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi +++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi @@ -1612,7 +1612,7 @@ remoteproc_adsp: remoteproc@3000000 { status = "disabled"; - remoteproc_adsp_glink: glink-edge { + glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index e87e82fa73e9..45391768e245 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -3755,7 +3755,7 @@ remoteproc_adsp: remoteproc@17300000 { status = "disabled"; - remoteproc_adsp_glink: glink-edge { + glink-edge { interrupts = ; label = "lpass"; qcom,remote-pid = <2>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index ee02acd18856..afe3f8018b22 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2956,7 +2956,7 @@ remoteproc_adsp: remoteproc@3000000 { status = "disabled"; - remoteproc_adsp_glink: glink-edge { + glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 47b028259d91..56cb6e959e4e 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2798,7 +2798,7 @@ remoteproc_adsp: remoteproc@3000000 { status = "disabled"; - remoteproc_adsp_glink: glink-edge { + glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 1bdd740039b0..396201905ef2 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3158,7 +3158,7 @@ remoteproc_adsp: remoteproc@6800000 { status = "disabled"; - remoteproc_adsp_glink: glink-edge { + glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index e2d98cf6adca..160ead25ecf7 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -4490,7 +4490,7 @@ remoteproc_adsp: remoteproc@6800000 { status = "disabled"; - remoteproc_adsp_glink: glink-edge { + glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 5a5761e5ce2c..4e0ae737c281 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -2248,7 +2248,7 @@ remoteproc_adsp: remoteproc@6800000 { status = "disabled"; - remoteproc_adsp_glink: glink-edge { + glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; From ecabfe832b817bd1c1fdb8841d7bc706bf621ef1 Mon Sep 17 00:00:00 2001 From: Gopikrishna Garmidi Date: Mon, 18 May 2026 02:52:53 -0700 Subject: [PATCH 407/665] arm64: dts: qcom: glymur: Fix wrong interrupt number for i2c19 The i2c19 node at 0x88c000 uses GIC SPI 584, but that interrupt belongs to the neighboring i2c18/spi18 node at 0x888000. The correct interrupt for i2c19 is GIC SPI 585, as used by its sibling nodes spi19 and uart19 which share the same register base and clock. Fixes: 41b6e8db400c ("arm64: dts: qcom: Introduce Glymur base dtsi") Signed-off-by: Gopikrishna Garmidi Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260518-glymur-fix-i2c19-irq-v1-1-7d5968bd9b2b@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 376fdb3cc8ad..85040459a452 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -989,7 +989,7 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, i2c19: i2c@88c000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x0088c000 0x0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS From 89e77275b55eac3d3b8027c9806eb32b24b05023 Mon Sep 17 00:00:00 2001 From: Anup Kulkarni Date: Tue, 19 May 2026 12:19:54 +0530 Subject: [PATCH 408/665] arm64: dts: qcom: lemans-evk: Enable CAN RX via I2C GPIO expander The LeMans EVK board routes the RX lines of CAN controllers 2, 4, and 6 (part of the RTSS subsystem) through a signal multiplexer controlled by GPIO 4 of the I2C GPIO expander at address 0x3b. The remaining CAN controllers, out of 8 total on RTSS, are wired directly to their transceivers. The multiplexer select pin defaults low on reset, disconnecting CAN 2, 4, and 6 RX lines from their respective transceivers, which results in no data being received on these interfaces. Configure GPIO 4 as output-high to assert the mux select line at boot, connecting the RX signals of CAN 2, 4, and 6 to their transceivers as required by the EVK board wiring. Signed-off-by: Anup Kulkarni Reviewed-by: Dmitry Baryshkov Acked-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260519064954.2759960-1-anup.kulkarni@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index c665db6a4595..34dfc8d22b6a 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -616,6 +616,13 @@ expander3: gpio@3b { interrupts-extended = <&tlmm 39 IRQ_TYPE_LEVEL_LOW>; pinctrl-0 = <&expander3_int>; pinctrl-names = "default"; + + rtss-can-sel-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "rtss-can-sel"; + }; }; eeprom@50 { From f6dd5665d8e525484c2d0ebdb7004319024ee640 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 20 May 2026 12:54:37 +0300 Subject: [PATCH 409/665] arm64: dts: qcom: qcs6490-rb3gen2: add rmtfs node Downstream kernels for RB3 Gen2 don't specify the RMTFS address, instead the kernel is supposed to allocate rmtfs buffers dynamically. The upstream kernel doesn't support dynamic allocation of RMTFS buffers, so use the fixed allocation. The RMTFS node (and corresponding interface) is required for the modem DSP to work (which otherwise would crash). Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260520-rb3g2-rmtfs-ipa-v1-1-8b3942ded279@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index ceb68a890bf4..37a3b51323ce 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -165,6 +165,15 @@ debug_vm_mem: debug-vm@d0600000 { reg = <0x0 0xd0600000 0x0 0x100000>; no-map; }; + + rmtfs_mem: memory@f8500000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0xf8500000 0x0 0x600000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = , ; + }; }; gpio-keys { From 1f7d0c42a08d157294b8dce4ac162c2853f287d0 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Wed, 20 May 2026 09:42:45 +0800 Subject: [PATCH 410/665] arm64: dts: qcom: glymur: add coresight nodes Add CoreSight nodes to enable trace paths like TPDM->ETF/STM->ETF. These devices are part of the AOSS, CDSP, QDSS, PCIe5, TraceNoc and some small subsystems, such as GCC, IPCC, PMU and so on. Delete cti_wpss DT node on Mahua since this device will cause NoC issue on Mahua device. Signed-off-by: Jie Gan Link: https://lore.kernel.org/r/20260520-add-coresight-nodes-for-glymur-v6-1-0bfdcdfce3ec@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 1097 ++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/mahua.dtsi | 1 + 2 files changed, 1098 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 85040459a452..ca0fd85e2946 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -362,6 +362,18 @@ domain_ss3: domain-sleep-0 { }; }; + dummy-sink { + compatible = "arm,coresight-dummy-sink"; + + in-ports { + port { + eud_in: endpoint { + remote-endpoint = <&swao_rep_out1>; + }; + }; + }; + }; + firmware { scm: scm { compatible = "qcom,scm-glymur", "qcom,scm"; @@ -5712,6 +5724,1035 @@ rx-pins { }; }; + stm: stm@10002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x0 0x10002000 0x0 0x1000>, + <0x0 0x16280000 0x0 0x180000>; + reg-names = "stm-base", + "stm-stimulus-base"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = <&funnel0_in7>; + }; + }; + }; + }; + + tpda@10004000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x10004000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + qdss_tpda_in1: endpoint { + remote-endpoint = <&spdm_tpdm_out>; + }; + }; + }; + + out-ports { + port { + qdss_tpda_out: endpoint { + remote-endpoint = <&funnel0_in6>; + }; + }; + }; + }; + + tpdm@1000f000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1000f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + spdm_tpdm_out: endpoint { + remote-endpoint = <&qdss_tpda_in1>; + }; + }; + }; + }; + + funnel@10041000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x10041000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + funnel0_in0: endpoint { + remote-endpoint = <&tn_ag_out>; + }; + }; + + port@6 { + reg = <6>; + + funnel0_in6: endpoint { + remote-endpoint = <&qdss_tpda_out>; + }; + }; + + port@7 { + reg = <7>; + + funnel0_in7: endpoint { + remote-endpoint = <&stm_out>; + }; + }; + }; + + out-ports { + port { + funnel0_out: endpoint { + remote-endpoint = <&aoss_funnel_in6>; + }; + }; + }; + }; + + tpdm@1102c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1102c000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + gcc_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in36>; + }; + }; + }; + }; + + tpdm@11180000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11180000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + cdsp_tpdm_out: endpoint { + remote-endpoint = <&cdsp_tpda_in0>; + }; + }; + }; + }; + + tpdm@11185000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11185000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + cdsp_dpm1_tpdm_out: endpoint { + remote-endpoint = <&cdsp_tpda_in5>; + }; + }; + }; + }; + + tpdm@11186000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11186000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + cdsp_dpm2_tpdm_out: endpoint { + remote-endpoint = <&cdsp_tpda_in6>; + }; + }; + }; + }; + + tpda@11188000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x11188000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + cdsp_tpda_in0: endpoint { + remote-endpoint = <&cdsp_tpdm_out>; + }; + }; + + port@1 { + reg = <1>; + + cdsp_tpda_in1: endpoint { + remote-endpoint = <&cdsp_llm_tpdm_out>; + }; + }; + + port@2 { + reg = <2>; + + cdsp_tpda_in2: endpoint { + remote-endpoint = <&cdsp_llm2_tpdm_out>; + }; + }; + + port@3 { + reg = <3>; + + cdsp_tpda_in3: endpoint { + remote-endpoint = <&cdsp_cmsr_tpdm_out>; + }; + }; + + port@4 { + reg = <4>; + + cdsp_tpda_in4: endpoint { + remote-endpoint = <&cdsp_cmsr2_tpdm_out>; + }; + }; + + port@5 { + reg = <5>; + + cdsp_tpda_in5: endpoint { + remote-endpoint = <&cdsp_dpm1_tpdm_out>; + }; + }; + + port@6 { + reg = <6>; + + cdsp_tpda_in6: endpoint { + remote-endpoint = <&cdsp_dpm2_tpdm_out>; + }; + }; + }; + + out-ports { + port { + cdsp_tpda_out: endpoint { + remote-endpoint = <&cdsp_funnel_in0>; + }; + }; + }; + }; + + funnel@11189000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x11189000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + cdsp_funnel_in0: endpoint { + remote-endpoint = <&cdsp_tpda_out>; + }; + }; + }; + + out-ports { + port { + cdsp_funnel_out: endpoint { + remote-endpoint = <&tn_ag_in53>; + }; + }; + }; + }; + + cti@11193000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x11193000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + cti_wpss: cti@111ab000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x111ab000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tpdm@111d0000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111d0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + qm_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in35>; + }; + }; + }; + }; + + itnoc@11200000 { + compatible = "qcom,coresight-itnoc"; + reg = <0x0 0x11200000 0x0 0x3c00>; + + clocks = <&aoss_qmp>; + clock-names = "apb"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@6 { + reg = <6>; + + tn_ag_in6: endpoint { + remote-endpoint = <&mm_dsb_tpdm_out>; + }; + }; + + port@10 { + reg = <0x10>; + + tn_ag_in16: endpoint { + remote-endpoint = <&east_dsb_tpdm_out>; + }; + }; + + port@21 { + reg = <0x21>; + + tn_ag_in33: endpoint { + remote-endpoint = <&west_dsb_tpdm_out>; + }; + }; + + port@23 { + reg = <0x23>; + + tn_ag_in35: endpoint { + remote-endpoint = <&qm_tpdm_out>; + }; + }; + + port@24 { + reg = <0x24>; + + tn_ag_in36: endpoint { + remote-endpoint = <&gcc_tpdm_out>; + }; + }; + + port@32 { + reg = <0x32>; + + tn_ag_in50: endpoint { + remote-endpoint = <&pcie_rscc_tpda_out>; + }; + }; + + port@35 { + reg = <0x35>; + + tn_ag_in53: endpoint { + remote-endpoint = <&cdsp_funnel_out>; + }; + }; + + port@3f { + reg = <0x3f>; + + tn_ag_in63: endpoint { + remote-endpoint = <¢er_dsb_tpdm_out>; + }; + }; + + port@40 { + reg = <0x40>; + + tn_ag_in64: endpoint { + remote-endpoint = <&ipcc_cmb_tpdm_out>; + }; + }; + + port@41 { + reg = <0x41>; + + tn_ag_in65: endpoint { + remote-endpoint = <&qrng_tpdm_out>; + }; + }; + + port@42 { + reg = <0x42>; + + tn_ag_in66: endpoint { + remote-endpoint = <&pmu_tpdm_out>; + }; + }; + + port@43 { + reg = <0x43>; + + tn_ag_in67: endpoint { + remote-endpoint = <&rdpm_west_cmb0_tpdm_out>; + }; + }; + + port@44 { + reg = <0x44>; + + tn_ag_in68: endpoint { + remote-endpoint = <&rdpm_west_cmb1_tpdm_out>; + }; + }; + + port@45 { + reg = <0x45>; + + tn_ag_in69: endpoint { + remote-endpoint = <&rdpm_west_cmb2_tpdm_out>; + }; + }; + + port@4b { + reg = <0x4b>; + + tn_ag_in75: endpoint { + remote-endpoint = <&south_dsb2_tpdm_out>; + }; + }; + + port@52 { + reg = <0x52>; + + tn_ag_in82: endpoint { + remote-endpoint = <&south_dsb_tpdm_out>; + }; + }; + + port@53 { + reg = <0x53>; + + tn_ag_in83: endpoint { + remote-endpoint = <¢er_dsb1_tpdm_out>; + }; + }; + }; + + out-ports { + port { + tn_ag_out: endpoint { + remote-endpoint = <&funnel0_in0>; + }; + }; + }; + }; + + tpdm@11207000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11207000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + mm_dsb_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in6>; + }; + }; + }; + }; + + tpdm@1120b000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1120b000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + east_dsb_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in16>; + }; + }; + }; + }; + + tpdm@11213000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11213000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + west_dsb_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in33>; + }; + }; + }; + }; + + tpdm@11219000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11219000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + center_dsb_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in63>; + }; + }; + }; + }; + + tpdm@1121a000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1121a000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + ipcc_cmb_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in64>; + }; + }; + }; + }; + + tpdm@1121b000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1121b000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + qrng_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in65>; + }; + }; + }; + }; + + tpdm@1121c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1121c000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + pmu_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in66>; + }; + }; + }; + }; + + tpdm@1121d000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1121d000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + rdpm_west_cmb0_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in67>; + }; + }; + }; + }; + + tpdm@1121e000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1121e000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + rdpm_west_cmb1_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in68>; + }; + }; + }; + }; + + tpdm@1121f000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1121f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + rdpm_west_cmb2_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in69>; + }; + }; + }; + }; + + tpdm@11220000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11220000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + center_dsb1_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in83>; + }; + }; + }; + }; + + tpdm@11224000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11224000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + south_dsb2_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in75>; + }; + }; + }; + }; + + tpdm@11228000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11228000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + south_dsb_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in82>; + }; + }; + }; + }; + + tpdm@11470000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11470000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + pcie_rscc_tpdm_out: endpoint { + remote-endpoint = <&pcie_rscc_tpda_in0>; + }; + }; + }; + }; + + tpda@11471000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x11471000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + pcie_rscc_tpda_in0: endpoint { + remote-endpoint = <&pcie_rscc_tpdm_out>; + }; + }; + }; + + out-ports { + port { + pcie_rscc_tpda_out: endpoint { + remote-endpoint = <&tn_ag_in50>; + }; + }; + }; + }; + + tpdm@11c03000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11c03000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + swao_prio4_tpdm_out: endpoint { + remote-endpoint = <&aoss_tpda_in4>; + }; + }; + }; + }; + + funnel@11c04000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x11c04000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@5 { + reg = <5>; + + aoss_funnel_in5: endpoint { + remote-endpoint = <&aoss_tpda_out>; + }; + }; + + port@6 { + reg = <6>; + + aoss_funnel_in6: endpoint { + remote-endpoint = <&funnel0_out>; + }; + }; + }; + + out-ports { + port { + aoss_funnel_out: endpoint { + remote-endpoint = <&etf0_in>; + }; + }; + }; + }; + + tmc_etf: tmc@11c05000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x11c05000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + etf0_in: endpoint { + remote-endpoint = <&aoss_funnel_out>; + }; + }; + }; + + out-ports { + port { + etf0_out: endpoint { + remote-endpoint = <&swao_rep_in>; + }; + }; + }; + }; + + replicator@11c06000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x11c06000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + swao_rep_in: endpoint { + remote-endpoint = <&etf0_out>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + swao_rep_out1: endpoint { + remote-endpoint = <&eud_in>; + }; + }; + }; + }; + + tpda@11c08000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x11c08000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + aoss_tpda_in0: endpoint { + remote-endpoint = <&swao_prio0_tpdm_out>; + }; + }; + + port@1 { + reg = <1>; + + aoss_tpda_in1: endpoint { + remote-endpoint = <&swao_prio1_tpdm_out>; + }; + }; + + port@2 { + reg = <2>; + + aoss_tpda_in2: endpoint { + remote-endpoint = <&swao_prio2_tpdm_out>; + }; + }; + + port@3 { + reg = <3>; + + aoss_tpda_in3: endpoint { + remote-endpoint = <&swao_prio3_tpdm_out>; + }; + }; + + port@4 { + reg = <4>; + + aoss_tpda_in4: endpoint { + remote-endpoint = <&swao_prio4_tpdm_out>; + }; + }; + + port@5 { + reg = <5>; + + aoss_tpda_in5: endpoint { + remote-endpoint = <&swao_tpdm_out>; + }; + }; + }; + + out-ports { + port { + aoss_tpda_out: endpoint { + remote-endpoint = <&aoss_funnel_in5>; + }; + }; + }; + }; + + tpdm@11c09000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11c09000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + swao_prio0_tpdm_out: endpoint { + remote-endpoint = <&aoss_tpda_in0>; + }; + }; + }; + }; + + tpdm@11c0a000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11c0a000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + swao_prio1_tpdm_out: endpoint { + remote-endpoint = <&aoss_tpda_in1>; + }; + }; + }; + }; + + tpdm@11c0b000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11c0b000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + swao_prio2_tpdm_out: endpoint { + remote-endpoint = <&aoss_tpda_in2>; + }; + }; + }; + }; + + tpdm@11c0c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11c0c000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + swao_prio3_tpdm_out: endpoint { + remote-endpoint = <&aoss_tpda_in3>; + }; + }; + }; + }; + + tpdm@11c0d000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11c0d000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + swao_tpdm_out: endpoint { + remote-endpoint = <&aoss_tpda_in5>; + }; + }; + }; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,glymur-smmu-500", "qcom,smmu-500", @@ -7513,4 +8554,60 @@ gpuss-1-critical { }; }; }; + + tpdm-cdsp-llm { + compatible = "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits = <32>; + + out-ports { + port { + cdsp_llm_tpdm_out: endpoint { + remote-endpoint = <&cdsp_tpda_in1>; + }; + }; + }; + }; + + tpdm-cdsp-llm2 { + compatible = "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits = <32>; + + out-ports { + port { + cdsp_llm2_tpdm_out: endpoint { + remote-endpoint = <&cdsp_tpda_in2>; + }; + }; + }; + }; + + tpdm-cdsp-cmsr { + compatible = "qcom,coresight-static-tpdm"; + + qcom,cmb-element-bits = <32>; + qcom,dsb-element-bits = <32>; + + out-ports { + port { + cdsp_cmsr_tpdm_out: endpoint { + remote-endpoint = <&cdsp_tpda_in3>; + }; + }; + }; + }; + + tpdm-cdsp-cmsr2 { + compatible = "qcom,coresight-static-tpdm"; + + qcom,cmb-element-bits = <32>; + qcom,dsb-element-bits = <32>; + + out-ports { + port { + cdsp_cmsr2_tpdm_out: endpoint { + remote-endpoint = <&cdsp_tpda_in4>; + }; + }; + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/mahua.dtsi b/arch/arm64/boot/dts/qcom/mahua.dtsi index 990a02c6afc1..22822b6b2e8b 100644 --- a/arch/arm64/boot/dts/qcom/mahua.dtsi +++ b/arch/arm64/boot/dts/qcom/mahua.dtsi @@ -21,6 +21,7 @@ /delete-node/ &cpu_pd15; /delete-node/ &cpu_pd16; /delete-node/ &cpu_pd17; +/delete-node/ &cti_wpss; /delete-node/ &thermal_aoss_6; /delete-node/ &thermal_aoss_7; /delete-node/ &thermal_cpu_2_0_0; From b39a174a535841e71c59661cc92408b710e0fe6a Mon Sep 17 00:00:00 2001 From: Alexander Koskovich Date: Wed, 1 Apr 2026 02:25:07 +0000 Subject: [PATCH 411/665] arm64: dts: qcom: milos: Add qfprom efuse node Add the qfprom efuse node and describe where the GPU speedbin fuse is located on Milos. Note that for SM7635-AB at least, the value is "221", the max frequency for this is 1050MHz. There's another speedbin out there for 1150MHz but we do not know the value for it so just document in this commit. Once the value is discovered we should add the speedbins to the A810 Adreno entry and update devicetree. Signed-off-by: Alexander Koskovich Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260331-milos-qfprom-v1-2-36017cc642db@pm.me Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/milos.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi index 886d8514ce33..8c9232988953 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -1331,6 +1331,18 @@ tcsr: clock-controller@1fc0000 { #reset-cells = <1>; }; + qfprom: efuse@221c8000 { + compatible = "qcom,milos-qfprom", "qcom,qfprom"; + reg = <0x0 0x221c8000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + gpu_speed_bin: gpu-speed-bin@138 { + reg = <0x138 0x2>; + bits = <0 9>; + }; + }; + remoteproc_adsp: remoteproc@3000000 { compatible = "qcom,milos-adsp-pas"; reg = <0x0 0x03000000 0x0 0x10000>; From db9900e518b2992cbbcbfb7572c2d436ec0feb6d Mon Sep 17 00:00:00 2001 From: Pankaj Patil Date: Tue, 31 Mar 2026 19:24:21 +0530 Subject: [PATCH 412/665] arm64: dts: qcom: glymur: Add qfprom efuse node Add the qfprom (Qualcomm Fuse ROM) efuse node and gpu speed bin child node for Glymur SoC Signed-off-by: Pankaj Patil Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260331-glymur-qfprom-v1-2-5b4284d23c80@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index ca0fd85e2946..b129e268aab4 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -7336,6 +7336,18 @@ nsp_noc: interconnect@320c0000 { #interconnect-cells = <2>; }; + qfprom: efuse@361c8000 { + compatible = "qcom,glymur-qfprom", "qcom,qfprom"; + reg = <0x0 0x361c8000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + gpu_speed_bin: gpu-speed-bin@138 { + reg = <0x138 0x2>; + bits = <0 9>; + }; + }; + imem: sram@81e08600 { compatible = "mmio-sram"; reg = <0x0 0x81e08600 0x0 0x300>; From 0299c007e6f34a2a5b724c332b86be77409ea729 Mon Sep 17 00:00:00 2001 From: Shuai Zhang Date: Wed, 29 Apr 2026 18:35:37 +0800 Subject: [PATCH 413/665] arm64: dts: qcom: monaco-arduino-monza: Add Bluetooth UART node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The QCA2066 Bluetooth chip is powered by a board-level 3.3 V supply provided by the hardware. This change connects the Bluetooth controller via UART10, and the corresponding GPIO is used to enable the Bluetooth chip. basic function test step: - bluetoothctl power on/off - bluetoothctl scan bredr/le - bluetoothctl pair - bluetoothctl connect low-state test and state: - rtcwake -d /dev/rtc0 -m no -s 30 && systemctl suspend cat /sys/kernel/debug/suspend_stats success: 1 fail: 0 failed_freeze: 0 failed_prepare: 0 failed_suspend: 0 failed_suspend_late: 0 failed_suspend_noirq: 0 failed_resume: 0 failed_resume_early: 0 failed_resume_noirq: 0 failures: last_failed_dev: last_failed_errno: 0 0 last_failed_step: Signed-off-by: Shuai Zhang Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260429103537.1282497-1-shuai.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts index ca14f0ea4dae..379b796f261f 100644 --- a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts +++ b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts @@ -21,6 +21,7 @@ aliases { ethernet0 = ðernet0; i2c1 = &i2c1; serial0 = &uart7; + serial1 = &uart10; }; chosen { @@ -454,6 +455,16 @@ &uart7 { status = "okay"; }; +&uart10 { + status = "okay"; + + bluetooth: bluetooth { + compatible = "qcom,qca2066-bt"; + enable-gpios = <&tlmm 55 GPIO_ACTIVE_HIGH>; + clocks = <&sleep_clk>; + }; +}; + &usb_1 { status = "okay"; }; From f3cd85f60c5eb2d817af6c62465018dd941ce4f3 Mon Sep 17 00:00:00 2001 From: Joel Selvaraj Date: Wed, 29 Apr 2026 15:16:53 +0200 Subject: [PATCH 414/665] arm64: dts: qcom: sdm845-xiaomi-beryllium: Correct IPA FW path The path was accidentally reverted back to old while refactoring of the device-tree. Fixes: 5bde31dc7b17 ("arm64: dts: qcom: sdm845-xiaomi-beryllium: Add placeholders and sort") Signed-off-by: Joel Selvaraj Signed-off-by: David Heidelberg Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260429-beryllium-ipa-fix-v1-1-816326ba9047@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index 9b7fdbca9e1c..54e58ca04693 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -287,7 +287,7 @@ &ibb { &ipa { qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; - firmware-name = "qcom/sdm845/beryllium/ipa_fws.mbn"; + firmware-name = "qcom/sdm845/Xiaomi/beryllium/ipa_fws.mbn"; status = "okay"; }; From 7a473107f9785700a5c57cee69f60c19a9703f95 Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Mon, 11 May 2026 16:26:41 +0530 Subject: [PATCH 415/665] arm64: dts: qcom: ipq5210: add watchdog node Add the watchdog device node for IPQ5210 SoC. Signed-off-by: Kathiravan Thirumoorthy Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260511-ipq5210_wdt-v1-1-870c4b7f77b6@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5210.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi index 3761eb03ab24..2cdc10529c48 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -236,6 +236,13 @@ v2m2: v2m@2000 { }; }; + watchdog@b017000 { + compatible = "qcom,apss-wdt-ipq5210", "qcom,kpss-wdt"; + reg = <0x0 0x0b017000 0x0 0x1000>; + interrupts = ; + clocks = <&sleep_clk>; + }; + timer@b120000 { compatible = "arm,armv7-timer-mem"; reg = <0x0 0x0b120000 0x0 0x1000>; From 6ba85ffe796ab4eff37e3229999b34a99954fb49 Mon Sep 17 00:00:00 2001 From: Xilin Wu Date: Thu, 7 May 2026 22:34:35 +0800 Subject: [PATCH 416/665] arm64: dts: qcom: sc8280xp: drop unused polling-delay-passive properties Remove the unused polling-delay-passive properties from thermal nodes without a passive trip point. Signed-off-by: Xilin Wu Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260507-sc8280xp-thermal-zones-v1-1-33d4395b1be9@radxa.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index afe3f8018b22..a2bd6b10e475 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -6898,8 +6898,6 @@ sound: sound { thermal-zones { cpu0-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens0 1>; trips { @@ -6912,8 +6910,6 @@ cpu-crit { }; cpu1-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens0 2>; trips { @@ -6926,8 +6922,6 @@ cpu-crit { }; cpu2-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens0 3>; trips { @@ -6940,8 +6934,6 @@ cpu-crit { }; cpu3-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens0 4>; trips { @@ -6954,8 +6946,6 @@ cpu-crit { }; cpu4-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens0 5>; trips { @@ -6968,8 +6958,6 @@ cpu-crit { }; cpu5-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens0 6>; trips { @@ -6982,8 +6970,6 @@ cpu-crit { }; cpu6-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens0 7>; trips { @@ -6996,8 +6982,6 @@ cpu-crit { }; cpu7-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens0 8>; trips { @@ -7010,8 +6994,6 @@ cpu-crit { }; cluster0-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens0 9>; trips { @@ -7051,8 +7033,6 @@ trip-point1 { }; mem-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens1 15>; trips { From 1daf54d8100e0e92c826ac8a2b888008b2571cc0 Mon Sep 17 00:00:00 2001 From: Saurabh Anand Date: Fri, 15 May 2026 12:44:48 +0530 Subject: [PATCH 417/665] arm64: dts: qcom: sm8750: allow mode-switch events to reach the QMP Combo PHY Allow mode-switch events to reach the QMP Combo PHY to support setting the QMP Combo PHY in DP 4Lanes Altmode. Signed-off-by: Saurabh Anand Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260515071448.1845500-1-saurabh.anand@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 4e0ae737c281..fafed417c66f 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -2794,6 +2794,7 @@ usb_dp_qmpphy: phy@88e8000 { #clock-cells = <1>; #phy-cells = <1>; + mode-switch; orientation-switch; status = "disabled"; From 181bef739979466b6ede95b34d6c94d0250b1c0e Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Fri, 15 May 2026 11:53:23 +0530 Subject: [PATCH 418/665] arm64: dts: qcom: hamoa-iot-evk: add MCP2518FD CAN on spi18 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the Microchip MCP2518FD CAN-FD controller on hamoa. The controller is connected via SPI18 and uses a 40 MHz oscillator. Signed-off-by: Viken Dadhaniya Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260515-hamoa-spi-can-devicetree-v2-1-d0e922608065@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts index 460f27dcd6f6..c7ba4b353ddd 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -29,6 +29,14 @@ backlight: backlight { pinctrl-names = "default"; }; + clocks { + mcp2518fd_osc: clock-40000000 { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + #clock-cells = <0>; + }; + }; + wcd938x: audio-codec { compatible = "qcom,wcd9385-codec"; @@ -1227,6 +1235,19 @@ tpm@0 { }; }; +&spi18 { + status = "okay"; + + can@0 { + compatible = "microchip,mcp2518fd"; + reg = <0>; + interrupts-extended = <&tlmm 68 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mcp2518fd_osc>; + spi-max-frequency = <14000000>; + microchip,xstbyen; + }; +}; + &swr0 { status = "okay"; From fe9f4a46895dc3062cedcdd38772dd578de9e62f Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Wed, 13 May 2026 13:25:48 -0400 Subject: [PATCH 419/665] arm64: dts: qcom: sdm670-google: add common device tree include The Pixel 3a XL can be supported by reusing most of the device tree from the Pixel 3a. Move the common elements to a common device tree include like with other devices. Since the original devicetree should only specify non-XL properties, it needs to be completely rewritten. Also change the SPDX license identifier from GPL-2.0 (which was deprecated as it can be misinterpreted as GPLv2 or later) into GPL-2.0-only. Signed-off-by: Richard Acayan Reviewed-by: Konrad Dybcio Assisted-by: "Claude Code Review Bot":claude-opus-4-6 Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260513172549.1345-2-mailingradian@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm670-google-common.dtsi | 712 +++++++++++++++++ .../boot/dts/qcom/sdm670-google-sargo.dts | 714 +----------------- 2 files changed, 725 insertions(+), 701 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sdm670-google-common.dtsi diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-common.dtsi b/arch/arm64/boot/dts/qcom/sdm670-google-common.dtsi new file mode 100644 index 000000000000..0f57b915186b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm670-google-common.dtsi @@ -0,0 +1,712 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device tree for Google Pixel 3a, adapted from google-blueline device tree, + * xiaomi-lavender device tree, and oneplus-common device tree. + * + * Copyright (c) 2022, Richard Acayan. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include "sdm670.dtsi" +#include "pm660.dtsi" +#include "pm660l.dtsi" + +/delete-node/ &mpss_region; +/delete-node/ &venus_mem; +/delete-node/ &wlan_msa_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &mba_region; +/delete-node/ &adsp_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &ipa_gsi_mem; +/delete-node/ &gpu_mem; + +/ { + aliases { }; + + battery: battery { + compatible = "simple-battery"; + + voltage-min-design-microvolt = <3312000>; + voltage-max-design-microvolt = <4400000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer: framebuffer@9c000000 { + compatible = "simple-framebuffer"; + memory-region = <&fb_mem>; + width = <1080>; + /* height is in specific device trees */ + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&vol_up_pin>; + + key-vol-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + + mpss_region: mpss@8b000000 { + reg = <0 0x8b000000 0 0x9800000>; + no-map; + }; + + venus_mem: venus@94800000 { + reg = <0 0x94800000 0 0x500000>; + no-map; + }; + + wlan_msa_mem: wlan-msa@94d00000 { + reg = <0 0x94d00000 0 0x100000>; + no-map; + }; + + cdsp_mem: cdsp@94e00000 { + reg = <0 0x94e00000 0 0x800000>; + no-map; + }; + + mba_region: mba@95600000 { + reg = <0 0x95600000 0 0x200000>; + no-map; + }; + + adsp_mem: adsp@95800000 { + reg = <0 0x95800000 0 0x2200000>; + no-map; + }; + + ipa_fw_mem: ipa-fw@97a00000 { + reg = <0 0x97a00000 0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi@97a10000 { + reg = <0 0x97a10000 0 0x5000>; + no-map; + }; + + gpu_mem: gpu@97a15000 { + reg = <0 0x97a15000 0 0x2000>; + no-map; + }; + + fb_mem: framebuffer-region@9c000000 { + reg = <0 0x9c000000 0 0x2400000>; + no-map; + }; + + /* Also includes ramoops regions */ + debug_info_mem: debug-info@a1800000 { + reg = <0 0xa1800000 0 0x411000>; + no-map; + }; + }; + + /* + * The touchscreen regulator seems to be controlled somehow by a gpio. + * Model it as a fixed regulator and keep it on. Without schematics we + * don't know how this is actually wired up... + */ + ts_1p8_supply: ts-1p8-regulator { + compatible = "regulator-fixed"; + regulator-name = "ts_1p8_supply"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm660_gpios 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3312000>; + + regulator-always-on; + regulator-boot-on; + }; + + /* + * Supply map from xiaomi-lavender specifies this as the supply for + * ldob1, ldob9, ldob10, ldoa2, and ldoa3, while downstream specifies + * this as a power domain. Set this as a fixed regulator with the same + * voltage as lavender until display is needed to avoid unneccessarily + * using a deprecated binding (regulator-fixed-domain). + */ + vreg_s2b_1p05: vreg-s2b-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_s2b"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + cam_front_ldo: cam-front-ldo-regulator { + compatible = "regulator-fixed"; + regulator-name = "cam_front_ldo"; + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + regulator-enable-ramp-delay = <135>; + + gpios = <&pm660l_gpios 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&cam_front_ldo_pin>; + pinctrl-names = "default"; + }; + + cam_vio_ldo: cam-vio-ldo-regulator { + compatible = "regulator-fixed"; + regulator-name = "cam_vio_ldo"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <233>; + + gpios = <&pm660_gpios 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&cam_vio_pin>; + pinctrl-names = "default"; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm660-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + vdd-l1-l6-l7-supply = <&vreg_s6a_0p87>; + vdd-l2-l3-supply = <&vreg_s2b_1p05>; + vdd-l5-supply = <&vreg_s2b_1p05>; + vdd-l8-l9-l10-l11-l12-l13-l14-supply = <&vreg_s4a_2p04>; + vdd-l15-l16-l17-l18-l19-supply = <&vreg_bob>; + + /* + * S1A (FTAPC0), S2A (FTAPC1), S3A (HFAPC1) are managed + * by the Core Power Reduction hardened (CPRh) and the + * Operating State Manager (OSM) HW automatically. + */ + + vreg_s4a_2p04: smps4 { + regulator-min-microvolt = <1808000>; + regulator-max-microvolt = <2040000>; + regulator-enable-ramp-delay = <200>; + }; + + vreg_s6a_0p87: smps6 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1352000>; + regulator-enable-ramp-delay = <150>; + }; + + /* LDOs */ + vreg_l1a_1p225: ldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1250000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l2a_1p0: ldo2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l3a_1p0: ldo3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l5a_0p848: ldo5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l6a_1p3: ldo6 { + regulator-min-microvolt = <1248000>; + regulator-max-microvolt = <1304000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l7a_1p2: ldo7 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l8a_1p8: ldo8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + regulator-always-on; + }; + + vreg_l9a_1p8: ldo9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l10a_1p8: ldo10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l11a_1p8: ldo11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l13a_1p8: ldo13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l14a_1p8: ldo14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l15a_1p8: ldo15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l16a_2p7: ldo16 { + regulator-min-microvolt = <2696000>; + regulator-max-microvolt = <2696000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l17a_1p8: ldo17 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l19a_3p3: ldo19 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-enable-ramp-delay = <250>; + }; + }; + + regulators-1 { + compatible = "qcom,pm660l-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + + vdd-l1-l9-l10-supply = <&vreg_s2b_1p05>; + vdd-l2-supply = <&vreg_bob>; + vdd-l3-l5-l7-l8-supply = <&vreg_bob>; + vdd-l4-l6-supply = <&vreg_bob>; + vdd-bob-supply = <&vph_pwr>; + + /* LDOs */ + vreg_l1b_0p925: ldo1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <900000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l2b_2p95: ldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l3b_3p0: ldo3 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3008000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l4b_2p95: ldo4 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l5b_2p95: ldo5 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l6b_3p3: ldo6 { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l7b_3p125: ldo7 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3100000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l8b_3p3: ldo8 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3312000>; + regulator-enable-ramp-delay = <250>; + }; + + /* + * Downstream specifies a fixed voltage of 3.312 V, but the + * PMIC4 BOB ranges don't support that. Widen the range a + * little to avoid adding a new BOB regulator type. + */ + vreg_bob: bob { + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3328000>; + regulator-enable-ramp-delay = <500>; + }; + }; +}; + +&camss { + vdda-phy-supply = <&vreg_l1a_1p225>; + vdda-pll-supply = <&vreg_s6a_0p87>; + + status = "okay"; +}; + +&camss_port1 { + camss_endpoint1: endpoint { + data-lanes = <0 1 2 3>; + remote-endpoint = <&cam_front_endpoint>; + }; +}; + +&cci { + pinctrl-0 = <&cci1_default>; + pinctrl-1 = <&cci1_sleep>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&cci_i2c1 { + camera@1a { + compatible = "sony,imx355"; + reg = <0x1a>; + + clocks = <&camcc CAM_CC_MCLK2_CLK>; + + /* + * The sensor can accept a 24 MHz clock, but 19.2 MHz has + * better driver compatibility. + */ + assigned-clocks = <&camcc CAM_CC_MCLK2_CLK>; + assigned-clock-rates = <19200000>; + + reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; + + avdd-supply = <&cam_front_ldo>; + dvdd-supply = <&cam_front_ldo>; + dovdd-supply = <&cam_vio_ldo>; + + pinctrl-0 = <&cam_mclk2_default>; + pinctrl-names = "default"; + + rotation = <270>; + orientation = <0>; + + port { + cam_front_endpoint: endpoint { + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <360000000>; + remote-endpoint = <&camss_endpoint1>; + }; + }; + }; +}; + +&gcc { + protected-clocks = , + , + ; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/sdm670/sargo/a615_zap.mbn"; +}; + +&i2c9 { + clock-frequency = <100000>; + status = "okay"; + + synaptics-rmi4-i2c@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_default>; + + vio-supply = <&ts_1p8_supply>; + + syna,reset-delay-ms = <200>; + syna,startup-delay-ms = <200>; + + #address-cells = <1>; + #size-cells = <0>; + + rmi4-f01@1 { + reg = <0x01>; + syna,nosleep-mode = <1>; + }; + + rmi4_f12: rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; + }; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l1a_1p225>; + status = "okay"; + + panel: panel@0 { + /* compatible is provided in specific device trees */ + reg = <0>; + + reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_default>; + + power-supply = <&vreg_l6b_3p3>; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l1b_0p925>; + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + +&pm660_charger { + monitored-battery = <&battery>; + status = "okay"; +}; + +&pm660_gpios { + cam_vio_pin: cam-vio-state { + pins = "gpio13"; + function = "normal"; + power-source = <0>; + }; +}; + +&pm660_rradc { + status = "okay"; +}; + +&pm660l_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <1>, <2>; + led-max-microamp = <500000>; + flash-max-microamp = <1500000>; + flash-max-timeout-us = <1280000>; + }; +}; + +&pm660l_gpios { + cam_front_ldo_pin: cam-front-state { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + }; + + vol_up_pin: vol-up-state { + pins = "gpio7"; + function = "normal"; + qcom,drive-strength = ; + input-enable; + bias-pull-up; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&sdhc_1 { + supports-cqe; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-ddr-1_8v; + + qcom,ddr-config = <0xc3040873>; + + vmmc-supply = <&vreg_l4b_2p95>; + vqmmc-supply = <&vreg_l8a_1p8>; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <81 4>; + + panel_default: panel-default-state { + te-pins { + pins = "gpio10"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + reset-pins { + pins = "gpio75"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + mode-pins { + pins = "gpio76"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + }; + + touchscreen_default: ts-default-state { + ts-reset-pins { + pins = "gpio99"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + output-high; + }; + + ts-irq-pins { + pins = "gpio125"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + ts-switch-pins { + pins = "gpio135"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l1b_0p925>; + vdda-pll-supply = <&vreg_l10a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l7b_3p125>; + + status = "okay"; +}; + +&usb_1 { + qcom,select-utmi-as-pipe-clk; + status = "okay"; +}; + +&usb_1_dwc3 { + /* Only peripheral works for now */ + dr_mode = "peripheral"; + + /* Do not assume that sdm670.dtsi will never support USB 3.0 */ + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts index eba2f3792dd0..c67a0396436b 100644 --- a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts +++ b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts @@ -1,720 +1,32 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* - * Device tree for Google Pixel 3a, adapted from google-blueline device tree, - * xiaomi-lavender device tree, and oneplus-common device tree. + * Device tree for Google Pixel 3a (non-XL). * - * Copyright (c) 2022, Richard Acayan. All rights reserved. + * Copyright (c) Richard Acayan. All rights reserved. */ /dts-v1/; -#include -#include -#include -#include -#include -#include "sdm670.dtsi" -#include "pm660.dtsi" -#include "pm660l.dtsi" - -/delete-node/ &mpss_region; -/delete-node/ &venus_mem; -/delete-node/ &wlan_msa_mem; -/delete-node/ &cdsp_mem; -/delete-node/ &mba_region; -/delete-node/ &adsp_mem; -/delete-node/ &ipa_fw_mem; -/delete-node/ &ipa_gsi_mem; -/delete-node/ &gpu_mem; +#include "sdm670-google-common.dtsi" / { model = "Google Pixel 3a"; compatible = "google,sargo", "qcom,sdm670"; - - aliases { }; - - battery: battery { - compatible = "simple-battery"; - - voltage-min-design-microvolt = <3312000>; - voltage-max-design-microvolt = <4400000>; - charge-full-design-microamp-hours = <3000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - framebuffer@9c000000 { - compatible = "simple-framebuffer"; - reg = <0 0x9c000000 0 (1080 * 2220 * 4)>; - width = <1080>; - height = <2220>; - stride = <(1080 * 4)>; - format = "a8r8g8b8"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&vol_up_pin>; - - key-vol-up { - label = "Volume Up"; - linux,code = ; - gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - - mpss_region: mpss@8b000000 { - reg = <0 0x8b000000 0 0x9800000>; - no-map; - }; - - venus_mem: venus@94800000 { - reg = <0 0x94800000 0 0x500000>; - no-map; - }; - - wlan_msa_mem: wlan-msa@94d00000 { - reg = <0 0x94d00000 0 0x100000>; - no-map; - }; - - cdsp_mem: cdsp@94e00000 { - reg = <0 0x94e00000 0 0x800000>; - no-map; - }; - - mba_region: mba@95600000 { - reg = <0 0x95600000 0 0x200000>; - no-map; - }; - - adsp_mem: adsp@95800000 { - reg = <0 0x95800000 0 0x2200000>; - no-map; - }; - - ipa_fw_mem: ipa-fw@97a00000 { - reg = <0 0x97a00000 0 0x10000>; - no-map; - }; - - ipa_gsi_mem: ipa-gsi@97a10000 { - reg = <0 0x97a10000 0 0x5000>; - no-map; - }; - - gpu_mem: gpu@97a15000 { - reg = <0 0x97a15000 0 0x2000>; - no-map; - }; - - framebuffer-region@9c000000 { - reg = <0 0x9c000000 0 0x2400000>; - no-map; - }; - - /* Also includes ramoops regions */ - debug_info_mem: debug-info@a1800000 { - reg = <0 0xa1800000 0 0x411000>; - no-map; - }; - }; - - /* - * The touchscreen regulator seems to be controlled somehow by a gpio. - * Model it as a fixed regulator and keep it on. Without schematics we - * don't know how this is actually wired up... - */ - ts_1p8_supply: ts-1p8-regulator { - compatible = "regulator-fixed"; - regulator-name = "ts_1p8_supply"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&pm660_gpios 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-min-microvolt = <3312000>; - regulator-max-microvolt = <3312000>; - - regulator-always-on; - regulator-boot-on; - }; - - /* - * Supply map from xiaomi-lavender specifies this as the supply for - * ldob1, ldob9, ldob10, ldoa2, and ldoa3, while downstream specifies - * this as a power domain. Set this as a fixed regulator with the same - * voltage as lavender until display is needed to avoid unneccessarily - * using a deprecated binding (regulator-fixed-domain). - */ - vreg_s2b_1p05: vreg-s2b-regulator { - compatible = "regulator-fixed"; - regulator-name = "vreg_s2b"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - cam_front_ldo: cam-front-ldo-regulator { - compatible = "regulator-fixed"; - regulator-name = "cam_front_ldo"; - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - regulator-enable-ramp-delay = <135>; - - gpios = <&pm660l_gpios 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&cam_front_ldo_pin>; - pinctrl-names = "default"; - }; - - cam_vio_ldo: cam-vio-ldo-regulator { - compatible = "regulator-fixed"; - regulator-name = "cam_vio_ldo"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <233>; - - gpios = <&pm660_gpios 13 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&cam_vio_pin>; - pinctrl-names = "default"; - }; }; -&apps_rsc { - regulators-0 { - compatible = "qcom,pm660-rpmh-regulators"; - qcom,pmic-id = "a"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - vdd-s4-supply = <&vph_pwr>; - vdd-s5-supply = <&vph_pwr>; - vdd-s6-supply = <&vph_pwr>; - - vdd-l1-l6-l7-supply = <&vreg_s6a_0p87>; - vdd-l2-l3-supply = <&vreg_s2b_1p05>; - vdd-l5-supply = <&vreg_s2b_1p05>; - vdd-l8-l9-l10-l11-l12-l13-l14-supply = <&vreg_s4a_2p04>; - vdd-l15-l16-l17-l18-l19-supply = <&vreg_bob>; - - /* - * S1A (FTAPC0), S2A (FTAPC1), S3A (HFAPC1) are managed - * by the Core Power Reduction hardened (CPRh) and the - * Operating State Manager (OSM) HW automatically. - */ - - vreg_s4a_2p04: smps4 { - regulator-min-microvolt = <1808000>; - regulator-max-microvolt = <2040000>; - regulator-enable-ramp-delay = <200>; - }; - - vreg_s6a_0p87: smps6 { - regulator-min-microvolt = <1224000>; - regulator-max-microvolt = <1352000>; - regulator-enable-ramp-delay = <150>; - }; - - /* LDOs */ - vreg_l1a_1p225: ldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1250000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l2a_1p0: ldo2 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l3a_1p0: ldo3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l5a_0p848: ldo5 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l6a_1p3: ldo6 { - regulator-min-microvolt = <1248000>; - regulator-max-microvolt = <1304000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l7a_1p2: ldo7 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l8a_1p8: ldo8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <250>; - regulator-always-on; - }; - - vreg_l9a_1p8: ldo9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l10a_1p8: ldo10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l11a_1p8: ldo11 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l12a_1p8: ldo12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l13a_1p8: ldo13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l14a_1p8: ldo14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l15a_1p8: ldo15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l16a_2p7: ldo16 { - regulator-min-microvolt = <2696000>; - regulator-max-microvolt = <2696000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l17a_1p8: ldo17 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l19a_3p3: ldo19 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3312000>; - regulator-enable-ramp-delay = <250>; - }; - }; - - regulators-1 { - compatible = "qcom,pm660l-rpmh-regulators"; - qcom,pmic-id = "b"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-s4-supply = <&vph_pwr>; - vdd-s5-supply = <&vph_pwr>; - - vdd-l1-l9-l10-supply = <&vreg_s2b_1p05>; - vdd-l2-supply = <&vreg_bob>; - vdd-l3-l5-l7-l8-supply = <&vreg_bob>; - vdd-l4-l6-supply = <&vreg_bob>; - vdd-bob-supply = <&vph_pwr>; - - /* LDOs */ - vreg_l1b_0p925: ldo1 { - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <900000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l2b_2p95: ldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2960000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l3b_3p0: ldo3 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3008000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l4b_2p95: ldo4 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l5b_2p95: ldo5 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l6b_3p3: ldo6 { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l7b_3p125: ldo7 { - regulator-min-microvolt = <3088000>; - regulator-max-microvolt = <3100000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l8b_3p3: ldo8 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3312000>; - regulator-enable-ramp-delay = <250>; - }; - - /* - * Downstream specifies a fixed voltage of 3.312 V, but the - * PMIC4 BOB ranges don't support that. Widen the range a - * little to avoid adding a new BOB regulator type. - */ - vreg_bob: bob { - regulator-min-microvolt = <3296000>; - regulator-max-microvolt = <3328000>; - regulator-enable-ramp-delay = <500>; - }; - }; +&battery { + charge-full-design-microamp-hours = <3000000>; }; -&camss { - vdda-phy-supply = <&vreg_l1a_1p225>; - vdda-pll-supply = <&vreg_s6a_0p87>; - - status = "okay"; +&framebuffer { + height = <2220>; }; -&camss_port1 { - camss_endpoint1: endpoint { - data-lanes = <0 1 2 3>; - remote-endpoint = <&cam_front_endpoint>; - }; +&panel { + compatible = "samsung,s6e3fa7-ams559nk06"; }; -&cci { - pinctrl-0 = <&cci1_default>; - pinctrl-1 = <&cci1_sleep>; - pinctrl-names = "default", "sleep"; - - status = "okay"; -}; - -&cci_i2c1 { - camera@1a { - compatible = "sony,imx355"; - reg = <0x1a>; - - clocks = <&camcc CAM_CC_MCLK2_CLK>; - - /* - * The sensor can accept a 24 MHz clock, but 19.2 MHz has - * better driver compatibility. - */ - assigned-clocks = <&camcc CAM_CC_MCLK2_CLK>; - assigned-clock-rates = <19200000>; - - reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; - - avdd-supply = <&cam_front_ldo>; - dvdd-supply = <&cam_front_ldo>; - dovdd-supply = <&cam_vio_ldo>; - - pinctrl-0 = <&cam_mclk2_default>; - pinctrl-names = "default"; - - rotation = <270>; - orientation = <0>; - - port { - cam_front_endpoint: endpoint { - data-lanes = <1 2 3 4>; - link-frequencies = /bits/ 64 <360000000>; - remote-endpoint = <&camss_endpoint1>; - }; - }; - }; -}; - -&gcc { - protected-clocks = , - , - ; -}; - -&gpi_dma1 { - status = "okay"; -}; - -&gpu { - status = "okay"; -}; - -&gpu_zap_shader { - firmware-name = "qcom/sdm670/sargo/a615_zap.mbn"; -}; - -&i2c9 { - clock-frequency = <100000>; - status = "okay"; - - synaptics-rmi4-i2c@20 { - compatible = "syna,rmi4-i2c"; - reg = <0x20>; - interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>; - - pinctrl-names = "default"; - pinctrl-0 = <&touchscreen_default>; - - vio-supply = <&ts_1p8_supply>; - - syna,reset-delay-ms = <200>; - syna,startup-delay-ms = <200>; - - #address-cells = <1>; - #size-cells = <0>; - - rmi4-f01@1 { - reg = <0x01>; - syna,nosleep-mode = <1>; - }; - - rmi4-f12@12 { - reg = <0x12>; - touchscreen-x-mm = <62>; - touchscreen-y-mm = <127>; - syna,sensor-type = <1>; - }; - }; -}; - -&mdss { - status = "okay"; -}; - -&mdss_dsi0 { - vdda-supply = <&vreg_l1a_1p225>; - status = "okay"; - - panel@0 { - compatible = "samsung,s6e3fa7-ams559nk06"; - reg = <0>; - - reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&panel_default>; - - power-supply = <&vreg_l6b_3p3>; - - port { - panel_in: endpoint { - remote-endpoint = <&mdss_dsi0_out>; - }; - }; - }; -}; - -&mdss_dsi0_out { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; -}; - -&mdss_dsi0_phy { - vdds-supply = <&vreg_l1b_0p925>; - status = "okay"; -}; - -&mdss_mdp { - status = "okay"; -}; - -&pm660_charger { - monitored-battery = <&battery>; - status = "okay"; -}; - -&pm660_gpios { - cam_vio_pin: cam-vio-state { - pins = "gpio13"; - function = "normal"; - power-source = <0>; - }; -}; - -&pm660_rradc { - status = "okay"; -}; - -&pm660l_flash { - status = "okay"; - - led-0 { - function = LED_FUNCTION_FLASH; - color = ; - led-sources = <1>, <2>; - led-max-microamp = <500000>; - flash-max-microamp = <1500000>; - flash-max-timeout-us = <1280000>; - }; -}; - -&pm660l_gpios { - cam_front_ldo_pin: cam-front-state { - pins = "gpio4"; - function = "normal"; - power-source = <0>; - }; - - vol_up_pin: vol-up-state { - pins = "gpio7"; - function = "normal"; - qcom,drive-strength = ; - input-enable; - bias-pull-up; - }; -}; - -&pon_pwrkey { - status = "okay"; -}; - -&pon_resin { - linux,code = ; - status = "okay"; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -&sdhc_1 { - supports-cqe; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - mmc-ddr-1_8v; - - qcom,ddr-config = <0xc3040873>; - - vmmc-supply = <&vreg_l4b_2p95>; - vqmmc-supply = <&vreg_l8a_1p8>; - - status = "okay"; -}; - -&tlmm { - gpio-reserved-ranges = <0 4>, <81 4>; - - panel_default: panel-default-state { - te-pins { - pins = "gpio10"; - function = "mdp_vsync"; - drive-strength = <2>; - bias-pull-down; - }; - - reset-pins { - pins = "gpio75"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - - mode-pins { - pins = "gpio76"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - }; - - touchscreen_default: ts-default-state { - ts-reset-pins { - pins = "gpio99"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - output-high; - }; - - ts-irq-pins { - pins = "gpio125"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - ts-switch-pins { - pins = "gpio135"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - output-low; - }; - }; -}; - -&usb_1_hsphy { - vdd-supply = <&vreg_l1b_0p925>; - vdda-pll-supply = <&vreg_l10a_1p8>; - vdda-phy-dpdm-supply = <&vreg_l7b_3p125>; - - status = "okay"; -}; - -&usb_1 { - qcom,select-utmi-as-pipe-clk; - status = "okay"; -}; - -&usb_1_dwc3 { - /* Only peripheral works for now */ - dr_mode = "peripheral"; - - /* Do not assume that sdm670.dtsi will never support USB 3.0 */ - phys = <&usb_1_hsphy>; - phy-names = "usb2-phy"; - maximum-speed = "high-speed"; +&rmi4_f12 { + touchscreen-x-mm = <62>; + touchscreen-y-mm = <127>; }; From f3919fa784a3e6dd557dfe2c41072f55742e013f Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Wed, 13 May 2026 13:25:49 -0400 Subject: [PATCH 420/665] arm64: dts: qcom: add support for pixel 3a xl with the tianma panel The Pixel 3a XL has variants with either a Samsung Display Controller (SDC) panel or a Tianma panel. Add the device tree for the variant with the Tianma panel. Signed-off-by: Richard Acayan Reviewed-by: Konrad Dybcio Assisted-by: "Claude Code Review Bot":claude-opus-4-6 Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260513172549.1345-3-mailingradian@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../dts/qcom/sdm670-google-bonito-tianma.dts | 32 +++++++++++++++++++ 2 files changed, 33 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm670-google-bonito-tianma.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 795cee4757ab..6f33c4e2f09c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -308,6 +308,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm632-fairphone-fp3.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm632-motorola-ocean.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm670-google-bonito-tianma.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm670-google-sargo.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-bonito-tianma.dts b/arch/arm64/boot/dts/qcom/sdm670-google-bonito-tianma.dts new file mode 100644 index 000000000000..42ddaf53d150 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm670-google-bonito-tianma.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device tree for Google Pixel 3a XL with the Tianma panel. + * + * Copyright (c) Richard Acayan. All rights reserved. + */ + +/dts-v1/; + +#include "sdm670-google-common.dtsi" + +/ { + model = "Google Pixel 3a XL (with Tianma panel)"; + compatible = "google,bonito-tianma", "google,bonito", "qcom,sdm670"; +}; + +&battery { + charge-full-design-microamp-hours = <3700000>; +}; + +&framebuffer { + height = <2160>; +}; + +&panel { + compatible = "novatek,nt37700f"; +}; + +&rmi4_f12 { + touchscreen-x-mm = <69>; + touchscreen-y-mm = <137>; +}; From 0e400da642d2b9830b0d41b431dbf12cd7921b52 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Thu, 9 Apr 2026 21:49:59 -0500 Subject: [PATCH 421/665] riscv: dts: tenstorrent: Add PMU node to blackhole for Linux perf support Add a riscv,pmu device tree node with SBI PMU event mappings for the SiFive X280 hardware performance counters. This enables OpenSBI to expose the SBI PMU extension, allowing Linux perf to use the 4 programmable counters (mhpmcounter3-6) across 3 event classes: instruction commit, microarchitectural, and memory system events. Event encodings are derived from the SiFive Tenstorrent X280 MC Manual (21G3.04.00) Table 13, section 3.10.5. Assisted-by: Claude:claude-opus-4-6[1m] Signed-off-by: Michael Neuling Reviewed-by: Drew Fustini Signed-off-by: Drew Fustini --- .../riscv/boot/dts/tenstorrent/blackhole.dtsi | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/riscv/boot/dts/tenstorrent/blackhole.dtsi b/arch/riscv/boot/dts/tenstorrent/blackhole.dtsi index 6408810d8d80..5f709e45d9b2 100644 --- a/arch/riscv/boot/dts/tenstorrent/blackhole.dtsi +++ b/arch/riscv/boot/dts/tenstorrent/blackhole.dtsi @@ -77,6 +77,54 @@ cpu3_intc: interrupt-controller { }; }; + pmu { + compatible = "riscv,pmu"; + riscv,event-to-mhpmevent = + /* SBI_PMU_HW_CPU_CYCLES -> CPU cycles */ + <0x00001 0x00000000 0x0001>, + /* SBI_PMU_HW_INSTRUCTIONS -> Instructions executed */ + <0x00002 0x00000000 0x0004>, + /* SBI_PMU_HW_CACHE_REFERENCES -> I-cache/ITIM busy | D-cache/DTIM busy */ + <0x00003 0x00000000 0x1801>, + /* SBI_PMU_HW_CACHE_MISSES -> I-cache miss | D-cache miss */ + <0x00004 0x00000000 0x0302>, + /* SBI_PMU_HW_BRANCH_INSTRUCTIONS -> Conditional branch retired */ + <0x00005 0x00000000 0x4000>, + /* + * SBI_PMU_HW_BRANCH_MISSES -> + * Branch direction misprediction | Branch/jump target misprediction + */ + <0x00006 0x00000000 0x6001>, + /* L1D_READ_MISS -> Data cache miss or MMIO access */ + <0x10001 0x00000000 0x0202>, + /* L1D_WRITE_ACCESS -> Data cache write-back */ + <0x10002 0x00000000 0x0402>, + /* L1I_READ_MISS -> Instruction cache miss */ + <0x10009 0x00000000 0x0102>, + /* LL_READ_MISS -> UTLB miss */ + <0x10011 0x00000000 0x2002>, + /* DTLB_READ_MISS -> Data TLB miss */ + <0x10019 0x00000000 0x1002>, + /* ITLB_READ_MISS -> Instruction TLB miss */ + <0x10021 0x00000000 0x0802>; + riscv,event-to-mhpmcounters = + <0x00001 0x00001 0x01>, + <0x00002 0x00002 0x04>, + <0x00003 0x00006 0x78>, + <0x10001 0x10002 0x78>, + <0x10009 0x10009 0x78>, + <0x10011 0x10011 0x78>, + <0x10019 0x10019 0x78>, + <0x10021 0x10021 0x78>; + riscv,raw-event-to-mhpmcounters = + /* Class 0: Instruction Commit Events, bits 8-25 variant */ + <0x0 0x0 0xffffffff 0xfc0000ff 0x78>, + /* Class 1: Microarchitectural Events, bits 8-18 variant */ + <0x0 0x1 0xffffffff 0xfff800ff 0x78>, + /* Class 2: Memory System Events, bits 8-13 variant */ + <0x0 0x2 0xffffffff 0xffffc0ff 0x78>; + }; + soc { #address-cells = <2>; #size-cells = <2>; From 33583baeb1ba7d328e6a9775d889036900b74cdb Mon Sep 17 00:00:00 2001 From: Nicholas Piggin Date: Thu, 21 May 2026 10:06:33 -0700 Subject: [PATCH 422/665] dt-bindings: iommu: riscv: Add bindings for Tenstorrent RISC-V IOMMU Extend the binding to cover details specific to the Tenstorrent RISC-V IOMMU. In particular, a second register range is added which contains M-privileged registers, e.g., PMAs and PMPs. The RISC-V spec S-privileged registers remain in the first register range and are compatible with "riscv,iommu" so the Linux driver does not notice any difference, but the binding will be used by OpenSBI and potentially other M-mode software. Reviewed-by: Joel Stanley Acked-by: Conor Dooley Acked-by: Joerg Roedel Signed-off-by: Nicholas Piggin [fustini: fix dt_binding_check errors] Signed-off-by: Drew Fustini --- .../bindings/iommu/riscv,iommu.yaml | 59 ++++++++++++++++--- 1 file changed, 51 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml index d4838c3b3741..f83efb3ee000 100644 --- a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml @@ -32,22 +32,35 @@ properties: # should be specified along with 'reg' property providing MMIO location. compatible: oneOf: - - items: + - description: Platform (non-PCIe) IOMMU implementations + items: - enum: - qemu,riscv-iommu + - tenstorrent,riscv-iommu - const: riscv,iommu - - items: + - description: PCIe IOMMU implementations + items: - enum: - pci1efd,edf1 - const: riscv,pci-iommu reg: - maxItems: 1 - description: - For non-PCI devices this represents base address and size of for the - IOMMU memory mapped registers interface. - For PCI IOMMU hardware implementation this should represent an address - of the IOMMU, as defined in the PCI Bus Binding reference. + minItems: 1 + items: + - description: + For non-PCI devices, base address and size of the IOMMU memory + mapped registers interface. For PCI IOMMU hardware + implementation, an address of the IOMMU, as defined in the PCI + Bus Binding reference. + - description: + Region containing platform specific MMRs for machine-mode + configuration, such as PMA and PMP registers. + + reg-names: + minItems: 1 + items: + - const: base + - const: machine '#iommu-cells': const: 1 @@ -75,6 +88,26 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + enum: + - tenstorrent,riscv-iommu + then: + properties: + reg: + minItems: 2 + reg-names: + minItems: 2 + else: + properties: + reg: + maxItems: 1 + reg-names: + maxItems: 1 + examples: - |+ /* Example 1 (IOMMU device with wired interrupts) */ @@ -145,3 +178,13 @@ examples: }; }; }; + + - |+ + /* Example 5 (Tenstorrent IOMMU device with MSIs) */ + iommu5: iommu@d2020000 { + compatible = "tenstorrent,riscv-iommu", "riscv,iommu"; + reg = <0xd2020000 0x10000>, <0xaa000000 0x10000>; + reg-names = "base", "machine"; + msi-parent = <&imsics_smode>; + #iommu-cells = <1>; + }; From 3a6ffc1b4fcecd021361393d7294badb0d89e5b0 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Mon, 18 May 2026 23:04:49 +0100 Subject: [PATCH 423/665] arm64: dts: allwinner: sun50i-a64: Enable DT overlays Enable DT overlays on some of the Pine64 devices to enable use of addon accessories such as WiFi or audio modules. Signed-off-by: Peter Robinson Link: https://patch.msgid.link/20260518220455.156874-1-pbrobinson@gmail.com Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/Makefile | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index d116864b6c2b..53e6b701e7d3 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -1,4 +1,10 @@ # SPDX-License-Identifier: GPL-2.0 +# Enables support for device-tree overlays for named devices +DTC_FLAGS_sun50i-a64-pine64-lts := -@ +DTC_FLAGS_sun50i-a64-pine64 := -@ +DTC_FLAGS_sun50i-a64-pine64-plus := -@ +DTC_FLAGS_sun50i-a64-sopine-baseboard := -@ + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-amarula-relic.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-bananapi-m64.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-nanopi-a64.dtb From d0298724f901d45c76f1f2193225706200f565e4 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Sat, 23 May 2026 15:02:33 +0100 Subject: [PATCH 424/665] arm64: dts: exynos: Add EL2 virtual timer interrupt A bunch of Samsung SoCs are missing the EL2 virtual timer interrupt despite using ARMv8.1+ CPUs. Add the missing interrupt, except for those broken designs where the interrupt is documented as not being wired. Acked-by: Jesper Nilsson Signed-off-by: Marc Zyngier Link: https://patch.msgid.link/20260523140242.586031-9-maz@kernel.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/axis/artpec9.dtsi | 3 ++- arch/arm64/boot/dts/exynos/exynos2200.dtsi | 3 ++- arch/arm64/boot/dts/exynos/exynos990.dtsi | 3 ++- arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 3 ++- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 3 ++- 5 files changed, 10 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/axis/artpec9.dtsi b/arch/arm64/boot/dts/exynos/axis/artpec9.dtsi index f8ed43c6e825..cd46aaf05628 100644 --- a/arch/arm64/boot/dts/exynos/axis/artpec9.dtsi +++ b/arch/arm64/boot/dts/exynos/axis/artpec9.dtsi @@ -272,6 +272,7 @@ timer { interrupts = , , , - ; + , + ; }; }; diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/dts/exynos/exynos2200.dtsi index 6487ccb58ae7..59662f9bdb98 100644 --- a/arch/arm64/boot/dts/exynos/exynos2200.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi @@ -1911,7 +1911,8 @@ timer { interrupts = , , , - ; + , + ; /* * Non-updatable, broken stock Samsung bootloader does not * configure CNTFRQ_EL0 diff --git a/arch/arm64/boot/dts/exynos/exynos990.dtsi b/arch/arm64/boot/dts/exynos/exynos990.dtsi index f8e2a31b4b75..2e6fb24a3c92 100644 --- a/arch/arm64/boot/dts/exynos/exynos990.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos990.dtsi @@ -405,7 +405,8 @@ timer { interrupts = , , , - ; + , + ; /* * Non-updatable, broken stock Samsung bootloader does not diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi index 66628cb32776..2c34a2b30ad0 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi @@ -148,7 +148,8 @@ timer { interrupts = , , , - ; + , + ; }; fixed-rate-clocks { diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index d085f9fb0f62..86933f22647b 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1856,7 +1856,8 @@ timer { , , , - ; + , + ; }; }; From 2f60e351633044dee88b63fb1600e284d2476e9c Mon Sep 17 00:00:00 2001 From: MoeLeak Date: Fri, 8 May 2026 19:44:13 +0800 Subject: [PATCH 425/665] riscv: dts: thead: Add TH1520 I2C1 controller Describe the TH1520 I2C1 controller so boards can enable devices attached to that bus. The controller is disabled by default because pinmuxing and connected peripherals are board-specific. Signed-off-by: MoeLeak Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index 5e91dc1d2b9b..94932c51b7e3 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -411,6 +411,17 @@ uart3: serial@ffe7f04000 { status = "disabled"; }; + i2c1: i2c@ffe7f24000 { + compatible = "thead,th1520-i2c", "snps,designware-i2c"; + reg = <0xff 0xe7f24000 0x0 0x4000>; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk CLK_I2C1>, <&clk CLK_PERI_APB_PCLK>; + clock-names = "ref", "pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gpio@ffe7f34000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xe7f34000 0x0 0x1000>; From a20241c08385c875c4d0deb6c8ffc15f13f5b388 Mon Sep 17 00:00:00 2001 From: MoeLeak Date: Fri, 8 May 2026 19:44:14 +0800 Subject: [PATCH 426/665] riscv: dts: thead: Enable WiFi on Lichee Pi 4A The Lichee Pi 4A has an RTL8723DS WiFi module connected to the TH1520 SDIO1 controller. The module reset line is driven through a PCA9557 GPIO expander on the I2C1 bus. Enable I2C1 for the GPIO expander and configure SDIO1 as a non-removable 4-bit SDIO bus using an mmc-pwrseq-simple reset sequence so the WiFi device can be powered and enumerated. Signed-off-by: MoeLeak Signed-off-by: Drew Fustini --- .../boot/dts/thead/th1520-lichee-pi-4a.dts | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts index 7cb7d28683bc..af6f25ebbf60 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts @@ -4,6 +4,7 @@ */ #include "th1520-lichee-module-4a.dtsi" +#include / { model = "Sipeed Lichee Pi 4A"; @@ -40,6 +41,12 @@ hdmi_con_in: endpoint { }; }; + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&ioexp2 4 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <200>; + }; + thermal-zones { cpu-thermal { polling-delay = <1000>; @@ -96,6 +103,20 @@ fan: pwm-fan { }; +&padctrl1_apsys { + i2c1_pins: i2c1-0 { + i2c-pins { + pins = "I2C1_SCL", "I2C1_SDA"; + function = "i2c"; + bias-pull-up = <2100>; + drive-strength = <7>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; +}; + &padctrl0_apsys { fan_pins: fan-0 { pwm1-pins { @@ -132,6 +153,32 @@ rx-pins { }; }; +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; + + ioexp2: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&sdio1 { + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + max-frequency = <198000000>; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + status = "okay"; +}; + &dpu { status = "okay"; }; From 3a5791956edbfa84d7256224167941931cbc46e7 Mon Sep 17 00:00:00 2001 From: Thomas Gerner Date: Thu, 14 May 2026 20:32:01 +0200 Subject: [PATCH 427/665] riscv: dts: thead: Enable wifi on the BeagleV-Ahead The BeagleV-Ahead board uses an AP6203BM WiFi chip from AMPAK Technology Inc. connected to SDIO1. The chip is compatible to the broadcom wireless driver. The AP6203BM is a dual-band 2.4GHz/5GHz Wi-Fi 4 (802.11a/b/g/n) and Bluetooth 5.4 module. Bluetooth is not enabled by this patch. Signed-off-by: Thomas Gerner Signed-off-by: Drew Fustini --- .../boot/dts/thead/th1520-beaglev-ahead.dts | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts index 91f3f9b987bc..e16484a47653 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -86,6 +86,11 @@ hdmi_con_in: endpoint { }; }; }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>; /* WL-REG-ON */ + }; }; &osc { @@ -239,6 +244,28 @@ rx-pins { slew-rate = <0>; }; }; + + wifi_pins: wifi-0 { + host-wake-pins { + pins = "GPIO2_25"; + function = "gpio"; + bias-disable; + drive-strength = <1>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + + reg-on-pins { + pins = "GPIO2_31"; + function = "gpio"; + bias-disable; + drive-strength = <3>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; }; &sdio0 { @@ -247,6 +274,27 @@ &sdio0 { status = "okay"; }; +&sdio1 { + bus-width = <4>; + max-frequency = <198000000>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_pins>; + #address-cells = <1>; + #size-cells = <0>; + non-removable; + keep-power-in-suspend; + mmc-pwrseq = <&wifi_pwrseq>; + status = "okay"; + + wifi@1 { + compatible = "cypress,cyw43012-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio2>; + interrupts = <25 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "host-wake"; + }; +}; + &dpu { status = "okay"; }; From 9897c586b09f79ebcf2e67a888743c046b20d254 Mon Sep 17 00:00:00 2001 From: Aleksander Jan Bajkowski Date: Sat, 23 May 2026 12:18:55 +0200 Subject: [PATCH 428/665] arm64: dts: mediatek: add LED and key support on Xiaomi AX3000T This patch adds support for keys and LEDs on the Xiaomi AX3000T. Signed-off-by: Aleksander Jan Bajkowski Signed-off-by: AngeloGioacchino Del Regno --- .../dts/mediatek/mt7981b-xiaomi-ax3000t.dts | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-xiaomi-ax3000t.dts b/arch/arm64/boot/dts/mediatek/mt7981b-xiaomi-ax3000t.dts index a314c3e05e50..db399cb3ead7 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b-xiaomi-ax3000t.dts +++ b/arch/arm64/boot/dts/mediatek/mt7981b-xiaomi-ax3000t.dts @@ -1,6 +1,9 @@ // SPDX-License-Identifier: GPL-2.0-only OR MIT /dts-v1/; +#include +#include +#include #include "mt7981b.dtsi" @@ -12,4 +15,37 @@ memory@40000000 { reg = <0 0x40000000 0 0x10000000>; device_type = "memory"; }; + + keys { + compatible = "gpio-keys"; + + key-mesh { + label = "MESH"; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + }; + + key-reset { + label = "RESET"; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + + led-1 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + }; }; From 96b33938cf783c790036e35860b206cf029f2e2a Mon Sep 17 00:00:00 2001 From: Durai Manickam KR Date: Mon, 25 May 2026 14:54:04 +0530 Subject: [PATCH 429/665] ARM: dts: microchip: add I3C controller Add I3C controller for sama7d65 SoC. Signed-off-by: Durai Manickam KR Signed-off-by: Manikandan Muralidharan Link: https://lore.kernel.org/r/20260525092405.1514213-5-manikandan.m@microchip.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index 67253bbc08df..ec200848c153 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -1055,5 +1055,13 @@ gic: interrupt-controller@e8c11000 { #address-cells = <0>; interrupt-controller; }; + + i3c: i3c@e9000000 { + compatible = "microchip,sama7d65-i3c-hci"; + reg = <0xe9000000 0x300>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 105>, <&pmc PMC_TYPE_GCK 105>; + status = "disabled"; + }; }; }; From 8071815790141d3f05e32b972a6c79fdbbb88cfa Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Fri, 15 May 2026 13:59:09 +0200 Subject: [PATCH 430/665] arm64: dts: microchip: lan969x: add OTP node Add the required OTP on LAN969x. Signed-off-by: Robert Marko Reviewed-by: Claudiu Beznea Link: https://lore.kernel.org/r/20260515115954.701155-3-robimarko@gmail.com Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/microchip/lan9691.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/lan9691.dtsi b/arch/arm64/boot/dts/microchip/lan9691.dtsi index 235e56bebbdb..ed997d87dd09 100644 --- a/arch/arm64/boot/dts/microchip/lan9691.dtsi +++ b/arch/arm64/boot/dts/microchip/lan9691.dtsi @@ -100,6 +100,11 @@ usb: usb@300000 { status = "disabled"; }; + otp: otp@e0021000 { + compatible = "microchip,lan9691-otpc"; + reg = <0xe0021000 0x1000>; + }; + flx0: flexcom@e0040000 { compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe0040000 0x100>; From 844c29197366e25ad361cf725d80acb4f10e3e19 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Thu, 21 May 2026 00:24:41 +0000 Subject: [PATCH 431/665] riscv: dts: spacemit: k3: Add pwm support Populate all pwm device tree nodes for SpacemiT K3 SoC, also documents the pinctrl info which would easily help to enable them in future. Link: https://patch.msgid.link/20260521-04-k3-pwm-dts-v4-1-04d4de0f2fc8@kernel.org Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 590 +++++++++++++++++++ arch/riscv/boot/dts/spacemit/k3.dtsi | 220 +++++++ 2 files changed, 810 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi index 23899d3f308a..252c64af76fe 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi @@ -56,6 +56,596 @@ i2c8-pins { }; }; + /omit-if-no-ref/ + pwm0_0_cfg: pwm0-0-cfg { + pwm0-0-pins { + pinmux = ; /* pwm0 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm0_1_cfg: pwm0-1-cfg { + pwm0-1-pins { + pinmux = ; /* pwm0 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm1_0_cfg: pwm1-0-cfg { + pwm1-0-pins { + pinmux = ; /* pwm1 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm1_1_cfg: pwm1-1-cfg { + pwm1-1-pins { + pinmux = ; /* pwm1 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm1_2_cfg: pwm1-2-cfg { + pwm1-2-pins { + pinmux = ; /* pwm1 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm2_0_cfg: pwm2-0-cfg { + pwm2-0-pins { + pinmux = ; /* pwm2 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm2_1_cfg: pwm2-1-cfg { + pwm2-1-pins { + pinmux = ; /* pwm2 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm2_2_cfg: pwm2-2-cfg { + pwm2-2-pins { + pinmux = ; /* pwm2 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm2_3_cfg: pwm2-3-cfg { + pwm2-3-pins { + pinmux = ; /* pwm2 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm3_0_cfg: pwm3-0-cfg { + pwm3-0-pins { + pinmux = ; /* pwm3 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm3_1_cfg: pwm3-1-cfg { + pwm3-1-pins { + pinmux = ; /* pwm3 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm3_2_cfg: pwm3-2-cfg { + pwm3-2-pins { + pinmux = ; /* pwm3 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm3_3_cfg: pwm3-3-cfg { + pwm3-3-pins { + pinmux = ; /* pwm3 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm4_0_cfg: pwm4-0-cfg { + pwm4-0-pins { + pinmux = ; /* pwm4 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm4_1_cfg: pwm4-1-cfg { + pwm4-1-pins { + pinmux = ; /* pwm4 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm4_2_cfg: pwm4-2-cfg { + pwm4-2-pins { + pinmux = ; /* pwm4 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm5_0_cfg: pwm5-0-cfg { + pwm5-0-pins { + pinmux = ; /* pwm5 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm5_1_cfg: pwm5-1-cfg { + pwm5-1-pins { + pinmux = ; /* pwm5 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm5_2_cfg: pwm5-2-cfg { + pwm5-2-pins { + pinmux = ; /* pwm5 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm6_0_cfg: pwm6-0-cfg { + pwm6-0-pins { + pinmux = ; /* pwm6 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm6_1_cfg: pwm6-1-cfg { + pwm6-1-pins { + pinmux = ; /* pwm6 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm6_2_cfg: pwm6-2-cfg { + pwm6-2-pins { + pinmux = ; /* pwm6 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm7_0_cfg: pwm7-0-cfg { + pwm7-0-pins { + pinmux = ; /* pwm7 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm7_1_cfg: pwm7-1-cfg { + pwm7-1-pins { + pinmux = ; /* pwm7 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm7_2_cfg: pwm7-2-cfg { + pwm7-2-pins { + pinmux = ; /* pwm7 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm8_0_cfg: pwm8-0-cfg { + pwm8-0-pins { + pinmux = ; /* pwm8 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm8_1_cfg: pwm8-1-cfg { + pwm8-1-pins { + pinmux = ; /* pwm8 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm8_2_cfg: pwm8-2-cfg { + pwm8-2-pins { + pinmux = ; /* pwm8 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm9_0_cfg: pwm9-0-cfg { + pwm9-0-pins { + pinmux = ; /* pwm9 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm9_1_cfg: pwm9-1-cfg { + pwm9-1-pins { + pinmux = ; /* pwm9 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm9_2_cfg: pwm9-2-cfg { + pwm9-2-pins { + pinmux = ; /* pwm9 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm10_0_cfg: pwm10-0-cfg { + pwm10-0-pins { + pinmux = ; /* pwm10 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm10_1_cfg: pwm10-1-cfg { + pwm10-1-pins { + pinmux = ; /* pwm10 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm10_2_cfg: pwm10-2-cfg { + pwm10-2-pins { + pinmux = ; /* pwm10 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm11_0_cfg: pwm11-0-cfg { + pwm11-0-pins { + pinmux = ; /* pwm11 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm11_1_cfg: pwm11-1-cfg { + pwm11-1-pins { + pinmux = ; /* pwm11 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm12_0_cfg: pwm12-0-cfg { + pwm12-0-pins { + pinmux = ; /* pwm12 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm12_1_cfg: pwm12-1-cfg { + pwm12-1-pins { + pinmux = ; /* pwm12 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm13_0_cfg: pwm13-0-cfg { + pwm13-0-pins { + pinmux = ; /* pwm13 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm13_1_cfg: pwm13-1-cfg { + pwm13-1-pins { + pinmux = ; /* pwm13 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm13_2_cfg: pwm13-2-cfg { + pwm13-2-pins { + pinmux = ; /* pwm13 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm14_0_cfg: pwm14-0-cfg { + pwm14-0-pins { + pinmux = ; /* pwm14 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm14_1_cfg: pwm14-1-cfg { + pwm14-1-pins { + pinmux = ; /* pwm14 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm14_2_cfg: pwm14-2-cfg { + pwm14-2-pins { + pinmux = ; /* pwm14 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm15_0_cfg: pwm15-0-cfg { + pwm15-0-pins { + pinmux = ; /* pwm15 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm15_1_cfg: pwm15-1-cfg { + pwm15-1-pins { + pinmux = ; /* pwm15 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm15_2_cfg: pwm15-2-cfg { + pwm15-2-pins { + pinmux = ; /* pwm15 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm16_0_cfg: pwm16-0-cfg { + pwm16-0-pins { + pinmux = ; /* pwm16 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm16_1_cfg: pwm16-1-cfg { + pwm16-1-pins { + pinmux = ; /* pwm16 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm16_2_cfg: pwm16-2-cfg { + pwm16-2-pins { + pinmux = ; /* pwm16 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm17_0_cfg: pwm17-0-cfg { + pwm17-0-pins { + pinmux = ; /* pwm17 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm17_1_cfg: pwm17-1-cfg { + pwm17-1-pins { + pinmux = ; /* pwm17 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm17_2_cfg: pwm17-2-cfg { + pwm17-2-pins { + pinmux = ; /* pwm17 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm18_0_cfg: pwm18-0-cfg { + pwm18-0-pins { + pinmux = ; /* pwm18 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm18_1_cfg: pwm18-1-cfg { + pwm18-1-pins { + pinmux = ; /* pwm18 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm18_2_cfg: pwm18-2-cfg { + pwm18-2-pins { + pinmux = ; /* pwm18 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm19_0_cfg: pwm19-0-cfg { + pwm19-0-pins { + pinmux = ; /* pwm19 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm19_1_cfg: pwm19-1-cfg { + pwm19-1-pins { + pinmux = ; /* pwm19 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm19_2_cfg: pwm19-2-cfg { + pwm19-2-pins { + pinmux = ; /* pwm19 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + /omit-if-no-ref/ uart0_0_cfg: uart0-0-cfg { uart0-0-pins { diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index d4be8de8fc6c..fa459bc95688 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -839,6 +839,226 @@ i2c8: i2c@d401d800 { status = "disabled"; }; + pwm0: pwm@d401a000 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd401a000 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM0>, + <&syscon_apbc CLK_APBC_PWM0_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM0>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1: pwm@d401a400 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd401a400 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM1>, + <&syscon_apbc CLK_APBC_PWM1_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM1>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2: pwm@d401a800 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd401a800 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM2>, + <&syscon_apbc CLK_APBC_PWM2_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM2>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3: pwm@d401ac00 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd401ac00 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM3>, + <&syscon_apbc CLK_APBC_PWM3_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM3>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm4: pwm@d401b000 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd401b000 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM4>, + <&syscon_apbc CLK_APBC_PWM4_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM4>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm5: pwm@d401b400 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd401b400 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM5>, + <&syscon_apbc CLK_APBC_PWM5_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM5>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm6: pwm@d401b800 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd401b800 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM6>, + <&syscon_apbc CLK_APBC_PWM6_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM6>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm7: pwm@d401bc00 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd401bc00 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM7>, + <&syscon_apbc CLK_APBC_PWM7_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM7>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm8: pwm@d4020000 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4020000 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM8>, + <&syscon_apbc CLK_APBC_PWM8_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM8>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm9: pwm@d4020400 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4020400 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM9>, + <&syscon_apbc CLK_APBC_PWM9_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM9>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm10: pwm@d4020800 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4020800 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM10>, + <&syscon_apbc CLK_APBC_PWM10_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm11: pwm@d4020c00 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4020c00 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM11>, + <&syscon_apbc CLK_APBC_PWM11_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM11>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm12: pwm@d4021000 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4021000 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM12>, + <&syscon_apbc CLK_APBC_PWM12_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM12>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm13: pwm@d4021400 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4021400 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM13>, + <&syscon_apbc CLK_APBC_PWM13_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM13>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm14: pwm@d4021800 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4021800 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM14>, + <&syscon_apbc CLK_APBC_PWM14_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM14>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm15: pwm@d4021c00 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4021c00 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM15>, + <&syscon_apbc CLK_APBC_PWM15_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM15>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm16: pwm@d4022000 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4022000 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM16>, + <&syscon_apbc CLK_APBC_PWM16_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM16>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm17: pwm@d4022400 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4022400 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM17>, + <&syscon_apbc CLK_APBC_PWM17_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM17>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm18: pwm@d4022800 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4022800 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM18>, + <&syscon_apbc CLK_APBC_PWM18_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM18>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm19: pwm@d4022c00 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4022c00 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM19>, + <&syscon_apbc CLK_APBC_PWM19_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM19>; + #pwm-cells = <3>; + status = "disabled"; + }; + pinctrl: pinctrl@d401e000 { compatible = "spacemit,k3-pinctrl"; reg = <0x0 0xd401e000 0x0 0x1000>; From 2bdc0ea4e7304f6aa7e87089609fd902d9de7a2d Mon Sep 17 00:00:00 2001 From: Nora Schiffer Date: Tue, 7 Apr 2026 13:42:37 +0200 Subject: [PATCH 432/665] arm64: dts: ti: k3-j722s-main: use J722S compatibles for WIZ, gmii-sel and CPSW3G Update WIZ, gmii-sel and CPSW3G to use the J722S-specific compatible strings, enabling SGMII support. The fallback compatibles preserve compatibility of the updated Device Trees with older kernels. Signed-off-by: Nora Schiffer Link: https://patch.msgid.link/391f17ba7b0e9dcaa1fc8210114dfda7eb3c0467.1775559102.git.nora.schiffer@ew.tq-group.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi index d1dbf1e24fbf..5a5b9a1bfd9e 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -18,7 +18,7 @@ serdes_refclk: clk-0 { &cbass_main { serdes_wiz0: phy@f000000 { - compatible = "ti,am64-wiz-10g"; + compatible = "ti,j722s-wiz-10g", "ti,am64-wiz-10g"; ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; #address-cells = <1>; #size-cells = <1>; @@ -56,7 +56,7 @@ serdes0: serdes@f000000 { }; serdes_wiz1: phy@f010000 { - compatible = "ti,am64-wiz-10g"; + compatible = "ti,j722s-wiz-10g", "ti,am64-wiz-10g"; ranges = <0x0f010000 0x0 0x0f010000 0x00010000>; #address-cells = <1>; #size-cells = <1>; @@ -444,6 +444,14 @@ serdes_ln_ctrl: mux-controller@4080 { }; }; +&cpsw3g { + compatible = "ti,j722s-cpsw-nuss", "ti,am642-cpsw-nuss"; +}; + +&phy_gmii_sel { + compatible = "ti,j722s-phy-gmii-sel", "ti,am654-phy-gmii-sel"; +}; + &oc_sram { reg = <0x00 0x70000000 0x00 0x40000>; ranges = <0x00 0x00 0x70000000 0x40000>; From 85e4c5733cd7efa39f10d7200095c016ce4a2815 Mon Sep 17 00:00:00 2001 From: Trevor Gamblin Date: Wed, 20 May 2026 15:06:23 +0200 Subject: [PATCH 433/665] riscv: dts: spacemit: k1-musepi-pro: add SD card support with UHS modes Update the Muse Pi Pro devicetree with SD card support to match what was done for the OrangePi RV2 in [1]. More precisely: - Enable sdhci0 controller with 4-bit bus width - Configure card detect GPIO with internal pull-up support - Connect vmmc-supply to buck4 for 3.3V card power - Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching - Add dual pinctrl states for voltage-dependent pin configuration - Support UHS-I SDR25, SDR50, and SDR104 modes - Add stable MMC device aliases (mmc0 = eMMC, mmc1 = SD card) [1] https://lore.kernel.org/linux-riscv/20260316-orangepi-sd-card-uhs-v3-0-aefd3b7832df@gmail.com/T/# Tested-by: Andre Heider Signed-off-by: Trevor Gamblin Signed-off-by: Iker Pedrosa Signed-off-by: Andre Heider Link: https://lore.kernel.org/linux-riscv/20260316-orangepi-sd-card-uhs-v3-0-aefd3b7832df@gmail.com/T/# Link: https://patch.msgid.link/20260520130624.1763487-1-a.heider@gmail.com Signed-off-by: Yixun Lan --- .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 22 ++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts index 4aef287353ca..0d809e4ad3b1 100644 --- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts @@ -19,6 +19,8 @@ aliases { serial0 = &uart0; i2c2 = &i2c2; i2c8 = &i2c8; + mmc0 = &emmc; + mmc1 = &sdhci0; }; chosen { @@ -218,7 +220,7 @@ buck6 { regulator-always-on; }; - aldo1 { + aldo1: aldo1 { regulator-min-microvolt = <500000>; regulator-max-microvolt = <3400000>; regulator-boot-on; @@ -384,3 +386,21 @@ hub_3_0: hub@2 { reset-gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_LOW>; /* HUB_RST */ }; }; + +&sdhci0 { + pinctrl-names = "default", "uhs"; + pinctrl-0 = <&mmc1_cfg>; + pinctrl-1 = <&mmc1_uhs_cfg>; + bus-width = <4>; + cd-gpios = <&gpio K1_GPIO(80) (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; + no-mmc; + no-sdio; + disable-wp; + cap-sd-highspeed; + vmmc-supply = <&buck4_3v3>; + vqmmc-supply = <&aldo1>; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; From 7f2eeae12690aaee6195f85ed129a29c17f156d1 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 19 May 2026 09:47:06 +0100 Subject: [PATCH 434/665] arm64: tegra: Fix address of Tegra264 main GPIO controller The 64-bit address of the main GPIO controller on Tegra264 is 0x810c300000. The main GPIO controller was incorrectly added under the bus@0 node instead of the bus@8100000000 node breaking the boot on Tegra264. Fix this by moving to main GPIO controller node under bus@8100000000. Fixes: c70e6bc11d20 ("arm64: tegra: Add Tegra264 GPIO controllers") Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra264.dtsi | 88 ++++++++++++------------ 1 file changed, 44 insertions(+), 44 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi index 06d8357bdf52..2d8e7e37830f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -3277,50 +3277,6 @@ rtc: rtc@c2c0000 { status = "disabled"; }; - gpio_main: gpio@c300000 { - compatible = "nvidia,tegra264-gpio"; - reg = <0x00 0x0c300000 0x0 0x4000>, - <0x00 0x0c310000 0x0 0x4000>; - reg-names = "security", "gpio"; - wakeup-parent = <&pmc>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - serial@c4e0000 { compatible = "nvidia,tegra264-utc"; reg = <0x0 0x0c4e0000 0x0 0x8000>, @@ -3586,6 +3542,50 @@ pci@c000000 { status = "disabled"; }; + gpio_main: gpio@c300000 { + compatible = "nvidia,tegra264-gpio"; + reg = <0x00 0x0c300000 0x0 0x4000>, + <0x00 0x0c310000 0x0 0x4000>; + reg-names = "security", "gpio"; + wakeup-parent = <&pmc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + i2c14: i2c@c410000 { compatible = "nvidia,tegra264-i2c"; reg = <0x00 0x0c410000 0x0 0x10000>; From 36532a9a22589a375556e16b103ae8275a4affc0 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 19 May 2026 09:47:07 +0100 Subject: [PATCH 435/665] arm64: tegra: Enable PCIe for Jetson AGX Thor Enable the PCIe controllers on the Jetson AGX Thor Developer Kit that are used for ethernet and NVMe. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- .../dts/nvidia/tegra264-p4071-0000+p3834-0008.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834-0008.dts b/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834-0008.dts index df6555b6d0e0..3bd4c4cf2871 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834-0008.dts +++ b/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834-0008.dts @@ -8,4 +8,16 @@ / { model = "NVIDIA Jetson AGX Thor Developer Kit"; compatible = "nvidia,p4071-0000+p3834-0008", "nvidia,p3834-0008", "nvidia,tegra264"; + + bus@a800000000 { + /* PCIe C2 to enable Ethernet */ + pci@8420000 { + status = "okay"; + }; + + /* PCIe C5 to enable NVME */ + pci@8480000 { + status = "okay"; + }; + }; }; From 10499d3e358364604eb9d7dd6adbc76b3b2078a6 Mon Sep 17 00:00:00 2001 From: Neil Cheng Date: Tue, 19 May 2026 10:38:37 +0800 Subject: [PATCH 436/665] dt-bindings: arm: aspeed: Add Meta Rainiera6 board Document the new compatibles used on Meta Rainiera6. Acked-by: Conor Dooley Signed-off-by: Neil Cheng Signed-off-by: Andrew Jeffery --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index b553e3415ce9..9ba195b8f22d 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -95,6 +95,7 @@ properties: - facebook,greatlakes-bmc - facebook,harma-bmc - facebook,minerva-cmc + - facebook,rainiera6-bmc - facebook,sanmiguel-bmc - facebook,santabarbara-bmc - facebook,yosemite4-bmc From 12b7b2bff1d18b72fb965cd5e0a0f8c7787a21b4 Mon Sep 17 00:00:00 2001 From: Neil Cheng Date: Tue, 19 May 2026 10:38:38 +0800 Subject: [PATCH 437/665] ARM: dts: aspeed: rainiera6: Add Meta Rainiera6 BMC Add device tree for the Meta (Facebook) Rainiera6 compute node, based on AST2600 BMC. Signed-off-by: Neil Cheng Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/Makefile | 1 + .../aspeed/aspeed-bmc-facebook-rainiera6.dts | 1012 +++++++++++++++++ 2 files changed, 1013 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-rainiera6.dts diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile index 7d70f08e436c..6b68671f9379 100644 --- a/arch/arm/boot/dts/aspeed/Makefile +++ b/arch/arm/boot/dts/aspeed/Makefile @@ -34,6 +34,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-facebook-harma.dtb \ aspeed-bmc-facebook-minerva.dtb \ aspeed-bmc-facebook-minipack.dtb \ + aspeed-bmc-facebook-rainiera6.dtb \ aspeed-bmc-facebook-sanmiguel.dtb \ aspeed-bmc-facebook-santabarbara.dtb \ aspeed-bmc-facebook-tiogapass.dtb \ diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-rainiera6.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-rainiera6.dts new file mode 100644 index 000000000000..b29e08cea254 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-rainiera6.dts @@ -0,0 +1,1012 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2026 Facebook Inc. + +/dts-v1/; +#include "aspeed-g6.dtsi" +#include +#include + +/ { + model = "Facebook Rainier BMC"; + compatible = "facebook,rainiera6-bmc", "aspeed,ast2600"; + + aliases { + i2c16 = &i2c5mux0ch0; + i2c17 = &i2c5mux0ch1; + i2c18 = &i2c5mux1ch0; + i2c19 = &i2c5mux1ch1; + i2c20 = &i2c6mux0ch0; + i2c21 = &i2c6mux0ch1; + i2c22 = &i2c6mux0ch2; + i2c23 = &i2c6mux0ch3; + i2c24 = &i2c8mux0ch0; + i2c25 = &i2c8mux0ch1; + i2c26 = &i2c8mux0ch2; + i2c27 = &i2c8mux0ch3; + i2c28 = &i2c26mux0ch0; + i2c29 = &i2c26mux0ch1; + i2c30 = &i2c26mux0ch2; + i2c31 = &i2c26mux0ch3; + serial0 = &uart1; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + }; + + chosen { + stdout-path = "serial4:57600n8"; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, + <&adc1 2>; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "bmc_heartbeat_amber"; + gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + label = "fp_id_amber"; + default-state = "off"; + gpios = <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>; + }; + + led-2 { + label = "power_fault_amber"; + default-state = "off"; + gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_HIGH>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + p1v8_adc_vref: regulator-p1v8-aux { + compatible = "regulator-fixed"; + regulator-name = "p1v8_adc_vref"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + spi_gpio: spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + sck-gpios = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + status = "okay"; + + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + spi-max-frequency = <33000000>; + reg = <0>; + }; + }; +}; + +&adc0 { + vref-supply = <&p1v8_adc_vref>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default &pinctrl_adc7_default>; + status = "okay"; +}; + +&adc1 { + aspeed,int-vref-microvolt = <2500000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc10_default>; + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&fmc { + status = "okay"; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-128.dtsi" + }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt-bmc"; + spi-max-frequency = <50000000>; + }; +}; + +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "BATTERY_DETECT","","BMC_I2C1_FPGA_ALERT_L","BMC_READY_R", + "IOEXP_INT_3V3_L_R1","FM_ID_LED","","", + /*C0-C7*/ "BMC_GPIOC0","","","","PMBUS_REQ_N","PSU_FW_UPDATE_REQ_N","", + "BMC_I2C_SSIF_ALERT_L", + /*D0-D7*/ "","","","","BMC_GPIOD4","","","", + /*E0-E7*/ "BMC_GPIOE0","BMC_GPIOE1","","","","","","", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "FM_BMC_MUX1_SEL_R","","","","","","FM_DEBUG_PORT_PRSNT_R1_N", + "FM_BMC_DBP_PRESENT_R_N", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","FLASH_WP_STATUS_R1","BMC_JTAG_MUX_SEL","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "PCIE_EP_RST_EN","BMC_FRU_WP","SCM_HPM_STBY_RST_N", + "SCM_HPM_STBY_R_EN","STBY_POWER_PG_3V3_R","TH500_SHDN_OK_L","","", + /*N0-N7*/ "LED_POSTCODE_0","LED_POSTCODE_1","LED_POSTCODE_2", + "LED_POSTCODE_3","LED_POSTCODE_4","LED_POSTCODE_5", + "LED_POSTCODE_6","LED_POSTCODE_7", + /*O0-O7*/ "RUN_POWER_PG","PWR_BRAKE_L","CHASSIS_AC_LOSS_L", + "BSM_PRSNT_R_N","PSU_SMB_ALERT_L","FM_TPM_PRSNT_0_N", + "PSU_FW_UPDATING_N","DEBUG_CARD_BYPASS", + /*P0-P7*/ "PWR_BTN_BMC_R1_N","IPEX_CABLE_PRSNT_L","ID_RST_BTN_BMC_R_N", + "RST_BMC_RSTBTN_OUT_R_N","BMC_PWR_LED","RUN_POWER_EN", + "SHDN_FORCE_L","BMC_HEARTBEAT_N", + /*Q0-Q7*/ "IRQ_PCH_TPM_SPI_LV3_N","USB_OC0_REAR_R_N","UART_MUX_SEL", + "I2C_MUX_RESET_L","RSVD_NV_PLT_DETECT","SPI_TPM_INT_L", + "CPU_JTAG_MUX_SELECT","THERM_BB_OVERT_L", + /*R0-R7*/ "THERM_BB_WARN_L","SPI_BMC_FPGA_INT_L","CPU_BOOT_DONE", + "PMBUS_GNT_L","CHASSIS_PWR_BRK_L","PCIE_WAKE_L","PDB_THERM_OVERT_L", + "SHDN_REQ_L", + /*S0-S7*/ "","","SYS_BMC_PWRBTN_R_N","FM_TPM_PRSNT_1_N", + "FM_BMC_DEBUG_SW_N","UID_LED_N","SYS_FAULT_LED_N", + "RUN_POWER_FAULT_L", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "L2_RST_REQ_OUT_L","L0L1_RST_REQ_OUT_L","BMC_ID_BEEP_SEL_R1", + "BMC_I2C0_FPGA_ALERT_L","SMB_BMC_TMP_ALERT","PWR_LED_N", + "SYS_RST_OUT_L","IRQ_TPM_SPI_N", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","FM_DBP_CPU_PREQ_GF_N_R1","","","","","","", + /*Y0-Y7*/ "","RST_BMC_SELF_HW_R1","FM_FLASH_LATCH_N_R1","", + "BMC_GPIOY4_R","BMC_GPIOY5_R","","", + /*Z0-Z7*/ "","","","","","","BMC_GPIOZ6_R","BMC_GPIOZ7_R"; +}; + +&gpio1 { + gpio-line-names = + /*18A0-18A7*/ "","","","","","","","", + /*18B0-18B7*/ "","","","","FM_BOARD_BMC_REV_ID0","FM_BOARD_BMC_REV_ID1", + "FM_BOARD_BMC_REV_ID2","", + /*18C0-18C7*/ "","","SPI_BMC_BIOS_ROM_IRQ0_R_N","","","","","", + /*18D0-18D7*/ "","","","","","","","", + /*18E0-18E3*/ "FM_BMC_PROT_LS_EN","AC_PWR_BMC_BTN_R_N","",""; +}; + +/* Rainiera6 SoC SSIF */ +&i2c1 { + status = "okay"; + + ssif_bmc: ssif-bmc@10 { + compatible = "ssif-bmc"; + reg = <0x10>; + status = "okay"; + }; +}; + +/* MCIO 2A I2C */ +&i2c2 { + status = "okay"; +}; + +&i2c4 { + multi-master; + mctp-controller; + clock-frequency = <400000>; + status = "okay"; + + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + /* OCP NIC TEMP */ + temperature-sensor@1f { + compatible = "ti,tmp421"; + reg = <0x1f>; + }; + + /* OCP NIC FRU EEPROM */ + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; +}; + +&i2c5 { + status = "okay"; + + gpio-expander@22 { + compatible = "nxp,pca9535"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "JTAG_BMC_IOEXP_MUX_OE", "JTAG_BMC_MCIO_MUX_S1", + "JTAG_BMC_MCIO_MUX_S0", "JTAG_IOEXP_BMC_MUX_SEL", + "FM_USB_MUX_1_OE_N", "FM_USB_MUX_2_OE_N", + "PROGRAMN_CPLD", "", + "", "", + "", "", + "", "", + "", ""; + }; + + /* I2C MUX for MCIO 1A */ + i2c-mux@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c5mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c5mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + /* I2C MUX for MCIO 0A */ + i2c-mux@77 { + compatible = "nxp,pca9546"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c5mux1ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c5mux1ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c6 { + status = "okay"; + + /* I2C MUX for PWRPIC #13 ~ #16 */ + i2c-mux@77 { + compatible = "nxp,pca9546"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + /* PWRPIC #13 */ + i2c6mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* PWRPIC #14 */ + i2c6mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* PWRPIC #16 */ + i2c6mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* PWRPIC #15 */ + i2c6mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c7 { + multi-master; + status = "okay"; + + ipmb@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c8 { + status = "okay"; + + power-monitor@14 { + compatible = "infineon,xdp710"; + reg = <0x14>; + }; + + adc@1d { + compatible = "ti,adc128d818"; + reg = <0x1d>; + ti,mode = /bits/ 8 <1>; + }; + + /* PDB IOEXP0 */ + pdb_io_expander0: gpio-expander@24 { + compatible = "nxp,pca9555"; + reg = <0x24>; + interrupt-parent = <&sgpiom0>; + interrupts = <92 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "FM_P52V_AUX_FLT_N","FM_P12V_AUX_ALERT_N", + "FM_SLOT1_HSC_FAULT","FM_SLOT2_HSC_FAULT", + "FM_SLOT3_HSC_FAULT","FM_SLOT4_HSC_FAULT", + "FM_SLOT5_HSC_FAULT","FM_SLOT6_HSC_FAULT", + "PRSNT_FAN0","PRSNT_FAN1", + "PRSNT_FAN2","PRSNT_FAN3", + "","", + "","INT_SLOT"; + }; + + /* PDB IOEXP1 */ + gpio-expander@25 { + compatible = "nxp,pca9555"; + reg = <0x25>; + interrupt-parent = <&pdb_io_expander0>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "SLOT1_CM_UPDATE","SLOT2_CM_UPDATE", + "SLOT3_CM_UPDATE","SLOT4_CM_UPDATE", + "SLOT5_CM_UPDATE","SLOT6_CM_UPDATE", + "","", + "","", + "","", + "","", + "",""; + }; + + power-sensor@40 { + compatible = "ti,ina238"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + /* PADDLE BD IOEXP */ + gpio-expander@41 { + compatible = "nxp,pca9536"; + reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "HSC_OC_GPIO0", "HSC_OC_GPIO1", + "HSC_OC_GPIO2", "HSC_OC_GPIO3"; + }; + + power-sensor@42 { + compatible = "ti,ina238"; + reg = <0x42>; + shunt-resistor = <1000>; + }; + + power-monitor@43 { + compatible = "lltc,ltc4287"; + reg = <0x43>; + shunt-resistor-micro-ohms = <100>; + }; + + power-sensor@44 { + compatible = "ti,ina238"; + reg = <0x44>; + shunt-resistor = <1000>; + }; + + power-sensor@45 { + compatible = "ti,ina238"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + + power-monitor@46 { + compatible = "mps,mp5998"; + reg = <0x46>; + }; + + power-monitor@47 { + compatible = "ti,tps25990"; + reg = <0x47>; + ti,rimon-micro-ohms = <430000000>; + }; + + temperature-sensor@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + }; + + temperature-sensor@49 { + compatible = "ti,tmp75"; + reg = <0x49>; + }; + + /* PDB FRU */ + eeprom@56 { + compatible = "atmel,24c128"; + reg = <0x56>; + }; + + /* Paddle BD FRU */ + eeprom@57 { + compatible = "atmel,24c128"; + reg = <0x57>; + }; + + power-monitor@58 { + compatible = "renesas,isl28022"; + reg = <0x58>; + shunt-resistor-micro-ohms = <10000>; + }; + + power-monitor@59 { + compatible = "renesas,isl28022"; + reg = <0x59>; + shunt-resistor-micro-ohms = <10000>; + }; + + power-monitor@5a { + compatible = "renesas,isl28022"; + reg = <0x5a>; + shunt-resistor-micro-ohms = <10000>; + }; + + power-monitor@5b { + compatible = "renesas,isl28022"; + reg = <0x5b>; + shunt-resistor-micro-ohms = <10000>; + }; + + psu@5c { + compatible = "renesas,raa228006"; + reg = <0x5c>; + }; + + fan-controller@5e{ + compatible = "maxim,max31790"; + reg = <0x5e>; + }; + + /* I2C MUX for PWRPIC #1, #2, #11, #12 */ + i2c-mux@77 { + compatible = "nxp,pca9546"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + /* PWRPIC #1 */ + i2c8mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* PWRPIC #2 */ + i2c8mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* PWRPIC #12 (Connector to CXL BD) */ + i2c8mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + i2c26mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c26mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c26mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + /* CXL FRU */ + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + i2c26mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + /* PWRPIC #11 */ + i2c8mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c9 { + status = "okay"; + + temperature-sensor@4b { + compatible = "ti,tmp75"; + reg = <0x4b>; + }; + + /* SCM FRU */ + eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; + + /* BSM FRU */ + eeprom@56 { + compatible = "atmel,24c64"; + reg = <0x56>; + }; +}; + +/* MCIO 0A I2C */ +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; + + /* I2C11_IOEXP_3 */ + gpio-expander@20 { + compatible = "nxp,pca9535"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "IRQ_INA230_FAN0_ALERT_N_CPLD", "IRQ_INA230_FAN1_ALERT_N_CPLD", + "IRQ_INA230_FAN2_ALERT_N_CPLD", "IRQ_INA230_FAN3_ALERT_N_CPLD", + "IRQ_INA230_P12V_DIMM_0_ALERT_N", "IRQ_INA230_P12V_DIMM_1_ALERT_N", + "IRQ_P3V3_E1S_0_FLT_N", "P12V_E1S_0_FAULT_R_N", + "IRQ_P3V3_E1S_1_FLT_N", "P12V_E1S_1_FAULT_R_N", + "IRQ_P3V3_NIC_FLT_N", "P12V_NIC_FAULT_R_N", + "SMB_SENSOR_ALERT_N", "FW_CPLD_RST_RTC_RST_R1", + "RTC_CLR", "RTC_U11_ALRT_N"; + }; + + /* I2C11_IOEXP_2 */ + gpio-expander@21 { + compatible = "nxp,pca9535"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "FAN_0_PRESENT_CPLD", "FAN_1_PRESENT_CPLD", + "FAN_2_PRESENT_CPLD", "FAN_3_PRESENT_CPLD", + "FAN_FAIL_L_CPLD", "FULL_SPEED_N_R_CPLD", + "P12V_FAN0_PWRGD_CPLD", "P12V_FAN1_PWRGD_CPLD", + "P12V_FAN2_PWRGD_CPLD", "P12V_FAN3_PWRGD_CPLD", + "FM_P12V_FAN0_FLTB_N_CPLD", "FM_P12V_FAN1_FLTB_N_CPLD", + "FM_P12V_FAN2_FLTB_N_CPLD", "FM_P12V_FAN3_FLTB_N_CPLD", + "P12V_FAN_EN_R_CPLD", ""; + }; + + /* I2C11_IOEXP_1 */ + gpio-expander@27 { + compatible = "nxp,pca9535"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "PWRGD_P12V_SCM", "PWRGD_P5V_STBY", + "PWRGD_P3V3_STBY", "PWRGD_P1V8_STBY", + "PWRGD_P1V2_STBY", "PWRGD_P1V1_STBY", + "PWRGD_P1V0_STBY", "", + "", "", + "", "", + "", "", + "", ""; + }; + + power-sensor@40 { + compatible = "ti,ina230"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + power-sensor@41 { + compatible = "ti,ina230"; + reg = <0x41>; + shunt-resistor = <1000>; + }; + + power-sensor@42 { + compatible = "ti,ina230"; + reg = <0x42>; + shunt-resistor = <2000>; + }; + + power-sensor@43 { + compatible = "ti,ina230"; + reg = <0x43>; + shunt-resistor = <2000>; + }; + + power-sensor@44 { + compatible = "ti,ina230"; + reg = <0x44>; + shunt-resistor = <2000>; + }; + + power-sensor@45 { + compatible = "ti,ina230"; + reg = <0x45>; + shunt-resistor = <2000>; + }; + + adc@49 { + compatible = "ti,ads7830"; + reg = <0x49>; + }; + + adc@4a { + compatible = "ti,ads7830"; + reg = <0x4a>; + }; + + adc@4b { + compatible = "ti,ads7830"; + reg = <0x4b>; + }; + rtc@6f { + compatible = "nuvoton,nct3018y"; + reg = <0x6f>; + status = "okay"; + }; +}; + +/* MCIO 4A I2C */ +&i2c12 { + multi-master; + mctp-controller; + clock-frequency = <400000>; + status = "okay"; + + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; +}; + +&i2c13 { + status = "okay"; + + fan-controller@20 { + compatible = "maxim,max31790"; + reg = <0x20>; + }; + + power-sensor@40 { + compatible = "ti,ina230"; + reg = <0x40>; + shunt-resistor = <2000>; + }; + + power-sensor@41 { + compatible = "ti,ina230"; + reg = <0x41>; + shunt-resistor = <2000>; + }; + + power-sensor@44 { + compatible = "ti,ina230"; + reg = <0x44>; + shunt-resistor = <2000>; + }; + + power-sensor@45 { + compatible = "ti,ina230"; + reg = <0x45>; + shunt-resistor = <2000>; + }; + + temperature-sensor@48 { + compatible = "national,lm75b"; + reg = <0x48>; + }; + + temperature-sensor@49 { + compatible = "national,lm75b"; + reg = <0x49>; + }; + + /* MB FRU */ + eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; +}; + +/* PROT reserve */ +&i2c14 { + status = "okay"; +}; + +/* MCIO 3A I2C */ +&i2c15 { + status = "okay"; +}; + +&mac2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ncsi3_default>; + use-ncsi; + status = "okay"; +}; + +&pinctrl { + pinctrl_ncsi3_default: ncsi3_default { + function = "RMII3"; + groups = "NCSI3"; + }; +}; + +&sgpiom0 { + status = "okay"; + ngpios = <128>; + bus-frequency = <2000000>; + gpio-line-names = + /*"input pin","output pin"*/ + "SOC_ERROR_N_CPLD","RST_SOC_SRST_N_CPLD", + "SOC_ELASTOPCLK_N","SOC_BMC_READY_CPLD", + "SOC_LINKSTOP_N","wIBB_BMC_SRST_OUT", + "SOC_POST_COMPLETE_CPLD","I3C_MUX_SEL_DIMM_C0_024", + "SOC_RESETREQ","I3C_MUX_SEL_DIMM_C0_135", + "SOC_SYS_PWRDN_CPLD","I3C_MUX_SEL_DIMM_C1_024", + "SOC_PORQ","I3C_MUX_SEL_DIMM_C1_135", + "SOC_HOT_N_CPLD","BOOT_PWRDIS_CPLD", + // IOB0-IOB7 bit8-15 + "PWRGD_V1P8_CPU","HDD0_PERST_N_CPLD", + "PWRGD_V1P26_CPLD","HDD1_PERST_N_CPLD", + "PWRGD_V1P2","MCIO_1A_PWRDIS_R", + "","", + "FM_CONFIG_ID","P3V_BAT_SCALED_EN", + "wALL_POWER_OK","PERST_CEM0_N_CPLD", + "wANDGATE_ALL_POWER_GD","PERST_CEM1_N_CPLD", + "wAC_CYCLE_12V","PERST_PLD_TUSB7340_N", + // IOC0-IOC7 bit16-23 + "wAC_CYCLE_54V","FM_USB_MUX_SEL_CPLD", + "FM_PLD_CLKS_DEV_EN","SMB_BOOT_RST_N_CPLD", + "PWRGD_P1V2_STBY","SMB_MCIO_0A_RST_R_N", + "wIBB_BMC_SRST","RST_SMB_NIC_R_N", + "PWRGD_P12V_E1S_0","FM_PPS_NIC_IN_BUF_OE_N_R", + "PWRGD_P12V_E1S_1","FM_BUF_PPS_NIC_IN_EN_CPLD", + "","FM_NIC_PPS_IN_OE_CPLD", + "PWRGD_P12V_NIC","FM_PPS_NIC_IN_S0_CPLD", + // IOD0-IOD7 bit24-31 + "wALL_POWER_OK_1","FM_NIC_PPS_IN_S1", + "wALL_POWER_OK_2","FM_PPS_NIC_OUT_CPU_OE_N", + "PWRGD_EAST_DIMM_CPLD","", + "PWRGD_WEST_DIMM_CPLD","FM_BUF_PPS_NIC_OUT_EN_CPLD", + "PWRGD_NIC_CPLD","", + "","PMBUS_MUX_SEL_C0", + "PHOENIX_PWRBTN_N_CPLD","PMBUS_MUX_SEL_C1", + "IRQ_INA230_E1S_0_ALERT_N","", + // IOE0-IOE7 bit32-39 + "IRQ_INA230_E1S_1_ALERT_N","PWR_ON_RST_TUSB7340_CPLD", + "","RST_PCIE_BOOT_PERST_N_CPLD", + "FM_NIC_WAKE_N_CPLD","RST_PCIE_CPLD_NIC_N_CPLD", + "FM_TPM_CONN_PRSNT_N","RST_PCIE_MCIO_0A_PERST_N_CPLD", + "HDD0_PRSNT_N_CPLD","RST_PCIE_MCIO_0B_PERST_N_CPLD", + "IRQ_INA230_P12V_NIC_ALERT_N","RST_PCIE_MCIO_1A_PERST_N_CPLD", + "IRQ_INA230_P12V_SCM_ALERT_N","RST_PCIE_MCIO_1A_SA_PERST_N_CPL", + "IRQ_PMBUS_ALERT_PWR11_R_N","RST_PCIE_MCIO_1B_PERST_N_CPLD", + // IOF0-IOF7 bit40-47 + "CHASSIS_LEAK_2A_R_N","RST_PCIE_MCIO_2A_PERST_N_CPLD", + "CHASSIS_LEAK_3A_R_N","RST_PCIE_MCIO_2B_PERST_N_CPLD", + "CHASSIS_LEAK_4A_R_N","RST_PCIE_MCIO_3A_PERST_N_CPLD", + "OC_ALERT_PADDLE_R_N","RST_PCIE_MCIO_3B_PERST_N_CPLD", + "OC_ALERT_PWR2_R_N","RST_PCIE_MCIO_4A_PERST_N_CPLD", + "OC_ALERT_PWR11_R_N","RST_PCIE_MCIO_4B_PERST_N_CPLD", + "FM_IOE_ALT_N","RST_PERST1_N_CPLD", + "LEAK_DETECT_1_PWR14_R_N","RST_PERST2_N_CPLD", + // IOG0-IOG7 bit48-55 + "LEAK_DETECT_2_PWR14_R_N","RST_PERST3_N_CPLD", + "LEAK_DETECT_1_PWR15_R_N","RST_SMB_MUX_MCIO_0A_R_N", + "LEAK_DETECT_2_PWR15_R_N","RST_SMB_MUX_MCIO_1A_R_N", + "MCIO_0A_SMB_ALERT_N","RST_SOC_EXTWARMRESET_CPLD", + "MCIO_1A_SMB_ALERT_N","RST_SOC_PORESET_N_BMC", + "MCIO_2A_SMB_ALERT_N","RST_USB_HUB_R_N", + "MCIO_2B_SMB_ALERT_N","SMB_MM7_MUX_RESET_N", + "MCIO_3A_SMB_ALERT_N","SMB_MUX_RESET_N_CPLD", + // IOH0-IOH7 bit56-63 + "MCIO_3B_SMB_ALERT_N","SOC_I2C_0_ALERT_CPLD", + "MCIO_4A_SMB_ALERT_N","SOC_LINKSTOP_OUT_N", + "MCIO_4B_SMB_ALERT_N","SPI_TPM_RST_R_N", + "MCIO_1A_THERMTRIP_N","", + "MCIO_2A_THERMTRIP_N","", + "MCIO_3A_THERMTRIP_N","", + "MCIO_4A_THERMTRIP_N_CPLD","", + "UV_ALERT_PADDLE_R_N","wFM_USB_MUX_OE_N", + // IOI0-IOI7 bit64-71 + "UV_ALERT_PWR2_R_N","wFM_USB_MUX_SEL", + "UV_ALERT_PWR11_R_N","", + "SOC_PMBUS_0_ALERT_R_CPLD","FM_BIOS_DEBUG_MODE_N", + "HDD1_PRSNT_N_CPLD","", + "","", + "SOC_DRAM_0_HOT_N_CPLD","", + "SOC_DRAM_1_HOT_N_CPLD","RST_PLTRST_PLD_B_N", + "SOC_DRAM_2_HOT_N_CPLD","FM_TPM_MUX6_SEL", + // IOJ0-IOJ7 bit72-79 + "SOC_DRAM_3_HOT_N_CPLD","CPLD_MUX6_EN_N", + "IRQ_P3V3_NIC_FLT_MOS_N_CPLD","", + "VRHOT_V0P75_PCIE_VDDQ_N","", + "P12V_SCM_FAULT_R_N","", + "SOC_I2C_1_ALERT_CPLD","", + "","", + "SOC_PLATHOT_N_CPLD","", + "SOC_THRMTRIP_N_CPLD","", + // IOK0-IOK7 bit80-87 + "VRHOT_VCPUC1_VCPUMC1_N","", + "VRHOT_VSYSC0_VSOCC0_N","", + "VRHOT_VSYSC1_VSOCC1_N","", + "VRHOT_VCPUC0_VCPUMC0_N","", + "","", + "INT_IOEXP_N","", + "RSVD_IOEXP_0A_SB1_R","", + "RSVD_IOEXP_0A_SB2_R","", + // IOL0-IOL7 bit88-95 + "IRQ_PMBUS_PWR2_ALERT_R_N","", + "FM_BORD_REV_ID0","", + "FM_BORD_REV_ID1","", + "FM_BORD_REV_ID2","", + "FM_VR_TYPE_0","", + "FM_VR_TYPE_1","", + "","", + "MCIO_0B_SMB_ALERT_N","", + // IOM0-IOM7 bit96-103 + "MCIO_1B_SMB_ALERT_N","", + "PRSNT_BOOT_N","", + "PRSNT_MCIO_1A_N","", + "wPRSNT_NIC_N","", + "","", + "SOC_TEST_MODE0","", + "PWRGD_V0P75_PCIE","", + "PWRGD_VDDQ","", + // ION0-ION7 bit104-111 + "PWRGD_VCPUC0","", + "PWRGD_VCPUMC0","", + "PWRGD_VCPUMC1","", + "PWRGD_VCPUC1","", + "PWRGD_VSYSC0","", + "PWRGD_VSOCC0","", + "PWRGD_VSYSC1","", + "PWRGD_VSOCC1","", + // IOO0-IOO7 bit112-119 + "SOC_PMBUS_1_ALERT_R_CPLD","", + "SOC_GPIO_15","", + "C0_POSTCODE_0_CPLD","", + "C0_POSTCODE_1_CPLD","", + "C0_POSTCODE_2_CPLD","", + "C0_POSTCODE_3_CPLD","", + "C0_POSTCODE_4_CPLD","", + "C1_POSTCODE_0_CPLD","", + // IOP0-IOP7 bit 120-127 + "C1_POSTCODE_1_CPLD","", + "C1_POSTCODE_2_CPLD","", + "C1_POSTCODE_3_CPLD","", + "C1_POSTCODE_4_CPLD","", + "","", + "SOC_GPIO_17","", + "SOC_GPIO_18","", + "SOC_GPIO_37",""; +}; + +/* BIOS Flash */ +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2_default>; + status = "okay"; + + flash@0 { + m25p,fast-read; + label = "pnor"; + spi-max-frequency = <12000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + status = "okay"; + }; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +/* SOL */ +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +/* BMC Console */ +&uart5 { + status = "okay"; +}; + +&wdt1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; + aspeed,reset-type = "soc"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + aspeed,ext-pulse-duration = <256>; + status = "okay"; +}; From 6b3a3c10cede25222aa2f15af2f3a588c7beb763 Mon Sep 17 00:00:00 2001 From: Anirudh Srinivasan Date: Tue, 31 Mar 2026 09:18:00 -0500 Subject: [PATCH 438/665] ARM: dts: aspeed: Enable networking for Asus Kommando IPMI Card Adds the DT nodes needed for ethernet support for Asus Kommando, with phy mode set to rgmii-id. When this DT was originally added, the phy mode was set to rgmii (which was incorrect). It was suggested to remove networking support from the DT till the Aspeed networking driver was patched so that the correct phy mode could be used. The discussion in [1] mentions that u-boot was inserting clk delays that weren't needed, which resulted in needing to set the phy mode in linux to rgmii incorrectly. The solution suggested there was to patch u-boot to no longer insert these clk delays and use rgmii-id as the phy mode for any future DTs added to linux. This DT was tested (on the OpenBMC u-boot fork [2]) with a u-boot DT modified to insert clk delays of 0 (instead of patching u-boot itself). [3] adds a u-boot DT for this device (without networking) and describes how to patch it to add networking support. If this patched DT is used, then networking works with rgmii-id phy mode in both u-boot and linux. [1] https://lore.kernel.org/linux-aspeed/ef88bb50-9f2c-458d-a7e5-dc5ecb9c777a@lunn.ch/ [2] https://github.com/openbmc/u-boot/tree/v2019.04-aspeed-openbmc [3] https://lore.kernel.org/openbmc/20260328-asus-kommando-v2-1-2a656f8cd314@gmail.com/ Signed-off-by: Anirudh Srinivasan Reviewed-by: Andrew Lunn Link: https://patch.msgid.link/20260331-asus-kommando-networking-v2-1-f7d72ae5d40d@gmail.com Signed-off-by: Andrew Jeffery --- .../aspeed-bmc-asus-kommando-ipmi-card.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asus-kommando-ipmi-card.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asus-kommando-ipmi-card.dts index ab7ad320067c..e0f7d92efa18 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-asus-kommando-ipmi-card.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asus-kommando-ipmi-card.dts @@ -107,6 +107,24 @@ &gpio1 { /*18E0 32*/ "","","","","","","",""; }; +&mac2 { + status = "okay"; + + phy-mode = "rgmii-id"; + phy-handle = <ðphy2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii3_default>; +}; + +&mdio2 { + status = "okay"; + + ethphy2: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + &vhub { status = "okay"; }; From 9c18b2048274d05bc78cdc309278a581e77c19a1 Mon Sep 17 00:00:00 2001 From: Mike Hsieh Date: Fri, 22 May 2026 18:07:59 +0800 Subject: [PATCH 439/665] ARM: dts: aspeed: clemente: Remove IOB NIC TMP421 nodes Remove the TMP421 sensor entry from the DTS, as it is no longer the primary telemetry source. Accessing the CX8 NIC via I2C while it is powered off causes voltage leakage on the bus, leading to EEPROM corruption on shared I2C devices. Removing this node prevents the BMC from initiating traffic to the NIC during initialization, protecting the integrity of the shared bus. Signed-off-by: Mike Hsieh Signed-off-by: Andrew Jeffery --- .../aspeed/aspeed-bmc-facebook-clemente.dts | 20 ------------------- 1 file changed, 20 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts index 2aff21442f11..820d39a92974 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts @@ -443,11 +443,6 @@ i2c0mux2ch0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; - // IOB0 NIC0 TEMP - temperature-sensor@1f { - compatible = "ti,tmp421"; - reg = <0x1f>; - }; }; i2c0mux2ch1: i2c@1 { @@ -466,11 +461,6 @@ i2c0mux2ch3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; - // IOB0 NIC1 TEMP - temperature-sensor@1f { - compatible = "ti,tmp421"; - reg = <0x1f>; - }; }; }; @@ -637,11 +627,6 @@ i2c0mux5ch0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; - // IOB1 NIC0 TEMP - temperature-sensor@1f { - compatible = "ti,tmp421"; - reg = <0x1f>; - }; }; i2c0mux5ch1: i2c@1 { @@ -666,11 +651,6 @@ i2c0mux5ch3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; - // IOB1 NIC1 TEMP - temperature-sensor@1f { - compatible = "ti,tmp421"; - reg = <0x1f>; - }; }; }; }; From 136fdfdad2170ef87d5991613f925b61e1cbe483 Mon Sep 17 00:00:00 2001 From: Potin Lai Date: Sat, 23 May 2026 10:28:07 +0800 Subject: [PATCH 440/665] ARM: dts: aspeed: sanmiguel: Add IOEXP interrupt pin settings Kernel dmesg reports IRQ #44 being disabled due to unhandled interrupts from multiple PCA953x IO expanders: [ 447.047861] irq 44: nobody cared (try booting with the "irqpoll" option) [ 447.063124] handlers: [ 447.068176] [<2ab869ad>] irq_default_primary_handler threaded [] pca953x_irq_handler [ 447.087268] [<2ab869ad>] irq_default_primary_handler threaded [] pca953x_irq_handler [ 447.106344] [<2ab869ad>] irq_default_primary_handler threaded [] pca953x_irq_handler [ 447.125421] [<2ab869ad>] irq_default_primary_handler threaded [] pca953x_irq_handler [ 447.144513] [<2ab869ad>] irq_default_primary_handler threaded [] pca953x_irq_handler [ 447.163587] [<2ab869ad>] irq_default_primary_handler threaded [] pca953x_irq_handler [ 447.182663] [<2ab869ad>] irq_default_primary_handler threaded [] pca953x_irq_handler [ 447.201756] [<2ab869ad>] irq_default_primary_handler threaded [] pca953x_irq_handler [ 447.220837] Disabling IRQ #44 The affected IOEXP nodes are missing interrupt pin configuration in the device tree, causing the interrupt line to remain asserted and resulting in repeated unhandled IRQ events. Add the required interrupt-related properties for the affected IOEXP devices to ensure proper interrupt handling and prevent the IRQ from being disabled. [arj: Drop markdown code-block fence, favour indentation] Signed-off-by: Potin Lai Link: https://patch.msgid.link/20260523-potin-update-sanmiguel-dts-20260522-v1-1-169f5fceb5f9@quantatw.com Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts index 74c8c1772109..61dbef45f8b0 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts @@ -334,6 +334,8 @@ hmc_ioexp: gpio@20 { reg = <0x20>; gpio-controller; #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = ; gpio-line-names = "", "", "HMC_EROT_FATAL_ERROR_L-I", "", @@ -552,6 +554,8 @@ smm_ext_ioexp: gpio@38 { reg = <0x38>; gpio-controller; #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = ; gpio-line-names = "SSD0_PRSNT_L-I", "E1S_PWR_EN-O", From 1249ee157de518a76cec169e2a5db4d6e523cc90 Mon Sep 17 00:00:00 2001 From: Potin Lai Date: Sat, 23 May 2026 10:28:08 +0800 Subject: [PATCH 441/665] ARM: dts: aspeed: sanmiguel: Fix the CPU_CHIPTHROT linename Fix the GPIO linenames for CPU_CHIPTHROT signals. The signals were incorrectly marked as output ("-O") while they are actually input signals ("-I"). [arj: Drop list of changed names] Signed-off-by: Potin Lai Link: https://patch.msgid.link/20260523-potin-update-sanmiguel-dts-20260522-v1-2-169f5fceb5f9@quantatw.com Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts index 61dbef45f8b0..d7ed497d7227 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts @@ -224,7 +224,7 @@ hpm0_ioexp_20: gpio@20 { "B0_M0_LEAK_DETECT_ALERT_L-I", "B0_M0_RUN_POWER_EN-O", "B0_M0_RUN_POWER_PG-I", - "B0_M0_CPU_CHIPTHROT_L-O", + "B0_M0_CPU_CHIPTHROT_L-I", "B0_M0_SHDN_REQ_L-O", "B0_M0_CPU_SHDN_OK_L-I", "B0_M0_CPLD_READY-I", @@ -398,7 +398,7 @@ hpm1_ioexp_20: gpio@20 { "B1_M0_LEAK_DETECT_ALERT_L-I", "B1_M0_RUN_POWER_EN-O", "B1_M0_RUN_POWER_PG-I", - "B1_M0_CPU_CHIPTHROT_L-O", + "B1_M0_CPU_CHIPTHROT_L-I", "B1_M0_SHDN_REQ_L-O", "B1_M0_CPU_SHDN_OK_L-I", "B1_M0_CPLD_READY-I", From 25ee898961a2c661e4cd72bc98f0060f1cd11222 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Sven=20P=C3=BCschel?= Date: Thu, 21 May 2026 00:44:33 +0200 Subject: [PATCH 442/665] arm64: dts: rockchip: add rga3 dt nodes to rk3588 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add devicetree nodes for the RGA3 (Raster Graphics Acceleration 3) peripheral in the RK3588. The existing rga node refers to the RGA2-Enhanced peripheral. The RK3588 contains one RGA2-Enhanced core and two RGA3 cores. Both feature a similar functionality of scaling, cropping and rotating of up to two input images into one output image. Key differences of the RGA3 are: - supports 10bit YUV output formats - supports 8x8 tiles and FBCD as inputs and outputs - supports BT2020 color space conversion - max output resolution of (8192-64)x(8192-64) - MMU can map up to 32G DDR RAM - fully planar formats (3 planes) are not supported - max scale up/down factor of 8 (RGA2 allows up to 16) Signed-off-by: Sven Püschel Link: https://patch.msgid.link/20260521-spu-rga3-v7-28-3f33e8c7145f@pengutronix.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 4535e0b6e979..4aff2701febf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1262,6 +1262,50 @@ vpu121_mmu: iommu@fdb50800 { #iommu-cells = <0>; }; + rga3_core0: rga@fdb60000 { + compatible = "rockchip,rk3588-rga3"; + reg = <0x0 0xfdb60000 0x0 0x200>; + interrupts = ; + clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>, <&cru CLK_RGA3_0_CORE>; + clock-names = "aclk", "hclk", "sclk"; + resets = <&cru SRST_RGA3_0_CORE>, <&cru SRST_A_RGA3_0>, <&cru SRST_H_RGA3_0>; + reset-names = "core", "axi", "ahb"; + power-domains = <&power RK3588_PD_RGA30>; + iommus = <&rga3_0_mmu>; + }; + + rga3_0_mmu: iommu@fdb60f00 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdb60f00 0x0 0x100>; + interrupts = ; + clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_RGA30>; + }; + + rga3_core1: rga@fdb70000 { + compatible = "rockchip,rk3588-rga3"; + reg = <0x0 0xfdb70000 0x0 0x200>; + interrupts = ; + clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>, <&cru CLK_RGA3_1_CORE>; + clock-names = "aclk", "hclk", "sclk"; + resets = <&cru SRST_RGA3_1_CORE>, <&cru SRST_A_RGA3_1>, <&cru SRST_H_RGA3_1>; + reset-names = "core", "axi", "ahb"; + power-domains = <&power RK3588_PD_RGA31>; + iommus = <&rga3_1_mmu>; + }; + + rga3_1_mmu: iommu@fdb70f00 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdb70f00 0x0 0x100>; + interrupts = ; + clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_RGA31>; + }; + rga: rga@fdb80000 { compatible = "rockchip,rk3588-rga", "rockchip,rk3288-rga"; reg = <0x0 0xfdb80000 0x0 0x180>; From c26a3fb47ff7c312808dc6267355aeb165434c54 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 28 Feb 2026 01:05:41 +0100 Subject: [PATCH 443/665] ARM: dts: gemini: iTian SQ201 need to boot from mtdblock3 Alter the rootfs partition to the one actually used for the rootfs. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/gemini/gemini-sq201.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/gemini/gemini-sq201.dts b/arch/arm/boot/dts/gemini/gemini-sq201.dts index f8c6f6e5cdea..fb6959324658 100644 --- a/arch/arm/boot/dts/gemini/gemini-sq201.dts +++ b/arch/arm/boot/dts/gemini/gemini-sq201.dts @@ -20,7 +20,7 @@ memory@0 { /* 128 MB */ }; chosen { - bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait"; + bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock3 rw rootfstype=squashfs,jffs2 rootwait"; stdout-path = &uart0; }; From 04ff9bcbc5d05921d7a4cc5477a7d40948841ec7 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 28 Feb 2026 01:05:42 +0100 Subject: [PATCH 444/665] ARM: dts: gemini: Tag disk led for disk-activity Linux now has a trigger specifically for all disk activity and this is what the LED is used for so tag it like such. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/gemini/gemini-nas4220b.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/gemini/gemini-nas4220b.dts b/arch/arm/boot/dts/gemini/gemini-nas4220b.dts index 6544c730340f..2488b9b24218 100644 --- a/arch/arm/boot/dts/gemini/gemini-nas4220b.dts +++ b/arch/arm/boot/dts/gemini/gemini-nas4220b.dts @@ -52,6 +52,7 @@ led-orange-hdd { /* Conflict with TVC */ gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; default-state = "on"; + linux,default-trigger = "disk-activity"; }; led-green-os { label = "nas4220b:green:os"; From 14535431a5a25311a0d434745a8edc56a84c3fd7 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 28 Feb 2026 01:05:43 +0100 Subject: [PATCH 445/665] ARM: dts: gemini: Add SSP/SPI block Add the SSP/SPI block to the Gemini device tree. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/gemini/gemini.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/gemini/gemini.dtsi b/arch/arm/boot/dts/gemini/gemini.dtsi index befe322bd7de..23e68e17ffbb 100644 --- a/arch/arm/boot/dts/gemini/gemini.dtsi +++ b/arch/arm/boot/dts/gemini/gemini.dtsi @@ -61,6 +61,12 @@ mux { groups = "rtcgrp"; }; }; + ssp_default_pins: pinctrl-ssp { + mux { + function = "ssp"; + groups = "sspgrp"; + }; + }; power_default_pins: pinctrl-power { mux { function = "power"; @@ -228,6 +234,17 @@ intcon: interrupt-controller@48000000 { #interrupt-cells = <2>; }; + spi@4a000000 { + compatible = "faraday,ftssp010"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4a000000 0x100>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&ssp_default_pins>; + status = "disabled"; + }; + power-controller@4b000000 { compatible = "cortina,gemini-power-controller"; reg = <0x4b000000 0x100>; From 4b8c63c6a2811c23995c5d8cc8bb63d26caab299 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 28 Feb 2026 01:05:44 +0100 Subject: [PATCH 446/665] dt-bindings: vendor-prefixes: Add Verbatim Corporation Verbatim Corporation has manufactured a few electronics items over the years. Link: https://en.wikipedia.org/wiki/Verbatim_(company) Acked-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 28784d66ae7b..5a043ad75cb1 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1783,6 +1783,8 @@ patternProperties: description: Variscite Ltd. "^vdl,.*": description: Van der Laan b.v. + "^verbatim,.*": + description: Verbatim Corporation "^verisilicon,.*": description: VeriSilicon Microelectronics (Shanghai) Co., Ltd. "^vertexcom,.*": From 5afc001ba600c2444db39c2968dc3fce44fa6866 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 28 Feb 2026 01:05:45 +0100 Subject: [PATCH 447/665] dt-bindings: arm: Add two missing Gemini devices This adds the Raidsonic IB-4210-B and the Verbatim S08V1901-D1 that were missing from the bindings. Acked-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/arm/gemini.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/gemini.yaml b/Documentation/devicetree/bindings/arm/gemini.yaml index fc092962ab56..dfb11244b57e 100644 --- a/Documentation/devicetree/bindings/arm/gemini.yaml +++ b/Documentation/devicetree/bindings/arm/gemini.yaml @@ -55,6 +55,11 @@ properties: - const: itian,sq201 - const: cortina,gemini + - description: Raidsonic NAS IB-4210-B + items: + - const: raidsonic,ib-4210-b + - const: cortina,gemini + - description: Raidsonic NAS IB-4220-B items: - const: raidsonic,ib-4220-b @@ -70,6 +75,11 @@ properties: - const: teltonika,rut1xx - const: cortina,gemini + - description: Verbatim S08V1901-D1 NAS + items: + - const: verbatim,s08v1901-d1 + - const: cortina,gemini + - description: Wiligear Wiliboard WBD-111 items: - const: wiligear,wiliboard-wbd111 From ccd7118d30488d69561e4c7a7e2062a367825719 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 28 Feb 2026 01:05:46 +0100 Subject: [PATCH 448/665] ARM: dts: Add a Verbatim Gigabit NAS DTS This adds a device tree for the Verbatim S08V1901-D1 NAS which also has the product names "Gigabit Network Hard Drive" "Gigabit NAS" and maybe other names. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/gemini/Makefile | 1 + .../gemini/gemini-verbatim-s08v1901-d1.dts | 225 ++++++++++++++++++ 2 files changed, 226 insertions(+) create mode 100644 arch/arm/boot/dts/gemini/gemini-verbatim-s08v1901-d1.dts diff --git a/arch/arm/boot/dts/gemini/Makefile b/arch/arm/boot/dts/gemini/Makefile index f9f63ce3eb49..d5d32f02e232 100644 --- a/arch/arm/boot/dts/gemini/Makefile +++ b/arch/arm/boot/dts/gemini/Makefile @@ -8,5 +8,6 @@ dtb-$(CONFIG_ARCH_GEMINI) += \ gemini-sl93512r.dtb \ gemini-sq201.dtb \ gemini-ssi1328.dtb \ + gemini-verbatim-s08v1901-d1.dtb \ gemini-wbd111.dtb \ gemini-wbd222.dtb diff --git a/arch/arm/boot/dts/gemini/gemini-verbatim-s08v1901-d1.dts b/arch/arm/boot/dts/gemini/gemini-verbatim-s08v1901-d1.dts new file mode 100644 index 000000000000..2a689d276863 --- /dev/null +++ b/arch/arm/boot/dts/gemini/gemini-verbatim-s08v1901-d1.dts @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the Verbatim S08V1901-D1 + * on product packaging called "Verbatim Gigabit Ethernet Hard Drive" + */ + +/dts-v1/; + +#include "gemini.dtsi" +#include +#include + +/ { + model = "Verbatim Gigabit Ethernet Hard Drive S08V1901-D1"; + compatible = "verbatim,s08v1901-d1", "cortina,gemini"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* 64MB SDRAM in 2 x Hynix HY5DU561622ETP-D43 */ + device_type = "memory"; + reg = <0x00000000 0x4000000>; + }; + + chosen { + bootargs = "console=ttyS0,19200n8 root=/dev/sda1 rw rootwait"; + stdout-path = &uart0; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button-reset { + debounce-interval = <50>; + wakeup-source; + linux,code = ; + label = "reset"; + gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + led-green-harddisk { + function = LED_FUNCTION_DISK_ACTIVITY; + color = ; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + linux,default-trigger = "disk-activity"; + }; + }; + + /* + * Fan control candidates: gpio0 10, gpio1 28 + */ + + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + /* Uses MDC and MDIO */ + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ + <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ + #address-cells = <1>; + #size-cells = <0>; + + /* This is a Realtek RTL8211CL ethernet PHY */ + phy0: ethernet-phy@1 { + reg = <1>; + }; + }; + + /* + * I haven't found a way to control the fan, it appears to be + * always on. + */ + thermal-zones { + chassis-thermal { + /* Poll every 20 seconds */ + polling-delay = <20000>; + /* Poll every 2nd second when cooling */ + polling-delay-passive = <2000>; + /* Use the thermal sensor in the hard drive */ + thermal-sensors = <&drive0>; + + /* Tripping points from the fan.script in the rootfs */ + trips { + alert: chassis-alert { + /* At 43 degrees turn on the fan */ + temperature = <43000>; + hysteresis = <3000>; + type = "active"; + }; + crit: chassis-crit { + /* Just shut down at 60 degrees */ + temperature = <60000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + soc { + flash@30000000 { + /* + * This is a Spansion S29GL128P11TFI01 852FB245 A + * 128Mbit (16MB) Flash memory. + */ + status = "okay"; + reg = <0x30000000 0x01000000>; + + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0xfe0000 */ + fis-index-block = <0x7f>; + }; + }; + + syscon: syscon@40000000 { + pinctrl { + /* + * gpio0agrp cover line 0-4 as line 1 is used for the LED + * gpio0hgrp cover line 21, 22 used by MDIO for Marvell PHY + */ + gpio0_default_pins: pinctrl-gpio0 { + mux { + function = "gpio0"; + groups = "gpio0agrp", "gpio0hgrp"; + }; + }; + gpio1_default_pins: pinctrl-gpio1 { + /* + * Free up the TVC pins at GPIO1 offset 28,29,30,31 + * line 31 is used for reset key + */ + mux { + function = "gpio1"; + groups = "gpio1dgrp"; + }; + }; + pinctrl-gmii { + mux { + function = "gmii"; + groups = "gmii_gmac0_grp"; + }; + /* TODO: investigate vendor registers on boot */ + conf0 { + pins = "V8 GMAC0 RXDV"; + skew-delay = <0>; + }; + conf1 { + pins = "Y7 GMAC0 RXC"; + skew-delay = <15>; + }; + conf2 { + pins = "T8 GMAC0 TXEN"; + skew-delay = <7>; + }; + conf3 { + pins = "U8 GMAC0 TXC"; + skew-delay = <10>; + }; + conf4 { + /* The data lines all have default skew */ + pins = "W8 GMAC0 RXD0", "V9 GMAC0 RXD1", + "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3", + "T7 GMAC0 TXD0", "U6 GMAC0 TXD1", + "V7 GMAC0 TXD2", "U7 GMAC0 TXD3"; + skew-delay = <7>; + }; + }; + }; + }; + + /* Both interfaces brought out on SATA connectors */ + sata: sata@46000000 { + cortina,gemini-ata-muxmode = <0>; + cortina,gemini-enable-sata-bridge; + status = "okay"; + }; + + gpio0: gpio@4d000000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_default_pins>; + }; + + gpio1: gpio@4e000000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio1_default_pins>; + }; + + ethernet@60000000 { + status = "okay"; + + ethernet-port@0 { + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + }; + + ide@63000000 { + status = "okay"; + /* + * This drive may have a temperature sensor with a + * thermal zone we can use for thermal control of the + * chassis temperature using the fan. + */ + drive0: ide-port@0 { + reg = <0>; + #thermal-sensor-cells = <0>; + }; + }; + + ide@63400000 { + status = "okay"; + }; + + usb@68000000 { + status = "okay"; + }; + + usb@69000000 { + status = "okay"; + }; + }; +}; From 0b6084ebde381d808c80bf42364298e2ae326175 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 28 Feb 2026 01:05:47 +0100 Subject: [PATCH 449/665] ARM: dts: Add a Raidsonic IB-4210-B DTS This adds a device tree for the Raidsonic IB-4210-B NAS, a slightly under-powered version of IB-4220-B with half the memory and the cheaper version of the SoC. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/gemini/Makefile | 1 + arch/arm/boot/dts/gemini/gemini-nas4210b.dts | 205 +++++++++++++++++++ 2 files changed, 206 insertions(+) create mode 100644 arch/arm/boot/dts/gemini/gemini-nas4210b.dts diff --git a/arch/arm/boot/dts/gemini/Makefile b/arch/arm/boot/dts/gemini/Makefile index d5d32f02e232..4722fb1bac49 100644 --- a/arch/arm/boot/dts/gemini/Makefile +++ b/arch/arm/boot/dts/gemini/Makefile @@ -2,6 +2,7 @@ dtb-$(CONFIG_ARCH_GEMINI) += \ gemini-dlink-dir-685.dtb \ gemini-dlink-dns-313.dtb \ + gemini-nas4210b.dtb \ gemini-nas4220b.dtb \ gemini-ns2502.dtb \ gemini-rut1xx.dtb \ diff --git a/arch/arm/boot/dts/gemini/gemini-nas4210b.dts b/arch/arm/boot/dts/gemini/gemini-nas4210b.dts new file mode 100644 index 000000000000..8bec57c8b7b1 --- /dev/null +++ b/arch/arm/boot/dts/gemini/gemini-nas4210b.dts @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the Gemini-based Raidsonic NAS IB-4210-B + * Based on the NAS Forum experiments by user "CptSpock". + */ + +/dts-v1/; + +#include "gemini.dtsi" +#include + +/ { + model = "Raidsonic NAS IB-4210-B"; + compatible = "raidsonic,ib-4210-b", "cortina,gemini"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { /* 64 MB */ + device_type = "memory"; + reg = <0x00000000 0x4000000>; + }; + + chosen { + bootargs = "console=ttyS0,19200n8 root=/dev/sda1 rw rootwait"; + stdout-path = &uart0; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button-setup { + debounce-interval = <100>; + wakeup-source; + linux,code = ; + label = "Backup button"; + /* Conflict with TVC */ + gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; + }; + button-restart { + debounce-interval = <100>; + wakeup-source; + linux,code = ; + label = "Softreset button"; + /* Conflict with TVC */ + gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + led-orange-hdd { + label = "nas4220b:orange:hdd"; + /* Conflict with TVC */ + gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "disk-activity"; + }; + led-green-os { + label = "nas4220b:green:os"; + /* Conflict with TVC */ + gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ + <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ + #address-cells = <1>; + #size-cells = <0>; + + /* Realtek RTL8211B */ + phy0: ethernet-phy@1 { + reg = <1>; + device_type = "ethernet-phy"; + }; + }; + + soc { + flash@30000000 { + status = "okay"; + /* 16MB of flash */ + reg = <0x30000000 0x01000000>; + + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0xfe0000 */ + fis-index-block = <0x7f>; + }; + }; + + syscon: syscon@40000000 { + pinctrl { + gpio0_default_pins: pinctrl-gpio0 { + mux { + function = "gpio0"; + groups = + "gpio0egrp", + /* Used by MDIO */ + "gpio0igrp"; + }; + }; + gpio1_default_pins: pinctrl-gpio1 { + mux { + function = "gpio1"; + /* Lines 28-31 used by LEDs and buttons */ + groups = "gpio1dgrp"; + }; + }; + pinctrl-gmii { + mux { + function = "gmii"; + groups = "gmii_gmac0_grp"; + }; + conf0 { + pins = "R8 GMAC0 RXDV", "U11 GMAC1 RXDV"; + skew-delay = <0>; + }; + conf1 { + pins = "T8 GMAC0 RXC"; + skew-delay = <10>; + }; + conf2 { + pins = "T11 GMAC1 RXC"; + skew-delay = <15>; + }; + conf3 { + pins = "P8 GMAC0 TXEN", "V11 GMAC1 TXEN"; + skew-delay = <7>; + }; + conf4 { + pins = "V7 GMAC0 TXC", "P10 GMAC1 TXC"; + skew-delay = <10>; + }; + conf5 { + /* The data lines all have default skew */ + pins = "U8 GMAC0 RXD0", "V8 GMAC0 RXD1", + "P9 GMAC0 RXD2", "R9 GMAC0 RXD3", + "R11 GMAC1 RXD0", "P11 GMAC1 RXD1", + "V12 GMAC1 RXD2", "U12 GMAC1 RXD3", + "R10 GMAC1 TXD0", "T10 GMAC1 TXD1", + "U10 GMAC1 TXD2", "V10 GMAC1 TXD3"; + skew-delay = <7>; + }; + conf6 { + pins = "U7 GMAC0 TXD0", "T7 GMAC0 TXD1", + "R7 GMAC0 TXD2", "P7 GMAC0 TXD3"; + skew-delay = <5>; + }; + /* Set up drive strength on GMAC0 to 16 mA */ + conf7 { + groups = "gmii_gmac0_grp"; + drive-strength = <16>; + }; + }; + }; + }; + + sata: sata@46000000 { + cortina,gemini-ata-muxmode = <0>; + cortina,gemini-enable-sata-bridge; + status = "okay"; + }; + + gpio0: gpio@4d000000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_default_pins>; + }; + + gpio1: gpio@4e000000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio1_default_pins>; + }; + + ethernet@60000000 { + status = "okay"; + + ethernet-port@0 { + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + ethernet-port@1 { + /* Not used in this platform */ + }; + }; + + ide@63000000 { + status = "okay"; + }; + + ide@63400000 { + status = "okay"; + }; + + usb@68000000 { + status = "okay"; + }; + + usb@69000000 { + status = "okay"; + }; + }; +}; From dce8e0cb88fb12d068459b75f299ff2242172257 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 28 Feb 2026 01:05:48 +0100 Subject: [PATCH 450/665] ARM: dts: gemini: Correct the RUT1xx Fix two problems with the RUT1xx device tree: - The memory is 32MB not 128MB - The console is 19200 BPS - Activate the PCI - Disable the unused USB ports Signed-off-by: Linus Walleij --- arch/arm/boot/dts/gemini/gemini-rut1xx.dts | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/gemini/gemini-rut1xx.dts b/arch/arm/boot/dts/gemini/gemini-rut1xx.dts index 0ebda4efd9d0..4bdf86bd7c23 100644 --- a/arch/arm/boot/dts/gemini/gemini-rut1xx.dts +++ b/arch/arm/boot/dts/gemini/gemini-rut1xx.dts @@ -14,13 +14,13 @@ / { #address-cells = <1>; #size-cells = <1>; - memory@0 { /* 128 MB */ + memory@0 { /* 32 MB */ device_type = "memory"; - reg = <0x00000000 0x8000000>; + reg = <0x00000000 0x2000000>; }; chosen { - bootargs = "console=ttyS0,115200n8"; + bootargs = "console=ttyS0,19200n8"; stdout-path = &uart0; }; @@ -113,6 +113,10 @@ gpio1: gpio@4e000000 { pinctrl-0 = <&gpio1_default_pins>; }; + pci@50000000 { + status = "okay"; + }; + ethernet@60000000 { status = "okay"; @@ -124,13 +128,5 @@ ethernet-port@1 { /* Not used in this platform */ }; }; - - usb@68000000 { - status = "okay"; - }; - - usb@69000000 { - status = "okay"; - }; }; }; From 2fcb272b0e6d60b3d0de7f7af9e652ea9514802d Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 17 Apr 2026 15:06:43 +0200 Subject: [PATCH 451/665] dt-bindings: reserved-memory: Change maintainer for BPMP SHMEM Peter sadly passed away a while ago, so change the maintainers for BPMP SHMEM to Jon and myself. Suggested-by: Geert Uytterhoeven Acked-by: Conor Dooley Signed-off-by: Thierry Reding --- .../bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml b/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml index 4380f622f9a9..6efadc5f8078 100644 --- a/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml +++ b/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Tegra CPU-NS - BPMP IPC reserved memory maintainers: - - Peter De Schrijver + - Thierry Reding + - Jonathan Hunter description: | Define a memory region used for communication between CPU-NS and BPMP. From 00b5b4e5d3c235950a80a7c5ca9297233640cbe9 Mon Sep 17 00:00:00 2001 From: Diogo Ivo Date: Thu, 14 May 2026 16:47:22 +0200 Subject: [PATCH 452/665] arm64: tegra: Mark MAX77620 as system power controller on Smaug Register the MAX77620 PMIC as the system power controller on Pixel C so the driver can install its sys-off handler. This allows the PMIC poweroff sequence to override the non-working PSCI SYSTEM_OFF implementation on this platform. Signed-off-by: Diogo Ivo Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index f0b8c2c80aa5..1791b47f0a73 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1467,6 +1467,8 @@ pmic: pmic@3c { gpio-controller; #gpio-cells = <2>; + system-power-controller; + pinctrl-names = "default"; pinctrl-0 = <&max77620_default>; From 1f1471284e9b5c2317b4dd8710270aa33c2fd2fe Mon Sep 17 00:00:00 2001 From: Prathamesh Shete Date: Mon, 18 May 2026 10:14:19 +0000 Subject: [PATCH 453/665] dt-bindings: tegra: pmc: Add Tegra238 compatible The PMC found on Tegra238 is similar to the version in earlier chips but some of the register offsets and bitfields differ, so add a specific compatible string for this new variant. Signed-off-by: Prathamesh Shete Acked-by: Conor Dooley Signed-off-by: Thierry Reding --- .../devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml index dcd1c5376507..dd1f637e4175 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml @@ -16,6 +16,7 @@ properties: - nvidia,tegra186-pmc - nvidia,tegra194-pmc - nvidia,tegra234-pmc + - nvidia,tegra238-pmc - nvidia,tegra264-pmc reg: @@ -76,6 +77,7 @@ allOf: contains: enum: - nvidia,tegra234-pmc + - nvidia,tegra238-pmc - nvidia,tegra264-pmc then: properties: From bba8eefb56480c7b06a25e99632b1b6510a25473 Mon Sep 17 00:00:00 2001 From: Manikanta Maddireddy Date: Fri, 15 May 2026 12:37:53 +0530 Subject: [PATCH 454/665] arm64: tegra: Fix aspm-l1-entry-delay-ns L1 latency cells The Tegra194 PCIe driver converts aspm-l1-entry-delay-ns to whole ms with ceiling division, then derives the Synopsys DesignWare PORT_AFR L1 entrance latency encoding as min(order_base_2(us), 7). The nanosecond values from the Fixes tag below round up to 4, 8, and 16 us, selecting PORT_AFR L1 entrance latency codes 2, 3, and 4 respectively. Raise the programmed latency so the PORT_AFR codes are 3 / 4 / 5 (8 / 16 / 32 us buckets) instead of 2 / 3 / 4 (4 / 8 / 16 us). - tegra194.dtsi: 4000 -> 8000 ns (all listed controllers) - tegra234.dtsi: 8000 -> 16000 ns (Root Port), 16000 -> 32000 ns (Endpoint) Fixes: d60ed99f1c9e ("arm64: tegra: Add aspm-l1-entry-delay-ns to PCIe nodes") Signed-off-by: Manikanta Maddireddy Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 18 ++++++------- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 32 ++++++++++++------------ 2 files changed, 25 insertions(+), 25 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 1d659454a6f9..7bbf0e892724 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2382,7 +2382,7 @@ pcie@14100000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <4000>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -2435,7 +2435,7 @@ pcie@14120000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <4000>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -2488,7 +2488,7 @@ pcie@14140000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <4000>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -2541,7 +2541,7 @@ pcie@14160000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <4000>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -2587,7 +2587,7 @@ pcie-ep@14160000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <4000>; + aspm-l1-entry-delay-ns = <8000>; interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; @@ -2634,7 +2634,7 @@ pcie@14180000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <4000>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -2680,7 +2680,7 @@ pcie-ep@14180000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <4000>; + aspm-l1-entry-delay-ns = <8000>; interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; @@ -2730,7 +2730,7 @@ pcie@141a0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <4000>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -2779,7 +2779,7 @@ pcie-ep@141a0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <4000>; + aspm-l1-entry-delay-ns = <8000>; interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 75bb9a0ad027..8e0c51e496e2 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -4532,7 +4532,7 @@ pcie@140a0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <8000>; + aspm-l1-entry-delay-ns = <16000>; bus-range = <0x0 0xff>; @@ -4587,7 +4587,7 @@ pcie@140c0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <8000>; + aspm-l1-entry-delay-ns = <16000>; bus-range = <0x0 0xff>; @@ -4642,7 +4642,7 @@ pcie@140e0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <8000>; + aspm-l1-entry-delay-ns = <16000>; bus-range = <0x0 0xff>; @@ -4689,7 +4689,7 @@ pcie-ep@140e0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <16000>; + aspm-l1-entry-delay-ns = <32000>; interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; @@ -4738,7 +4738,7 @@ pcie@14100000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <8000>; + aspm-l1-entry-delay-ns = <16000>; bus-range = <0x0 0xff>; @@ -4793,7 +4793,7 @@ pcie@14120000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <8000>; + aspm-l1-entry-delay-ns = <16000>; bus-range = <0x0 0xff>; @@ -4848,7 +4848,7 @@ pcie@14140000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <8000>; + aspm-l1-entry-delay-ns = <16000>; bus-range = <0x0 0xff>; @@ -4903,7 +4903,7 @@ pcie@14160000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <8000>; + aspm-l1-entry-delay-ns = <16000>; bus-range = <0x0 0xff>; @@ -4945,7 +4945,7 @@ pcie-ep@14160000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <16000>; + aspm-l1-entry-delay-ns = <32000>; interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; @@ -4992,7 +4992,7 @@ pcie@14180000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <8000>; + aspm-l1-entry-delay-ns = <16000>; bus-range = <0x0 0xff>; @@ -5047,7 +5047,7 @@ pcie@141a0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <8000>; + aspm-l1-entry-delay-ns = <16000>; bus-range = <0x0 0xff>; @@ -5094,7 +5094,7 @@ pcie-ep@141a0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <16000>; + aspm-l1-entry-delay-ns = <32000>; interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; @@ -5143,7 +5143,7 @@ pcie@141c0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <8000>; + aspm-l1-entry-delay-ns = <16000>; bus-range = <0x0 0xff>; @@ -5190,7 +5190,7 @@ pcie-ep@141c0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <16000>; + aspm-l1-entry-delay-ns = <32000>; interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; @@ -5239,7 +5239,7 @@ pcie@141e0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <8000>; + aspm-l1-entry-delay-ns = <16000>; bus-range = <0x0 0xff>; @@ -5286,7 +5286,7 @@ pcie-ep@141e0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <16000>; + aspm-l1-entry-delay-ns = <32000>; interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; From 1fe27b10dc97c85821dfae1e4e6f9db4472287aa Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Tue, 28 Apr 2026 13:06:55 -0700 Subject: [PATCH 455/665] ARM: tegra: Add #{address,size}-cells to Chromium-based /firmware Chromium/Depthcharge bootloaders may dynamically add a few device nodes to a system's DTB under a /firmware node. A typical DT looks something like the following: / { firmware { ranges; coreboot { compatible = "coreboot"; reg = <...>; ...; }; }; }; Notably, the /firmware node has an empty 'ranges', but does not have address/size-cells. Commit 6e5773d52f4a ("of/address: Fix WARN when attempting translating non-translatable addresses") started requiring #address-cells for a device's parent if we want to use the reg resource in a device node. This leads to errors like the following: [ 7.763870] coreboot_table firmware:coreboot: probe with driver coreboot_table failed with error -22 Add appropriate #{address,size}-cells to work around the problem. Note that Google has also patched the Depthcharge bootloader source to add {address,size}-cells [1], but bootloader updates are typically delivered only via Google OS updates. Not all users install Google software updates, and even if they do, Google may not produce updated binaries for all/older devices. [1] https://lore.kernel.org/all/20241209092809.GA3246424@google.com/ https://crrev.com/c/6051580 ("coreboot: Insert #address-cells and #size-cells for firmware node") Closes: https://lore.kernel.org/all/aeKlYzTiL0OB1y3g@google.com/ Fixes: 6e5773d52f4a ("of/address: Fix WARN when attempting translating non-translatable addresses") Signed-off-by: Brian Norris Reviewed-by: Douglas Anderson Signed-off-by: Thierry Reding --- arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi | 5 +++++ arch/arm/boot/dts/nvidia/tegra124-venice2.dts | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi b/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi index 974c76f007db..89a749cb8933 100644 --- a/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi @@ -14,6 +14,11 @@ chosen { stdout-path = "serial0:115200n8"; }; + firmware { + #address-cells = <1>; + #size-cells = <1>; + }; + /* * Note that recent version of the device tree compiler (starting with * version 1.4.2) warn about this node containing a reg property, but diff --git a/arch/arm/boot/dts/nvidia/tegra124-venice2.dts b/arch/arm/boot/dts/nvidia/tegra124-venice2.dts index df98dc2a67b8..059ee6c5b13c 100644 --- a/arch/arm/boot/dts/nvidia/tegra124-venice2.dts +++ b/arch/arm/boot/dts/nvidia/tegra124-venice2.dts @@ -18,6 +18,11 @@ chosen { stdout-path = "serial0:115200n8"; }; + firmware { + #address-cells = <1>; + #size-cells = <1>; + }; + memory@80000000 { reg = <0x0 0x80000000 0x0 0x80000000>; }; From bdc80b3246f18f8f9f94af78c3c9f3c22c62fad3 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 27 Apr 2026 10:03:10 +0300 Subject: [PATCH 456/665] ARM: tegra: Add EMC OPP and ICC properties to Tegra114 EMC and ACTMON device-tree nodes Add EMC OPP tables and interconnect paths that will be used for dynamic memory bandwidth scaling based on memory utilization statistics. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen Signed-off-by: Thierry Reding --- .../dts/nvidia/tegra114-peripherals-opp.dtsi | 164 ++++++++++++++++++ arch/arm/boot/dts/nvidia/tegra114.dtsi | 9 + 2 files changed, 173 insertions(+) create mode 100644 arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi diff --git a/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi b/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi new file mode 100644 index 000000000000..b40a1c24abab --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + emc_icc_dvfs_opp_table: opp-table-emc { + compatible = "operating-points-v2"; + + opp-12750000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x000F>; + }; + + opp-20400000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x000F>; + }; + + opp-40800000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x000F>; + }; + + opp-68000000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x000F>; + }; + + opp-102000000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x000F>; + }; + + opp-204000000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x000F>; + opp-suspend; + }; + + opp-312000000-1000 { + opp-microvolt = <1000000 1000000 1390000>; + opp-hz = /bits/ 64 <312000000>; + opp-supported-hw = <0x000F>; + }; + + opp-408000000-1000 { + opp-microvolt = <1000000 1000000 1390000>; + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x000F>; + }; + + /* + * T40X can work with 1050mV for 528MHz but T40T which is + * in the same group as T40X requires 1100mV. If there will + * be enough data that T40T can work reliably with 1050mV + * for 528MHz then voltage for 528MHz opp can be lowered. + * T40S should remain with 1100mV for 528MHz opp. + */ + opp-528000000-1100 { + opp-microvolt = <1100000 1100000 1390000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x000F>; + }; + + opp-624000000-1100 { + opp-microvolt = <1100000 1100000 1390000>; + opp-hz = /bits/ 64 <624000000>; + opp-supported-hw = <0x000F>; + }; + + opp-792000000-1100 { + opp-microvolt = <1100000 1100000 1390000>; + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x000F>; + }; + + opp-900000000-1200 { + opp-microvolt = <1200000 1200000 1390000>; + opp-hz = /bits/ 64 <900000000>; + opp-supported-hw = <0x000E>; + }; + }; + + emc_bw_dfs_opp_table: opp-table-actmon { + compatible = "operating-points-v2"; + + opp-12750000 { + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <204000>; + }; + + opp-20400000 { + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <326400>; + }; + + opp-40800000 { + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <652800>; + }; + + opp-68000000 { + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <1088000>; + }; + + opp-102000000 { + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <1632000>; + }; + + opp-204000000 { + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <3264000>; + opp-suspend; + }; + + opp-312000000 { + opp-hz = /bits/ 64 <312000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <4992000>; + }; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <6528000>; + }; + + opp-528000000 { + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <8448000>; + }; + + opp-624000000 { + opp-hz = /bits/ 64 <624000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <9984000>; + }; + + opp-792000000 { + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <12672000>; + }; + + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-supported-hw = <0x000E>; + opp-peak-kBps = <14400000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi index 7e8f90d33935..6c2b79b35938 100644 --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi @@ -8,6 +8,8 @@ #include #include +#include "tegra114-peripherals-opp.dtsi" + / { compatible = "nvidia,tegra114"; interrupt-parent = <&lic>; @@ -323,6 +325,9 @@ actmon: actmon@6000c800 { clock-names = "actmon", "emc"; resets = <&tegra_car TEGRA114_CLK_ACTMON>; reset-names = "actmon"; + operating-points-v2 = <&emc_bw_dfs_opp_table>; + interconnects = <&mc TEGRA114_MC_MPCORER &emc>; + interconnect-names = "cpu-read"; #cooling-cells = <2>; }; @@ -655,6 +660,7 @@ mc: memory-controller@70019000 { #reset-cells = <1>; #iommu-cells = <1>; + #interconnect-cells = <1>; }; emc: external-memory-controller@7001b000 { @@ -665,6 +671,9 @@ emc: external-memory-controller@7001b000 { clock-names = "emc"; nvidia,memory-controller = <&mc>; + operating-points-v2 = <&emc_icc_dvfs_opp_table>; + + #interconnect-cells = <0>; }; hda@70030000 { From 88627b26bad4a4486f75fbcf6fb5ee99ded27704 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 27 Apr 2026 10:03:11 +0300 Subject: [PATCH 457/665] ARM: tegra: Add DC interconnections for Tegra114 Add DC interconnections to Tegra114 device tree to reflect connections between MC, EMC and DC. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen Signed-off-by: Thierry Reding --- arch/arm/boot/dts/nvidia/tegra114.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi index 6c2b79b35938..f46406b06a07 100644 --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi @@ -125,6 +125,17 @@ dc@54200000 { nvidia,head = <0>; + interconnects = <&mc TEGRA114_MC_DISPLAY0A &emc>, + <&mc TEGRA114_MC_DISPLAY0B &emc>, + <&mc TEGRA114_MC_DISPLAY1B &emc>, + <&mc TEGRA114_MC_DISPLAY0C &emc>, + <&mc TEGRA114_MC_DISPLAYHC &emc>; + interconnect-names = "wina", + "winb", + "winb-vfilter", + "winc", + "cursor"; + rgb { status = "disabled"; }; @@ -144,6 +155,17 @@ dc@54240000 { nvidia,head = <1>; + interconnects = <&mc TEGRA114_MC_DISPLAY0AB &emc>, + <&mc TEGRA114_MC_DISPLAY0BB &emc>, + <&mc TEGRA114_MC_DISPLAY1BB &emc>, + <&mc TEGRA114_MC_DISPLAY0CB &emc>, + <&mc TEGRA114_MC_DISPLAYHCB &emc>; + interconnect-names = "wina", + "winb", + "winb-vfilter", + "winc", + "cursor"; + rgb { status = "disabled"; }; From 4cc90d4c043e73a88f28145a6713d336506da53f Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 27 Apr 2026 10:03:12 +0300 Subject: [PATCH 458/665] ARM: tegra: Configure Tegra114 power domains Add power domains found in Tegra114 and configure operating-points-v2 for supported devices accordingly. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen Signed-off-by: Thierry Reding --- .../dts/nvidia/tegra114-peripherals-opp.dtsi | 1275 +++++++++++++++++ arch/arm/boot/dts/nvidia/tegra114.dtsi | 126 ++ 2 files changed, 1401 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi b/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi index b40a1c24abab..bab6122dba48 100644 --- a/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi @@ -1,6 +1,76 @@ // SPDX-License-Identifier: GPL-2.0 / { + core_opp_table: opp-table-core { + compatible = "operating-points-v2"; + opp-shared; + + core_opp_900: opp-900000 { + opp-microvolt = <900000 900000 1390000>; + opp-level = <900000>; + }; + + core_opp_950: opp-950000 { + opp-microvolt = <950000 950000 1390000>; + opp-level = <950000>; + }; + + core_opp_1000: opp-1000000 { + opp-microvolt = <1000000 1000000 1390000>; + opp-level = <1000000>; + }; + + core_opp_1050: opp-1050000 { + opp-microvolt = <1050000 1050000 1390000>; + opp-level = <1050000>; + }; + + core_opp_1100: opp-1100000 { + opp-microvolt = <1100000 1100000 1390000>; + opp-level = <1100000>; + }; + + core_opp_1120: opp-1120000 { + opp-microvolt = <1120000 1120000 1390000>; + opp-level = <1120000>; + }; + + core_opp_1150: opp-1150000 { + opp-microvolt = <1150000 1150000 1390000>; + opp-level = <1150000>; + }; + + core_opp_1170: opp-1170000 { + opp-microvolt = <1170000 1170000 1390000>; + opp-level = <1170000>; + }; + + core_opp_1200: opp-1200000 { + opp-microvolt = <1200000 1200000 1390000>; + opp-level = <1200000>; + }; + + core_opp_1250: opp-1250000 { + opp-microvolt = <1250000 1250000 1390000>; + opp-level = <1250000>; + }; + + core_opp_1300: opp-1300000 { + opp-microvolt = <1300000 1300000 1390000>; + opp-level = <1300000>; + }; + + core_opp_1350: opp-1350000 { + opp-microvolt = <1350000 1350000 1390000>; + opp-level = <1350000>; + }; + + core_opp_1390: opp-1390000 { + opp-microvolt = <1390000 1390000 1390000>; + opp-level = <1390000>; + }; + }; + emc_icc_dvfs_opp_table: opp-table-emc { compatible = "operating-points-v2"; @@ -8,36 +78,42 @@ opp-12750000-900 { opp-microvolt = <900000 900000 1390000>; opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_900>; }; opp-20400000-900 { opp-microvolt = <900000 900000 1390000>; opp-hz = /bits/ 64 <20400000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_900>; }; opp-40800000-900 { opp-microvolt = <900000 900000 1390000>; opp-hz = /bits/ 64 <40800000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_900>; }; opp-68000000-900 { opp-microvolt = <900000 900000 1390000>; opp-hz = /bits/ 64 <68000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_900>; }; opp-102000000-900 { opp-microvolt = <900000 900000 1390000>; opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_900>; }; opp-204000000-900 { opp-microvolt = <900000 900000 1390000>; opp-hz = /bits/ 64 <204000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_900>; opp-suspend; }; @@ -45,12 +121,14 @@ opp-312000000-1000 { opp-microvolt = <1000000 1000000 1390000>; opp-hz = /bits/ 64 <312000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; }; opp-408000000-1000 { opp-microvolt = <1000000 1000000 1390000>; opp-hz = /bits/ 64 <408000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; }; /* @@ -64,24 +142,28 @@ opp-528000000-1100 { opp-microvolt = <1100000 1100000 1390000>; opp-hz = /bits/ 64 <528000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; }; opp-624000000-1100 { opp-microvolt = <1100000 1100000 1390000>; opp-hz = /bits/ 64 <624000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; }; opp-792000000-1100 { opp-microvolt = <1100000 1100000 1390000>; opp-hz = /bits/ 64 <792000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; }; opp-900000000-1200 { opp-microvolt = <1200000 1200000 1390000>; opp-hz = /bits/ 64 <900000000>; opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1200>; }; }; @@ -161,4 +243,1197 @@ opp-900000000 { opp-peak-kBps = <14400000>; }; }; + + vi_dvfs_opp_table: opp-table-vi { + compatible = "operating-points-v2"; + + opp-114000000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <114000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_900>; + }; + + opp-216000000-950 { + opp-microvolt = <950000 950000 1390000>; + opp-hz = /bits/ 64 <216000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-240000000-1000 { + opp-microvolt = <1000000 1000000 1390000>; + opp-hz = /bits/ 64 <240000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-312000000-1050 { + opp-microvolt = <1050000 1050000 1390000>; + opp-hz = /bits/ 64 <312000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1050>; + }; + + opp-372000000-1100 { + opp-microvolt = <1100000 1100000 1390000>; + opp-hz = /bits/ 64 <372000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp-408000000-1050 { + opp-microvolt = <1050000 1050000 1390000>; + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1050>; + }; + + opp-408000000-1120 { + opp-microvolt = <1120000 1120000 1390000>; + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1120>; + }; + }; + + epp_dvfs_opp_table: opp-table-epp { + compatible = "operating-points-v2"; + + opp-192000000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <192000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_900>; + }; + + opp-240000000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <240000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_900>; + }; + + opp-228000000-950 { + opp-microvolt = <950000 950000 1390000>; + opp-hz = /bits/ 64 <228000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_950>; + }; + + opp-300000000-950 { + opp-microvolt = <950000 950000 1390000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_950>; + }; + + opp-300000000-1000 { + opp-microvolt = <1000000 1000000 1390000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-384000000-1000 { + opp-microvolt = <1000000 1000000 1390000>; + opp-hz = /bits/ 64 <384000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1000>; + }; + + opp-396000000-1050 { + opp-microvolt = <1050000 1050000 1390000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1050>; + }; + + opp-468000000-1050 { + opp-microvolt = <1050000 1050000 1390000>; + opp-hz = /bits/ 64 <468000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1050>; + }; + + opp-492000000-1100 { + opp-microvolt = <1100000 1100000 1390000>; + opp-hz = /bits/ 64 <492000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp-528000000-1100 { + opp-microvolt = <1100000 1100000 1390000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1100>; + }; + + opp-516000000-1120 { + opp-microvolt = <1120000 1120000 1390000>; + opp-hz = /bits/ 64 <516000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1120>; + }; + + opp-564000000-1120 { + opp-microvolt = <1120000 1120000 1390000>; + opp-hz = /bits/ 64 <564000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1120>; + }; + + opp-552000000-1170 { + opp-microvolt = <1170000 1170000 1390000>; + opp-hz = /bits/ 64 <552000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1170>; + }; + + opp-600000000-1170 { + opp-microvolt = <1170000 1170000 1390000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1170>; + }; + + opp-600000000-1250 { + opp-microvolt = <1250000 1250000 1390000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1250>; + }; + + opp-636000000-1200 { + opp-microvolt = <1200000 1200000 1390000>; + opp-hz = /bits/ 64 <636000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1200>; + }; + + opp-672000000-1250 { + opp-microvolt = <1250000 1250000 1390000>; + opp-hz = /bits/ 64 <672000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1250>; + }; + + opp-828000000-1390 { + opp-microvolt = <1390000 1390000 1390000>; + opp-hz = /bits/ 64 <828000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1390>; + }; + }; + + gr2d_dvfs_opp_table: opp-table-gr2d { + compatible = "operating-points-v2"; + + opp-192000000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <192000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_900>; + }; + + opp-240000000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <240000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_900>; + }; + + opp-228000000-950 { + opp-microvolt = <950000 950000 1390000>; + opp-hz = /bits/ 64 <228000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_950>; + }; + + opp-300000000-950 { + opp-microvolt = <950000 950000 1390000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_950>; + }; + + opp-300000000-1000 { + opp-microvolt = <1000000 1000000 1390000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-384000000-1000 { + opp-microvolt = <1000000 1000000 1390000>; + opp-hz = /bits/ 64 <384000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1000>; + }; + + opp-396000000-1050 { + opp-microvolt = <1050000 1050000 1390000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1050>; + }; + + opp-468000000-1050 { + opp-microvolt = <1050000 1050000 1390000>; + opp-hz = /bits/ 64 <468000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1050>; + }; + + opp-492000000-1100 { + opp-microvolt = <1100000 1100000 1390000>; + opp-hz = /bits/ 64 <492000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp-528000000-1100 { + opp-microvolt = <1100000 1100000 1390000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1100>; + }; + + opp-516000000-1120 { + opp-microvolt = <1120000 1120000 1390000>; + opp-hz = /bits/ 64 <516000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1120>; + }; + + opp-564000000-1120 { + opp-microvolt = <1120000 1120000 1390000>; + opp-hz = /bits/ 64 <564000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1120>; + }; + + opp-552000000-1170 { + opp-microvolt = <1170000 1170000 1390000>; + opp-hz = /bits/ 64 <552000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1170>; + }; + + opp-600000000-1170 { + opp-microvolt = <1170000 1170000 1390000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1170>; + }; + + opp-600000000-1250 { + opp-microvolt = <1250000 1250000 1390000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1250>; + }; + + opp-636000000-1200 { + opp-microvolt = <1200000 1200000 1390000>; + opp-hz = /bits/ 64 <636000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1200>; + }; + + opp-672000000-1250 { + opp-microvolt = <1250000 1250000 1390000>; + opp-hz = /bits/ 64 <672000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1250>; + }; + + opp-828000000-1390 { + opp-microvolt = <1390000 1390000 1390000>; + opp-hz = /bits/ 64 <828000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1390>; + }; + }; + + gr3d_dvfs_opp_table: opp-table-gr3d { + compatible = "operating-points-v2"; + + opp-192000000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <192000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_900>; + }; + + opp-240000000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <240000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_900>; + }; + + opp-228000000-950 { + opp-microvolt = <950000 950000 1390000>; + opp-hz = /bits/ 64 <228000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_950>; + }; + + opp-300000000-950 { + opp-microvolt = <950000 950000 1390000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_950>; + }; + + opp-300000000-1000 { + opp-microvolt = <1000000 1000000 1390000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-384000000-1000 { + opp-microvolt = <1000000 1000000 1390000>; + opp-hz = /bits/ 64 <384000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1000>; + }; + + opp-396000000-1050 { + opp-microvolt = <1050000 1050000 1390000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1050>; + }; + + opp-468000000-1050 { + opp-microvolt = <1050000 1050000 1390000>; + opp-hz = /bits/ 64 <468000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1050>; + }; + + opp-492000000-1100 { + opp-microvolt = <1100000 1100000 1390000>; + opp-hz = /bits/ 64 <492000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp-528000000-1100 { + opp-microvolt = <1100000 1100000 1390000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1100>; + }; + + opp-516000000-1120 { + opp-microvolt = <1120000 1120000 1390000>; + opp-hz = /bits/ 64 <516000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1120>; + }; + + opp-564000000-1120 { + opp-microvolt = <1120000 1120000 1390000>; + opp-hz = /bits/ 64 <564000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1120>; + }; + + opp-552000000-1170 { + opp-microvolt = <1170000 1170000 1390000>; + opp-hz = /bits/ 64 <552000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1170>; + }; + + opp-600000000-1170 { + opp-microvolt = <1170000 1170000 1390000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1170>; + }; + + opp-600000000-1250 { + opp-microvolt = <1250000 1250000 1390000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1250>; + }; + + opp-636000000-1200 { + opp-microvolt = <1200000 1200000 1390000>; + opp-hz = /bits/ 64 <636000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1200>; + }; + + opp-672000000-1250 { + opp-microvolt = <1250000 1250000 1390000>; + opp-hz = /bits/ 64 <672000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1250>; + }; + + opp-828000000-1390 { + opp-microvolt = <1390000 1390000 1390000>; + opp-hz = /bits/ 64 <828000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1390>; + }; + }; + + msenc_dvfs_opp_table: opp-table-msenc { + compatible = "operating-points-v2"; + + opp-144000000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <144000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_900>; + }; + + opp-182000000-950 { + opp-microvolt = <950000 950000 1390000>; + opp-hz = /bits/ 64 <182000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_950>; + }; + + opp-204000000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_900>; + }; + + opp-240000000-1000 { + opp-microvolt = <1000000 1000000 1390000>; + opp-hz = /bits/ 64 <240000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-252000000-950 { + opp-microvolt = <950000 950000 1390000>; + opp-hz = /bits/ 64 <252000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_950>; + }; + + opp-312000000-1050 { + opp-microvolt = <1050000 1050000 1390000>; + opp-hz = /bits/ 64 <312000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1050>; + }; + + opp-324000000-1000 { + opp-microvolt = <1000000 1000000 1390000>; + opp-hz = /bits/ 64 <324000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1000>; + }; + + opp-384000000-1100 { + opp-microvolt = <1100000 1100000 1390000>; + opp-hz = /bits/ 64 <384000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp-408000000-1050 { + opp-microvolt = <1050000 1050000 1390000>; + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1050>; + }; + + opp-432000000-1120 { + opp-microvolt = <1120000 1120000 1390000>; + opp-hz = /bits/ 64 <432000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1120>; + }; + + opp-456000000-1100 { + opp-microvolt = <1100000 1100000 1390000>; + opp-hz = /bits/ 64 <456000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1100>; + }; + + opp-480000000-1120 { + opp-microvolt = <1120000 1120000 1390000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1120>; + }; + + opp-480000000-1170 { + opp-microvolt = <1170000 1170000 1390000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1170>; + }; + }; + + tsec_dvfs_opp_table: opp-table-tsec { + compatible = "operating-points-v2"; + + opp-144000000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <144000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_900>; + }; + + opp-182000000-950 { + opp-microvolt = <950000 950000 1390000>; + opp-hz = /bits/ 64 <182000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_950>; + }; + + opp-204000000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_900>; + }; + + opp-240000000-1000 { + opp-microvolt = <1000000 1000000 1390000>; + opp-hz = /bits/ 64 <240000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-252000000-950 { + opp-microvolt = <950000 950000 1390000>; + opp-hz = /bits/ 64 <252000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_950>; + }; + + opp-312000000-1050 { + opp-microvolt = <1050000 1050000 1390000>; + opp-hz = /bits/ 64 <312000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1050>; + }; + + opp-324000000-1000 { + opp-microvolt = <1000000 1000000 1390000>; + opp-hz = /bits/ 64 <324000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1000>; + }; + + opp-384000000-1100 { + opp-microvolt = <1100000 1100000 1390000>; + opp-hz = /bits/ 64 <384000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp-408000000-1050 { + opp-microvolt = <1050000 1050000 1390000>; + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1050>; + }; + + opp-432000000-1120 { + opp-microvolt = <1120000 1120000 1390000>; + opp-hz = /bits/ 64 <432000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1120>; + }; + + opp-456000000-1100 { + opp-microvolt = <1100000 1100000 1390000>; + opp-hz = /bits/ 64 <456000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1100>; + }; + + opp-480000000-1120 { + opp-microvolt = <1120000 1120000 1390000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1120>; + }; + + opp-480000000-1170 { + opp-microvolt = <1170000 1170000 1390000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1170>; + }; + }; + + vde_dvfs_opp_table: opp-table-vde { + compatible = "operating-points-v2"; + + opp-144000000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <144000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_900>; + }; + + opp-182000000-950 { + opp-microvolt = <950000 950000 1390000>; + opp-hz = /bits/ 64 <182000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_950>; + }; + + opp-204000000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_900>; + }; + + opp-240000000-1000 { + opp-microvolt = <1000000 1000000 1390000>; + opp-hz = /bits/ 64 <240000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-252000000-950 { + opp-microvolt = <950000 950000 1390000>; + opp-hz = /bits/ 64 <252000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_950>; + }; + + opp-312000000-1050 { + opp-microvolt = <1050000 1050000 1390000>; + opp-hz = /bits/ 64 <312000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1050>; + }; + + opp-324000000-1000 { + opp-microvolt = <1000000 1000000 1390000>; + opp-hz = /bits/ 64 <324000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1000>; + }; + + opp-384000000-1100 { + opp-microvolt = <1100000 1100000 1390000>; + opp-hz = /bits/ 64 <384000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp-408000000-1050 { + opp-microvolt = <1050000 1050000 1390000>; + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1050>; + }; + + opp-432000000-1120 { + opp-microvolt = <1120000 1120000 1390000>; + opp-hz = /bits/ 64 <432000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1120>; + }; + + opp-456000000-1100 { + opp-microvolt = <1100000 1100000 1390000>; + opp-hz = /bits/ 64 <456000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1100>; + }; + + opp-480000000-1120 { + opp-microvolt = <1120000 1120000 1390000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1120>; + }; + + opp-480000000-1170 { + opp-microvolt = <1170000 1170000 1390000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1170>; + }; + }; + + host1x_dvfs_opp_table: opp-table-host1x { + compatible = "operating-points-v2"; + + opp-144000000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <144000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_900>; + }; + + opp-180000000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <180000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_900>; + }; + + opp-188000000-950 { + opp-microvolt = <950000 950000 1390000>; + opp-hz = /bits/ 64 <188000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_950>; + }; + + opp-228000000-950 { + opp-microvolt = <950000 950000 1390000>; + opp-hz = /bits/ 64 <228000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_950>; + }; + + opp-240000000-1000 { + opp-microvolt = <1000000 1000000 1390000>; + opp-hz = /bits/ 64 <240000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-276000000-1000 { + opp-microvolt = <1000000 1000000 1390000>; + opp-hz = /bits/ 64 <276000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1000>; + }; + + opp-276000000-1050 { + opp-microvolt = <1050000 1050000 1390000>; + opp-hz = /bits/ 64 <276000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1050>; + }; + + opp-324000000-1100 { + opp-microvolt = <1100000 1100000 1390000>; + opp-hz = /bits/ 64 <324000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp-336000000-1050 { + opp-microvolt = <1050000 1050000 1390000>; + opp-hz = /bits/ 64 <336000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1050>; + }; + + opp-336000000-1120 { + opp-microvolt = <1120000 1120000 1390000>; + opp-hz = /bits/ 64 <336000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1120>; + }; + + opp-372000000-1100 { + opp-microvolt = <1100000 1100000 1390000>; + opp-hz = /bits/ 64 <372000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1100>; + }; + + opp-384000000-1120 { + opp-microvolt = <1120000 1120000 1390000>; + opp-hz = /bits/ 64 <384000000>; + opp-supported-hw = <0x000E>; + required-opps = <&core_opp_1120>; + }; + }; + + pll_m_dvfs_opp_table: opp-table-pllm { + compatible = "operating-points-v2"; + + opp-800000000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_900>; + }; + + opp-1066000000-1000 { + opp-microvolt = <1000000 1000000 1390000>; + opp-hz = /bits/ 64 <1066000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + pll_c_dvfs_opp_table: opp-table-pllc { + compatible = "operating-points-v2"; + + opp-800000000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_900>; + }; + + opp-1066000000-1000 { + opp-microvolt = <1000000 1000000 1390000>; + opp-hz = /bits/ 64 <1066000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + pll_c2_dvfs_opp_table: opp-table-pllc2 { + compatible = "operating-points-v2"; + + opp-800000000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_900>; + }; + + opp-1066000000-1000 { + opp-microvolt = <1000000 1000000 1390000>; + opp-hz = /bits/ 64 <1066000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + pll_c3_dvfs_opp_table: opp-table-pllc3 { + compatible = "operating-points-v2"; + + opp-800000000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_900>; + }; + + opp-1066000000-1000 { + opp-microvolt = <1000000 1000000 1390000>; + opp-hz = /bits/ 64 <1066000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + sbc1_dvfs_opp_table: opp-table-sbc1 { + compatible = "operating-points-v2"; + + opp-48000000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <48000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_900>; + }; + + opp-52000000-1100 { + opp-microvolt = <1100000 1100000 1390000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + sbc2_dvfs_opp_table: opp-table-sbc2 { + compatible = "operating-points-v2"; + + opp-48000000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <48000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_900>; + }; + + opp-52000000-1100 { + opp-microvolt = <1100000 1100000 1390000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + sbc3_dvfs_opp_table: opp-table-sbc3 { + compatible = "operating-points-v2"; + + opp-48000000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <48000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_900>; + }; + + opp-52000000-1100 { + opp-microvolt = <1100000 1100000 1390000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + sbc4_dvfs_opp_table: opp-table-sbc4 { + compatible = "operating-points-v2"; + + opp-48000000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <48000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_900>; + }; + + opp-52000000-1100 { + opp-microvolt = <1100000 1100000 1390000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + sbc5_dvfs_opp_table: opp-table-sbc5 { + compatible = "operating-points-v2"; + + opp-48000000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <48000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_900>; + }; + + opp-52000000-1100 { + opp-microvolt = <1100000 1100000 1390000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + sbc6_dvfs_opp_table: opp-table-sbc6 { + compatible = "operating-points-v2"; + + opp-48000000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <48000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_900>; + }; + + opp-52000000-1100 { + opp-microvolt = <1100000 1100000 1390000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + sdmmc1_dvfs_opp_table: opp-table-sdmmc1 { + compatible = "operating-points-v2"; + + opp-81600000-950 { + opp-microvolt = <950000 950000 1390000>; + opp-hz = /bits/ 64 <81600000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-156000000-1120 { + opp-microvolt = <1120000 1120000 1390000>; + opp-hz = /bits/ 64 <156000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1120>; + }; + + opp-204000000-1250 { + opp-microvolt = <1250000 1250000 1390000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1250>; + }; + }; + + sdmmc3_dvfs_opp_table: opp-table-sdmmc3 { + compatible = "operating-points-v2"; + + opp-81600000-950 { + opp-microvolt = <950000 950000 1390000>; + opp-hz = /bits/ 64 <81600000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-156000000-1120 { + opp-microvolt = <1120000 1120000 1390000>; + opp-hz = /bits/ 64 <156000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1120>; + }; + + opp-204000000-1250 { + opp-microvolt = <1250000 1250000 1390000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1250>; + }; + }; + + sdmmc4_dvfs_opp_table: opp-table-sdmmc4 { + compatible = "operating-points-v2"; + + opp-81600000-950 { + opp-microvolt = <950000 950000 1390000>; + opp-hz = /bits/ 64 <81600000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-156000000-1120 { + opp-microvolt = <1120000 1120000 1390000>; + opp-hz = /bits/ 64 <156000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1120>; + }; + + opp-200000000-1250 { + opp-microvolt = <1250000 1250000 1390000>; + opp-hz = /bits/ 64 <200000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1250>; + }; + }; + + hdmi_dvfs_opp_table: opp-table-hdmi { + compatible = "operating-points-v2"; + + opp-148500000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <148500000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_900>; + }; + + opp-297000000-1050 { + opp-microvolt = <1050000 1050000 1390000>; + opp-hz = /bits/ 64 <297000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1050>; + }; + }; + + disp1_dvfs_opp_table: opp-table-disp1 { + compatible = "operating-points-v2"; + + opp-166000000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <166000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_900>; + }; + + opp-297000000-1050 { + opp-microvolt = <1050000 1050000 1390000>; + opp-hz = /bits/ 64 <297000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1050>; + }; + }; + + disp2_dvfs_opp_table: opp-table-disp2 { + compatible = "operating-points-v2"; + + opp-166000000-900 { + opp-microvolt = <900000 900000 1390000>; + opp-hz = /bits/ 64 <166000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_900>; + }; + + opp-297000000-1050 { + opp-microvolt = <1050000 1050000 1390000>; + opp-hz = /bits/ 64 <297000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1050>; + }; + }; + + xusb_falcon_dvfs_opp_table: opp-table-xusb-falcon { + compatible = "operating-points-v2"; + + opp-336000000-950 { + opp-microvolt = <950000 950000 1390000>; + opp-hz = /bits/ 64 <336000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + }; + + xusb_host_dvfs_opp_table: opp-table-xusb-host { + compatible = "operating-points-v2"; + + opp-112000000-950 { + opp-microvolt = <950000 950000 1390000>; + opp-hz = /bits/ 64 <112000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + }; + + xusb_dev_dvfs_opp_table: opp-table-xusb-dev { + compatible = "operating-points-v2"; + + opp-58300000-950 { + opp-microvolt = <950000 950000 1390000>; + opp-hz = /bits/ 64 <58300000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + }; + + xusb_ss_dvfs_opp_table: opp-table-xusb-ss { + compatible = "operating-points-v2"; + + opp-122400000-950 { + opp-microvolt = <950000 950000 1390000>; + opp-hz = /bits/ 64 <122400000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + }; + + xusb_fs_dvfs_opp_table: opp-table-xusb-fs { + compatible = "operating-points-v2"; + + opp-48000000-950 { + opp-microvolt = <950000 950000 1390000>; + opp-hz = /bits/ 64 <48000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + }; + + xusb_hs_dvfs_opp_table: opp-table-xusb-hs { + compatible = "operating-points-v2"; + + opp-61200000-950 { + opp-microvolt = <950000 950000 1390000>; + opp-hz = /bits/ 64 <61200000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + }; + + /* Add usbd, usb2 and usb3 opp tables if needed */ }; diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi index f46406b06a07..a5958f3a965b 100644 --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi @@ -58,6 +58,8 @@ vi@54080000 { clocks = <&tegra_car TEGRA114_CLK_VI>; resets = <&tegra_car 20>; reset-names = "vi"; + power-domains = <&pd_venc>; + operating-points-v2 = <&vi_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_VI>; @@ -71,6 +73,8 @@ epp@540c0000 { clocks = <&tegra_car TEGRA114_CLK_EPP>; resets = <&tegra_car TEGRA114_CLK_EPP>; reset-names = "epp"; + power-domains = <&pd_heg>; + operating-points-v2 = <&epp_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_EPP>; @@ -84,6 +88,7 @@ isp@54100000 { clocks = <&tegra_car TEGRA114_CLK_ISP>; resets = <&tegra_car TEGRA114_CLK_ISP>; reset-names = "isp"; + power-domains = <&pd_venc>; iommus = <&mc TEGRA_SWGROUP_ISP>; @@ -97,6 +102,8 @@ gr2d@54140000 { clocks = <&tegra_car TEGRA114_CLK_GR2D>; resets = <&tegra_car 21>, <&mc TEGRA114_MC_RESET_2D>; reset-names = "2d", "mc"; + power-domains = <&pd_heg>; + operating-points-v2 = <&gr2d_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_G2>; }; @@ -107,6 +114,8 @@ gr3d@54180000 { clocks = <&tegra_car TEGRA114_CLK_GR3D>; resets = <&tegra_car 24>, <&mc TEGRA114_MC_RESET_3D>; reset-names = "3d", "mc"; + power-domains = <&pd_3d>; + operating-points-v2 = <&gr3d_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_NV>; }; @@ -120,6 +129,8 @@ dc@54200000 { clock-names = "dc", "parent"; resets = <&tegra_car 27>; reset-names = "dc"; + power-domains = <&pd_core>; + operating-points-v2 = <&disp1_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_DC>; @@ -150,6 +161,8 @@ dc@54240000 { clock-names = "dc", "parent"; resets = <&tegra_car 26>; reset-names = "dc"; + power-domains = <&pd_core>; + operating-points-v2 = <&disp2_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_DCB>; @@ -180,6 +193,8 @@ hdmi@54280000 { clock-names = "hdmi", "parent"; resets = <&tegra_car 51>; reset-names = "hdmi"; + power-domains = <&pd_core>; + operating-points-v2 = <&hdmi_dvfs_opp_table>; status = "disabled"; }; @@ -193,6 +208,7 @@ dsia: dsi@54300000 { resets = <&tegra_car 48>; reset-names = "dsi"; nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ + power-domains = <&pd_core>; status = "disabled"; #address-cells = <1>; @@ -209,6 +225,7 @@ dsib: dsi@54400000 { resets = <&tegra_car 82>; reset-names = "dsi"; nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */ + power-domains = <&pd_core>; status = "disabled"; #address-cells = <1>; @@ -222,6 +239,8 @@ msenc@544c0000 { clocks = <&tegra_car TEGRA114_CLK_MSENC>; resets = <&tegra_car TEGRA114_CLK_MSENC>; reset-names = "mpe"; + power-domains = <&pd_mpe>; + operating-points-v2 = <&msenc_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_MSENC>; @@ -234,6 +253,8 @@ tsec@54500000 { interrupts = ; clocks = <&tegra_car TEGRA114_CLK_TSEC>; resets = <&tegra_car TEGRA114_CLK_TSEC>; + power-domains = <&pd_core>; + operating-points-v2 = <&tsec_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_TSEC>; @@ -393,6 +414,8 @@ vde@6001a000 { reset-names = "vde", "mc"; resets = <&tegra_car 61>, <&mc TEGRA114_MC_RESET_VDE>; iommus = <&mc TEGRA_SWGROUP_VDE>; + power-domains = <&pd_vde>; + operating-points-v2 = <&vde_dvfs_opp_table>; }; apbmisc@70000800 { @@ -470,6 +493,7 @@ pwm: pwm@7000a000 { clocks = <&tegra_car TEGRA114_CLK_PWM>; resets = <&tegra_car 17>; reset-names = "pwm"; + power-domains = <&pd_core>; status = "disabled"; }; @@ -560,6 +584,8 @@ spi@7000d400 { reset-names = "spi"; dmas = <&apbdma 15>, <&apbdma 15>; dma-names = "rx", "tx"; + power-domains = <&pd_core>; + operating-points-v2 = <&sbc1_dvfs_opp_table>; status = "disabled"; }; @@ -575,6 +601,8 @@ spi@7000d600 { reset-names = "spi"; dmas = <&apbdma 16>, <&apbdma 16>; dma-names = "rx", "tx"; + power-domains = <&pd_core>; + operating-points-v2 = <&sbc2_dvfs_opp_table>; status = "disabled"; }; @@ -590,6 +618,8 @@ spi@7000d800 { reset-names = "spi"; dmas = <&apbdma 17>, <&apbdma 17>; dma-names = "rx", "tx"; + power-domains = <&pd_core>; + operating-points-v2 = <&sbc3_dvfs_opp_table>; status = "disabled"; }; @@ -605,6 +635,8 @@ spi@7000da00 { reset-names = "spi"; dmas = <&apbdma 18>, <&apbdma 18>; dma-names = "rx", "tx"; + power-domains = <&pd_core>; + operating-points-v2 = <&sbc4_dvfs_opp_table>; status = "disabled"; }; @@ -620,6 +652,8 @@ spi@7000dc00 { reset-names = "spi"; dmas = <&apbdma 27>, <&apbdma 27>; dma-names = "rx", "tx"; + power-domains = <&pd_core>; + operating-points-v2 = <&sbc5_dvfs_opp_table>; status = "disabled"; }; @@ -635,6 +669,8 @@ spi@7000de00 { reset-names = "spi"; dmas = <&apbdma 28>, <&apbdma 28>; dma-names = "rx", "tx"; + power-domains = <&pd_core>; + operating-points-v2 = <&sbc6_dvfs_opp_table>; status = "disabled"; }; @@ -661,6 +697,86 @@ tegra_pmc: pmc@7000e400 { clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; #clock-cells = <1>; + + pd_core: core-domain { + #power-domain-cells = <0>; + operating-points-v2 = <&core_opp_table>; + }; + + powergates { + /* + * TODO: Add DIS and DISB domains once DC is able + * to handle them properly. VENC and DISB should + * set DIS as their source power domain due to + * internal dependency. + */ + + pd_heg: heg { + clocks = <&tegra_car TEGRA114_CLK_GR2D>, + <&tegra_car TEGRA114_CLK_EPP>; + resets = <&mc TEGRA114_MC_RESET_2D>, + <&mc TEGRA114_MC_RESET_EPP>, + <&tegra_car TEGRA114_CLK_GR2D>, + <&tegra_car TEGRA114_CLK_EPP>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_mpe: mpe { + clocks = <&tegra_car TEGRA114_CLK_MSENC>; + resets = <&mc TEGRA114_MC_RESET_MPE>, + <&tegra_car TEGRA114_CLK_MSENC>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_3d: td { + clocks = <&tegra_car TEGRA114_CLK_GR3D>; + resets = <&mc TEGRA114_MC_RESET_3D>, + <&tegra_car TEGRA114_CLK_GR3D>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_vde: vdec { + clocks = <&tegra_car TEGRA114_CLK_VDE>; + resets = <&mc TEGRA114_MC_RESET_VDE>, + <&tegra_car TEGRA114_CLK_VDE>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_venc: venc { + clocks = <&tegra_car TEGRA114_CLK_ISP>, + <&tegra_car TEGRA114_CLK_VI>, + <&tegra_car TEGRA114_CLK_CSI>; + resets = <&mc TEGRA114_MC_RESET_ISP>, + <&mc TEGRA114_MC_RESET_VI>, + <&tegra_car TEGRA114_CLK_ISP>, + <&tegra_car 20 /* VI */>, + <&tegra_car TEGRA114_CLK_CSI>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_xusbss: xusba { + clocks = <&tegra_car TEGRA114_CLK_XUSB_SS>; + resets = <&tegra_car TEGRA114_CLK_XUSB_SS>; + #power-domain-cells = <0>; + }; + + pd_xusbdev: xusbb { + clocks = <&tegra_car TEGRA114_CLK_XUSB_DEV>; + resets = <&tegra_car 95>; + #power-domain-cells = <0>; + }; + + pd_xusbhost: xusbc { + clocks = <&tegra_car TEGRA114_CLK_XUSB_HOST>; + resets = <&tegra_car TEGRA114_CLK_XUSB_HOST>; + #power-domain-cells = <0>; + }; + }; }; fuse@7000f800 { @@ -670,6 +786,7 @@ fuse@7000f800 { clock-names = "fuse"; resets = <&tegra_car 39>; reset-names = "fuse"; + power-domains = <&pd_core>; }; mc: memory-controller@70019000 { @@ -691,6 +808,7 @@ emc: external-memory-controller@7001b000 { interrupts = ; clocks = <&tegra_car TEGRA114_CLK_EMC>; clock-names = "emc"; + power-domains = <&pd_core>; nvidia,memory-controller = <&mc>; operating-points-v2 = <&emc_icc_dvfs_opp_table>; @@ -885,6 +1003,8 @@ mmc@78000000 { clock-names = "sdhci"; resets = <&tegra_car 14>; reset-names = "sdhci"; + power-domains = <&pd_core>; + operating-points-v2 = <&sdmmc1_dvfs_opp_table>; status = "disabled"; }; @@ -907,6 +1027,8 @@ mmc@78000400 { clock-names = "sdhci"; resets = <&tegra_car 69>; reset-names = "sdhci"; + power-domains = <&pd_core>; + operating-points-v2 = <&sdmmc3_dvfs_opp_table>; status = "disabled"; }; @@ -918,6 +1040,8 @@ mmc@78000600 { clock-names = "sdhci"; resets = <&tegra_car 15>; reset-names = "sdhci"; + power-domains = <&pd_core>; + operating-points-v2 = <&sdmmc4_dvfs_opp_table>; status = "disabled"; }; @@ -930,6 +1054,7 @@ usb@7d000000 { resets = <&tegra_car 22>; reset-names = "usb"; nvidia,phy = <&phy1>; + power-domains = <&pd_core>; status = "disabled"; }; @@ -970,6 +1095,7 @@ usb@7d008000 { resets = <&tegra_car 59>; reset-names = "usb"; nvidia,phy = <&phy3>; + power-domains = <&pd_core>; status = "disabled"; }; From f0fbedccae9e16624977cca02216ab2399f5a3ab Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Tue, 28 Apr 2026 13:06:58 -0700 Subject: [PATCH 459/665] arm64: tegra: Add #{address,size}-cells to Chromium-based /firmware Chromium/Depthcharge bootloaders may dynamically add a few device nodes to a system's DTB under a /firmware node. A typical DT looks something like the following: / { firmware { ranges; coreboot { compatible = "coreboot"; reg = <...>; ...; }; }; }; Notably, the /firmware node has an empty 'ranges', but does not have address/size-cells. Commit 6e5773d52f4a ("of/address: Fix WARN when attempting translating non-translatable addresses") started requiring #address-cells for a device's parent if we want to use the reg resource in a device node. This leads to errors like the following: [ 7.763870] coreboot_table firmware:coreboot: probe with driver coreboot_table failed with error -22 Add appropriate #{address,size}-cells to work around the problem. Note that Google has also patched the Depthcharge bootloader source to add {address,size}-cells [1], but bootloader updates are typically delivered only via Google OS updates. Not all users install Google software updates, and even if they do, Google may not produce updated binaries for all/older devices. [1] https://lore.kernel.org/all/20241209092809.GA3246424@google.com/ https://crrev.com/c/6051580 ("coreboot: Insert #address-cells and #size-cells for firmware node") Closes: https://lore.kernel.org/all/aeKlYzTiL0OB1y3g@google.com/ Fixes: 6e5773d52f4a ("of/address: Fix WARN when attempting translating non-translatable addresses") Signed-off-by: Brian Norris Reviewed-by: Douglas Anderson Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132-norrin.dts | 5 +++++ arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index 683ac124523b..1f5222d43e62 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -18,6 +18,11 @@ chosen { stdout-path = "serial0:115200n8"; }; + firmware { + #address-cells = <2>; + #size-cells = <2>; + }; + memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x80000000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 1791b47f0a73..e0fde65a552b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -25,6 +25,11 @@ chosen { stdout-path = "serial0:115200n8"; }; + firmware { + #address-cells = <2>; + #size-cells = <2>; + }; + memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0xc0000000>; From d8d7e7549312c50fa5dcd69a6dc6f0035e770c09 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Sat, 23 May 2026 15:02:40 +0100 Subject: [PATCH 460/665] arm64: dts: rockchip: Add EL2 virtual timer interrupt The ARMv8.2 based CPUs used in a number of Rockchip SoCs are missing the EL2 virtual timer interrupt. Add it. Signed-off-by: Marc Zyngier Link: https://patch.msgid.link/20260523140242.586031-16-maz@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index 64bdd8b7754b..a5832895bd39 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -195,7 +195,8 @@ timer { interrupts = , , , - ; + , + ; arm,no-tick-in-suspend; }; From 3abf3f5c84fd32a95132a403e0209c8010b227f8 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 20 May 2026 23:45:27 +0000 Subject: [PATCH 461/665] dt-bindings: riscv: spacemit: Add K3 CoM260-IFX board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SpacemiT K3 CoM260-IFX board combines a 69.6 × 45 mm compute module with a reference carrier board. The module integrates up to 32GB LPDDR5 memory, UFS storage, Micro SD card slot and includes interfaces such as dual MIPI CSI-2 connectors, M.2 expansion, USB 3.0, Gigabit Ethernet, DisplayPort, and a 40-pin expansion header. The carrier board is intended as a general-purpose development platform for CoM260 module and exposes interfaces for all of storage, display, networking, and camera connectivity. Acked-by: Conor Dooley Link: https://patch.msgid.link/20260520-02-k3-com260-ifx-v2-1-d55095457cf0@kernel.org Signed-off-by: Yixun Lan --- Documentation/devicetree/bindings/riscv/spacemit.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml index af8030242bdc..311bbccba0ba 100644 --- a/Documentation/devicetree/bindings/riscv/spacemit.yaml +++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml @@ -32,6 +32,11 @@ properties: - deepcomputing,fml13v05 - spacemit,k3-pico-itx - const: spacemit,k3 + - items: + - enum: + - spacemit,k3-com260-ifx + - const: spacemit,k3-com260 + - const: spacemit,k3 additionalProperties: true From cfe5c91cb73c87f9021e446ec9d323c483851c46 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 20 May 2026 23:45:28 +0000 Subject: [PATCH 462/665] riscv: dts: spacemit: k3: Initial support for CoM260-IFX board The K3 CoM260-IFX board combine with one 260 pins "Gold Finger" computer module with a carrier board. The module integrates the K3 SoC, LPDDR5, UFS storage, Gigabit Ethernet, Micro SD card, PMIC Chip. The board offers a comprehensive array of interfaces, including MIPI-DSI, MIPI-CSI, DisplayPort, SDIO, SPI, I2S, I2C, CAN-FD, PWM, UART, USB, PCIe, and GMAC. Add initial support for enabling Serial UART and ethernet. Link: https://patch.msgid.link/20260520-02-k3-com260-ifx-v2-2-d55095457cf0@kernel.org Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/Makefile | 1 + .../riscv/boot/dts/spacemit/k3-com260-ifx.dts | 21 ++ arch/riscv/boot/dts/spacemit/k3-com260.dtsi | 190 ++++++++++++++++++ arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 33 +++ 4 files changed, 245 insertions(+) create mode 100644 arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts create mode 100644 arch/riscv/boot/dts/spacemit/k3-com260.dtsi diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile index acb993c452ba..28ec9e1e0a62 100644 --- a/arch/riscv/boot/dts/spacemit/Makefile +++ b/arch/riscv/boot/dts/spacemit/Makefile @@ -4,5 +4,6 @@ dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-r2s.dtb dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb +dtb-$(CONFIG_ARCH_SPACEMIT) += k3-com260-ifx.dtb dtb-$(CONFIG_ARCH_SPACEMIT) += k3-deepcomputing-fml13v05.dtb dtb-$(CONFIG_ARCH_SPACEMIT) += k3-pico-itx.dtb diff --git a/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts new file mode 100644 index 000000000000..238bb03d0e9e --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd + * Copyright (c) 2026 Yixun Lan + */ + +#include "k3-com260.dtsi" + +/ { + model = "SpacemiT K3 CoM260 IFX"; + compatible = "spacemit,k3-com260-ifx", "spacemit,k3-com260", "spacemit,k3"; + + aliases { + serial0 = &uart0; + ethernet0 = ð1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; diff --git a/arch/riscv/boot/dts/spacemit/k3-com260.dtsi b/arch/riscv/boot/dts/spacemit/k3-com260.dtsi new file mode 100644 index 000000000000..a38d7b738258 --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k3-com260.dtsi @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd + * Copyright (c) 2026 Yixun Lan + */ +#include + +#include "k3.dtsi" +#include "k3-pinctrl.dtsi" + +/ { + model = "SpacemiT K3 CoM260 Module"; + compatible = "spacemit,k3-com260", "spacemit,k3"; + + memory@100000000 { + device_type = "memory"; + reg = <0x1 0x00000000 0x4 0x00000000>; + }; + + reg_5v_sys: regulator-5v-sys { + compatible = "regulator-fixed"; + regulator-name = "P5V0_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&i2c8 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_cfg>; + status = "okay"; + + pmic@41 { + compatible = "spacemit,p1"; + reg = <0x41>; + interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; + vin1-supply = <®_5v_sys>; + vin2-supply = <®_5v_sys>; + vin3-supply = <®_5v_sys>; + vin4-supply = <®_5v_sys>; + vin5-supply = <®_5v_sys>; + vin6-supply = <®_5v_sys>; + aldoin-supply = <®_5v_sys>; + dldoin1-supply = <&buck4>; + dldoin2-supply = <&buck4>; + + regulators { + buck1: buck1 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck2: buck2 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck3: buck3 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck4: buck4 { + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2100000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck5: buck5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck6: buck6 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <500000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + aldo1: aldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + aldo2: aldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + aldo3: aldo3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + aldo4: aldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + dldo1: dldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + dldo2: dldo2 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + }; + + dldo3: dldo3 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-always-on; + regulator-boot-on; + }; + + dldo4: dldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + dldo5: dldo5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + dldo6: dldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + dldo7: dldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +ð1 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_rgmii_0_cfg>, <&gmac1_phy_0_cfg>; + phy-mode = "rgmii-id"; + phy-handle = <&phy1>; + status = "okay"; + + mdio { + phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-gpios = <&gpio 1 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_0_cfg>; + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi index 252c64af76fe..3ee1471f3798 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi @@ -45,6 +45,39 @@ gmac0-phy-0-pins { }; }; + gmac1_rgmii_0_cfg: gmac1-rgmii-0-cfg { + gmac1-rgmii-0-pins { + pinmux = , /* gmac1_rxdv */ + , /* gmac1 rx d0 */ + , /* gmac1 rx d1 */ + , /* gmac1 rx_clk */ + , /* gmac1 rx d2 */ + , /* gmac1 rx d3 */ + , /* gmac1 tx d0 */ + , /* gmac1 tx d1 */ + , /* gmac1 tx clk */ + , /* gmac1 tx d2 */ + , /* gmac1 tx d3 */ + , /* gmac1 tx_en */ + , /* gmac1 mdc */ + ; /* gmac1 mdio */ + + bias-disable; + drive-strength = <25>; + power-source = <1800>; + }; + }; + + gmac1_phy_0_cfg: gmac1-phy-0-cfg { + gmac1-phy-0-pins { + pinmux = ; /* gmac1 int */ + + bias-disable; + drive-strength = <25>; + power-source = <1800>; + }; + }; + /omit-if-no-ref/ i2c8_cfg: i2c8-cfg { i2c8-pins { From c7126247fb797127ced68691583932d0a05bbd68 Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Fri, 22 May 2026 23:23:11 +0200 Subject: [PATCH 463/665] arm64: dts: rockchip: add vicap node to rk3588 Add the device tree node for the RK3588 Video Capture (VICAP) unit. Signed-off-by: Michael Riesch [converted reg values in vicap ports to hexadecimal, to have them align with the port@X values, and be less confusing] Link: https://patch.msgid.link/20260522-rk3588-vicap-v5-5-d1d1f5265c56@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 91 +++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 4aff2701febf..a22da6671da3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1474,6 +1474,89 @@ av1d: video-codec@fdc70000 { resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; }; + vicap: video-capture@fdce0000 { + compatible = "rockchip,rk3588-vicap"; + reg = <0x0 0xfdce0000 0x0 0x800>; + interrupts = ; + clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, + <&cru DCLK_VICAP>, <&cru ICLK_CSIHOST0>, + <&cru ICLK_CSIHOST1>; + clock-names = "aclk", "hclk", "dclk", "iclk", "iclk1"; + iommus = <&vicap_mmu>; + power-domains = <&power RK3588_PD_VI>; + resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, + <&cru SRST_D_VICAP>, <&cru SRST_CSIHOST0_VICAP>, + <&cru SRST_CSIHOST1_VICAP>, + <&cru SRST_CSIHOST2_VICAP>, + <&cru SRST_CSIHOST3_VICAP>, + <&cru SRST_CSIHOST4_VICAP>, + <&cru SRST_CSIHOST5_VICAP>; + reset-names = "arst", "hrst", "drst", "irst0", "irst1", + "irst2", "irst3", "irst4", "irst5"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + vicap_dvp: port@0 { + reg = <0x0>; + }; + + vicap_mipi0: port@1 { + reg = <0x1>; + }; + + vicap_mipi1: port@2 { + reg = <0x2>; + }; + + vicap_mipi2: port@3 { + reg = <0x3>; + + vicap_mipi2_input: endpoint { + remote-endpoint = <&csi2_output>; + }; + }; + + vicap_mipi3: port@4 { + reg = <0x4>; + }; + + vicap_mipi4: port@5 { + reg = <0x5>; + + vicap_mipi4_input: endpoint { + remote-endpoint = <&csi4_output>; + }; + }; + + vicap_mipi5: port@6 { + reg = <0x6>; + }; + + vicap_toisp0: port@10 { + reg = <0x10>; + }; + + vicap_toisp1: port@11 { + reg = <0x11>; + }; + }; + }; + + vicap_mmu: iommu@fdce0800 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdce0800 0x0 0x40>, <0x0 0xfdce0900 0x0 0x40>; + interrupts = ; + clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_VI>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + csi2: csi@fdd30000 { compatible = "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2"; reg = <0x0 0xfdd30000 0x0 0x10000>; @@ -1496,6 +1579,10 @@ csi2_in: port@0 { csi2_out: port@1 { reg = <1>; + + csi2_output: endpoint { + remote-endpoint = <&vicap_mipi2_input>; + }; }; }; }; @@ -1522,6 +1609,10 @@ csi4_in: port@0 { csi4_out: port@1 { reg = <1>; + + csi4_output: endpoint { + remote-endpoint = <&vicap_mipi4_input>; + }; }; }; }; From bfc2779116ab7636a08c254d76a7a43d06feae1c Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Fri, 22 May 2026 23:23:12 +0200 Subject: [PATCH 464/665] arm64: dts: rockchip: add radxa camera 4k on rock 5b+ cam0 Add device tree overlay for the Radxa Camera 4K (featuring the Sony IMX415 image sensor) to applied on the Radxa ROCK 5B+ CAM0 port. Signed-off-by: Michael Riesch Link: https://patch.msgid.link/20260522-rk3588-vicap-v5-6-d1d1f5265c56@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 5 + .../rk3588-rock-5b-plus-radxa-cam4k-cam0.dtso | 99 +++++++++++++++++++ 2 files changed, 104 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam0.dtso diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index cb55c6b70d0e..d4ff476fb981 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -206,6 +206,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-plus.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-plus-radxa-cam4k-cam0.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5t.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou-video-demo.dtbo @@ -321,6 +322,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtb rk3588-rock-5b-pcie-srns-dtbs := rk3588-rock-5b.dtb \ rk3588-rock-5b-pcie-srns.dtbo +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-plus-radxa-4k-cam.dtb +rk3588-rock-5b-plus-radxa-4k-cam-dtbs := rk3588-rock-5b-plus.dtb \ + rk3588-rock-5b-plus-radxa-cam4k-cam0.dtbo + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou-haikou-video-demo.dtb rk3588-tiger-haikou-haikou-video-demo-dtbs := rk3588-tiger-haikou.dtb \ rk3588-tiger-haikou-video-demo.dtbo diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam0.dtso b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam0.dtso new file mode 100644 index 000000000000..ee9ecf68a886 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam0.dtso @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device tree overlay for the Radxa Camera 4K attached to the CAM0 port of + * the Radxa ROCK 5B+. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + savdd_cam0: regulator-savdd-cam0 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-name = "savdd_cam0"; + vin-supply = <&vcc_3v3_s3>; + }; + + sdvdd_cam0: regulator-sdvdd-cam0 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "sdvdd_cam0"; + vin-supply = <&vcc5v0_sys>; + }; + + siovdd_cam0: regulator-siovdd-cam0 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "siovdd_cam0"; + vin-supply = <&vcc_3v3_s3>; + }; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + imx415: camera-sensor@1a { + compatible = "sony,imx415"; + reg = <0x1a>; + assigned-clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + assigned-clock-rates = <37125000>; + avdd-supply = <&savdd_cam0>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + dvdd-supply = <&sdvdd_cam0>; + orientation = <2>; /* External */ + ovdd-supply = <&siovdd_cam0>; + pinctrl-names = "default"; + pinctrl-0 = <&cam0_rstn &mipim0_camera3_clk>; + reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>; + + port { + imx415_output: endpoint { + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <445500000>; + remote-endpoint = <&csi2_input>; + }; + }; + }; +}; + +&pinctrl { + cam0 { + cam0_rstn: cam0-rstn-pinctrl { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&csi2 { + status = "okay"; +}; + +&csi2_in { + csi2_input: endpoint { + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <445500000>; + remote-endpoint = <&imx415_output>; + }; +}; + +&csi_dphy0 { + status = "okay"; +}; + +&vicap { + status = "okay"; +}; + +&vicap_mmu { + status = "okay"; +}; From a34ae4f44c9ff4f4170dd21cdb22efad63710af4 Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Fri, 22 May 2026 23:23:13 +0200 Subject: [PATCH 465/665] arm64: dts: rockchip: add radxa camera 4k on rock 5b+ cam1 Add device tree overlay for the Radxa Camera 4K (featuring the Sony IMX415 image sensor) to applied on the Radxa ROCK 5B+ CAM1 port. Signed-off-by: Michael Riesch Link: https://patch.msgid.link/20260522-rk3588-vicap-v5-7-d1d1f5265c56@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 4 +- .../rk3588-rock-5b-plus-radxa-cam4k-cam1.dtso | 99 +++++++++++++++++++ 2 files changed, 102 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam1.dtso diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index d4ff476fb981..761d82b4f4f2 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -207,6 +207,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-plus-radxa-cam4k-cam0.dtbo +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-plus-radxa-cam4k-cam1.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5t.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou-video-demo.dtbo @@ -324,7 +325,8 @@ rk3588-rock-5b-pcie-srns-dtbs := rk3588-rock-5b.dtb \ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-plus-radxa-4k-cam.dtb rk3588-rock-5b-plus-radxa-4k-cam-dtbs := rk3588-rock-5b-plus.dtb \ - rk3588-rock-5b-plus-radxa-cam4k-cam0.dtbo + rk3588-rock-5b-plus-radxa-cam4k-cam0.dtbo \ + rk3588-rock-5b-plus-radxa-cam4k-cam1.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou-haikou-video-demo.dtb rk3588-tiger-haikou-haikou-video-demo-dtbs := rk3588-tiger-haikou.dtb \ diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam1.dtso b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam1.dtso new file mode 100644 index 000000000000..8a4cf3fdbf8e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam1.dtso @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device tree overlay for the Radxa Camera 4K attached to the CAM1 port of + * the Radxa ROCK 5B+. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + savdd_cam1: regulator-savdd-cam1 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-name = "savdd_cam1"; + vin-supply = <&vcc_3v3_s3>; + }; + + sdvdd_cam1: regulator-sdvdd-cam1 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "sdvdd_cam1"; + vin-supply = <&vcc5v0_sys>; + }; + + siovdd_cam1: regulator-siovdd-cam1 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "siovdd_cam1"; + vin-supply = <&vcc_3v3_s3>; + }; +}; + +&i2c4 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + cam1_imx415: camera-sensor@1a { + compatible = "sony,imx415"; + reg = <0x1a>; + assigned-clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + assigned-clock-rates = <37125000>; + avdd-supply = <&savdd_cam1>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + dvdd-supply = <&sdvdd_cam1>; + orientation = <2>; /* External */ + ovdd-supply = <&siovdd_cam1>; + pinctrl-names = "default"; + pinctrl-0 = <&cam1_rstn &mipim0_camera4_clk>; + reset-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>; + + port { + cam1_imx415_output: endpoint { + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <445500000>; + remote-endpoint = <&csi4_input>; + }; + }; + }; +}; + +&pinctrl { + cam1 { + cam1_rstn: cam1-rstn-pinctrl { + rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&csi4 { + status = "okay"; +}; + +&csi4_in { + csi4_input: endpoint { + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <445500000>; + remote-endpoint = <&cam1_imx415_output>; + }; +}; + +&csi_dphy1 { + status = "okay"; +}; + +&vicap { + status = "okay"; +}; + +&vicap_mmu { + status = "okay"; +}; From 3b7b80753c1f1a2e0d5f901d3ea1b75f258bb9de Mon Sep 17 00:00:00 2001 From: Aaron Kling Date: Sat, 1 Nov 2025 18:01:10 -0500 Subject: [PATCH 466/665] Revert "arm64: tegra: Disable ISO SMMU for Tegra194" This reverts commit ebea268ea583ba4970df425dfef8c8e21d0a4e12. Mmu is now being enabled for the display controllers. Signed-off-by: Aaron Kling Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 7bbf0e892724..5042224d8736 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1795,7 +1795,7 @@ iommu@10000000 { #iommu-cells = <1>; nvidia,memory-controller = <&mc>; - status = "disabled"; + status = "okay"; }; smmu: iommu@12000000 { From e1215cd6d3b9338e72573cc1cc60922b5bd34da4 Mon Sep 17 00:00:00 2001 From: Aaron Kling Date: Sat, 1 Nov 2025 18:01:11 -0500 Subject: [PATCH 467/665] arm64: tegra: Enable SMMU on Tegra194 display controllers These use a separate SMMU instance compared to everything else currently enabled for the SoC. Signed-off-by: Aaron Kling Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 5042224d8736..eb7e3c666df6 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1722,7 +1722,7 @@ bpmp-noc@d600000 { nvidia,apbmisc = <&apbmisc>; }; - iommu@10000000 { + smmu_iso: iommu@10000000 { compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; reg = <0x0 0x10000000 0x0 0x800000>; interrupts = , @@ -1962,6 +1962,7 @@ display@15200000 { interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; interconnect-names = "dma-mem", "read-1"; + iommus = <&smmu_iso TEGRA194_SID_NVDISPLAY>; nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; nvidia,head = <0>; @@ -1980,6 +1981,7 @@ display@15210000 { interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; interconnect-names = "dma-mem", "read-1"; + iommus = <&smmu_iso TEGRA194_SID_NVDISPLAY>; nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; nvidia,head = <1>; @@ -1998,6 +2000,7 @@ display@15220000 { interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; interconnect-names = "dma-mem", "read-1"; + iommus = <&smmu_iso TEGRA194_SID_NVDISPLAY>; nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; nvidia,head = <2>; @@ -2016,6 +2019,7 @@ display@15230000 { interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; interconnect-names = "dma-mem", "read-1"; + iommus = <&smmu_iso TEGRA194_SID_NVDISPLAY>; nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; nvidia,head = <3>; From 8399055d9f98e94c33608fe9d61afc09a43cc4df Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 11 May 2026 10:48:51 +0300 Subject: [PATCH 468/665] ARM: tegra: lg-x3: Complete video device graph Add front and rear camera nodes and interlink them with Tegra CSI and VI. Adjust camera PMIC voltages to better fit requirements and fix the focuser node. Signed-off-by: Svyatoslav Ryhel Signed-off-by: Thierry Reding --- arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts | 28 ++++ arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts | 46 ++++++ arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi | 154 +++++++++++++++++-- 3 files changed, 214 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts b/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts index cc14e6dca770..1b21d7628c8c 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts +++ b/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts @@ -12,6 +12,18 @@ aliases { mmc2 = &sdmmc1; /* WiFi */ }; + host1x@50000000 { + vi@54080000 { + csi@800 { + /delete-node/ channel@1; + }; + + ports { + /delete-node/ port@1; + }; + }; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -116,6 +128,22 @@ rmi4-f11@11 { }; }; + i2c@7000c500 { + camera-pmic@7d { + vt_1v2_front: ldo1 { + regulator-name = "vt_1v2_dig"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vt_2v7_front: ldo2 { + regulator-name = "vt_2v7_vana"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + }; + }; + spi@7000dc00 { dsi@2 { /* diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts b/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts index 414117fd4382..896639599c12 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts +++ b/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts @@ -118,6 +118,52 @@ rmi4-f1a@1a { }; }; + i2c@7000c500 { + /* Aptina 1/6" HD SOC (MT9M114) */ + front-camera@48 { + compatible = "onnn,mt9m114"; + reg = <0x48>; + + clocks = <&tegra_car TEGRA30_CLK_CSUS>; + + reset-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_LOW>; + + vddio-supply = <&vio_1v8_front>; + vdd-supply = <&vt_1v8_front>; + vaa-supply = <&vt_2v8_front>; + + orientation = <0>; /* Front camera */ + + assigned-clocks = <&tegra_car TEGRA30_CLK_VI_SENSOR>, + <&tegra_car TEGRA30_CLK_CSUS>; + assigned-clock-rates = <24000000>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>, + <&tegra_car TEGRA30_CLK_VI_SENSOR>; + + port { + front_camera_output: endpoint { + bus-type = ; + link-frequencies = /bits/ 64 <384000000>; + remote-endpoint = <&csib_input>; + }; + }; + }; + + camera-pmic@7d { + vt_1v8_front: ldo1 { + regulator-name = "vt_1v8_dig"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vt_2v8_front: ldo2 { + regulator-name = "vt_2v8_vana"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + }; + }; + spi@7000dc00 { dsi@2 { /* diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi b/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi index 768e201456d8..d2a5904cebed 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi @@ -3,6 +3,7 @@ #include #include #include +#include #include #include @@ -74,6 +75,91 @@ trustzone@bfe00000 { }; host1x@50000000 { + vi@54080000 { + status = "okay"; + + csi@800 { + status = "okay"; + + avdd-dsi-csi-supply = <&avdd_dsi_csi>; + + /* CSI-A */ + channel@0 { + reg = <0>; + + nvidia,mipi-calibrate = <&csi 0>; /* CSIA pad */ + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csia_input: endpoint { + data-lanes = <1 2>; + remote-endpoint = <&rear_camera_output>; + }; + }; + + port@1 { + reg = <1>; + + csia_output: endpoint { + remote-endpoint = <&vi_ppa_input>; + }; + }; + }; + + /* CSI-B */ + channel@1 { + reg = <1>; + + nvidia,mipi-calibrate = <&csi 1>; /* CSIB pad */ + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csib_input: endpoint { + data-lanes = <3>; + remote-endpoint = <&front_camera_output>; + }; + }; + + port@1 { + reg = <1>; + + csib_output: endpoint { + remote-endpoint = <&vi_ppb_input>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vi_ppa_input: endpoint { + remote-endpoint = <&csia_output>; + }; + }; + + port@1 { + reg = <1>; + + vi_ppb_input: endpoint { + remote-endpoint = <&csib_output>; + }; + }; + }; + }; + lcd: dc@54200000 { rgb { status = "okay"; @@ -1112,29 +1198,68 @@ dw9714: coil@c { compatible = "dongwoon,dw9714"; reg = <0x0c>; - enable-gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_HIGH>; + powerdown-gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; vcc-supply = <&vcc_focuser>; }; + /* SONY IMX111 1/4" BSI */ + rear-camera@10 { + compatible = "sony,imx111"; + reg = <0x10>; + + clocks = <&tegra_car TEGRA30_CLK_CSUS>; + + reset-gpios = <&gpio TEGRA_GPIO(K, 4) GPIO_ACTIVE_LOW>; + + iovdd-supply = <&vio_1v8_rear>; + dvdd-supply = <&vdd_1v2_rear>; + avdd-supply = <&vdd_2v7_rear>; + + orientation = <1>; /* Rear camera */ + rotation = <90>; + + nvmem = <&m24c08>; + lens-focus = <&dw9714>; + + assigned-clocks = <&tegra_car TEGRA30_CLK_VI_SENSOR>, + <&tegra_car TEGRA30_CLK_CSUS>; + assigned-clock-rates = <24000000>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>, + <&tegra_car TEGRA30_CLK_VI_SENSOR>; + + port { + rear_camera_output: endpoint { + data-lanes = <1 2>; + bus-type = ; + link-frequencies = /bits/ 64 <542400000>; + remote-endpoint = <&csia_input>; + }; + }; + }; + + /* rear camera sensor eeprom m24c08 from ST */ + m24c08: eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + + /* if high then WP is on, if low then off */ + wp-gpios = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>; + + /* it is not OTP but writing is unwanted */ + read-only; + pagesize = <16>; + num-addresses = <1>; + + vcc-supply = <&vio_1v8_rear>; + }; + camera-pmic@7d { compatible = "ti,lp8720"; reg = <0x7d>; enable-gpios = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>; - vt_1v2_front: ldo1 { - regulator-name = "vt_1v2_dig"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vt_2v7_front: ldo2 { - regulator-name = "vt_2v7_vana"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - vdd_2v7_rear: ldo3 { regulator-name = "8m_2v7_vana"; regulator-min-microvolt = <2700000>; @@ -1348,10 +1473,11 @@ vdd_1v2_mhl: ldo7 { maxim,active-fps-source = ; }; - ldo8 { + avdd_dsi_csi: ldo8 { regulator-name = "avdd_dsi_csi"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; + regulator-boot-on; maxim,active-fps-source = ; }; From 61cf0112f79d6c6de2a002874b8618e802b664f2 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 11 May 2026 10:48:52 +0300 Subject: [PATCH 469/665] ARM: tegra: lg-x3: Set PMIC's RTC address LG X3 devices have the PMIC's RTC module located at a non-standard address. Set the correct address. Signed-off-by: Svyatoslav Ryhel Signed-off-by: Thierry Reding --- arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi b/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi index d2a5904cebed..60e8a19aa70e 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi @@ -1297,7 +1297,8 @@ pwr_i2c: i2c@7000d000 { pmic: max77663@1c { compatible = "maxim,max77663"; - reg = <0x1c>; + reg = <0x1c>, <0x48>; + reg-names = "pmic", "rtc"; interrupts = ; #interrupt-cells = <2>; From ece4229e457de4ceeec80890c5c760f0c858eeea Mon Sep 17 00:00:00 2001 From: Ion Agorria Date: Mon, 11 May 2026 10:48:53 +0300 Subject: [PATCH 470/665] ARM: tegra: p880: Lower CPU thermal limit Lower the CPU thermal limit for the LG P880, since its chassis has less thermal dissipation capability than the P895. Signed-off-by: Ion Agorria Signed-off-by: Svyatoslav Ryhel Signed-off-by: Thierry Reding --- arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts b/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts index 1b21d7628c8c..6b30e17459ac 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts +++ b/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts @@ -537,4 +537,17 @@ sound { nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; }; + + thermal-zones { + cpu-thermal { + trips { + cpu-alert { + /* throttle at 60C until temperature drops to 59.8C */ + temperature = <60000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + }; }; From a5acde8adb4d4d921a004b8df995d50255253afa Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 11 May 2026 10:48:54 +0300 Subject: [PATCH 471/665] ARM: tegra: grouper: Add support for front camera Add front camera video path. Signed-off-by: Svyatoslav Ryhel Signed-off-by: Thierry Reding --- .../tegra30-asus-nexus7-grouper-common.dtsi | 128 ++++++++++++++++++ ...egra30-asus-nexus7-grouper-maxim-pmic.dtsi | 4 +- .../tegra30-asus-nexus7-grouper-ti-pmic.dtsi | 4 +- 3 files changed, 132 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-common.dtsi index 15f53babdc21..892d718294dd 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-common.dtsi @@ -2,6 +2,7 @@ #include #include +#include #include #include @@ -84,6 +85,93 @@ init-mode-hog { }; }; + host1x@50000000 { + vi@54080000 { + status = "okay"; + + csi@800 { + status = "okay"; + + avdd-dsi-csi-supply = <&avdd_dsi_csi>; + + /* CSI-A */ + channel@0 { + reg = <0>; + + nvidia,mipi-calibrate = <&csi 0>; /* CSIA pad */ + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csia_input: endpoint { + data-lanes = <1 2>; + /* No rear camera */ + }; + }; + + port@1 { + reg = <1>; + + csia_output: endpoint { + remote-endpoint = <&vi_ppa_input>; + }; + }; + }; + + /* CSI-B */ + channel@1 { + reg = <1>; + + nvidia,mipi-calibrate = <&csi 1>; /* CSIB pad */ + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csib_input: endpoint { + data-lanes = <3>; + remote-endpoint = <&front_camera_output>; + }; + }; + + port@1 { + reg = <1>; + + csib_output: endpoint { + remote-endpoint = <&vi_ppb_input>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vi_ppa_input: endpoint { + remote-endpoint = <&csia_output>; + }; + }; + + port@1 { + reg = <1>; + + vi_ppb_input: endpoint { + remote-endpoint = <&csib_output>; + }; + }; + }; + }; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -890,6 +978,36 @@ light-sensor@1c { vdd-supply = <&vdd_3v3_sys>; }; + /* Aptina 1/6" HD SOC (MI1040) */ + front-camera@48 { + compatible = "aptina,mi1040"; + reg = <0x48>; + + clocks = <&tegra_car TEGRA30_CLK_CSUS>; + + reset-gpios = <&gpio TEGRA_GPIO(O, 0) GPIO_ACTIVE_LOW>; + + vddio-supply = <&avdd_cam1>; + vdd-supply = <&vddio_cam>; + vaa-supply = <&avdd_cam1>; + + orientation = <0>; /* Front camera */ + + assigned-clocks = <&tegra_car TEGRA30_CLK_VI_SENSOR>, + <&tegra_car TEGRA30_CLK_CSUS>; + assigned-clock-rates = <24000000>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>, + <&tegra_car TEGRA30_CLK_VI_SENSOR>; + + port { + front_camera_output: endpoint { + bus-type = ; + link-frequencies = /bits/ 64 <384000000>; + remote-endpoint = <&csib_input>; + }; + }; + }; + accelerometer@68 { compatible = "invensense,mpu6050"; reg = <0x68>; @@ -1203,6 +1321,16 @@ vcc_3v3_ts: regulator-ts { vin-supply = <&vdd_5v0_sys>; }; + avdd_cam1: regulator-vcam1 { + compatible = "regulator-fixed"; + regulator-name = "avdd_cam1"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + sound { compatible = "nvidia,tegra-audio-rt5640-grouper", "nvidia,tegra-audio-rt5640"; diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi index 694c7fe37eb8..4bd98935031b 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi @@ -135,7 +135,7 @@ ldo4 { regulator-boot-on; }; - ldo5 { + vddio_cam: ldo5 { regulator-name = "vdd_camera"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -149,7 +149,7 @@ ldo6 { regulator-boot-on; }; - ldo7 { + avdd_dsi_csi: ldo7 { regulator-name = "avdd_dsi_csi"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-ti-pmic.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-ti-pmic.dtsi index ee4a3f482769..8fe3c62c9052 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-ti-pmic.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-ti-pmic.dtsi @@ -92,13 +92,13 @@ ldo4 { regulator-always-on; }; - ldo5 { + vddio_cam: ldo5 { regulator-name = "vddio_sdmmc,avdd_vdac"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - ldo6 { + avdd_dsi_csi: ldo6 { regulator-name = "avdd_dsi_csi,pwrdet_mipi"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; From 34d89435081d07b052dd522a57054132dada5400 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 11 May 2026 10:48:55 +0300 Subject: [PATCH 472/665] ARM: tegra: transformer: Add support for front camera Add front camera video path. Aptina MI1040 camera is used on all supported ASUS Transformers, but only TF201 and TF700T will work since on TF300T/TG/TL front camera is linked through an additional ISP. Signed-off-by: Svyatoslav Ryhel Signed-off-by: Thierry Reding --- .../tegra30-asus-transformer-common.dtsi | 138 +++++++++++++++++- 1 file changed, 137 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-transformer-common.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-transformer-common.dtsi index ead95306840f..e6d079647f77 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-asus-transformer-common.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-transformer-common.dtsi @@ -2,6 +2,7 @@ #include #include +#include #include #include "tegra30.dtsi" @@ -73,6 +74,91 @@ trustzone@bfe00000 { }; host1x@50000000 { + vi@54080000 { + status = "okay"; + + csi@800 { + status = "okay"; + + avdd-dsi-csi-supply = <&avdd_dsi_csi>; + + /* CSI-A */ + channel@0 { + reg = <0>; + + nvidia,mipi-calibrate = <&csi 0>; /* CSIA pad */ + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csia_input: endpoint { + data-lanes = <1 2>; + /* Add rear camera */ + }; + }; + + port@1 { + reg = <1>; + + csia_output: endpoint { + remote-endpoint = <&vi_ppa_input>; + }; + }; + }; + + /* CSI-B */ + channel@1 { + reg = <1>; + + nvidia,mipi-calibrate = <&csi 1>; /* CSIB pad */ + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csib_input: endpoint { + data-lanes = <3>; + remote-endpoint = <&front_camera_output>; + }; + }; + + port@1 { + reg = <1>; + + csib_output: endpoint { + remote-endpoint = <&vi_ppb_input>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vi_ppa_input: endpoint { + remote-endpoint = <&csia_output>; + }; + }; + + port@1 { + reg = <1>; + + vi_ppb_input: endpoint { + remote-endpoint = <&csib_output>; + }; + }; + }; + }; + hdmi: hdmi@54280000 { status = "okay"; @@ -1160,6 +1246,36 @@ light-sensor@1c { vdd-supply = <&vdd_3v3_sys>; }; + /* Aptina 1/6" HD SOC (MI1040) */ + front-camera@48 { + compatible = "aptina,mi1040"; + reg = <0x48>; + + clocks = <&tegra_car TEGRA30_CLK_CSUS>; + + reset-gpios = <&gpio TEGRA_GPIO(O, 0) GPIO_ACTIVE_LOW>; + + vddio-supply = <&vdd_1v8_cam>; + vdd-supply = <&vdd_1v8_cam>; + vaa-supply = <&avdd_2v85_fcam>; + + orientation = <0>; /* Front camera */ + + assigned-clocks = <&tegra_car TEGRA30_CLK_VI_SENSOR>, + <&tegra_car TEGRA30_CLK_CSUS>; + assigned-clock-rates = <24000000>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>, + <&tegra_car TEGRA30_CLK_VI_SENSOR>; + + port { + front_camera_output: endpoint { + bus-type = ; + link-frequencies = /bits/ 64 <384000000>; + remote-endpoint = <&csib_input>; + }; + }; + }; + gyroscope@68 { compatible = "invensense,mpu3050"; reg = <0x68>; @@ -1297,7 +1413,7 @@ ldo4 { /* LDO5 is not used by Transformers */ - ldo6 { + avdd_dsi_csi: ldo6 { regulator-name = "avdd_dsi_csi,pwrdet_mipi"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; @@ -1672,6 +1788,26 @@ hdmi_5v0_sys: regulator-hdmi { vin-supply = <&vdd_5v0_sys>; }; + vdd_1v8_cam: regulator-viocam { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_cam"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_1v8_vio>; + }; + + avdd_2v85_fcam: regulator-avcam-front { + compatible = "regulator-fixed"; + regulator-name = "vdd_2v85_fcam"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + sound { nvidia,i2s-controller = <&tegra_i2s1>; From 5333a49e51c2d0d5fe1615f721898036733ed5b0 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 11 May 2026 10:48:56 +0300 Subject: [PATCH 473/665] ARM: tegra: transformers: Add connector node for common trees All ASUS Transformers have micro-HDMI connector directly available. After Tegra HDMI got bridge/connector support, we should use connector framework for proper HW description. Tested-by: Andreas Westman Dorcsak # ASUS TF T30 Tested-by: Robert Eckelmann # ASUS TF101 T20 Tested-by: Svyatoslav Ryhel # ASUS TF201 T30 Signed-off-by: Svyatoslav Ryhel Signed-off-by: Thierry Reding --- .../tegra20-asus-transformer-common.dtsi | 22 ++++++++++++++++--- .../tegra30-asus-transformer-common.dtsi | 21 ++++++++++++++++-- 2 files changed, 38 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/nvidia/tegra20-asus-transformer-common.dtsi b/arch/arm/boot/dts/nvidia/tegra20-asus-transformer-common.dtsi index b48f53c00efa..5b758aad8d15 100644 --- a/arch/arm/boot/dts/nvidia/tegra20-asus-transformer-common.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra20-asus-transformer-common.dtsi @@ -79,9 +79,11 @@ hdmi@54280000 { pll-supply = <&hdmi_pll_reg>; hdmi-supply = <&vdd_hdmi_en>; - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) - GPIO_ACTIVE_HIGH>; + port { + hdmi_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; }; }; @@ -1017,6 +1019,20 @@ key-volume-up { }; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "d"; + + hpd-gpios = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + ddc-i2c-bus = <&hdmi_ddc>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + }; + i2cmux { compatible = "i2c-mux-pinctrl"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-transformer-common.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-transformer-common.dtsi index e6d079647f77..bf1c3a31d406 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-asus-transformer-common.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-transformer-common.dtsi @@ -166,8 +166,11 @@ hdmi: hdmi@54280000 { pll-supply = <&vdd_1v8_vio>; vdd-supply = <&vdd_3v3_sys>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - nvidia,ddc-i2c-bus = <&hdmi_ddc>; + port { + hdmi_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; }; }; @@ -1688,6 +1691,20 @@ key-volume-up { }; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "d"; + + hpd-gpios = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + ddc-i2c-bus = <&hdmi_ddc>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + }; + vdd_5v0_bat: regulator-bat { compatible = "regulator-fixed"; regulator-name = "vdd_ac_bat"; From 2ecff0cda80b9ba0e513620003d156cfef7394df Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 11 May 2026 10:48:57 +0300 Subject: [PATCH 474/665] ARM: tegra: tf600t: Configure panel Configure DSI panel used in ASUS VivoTab TF600T. Tested-by: Andreas Westman Dorcsak Signed-off-by: Svyatoslav Ryhel Signed-off-by: Thierry Reding --- .../boot/dts/nvidia/tegra30-asus-tf600t.dts | 62 ++++++++++++++++++- 1 file changed, 60 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-tf600t.dts b/arch/arm/boot/dts/nvidia/tegra30-asus-tf600t.dts index 9296e7970ce4..8b68bfef8dee 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-asus-tf600t.dts +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-tf600t.dts @@ -23,6 +23,7 @@ aliases { rtc0 = &pmic; rtc1 = "/rtc@7000e000"; + display0 = &lcd; display1 = &hdmi; serial1 = &uartc; /* Bluetooth */ @@ -55,6 +56,37 @@ linux,cma@80000000 { }; host1x@50000000 { + vi@54080000 { + status = "okay"; + + csi@800 { + status = "okay"; + + avdd-dsi-csi-supply = <&avdd_dsi_csi>; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vi_ppa_input: endpoint { + /* Link to the rear camera */ + }; + }; + + port@1 { + reg = <1>; + + vi_ppb_input: endpoint { + /* Link to the front camera */ + }; + }; + }; + }; + hdmi: hdmi@54280000 { status = "okay"; @@ -68,6 +100,22 @@ hdmi_out: endpoint { }; }; }; + + lcd: dsi@54300000 { + status = "okay"; + + avdd-dsi-csi-supply = <&avdd_dsi_csi>; + + panel@0 { + compatible = "hydis,hv101hd1"; + reg = <0>; + + vdd-supply = <&vdd_panel>; + vio-supply = <&vio_panel>; + + backlight = <&backlight>; + }; + }; }; vde@6001a000 { @@ -1123,11 +1171,10 @@ pmic-sleep-hog { }; regulators { - vdd_lcd: vdd1 { + vio_panel: vdd1 { regulator-name = "vddio_ddr_1v2"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; - regulator-always-on; regulator-boot-on; ti,regulator-ext-sleep-control = <8>; }; @@ -2386,6 +2433,17 @@ vdd_5v0_bl: regulator-bl { vin-supply = <&vdd_5v0_bat>; }; + vdd_panel: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "vdd_panel"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + hdmi_5v0_sys: regulator-hdmi { compatible = "regulator-fixed"; regulator-name = "hdmi_5v0_sys"; From d9c890d753034adcae0f74de578deed60d58233a Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 11 May 2026 10:48:58 +0300 Subject: [PATCH 475/665] ARM: tegra: tf600t: Drop backlight regulator Drop dedicated backlight regulator since the GPIO used in it is actually SFIO controlling backlight and setting it as GPIO causes backlight to freeze at maximum level. Tested-by: Andreas Westman Dorcsak Signed-off-by: Svyatoslav Ryhel Signed-off-by: Thierry Reding --- arch/arm/boot/dts/nvidia/tegra30-asus-tf600t.dts | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-tf600t.dts b/arch/arm/boot/dts/nvidia/tegra30-asus-tf600t.dts index 8b68bfef8dee..0bebea0cb8c4 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-asus-tf600t.dts +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-tf600t.dts @@ -2192,7 +2192,7 @@ backlight: backlight { compatible = "pwm-backlight"; enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_5v0_bl>; + power-supply = <&vdd_5v0_sys>; pwms = <&pwm 0 71428>; brightness-levels = <1 255>; @@ -2422,17 +2422,6 @@ vdd_3v3_als: regulator-als { vin-supply = <&vdd_3v3_sys>; }; - vdd_5v0_bl: regulator-bl { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v0_bl"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - gpio = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_bat>; - }; - vdd_panel: regulator-panel { compatible = "regulator-fixed"; regulator-name = "vdd_panel"; From 774bc2764647cfd6b65727cfa978d809f11df392 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 11 May 2026 10:48:59 +0300 Subject: [PATCH 476/665] ARM: tegra: tf600t: Invert accelerometer calibration matrix IMU calibration matrix used in the device tree is inverted when testing on the device which results in wrong screen orientation. Invert it to match the matrix dumped from the device. Tested-by: Andreas Westman Dorcsak Signed-off-by: Svyatoslav Ryhel Signed-off-by: Thierry Reding --- arch/arm/boot/dts/nvidia/tegra30-asus-tf600t.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-tf600t.dts b/arch/arm/boot/dts/nvidia/tegra30-asus-tf600t.dts index 0bebea0cb8c4..5c634b0f3f46 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-asus-tf600t.dts +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-tf600t.dts @@ -1091,9 +1091,9 @@ imu@69 { vdd-supply = <&vdd_3v3_sys>; vddio-supply = <&vdd_1v8_vio>; - mount-matrix = "0", "-1", "0", - "-1", "0", "0", - "0", "0", "-1"; + mount-matrix = "0", "1", "0", + "1", "0", "0", + "0", "0", "1"; /* External I2C interface */ i2c-gate { From fba4a31a7f3b6b29b01c83180f83e7ed4c398738 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 11 Apr 2026 15:02:35 +0200 Subject: [PATCH 477/665] arm64: dts: st: Fix SAI addresses on stm32mp251 The second field of SAI register addresses should be within 0x3f0 bytes from the start of the SAI register addresses, the second field describes the ID registers which are at that addrses. Currently, the second field does not match RM, fix it. Fixes: bf26d75a95f1 ("arm64: dts: st: add sai support on stm32mp251") Signed-off-by: Marek Vasut Reviewed-by: Olivier Moysan Link: https://lore.kernel.org/r/20260411130300.19603-1-marex@nabladev.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 673fbc5632e6..9c63fdb5a885 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1202,7 +1202,7 @@ spi5: spi@40280000 { sai1: sai@40290000 { compatible = "st,stm32mp25-sai"; - reg = <0x40290000 0x4>, <0x4029a3f0 0x10>; + reg = <0x40290000 0x4>, <0x402903f0 0x10>; ranges = <0 0x40290000 0x400>; #address-cells = <1>; #size-cells = <1>; @@ -1236,7 +1236,7 @@ sai1b: audio-controller@40290024 { sai2: sai@402a0000 { compatible = "st,stm32mp25-sai"; - reg = <0x402a0000 0x4>, <0x402aa3f0 0x10>; + reg = <0x402a0000 0x4>, <0x402a03f0 0x10>; ranges = <0 0x402a0000 0x400>; #address-cells = <1>; #size-cells = <1>; @@ -1270,7 +1270,7 @@ sai2b: audio-controller@402a0024 { sai3: sai@402b0000 { compatible = "st,stm32mp25-sai"; - reg = <0x402b0000 0x4>, <0x402ba3f0 0x10>; + reg = <0x402b0000 0x4>, <0x402b03f0 0x10>; ranges = <0 0x402b0000 0x400>; #address-cells = <1>; #size-cells = <1>; @@ -1362,7 +1362,7 @@ usart1: serial@40330000 { sai4: sai@40340000 { compatible = "st,stm32mp25-sai"; - reg = <0x40340000 0x4>, <0x4034a3f0 0x10>; + reg = <0x40340000 0x4>, <0x403403f0 0x10>; ranges = <0 0x40340000 0x400>; #address-cells = <1>; #size-cells = <1>; From 245552af869d35ae27cac2121696dd630f15b3bf Mon Sep 17 00:00:00 2001 From: Jinseok Kim Date: Wed, 27 May 2026 19:39:26 +0900 Subject: [PATCH 478/665] arm: dts: bcm2711: Fix typo in gpio-line-names Replace "RGMIO_MDC" with "RGMII_MDC" in gpio-line-names. Signed-off-by: Jinseok Kim Link: https://lore.kernel.org/r/20260527103930.2973-1-always.starving0@gmail.com Fixes: cd87c180b301 ("ARM: dts: bcm2711-rpi-4-b: Add SoC GPIO labels") Fixes: ea93ada05c9e ("ARM: dts: Add Raspberry Pi Compute Module 4 IO Board") Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts | 2 +- arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts index 353bb50ce542..5469fa663526 100644 --- a/arch/arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts +++ b/arch/arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts @@ -110,7 +110,7 @@ &gpio { "GPIO26", "GPIO27", "RGMII_MDIO", - "RGMIO_MDC", + "RGMII_MDC", /* Used by BT module */ "CTS0", /* 30 */ "RTS0", diff --git a/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts b/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts index 6bc77dd48c0d..1f4ebec68370 100644 --- a/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts +++ b/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts @@ -56,7 +56,7 @@ &gpio { "GPIO26", "GPIO27", "RGMII_MDIO", - "RGMIO_MDC", + "RGMII_MDC", /* Used by BT module */ "CTS0", "RTS0", From ff4427a465a018fedaadd607c8166588a28a79d1 Mon Sep 17 00:00:00 2001 From: Vitor Soares Date: Fri, 22 May 2026 17:11:05 +0100 Subject: [PATCH 479/665] arm64: dts: ti: k3-am62-verdin: Add Toradex DSI to LVDS adapter with 10.1" display Add a device tree overlay for the Toradex DSI to LVDS Adapter with the Toradex Capacitive Touch Display 10.1" LVDS. The adapter connects to the Verdin DSI_1 interface. It is based on the Texas Instruments SN65DSI84 DSI-to-LVDS bridge and drives a LogicTechno LT170410-2WHC 10.1" WXGA LVDS panel. Touch input is provided by an Atmel MaxTouch capacitive touch controller. Link: https://developer.toradex.com/hardware/accessories/add-ons/dsi-lvds-adapter Link: https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-lvds Assisted-by: Claude:claude-sonnet-4.6 Signed-off-by: Vitor Soares Reviewed-by: Francesco Dolcini Link: https://patch.msgid.link/20260522161105.277519-14-ivitro@gmail.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 5 + ...in-dsi-to-lvds-panel-cap-touch-10inch.dtso | 124 ++++++++++++++++++ 2 files changed, 129 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 21db60cd19de..b2408f62c139 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -24,6 +24,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-tqma62xx-mba62xx.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dsi-to-hdmi.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dahlia-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dev-dsi-to-hdmi.dtb @@ -209,6 +210,9 @@ k3-am625-sk-csi2-ov5640-dtbs := k3-am625-sk.dtb \ k3-am625-sk-csi2-tevi-ov5640-dtbs := k3-am625-sk.dtb \ k3-am62x-sk-csi2-tevi-ov5640.dtbo k3-am625-sk-hdmi-audio-dtbs := k3-am625-sk.dtb k3-am62x-sk-hdmi-audio.dtbo +k3-am625-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch-dtbs := \ + k3-am625-verdin-wifi-dev.dtb \ + k3-am625-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtbo k3-am62-lp-sk-hdmi-audio-dtbs := k3-am62-lp-sk.dtb k3-am62x-sk-hdmi-audio.dtbo k3-am62-lp-sk-nand-dtbs := k3-am62-lp-sk.dtb k3-am62-lp-sk-nand.dtbo k3-am62a7-phyboard-lyra-disable-eth-phy-dtbs := k3-am62a7-phyboard-lyra-rdk.dtb \ @@ -310,6 +314,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am625-sk-csi2-ov5640.dtb \ k3-am625-sk-csi2-tevi-ov5640.dtb \ k3-am625-sk-hdmi-audio.dtb \ + k3-am625-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch.dtb \ k3-am62-lp-sk-hdmi-audio.dtb \ k3-am62-lp-sk-nand.dtb \ k3-am62a7-phyboard-lyra-disable-eth-phy.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtso b/arch/arm64/boot/dts/ti/k3-am625-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtso new file mode 100644 index 000000000000..deb74ecc5eb4 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtso @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Toradex DSI to LVDS Adapter on Verdin DSI_1 with Capacitive Touch Display 10.1" + * Used on Dahlia (X17) and Development Board (X48) that expose DSI_1 via an + * Samtec LSS-130 connector. + * + * https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-lvds + * https://www.toradex.com/accessories/capacitive-touch-display-10.1-inch-lvds + * https://developer.toradex.com/hardware/accessories/add-ons/dsi-lvds-adapter + * https://www.toradex.com/accessories/verdin-dsi-to-lvds-adapter + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + backlight_pwm3: backlight-pwm3 { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2s_2_d_out_gpio>; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + /* Verdin I2S_2_D_OUT as GPIO (SODIMM 46) */ + enable-gpios = <&main_gpio0 34 GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3>; + /* Verdin PWM_3_DSI (SODIMM 19) */ + pwms = <&epwm1 0 6666667 PWM_POLARITY_INVERTED>; + }; + + panel-lvds-bridge { + compatible = "logictechno,lt170410-2whc"; + backlight = <&backlight_pwm3>; + power-supply = <®_3v3_dsi>; + + port { + panel_lvds_bridge_in: endpoint { + remote-endpoint = <&dsi_lvds_bridge_out>; + }; + }; + }; + + reg_3v3_dsi: regulator-3v3-dsi { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_DSI"; + }; +}; + +&dsi_bridge { + status = "okay"; +}; + +&dsi_bridge_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi_bridge_out: endpoint { + remote-endpoint = <&dsi_lvds_bridge_in>; + }; + }; +}; + +&dss { + status = "okay"; +}; + +/* Verdin I2C_1 */ +&main_i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + bridge@2c { + compatible = "ti,sn65dsi84"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dsi1_bkl_en>; + /* Verdin GPIO_10_DSI (SODIMM 21) - DSI_1_BKL_EN */ + enable-gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_lvds_bridge_in: endpoint { + remote-endpoint = <&dsi_bridge_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@2 { + reg = <2>; + + dsi_lvds_bridge_out: endpoint { + remote-endpoint = <&panel_lvds_bridge_in>; + }; + }; + }; + }; + + touchscreen@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dsi1_int>, <&pinctrl_i2s_2_bclk_gpio>; + /* Verdin GPIO_9_DSI (SODIMM 17) - TOUCH_INT# */ + interrupt-parent = <&main_gpio1>; + interrupts = <49 IRQ_TYPE_EDGE_FALLING>; + /* Verdin I2S_2_BCLK (SODIMM 42) - TOUCH_RESET# */ + reset-gpios = <&main_gpio0 35 GPIO_ACTIVE_LOW>; + }; +}; From 38d01a245e66c30e7372a4a67d310fbcd8319649 Mon Sep 17 00:00:00 2001 From: Vitor Soares Date: Fri, 22 May 2026 17:11:06 +0100 Subject: [PATCH 480/665] arm64: dts: ti: k3-am62-verdin: Add Toradex Capacitive Touch Display 10.1" LVDS Add a device tree overlay for the Toradex Capacitive Touch Display 10.1" LVDS connected via Verdin AM62 OLDI on carrier boards exposing LVDS interface (e.g., Mallow). The panel is a LogicTechno LT170410-2WHC 10.1" WXGA IPS LCD and the touch input is provided by an Atmel MaxTouch capacitive touch controller. Link: https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-lvds Assisted-by: Claude:claude-sonnet-4.6 Signed-off-by: Vitor Soares Reviewed-by: Francesco Dolcini Link: https://patch.msgid.link/20260522161105.277519-15-ivitro@gmail.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 5 + ...25-verdin-panel-cap-touch-10inch-lvds.dtso | 120 ++++++++++++++++++ 2 files changed, 125 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-panel-cap-touch-10inch-lvds.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index b2408f62c139..867c05b675d1 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -33,6 +33,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-ivy.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-mallow.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-yavia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-zinnia.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-panel-cap-touch-10inch-lvds.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dev-dsi-to-hdmi.dtb @@ -213,6 +214,9 @@ k3-am625-sk-hdmi-audio-dtbs := k3-am625-sk.dtb k3-am62x-sk-hdmi-audio.dtbo k3-am625-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch-dtbs := \ k3-am625-verdin-wifi-dev.dtb \ k3-am625-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtbo +k3-am625-verdin-wifi-mallow-panel-cap-touch-10inch-lvds-dtbs := \ + k3-am625-verdin-wifi-mallow.dtb \ + k3-am625-verdin-panel-cap-touch-10inch-lvds.dtbo k3-am62-lp-sk-hdmi-audio-dtbs := k3-am62-lp-sk.dtb k3-am62x-sk-hdmi-audio.dtbo k3-am62-lp-sk-nand-dtbs := k3-am62-lp-sk.dtb k3-am62-lp-sk-nand.dtbo k3-am62a7-phyboard-lyra-disable-eth-phy-dtbs := k3-am62a7-phyboard-lyra-rdk.dtb \ @@ -315,6 +319,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am625-sk-csi2-tevi-ov5640.dtb \ k3-am625-sk-hdmi-audio.dtb \ k3-am625-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch.dtb \ + k3-am625-verdin-wifi-mallow-panel-cap-touch-10inch-lvds.dtb \ k3-am62-lp-sk-hdmi-audio.dtb \ k3-am62-lp-sk-nand.dtb \ k3-am62a7-phyboard-lyra-disable-eth-phy.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-panel-cap-touch-10inch-lvds.dtso b/arch/arm64/boot/dts/ti/k3-am625-verdin-panel-cap-touch-10inch-lvds.dtso new file mode 100644 index 000000000000..f83366b11bdb --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-panel-cap-touch-10inch-lvds.dtso @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Toradex Capacitive Touch Display 10.1" connected via Verdin AM62 OLDI + * on carrier boards with a Toradex standard LVDS display connector + * (e.g., Mallow). + * + * https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-lvds + * https://www.toradex.com/accessories/capacitive-touch-display-10.1-inch-lvds + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include "k3-pinctrl.h" + +&{/} { + backlight_pwm2: backlight-pwm2 { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2s_2_d_out_gpio>; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + /* Verdin I2S_2_D_OUT as GPIO (SODIMM 46) */ + enable-gpios = <&main_gpio0 34 GPIO_ACTIVE_HIGH>; + /* Verdin PWM_2 (SODIMM 16) */ + pwms = <&epwm0 1 6666667 PWM_POLARITY_INVERTED>; + }; + + panel-lvds-native { + compatible = "logictechno,lt170410-2whc"; + backlight = <&backlight_pwm2>; + power-supply = <®_3v3_lvds>; + + port { + panel_lvds_native_in: endpoint { + remote-endpoint = <&oldi0_out>; + }; + }; + }; + + reg_3v3_lvds: regulator-3v3-lvds { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_LVDS"; + }; +}; + +&dss { + status = "okay"; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* DSS VP1: internal DPI output to OLDIx */ + port@0 { + reg = <0>; + + dss0_out: endpoint { + remote-endpoint = <&oldi0_in>; + }; + }; +}; + +/* Verdin I2C_2_DSI */ +&main_i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2s_2_d_in_gpio>, <&pinctrl_i2s_2_sync_gpio>; + /* Verdin I2S_2_SYNC as GPIO (SODIMM 44) */ + interrupt-parent = <&main_gpio0>; + interrupts = <37 IRQ_TYPE_EDGE_FALLING>; + /* Verdin I2S_2_D_IN as GPIO (SODIMM 48) */ + reset-gpios = <&main_gpio0 33 GPIO_ACTIVE_LOW>; + }; +}; + +&main_pmx0 { + /* Mallow Touch RST */ + pinctrl_i2s_2_d_in_gpio: main-gpio0-33-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0088, PIN_INPUT, 7) /* (L24) GPMC0_OEn_REn.GPIO0_33 */ /* SODIMM 48 */ + >; + }; + + /* Mallow Touch INT# */ + pinctrl_i2s_2_sync_gpio: main-gpio0-37-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0098, PIN_INPUT, 7) /* (U23) GPMC0_WAIT0.GPIO0_37 */ /* SODIMM 44 */ + >; + }; +}; + +&oldi0 { + status = "okay"; +}; + +&oldi0_port0 { + oldi0_in: endpoint { + remote-endpoint = <&dss0_out>; + }; +}; + +&oldi0_port1 { + oldi0_out: endpoint { + remote-endpoint = <&panel_lvds_native_in>; + }; +}; From 8e76e1539c440c3070e4004bd20392588f870010 Mon Sep 17 00:00:00 2001 From: Vitor Soares Date: Fri, 22 May 2026 17:11:09 +0100 Subject: [PATCH 481/665] arm64: dts: ti: k3-am62-verdin: Add Toradex Capacitive Touch Display 10.1" DSI Add a device tree overlay for the Toradex Capacitive Touch Display 10.1" on the Verdin DSI_1 interface. The display features an internal Texas Instruments SN65DSI83 DSI-to-LVDS bridge driving a Riverdi RVT101HVLNWC00 10.1" WXGA (1280x800) IPS TFT LCD panel. The touch input is provided by an Ilitek ILI2132 capacitive touch controller. The overlay is also combined with the Verdin AM62 Dahlia carrier board device trees to provide ready-to-use DTBs in both WiFi and non-Wifi SoM variants. Link: https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-dsi Link: https://developer.toradex.com/hardware/accessories/add-ons/dsi-display-adapter/ Assisted-by: Claude:claude-sonnet-4.6 Signed-off-by: Vitor Soares Reviewed-by: Francesco Dolcini Link: https://patch.msgid.link/20260522161105.277519-18-ivitro@gmail.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 9 ++ ...625-verdin-panel-cap-touch-10inch-dsi.dtso | 132 ++++++++++++++++++ 2 files changed, 141 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-panel-cap-touch-10inch-dsi.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 867c05b675d1..dc397bc693ac 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -11,10 +11,16 @@ # Boards with AM62x SoC k3-am625-verdin-nonwifi-dahlia-dsi-to-hdmi-dtbs := k3-am625-verdin-nonwifi-dahlia.dtb \ k3-am625-verdin-dsi-to-hdmi.dtbo +k3-am625-verdin-nonwifi-dahlia-panel-cap-touch-10inch-dsi-dtbs := \ + k3-am625-verdin-nonwifi-dahlia.dtb \ + k3-am625-verdin-panel-cap-touch-10inch-dsi.dtbo k3-am625-verdin-nonwifi-dev-dsi-to-hdmi-dtbs := k3-am625-verdin-nonwifi-dev.dtb \ k3-am625-verdin-dsi-to-hdmi.dtbo k3-am625-verdin-wifi-dahlia-dsi-to-hdmi-dtbs := k3-am625-verdin-wifi-dahlia.dtb \ k3-am625-verdin-dsi-to-hdmi.dtbo +k3-am625-verdin-wifi-dahlia-panel-cap-touch-10inch-dsi-dtbs := \ + k3-am625-verdin-wifi-dahlia.dtb \ + k3-am625-verdin-panel-cap-touch-10inch-dsi.dtbo k3-am625-verdin-wifi-dev-dsi-to-hdmi-dtbs := k3-am625-verdin-wifi-dev.dtb \ k3-am625-verdin-dsi-to-hdmi.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay.dtb @@ -26,6 +32,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-tqma62xx-mba62xx.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dsi-to-hdmi.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dahlia-dsi-to-hdmi.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dahlia-panel-cap-touch-10inch-dsi.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dev-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dev.dtb @@ -33,8 +40,10 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-ivy.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-mallow.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-yavia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-zinnia.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-panel-cap-touch-10inch-dsi.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-panel-cap-touch-10inch-lvds.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia-dsi-to-hdmi.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia-panel-cap-touch-10inch-dsi.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dev-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dev.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-panel-cap-touch-10inch-dsi.dtso b/arch/arm64/boot/dts/ti/k3-am625-verdin-panel-cap-touch-10inch-dsi.dtso new file mode 100644 index 000000000000..ed66feec9462 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-panel-cap-touch-10inch-dsi.dtso @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Toradex Capacitive Touch Display 10.1" on Verdin DSI_1. + * On Dahlia (X17) and Development Board (X48), DSI_1 is exposed via a + * Samtec LSS-130 connector and requires the Toradex DSI Display Adapter + * to convert to FFC/FPC connector. + * + * https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-dsi + * https://www.toradex.com/accessories/capacitive-touch-display-10.1-inch-dsi + * https://developer.toradex.com/hardware/accessories/add-ons/dsi-display-adapter + * https://www.toradex.com/accessories/verdin-dsi-display-adapter + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + backlight_pwm3: backlight-pwm3 { + compatible = "pwm-backlight"; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + power-supply = <®_3v3>; + /* Verdin PWM_3_DSI (SODIMM 19) - PWM_3_DSI_LVDS */ + pwms = <&epwm1 0 6666667 0>; + }; + + panel-lvds-bridge { + compatible = "riverdi,rvt101hvlnwc00", "panel-lvds"; + backlight = <&backlight_pwm3>; + data-mapping = "vesa-24"; + height-mm = <136>; + width-mm = <217>; + + panel-timing { + clock-frequency = <72400000>; + de-active = <1>; + hactive = <1280>; + hback-porch = <88 88 88>; + hfront-porch = <12 72 132>; + hsync-active = <0>; + hsync-len = <1 5 40>; + pixelclk-active = <1>; + vactive = <800>; + vback-porch = <23 23 23>; + vfront-porch = <1 15 49>; + vsync-active = <0>; + vsync-len = <1 10 20>; + }; + + port { + panel_lvds_bridge_in: endpoint { + remote-endpoint = <&dsi_lvds_bridge_out>; + }; + }; + }; +}; + +&dsi_bridge { + status = "okay"; +}; + +&dsi_bridge_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi_bridge_out: endpoint { + remote-endpoint = <&dsi_lvds_bridge_in>; + }; + }; +}; + +&dss { + status = "okay"; +}; + +/* Verdin I2C_2_DSI */ +&main_i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + bridge@2c { + compatible = "ti,sn65dsi83"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dsi1_bkl_en>; + /* Verdin GPIO_10_DSI (SODIMM 21) - DSI_1_BKL_EN */ + enable-gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_lvds_bridge_in: endpoint { + remote-endpoint = <&dsi_bridge_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@2 { + reg = <2>; + + dsi_lvds_bridge_out: endpoint { + remote-endpoint = <&panel_lvds_bridge_in>; + }; + }; + }; + }; + + touchscreen@41 { + compatible = "ilitek,ili2132"; + reg = <0x41>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dsi1_int>, <&pinctrl_i2s_2_bclk_gpio>; + /* Verdin GPIO_9_DSI (SODIMM 17) - TOUCH_INT# */ + interrupt-parent = <&main_gpio1>; + interrupts = <49 IRQ_TYPE_EDGE_RISING>; + /* Verdin I2S_2_BCLK (SODIMM 42) - TOUCH_RESET# */ + reset-gpios = <&main_gpio0 35 GPIO_ACTIVE_LOW>; + }; +}; From 8a637725ad7cb29434bba0deb6b530d3116429b3 Mon Sep 17 00:00:00 2001 From: Vitor Soares Date: Fri, 22 May 2026 17:11:10 +0100 Subject: [PATCH 482/665] arm64: dts: ti: k3-am62-verdin: Add Toradex Capacitive Touch Display 7" DSI Add a device tree overlay for the Toradex Capacitive Touch Display 7" DSI on the Verdin DSI_1 interface. The display features an internal Texas Instruments SN65DSI83 DSI-to-LVDS bridge driving a Riverdi RVT70HSLNWCA0 7" WSVGA IPS TFT LCD panel. The touch input is provided by an Ilitek ILI2132 capacitive touch controller. Link: https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-7inch-dsi Link: https://developer.toradex.com/hardware/accessories/add-ons/dsi-display-adapter/ Assisted-by: Claude:claude-sonnet-4.6 Signed-off-by: Vitor Soares Reviewed-by: Francesco Dolcini Link: https://patch.msgid.link/20260522161105.277519-19-ivitro@gmail.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 5 + ...m625-verdin-panel-cap-touch-7inch-dsi.dtso | 132 ++++++++++++++++++ 2 files changed, 137 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-panel-cap-touch-7inch-dsi.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index dc397bc693ac..14898f8ab0e2 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-yavia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-zinnia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-panel-cap-touch-10inch-dsi.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-panel-cap-touch-10inch-lvds.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-panel-cap-touch-7inch-dsi.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia-panel-cap-touch-10inch-dsi.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia.dtb @@ -223,6 +224,9 @@ k3-am625-sk-hdmi-audio-dtbs := k3-am625-sk.dtb k3-am62x-sk-hdmi-audio.dtbo k3-am625-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch-dtbs := \ k3-am625-verdin-wifi-dev.dtb \ k3-am625-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtbo +k3-am625-verdin-wifi-dev-panel-cap-touch-7inch-dsi-dtbs := \ + k3-am625-verdin-wifi-dev.dtb \ + k3-am625-verdin-panel-cap-touch-7inch-dsi.dtbo k3-am625-verdin-wifi-mallow-panel-cap-touch-10inch-lvds-dtbs := \ k3-am625-verdin-wifi-mallow.dtb \ k3-am625-verdin-panel-cap-touch-10inch-lvds.dtbo @@ -328,6 +332,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am625-sk-csi2-tevi-ov5640.dtb \ k3-am625-sk-hdmi-audio.dtb \ k3-am625-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch.dtb \ + k3-am625-verdin-wifi-dev-panel-cap-touch-7inch-dsi.dtb \ k3-am625-verdin-wifi-mallow-panel-cap-touch-10inch-lvds.dtb \ k3-am62-lp-sk-hdmi-audio.dtb \ k3-am62-lp-sk-nand.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-panel-cap-touch-7inch-dsi.dtso b/arch/arm64/boot/dts/ti/k3-am625-verdin-panel-cap-touch-7inch-dsi.dtso new file mode 100644 index 000000000000..1f44133f9ca6 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-panel-cap-touch-7inch-dsi.dtso @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Toradex Capacitive Touch Display 7" on Verdin DSI_1. + * On Dahlia (X17) and Development Board (X48), DSI_1 is exposed via a + * Samtec LSS-130 connector and requires the Toradex DSI Display Adapter + * to convert to FFC/FPC connector. + * + * https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-7inch-dsi + * https://www.toradex.com/accessories/capacitive-touch-display-7-inch-dsi + * https://developer.toradex.com/hardware/accessories/add-ons/dsi-display-adapter + * https://www.toradex.com/accessories/verdin-dsi-display-adapter + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + backlight_pwm3: backlight-pwm3 { + compatible = "pwm-backlight"; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + power-supply = <®_3v3>; + /* Verdin PWM_3_DSI (SODIMM 19) - PWM_3_DSI_LVDS */ + pwms = <&epwm1 0 6666667 0>; + }; + + panel-lvds-bridge { + compatible = "riverdi,rvt70hslnwca0", "panel-lvds"; + backlight = <&backlight_pwm3>; + data-mapping = "vesa-24"; + height-mm = <86>; + width-mm = <154>; + + panel-timing { + clock-frequency = <51200000>; + de-active = <1>; + hactive = <1024>; + hback-porch = <160 160 160>; + hfront-porch = <16 160 216>; + hsync-active = <0>; + hsync-len = <1 5 140>; + pixelclk-active = <1>; + vactive = <600>; + vback-porch = <23 23 23>; + vfront-porch = <1 12 126>; + vsync-active = <0>; + vsync-len = <1 10 20>; + }; + + port { + panel_lvds_bridge_in: endpoint { + remote-endpoint = <&dsi_lvds_bridge_out>; + }; + }; + }; +}; + +&dsi_bridge { + status = "okay"; +}; + +&dsi_bridge_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi_bridge_out: endpoint { + remote-endpoint = <&dsi_lvds_bridge_in>; + }; + }; +}; + +&dss { + status = "okay"; +}; + +/* Verdin I2C_2_DSI */ +&main_i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + bridge@2c { + compatible = "ti,sn65dsi83"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dsi1_bkl_en>; + /* Verdin GPIO_10_DSI (SODIMM 21) - DSI_1_BKL_EN */ + enable-gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_lvds_bridge_in: endpoint { + remote-endpoint = <&dsi_bridge_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@2 { + reg = <2>; + + dsi_lvds_bridge_out: endpoint { + remote-endpoint = <&panel_lvds_bridge_in>; + }; + }; + }; + }; + + touchscreen@41 { + compatible = "ilitek,ili2132"; + reg = <0x41>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dsi1_int>, <&pinctrl_i2s_2_bclk_gpio>; + /* Verdin GPIO_9_DSI (SODIMM 17) - TOUCH_INT# */ + interrupt-parent = <&main_gpio1>; + interrupts = <49 IRQ_TYPE_EDGE_RISING>; + /* Verdin I2S_2_BCLK (SODIMM 42) - TOUCH_RESET# */ + reset-gpios = <&main_gpio0 35 GPIO_ACTIVE_LOW>; + }; +}; From a8891ba79990aded756e8bb92ebb690a4da6dab2 Mon Sep 17 00:00:00 2001 From: Vitor Soares Date: Fri, 22 May 2026 17:11:11 +0100 Subject: [PATCH 483/665] arm64: dts: ti: k3-am62-verdin: Add NAU8822 Bridge Tied Load Add a device tree overlay enabling Bridge Tied Load (BTL) mode on the Nuvoton NAU8822 audio codec present on the Verdin Development Board. In BTL mode, the two loudspeaker outputs are bridged to deliver higher output power on the X28 speaker connector. Assisted-by: Claude:claude-sonnet-4.6 Signed-off-by: Vitor Soares Reviewed-by: Francesco Dolcini Link: https://patch.msgid.link/20260522161105.277519-20-ivitro@gmail.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 4 ++++ .../dts/ti/k3-am625-verdin-dev-nau8822-btl.dtso | 14 ++++++++++++++ 2 files changed, 18 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-dev-nau8822-btl.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 14898f8ab0e2..a1083c0b2502 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay-csi2-tevi-ov5640.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-tqma62xx-mba62xx.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dev-nau8822-btl.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dsi-to-hdmi.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dahlia-dsi-to-hdmi.dtb @@ -224,6 +225,8 @@ k3-am625-sk-hdmi-audio-dtbs := k3-am625-sk.dtb k3-am62x-sk-hdmi-audio.dtbo k3-am625-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch-dtbs := \ k3-am625-verdin-wifi-dev.dtb \ k3-am625-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtbo +k3-am625-verdin-wifi-dev-nau8822-btl-dtbs := k3-am625-verdin-wifi-dev.dtb \ + k3-am625-verdin-dev-nau8822-btl.dtbo k3-am625-verdin-wifi-dev-panel-cap-touch-7inch-dsi-dtbs := \ k3-am625-verdin-wifi-dev.dtb \ k3-am625-verdin-panel-cap-touch-7inch-dsi.dtbo @@ -332,6 +335,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am625-sk-csi2-tevi-ov5640.dtb \ k3-am625-sk-hdmi-audio.dtb \ k3-am625-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch.dtb \ + k3-am625-verdin-wifi-dev-nau8822-btl.dtb \ k3-am625-verdin-wifi-dev-panel-cap-touch-7inch-dsi.dtb \ k3-am625-verdin-wifi-mallow-panel-cap-touch-10inch-lvds.dtb \ k3-am62-lp-sk-hdmi-audio.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-dev-nau8822-btl.dtso b/arch/arm64/boot/dts/ti/k3-am625-verdin-dev-nau8822-btl.dtso new file mode 100644 index 000000000000..e4b662519a6b --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-dev-nau8822-btl.dtso @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Enable Bridge Tied Load (BTL) speaker mode on the Verdin Development Board, + * combining the two loudspeaker outputs for higher output power. + */ + +/dts-v1/; +/plugin/; + +&nau8822_1a { + nuvoton,spk-btl; +}; From ca61bcec3e8a52ad2bf8b02f9244df1d47447ffa Mon Sep 17 00:00:00 2001 From: Vitor Soares Date: Fri, 22 May 2026 17:11:12 +0100 Subject: [PATCH 484/665] arm64: dts: ti: k3-am62-verdin: Reserve UART_4 for Cortex-M4F Add a device tree overlay reserving AM62 MCU_UART0 (Verdin UART_4) for use by the Cortex-M4F co-processor as its debug UART. Assisted-by: Claude:claude-sonnet-4.6 Signed-off-by: Vitor Soares Reviewed-by: Francesco Dolcini Link: https://patch.msgid.link/20260522161105.277519-21-ivitro@gmail.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 4 ++++ .../boot/dts/ti/k3-am625-verdin-uart4-mcu.dtso | 13 +++++++++++++ 2 files changed, 17 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-uart4-mcu.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index a1083c0b2502..31c9bc1d48b1 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -44,6 +44,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-zinnia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-panel-cap-touch-10inch-dsi.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-panel-cap-touch-10inch-lvds.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-panel-cap-touch-7inch-dsi.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-uart4-mcu.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia-panel-cap-touch-10inch-dsi.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia.dtb @@ -230,6 +231,8 @@ k3-am625-verdin-wifi-dev-nau8822-btl-dtbs := k3-am625-verdin-wifi-dev.dtb \ k3-am625-verdin-wifi-dev-panel-cap-touch-7inch-dsi-dtbs := \ k3-am625-verdin-wifi-dev.dtb \ k3-am625-verdin-panel-cap-touch-7inch-dsi.dtbo +k3-am625-verdin-wifi-dev-uart4-mcu-dtbs := k3-am625-verdin-wifi-dev.dtb \ + k3-am625-verdin-uart4-mcu.dtbo k3-am625-verdin-wifi-mallow-panel-cap-touch-10inch-lvds-dtbs := \ k3-am625-verdin-wifi-mallow.dtb \ k3-am625-verdin-panel-cap-touch-10inch-lvds.dtbo @@ -337,6 +340,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am625-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch.dtb \ k3-am625-verdin-wifi-dev-nau8822-btl.dtb \ k3-am625-verdin-wifi-dev-panel-cap-touch-7inch-dsi.dtb \ + k3-am625-verdin-wifi-dev-uart4-mcu.dtb \ k3-am625-verdin-wifi-mallow-panel-cap-touch-10inch-lvds.dtb \ k3-am62-lp-sk-hdmi-audio.dtb \ k3-am62-lp-sk-nand.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-uart4-mcu.dtso b/arch/arm64/boot/dts/ti/k3-am625-verdin-uart4-mcu.dtso new file mode 100644 index 000000000000..e263809cdf74 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-uart4-mcu.dtso @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Verdin AM62 Cortex-M4F debug UART + */ + +/dts-v1/; +/plugin/; + +&mcu_uart0 { + status = "reserved"; +}; From f63de43a0d6f13874b6c20af0ca4726f7a5327f8 Mon Sep 17 00:00:00 2001 From: Vitor Soares Date: Fri, 22 May 2026 17:11:13 +0100 Subject: [PATCH 485/665] arm64: dts: ti: k3-am62-verdin: Add Toradex OV5640 CSI Cameras Add device tree overlays for the Toradex OV5640 CSI Cameras on Verdin CSI_1. Two variants are supported: the current CSI Camera Set 5MP OV5640 with a 27 MHz oscillator and the legacy CSI Camera Module 5MP OV5640 with a 24 MHz oscillator. Link: https://developer.toradex.com/hardware/accessories/cameras/csi-camera-module-5mp-ov5640-arducam Link: https://developer.toradex.com/hardware/legacy-products/other/csi-camera-module-5mp-ov5640/ Assisted-by: Claude:claude-sonnet-4.6 Signed-off-by: Vitor Soares Reviewed-by: Francesco Dolcini Link: https://patch.msgid.link/20260522161105.277519-22-ivitro@gmail.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 8 +++ .../dts/ti/k3-am625-verdin-ov5640-24mhz.dtso | 17 +++++ .../boot/dts/ti/k3-am625-verdin-ov5640.dtsi | 71 +++++++++++++++++++ .../boot/dts/ti/k3-am625-verdin-ov5640.dtso | 18 +++++ 4 files changed, 114 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-ov5640-24mhz.dtso create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-ov5640.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-ov5640.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 31c9bc1d48b1..60844951c9ce 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -41,6 +41,8 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-ivy.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-mallow.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-yavia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-zinnia.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-ov5640-24mhz.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-ov5640.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-panel-cap-touch-10inch-dsi.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-panel-cap-touch-10inch-lvds.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-panel-cap-touch-7inch-dsi.dtbo @@ -228,6 +230,10 @@ k3-am625-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch-dtbs := \ k3-am625-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtbo k3-am625-verdin-wifi-dev-nau8822-btl-dtbs := k3-am625-verdin-wifi-dev.dtb \ k3-am625-verdin-dev-nau8822-btl.dtbo +k3-am625-verdin-wifi-dev-ov5640-24mhz-dtbs := k3-am625-verdin-wifi-dev.dtb \ + k3-am625-verdin-ov5640-24mhz.dtbo +k3-am625-verdin-wifi-dev-ov5640-dtbs := k3-am625-verdin-wifi-dev.dtb \ + k3-am625-verdin-ov5640.dtbo k3-am625-verdin-wifi-dev-panel-cap-touch-7inch-dsi-dtbs := \ k3-am625-verdin-wifi-dev.dtb \ k3-am625-verdin-panel-cap-touch-7inch-dsi.dtbo @@ -339,6 +345,8 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am625-sk-hdmi-audio.dtb \ k3-am625-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch.dtb \ k3-am625-verdin-wifi-dev-nau8822-btl.dtb \ + k3-am625-verdin-wifi-dev-ov5640-24mhz.dtb \ + k3-am625-verdin-wifi-dev-ov5640.dtb \ k3-am625-verdin-wifi-dev-panel-cap-touch-7inch-dsi.dtb \ k3-am625-verdin-wifi-dev-uart4-mcu.dtb \ k3-am625-verdin-wifi-mallow-panel-cap-touch-10inch-lvds.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-ov5640-24mhz.dtso b/arch/arm64/boot/dts/ti/k3-am625-verdin-ov5640-24mhz.dtso new file mode 100644 index 000000000000..7089336fa5b4 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-ov5640-24mhz.dtso @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Toradex CSI Camera Module 5MP OV5640 on Verdin CSI_1. + * + * https://developer.toradex.com/hardware/legacy-products/other/csi-camera-module-5mp-ov5640/ + */ + +/dts-v1/; +/plugin/; + +#include "k3-am625-verdin-ov5640.dtsi" + +&clk_ov5640_osc { + clock-frequency = <24000000>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-ov5640.dtsi b/arch/arm64/boot/dts/ti/k3-am625-verdin-ov5640.dtsi new file mode 100644 index 000000000000..eb3df9d85517 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-ov5640.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Common device tree include for Toradex OV5640 CSI camera on Verdin CSI_1. + */ + +#include + +&{/} { + clk_ov5640_osc: ov5640-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + regulator_camera: regulator-camera { + compatible = "regulator-fixed"; + /* Verdin GPIO_8_CSI (SODIMM 222) - CAM_1_CON_PWRCTRL */ + gpio = <&main_gpio0 42 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "V_CSI"; + startup-delay-us = <5000>; + }; +}; + +&csi0_port0 { + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; +}; + +&dphy0 { + status = "okay"; +}; + +&main_i2c3 { + #address-cells = <1>; + #size-cells = <0>; + + camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + + clocks = <&clk_ov5640_osc>; + clock-names = "xclk"; + AVDD-supply = <®ulator_camera>; + DOVDD-supply = <®ulator_camera>; + DVDD-supply = <®ulator_camera>; + /* Verdin GPIO_6 (SODIMM 218) - CAM_1_CON_PWRDWN */ + powerdown-gpios = <&main_gpio0 36 GPIO_ACTIVE_HIGH>; + /* Verdin GPIO_5 (SODIMM 216) - CAM_1_CON_RST */ + reset-gpios = <&main_gpio0 40 GPIO_ACTIVE_LOW>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-ov5640.dtso b/arch/arm64/boot/dts/ti/k3-am625-verdin-ov5640.dtso new file mode 100644 index 000000000000..e7f02cfaa94f --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-ov5640.dtso @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Toradex CSI Camera Set 5MP OV5640 on Verdin CSI_1. + * + * https://developer.toradex.com/hardware/accessories/cameras/csi-camera-module-5mp-ov5640-arducam + * https://www.toradex.com/accessories/csi-camera-ov5640 + */ + +/dts-v1/; +/plugin/; + +#include "k3-am625-verdin-ov5640.dtsi" + +&clk_ov5640_osc { + clock-frequency = <27000000>; +}; From a63211b0b7c9cea098ab954bbafec31982c89f57 Mon Sep 17 00:00:00 2001 From: Vitor Soares Date: Fri, 22 May 2026 17:11:14 +0100 Subject: [PATCH 486/665] arm64: dts: ti: k3-am62-verdin: Add Toradex Verdin Mezzanine CAN Add a device tree overlay enabling AM62 MCU_MCAN1 on the Toradex Verdin Development Board with Verdin AM62 Mezzanine expansion board. MCU_MCAN1 is exposed on the Mezzanine CAN Header (J13), Pin 3 (CAN1_CONN_N) and Pin 4 (CAN1_CONN_P). Assisted-by: Claude:claude-sonnet-4.6 Signed-off-by: Vitor Soares Reviewed-by: Francesco Dolcini Link: https://patch.msgid.link/20260522161105.277519-23-ivitro@gmail.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 4 +++ .../ti/k3-am625-verdin-dev-mezzanine-can.dtso | 28 +++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-dev-mezzanine-can.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 60844951c9ce..90bb3b0522d3 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay-csi2-tevi-ov5640.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-tqma62xx-mba62xx.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dev-mezzanine-can.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dev-nau8822-btl.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dsi-to-hdmi.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtbo @@ -228,6 +229,8 @@ k3-am625-sk-hdmi-audio-dtbs := k3-am625-sk.dtb k3-am62x-sk-hdmi-audio.dtbo k3-am625-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch-dtbs := \ k3-am625-verdin-wifi-dev.dtb \ k3-am625-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtbo +k3-am625-verdin-wifi-dev-mezzanine-can-dtbs := k3-am625-verdin-wifi-dev.dtb \ + k3-am625-verdin-dev-mezzanine-can.dtbo k3-am625-verdin-wifi-dev-nau8822-btl-dtbs := k3-am625-verdin-wifi-dev.dtb \ k3-am625-verdin-dev-nau8822-btl.dtbo k3-am625-verdin-wifi-dev-ov5640-24mhz-dtbs := k3-am625-verdin-wifi-dev.dtb \ @@ -344,6 +347,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am625-sk-csi2-tevi-ov5640.dtb \ k3-am625-sk-hdmi-audio.dtb \ k3-am625-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch.dtb \ + k3-am625-verdin-wifi-dev-mezzanine-can.dtb \ k3-am625-verdin-wifi-dev-nau8822-btl.dtb \ k3-am625-verdin-wifi-dev-ov5640-24mhz.dtb \ k3-am625-verdin-wifi-dev-ov5640.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-dev-mezzanine-can.dtso b/arch/arm64/boot/dts/ti/k3-am625-verdin-dev-mezzanine-can.dtso new file mode 100644 index 000000000000..7ebf60d27c3c --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-dev-mezzanine-can.dtso @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Enable AM62 MCU_MCAN1 exposed on Toradex Verdin Development Board with + * Verdin AM62 Mezzanine expansion board on CAN Header (J13), + * Pin 3 (CAN1_CONN_N) and Pin 4 (CAN1_CONN_P). + */ + +/dts-v1/; +/plugin/; + +#include "k3-pinctrl.h" + +&mcu_pmx0 { + pinctrl_mcu_mcan1: mcu-mcan1-default-pins { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0040, PIN_INPUT, 0) /* (D4) MCU_MCAN1_RX (SODIMM 116) */ + AM62X_MCU_IOPAD(0x003c, PIN_OUTPUT, 0) /* (E5) MCU_MCAN1_TX (SODIMM 128) */ + >; + }; +}; + +&mcu_mcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_mcan1>; + status = "okay"; +}; From 837c7dbc5bee260768333c1f985dd0688b5aff8a Mon Sep 17 00:00:00 2001 From: Vitor Soares Date: Fri, 22 May 2026 17:11:15 +0100 Subject: [PATCH 487/665] arm64: dts: ti: k3-am62-verdin: Add Mezzanine with Toradex Display 10.1" LVDS Add a device tree overlay enabling the Toradex Capacitive Touch Display 10.1" LVDS on the Verdin Development Board with Verdin AM62 Mezzanine expansion board. The panel connects via the AM62 OLDI0 on the Mezzanine LVDS interface (J10). The panel is a LogicTechno LT170410-2WHC 10.1" WXGA IPS LCD and the touch input is provided by an Atmel MaxTouch capacitive touch controller. Link: https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-lvds Assisted-by: Claude:claude-sonnet-4.6 Signed-off-by: Vitor Soares Reviewed-by: Francesco Dolcini Link: https://patch.msgid.link/20260522161105.277519-24-ivitro@gmail.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 5 + ...mezzanine-panel-cap-touch-10inch-lvds.dtso | 98 +++++++++++++++++++ 2 files changed, 103 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-dev-mezzanine-panel-cap-touch-10inch-lvds.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 90bb3b0522d3..371f9a043fe5 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -30,6 +30,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-tqma62xx-mba62xx.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dev-mezzanine-can.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dev-mezzanine-panel-cap-touch-10inch-lvds.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dev-nau8822-btl.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dsi-to-hdmi.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtbo @@ -231,6 +232,9 @@ k3-am625-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch-dtbs := \ k3-am625-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtbo k3-am625-verdin-wifi-dev-mezzanine-can-dtbs := k3-am625-verdin-wifi-dev.dtb \ k3-am625-verdin-dev-mezzanine-can.dtbo +k3-am625-verdin-wifi-dev-mezzanine-panel-cap-touch-10inch-lvds-dtbs := \ + k3-am625-verdin-wifi-dev.dtb \ + k3-am625-verdin-dev-mezzanine-panel-cap-touch-10inch-lvds.dtbo k3-am625-verdin-wifi-dev-nau8822-btl-dtbs := k3-am625-verdin-wifi-dev.dtb \ k3-am625-verdin-dev-nau8822-btl.dtbo k3-am625-verdin-wifi-dev-ov5640-24mhz-dtbs := k3-am625-verdin-wifi-dev.dtb \ @@ -348,6 +352,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am625-sk-hdmi-audio.dtb \ k3-am625-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch.dtb \ k3-am625-verdin-wifi-dev-mezzanine-can.dtb \ + k3-am625-verdin-wifi-dev-mezzanine-panel-cap-touch-10inch-lvds.dtb \ k3-am625-verdin-wifi-dev-nau8822-btl.dtb \ k3-am625-verdin-wifi-dev-ov5640-24mhz.dtb \ k3-am625-verdin-wifi-dev-ov5640.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-dev-mezzanine-panel-cap-touch-10inch-lvds.dtso b/arch/arm64/boot/dts/ti/k3-am625-verdin-dev-mezzanine-panel-cap-touch-10inch-lvds.dtso new file mode 100644 index 000000000000..83fc4f3a24f5 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-dev-mezzanine-panel-cap-touch-10inch-lvds.dtso @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Toradex Capacitive Touch Display 10.1" LVDS on the Verdin AM62 Mezzanine + * LVDS interface (J10), used with the Verdin Development Board. + * + * https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-lvds + * https://www.toradex.com/accessories/capacitive-touch-display-10.1-inch-lvds + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + backlight_pwm2: backlight-pwm2 { + compatible = "pwm-backlight"; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + /* Verdin GPIO_4 (SODIMM 212) - LVDS_BKL_EN */ + enable-gpios = <&mcu_gpio0 4 GPIO_ACTIVE_HIGH>; + /* Verdin PWM_2 (SODIMM 16) - LVDS_PWM */ + pwms = <&epwm0 1 6666667 PWM_POLARITY_INVERTED>; + }; + + panel-lvds-native { + compatible = "logictechno,lt170410-2whc"; + backlight = <&backlight_pwm2>; + power-supply = <®_3v3_lvds>; + + port { + panel_lvds_native_in: endpoint { + remote-endpoint = <&oldi0_out>; + }; + }; + }; + + reg_3v3_lvds: regulator-3v3-lvds { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_LVDS"; + }; +}; + +&dss { + status = "okay"; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* DSS VP1: internal DPI output to OLDIx */ + port@0 { + reg = <0>; + + dss0_out: endpoint { + remote-endpoint = <&oldi0_in>; + }; + }; +}; + +/* Verdin I2C_2_DSI */ +&main_i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + /* Verdin GPIO_3 (SODIMM 210) - LVDS_TOUCH_INT# */ + interrupt-parent = <&mcu_gpio0>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + /* Verdin GPIO_2 (SODIMM 208) - LVDS_TOUCH_RST# */ + reset-gpios = <&mcu_gpio0 2 GPIO_ACTIVE_LOW>; + }; +}; + +&oldi0 { + status = "okay"; +}; + +&oldi0_port0 { + oldi0_in: endpoint { + remote-endpoint = <&dss0_out>; + }; +}; + +&oldi0_port1 { + oldi0_out: endpoint { + remote-endpoint = <&panel_lvds_native_in>; + }; +}; From b4a789799d4c2be03a2c9a4e06f3ea817bb04416 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Tue, 26 May 2026 15:22:58 -0400 Subject: [PATCH 488/665] riscv: dts: spacemit: k3: Add Ziccrse extension for X100 cores Add the Ziccrse ISA extension to all eight X100 cores. Ziccrse provides a forward progress guarantee on LR/SC sequences in main memory regions with cacheability and coherence PMAs. The SpacemiT X100 core supports it per the SpacemiT K3 hardware specification. Signed-off-by: Guodong Xu Reviewed-by: Yixun lan Link: https://patch.msgid.link/20260526-k3-ziccrse-v1-1-c759792ca3a3@riscstar.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index fa459bc95688..223e66721bf9 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -36,7 +36,7 @@ cpu_0: cpu@0 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin", "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", - "ziccamoa", "ziccif", "zicclsm", "zicntr", + "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", @@ -77,7 +77,7 @@ cpu_1: cpu@1 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin", "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", - "ziccamoa", "ziccif", "zicclsm", "zicntr", + "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", @@ -118,7 +118,7 @@ cpu_2: cpu@2 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin", "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", - "ziccamoa", "ziccif", "zicclsm", "zicntr", + "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", @@ -159,7 +159,7 @@ cpu_3: cpu@3 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin", "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", - "ziccamoa", "ziccif", "zicclsm", "zicntr", + "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", @@ -200,7 +200,7 @@ cpu_4: cpu@4 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin", "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", - "ziccamoa", "ziccif", "zicclsm", "zicntr", + "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", @@ -241,7 +241,7 @@ cpu_5: cpu@5 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin", "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", - "ziccamoa", "ziccif", "zicclsm", "zicntr", + "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", @@ -282,7 +282,7 @@ cpu_6: cpu@6 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin", "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", - "ziccamoa", "ziccif", "zicclsm", "zicntr", + "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", @@ -323,7 +323,7 @@ cpu_7: cpu@7 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin", "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", - "ziccamoa", "ziccif", "zicclsm", "zicntr", + "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", From 3ea695eb111fc5a7ffddd21d5c3fee6d82560413 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Mon, 18 May 2026 20:58:16 +0000 Subject: [PATCH 489/665] dts: riscv: spacemit: k3: Fix I/O power settings SpacemiT K3 SoC support dual-voltage I/O power domain, while initially configure to 3.3v, and need to access register from APBC space to switch to 1.8v domain. Fix the GMAC0's I/O pins 1.8v switch failure that will result a broken ethernet driver. Fixes: d8944577496b ("riscv: dts: spacemit: k3: add pinctrl support") Reported-by: Han Gao Link: https://patch.msgid.link/20260518-07-dts-pinctrl-io-power-v1-1-abe19c14a726@kernel.org Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index 223e66721bf9..19fc9b49668e 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -1065,6 +1065,7 @@ pinctrl: pinctrl@d401e000 { clocks = <&syscon_apbc CLK_APBC_AIB>, <&syscon_apbc CLK_APBC_AIB_BUS>; clock-names = "func", "bus"; + spacemit,apbc = <&syscon_apbc>; }; uart10: serial@d401f000 { From 20550601bf4c23effa013a5f37e5250618869e87 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Wed, 27 May 2026 21:24:29 +0100 Subject: [PATCH 490/665] MAINTAINERS: Add Peter Griffin as a co-maintainer of Samsung Exynos SoCs As Google Tensor gs101 is based off a Samsung Exynos design I've been working on many of these drivers and have an interest in helping maintain this code. Signed-off-by: Peter Griffin Link: https://patch.msgid.link/20260527-samsung-soc-maintainer-v1-1-40829c3fb133@linaro.org Acked-by: Sylwester Nawrocki # Samsung clocks Link: https://patch.msgid.link/20260527-samsung-clk-maintainer-v1-1-97b179224ca5@linaro.org Signed-off-by: Krzysztof Kozlowski --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 2fb1c75afd16..e8218c2749b7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3428,6 +3428,7 @@ N: rockchip ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES M: Krzysztof Kozlowski +M: Peter Griffin R: Alim Akhtar L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-samsung-soc@vger.kernel.org @@ -23802,6 +23803,7 @@ SAMSUNG SOC CLOCK DRIVERS M: Krzysztof Kozlowski M: Sylwester Nawrocki M: Chanwoo Choi +M: Peter Griffin R: Alim Akhtar L: linux-samsung-soc@vger.kernel.org S: Maintained From 1e25ddddfa1e39300fa5e339275e0a469aa41899 Mon Sep 17 00:00:00 2001 From: Tommaso Merciai Date: Wed, 8 Apr 2026 12:37:03 +0200 Subject: [PATCH 491/665] arm64: dts: renesas: r9a09g047: Add fcpvd{0,1} nodes Add fcpvd{0,1} nodes to the RZ/G3E SoC DTSI. Reviewed-by: Geert Uytterhoeven Signed-off-by: Tommaso Merciai Reviewed-by: Laurent Pinchart Link: https://patch.msgid.link/1ba6a98ace4ad9525d054cbaa308d3aeeecfa22a.1775636898.git.tommaso.merciai.xr@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 4267b10937f3..92a3491fb7ea 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -1585,6 +1585,30 @@ csi2cru: endpoint@0 { }; }; }; + + fcpvd0: fcp@16470000 { + compatible = "renesas,r9a09g047-fcpvd", + "renesas,fcpv"; + reg = <0 0x16470000 0 0x10000>; + clocks = <&cpg CPG_MOD 0xed>, + <&cpg CPG_MOD 0xee>, + <&cpg CPG_MOD 0xef>; + clock-names = "aclk", "pclk", "vclk"; + resets = <&cpg 0xdc>; + power-domains = <&cpg>; + }; + + fcpvd1: fcp@164a0000 { + compatible = "renesas,r9a09g047-fcpvd", + "renesas,fcpv"; + reg = <0 0x164a0000 0 0x10000>; + clocks = <&cpg CPG_MOD 0x1a8>, + <&cpg CPG_MOD 0x1a9>, + <&cpg CPG_MOD 0x1aa>; + clock-names = "aclk", "pclk", "vclk"; + resets = <&cpg 0x11e>; + power-domains = <&cpg>; + }; }; stmmac_axi_setup: stmmac-axi-config { From b6f8dd27e9c5721d84e8e6235065ef094fb3bdd3 Mon Sep 17 00:00:00 2001 From: Tommaso Merciai Date: Wed, 8 Apr 2026 12:37:04 +0200 Subject: [PATCH 492/665] arm64: dts: renesas: r9a09g047: Add vspd{0,1} nodes Add vspd{0,1} nodes to the RZ/G3E SoC DTSI. Reviewed-by: Geert Uytterhoeven Signed-off-by: Tommaso Merciai Reviewed-by: Laurent Pinchart Link: https://patch.msgid.link/46547aaff3cdb8ea6e17cf1fdec699d83a1cd71b.1775636898.git.tommaso.merciai.xr@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 92a3491fb7ea..b48da8534a3d 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -1609,6 +1609,34 @@ fcpvd1: fcp@164a0000 { resets = <&cpg 0x11e>; power-domains = <&cpg>; }; + + vspd0: vsp@16480000 { + compatible = "renesas,r9a09g047-vsp2", + "renesas,r9a07g044-vsp2"; + reg = <0 0x16480000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 0xed>, + <&cpg CPG_MOD 0xee>, + <&cpg CPG_MOD 0xef>; + clock-names = "aclk", "pclk", "vclk"; + resets = <&cpg 0xdc>; + power-domains = <&cpg>; + renesas,fcp = <&fcpvd0>; + }; + + vspd1: vsp@164b0000 { + compatible = "renesas,r9a09g047-vsp2", + "renesas,r9a07g044-vsp2"; + reg = <0 0x164b0000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 0x1a8>, + <&cpg CPG_MOD 0x1a9>, + <&cpg CPG_MOD 0x1aa>; + clock-names = "aclk", "pclk", "vclk"; + resets = <&cpg 0x11e>; + power-domains = <&cpg>; + renesas,fcp = <&fcpvd1>; + }; }; stmmac_axi_setup: stmmac-axi-config { From 5c63f3e78e9483bcd6109f744073f51b55251ce3 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Fri, 10 Apr 2026 19:35:28 +0300 Subject: [PATCH 493/665] arm64: dts: renesas: r9a07g0{43,44,54}: Remove TCIU8 interrupt from MTU3 The TCIU8 interrupt used to be documented in earlier revisions of the user manuals, but has since been removed. The corresponding entry is now marked as reserved in the interrupt mapping tables of all supported SoCs. - Page 486, Table 8.2 Interrupt mapping (7/13) in the Renesas RZ/G2UL Rev.1.40 User Manual - Page 363, Table 8.2 Interrupt Mapping (6/13) in the Renesas RZ/Five Rev.1.30 User Manual - Page 528, Table 8.2 Interrupt mapping (7/13) in the Renesas RZ/G2L and RZ/G2LC Rev.1.50 User Manual - Page 540, Table 8.2 Interrupt mapping (7/13) in the Renesas RZ/V2L Rev.1.50 User Manual Remove the TCIU8 interrupt. This does not cause any breakage as the driver does not make use of the interrupts. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260410163530.383818-9-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 5 ++--- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 5 ++--- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 5 ++--- 3 files changed, 6 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index ded4f1f11d60..38aebeeea464 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -120,8 +120,7 @@ mtu3: timer@10001200 { , , , - , - ; + ; interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", "tciv0", "tgie0", "tgif0", "tgia1", "tgib1", "tciv1", "tciu1", @@ -136,7 +135,7 @@ mtu3: timer@10001200 { "tgia7", "tgib7", "tgic7", "tgid7", "tciv7", "tgia8", "tgib8", "tgic8", "tgid8", - "tciv8", "tciu8"; + "tciv8"; clocks = <&cpg CPG_MOD R9A07G043_MTU_X_MCK_MTU3>; power-domains = <&cpg>; resets = <&cpg R9A07G043_MTU_X_PRESET_MTU3>; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index cb0c9550aa03..873b52b168bc 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -220,8 +220,7 @@ mtu3: timer@10001200 { , , , - , - ; + ; interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", "tciv0", "tgie0", "tgif0", "tgia1", "tgib1", "tciv1", "tciu1", @@ -236,7 +235,7 @@ mtu3: timer@10001200 { "tgia7", "tgib7", "tgic7", "tgid7", "tciv7", "tgia8", "tgib8", "tgic8", "tgid8", - "tciv8", "tciu8"; + "tciv8"; clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>; power-domains = <&cpg>; resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>; diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 7a3e5b6a685f..587fab0ceb3f 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -220,8 +220,7 @@ mtu3: timer@10001200 { , , , - , - ; + ; interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", "tciv0", "tgie0", "tgif0", "tgia1", "tgib1", "tciv1", "tciu1", @@ -236,7 +235,7 @@ mtu3: timer@10001200 { "tgia7", "tgib7", "tgic7", "tgid7", "tciv7", "tgia8", "tgib8", "tgic8", "tgid8", - "tciv8", "tciu8"; + "tciv8"; clocks = <&cpg CPG_MOD R9A07G054_MTU_X_MCK_MTU3>; power-domains = <&cpg>; resets = <&cpg R9A07G054_MTU_X_PRESET_MTU3>; From f7abc1cf249fce5e9a7e1a7263c03cae55ffba39 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Fri, 10 Apr 2026 19:35:29 +0300 Subject: [PATCH 494/665] arm64: dts: renesas: r9a09g077: Add MTU3 support The Renesas RZ/T2H (R9A09G077) SoC has an MTU3 block. Add support for it. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260410163530.383818-10-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 68 ++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi index 3761551c9647..fe5d206d4def 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -1116,6 +1116,74 @@ gic: interrupt-controller@83000000 { interrupts = ; }; + mtu3: timer@90001200 { + compatible = "renesas,r9a09g077-mtu3", + "renesas,rz-mtu3"; + reg = <0 0x90001200 0 0xb00>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", + "tciv0", "tgie0", "tgif0", + "tgia1", "tgib1", "tciv1", "tciu1", + "tgia2", "tgib2", "tciv2", "tciu2", + "tgia3", "tgib3", "tgic3", "tgid3", + "tciv3", + "tgia4", "tgib4", "tgic4", "tgid4", + "tciv4", + "tgiu5", "tgiv5", "tgiw5", + "tgia6", "tgib6", "tgic6", "tgid6", + "tciv6", + "tgia7", "tgib7", "tgic7", "tgid7", + "tciv7", + "tgia8", "tgib8", "tgic8", "tgid8", + "tciv8"; + clocks = <&cpg CPG_MOD 200>; + power-domains = <&cpg>; + #pwm-cells = <3>; + status = "disabled"; + }; + adc0: adc@90014000 { compatible = "renesas,r9a09g077-adc"; reg = <0 0x90014000 0 0x400>; From 893227dea79e57f43588080ca3f95abcc1d9c703 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Fri, 10 Apr 2026 19:35:30 +0300 Subject: [PATCH 495/665] arm64: dts: renesas: r9a09g087: Add MTU3 support The Renesas RZ/N2H (R9A09G087) SoC has an MTU3 block. Add support for it. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260410163530.383818-11-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 68 ++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi index f697e9698ed3..c64b532f3d23 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -1119,6 +1119,74 @@ gic: interrupt-controller@83000000 { interrupts = ; }; + mtu3: timer@90001200 { + compatible = "renesas,r9a09g087-mtu3", + "renesas,rz-mtu3"; + reg = <0 0x90001200 0 0xb00>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", + "tciv0", "tgie0", "tgif0", + "tgia1", "tgib1", "tciv1", "tciu1", + "tgia2", "tgib2", "tciv2", "tciu2", + "tgia3", "tgib3", "tgic3", "tgid3", + "tciv3", + "tgia4", "tgib4", "tgic4", "tgid4", + "tciv4", + "tgiu5", "tgiv5", "tgiw5", + "tgia6", "tgib6", "tgic6", "tgid6", + "tciv6", + "tgia7", "tgib7", "tgic7", "tgid7", + "tciv7", + "tgia8", "tgib8", "tgic8", "tgid8", + "tciv8"; + clocks = <&cpg CPG_MOD 200>; + power-domains = <&cpg>; + #pwm-cells = <3>; + status = "disabled"; + }; + adc0: adc@90014000 { compatible = "renesas,r9a09g087-adc", "renesas,r9a09g077-adc"; reg = <0 0x90014000 0 0x400>; From 85759e0e74751c1feaf245532856eb7565a00a02 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 20 Apr 2026 14:22:11 +0100 Subject: [PATCH 496/665] arm64: dts: renesas: rz-smarc-du-adv7513: Simplify DU port configuration The SoC dtsi already defines the du node with its ports hierarchy, including the du_out_rgb endpoint node under port@0. There is no need to redefine the entire ports/port@0 structure in the board-level dtsi. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260420132211.1350656-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/rz-smarc-du-adv7513.dtsi | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/rz-smarc-du-adv7513.dtsi b/arch/arm64/boot/dts/renesas/rz-smarc-du-adv7513.dtsi index f5412578ee65..dbe16908b260 100644 --- a/arch/arm64/boot/dts/renesas/rz-smarc-du-adv7513.dtsi +++ b/arch/arm64/boot/dts/renesas/rz-smarc-du-adv7513.dtsi @@ -24,19 +24,10 @@ &du { pinctrl-names = "default"; status = "okay"; +}; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - du_out_rgb: endpoint { - remote-endpoint = <&adv7513_in>; - }; - }; - }; +&du_out_rgb { + remote-endpoint = <&adv7513_in>; }; &ADV7513_PARENT_I2C { From 4c443296ff17f5670ce926f47de8ec5a1f50f857 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Fri, 1 May 2026 11:51:15 +0100 Subject: [PATCH 497/665] arm64: dts: renesas: r9a09g056: Add PCIe node Add PCIe node to Renesas RZ/V2N ("R9A09G056") SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260501105116.33452-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 69 ++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index dc5b116679c0..d6c8c39df2a4 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -1044,6 +1044,75 @@ rsci9: serial@12803000 { status = "disabled"; }; + pcie: pcie@13400000 { + compatible = "renesas,r9a09g056-pcie", "renesas,r9a09g047-pcie"; + reg = <0 0x13400000 0 0x10000>; + ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>, + <0x43000000 4 0x40000000 4 0x40000000 6 0x00000000>; + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 2 0x00000000>; + bus-range = <0x0 0xff>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "serr", "serr_cor", "serr_nonfatal", + "serr_fatal", "axi_err", "inta", + "intb", "intc", "intd", "msi", + "link_bandwidth", "pm_pme", "dma", + "pcie_evt", "msg", "all", + "link_equalization_request", + "turn_off_event", "pmu_poweroff", + "d3_event_f0", "d3_event_f1", + "cfg_pmcsr_writeclear_f0", + "cfg_pmcsr_writeclear_f1"; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie 0 0 0 0>, /* INTA */ + <0 0 0 2 &pcie 0 0 0 1>, /* INTB */ + <0 0 0 3 &pcie 0 0 0 2>, /* INTC */ + <0 0 0 4 &pcie 0 0 0 3>; /* INTD */ + clocks = <&cpg CPG_MOD 0xc4>, <&cpg CPG_MOD 0xc5>; + clock-names = "aclk", "pmu"; + resets = <&cpg 0xb2>; + reset-names = "aresetn"; + power-domains = <&cpg>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + renesas,sysc = <&sys>; + status = "disabled"; + + pcie_port0: pcie@0,0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + ranges; + device_type = "pci"; + vendor-id = <0x1912>; + device-id = <0x003b>; + #address-cells = <3>; + #size-cells = <2>; + }; + }; + i2c0: i2c@14400400 { compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; reg = <0 0x14400400 0 0x400>; From 62169c13d85c143174b61876ff60328b838e02b9 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Fri, 1 May 2026 11:51:16 +0100 Subject: [PATCH 498/665] arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable PCIe Enable the PCIE1 slot available on the RZ/V2N EVK. Note, the PCIE_REFCLK comes from 5L35023B versa clock generator, once the support for this clock generator is added, the fixed clock node can be removed and can be replaced with a reference to the clock generator. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260501105116.33452-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r9a09g056n48-rzv2n-evk.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts index 00e5455ea5ab..43ffde419d91 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts @@ -63,6 +63,12 @@ memory@48000000 { reg = <0x0 0x48000000 0x1 0xf8000000>; }; + pcie_refclk: clock-pcie-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + reg_0p8v: regulator-0p8v { compatible = "regulator-fixed"; regulator-name = "fixed-0.8V"; @@ -333,6 +339,17 @@ &ostm7 { status = "okay"; }; +&pcie { + pinctrl-0 = <&pcie_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pcie_port0 { + clocks = <&pcie_refclk>; + clock-names = "ref"; +}; + &pinctrl { eth0_pins: eth0 { pins = "ET0_TXC_TXCLK"; @@ -383,6 +400,12 @@ i2c8_pins: i2c8 { ; /* I2C8_SCL */ }; + pcie_pins: pcie { + pins = "PCIE0_RSTOUTB"; + slew-rate = <0>; + renesas,output-impedance = <2>; + }; + scif_pins: scif { pins = "SCIF_TXD", "SCIF_RXD"; renesas,output-impedance = <1>; From 5f10bbf91ea2e733ba8c5e88b1515217eb41c772 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 4 May 2026 16:37:15 +0200 Subject: [PATCH 499/665] arm64: dts: renesas: Simplify AA1024XD12 display DTO Move all differences into panel-aa104xd12.dtsi, rename OF_GRAPH links to generic lvds_panel_out and lvds_panel_in names, and parametrize the LVDS output in use using RENESAS_LVDS_OUTPUT macro. No functional change. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260504143751.42753-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- .../renesas/draak-ebisu-panel-aa104xd12.dtso | 33 +--------- .../boot/dts/renesas/panel-aa104xd12.dtsi | 62 +++++++++++++------ .../dts/renesas/salvator-panel-aa104xd12.dtso | 33 +--------- 3 files changed, 46 insertions(+), 82 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dtso b/arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dtso index 90767d74e21b..2ab7e947a05b 100644 --- a/arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dtso +++ b/arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dtso @@ -6,36 +6,5 @@ * Copyright 2021 Ideas on Board Oy */ -/dts-v1/; -/plugin/; - -&{/} { +#define RENESAS_LVDS_OUTPUT lvds1 #include "panel-aa104xd12.dtsi" -}; - -&{/panel} { - backlight = <&backlight>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds1_out>; - }; - }; -}; - -&lvds1 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - lvds1_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/panel-aa104xd12.dtsi b/arch/arm64/boot/dts/renesas/panel-aa104xd12.dtsi index 4b1f0982b9e4..11113a13a337 100644 --- a/arch/arm64/boot/dts/renesas/panel-aa104xd12.dtsi +++ b/arch/arm64/boot/dts/renesas/panel-aa104xd12.dtsi @@ -5,26 +5,52 @@ * Copyright (C) 2014 Renesas Electronics Corp. */ -panel { - compatible = "mitsubishi,aa104xd12", "panel-lvds"; +/dts-v1/; +/plugin/; - width-mm = <210>; - height-mm = <158>; - data-mapping = "jeida-18"; +&{/} { + panel { + compatible = "mitsubishi,aa104xd12", "panel-lvds"; + backlight = <&backlight>; - panel-timing { - /* 1024x768 @65Hz */ - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hsync-len = <136>; - hfront-porch = <20>; - hback-porch = <160>; - vfront-porch = <3>; - vback-porch = <29>; - vsync-len = <6>; - }; + width-mm = <210>; + height-mm = <158>; + data-mapping = "jeida-18"; - port { + panel-timing { + /* 1024x768 @65Hz */ + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hsync-len = <136>; + hfront-porch = <20>; + hback-porch = <160>; + vfront-porch = <3>; + vback-porch = <29>; + vsync-len = <6>; + }; + + port { + lvds_panel_in: endpoint { + remote-endpoint = <&lvds_panel_out>; + }; + }; + }; +}; + +&RENESAS_LVDS_OUTPUT { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + lvds_panel_out: endpoint { + remote-endpoint = <&lvds_panel_in>; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dtso b/arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dtso index 7807c3f80409..4eb3e06ce52b 100644 --- a/arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dtso +++ b/arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dtso @@ -6,36 +6,5 @@ * Copyright 2021 Ideas on Board Oy */ -/dts-v1/; -/plugin/; - -&{/} { +#define RENESAS_LVDS_OUTPUT lvds0 #include "panel-aa104xd12.dtsi" -}; - -&{/panel} { - backlight = <&backlight>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; -}; - -&lvds0 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; From e8a97edd672a5114ad50740d3c3b00f908aa6f74 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 4 May 2026 16:43:25 +0200 Subject: [PATCH 500/665] dt-bindings: clock: cirrus,cs2000-cp: Document CS2500 Document backward compatibility support for the CS2500 chip, which is a drop-in replacement for the CS2000 chip. Acked-by: Conor Dooley Acked-by: Stephen Boyd Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260504144534.43745-4-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- .../devicetree/bindings/clock/cirrus,cs2000-cp.yaml | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml b/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml index d416c374e853..ceeaa8f9fb08 100644 --- a/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml +++ b/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml @@ -11,14 +11,19 @@ maintainers: description: | The CS2000-CP is an extremely versatile system clocking device that - utilizes a programmable phase lock loop. + utilizes a programmable phase lock loop. CS2500 is a compatible + drop-in replacement for CS2000-CP. Link: https://www.cirrus.com/products/cs2000/ + Link: https://www.cirrus.com/products/cs2500/ properties: compatible: - enum: - - cirrus,cs2000-cp + oneOf: + - items: + - const: cirrus,cs2500 + - const: cirrus,cs2000-cp + - const: cirrus,cs2000-cp clocks: description: From 2cba284c0c8d115453766325a3a879aa06fe0900 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 4 May 2026 16:43:26 +0200 Subject: [PATCH 501/665] dt-bindings: soc: renesas: Document R-Car R8A779MD Geist Document the compatible value for the Renesas R-Car M3Le (R8A779MD) SoC and the Renesas Geist development board. The Renesas M3Le SoC is a register-compatible variant of the R8A77965 (M3-N) with reduced set of peripherals. The Geist board is derived from Renesas Salvator-X/XS boards, with adjustment for the R8A779MD SoC. Acked-by: Conor Dooley Reviewed-by: Geert Uytterhoeven Signed-off-by: Marek Vasut Link: https://patch.msgid.link/20260504144534.43745-5-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml index 5c22c51b1533..eeef34e3d7d0 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -473,6 +473,12 @@ properties: - const: renesas,r8a779mb - const: renesas,r8a7795 + - description: R-Car M3Le (R8A779MD) + items: + - const: renesas,geist # M3Le Geist (RTP8A779MDASKB0F10S) + - const: renesas,r8a779md + - const: renesas,r8a77965 + - description: R-Car X5H (R8A78000) items: - enum: From ad9d44ddeefd20e351a37a86e73e2667f55daa79 Mon Sep 17 00:00:00 2001 From: Nguyen Tran Date: Mon, 4 May 2026 16:43:28 +0200 Subject: [PATCH 502/665] arm64: dts: renesas: r8a779md: Add Renesas R-Car R8A779MD M3Le DTs Add support for the Renesas R-Car M3Le (R8A779MD) SoC, a variant of the R-Car M3-N (R8A77965) SoC. The Renesas M3Le SoC is a register-compatible variant of the R8A77965 (M3-N) with reduced set of peripherals. Signed-off-by: Nguyen Tran Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260504144534.43745-7-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779md.dtsi | 59 +++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779md.dtsi diff --git a/arch/arm64/boot/dts/renesas/r8a779md.dtsi b/arch/arm64/boot/dts/renesas/r8a779md.dtsi new file mode 100644 index 000000000000..f30654141341 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779md.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car M3Le (R8A779MD) SoC + * + * Copyright (C) 2025-2026 Renesas Electronics Corp. + */ + +#include "r8a77965.dtsi" + +/ { + compatible = "renesas,r8a779md", "renesas,r8a77965"; +}; + +/delete-node/ &csi20; +/delete-node/ &drif00; +/delete-node/ &drif01; +/delete-node/ &drif10; +/delete-node/ &drif11; +/delete-node/ &drif20; +/delete-node/ &drif21; +/delete-node/ &drif30; +/delete-node/ &drif31; +/delete-node/ &du; +/delete-node/ &ehci1; +/delete-node/ &hdmi0; +/delete-node/ &lvds0; +/delete-node/ &mlp; +/delete-node/ &ohci1; +/delete-node/ &pciec1; +/delete-node/ &sata; +/delete-node/ &usb2_phy1; +/delete-node/ &usb3_peri0; +/delete-node/ &usb3_phy0; +/delete-node/ &vin0csi20; +/delete-node/ &vin1csi20; +/delete-node/ &vin2csi20; +/delete-node/ &vin3csi20; +/delete-node/ &vin4csi20; +/delete-node/ &vin5csi20; +/delete-node/ &vin6csi20; +/delete-node/ &vin7csi20; +/delete-node/ &xhci0; + +&sdhi0 { + compatible = "renesas,sdhi-r8a779md", "renesas,rcar-gen3-sdhi"; +}; + +&sdhi1 { + compatible = "renesas,sdhi-r8a779md", "renesas,rcar-gen3-sdhi"; +}; + +&sdhi2 { + compatible = "renesas,sdhi-r8a779md", "renesas,rcar-gen3-sdhi"; +}; + +&sdhi3 { + compatible = "renesas,sdhi-r8a779md", "renesas,rcar-gen3-sdhi"; + no-mmc; +}; From 9f763ef2a3fb54d65570937223de327575725001 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 5 May 2026 00:56:51 +0200 Subject: [PATCH 503/665] arm64: dts: renesas: draak: Rename clk-multiplier to clock-controller Use standard clock-controller node name for the CS2000-CP. No functional change. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260504225704.115125-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/draak.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/draak.dtsi b/arch/arm64/boot/dts/renesas/draak.dtsi index c83c97d99113..c9c5c3ab06c3 100644 --- a/arch/arm64/boot/dts/renesas/draak.dtsi +++ b/arch/arm64/boot/dts/renesas/draak.dtsi @@ -435,7 +435,7 @@ adv7612_out: endpoint { }; }; - cs2000: clk-multiplier@4f { + cs2000: clock-controller@4f { #clock-cells = <0>; compatible = "cirrus,cs2000-cp"; reg = <0x4f>; From decb897f06d58434db642d695755219533fbff9f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 5 May 2026 00:56:52 +0200 Subject: [PATCH 504/665] arm64: dts: renesas: ebisu: Rename clk-multiplier to clock-controller Use standard clock-controller node name for the CS2000-CP. No functional change. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260504225704.115125-2-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/ebisu.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/ebisu.dtsi b/arch/arm64/boot/dts/renesas/ebisu.dtsi index ba564aa09866..add60324e0e4 100644 --- a/arch/arm64/boot/dts/renesas/ebisu.dtsi +++ b/arch/arm64/boot/dts/renesas/ebisu.dtsi @@ -512,7 +512,7 @@ ak4613: codec@10 { asahi-kasei,out6-single-end; }; - cs2000: clk-multiplier@4f { + cs2000: clock-controller@4f { #clock-cells = <0>; compatible = "cirrus,cs2000-cp"; reg = <0x4f>; From cced1504d2c2505a97caa03ce6aa8016de00bc24 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 5 May 2026 00:56:53 +0200 Subject: [PATCH 505/665] arm64: dts: renesas: hihope: Rename clk-multiplier to clock-controller Use standard clock-controller node name for the CS2000-CP. No functional change. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260504225704.115125-3-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/hihope-rev4.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi b/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi index 8bfc66b8ef86..acce3c0452f4 100644 --- a/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi @@ -50,7 +50,7 @@ &i2c2 { pinctrl-names = "default"; status = "okay"; - cs2000: clk-multiplier@4f { + cs2000: clock-controller@4f { #clock-cells = <0>; compatible = "cirrus,cs2000-cp"; reg = <0x4f>; From b008ad40670b67e1cf6cfaa0692d830fc70dd94a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 5 May 2026 00:56:54 +0200 Subject: [PATCH 506/665] arm64: dts: renesas: salvator-common: Rename clk-multiplier to clock-controller Use standard clock-controller node name for the CS2000-CP. No functional change. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260504225704.115125-4-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/salvator-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index 0b29bf9564eb..b1f56efe25d9 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -507,7 +507,7 @@ ak4613_endpoint: endpoint { }; }; - cs2000: clk-multiplier@4f { + cs2000: clock-controller@4f { #clock-cells = <0>; compatible = "cirrus,cs2000-cp"; reg = <0x4f>; From 5acc8d529a2980e43126ae0091b45310ead9036d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 5 May 2026 00:56:55 +0200 Subject: [PATCH 507/665] arm64: dts: renesas: ulcb: Rename clk-multiplier to clock-controller Use standard clock-controller node name for the CS2000-CP. No functional change. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260504225704.115125-5-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/ulcb.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index 67fd6a65db89..ae36a2e66948 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -221,7 +221,7 @@ ak4613: codec@10 { asahi-kasei,out6-single-end; }; - cs2000: clk-multiplier@4f { + cs2000: clock-controller@4f { #clock-cells = <0>; compatible = "cirrus,cs2000-cp"; reg = <0x4f>; From 131009c3fe7108c9b1c0bd5dfdbb12ff3224202e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 5 May 2026 05:42:42 +0200 Subject: [PATCH 508/665] arm64: dts: renesas: salvator-common: Specify ethernet PHY reset timings The KSZ9031RNX reference manual [1] DS00002117K page 62 FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING Note 2 states, that after the de-assertion of reset, wait a minimum of 100 us before starting programming on the MIIM (MDC/MDIO) interface. Set DT property reset-deassert-us to three times that, 300 us, to provide ample time between reset deassertion and MDIO access. The KSZ9031RNX reference manual [1] DS00002117K page 62 TABLE 7-4: POWER-UP/POWER-DOWN/RESET TIMING PARAMETERS row tSR Stable supply voltages to de-assertion of reset is at minimum 10 ms. Set DT property reset-assert-us to 10ms because the KSZ9031RNX RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ9031RNX-Data-Sheet-DS00002117.pdf Signed-off-by: Marek Vasut Tested-by: Geert Uytterhoeven Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260505034325.167797-2-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/salvator-common.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index b1f56efe25d9..1317ede2f719 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -361,6 +361,8 @@ phy0: ethernet-phy@0 { reg = <0>; interrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>; reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; }; }; From fb798ae948ddde64ad9a4adc92ad185a80dc72dc Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 5 May 2026 05:42:43 +0200 Subject: [PATCH 509/665] arm64: dts: renesas: ulcb: Specify ethernet PHY reset timings The KSZ9031RNX reference manual [1] DS00002117K page 62 FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING Note 2 states, that after the de-assertion of reset, wait a minimum of 100 us before starting programming on the MIIM (MDC/MDIO) interface. Set DT property reset-deassert-us to three times that, 300 us, to provide ample time between reset deassertion and MDIO access. The KSZ9031RNX reference manual [1] DS00002117K page 62 TABLE 7-4: POWER-UP/POWER-DOWN/RESET TIMING PARAMETERS row tSR Stable supply voltages to de-assertion of reset is at minimum 10 ms. Set DT property reset-assert-us to 10ms because the KSZ9031RNX RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ9031RNX-Data-Sheet-DS00002117.pdf Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260505034325.167797-3-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/ulcb.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index ae36a2e66948..119f2b5024b3 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -163,6 +163,8 @@ phy0: ethernet-phy@0 { reg = <0>; interrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>; reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; }; }; From 67c2dd78f43f129f6c92ea4aca00035139ecea1e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 5 May 2026 05:42:44 +0200 Subject: [PATCH 510/665] arm64: dts: renesas: eagle: Specify ethernet PHY reset timings The KSZ9031RNX reference manual [1] DS00002117K page 62 FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING Note 2 states, that after the de-assertion of reset, wait a minimum of 100 us before starting programming on the MIIM (MDC/MDIO) interface. Set DT property reset-deassert-us to three times that, 300 us, to provide ample time between reset deassertion and MDIO access. The KSZ9031RNX reference manual [1] DS00002117K page 62 TABLE 7-4: POWER-UP/POWER-DOWN/RESET TIMING PARAMETERS row tSR Stable supply voltages to de-assertion of reset is at minimum 10 ms. Set DT property reset-assert-us to 10ms because the KSZ9031RNX RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ9031RNX-Data-Sheet-DS00002117.pdf Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260505034325.167797-4-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts index b26c5a709777..a2ad79ddf73d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts @@ -113,6 +113,8 @@ phy0: ethernet-phy@0 { reg = <0>; interrupts-extended = <&gpio1 17 IRQ_TYPE_LEVEL_LOW>; reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; }; }; From ae49d5842944d4b5af80f5ec44f29c1909dac913 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 5 May 2026 05:42:45 +0200 Subject: [PATCH 511/665] arm64: dts: renesas: v3msk: Specify ethernet PHY reset timings The KSZ9031RNX reference manual [1] DS00002117K page 62 FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING Note 2 states, that after the de-assertion of reset, wait a minimum of 100 us before starting programming on the MIIM (MDC/MDIO) interface. Set DT property reset-deassert-us to three times that, 300 us, to provide ample time between reset deassertion and MDIO access. The KSZ9031RNX reference manual [1] DS00002117K page 62 TABLE 7-4: POWER-UP/POWER-DOWN/RESET TIMING PARAMETERS row tSR Stable supply voltages to de-assertion of reset is at minimum 10 ms. Set DT property reset-assert-us to 10ms because the KSZ9031RNX RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ9031RNX-Data-Sheet-DS00002117.pdf Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260505034325.167797-5-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts index 343f9610f892..10c9a2e9ed18 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts @@ -119,6 +119,8 @@ phy0: ethernet-phy@0 { reg = <0>; interrupts-extended = <&gpio1 17 IRQ_TYPE_LEVEL_LOW>; reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; }; }; From feef18ea6e86b26b6c80d09b1e93a33b3606646f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 5 May 2026 05:42:46 +0200 Subject: [PATCH 512/665] arm64: dts: renesas: condor-common: Specify ethernet PHY reset timings The KSZ9031RNX reference manual [1] DS00002117K page 62 FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING Note 2 states, that after the de-assertion of reset, wait a minimum of 100 us before starting programming on the MIIM (MDC/MDIO) interface. Set DT property reset-deassert-us to three times that, 300 us, to provide ample time between reset deassertion and MDIO access. The KSZ9031RNX reference manual [1] DS00002117K page 62 TABLE 7-4: POWER-UP/POWER-DOWN/RESET TIMING PARAMETERS row tSR Stable supply voltages to de-assertion of reset is at minimum 10 ms. Set DT property reset-assert-us to 10ms because the KSZ9031RNX RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ9031RNX-Data-Sheet-DS00002117.pdf Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260505034325.167797-6-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/condor-common.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/condor-common.dtsi b/arch/arm64/boot/dts/renesas/condor-common.dtsi index 6b22cc0b05b1..9d55509b00b1 100644 --- a/arch/arm64/boot/dts/renesas/condor-common.dtsi +++ b/arch/arm64/boot/dts/renesas/condor-common.dtsi @@ -168,6 +168,8 @@ phy0: ethernet-phy@0 { reg = <0>; interrupts-extended = <&gpio4 23 IRQ_TYPE_LEVEL_LOW>; reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; }; }; From c5c95e512b1afdd72865703bf6056b8b7b149fcb Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 5 May 2026 05:42:47 +0200 Subject: [PATCH 513/665] arm64: dts: renesas: v3hsk: Specify ethernet PHY reset timings The KSZ9031RNX reference manual [1] DS00002117K page 62 FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING Note 2 states, that after the de-assertion of reset, wait a minimum of 100 us before starting programming on the MIIM (MDC/MDIO) interface. Set DT property reset-deassert-us to three times that, 300 us, to provide ample time between reset deassertion and MDIO access. The KSZ9031RNX reference manual [1] DS00002117K page 62 TABLE 7-4: POWER-UP/POWER-DOWN/RESET TIMING PARAMETERS row tSR Stable supply voltages to de-assertion of reset is at minimum 10 ms. Set DT property reset-assert-us to 10ms because the KSZ9031RNX RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ9031RNX-Data-Sheet-DS00002117.pdf Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260505034325.167797-7-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts index e3725304fed0..52462e61b719 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts @@ -126,6 +126,8 @@ phy0: ethernet-phy@0 { reg = <0>; interrupts-extended = <&gpio4 23 IRQ_TYPE_LEVEL_LOW>; reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; }; }; From 1978e91b4c74b42067b19848d1dc28fd3da4e0f4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 5 May 2026 05:42:48 +0200 Subject: [PATCH 514/665] arm64: dts: renesas: ebisu: Specify ethernet PHY reset timings The KSZ9031RNX reference manual [1] DS00002117K page 62 FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING Note 2 states, that after the de-assertion of reset, wait a minimum of 100 us before starting programming on the MIIM (MDC/MDIO) interface. Set DT property reset-deassert-us to three times that, 300 us, to provide ample time between reset deassertion and MDIO access. The KSZ9031RNX reference manual [1] DS00002117K page 62 TABLE 7-4: POWER-UP/POWER-DOWN/RESET TIMING PARAMETERS row tSR Stable supply voltages to de-assertion of reset is at minimum 10 ms. Set DT property reset-assert-us to 10ms because the KSZ9031RNX RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ9031RNX-Data-Sheet-DS00002117.pdf Signed-off-by: Marek Vasut Tested-by: Geert Uytterhoeven Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260505034325.167797-8-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/ebisu.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/ebisu.dtsi b/arch/arm64/boot/dts/renesas/ebisu.dtsi index add60324e0e4..4b3775afcb01 100644 --- a/arch/arm64/boot/dts/renesas/ebisu.dtsi +++ b/arch/arm64/boot/dts/renesas/ebisu.dtsi @@ -322,6 +322,8 @@ phy0: ethernet-phy@0 { reg = <0>; interrupts-extended = <&gpio2 21 IRQ_TYPE_LEVEL_LOW>; reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; /* * TX clock internal delay mode is required for reliable * 1Gbps communication using the KSZ9031RNX phy present on From bbde39085f70dbe822fb6d826eca127518273f07 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 5 May 2026 05:42:49 +0200 Subject: [PATCH 515/665] arm64: dts: renesas: draak: Specify ethernet PHY reset timings The KSZ9031RNX reference manual [1] DS00002117K page 62 FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING Note 2 states, that after the de-assertion of reset, wait a minimum of 100 us before starting programming on the MIIM (MDC/MDIO) interface. Set DT property reset-deassert-us to three times that, 300 us, to provide ample time between reset deassertion and MDIO access. The KSZ9031RNX reference manual [1] DS00002117K page 62 TABLE 7-4: POWER-UP/POWER-DOWN/RESET TIMING PARAMETERS row tSR Stable supply voltages to de-assertion of reset is at minimum 10 ms. Set DT property reset-assert-us to 10ms because the KSZ9031RNX RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ9031RNX-Data-Sheet-DS00002117.pdf Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260505034325.167797-9-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/draak.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/draak.dtsi b/arch/arm64/boot/dts/renesas/draak.dtsi index c9c5c3ab06c3..f2f25fe5d778 100644 --- a/arch/arm64/boot/dts/renesas/draak.dtsi +++ b/arch/arm64/boot/dts/renesas/draak.dtsi @@ -249,6 +249,8 @@ phy0: ethernet-phy@0 { reg = <0>; interrupts-extended = <&gpio5 19 IRQ_TYPE_LEVEL_LOW>; reset-gpios = <&gpio5 18 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; /* * TX clock internal delay mode is required for reliable * 1Gbps communication using the KSZ9031RNX phy present on From 5bff12f97b73a4278b1c54f5db019ccc608901b8 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 5 May 2026 05:42:50 +0200 Subject: [PATCH 516/665] arm64: dts: renesas: falcon: Specify ethernet PHY reset timings The KSZ9031RNX reference manual [1] DS00002117K page 62 FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING Note 2 states, that after the de-assertion of reset, wait a minimum of 100 us before starting programming on the MIIM (MDC/MDIO) interface. Set DT property reset-deassert-us to three times that, 300 us, to provide ample time between reset deassertion and MDIO access. The KSZ9031RNX reference manual [1] DS00002117K page 62 TABLE 7-4: POWER-UP/POWER-DOWN/RESET TIMING PARAMETERS row tSR Stable supply voltages to de-assertion of reset is at minimum 10 ms. Set DT property reset-assert-us to 10ms because the KSZ9031RNX RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ9031RNX-Data-Sheet-DS00002117.pdf Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260505034325.167797-10-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts index 6bd580737f25..ea5dcee73658 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts @@ -33,6 +33,8 @@ phy0: ethernet-phy@0 { reg = <0>; interrupts-extended = <&gpio4 16 IRQ_TYPE_LEVEL_LOW>; reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; }; }; From 0a5e30c062da53053f5ac7b55a6b1993df8f5fe4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 5 May 2026 05:42:51 +0200 Subject: [PATCH 517/665] arm64: dts: renesas: white-hawk: Specify ethernet PHY reset timings The KSZ9031RNX reference manual [1] DS00002117K page 62 FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING Note 2 states, that after the de-assertion of reset, wait a minimum of 100 us before starting programming on the MIIM (MDC/MDIO) interface. Set DT property reset-deassert-us to three times that, 300 us, to provide ample time between reset deassertion and MDIO access. The KSZ9031RNX reference manual [1] DS00002117K page 62 TABLE 7-4: POWER-UP/POWER-DOWN/RESET TIMING PARAMETERS row tSR Stable supply voltages to de-assertion of reset is at minimum 10 ms. Set DT property reset-assert-us to 10ms because the KSZ9031RNX RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ9031RNX-Data-Sheet-DS00002117.pdf Signed-off-by: Marek Vasut Tested-by: Geert Uytterhoeven Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260505034325.167797-11-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi b/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi index b4024e85ae5a..c5045bda45c3 100644 --- a/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi +++ b/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi @@ -169,6 +169,8 @@ avb0_phy: ethernet-phy@0 { reg = <0>; interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>; reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; }; }; }; From 0b99c3aa40e7fa98f28a966d96967b5e50946f91 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 5 May 2026 05:42:52 +0200 Subject: [PATCH 518/665] arm64: dts: renesas: gray-hawk: Specify ethernet PHY reset timings The KSZ9031RNX reference manual [1] DS00002117K page 62 FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING Note 2 states, that after the de-assertion of reset, wait a minimum of 100 us before starting programming on the MIIM (MDC/MDIO) interface. Set DT property reset-deassert-us to three times that, 300 us, to provide ample time between reset deassertion and MDIO access. The KSZ9031RNX reference manual [1] DS00002117K page 62 TABLE 7-4: POWER-UP/POWER-DOWN/RESET TIMING PARAMETERS row tSR Stable supply voltages to de-assertion of reset is at minimum 10 ms. Set DT property reset-assert-us to 10ms because the KSZ9031RNX RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ9031RNX-Data-Sheet-DS00002117.pdf Signed-off-by: Marek Vasut Tested-by: Geert Uytterhoeven Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260505034325.167797-12-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/gray-hawk-single.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/gray-hawk-single.dtsi b/arch/arm64/boot/dts/renesas/gray-hawk-single.dtsi index 792a4aa8f4a9..274493720b14 100644 --- a/arch/arm64/boot/dts/renesas/gray-hawk-single.dtsi +++ b/arch/arm64/boot/dts/renesas/gray-hawk-single.dtsi @@ -213,6 +213,8 @@ avb0_phy: ethernet-phy@0 { reg = <0>; interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>; reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; }; }; }; From 141853e48860bc4aa74e312ae56bb72ff06107b1 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 5 May 2026 08:01:54 +0100 Subject: [PATCH 519/665] arm64: dts: renesas: r9a08g046: Add scif{1..5} device nodes Add scif{1..5} device nodes to RZ/G3L ("R9A08G046") SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260505070206.7932-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 90 ++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi index 02a3029c058e..19f2c9f29f5c 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -166,6 +166,96 @@ scif0: serial@100ac000 { status = "disabled"; }; + scif1: serial@100ac400 { + compatible = "renesas,scif-r9a08g046", "renesas,scif-r9a07g044"; + reg = <0 0x100ac400 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A08G046_SCIF1_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A08G046_SCIF1_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif2: serial@1004c000 { + compatible = "renesas,scif-r9a08g046", "renesas,scif-r9a07g044"; + reg = <0 0x1004c000 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A08G046_SCIF2_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A08G046_SCIF2_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif3: serial@1004c400 { + compatible = "renesas,scif-r9a08g046", "renesas,scif-r9a07g044"; + reg = <0 0x1004c400 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A08G046_SCIF3_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A08G046_SCIF3_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif4: serial@1004c800 { + compatible = "renesas,scif-r9a08g046", "renesas,scif-r9a07g044"; + reg = <0 0x1004c800 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A08G046_SCIF4_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A08G046_SCIF4_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif5: serial@1004e000 { + compatible = "renesas,scif-r9a08g046", "renesas,scif-r9a07g044"; + reg = <0 0x1004e000 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A08G046_SCIF5_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A08G046_SCIF5_RST_SYSTEM_N>; + status = "disabled"; + }; + i2c0: i2c@100ae000 { reg = <0 0x100ae000 0 0x400>; #address-cells = <1>; From bee6b1251fd2e91de6221bb3e23d2ae1384ffb4f Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 5 May 2026 08:01:55 +0100 Subject: [PATCH 520/665] arm64: dts: renesas: r9a08g046: Add i2c{0..3} device nodes Add i2c{0..3} device nodes to RZ/G3L ("R9A08G046") SoC DTSI. As the place holders for i2c0 is removed, add the pincontrol device nodes to make it functional on the board DTS. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260505070206.7932-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 83 ++++++++++++++++++- .../boot/dts/renesas/rzg3l-smarc-som.dtsi | 11 +++ 2 files changed, 93 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi index 19f2c9f29f5c..323e7d107a19 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -257,10 +257,91 @@ scif5: serial@1004e000 { }; i2c0: i2c@100ae000 { + compatible = "renesas,riic-r9a08g046", "renesas,riic-r9a09g057"; reg = <0 0x100ae000 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A08G046_I2C0_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A08G046_I2C0_MRST>; + power-domains = <&cpg>; #address-cells = <1>; #size-cells = <0>; - /* placeholder */ + status = "disabled"; + }; + + i2c1: i2c@10090400 { + compatible = "renesas,riic-r9a08g046", "renesas,riic-r9a09g057"; + reg = <0 0x10090400 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A08G046_I2C1_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A08G046_I2C1_MRST>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@10090800 { + compatible = "renesas,riic-r9a08g046", "renesas,riic-r9a09g057"; + reg = <0 0x10090800 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A08G046_I2C2_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A08G046_I2C2_MRST>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@10090c00 { + compatible = "renesas,riic-r9a08g046", "renesas,riic-r9a09g057"; + reg = <0 0x10090c00 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A08G046_I2C3_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A08G046_I2C3_MRST>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; canfd: can@100c0000 { diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi index b28e59a65259..7770de2064d9 100644 --- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi @@ -11,6 +11,7 @@ / { aliases { ethernet0 = ð0; ethernet1 = ð1; + i2c0 = &i2c0; }; memory@48000000 { @@ -50,6 +51,11 @@ &extal_clk { clock-frequency = <24000000>; }; +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; +}; + &mdio0 { phy0: ethernet-phy@7 { compatible = "ethernet-phy-id0022.1640"; @@ -144,6 +150,11 @@ ctrl { power-source = <1800>; }; }; + + i2c0_pins: i2c0 { + pinmux = , /* RIIC0_SCL */ + ; /* RIIC0_SDA */ + }; }; &wdt0 { From 0df7429fcb8360caa6d2b05c9efa217daa966279 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 5 May 2026 13:36:59 +0100 Subject: [PATCH 521/665] arm64: dts: renesas: r9a08g046: Add DMAC node Add the DMA controller device tree node for the RZ/G3L (r9a08g046) SoC. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260505123708.134069-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi index 323e7d107a19..5f8eb93da3c1 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -482,6 +482,43 @@ icu: interrupt-controller@11050000 { resets = <&cpg R9A08G046_IA55_RESETN>; }; + dmac: dma-controller@11820000 { + compatible = "renesas,r9a08g046-dmac", "renesas,rz-dmac"; + reg = <0 0x11820000 0 0x10000>, + <0 0x11830000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD R9A08G046_DMAC_ACLK>, + <&cpg CPG_MOD R9A08G046_DMAC_PCLK>; + clock-names = "main", "register"; + power-domains = <&cpg>; + resets = <&cpg R9A08G046_DMAC_ARESETN>, + <&cpg R9A08G046_DMAC_RST_ASYNC>; + reset-names = "arst", "rst_async"; + #dma-cells = <1>; + dma-channels = <16>; + }; + sdhi1: mmc@11c10000 { reg = <0x0 0x11c10000 0 0x10000>; /* placeholder */ From 17dc49f44c33cff7133fd48d5bc18bb0f625503a Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 5 May 2026 13:37:00 +0100 Subject: [PATCH 522/665] arm64: dts: renesas: r9a08g046: Add SSI support Add SSI{0,1,2,3} nodes to RZ/G3L SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260505123708.134069-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 76 ++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi index 5f8eb93da3c1..70f820f14335 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -349,6 +349,82 @@ canfd: can@100c0000 { /* placeholder */ }; + ssi0: ssi@100e4000 { + compatible = "renesas,r9a08g046-ssi", "renesas,rz-ssi"; + reg = <0 0x100e4000 0 0x400>; + interrupts = , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx"; + clocks = <&cpg CPG_MOD R9A08G046_SSI0_PCLK2>, + <&cpg CPG_MOD R9A08G046_SSI0_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A08G046_SSI0_RST_M2_REG>; + dmas = <&dmac 0x2665>, <&dmac 0x2666>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi1: ssi@100e4400 { + compatible = "renesas,r9a08g046-ssi", "renesas,rz-ssi"; + reg = <0 0x100e4400 0 0x400>; + interrupts = , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx"; + clocks = <&cpg CPG_MOD R9A08G046_SSI1_PCLK2>, + <&cpg CPG_MOD R9A08G046_SSI1_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A08G046_SSI1_RST_M2_REG>; + dmas = <&dmac 0x2669>, <&dmac 0x266a>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi2: ssi@100e4800 { + compatible = "renesas,r9a08g046-ssi", "renesas,rz-ssi"; + reg = <0 0x100e4800 0 0x400>; + interrupts = , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx"; + clocks = <&cpg CPG_MOD R9A08G046_SSI2_PCLK2>, + <&cpg CPG_MOD R9A08G046_SSI2_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A08G046_SSI2_RST_M2_REG>; + dmas = <&dmac 0x266d>, <&dmac 0x266e>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi3: ssi@100e4c00 { + compatible = "renesas,r9a08g046-ssi", "renesas,rz-ssi"; + reg = <0 0x100e4c00 0 0x400>; + interrupts = , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx"; + clocks = <&cpg CPG_MOD R9A08G046_SSI3_PCLK2>, + <&cpg CPG_MOD R9A08G046_SSI3_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A08G046_SSI3_RST_M2_REG>; + dmas = <&dmac 0x2671>, <&dmac 0x2672>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a08g046-cpg"; reg = <0 0x11010000 0 0x10000>; From e014a2299806b8724358f7e13579c9384a19435c Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 5 May 2026 13:37:01 +0100 Subject: [PATCH 523/665] arm64: dts: renesas: r9a08g046: Add audio clock nodes Add audio_clk1 and audio_clk2 fixed-clock nodes to the RZ/G3L (r9a08g046) SoC DTSI. These clocks are external to the SoC and their frequencies are board-dependent, so they are defined with clock-frequency = <0> as placeholders that must be overridden in board-level DTS files. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260505123708.134069-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi index 70f820f14335..4bb156dc3b23 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -14,6 +14,20 @@ / { #size-cells = <2>; interrupt-parent = <&gic>; + audio_clk1: audio1-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by boards that provide it. */ + clock-frequency = <0>; + }; + + audio_clk2: audio2-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by boards that provide it. */ + clock-frequency = <0>; + }; + cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; From 87e8d5ef4500e5f27e84d4c2052b40bd8790172d Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 6 May 2026 16:58:03 +0100 Subject: [PATCH 524/665] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add alias for on-SoC RTC The RZ/V2H SoC provides an internal RTC, which is enabled in the DT. The RZ/V2H EVK board also includes an external RTC in the RAA215300 PMIC. Add an "rtc0" alias pointing to the on-SoC RTC node to ensure a stable device numbering. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260506155804.3984418-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts index bd69109a5086..3c1ddacc0944 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts @@ -27,6 +27,7 @@ aliases { i2c7 = &i2c7; i2c8 = &i2c8; mmc1 = &sdhi1; + rtc0 = &rtc; serial0 = &scif; }; From 8fdfbe0f114fd406a1e98d185a8f9e1d193a6526 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 6 May 2026 16:58:04 +0100 Subject: [PATCH 525/665] arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Add alias for on-SoC RTC The RZ/V2N SoC provides an internal RTC, which is enabled in the DT. The RZ/V2N EVK board also includes an external RTC in the RAA215300 PMIC. Add an "rtc0" alias pointing to the on-SoC RTC node to ensure a stable device numbering. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260506155804.3984418-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts index 43ffde419d91..c43325dd1c55 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts @@ -26,6 +26,7 @@ aliases { i2c7 = &i2c7; i2c8 = &i2c8; mmc1 = &sdhi1; + rtc0 = &rtc; serial0 = &scif; }; From 7cf0a16bdbea1ae52356ddf1c4d85e6c364d8a07 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 14 May 2026 00:50:24 +0200 Subject: [PATCH 526/665] arm64: dts: renesas: r8a78000: Add PSCI node Describe SMC based PSCI access in SoC DT. The system can interact with TFA BL31 PSCI provider running on the Cortex-A cores via SMC calls. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260513225037.49803-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a78000.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi index 3ec1b53d2782..5e8fdc818256 100644 --- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi @@ -665,6 +665,11 @@ extalr_clk: extalr-clk { /* clock-frequency must be set on board */ }; + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + /* External SCIF clock - to be overridden by boards that provide it */ scif_clk: scif-clk { compatible = "fixed-clock"; From 54613573ff1495b928e2841b257c081a58566901 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 14 May 2026 14:53:06 +0200 Subject: [PATCH 527/665] arm64: dts: renesas: r8a78000: Fix GIC-720AE View 1 Redistributor description MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Renesas R-Car X5H (R8A78000) SoC contains Arm CoreLink GIC-720AE Generic Interrupt Controller with Multi View capability. Firmware has access to configuration View 0, Linux kernel has access to View 1. The Arm CoreLink GIC-720AE Generic Interrupt Controller Technical Reference Manual, currently latest r2p1 [1], chapter "5. Programmers model for GIC-720AE", subchapter "5.4 Redistributor registers for control and physical LPIs summary", part "5.4.3 GICR_TYPER, Redistributor Type Register", "Table 5-50: GICR_TYPER bit descriptions" on page 200, clarifies register "GICR_TYPER" bit 4 "Last" behavior in Multi View setup as follows: Last Last Redistributor: 0 ... This Redistributor is not the last Redistributor on the chip. 1 ... This Redistributor is the last Redistributor on the chip. When GICD_CFGID.VIEW == 1, for views 1, 2, or 3 this bit always returns 1. On this SoC, GICD_CFGID.VIEW is 1 and the Linux kernel has access to View 1, therefore Linux kernel GICv3 driver will interpret register "GICR_TYPER" bit 4 "Last" = 1 in the first Redistributor in continuous Redistributor page as that first Redistributor being the one and only Redistributor and will stop processing the continuous Redistributor page further. This will prevent the other Redistributors from being recognized by the system and used for other PEs. Because the hardware indicates that the continuous Redistributor page is not continuous for View 1, 2, or 3, describe every Redistributor separately in the DT. This makes all Redistributors for all cores accessible in Linux. [1] https://documentation-service.arm.com/static/69ef3c1cd35efd294e335c43 Arm® CoreLinkâ„¢ GIC-720AE Generic Interrupt Controller Revision: r2p1 / Issue 12 / 102666_0201_12_en Fixes: 63500d12cf76 ("arm64: dts: renesas: Add R8A78000 SoC support") Acked-by: Marc Zyngier Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260514125328.20954-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a78000.dtsi | 36 +++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi index 5e8fdc818256..d14f0cc0ad36 100644 --- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi @@ -694,8 +694,40 @@ gic: interrupt-controller@39000000 { #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; - reg = <0 0x39000000 0 0x10000>, - <0 0x39080000 0 0x800000>; + #redistributor-regions = <32>; + reg = <0x0 0x39000000 0x0 0x10000>, + <0x0 0x39080000 0x0 0x40000>, + <0x0 0x390c0000 0x0 0x40000>, + <0x0 0x39100000 0x0 0x40000>, + <0x0 0x39140000 0x0 0x40000>, + <0x0 0x39180000 0x0 0x40000>, + <0x0 0x391c0000 0x0 0x40000>, + <0x0 0x39200000 0x0 0x40000>, + <0x0 0x39240000 0x0 0x40000>, + <0x0 0x39280000 0x0 0x40000>, + <0x0 0x392c0000 0x0 0x40000>, + <0x0 0x39300000 0x0 0x40000>, + <0x0 0x39340000 0x0 0x40000>, + <0x0 0x39380000 0x0 0x40000>, + <0x0 0x393c0000 0x0 0x40000>, + <0x0 0x39400000 0x0 0x40000>, + <0x0 0x39440000 0x0 0x40000>, + <0x0 0x39480000 0x0 0x40000>, + <0x0 0x394c0000 0x0 0x40000>, + <0x0 0x39500000 0x0 0x40000>, + <0x0 0x39540000 0x0 0x40000>, + <0x0 0x39580000 0x0 0x40000>, + <0x0 0x395c0000 0x0 0x40000>, + <0x0 0x39600000 0x0 0x40000>, + <0x0 0x39640000 0x0 0x40000>, + <0x0 0x39680000 0x0 0x40000>, + <0x0 0x396c0000 0x0 0x40000>, + <0x0 0x39700000 0x0 0x40000>, + <0x0 0x39740000 0x0 0x40000>, + <0x0 0x39780000 0x0 0x40000>, + <0x0 0x397c0000 0x0 0x40000>, + <0x0 0x39800000 0x0 0x40000>, + <0x0 0x39840000 0x0 0x40000>; interrupts = ; }; From a6c4c7114b5b4ffe3685fe26002eccd40eb11f3c Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 14 May 2026 22:02:17 +0100 Subject: [PATCH 528/665] arm64: dts: renesas: rzt2h-n2h-evk: Configure eMMC/SDHI pins The HW user manual for the Renesas RZ/T2H and the RZ/N2H states that for SDR104, SDR50, and HS200 to work properly the eMMC/SDHI interface pins have to be configured as specified below: - SDn_CLK pin - drive strength: Ultra High, slew rate: Fast, - Other SDn_* pins: drive strength: High, slew rate: Fast, Schmitt trigger: disabled (not applicable to SDn_RST pins). HS DDR and DDR50 are currently not supported, and for every other bus mode the eMMC/SDHI interface pins should be configured as specified below: - SDn_CLK pin - drive strength: High, slew rate: Fast, - Other SDn_* pins: drive strength: Middle, slew rate: Fast, Schmitt trigger: disabled (not applicable to SDn_RST pins). Adjust the pin definitions accordingly. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Reviewed-by: Lad Prabhakar Link: https://patch.msgid.link/20260514210220.7616-1-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/rzt2h-n2h-evk-common.dtsi | 147 ++++++++++++++++-- 1 file changed, 136 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi index f87c2492f414..ba0f5d12772c 100644 --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi @@ -275,12 +275,63 @@ data-pins { , /* SD0_DATA5 */ , /* SD0_DATA6 */ ; /* SD0_DATA7 */ + drive-strength-microamp = <5000>; + slew-rate = <1>; + input-schmitt-disable; }; - ctrl-pins { - pinmux = , /* SD0_CLK */ - , /* SD0_CMD */ - ; /* SD0_RST# */ + clk-pins { + pinmux = ; /* SD0_CLK */ + drive-strength-microamp = <9000>; + slew-rate = <1>; + }; + + cmd-pins { + pinmux = ; /* SD0_CMD */ + drive-strength-microamp = <5000>; + slew-rate = <1>; + input-schmitt-disable; + }; + + rst-pins { + pinmux = ; /* SD0_RST# */ + drive-strength-microamp = <5000>; + slew-rate = <1>; + }; + }; + + sdhi0_emmc_uhs_pins: sd0-emmc-uhs-group { + data-pins { + pinmux = , /* SD0_DATA0 */ + , /* SD0_DATA1 */ + , /* SD0_DATA2 */ + , /* SD0_DATA3 */ + , /* SD0_DATA4 */ + , /* SD0_DATA5 */ + , /* SD0_DATA6 */ + ; /* SD0_DATA7 */ + drive-strength-microamp = <9000>; + slew-rate = <1>; + input-schmitt-disable; + }; + + clk-pins { + pinmux = ; /* SD0_CLK */ + drive-strength-microamp = <11800>; + slew-rate = <1>; + }; + + cmd-pins { + pinmux = ; /* SD0_CMD */ + drive-strength-microamp = <9000>; + slew-rate = <1>; + input-schmitt-disable; + }; + + rst-pins { + pinmux = ; /* SD0_RST# */ + drive-strength-microamp = <9000>; + slew-rate = <1>; }; }; @@ -299,12 +350,49 @@ data-pins { , /* SD0_DATA1 */ , /* SD0_DATA2 */ ; /* SD0_DATA3 */ + drive-strength-microamp = <5000>; + slew-rate = <1>; + input-schmitt-disable; + }; + + clk-pins { + pinmux = ; /* SD0_CLK */ + drive-strength-microamp = <9000>; + slew-rate = <1>; }; ctrl-pins { - pinmux = , /* SD0_CLK */ - , /* SD0_CMD */ + pinmux = , /* SD0_CMD */ ; /* SD0_CD */ + drive-strength-microamp = <5000>; + slew-rate = <1>; + input-schmitt-disable; + }; + }; + + sdhi0_sd_uhs_pins: sd0-sd-uhs-group { + data-pins { + pinmux = , /* SD0_DATA0 */ + , /* SD0_DATA1 */ + , /* SD0_DATA2 */ + ; /* SD0_DATA3 */ + drive-strength-microamp = <9000>; + slew-rate = <1>; + input-schmitt-disable; + }; + + clk-pins { + pinmux = ; /* SD0_CLK */ + drive-strength-microamp = <11800>; + slew-rate = <1>; + }; + + ctrl-pins { + pinmux = , /* SD0_CMD */ + ; /* SD0_CD */ + drive-strength-microamp = <9000>; + slew-rate = <1>; + input-schmitt-disable; }; }; @@ -323,12 +411,49 @@ data-pins { , /* SD1_DATA1 */ , /* SD1_DATA2 */ ; /* SD1_DATA3 */ + drive-strength-microamp = <5000>; + slew-rate = <1>; + input-schmitt-disable; + }; + + clk-pins { + pinmux = ; /* SD1_CLK */ + drive-strength-microamp = <9000>; + slew-rate = <1>; }; ctrl-pins { - pinmux = , /* SD1_CLK */ - , /* SD1_CMD */ + pinmux = , /* SD1_CMD */ ; /* SD1_CD */ + drive-strength-microamp = <5000>; + slew-rate = <1>; + input-schmitt-disable; + }; + }; + + sdhi1_uhs_pins: sd1-uhs-group { + data-pins { + pinmux = , /* SD1_DATA0 */ + , /* SD1_DATA1 */ + , /* SD1_DATA2 */ + ; /* SD1_DATA3 */ + drive-strength-microamp = <9000>; + slew-rate = <1>; + input-schmitt-disable; + }; + + clk-pins { + pinmux = ; /* SD1_CLK */ + drive-strength-microamp = <11800>; + slew-rate = <1>; + }; + + ctrl-pins { + pinmux = , /* SD1_CMD */ + ; /* SD1_CD */ + drive-strength-microamp = <9000>; + slew-rate = <1>; + input-schmitt-disable; }; }; }; @@ -342,7 +467,7 @@ &sci0 { #if SD0_EMMC &sdhi0 { pinctrl-0 = <&sdhi0_emmc_pins>; - pinctrl-1 = <&sdhi0_emmc_pins>; + pinctrl-1 = <&sdhi0_emmc_uhs_pins>; pinctrl-names = "default", "state_uhs"; vmmc-supply = <®_3p3v>; vqmmc-supply = <®_1p8v>; @@ -357,7 +482,7 @@ &sdhi0 { #if SD0_SD &sdhi0 { pinctrl-0 = <&sdhi0_sd_pins>; - pinctrl-1 = <&sdhi0_sd_pins>; + pinctrl-1 = <&sdhi0_sd_uhs_pins>; pinctrl-names = "default", "state_uhs"; vmmc-supply = <®_3p3v>; vqmmc-supply = <&vqmmc_sdhi0>; @@ -372,7 +497,7 @@ &sdhi0 { #if SD1_MICRO_SD &sdhi1 { pinctrl-0 = <&sdhi1_pins>; - pinctrl-1 = <&sdhi1_pins>; + pinctrl-1 = <&sdhi1_uhs_pins>; pinctrl-names = "default", "state_uhs"; vmmc-supply = <®_3p3v>; vqmmc-supply = <&vccq_sdhi1>; From 5250b3b1ad99d216b31c98b2b321f1dee362a1b5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 17 May 2026 18:31:25 +0200 Subject: [PATCH 529/665] arm64: dts: renesas: ironhide: Describe all reserved memory Fully describe all available DRAM in the DT, and describe regions which are not accessible because they are used by firmware in reserved-memory nodes. Replace the first memory bank memory@60600000 with memory@40000000 and a 518 MiB long reserved-memory no-map subnode. This memory region is used by other cores in the system. Reserve 32 kiB of memory at 0x8c100000 for parameters shared by IPL, SCP, TFA BL31 and TEE. Reserve 512 kiB of memory at 0x8c200000 for TFA BL31. The upcoming upstream TFA 2.15 BL31 uses memory from 0x8c200000..0x8c242fff; rounding up to 512 kiB is slight future-proofing. Reserve 32 MiB of memory at 0x8c400000 for OPTEE-OS, which is the entire OPTEE-OS TZ protected DRAM area. Neither TFA BL31 nor OPTEE-OS modify the DT passed to Linux in any way with any new reserved-memory {} nodes to reserve memory areas used by the TFA BL31 or OPTEE-OS to prevent the next stage from using those areas, which lets Linux use all of the available DRAM as it is described in the DT that was passed in by U-Boot, including the areas that are newly utilized by TFA BL31 or OPTEE-OS. In case of high DRAM utilization, unless the memory used by TFA BL31 or OPTEE-OS is properly reserved, Linux may use and corrupt the memory used by TFA BL31 or OPTEE-OS, which would lead to the system becoming unresponsive. Fixes: ad142a4ef710 ("arm64: dts: renesas: r8a78000: Add initial Ironhide board support") Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260517163212.18016-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r8a78000-ironhide.dts | 35 +++++++++++++++++-- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts index a721734fbd5d..ed027a6c356e 100644 --- a/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts +++ b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts @@ -20,10 +20,9 @@ chosen { stdout-path = "serial0:1843200n8"; }; - memory@60600000 { + memory@40000000 { device_type = "memory"; - /* first 518MiB is reserved for other purposes. */ - reg = <0x0 0x60600000 0x0 0x5fa00000>; + reg = <0x0 0x40000000 0x0 0x80000000>; }; memory@1080000000 { @@ -65,6 +64,36 @@ memory@1e00000000 { device_type = "memory"; reg = <0x1e 0x00000000 0x1 0x00000000>; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* First 518 MiB is reserved for other purposes. */ + firmware@40000000 { + reg = <0x0 0x40000000 0x0 0x20600000>; + no-map; + }; + + /* Parameters set by IPL. */ + parameters@8c100000 { + reg = <0x0 0x8c100000 0x0 0x00008000>; + no-map; + }; + + /* TFA BL31. */ + tfa-bl31@8c200000 { + reg = <0x0 0x8c200000 0x0 0x00080000>; + no-map; + }; + + /* TEE TZ DRAM. */ + tee@8c400000 { + reg = <0x0 0x8c400000 0x0 0x02000000>; + no-map; + }; + }; }; &extal_clk { From a3904c5a6e59e3454c268a43da800cd46fa36523 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 19 May 2026 09:47:03 +0200 Subject: [PATCH 530/665] arm64: dts: renesas: r8a78000: Add MFIS, MFIS-SCP, and transport nodes Describe the MFIS and MFIS SCP instances which are used for various tasks including inter-processor communication. Remove the PRR node because it is part of MFIS on R-Car X5H and should be handled using the MFIS compatible. Also, describe the S-TCM transport area used for shared memory mailboxing. Signed-off-by: Vinh Nguyen Signed-off-by: Hai Pham Signed-off-by: Kuninori Morimoto Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260519074702.3308-5-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a78000.dtsi | 129 +++++++++++++++++++++- 1 file changed, 126 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi index d14f0cc0ad36..7780fb4e8351 100644 --- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi @@ -683,9 +683,123 @@ soc: soc { #size-cells = <2>; ranges; - prr: chipid@189e0044 { - compatible = "renesas,prr"; - reg = <0 0x189e0044 0 4>; + mfis: system-controller@189e0000 { + compatible = "renesas,r8a78000-mfis"; + reg = <0 0x189e0000 0 0x1000>, <0 0x18800000 0 0x40000>; + reg-names = "common", "mboxes"; + interrupts = , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , ; + interrupt-names = "ch0i", "ch0e", "ch1i", "ch1e", "ch2i", "ch2e", "ch3i", "ch3e", + "ch4i", "ch4e", "ch5i", "ch5e", "ch6i", "ch6e", "ch7i", "ch7e", + "ch8i", "ch8e", "ch9i", "ch9e", "ch10i", "ch10e", "ch11i", "ch11e", + "ch12i", "ch12e", "ch13i", "ch13e", "ch14i", "ch14e", "ch15i", "ch15e", + "ch16i", "ch16e", "ch17i", "ch17e", "ch18i", "ch18e", "ch19i", "ch19e", + "ch20i", "ch20e", "ch21i", "ch21e", "ch22i", "ch22e", "ch23i", "ch23e", + "ch24i", "ch24e", "ch25i", "ch25e", "ch26i", "ch26e", "ch27i", "ch27e", + "ch28i", "ch28e", "ch29i", "ch29e", "ch30i", "ch30e", "ch31i", "ch31e", + "ch32i", "ch32e", "ch33i", "ch33e", "ch34i", "ch34e", "ch35i", "ch35e", + "ch36i", "ch36e", "ch37i", "ch37e", "ch38i", "ch38e", "ch39i", "ch39e", + "ch40i", "ch40e", "ch41i", "ch41e", "ch42i", "ch42e", "ch43i", "ch43e", + "ch44i", "ch44e", "ch45i", "ch45e", "ch46i", "ch46e", "ch47i", "ch47e", + "ch48i", "ch48e", "ch49i", "ch49e", "ch50i", "ch50e", "ch51i", "ch51e", + "ch52i", "ch52e", "ch53i", "ch53e", "ch54i", "ch54e", "ch55i", "ch55e", + "ch56i", "ch56e", "ch57i", "ch57e", "ch58i", "ch58e", "ch59i", "ch59e", + "ch60i", "ch60e", "ch61i", "ch61e", "ch62i", "ch62e", "ch63i", "ch63e"; + #mbox-cells = <2>; + #hwlock-cells = <1>; + status = "disabled"; + }; + + mfis_scp: system-controller@189e1000 { + compatible = "renesas,r8a78000-mfis-scp"; + reg = <0 0x189e1000 0 0x1000>, <0 0x18840000 0 0x2c000>; + reg-names = "common", "mboxes"; + interrupts = , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , ; + /* SCP uses I side IRQ only */ + interrupt-names = "ch0i", "ch1i", "ch2i", "ch3i", "ch4i", "ch5i", "ch6i", "ch7i", + "ch8i", "ch9i", "ch10i", "ch11i", "ch12i", "ch13i", "ch14i", "ch15i", + "ch16i", "ch17i", "ch18i", "ch19i", "ch20i", "ch21i", "ch22i", "ch23i", + "ch24i", "ch25i", "ch26i", "ch27i", "ch28i", "ch29i", "ch30i", "ch31i"; + #mbox-cells = <2>; + #hwlock-cells = <1>; + status = "disabled"; }; /* Application Processors manage View-1 of a GIC-720AE */ @@ -810,6 +924,15 @@ hscif3: serial@c071c000 { clock-names = "fck", "brg_int", "scif_clk"; status = "disabled"; }; + + stcm_transport: sram@c1060000 { + compatible = "mmio-sram"; + reg = <0x0 0xc1060000 0x0 0x1c00>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0xc1060000 0x1c00>; + /* actual transport nodes must be set per board file */ + }; }; timer { From 1b6a230750ee66b9ca8cb5675cc7eca802657570 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 19 May 2026 09:47:04 +0200 Subject: [PATCH 531/665] arm64: dts: renesas: ironhide: Enable to use SCMI Enable SCMI via MFIS-SCP and S-TCM transport area. Signed-off-by: Kuninori Morimoto Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260519074702.3308-6-wsa+renesas@sang-engineering.com [geert: Drop scmi_clk node] Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r8a78000-ironhide.dts | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts index ed027a6c356e..d2b3fc08954a 100644 --- a/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts +++ b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts @@ -6,6 +6,7 @@ */ /dts-v1/; +#include #include "r8a78000.dtsi" / { @@ -20,6 +21,19 @@ chosen { stdout-path = "serial0:1843200n8"; }; + firmware { + scmi: scmi { + compatible = "arm,scmi"; + mboxes = <&mfis_scp 2 MFIS_CHANNEL_TX>, + <&mfis_scp 2 MFIS_CHANNEL_RX>; + mbox-names = "tx", "rx"; + shmem = <&scmi_tx_shmem>, <&scmi_rx_shmem>; + arm,no-completion-irq; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + memory@40000000 { device_type = "memory"; reg = <0x0 0x40000000 0x0 0x80000000>; @@ -109,6 +123,22 @@ &hscif0 { status = "okay"; }; +&mfis_scp { + status = "okay"; +}; + &scif_clk { clock-frequency = <26000000>; }; + +&stcm_transport { + scmi_tx_shmem: sram@1200 { + compatible = "arm,scmi-shmem"; + reg = <0x1200 0x0100>; + }; + + scmi_rx_shmem: sram@1300 { + compatible = "arm,scmi-shmem"; + reg = <0x1300 0x100>; + }; +}; From daae3ecaeb1b14ba06fe7c0ca1c1d88bdf094d07 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 19 May 2026 11:00:17 +0100 Subject: [PATCH 532/665] arm64: dts: renesas: r9a08g046: Add rsci{0..3} device nodes Add rsci{0..3} device nodes to the RZ/G3L ("R9A08G046") SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260519100022.116318-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 84 ++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi index 4bb156dc3b23..03bdee870528 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -358,6 +358,90 @@ i2c3: i2c@10090c00 { status = "disabled"; }; + rsci0: serial@100b8000 { + compatible = "renesas,r9a08g046-rsci"; + reg = <0 0x100b8000 0 0x1000>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD R9A08G046_RSCI0_TCLK>, + <&cpg CPG_MOD R9A08G046_RSCI0_PCLK>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + resets = <&cpg R9A08G046_RSCI0_PRESETN>, + <&cpg R9A08G046_RSCI0_TRESETN>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci1: serial@100f1000 { + compatible = "renesas,r9a08g046-rsci"; + reg = <0 0x100f1000 0 0x1000>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD R9A08G046_RSCI1_TCLK>, + <&cpg CPG_MOD R9A08G046_RSCI1_PCLK>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + resets = <&cpg R9A08G046_RSCI1_PRESETN>, + <&cpg R9A08G046_RSCI1_TRESETN>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci2: serial@100f2000 { + compatible = "renesas,r9a08g046-rsci"; + reg = <0 0x100f2000 0 0x1000>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD R9A08G046_RSCI2_TCLK>, + <&cpg CPG_MOD R9A08G046_RSCI2_PCLK>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + resets = <&cpg R9A08G046_RSCI2_PRESETN>, + <&cpg R9A08G046_RSCI2_TRESETN>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci3: serial@100f3000 { + compatible = "renesas,r9a08g046-rsci"; + reg = <0 0x100f3000 0 0x1000>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD R9A08G046_RSCI3_TCLK>, + <&cpg CPG_MOD R9A08G046_RSCI3_PCLK>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + resets = <&cpg R9A08G046_RSCI3_PRESETN>, + <&cpg R9A08G046_RSCI3_TRESETN>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + canfd: can@100c0000 { reg = <0 0x100c0000 0 0x20000>; /* placeholder */ From f82892de7f4878f54a4035be06f3acc6e6449616 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 20 May 2026 12:51:39 +0100 Subject: [PATCH 533/665] arm64: dts: renesas: r9a07g043: Add max-frequency to SDHI nodes Add the max-frequency property set to 133333333 Hz (133.33 MHz) to both SDHI0 and SDHI1 MMC controller nodes in the RZ/{G2UL,Five} (r9a07g043) device tree, increasing performance by ca. 33%. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260520115144.60067-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 38aebeeea464..6c4b2dad1550 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -655,6 +655,7 @@ sdhi0: mmc@11c00000 { <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>, <&cpg CPG_MOD R9A07G043_SDHI0_ACLK>; clock-names = "core", "clkh", "cd", "aclk"; + max-frequency = <133333333>; resets = <&cpg R9A07G043_SDHI0_IXRST>; power-domains = <&cpg>; status = "disabled"; @@ -671,6 +672,7 @@ sdhi1: mmc@11c10000 { <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>, <&cpg CPG_MOD R9A07G043_SDHI1_ACLK>; clock-names = "core", "clkh", "cd", "aclk"; + max-frequency = <133333333>; resets = <&cpg R9A07G043_SDHI1_IXRST>; power-domains = <&cpg>; status = "disabled"; From 1b3c392bd655af31a414fc82382cec13e090a997 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 20 May 2026 12:51:40 +0100 Subject: [PATCH 534/665] arm64: dts: renesas: r9a07g044: Add max-frequency to SDHI nodes Add the max-frequency property set to 133333333 Hz (133.33 MHz) to both SDHI0 and SDHI1 MMC controller nodes in the RZ/{G2L,G2LC} (r9a07g044) device tree, increasing performance by ca. 33%. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260520115144.60067-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 873b52b168bc..f40315a707d1 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -1174,6 +1174,7 @@ sdhi0: mmc@11c00000 { <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>, <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>; clock-names = "core", "clkh", "cd", "aclk"; + max-frequency = <133333333>; resets = <&cpg R9A07G044_SDHI0_IXRST>; power-domains = <&cpg>; status = "disabled"; @@ -1190,6 +1191,7 @@ sdhi1: mmc@11c10000 { <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>, <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>; clock-names = "core", "clkh", "cd", "aclk"; + max-frequency = <133333333>; resets = <&cpg R9A07G044_SDHI1_IXRST>; power-domains = <&cpg>; status = "disabled"; From dcbbb1266043d1d7ca1f129d2ca58a6ce8e04cbb Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 20 May 2026 12:51:41 +0100 Subject: [PATCH 535/665] arm64: dts: renesas: r9a07g054: Add max-frequency to SDHI nodes Add the max-frequency property set to 133333333 Hz (133.33 MHz) to both SDHI0 and SDHI1 MMC controller nodes in the RZ/V2L (r9a07g054) device tree, increasing performance by ca. 33%. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260520115144.60067-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 587fab0ceb3f..f689996b5808 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -1182,6 +1182,7 @@ sdhi0: mmc@11c00000 { <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>, <&cpg CPG_MOD R9A07G054_SDHI0_ACLK>; clock-names = "core", "clkh", "cd", "aclk"; + max-frequency = <133333333>; resets = <&cpg R9A07G054_SDHI0_IXRST>; power-domains = <&cpg>; status = "disabled"; @@ -1198,6 +1199,7 @@ sdhi1: mmc@11c10000 { <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>, <&cpg CPG_MOD R9A07G054_SDHI1_ACLK>; clock-names = "core", "clkh", "cd", "aclk"; + max-frequency = <133333333>; resets = <&cpg R9A07G054_SDHI1_IXRST>; power-domains = <&cpg>; status = "disabled"; From d61a35b0a3e43ea91781c41e02046b7d73fb3f1e Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Wed, 20 May 2026 16:23:15 +0300 Subject: [PATCH 536/665] arm64: dts: renesas: r9a07g044: Add DMA properties to serial nodes Add DMA properties to the serial nodes on the RZ/G2L SoC. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260520132315.944117-1-claudiu.beznea@kernel.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index f40315a707d1..2ced800713fc 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -504,6 +504,8 @@ scif0: serial@1004b800 { "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>; clock-names = "fck"; + dmas = <&dmac 0x4e79>, <&dmac 0x4e7a>; + dma-names = "tx", "rx"; power-domains = <&cpg>; resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>; status = "disabled"; @@ -522,6 +524,8 @@ scif1: serial@1004bc00 { "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G044_SCIF1_CLK_PCK>; clock-names = "fck"; + dmas = <&dmac 0x4e7d>, <&dmac 0x4e7e>; + dma-names = "tx", "rx"; power-domains = <&cpg>; resets = <&cpg R9A07G044_SCIF1_RST_SYSTEM_N>; status = "disabled"; @@ -540,6 +544,8 @@ scif2: serial@1004c000 { "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G044_SCIF2_CLK_PCK>; clock-names = "fck"; + dmas = <&dmac 0x4e81>, <&dmac 0x4e82>; + dma-names = "tx", "rx"; power-domains = <&cpg>; resets = <&cpg R9A07G044_SCIF2_RST_SYSTEM_N>; status = "disabled"; @@ -558,6 +564,8 @@ scif3: serial@1004c400 { "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G044_SCIF3_CLK_PCK>; clock-names = "fck"; + dmas = <&dmac 0x4e85>, <&dmac 0x4e86>; + dma-names = "tx", "rx"; power-domains = <&cpg>; resets = <&cpg R9A07G044_SCIF3_RST_SYSTEM_N>; status = "disabled"; @@ -576,6 +584,8 @@ scif4: serial@1004c800 { "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G044_SCIF4_CLK_PCK>; clock-names = "fck"; + dmas = <&dmac 0x4e89>, <&dmac 0x4e8a>; + dma-names = "tx", "rx"; power-domains = <&cpg>; resets = <&cpg R9A07G044_SCIF4_RST_SYSTEM_N>; status = "disabled"; From 71e900344ada84fc55fb103950a0d4819f6c6e1c Mon Sep 17 00:00:00 2001 From: Nguyen Tran Date: Fri, 22 May 2026 19:19:57 +0200 Subject: [PATCH 537/665] arm64: dts: renesas: r8a779md: Add support for R-Car M3Le R8A779MD Geist Add support for the Geist board based on the Renesas R-Car R8A779MD (M3Le) SoC, a register-compatible variant of the R8A77965 (M3-N) with reduced set of peripherals. Reviewed-by: Geert Uytterhoeven Signed-off-by: Nguyen Tran Signed-off-by: Marek Vasut Link: https://patch.msgid.link/20260522172000.15096-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 1 + .../arm64/boot/dts/renesas/r8a779md-geist.dts | 720 ++++++++++++++++++ 2 files changed, 721 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779md-geist.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index ca45d2857ea7..8bf155badd11 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -60,6 +60,7 @@ r8a77965-salvator-xs-panel-aa104xd12-dtbs := r8a77965-salvator-xs.dtb salvator-p dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-xs-panel-aa104xd12.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-ulcb.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-ulcb-kf.dtb +dtb-$(CONFIG_ARCH_R8A77965) += r8a779md-geist.dtb dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle-function-expansion.dtbo diff --git a/arch/arm64/boot/dts/renesas/r8a779md-geist.dts b/arch/arm64/boot/dts/renesas/r8a779md-geist.dts new file mode 100644 index 000000000000..0e4724336e73 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779md-geist.dts @@ -0,0 +1,720 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the Geist board with R-Car M3Le + * + * Copyright (C) 2025-2026 Renesas Electronics Corp. + */ + +/dts-v1/; +#include +#include +#include "r8a779md.dtsi" + +/ { + model = "Renesas Geist board based on r8a779md"; + compatible = "renesas,geist", "renesas,r8a779md", "renesas,r8a77965"; + + aliases { + serial0 = &scif2; + serial1 = &hscif1; + ethernet0 = &avb; + mmc0 = &sdhi2; + mmc1 = &sdhi0; + }; + + audio_clkout: audio-clkout { + /* + * This is same as <&rcar_sound 0> + * but needed to avoid cs2500/rcar_sound probe dead-lock + */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 50000>; + + brightness-levels = <256 128 64 16 8 4 0>; + default-brightness-level = <6>; + + power-supply = <®_12v>; + enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + stdout-path = "serial0:115200n8"; + }; + + cvbs-in { + compatible = "composite-video-connector"; + label = "CVBS IN"; + + port { + cvbs_con: endpoint { + remote-endpoint = <&adv7482_ain7>; + }; + }; + }; + + hdmi-in { + compatible = "hdmi-connector"; + label = "HDMI IN"; + type = "a"; + + port { + hdmi_in_con: endpoint { + remote-endpoint = <&adv7482_hdmi>; + }; + }; + }; + + keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&keys_pins>; + pinctrl-names = "default"; + + key-1 { + gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW4-1"; + wakeup-source; + debounce-interval = <20>; + }; + + key-2 { + gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW4-2"; + wakeup-source; + debounce-interval = <20>; + }; + + key-3 { + gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW4-3"; + wakeup-source; + debounce-interval = <20>; + }; + + key-4 { + gpios = <&gpio5 23 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW4-4"; + wakeup-source; + debounce-interval = <20>; + }; + + key-a { + gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "TSW0"; + wakeup-source; + debounce-interval = <20>; + }; + + key-b { + gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "TSW1"; + wakeup-source; + debounce-interval = <20>; + }; + + key-c { + gpios = <&gpio6 13 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "TSW2"; + wakeup-source; + debounce-interval = <20>; + }; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@480000000 { + device_type = "memory"; + reg = <0x4 0x80000000 0x0 0x80000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_12v: regulator-12v { + compatible = "regulator-fixed"; + regulator-name = "fixed-12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-boot-on; + regulator-always-on; + }; + + vbus0_usb2: regulator-vbus0-usb2 { + compatible = "regulator-fixed"; + + regulator-name = "USB20_VBUS0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; + + sound_card: sound { + compatible = "audio-graph-card"; + + label = "rcar-sound"; + dais = <&rsnd_port0>; /* AK4619 Audio Codec */ + }; + + x12_clk: x12-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + /* External DU dot clocks */ + x21_clk: x21-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <33000000>; + }; + + x22_clk: x22-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <33000000>; + }; + + x23_clk: x23-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + x3013_clk: x3013-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&audio_clk_a { + clock-frequency = <22579200>; +}; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + tx-internal-delay-ps = <2000>; + status = "okay"; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0022.1622"; + rxc-skew-ps = <1500>; + reg = <0>; + interrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; +}; + +&csi40 { + status = "okay"; + + ports { + port@0 { + csi40_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&adv7482_txa>; + }; + }; + }; +}; + +&ehci0 { + dr_mode = "otg"; + status = "okay"; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&hscif1 { + pinctrl-0 = <&hscif1_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + /* Please only enable hscif1 or scif1 */ + status = "okay"; +}; + +&hsusb { + dr_mode = "otg"; + status = "okay"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "okay"; + + ak4619: codec@10 { + compatible = "asahi-kasei,ak4619"; + reg = <0x10>; + clocks = <&rcar_sound 3>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + + port { + ak4619_endpoint: endpoint { + remote-endpoint = <&rsnd_endpoint0>; + }; + }; + }; + + /* Pin-to-pin, register map, and control compatible with CS2000 and CS2200 */ + cs2500: clock-controller@4f { + #clock-cells = <0>; + compatible = "cirrus,cs2500", "cirrus,cs2000-cp"; + reg = <0x4f>; + clocks = <&audio_clkout>, <&x12_clk>; + clock-names = "clk_in", "ref_clk"; + + assigned-clocks = <&cs2500>; + assigned-clock-rates = <24576000>; /* 1/1 divide */ + }; +}; + +&i2c4 { + clock-frequency = <400000>; + status = "okay"; + + versaclock3: clock-controller@68 { + compatible = "renesas,5p35023"; + reg = <0x68>; + #clock-cells = <1>; + clocks = <&x3013_clk>; + assigned-clocks = <&versaclock3 4>, <&versaclock3 5>; + assigned-clock-rates = <100000000>, <100000000>; + }; + + versaclock5: clock-controller@6a { + compatible = "idt,5p49v5923"; + reg = <0x6a>; + #clock-cells = <1>; + clocks = <&x23_clk>; + clock-names = "xin"; + }; + + video-receiver@70 { + compatible = "adi,adv7482"; + reg = <0x70 0x71 0x72 0x73 0x74 0x75 + 0x60 0x61 0x62 0x63 0x64 0x65>; + reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater", + "infoframe", "cbus", "cec", "sdp", "txa", "txb" ; + + interrupts-extended = <&gpio6 30 IRQ_TYPE_LEVEL_LOW>, + <&gpio6 31 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "intrq1", "intrq2"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + + adv7482_ain7: endpoint { + remote-endpoint = <&cvbs_con>; + }; + }; + + port@8 { + reg = <8>; + + adv7482_hdmi: endpoint { + remote-endpoint = <&hdmi_in_con>; + }; + }; + + port@a { + reg = <10>; + + adv7482_txa: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi40_in>; + }; + }; + }; + }; + + csa_vdd: adc@7c { + compatible = "maxim,max9611"; + reg = <0x7c>; + + shunt-resistor-micro-ohms = <5000>; + }; + + csa_dvfs: adc@7f { + compatible = "maxim,max9611"; + reg = <0x7f>; + + shunt-resistor-micro-ohms = <5000>; + }; +}; + +&i2c_dvfs { + status = "okay"; + + clock-frequency = <400000>; + + eeprom@50 { + compatible = "rohm,br24t01", "atmel,24c01"; + reg = <0x50>; + pagesize = <8>; + }; +}; + +&ohci0 { + dr_mode = "otg"; + status = "okay"; +}; + +&pcie_bus_clk { + status = "disabled"; +}; + +&pciec0 { + clocks = <&cpg CPG_MOD 319>, <&versaclock3 4>; + status = "okay"; +}; + +&pciec0_rp { + clocks = <&versaclock3 5>; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + avb_pins: avb { + mux { + groups = "avb_link", "avb_mdio", "avb_mii"; + function = "avb"; + }; + + pins_mdio { + groups = "avb_mdio"; + drive-strength = <24>; + }; + + pins_mii_tx { + pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0", + "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3"; + drive-strength = <12>; + }; + }; + + hscif1_pins: hscif1 { + groups = "hscif1_data_a", "hscif1_ctrl_a"; + function = "hscif1"; + }; + + i2c2_pins: i2c2 { + groups = "i2c2_a"; + function = "i2c2"; + }; + + irq0_pins: irq0 { + groups = "intc_ex_irq0"; + function = "intc_ex"; + }; + + keys_pins: keys { + pins = "GP_5_17", "GP_5_20", "GP_5_22"; + bias-pull-up; + }; + + pwm1_pins: pwm1 { + groups = "pwm1_a"; + function = "pwm1"; + }; + + scif1_pins: scif1 { + groups = "scif1_data_a", "scif1_ctrl"; + function = "scif1"; + }; + + scif2_pins: scif2 { + groups = "scif2_data_a"; + function = "scif2"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk_a"; + function = "scif_clk"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; + }; + + sdhi2_pins: sd2 { + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; + function = "sdhi2"; + power-source = <1800>; + }; + + sound_pins: sound { + groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; + function = "ssi"; + }; + + sound_clk_pins: sound_clk { + groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a", + "audio_clkout_a", "audio_clkout3_a"; + function = "audio_clk"; + }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; +}; + +&pwm1 { + pinctrl-0 = <&pwm1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&rcar_sound { + pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; + pinctrl-names = "default"; + + /* Single DAI */ + #sound-dai-cells = <0>; + + /* audio_clkout0/1/2/3 */ + #clock-cells = <1>; + clock-frequency = <12288000 11289600>; + + status = "okay"; + + /* update to */ + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&cs2500>, + <&audio_clk_c>, + <&cpg CPG_MOD 922>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + rsnd_port0: port@0 { + reg = <0>; + + rsnd_endpoint0: endpoint { + remote-endpoint = <&ak4619_endpoint>; + dai-format = "left_j"; + bitclock-master = <&rsnd_endpoint0>; + frame-master = <&rsnd_endpoint0>; + playback = <&ssi0>, <&src0>, <&dvc0>; + capture = <&ssi1>, <&src1>, <&dvc1>; + }; + }; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + +&scif1 { + pinctrl-0 = <&scif1_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + /* Please only enable hscif1 or scif1 */ + /* status = "okay"; */ +}; + +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdhi2 { + /* used for on-board 8bit eMMC */ + pinctrl-0 = <&sdhi2_pins>; + pinctrl-1 = <&sdhi2_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + no-sd; + no-sdio; + non-removable; + fixed-emmc-driver-type = <1>; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&ssi1 { + shared-pin; +}; + +&usb_extal_clk { + clock-frequency = <50000000>; +}; + +&usb2_phy0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + + vbus-supply = <&vbus0_usb2>; + status = "okay"; +}; + +&vin0 { + status = "okay"; +}; + +&vin1 { + status = "okay"; +}; + +&vin2 { + status = "okay"; +}; + +&vin3 { + status = "okay"; +}; + +&vin4 { + status = "okay"; +}; + +&vin5 { + status = "okay"; +}; + +&vin6 { + status = "okay"; +}; + +&vin7 { + status = "okay"; +}; + +&vspb { + status = "okay"; +}; + +&vspi0 { + status = "okay"; +}; From 0bbc248fa2cc834392f128bfd127a03f6dbe9d55 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sun, 24 May 2026 10:20:11 +0100 Subject: [PATCH 538/665] arm64: dts: renesas: rzg3e-smarc-som: Sort GMAC pinmux entries Sort the pinmux entries for both GMAC ctrl nodes in port order (A/B/C and D/E/F respectively) and remove the extra blank line before the second pinmux assignment. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260524092016.46346-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 49 +++++++++---------- 1 file changed, 24 insertions(+), 25 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi index d978619155d2..2e1d9686df88 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -193,20 +193,20 @@ clk { }; ctrl { - pinmux = , /* MDC */ - , /* MDIO */ - , /* PHY_INTR (IRQ2) */ - , /* RXD3 */ - , /* RXD2 */ - , /* RXD1 */ - , /* RXD0 */ - , /* RXC */ + pinmux = , /* MDIO */ + , /* MDC */ , /* RX_CTL */ - , /* TXD3 */ - , /* TXD2 */ - , /* TXD1 */ + , /* TX_CTL */ + , /* RXC */ , /* TXD0 */ - ; /* TX_CTL */ + , /* TXD1 */ + , /* TXD2 */ + , /* TXD3 */ + , /* RXD0 */ + , /* RXD1 */ + , /* RXD2 */ + , /* RXD3 */ + ; /* PHY_INTR (IRQ2) */ }; }; @@ -217,21 +217,20 @@ clk { }; ctrl { - - pinmux = , /* MDC */ - , /* MDIO */ - , /* PHY_INTR (IRQ15) */ - , /* RXD3 */ - , /* RXD2 */ - , /* RXD1 */ - , /* RXD0 */ - , /* RXC */ + pinmux = , /* MDIO */ + , /* MDC */ , /* RX_CTL */ - , /* TXD3 */ - , /* TXD2 */ - , /* TXD1 */ + , /* TX_CTL */ + , /* RXC */ , /* TXD0 */ - ; /* TX_CTL */ + , /* TXD1 */ + , /* TXD2 */ + , /* TXD3 */ + , /* RXD0 */ + , /* RXD1 */ + , /* RXD2 */ + , /* RXD3 */ + ; /* PHY_INTR (IRQ15) */ }; }; From f0b0d1658a23560efb9e0aef012898c5c59dc447 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 26 May 2026 21:40:43 +0100 Subject: [PATCH 539/665] arm64: dts: renesas: r9a09g077: Add xSPI nodes Add device tree nodes for the two xSPI (Expanded SPI) controllers integrated into the RZ/T2H (R9A09G077) SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260526204045.3481604-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi index fe5d206d4def..40494159831d 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -1006,6 +1006,46 @@ mii_conv3: mii-conv@3 { }; }; + xspi0: spi@801c0000 { + compatible = "renesas,r9a09g077-xspi", + "renesas,r9a09g047-xspi"; + reg = <0 0x801c0000 0 0x1000>, + <0 0x40000000 0 0x10000000>; + reg-names = "regs", "dirmap"; + interrupts = , + ; + interrupt-names = "pulse", "err_pulse"; + clocks = <&cpg CPG_MOD 4>, + <&cpg CPG_CORE R9A09G077_XSPI_CLK0>; + clock-names = "ahb", "spi"; + resets = <&cpg 4>; + reset-names = "hresetn"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + xspi1: spi@801c1000 { + compatible = "renesas,r9a09g077-xspi", + "renesas,r9a09g047-xspi"; + reg = <0 0x801c1000 0 0x1000>, + <0 0x50000000 0 0x10000000>; + reg-names = "regs", "dirmap"; + interrupts = , + ; + interrupt-names = "pulse", "err_pulse"; + clocks = <&cpg CPG_MOD 5>, + <&cpg CPG_CORE R9A09G077_XSPI_CLK1>; + clock-names = "ahb", "spi"; + resets = <&cpg 5>; + reset-names = "hresetn"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + cpg: clock-controller@80280000 { compatible = "renesas,r9a09g077-cpg-mssr"; reg = <0 0x80280000 0 0x10000>, From 8fa0a1ae4f434be1b8ea6223636c065c8e39d09b Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 26 May 2026 21:40:44 +0100 Subject: [PATCH 540/665] arm64: dts: renesas: r9a09g087: Add xSPI nodes Add device tree nodes for the two xSPI (Expanded SPI) controllers integrated into the RZ/N2H (R9A09G087) SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260526204045.3481604-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi index c64b532f3d23..e8d4f76949cc 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -1009,6 +1009,46 @@ mii_conv3: mii-conv@3 { }; }; + xspi0: spi@801c0000 { + compatible = "renesas,r9a09g087-xspi", + "renesas,r9a09g047-xspi"; + reg = <0 0x801c0000 0 0x1000>, + <0 0x40000000 0 0x10000000>; + reg-names = "regs", "dirmap"; + interrupts = , + ; + interrupt-names = "pulse", "err_pulse"; + clocks = <&cpg CPG_MOD 4>, + <&cpg CPG_CORE R9A09G087_XSPI_CLK0>; + clock-names = "ahb", "spi"; + resets = <&cpg 4>; + reset-names = "hresetn"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + xspi1: spi@801c1000 { + compatible = "renesas,r9a09g087-xspi", + "renesas,r9a09g047-xspi"; + reg = <0 0x801c1000 0 0x1000>, + <0 0x50000000 0 0x10000000>; + reg-names = "regs", "dirmap"; + interrupts = , + ; + interrupt-names = "pulse", "err_pulse"; + clocks = <&cpg CPG_MOD 5>, + <&cpg CPG_CORE R9A09G087_XSPI_CLK1>; + clock-names = "ahb", "spi"; + resets = <&cpg 5>; + reset-names = "hresetn"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + cpg: clock-controller@80280000 { compatible = "renesas,r9a09g087-cpg-mssr"; reg = <0 0x80280000 0 0x10000>, From f4418ce75760e5f546a1bdd0876056febc430b1f Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 27 May 2026 21:24:30 +0100 Subject: [PATCH 541/665] arm64: dts: renesas: rzt2h-n2h-evk: Enable xSPI nodes Enable the xSPI0 and xSPI1 controllers on the RZ/T2H N2H EVK board. Configure the xSPI0 controller interface to 1-bit (x1) mode, even though the connected MX25LW51245 octal flash device supports octal mode. Add a corresponding inline hardware comment detailing this restriction; operating in octal mode causes the BootROM to fail loading the first-stage bootloader following a Watchdog Timer (WDT) reset. Configure the xSPI1 controller interface connected to the AT25SF128A flash device for 4-bit (x4) mode to utilize all available data lines. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260527202430.606341-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r9a09g077m44-rzt2h-evk.dts | 15 +++ .../dts/renesas/rzt2h-n2h-evk-common.dtsi | 127 ++++++++++++++++++ 2 files changed, 142 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts index 4c0e52850ca9..e9ed2de128f6 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -345,3 +345,18 @@ usb_pins: usb-pins { }; }; +/* + * XSPI0 Pin Configuration: + * ------------------------ + * Signal | Pin | SW5 + * -----------|---------|--------------- + * XSPI0_ECS | P07_5 | 5: OFF, 6: ON + */ +&xspi0_pins { + ecs-pins { + pinmux = ; /* XSPI0_ECS0 */ + drive-strength-microamp = <2500>; + input-schmitt-disable; + slew-rate = <0>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi index ba0f5d12772c..e86e6d3aa8a3 100644 --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi @@ -5,6 +5,7 @@ * Copyright (C) 2025 Renesas Electronics Corp. */ +#include #include #include #include @@ -20,6 +21,8 @@ aliases { mmc0 = &sdhi0; mmc1 = &sdhi1; serial0 = &sci0; + spi0 = &xspi0; + spi1 = &xspi1; }; chosen { @@ -456,6 +459,45 @@ ctrl-pins { input-schmitt-disable; }; }; + + xspi0_pins: xspi0-group { + ctrl-data-pins { + pinmux = , /* XSPI0_CKP */ + , /* XSPI0_CS0 */ + , /* XSPI0_DS */ + , /* XSPI0_IO0 */ + , /* XSPI0_IO1 */ + , /* XSPI0_IO2 */ + , /* XSPI0_IO3 */ + , /* XSPI0_IO4 */ + , /* XSPI0_IO5 */ + , /* XSPI0_IO6 */ + , /* XSPI0_IO7 */ + ; /* XSPI0_RESET0 */ + drive-strength-microamp = <9000>; + input-schmitt-disable; + slew-rate = <1>; + }; + }; + + /* + * XSPI1 Pin Configuration: + * ------------------------ + * Signal | Pin | RZ/T2H (SW1) | RZ/N2H (DSW2) + * -----------|----------|---------------|--------------- + * ALL | Multiple | 6: ON | 6: ON + */ + xspi1_pins: xspi1-pins { + pinmux = , /* XSPI1_CKP */ + , /* XSPI1_CS0 */ + , /* XSPI1_IO0 */ + , /* XSPI1_IO1 */ + , /* XSPI1_IO2 */ + ; /* XSPI1_IO3 */ + drive-strength-microamp = <9000>; + input-schmitt-enable; + slew-rate = <1>; + }; }; &sci0 { @@ -520,3 +562,88 @@ &wdt2 { timeout-sec = <60>; }; +&xspi0 { + pinctrl-0 = <&xspi0_pins>; + pinctrl-names = "default"; + status = "okay"; + + assigned-clocks = <&cpg CPG_CORE R9A09G077_XSPI_CLK0>; + assigned-clock-rates = <50000000>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + vcc-supply = <®_3p3v>; + m25p,fast-read; + /* + * Configure for 1-bit mode to prevent the BootROM from failing + * to load the first-stage bootloader following a watchdog reset. + */ + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + spi-max-frequency = <50000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bl2-0"; + reg = <0x00000000 0x00060000>; + read-only; + }; + + partition@60000 { + label = "fip-0"; + reg = <0x00060000 0x007a0000>; + read-only; + }; + + partition@800000 { + label = "user-0"; + reg = <0x800000 0x003800000>; + }; + }; + }; +}; + +&xspi1 { + pinctrl-0 = <&xspi1_pins>; + pinctrl-names = "default"; + status = "okay"; + + assigned-clocks = <&cpg CPG_CORE R9A09G077_XSPI_CLK1>; + assigned-clock-rates = <50000000>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + vcc-supply = <®_3p3v>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bl2-1"; + reg = <0x00000000 0x00060000>; + }; + + partition@60000 { + label = "fip-1"; + reg = <0x00060000 0x007a0000>; + }; + + partition@800000 { + label = "user-1"; + reg = <0x800000 0x800000>; + }; + }; + }; +}; From 662ce0d73322d17614b86b641aa0ff27a254c87b Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 28 May 2026 08:02:34 +0100 Subject: [PATCH 542/665] arm64: dts: renesas: r9a08g046l48-smarc: Add gpio keys RZ/G3L SMARC EVK has 3 user buttons called USER_SW1, USER_SW2 and USER_SW3. Instantiate the gpio-keys driver for these buttons by removing place holders and replacing proper pins for the buttons. USER_SW{1,2,3} are configured as wakeup-sources, so they can wake up the system during s2idle. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260528070239.33352-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a08g046l48-smarc.dts | 26 ++++++++++++++----- .../boot/dts/renesas/rzg3l-smarc-som.dtsi | 17 ++++++++++++ 2 files changed, 37 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts index 0ae052238b3b..ef00e316fbde 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts @@ -7,10 +7,18 @@ /dts-v1/; -/* Add place holder to avoid compilation error with renesas-smarc2.dtsi */ -#define KEY_1_GPIO 1 -#define KEY_2_GPIO 2 -#define KEY_3_GPIO 3 +/* Switch selection settings */ +#define RZ_BOOT_MODE3 1 +#define SW_DPI_EN 0 +#define SW_GPIO4 1 + +#define PMOD_GPIO4 0 +#define PMOD_GPIO6 0 +#define PMOD_GPIO7 0 + +#define KEY_1_GPIO RZG3L_GPIO(J, 3) +#define KEY_2_GPIO RZG3L_GPIO(6, 4) +#define KEY_3_GPIO RZG3L_GPIO(6, 5) #include #include @@ -30,11 +38,17 @@ aliases { }; &keys { - status = "disabled"; - +#if !RZ_BOOT_MODE3 || !SW_GPIO4 || PMOD_GPIO4 /delete-node/ key-1; +#endif + +#if SW_DPI_EN || PMOD_GPIO6 /delete-node/ key-2; +#endif + +#if SW_DPI_EN || PMOD_GPIO7 /delete-node/ key-3; +#endif }; &pinctrl { diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi index 7770de2064d9..06c6ccac5ad2 100644 --- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi @@ -5,6 +5,23 @@ * Copyright (C) 2026 Renesas Electronics Corp. */ +/* + * Please set the below switch position on the SoM and the corresponding macro + * on the board DTS: + * + * Switch position SYS.5, Macro SW_DPI_EN: + * 0 - Select multiple SMARC signals active + * 1 - Select LCD + * + * Switch position BOOT.1, Macro RZ_BOOT_MODE3: + * 0 - Select JTAG enabled + * 1 - Select SDIO {CD,IOVS,PWEN} and GPIO4 Active + * + * Switch position SW_GPIO4, Macro SW_GPIO4: + * 0 - Select RZ_VBAT_TAMPER (position 2-1) + * 1 - Select GPIO4 (position 2-3) + */ + / { compatible = "renesas,rzg3l-smarcm", "renesas,r9a08g046l48", "renesas,r9a08g046"; From 3f9c7afdfa60eb726c7f8fb8529ab6519a104db8 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 28 May 2026 08:02:35 +0100 Subject: [PATCH 543/665] arm64: dts: renesas: r9a08g046l48-smarc: Enable I2C{2,3} devices Enable I2C{2,3} on the RZ/G3L SMARC EVK board. I2C3 is enabled by setting SW SYS.2 to the OFF position. Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das Link: https://patch.msgid.link/20260528070239.33352-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a08g046l48-smarc.dts | 29 +++++++++++++++++++ .../boot/dts/renesas/rzg3l-smarc-som.dtsi | 4 +++ 2 files changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts index ef00e316fbde..1512b7df39bd 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts @@ -11,6 +11,7 @@ #define RZ_BOOT_MODE3 1 #define SW_DPI_EN 0 #define SW_GPIO4 1 +#define SW_I3C_EN 0 #define PMOD_GPIO4 0 #define PMOD_GPIO6 0 @@ -33,10 +34,28 @@ / { "renesas,r9a08g046l48", "renesas,r9a08g046"; aliases { + i2c2 = &i2c2; + i2c3 = &i2c3; serial3 = &scif0; }; }; +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +#if !SW_I3C_EN +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; +#endif + &keys { #if !RZ_BOOT_MODE3 || !SW_GPIO4 || PMOD_GPIO4 /delete-node/ key-1; @@ -52,6 +71,16 @@ &keys { }; &pinctrl { + i2c2_pins: i2c2 { + pinmux = , /* RIIC2_SCL */ + ; /* RIIC2_SDA */ + }; + + i2c3_pins: i2c3 { + pinmux = , /* RIIC3_SCL */ + ; /* RIIC3_SDA */ + }; + scif0_pins: scif0 { pins = "SCIF0_TXD", "SCIF0_RXD"; power-source = <1800>; diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi index 06c6ccac5ad2..17bf44778398 100644 --- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi @@ -9,6 +9,10 @@ * Please set the below switch position on the SoM and the corresponding macro * on the board DTS: * + * Switch position SYS.2, Macro SW_I3C_EN: + * 0 - SMARC_I2C_GP is enabled + * 1 - I3C is enabled + * * Switch position SYS.5, Macro SW_DPI_EN: * 0 - Select multiple SMARC signals active * 1 - Select LCD From 80e32321c3df7bec3029725c526935493939f34c Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 28 May 2026 08:45:44 +0100 Subject: [PATCH 544/665] arm64: dts: renesas: rzg3l-smarc-som: Enable Versa clock generator The RZ/G3L SMARC SoM has a Versa 5P35023B clock generator to generate the following clocks: - ref: Not connected, - se1: AUDIO_MCK (11.2896 or 12.2880 MHz), - se2: RZ_AUDIO_CLK_B (11.2896 MHz), - se3: RZ_AUDIO_CLK_C (12.2880 MHz), - diff{1,1B}: ET{0,1}_PHY_CLK (25 MHz), - diff2{2,2B}: Not connected. Enable the Vversa 5P35023B clock generator on the RZ/G3L SoM DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260528074615.91110-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/rzg3l-smarc-som.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi index 17bf44778398..5e58e08e7fad 100644 --- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi @@ -40,6 +40,12 @@ memory@48000000 { /* First 128MiB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x78000000>; }; + + x2_clk: x2-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; }; ð0 { @@ -75,6 +81,18 @@ &extal_clk { &i2c0 { pinctrl-0 = <&i2c0_pins>; pinctrl-names = "default"; + + versa3: clock-generator@68 { + compatible = "renesas,5p35023"; + reg = <0x68>; + #clock-cells = <1>; + clocks = <&x2_clk>; + + assigned-clocks = <&versa3 1>, <&versa3 2>, + <&versa3 3>, <&versa3 4>; + assigned-clock-rates = <12288000>, <11289600>, + <12288000>, <25000000>; + }; }; &mdio0 { From 0d4ed954061efc3e47fa889d3de0675f933f438f Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 28 May 2026 08:45:45 +0100 Subject: [PATCH 545/665] arm64: dts: renesas: r9a08g046l48-smarc: Enable audio Enable audio on the RZ/G3L SMARC EVK by linking SSI0 with the DA7212 audio CODEC. The SSI0 signals are multiplexed with SD2 and are selected by switch SW_SD2_EN#. Add regulator nodes regulator-{1p8v,3p3v} to the SoM DTSI for reuse by eMMC. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260528074615.91110-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a08g046l48-smarc.dts | 72 +++++++++++++++++++ .../boot/dts/renesas/rzg3l-smarc-som.dtsi | 22 ++++++ 2 files changed, 94 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts index 1512b7df39bd..32d3b08a3cf3 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts @@ -9,6 +9,7 @@ /* Switch selection settings */ #define RZ_BOOT_MODE3 1 +#define SW_SD2_EN 0 #define SW_DPI_EN 0 #define SW_GPIO4 1 #define SW_I3C_EN 0 @@ -38,6 +39,32 @@ aliases { i2c3 = &i2c3; serial3 = &scif0; }; + +#if !SW_SD2_EN && !SW_I3C_EN + snd_rzg3l: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "snd_rzg3l"; + #address-cells = <1>; + #size-cells = <0>; + + ssi_link_play: simple-audio-card,dai-link@0 { + reg = <0>; + format = "i2s"; + bitclock-master = <&cpu_dai>; + frame-master = <&cpu_dai>; + mclk-fs = <256>; + + cpu_dai: cpu { + sound-dai = <&ssi0>; + }; + + codec_dai: codec { + sound-dai = <&da7212>; + clocks = <&versa3 1>; + }; + }; + }; +#endif }; &i2c2 { @@ -53,6 +80,27 @@ &i2c3 { pinctrl-names = "default"; status = "okay"; + + da7212: codec@1a { + compatible = "dlg,da7212"; + reg = <0x1a>; + + clocks = <&versa3 1>; + clock-names = "mclk"; + + #sound-dai-cells = <0>; + + dlg,micbias1-lvl = <2500>; + dlg,micbias2-lvl = <2500>; + dlg,dmic-data-sel = "lrise_rfall"; + dlg,dmic-samplephase = "between_clkedge"; + dlg,dmic-clkrate = <3000000>; + + VDDA-supply = <®_1p8v>; + VDDSP-supply = <®_3p3v>; + VDDMIC-supply = <®_3p3v>; + VDDIO-supply = <®_1p8v>; + }; }; #endif @@ -71,6 +119,11 @@ &keys { }; &pinctrl { + audio_clk_pins: audio-clock { + pinmux = , /* AUDIO_CLK_B */ + ; /* AUDIO_CLK_C */ + }; + i2c2_pins: i2c2 { pinmux = , /* RIIC2_SCL */ ; /* RIIC2_SDA */ @@ -85,9 +138,28 @@ scif0_pins: scif0 { pins = "SCIF0_TXD", "SCIF0_RXD"; power-source = <1800>; }; + + ssi0_pins: ssi0 { + pinmux = , /* SSIF0_RXD */ + , /* SSIF0_BCK */ + , /* SSIF0_RCK */ + ; /* SSIF0_TXD */ + }; }; &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; }; + +#if !SW_SD2_EN +&ssi0 { + clocks = <&cpg CPG_MOD R9A08G046_SSI0_PCLK2>, + <&cpg CPG_MOD R9A08G046_SSI0_PCLK_SFR>, + <&versa3 2>, <&versa3 3>; + pinctrl-0 = <&audio_clk_pins>, <&ssi0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; +#endif diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi index 5e58e08e7fad..091a227233cb 100644 --- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi @@ -13,6 +13,10 @@ * 0 - SMARC_I2C_GP is enabled * 1 - I3C is enabled * + * Switch position SYS.4, Macro SW_SD2_EN: + * 0 - Select I2S0 + * 1 - Select SD2 + * * Switch position SYS.5, Macro SW_DPI_EN: * 0 - Select multiple SMARC signals active * 1 - Select LCD @@ -41,6 +45,24 @@ memory@48000000 { reg = <0x0 0x48000000 0x0 0x78000000>; }; + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + x2_clk: x2-clock { compatible = "fixed-clock"; #clock-cells = <0>; From 793cc54475b49b5b558902b5c13e4bfe66530a50 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Wed, 20 May 2026 18:00:00 +0800 Subject: [PATCH 546/665] riscv: dts: spacemit: enable PMIC on OrangePi R2S Enable the i2c8 interface and add the connected SpacemiT P1 PMIC and its associated regulators to support voltage regulation on the board. Signed-off-by: Chukun Pan Reviewed-by: Yixun lan Link: https://patch.msgid.link/20260520100000.575719-1-amadeus@jmu.edu.cn Signed-off-by: Yixun Lan --- .../boot/dts/spacemit/k1-orangepi-r2s.dts | 134 ++++++++++++++++++ 1 file changed, 134 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts index 1ecc40749e5a..b13a8d6a2670 100644 --- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts @@ -13,6 +13,7 @@ / { compatible = "xunlong,orangepi-r2s", "spacemit,k1"; aliases { + i2c8 = &i2c8; serial0 = &uart0; ethernet0 = ð0; ethernet1 = ð1; @@ -22,6 +23,15 @@ chosen { stdout-path = "serial0"; }; + vcc4v0: regulator-vcc4v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc4v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; + }; + vcc5v0_usb: regulator-vcc5v0-usb { compatible = "regulator-fixed"; enable-active-high; @@ -94,6 +104,130 @@ rgmii1: phy@1 { }; }; +&i2c8 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_cfg>; + status = "okay"; + + pmic@41 { + compatible = "spacemit,p1"; + reg = <0x41>; + interrupts = <64>; + vin1-supply = <&vcc4v0>; + vin2-supply = <&vcc4v0>; + vin3-supply = <&vcc4v0>; + vin4-supply = <&vcc4v0>; + vin5-supply = <&vcc4v0>; + vin6-supply = <&vcc4v0>; + aldoin-supply = <&vcc4v0>; + dldoin1-supply = <&buck5>; + dldoin2-supply = <&buck5>; + + regulators { + buck1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck3_1v8: buck3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck4_3v3: buck4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck5: buck5 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck6 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + aldo1_3v3: aldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + + aldo2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + aldo3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + aldo4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + + dldo2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-always-on; + }; + + dldo5 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo6 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-always-on; + }; + + dldo7 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + }; + }; +}; + &pdma { status = "okay"; }; From ab1375e25ea3fef62a4a5a93abf5d03d67aaf99c Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 6 May 2026 00:52:43 +0800 Subject: [PATCH 547/665] arm64: dts: rockchip: Fix EEPROM compatible on rk3399-nanopi-r4s-enterprise The EEPROM used on the R4S (enterprise) is the 24AA025E48T-I/OT from MicroChip. This is a 2-Kbit EEPROM with 16-byte page size. The latter half of the EEPROM is read-only, and the last 48 bits contain a globally unique MAC address. That is to say this is not an ordinary EEPROM. The compatible for this type of EEPROM was introduced later that the board. Switch over to the correct compatible now that it is available. Signed-off-by: Chen-Yu Tsai Link: https://patch.msgid.link/20260505165244.1902-1-wens@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts index b76f98962076..e366f1a04b32 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts @@ -16,7 +16,7 @@ &gmac { &i2c2 { eeprom@51 { - compatible = "microchip,24c02", "atmel,24c02"; + compatible = "microchip,24aa025e48"; reg = <0x51>; pagesize = <16>; size = <256>; From 8333fe46b0010d110b36f1628dd8dfc77d2c389a Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 6 May 2026 01:29:02 +0800 Subject: [PATCH 548/665] arm64: dts: rockchip: Disable removed devices from rk3399-nanopi-r4s While the design of the NanoPi R4S is based on the common NanoPi 4 family, it is trimmed down a lot. Disable all the peripherals on the SoC that are not used, and delete all the external components that are not present. Signed-off-by: Chen-Yu Tsai [feels like the cleaner option, than to move those peripherals into a new rk3399-nanopi-allothers.dtsi, as the r4s variants are not as many ] Link: https://patch.msgid.link/20260505172903.33271-1-wens@kernel.org Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-nanopi-r4s.dtsi | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi index 3a9a10f531bd..4274d1b6e80a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi @@ -66,16 +66,41 @@ &emmc_phy { status = "disabled"; }; +/* No USB type-C PD power manager */ +/delete-node/ &fusb0; + +&i2c1 { + status = "disabled"; +}; + &i2c4 { status = "disabled"; }; +&i2c7 { + status = "disabled"; +}; + +&i2s2 { + status = "disabled"; +}; + +&hdmi { + status = "disabled"; +}; + +&hdmi_sound { + status = "disabled"; +}; + &pcie0 { num-lanes = <1>; vpcie3v3-supply = <&vcc3v3_sys>; }; &pinctrl { + /delete-node/ fusb30x; + gpio-leds { /delete-node/ status-led-pin; @@ -101,14 +126,21 @@ reset_button_pin: reset-button-pin { }; }; +&pwm0 { + status = "disabled"; +}; + &sdhci { status = "disabled"; }; &sdio0 { + /delete-property/ mmc-pwrseq; status = "disabled"; }; +/delete-node/ &sdio_pwrseq; + &u2phy0_host { phy-supply = <&vdd_5v>; }; @@ -119,12 +151,48 @@ &u2phy1_host { &uart0 { status = "disabled"; + + /delete-node/ bluetooth; }; +&u2phy1_host { + status = "disabled"; +}; + +&usb_host1_ehci { + status = "disabled"; +}; + +&usb_host1_ohci { + status = "disabled"; +}; &usbdrd_dwc3_0 { dr_mode = "host"; }; +/delete-node/ &vbus_typec; + &vcc3v3_sys { vin-supply = <&vcc5v0_sys>; }; + +&vopb { + status = "disabled"; +}; + +&vopb_mmu { + status = "disabled"; +}; + +&vopl { + status = "disabled"; +}; + +&vopl_mmu { + status = "disabled"; +}; + +/delete-node/ &bt_host_wake_l; +/delete-node/ &bt_reg_on_h; +/delete-node/ &bt_wake_l; +/delete-node/ &wifi_reg_on_h; From 720fe68fd9f138ada2936ffcf3dd0129a889455a Mon Sep 17 00:00:00 2001 From: Gray Huang Date: Thu, 7 May 2026 11:35:40 +0800 Subject: [PATCH 549/665] arm64: dts: rockchip: Enable USB for Khadas Edge 2L The Khadas Edge 2L board provides one USB 3.0 Host port and one USB 2.0 port (connected via an internal hub). Enable the corresponding DWC3 controllers and PHYs. Signed-off-by: Gray Huang Link: https://patch.msgid.link/20260507033541.2576335-2-gray.huang@wesion.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3576-khadas-edge-2l.dts | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts b/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts index e7fe22eb31a3..967a95ce01de 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts @@ -30,6 +30,29 @@ hdmi_con_in: endpoint { }; }; + vcc5v0_device: regulator-vcc5v0-device { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_device"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_host: regulator-vcc5v0-host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren>; + vin-supply = <&vcc5v0_device>; + }; + vcc_sys: regulator-vcc5v0-sys { compatible = "regulator-fixed"; regulator-name = "vcc_sys"; @@ -78,6 +101,10 @@ &combphy0_ps { status = "okay"; }; +&combphy1_psu { + status = "okay"; +}; + &cpu_l0 { cpu-supply = <&vdd_cpu_lit_s0>; }; @@ -531,6 +558,12 @@ pcie0_rst: pcie0-rst { }; }; + usb { + usb_host_pwren: usb-host-pwren { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + wifi { wifi_reg_on: wifi-reg-on { rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; @@ -552,10 +585,24 @@ &sdhci { status = "okay"; }; +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + &uart0 { status = "okay"; }; +&usb_drd1_dwc3 { + dr_mode = "host"; + status = "okay"; +}; + &vop { status = "okay"; }; From ef81db2fdd5a75e3834a4726dc7837f6d2a7229d Mon Sep 17 00:00:00 2001 From: Gray Huang Date: Thu, 7 May 2026 11:35:41 +0800 Subject: [PATCH 550/665] arm64: dts: rockchip: Add Bluetooth support for Khadas Edge 2L Enable Bluetooth support for the Ampak AP6275P module on the Khadas Edge 2L. This involves enabling the UART5 interface for HCI communication and defining the required regulators and power-sequence pins. Signed-off-by: Gray Huang Link: https://patch.msgid.link/20260507033541.2576335-3-gray.huang@wesion.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3576-khadas-edge-2l.dts | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts b/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts index 967a95ce01de..3121a0ba7c7c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts @@ -552,6 +552,20 @@ wifi: wifi@0,0 { }; &pinctrl { + bluetooth { + bt_reg_on: bt-reg-on { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + bt_wake_host: bt-wake-host { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + host_wake_bt: host-wake-bt { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + pcie0 { pcie0_rst: pcie0-rst { rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; @@ -598,6 +612,27 @@ &uart0 { status = "okay"; }; +&uart5 { + pinctrl-0 = <&uart5m1_xfer &uart5m1_ctsn &uart5m1_rtsn>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&hym8563>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-0 = <&bt_reg_on &bt_wake_host &host_wake_bt>; + pinctrl-names = "default"; + shutdown-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + vbat-supply = <&vcc_3v3_s3>; + vddio-supply = <&vcc_1v8_s3>; + }; +}; + &usb_drd1_dwc3 { dr_mode = "host"; status = "okay"; From 6570a6354bd35619070bedd71dee027b5ecf6006 Mon Sep 17 00:00:00 2001 From: Eduard Bostina Date: Mon, 23 Mar 2026 19:59:44 +0200 Subject: [PATCH 551/665] dt-bindings: watchdog: Convert TS-4800 to DT schema Convert the Technologic Systems TS-4800 watchdog timer bindings to DT schema. Signed-off-by: Eduard Bostina Reviewed-by: Guenter Roeck Reviewed-by: Krzysztof Kozlowski Signed-off-by: Frank Li --- .../watchdog/technologic,ts4800-wdt.yaml | 40 +++++++++++++++++++ .../bindings/watchdog/ts4800-wdt.txt | 25 ------------ 2 files changed, 40 insertions(+), 25 deletions(-) create mode 100644 Documentation/devicetree/bindings/watchdog/technologic,ts4800-wdt.yaml delete mode 100644 Documentation/devicetree/bindings/watchdog/ts4800-wdt.txt diff --git a/Documentation/devicetree/bindings/watchdog/technologic,ts4800-wdt.yaml b/Documentation/devicetree/bindings/watchdog/technologic,ts4800-wdt.yaml new file mode 100644 index 000000000000..5c2541ac60cf --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/technologic,ts4800-wdt.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/technologic,ts4800-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Technologic Systems TS-4800 Watchdog + +maintainers: + - Eduard Bostina + +properties: + compatible: + const: technologic,ts4800-wdt + + syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to the FPGA's syscon + - description: Offset to the watchdog register + description: Phandle / integers array that points to the syscon node which + describes the FPGA's syscon registers. + +required: + - compatible + - syscon + +allOf: + - $ref: watchdog.yaml# + +unevaluatedProperties: false + +examples: + - | + watchdog { + compatible = "technologic,ts4800-wdt"; + syscon = <&syscon 0xe>; + timeout-sec = <10>; + }; diff --git a/Documentation/devicetree/bindings/watchdog/ts4800-wdt.txt b/Documentation/devicetree/bindings/watchdog/ts4800-wdt.txt deleted file mode 100644 index 8f6caad4258d..000000000000 --- a/Documentation/devicetree/bindings/watchdog/ts4800-wdt.txt +++ /dev/null @@ -1,25 +0,0 @@ -Technologic Systems Watchdog - -Required properties: -- compatible: must be "technologic,ts4800-wdt" -- syscon: phandle / integer array that points to the syscon node which - describes the FPGA's syscon registers. - - phandle to FPGA's syscon - - offset to the watchdog register - -Optional property: -- timeout-sec: contains the watchdog timeout in seconds. - -Example: - -syscon: syscon@b0010000 { - compatible = "syscon", "simple-mfd"; - reg = <0xb0010000 0x3d>; - reg-io-width = <2>; - - wdt@e { - compatible = "technologic,ts4800-wdt"; - syscon = <&syscon 0xe>; - timeout-sec = <10>; - }; -} From dcf7bac8c2470a61cd457ed2e6f57960004ca392 Mon Sep 17 00:00:00 2001 From: Eduard Bostina Date: Mon, 23 Mar 2026 19:59:45 +0200 Subject: [PATCH 552/665] ARM: dts: nxp: imx51-ts4800: Rename wdt node to watchdog The Technologic Systems TS-4800 watchdog node was previously named 'wdt', which violates the core watchdog.yaml schema expecting generic node names. Rename the node to 'watchdog' to fix the following dtbs_check warning: 'wdt' does not match '^(pmic|timer|watchdog)(@.*|-([0-9]|[1-9][0-9]+))?$' Signed-off-by: Eduard Bostina Reviewed-by: Daniel Baluta Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts b/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts index 079bd3d14999..4427d178be2c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts +++ b/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts @@ -155,7 +155,7 @@ syscon: syscon@10000 { reg = <0x10000 0x3d>; reg-io-width = <2>; - wdt { + watchdog { compatible = "technologic,ts4800-wdt"; syscon = <&syscon 0xe>; }; From 9dc39532172cbbc9e4fd5ef4e955b84ed5d96402 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Wed, 22 Apr 2026 17:35:42 +0800 Subject: [PATCH 553/665] ARM: dts: imx6qdl: Add Root Port node and PERST property Since describing the PCIe PERST# property under Host Bridge node is now deprecated, it is recommended to add it to the Root Port node, so creating the Root Port node and add the reset-gpios property in Root Port. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts | 17 ++++------------- arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi | 5 +++++ arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi | 11 +++++++++++ arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts | 5 +++++ 4 files changed, 25 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts b/arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts index c78f101c3cc1..2ddd71f09da3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts @@ -323,19 +323,10 @@ &ipu1_di0_disp0 { remote-endpoint = <¶llel_display_in>; }; -&pcie { - pcie@0,0 { - reg = <0x000000 0 0 0 0>; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - ranges; - - /* non-removable i211 ethernet card */ - eth1: ethernet@0,0 { - reg = <0x010000 0 0 0 0>; - }; +&pcie_port0 { + /* non-removable i211 ethernet card */ + eth1: ethernet@0,0 { + reg = <0x010000 0 0 0 0>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi index ba29720e3f72..fe9046c03ddd 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi @@ -754,11 +754,16 @@ lvds0_out: endpoint { &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; + /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; vpcie-supply = <®_pcie>; status = "okay"; }; +&pcie_port0 { + reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; +}; + &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi index 76e6043e1f91..eeb376193398 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi @@ -289,6 +289,17 @@ pcie: pcie@1ffc000 { <&clks IMX6QDL_CLK_PCIE_REF_125M>; clock-names = "pcie", "pcie_bus", "pcie_phy"; status = "disabled"; + + pcie_port0: pcie@0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; aips1: bus@2000000 { /* AIPS1 */ diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts index c5b220aeaefd..6b12cab7175f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts @@ -45,10 +45,15 @@ MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 }; &pcie { + /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>; status = "okay"; }; +&pcie_port0 { + reset-gpios = <&max7310_c 5 GPIO_ACTIVE_LOW>; +}; + &sata { status = "okay"; }; From f96840444d86b3834f0b1a306d7f8a597fdcabd8 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Wed, 22 Apr 2026 17:35:43 +0800 Subject: [PATCH 554/665] ARM: dts: imx6sx: Add Root Port node and PERST property Since describing the PCIe PERST# property under Host Bridge node is now deprecated, it is recommended to add it to the Root Port node, so creating the Root Port node and add the reset-gpios property in Root Port. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi | 5 +++++ arch/arm/boot/dts/nxp/imx/imx6sx.dtsi | 11 +++++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi index 3e238d8118fa..338de4d144b2 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi @@ -282,11 +282,16 @@ codec: wm8962@1a { &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; + /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&gpio2 0 GPIO_ACTIVE_LOW>; vpcie-supply = <®_pcie_gpio>; status = "okay"; }; +&pcie_port0 { + reset-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; +}; + &lcdif1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcd>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi index 1426f357d474..d42363cb5105 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi @@ -1470,6 +1470,17 @@ pcie: pcie@8ffc000 { power-domains = <&pd_disp>, <&pd_pci>; power-domain-names = "pcie", "pcie_phy"; status = "disabled"; + + pcie_port0: pcie@0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; }; }; From 01f13c165d1c43b1c941875bfade26a279121829 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Wed, 22 Apr 2026 17:35:44 +0800 Subject: [PATCH 555/665] ARM: dts: imx7d: Add Root Port node and PERST property Since describing the PCIe PERST# property under Host Bridge node is now deprecated, it is recommended to add it to the Root Port node, so creating the Root Port node and add the reset-gpios property in Root Port. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts | 5 +++++ arch/arm/boot/dts/nxp/imx/imx7d.dtsi | 11 +++++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts b/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts index a370e868cafe..0046b276b8b9 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts @@ -456,10 +456,15 @@ display_out: endpoint { }; &pcie { + /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>; status = "okay"; }; +&pcie_port0 { + reset-gpios = <&extended_io 1 GPIO_ACTIVE_LOW>; +}; + ®_1p0d { vin-supply = <&sw2_reg>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d.dtsi b/arch/arm/boot/dts/nxp/imx/imx7d.dtsi index d961c61a93af..3c5c1f2c1460 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7d.dtsi @@ -155,6 +155,17 @@ pcie: pcie@33800000 { reset-names = "pciephy", "apps", "turnoff"; fsl,imx7d-pcie-phy = <&pcie_phy>; status = "disabled"; + + pcie_port0: pcie@0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; }; }; From a767ab8ae66e574c6427ab88f55e9e43471edb4e Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 11 May 2026 17:04:57 -0400 Subject: [PATCH 556/665] ARM: dts: imx: add ti,deskew = <0> for ti,tfp410 Add required proprety ti,deskew for ti,tfp410, which have not defined default value in yaml. 0 is default value according to drivers/gpu/drm/bridge/ti-tfp410.c. Fix below check_dtbs warning: dvi-encoder (ti,tfp410): 'ti,deskew' is a required property Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx51-babbage.dts | 1 + arch/arm/boot/dts/nxp/imx/imx53-cx9020.dts | 1 + arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx51-babbage.dts b/arch/arm/boot/dts/nxp/imx/imx51-babbage.dts index 1b6ec55f9068..6129795947d3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx51-babbage.dts +++ b/arch/arm/boot/dts/nxp/imx/imx51-babbage.dts @@ -126,6 +126,7 @@ dvi_connector_in: endpoint { dvi-encoder { compatible = "ti,tfp410"; + ti,deskew = <0>; ports { #address-cells = <1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-cx9020.dts b/arch/arm/boot/dts/nxp/imx/imx53-cx9020.dts index 0814f5665a59..02be8b6da696 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-cx9020.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-cx9020.dts @@ -60,6 +60,7 @@ dvi_connector_in: endpoint { dvi-converter { compatible = "ti,tfp410"; + ti,deskew = <0>; ports { #address-cells = <1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts b/arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts index 2ddd71f09da3..c69052d776e3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts @@ -61,6 +61,7 @@ aliases { encoder { compatible = "ti,tfp410"; + ti,deskew = <0>; ports { #address-cells = <1>; From d6af25d182b2ece6223dbba0084b269526d3a5ae Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 11 May 2026 17:04:58 -0400 Subject: [PATCH 557/665] ARM: dts: imx53-qsb: add dvdd and avdd supply for panel sii,43wvf1g Add dvdd and avdd supply and regulators for panel sii,43wvf1g to fix below check_dtbs warnings: panel (sii,43wvf1g): 'dvdd-supply' is a required property Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx53-qsb-common.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx53-qsb-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-qsb-common.dtsi index 1869ad86baf2..d3b27dc3c2c7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-qsb-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx53-qsb-common.dtsi @@ -91,6 +91,8 @@ panel_dpi: panel { pinctrl-0 = <&pinctrl_display_power>; backlight = <&backlight_parallel>; enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; + dvdd-supply = <®_3p2v>; + avdd-supply = <®_5v>; port { panel_in: endpoint { @@ -107,6 +109,14 @@ reg_3p2v: regulator-3p2v { regulator-always-on; }; + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + reg_usb_vbus: regulator-usb-vbus { compatible = "regulator-fixed"; regulator-name = "usb_vbus"; From 740e76b89b1cd75f519a949b77954ff9cf71c82f Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 11 May 2026 17:04:59 -0400 Subject: [PATCH 558/665] ARM: dts: imx53-ppd: add '#phy-cells' for usb-nop-xceiv Add '#phy-cells' for usb-nop-xceiv to fix below check_dtbs warnings: usbphy-2 (usb-nop-xceiv): '#phy-cells' is a required property Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx53-ppd.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx53-ppd.dts b/arch/arm/boot/dts/nxp/imx/imx53-ppd.dts index e45a97d3f449..f0fb88c14171 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-ppd.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-ppd.dts @@ -258,6 +258,7 @@ usbphy2: usbphy-2 { clock-names = "main_clk"; clock-frequency = <24000000>; clocks = <&clks IMX5_CLK_CKO2>; + #phy-cells = <0>; assigned-clocks = <&clks IMX5_CLK_CKO2_SEL>, <&clks IMX5_CLK_OSC>; assigned-clock-parents = <&clks IMX5_CLK_OSC>; }; @@ -270,6 +271,7 @@ usbphy3: usbphy-3 { clock-frequency = <24000000>; clocks = <&clks IMX5_CLK_CKO2>; + #phy-cells = <0>; assigned-clocks = <&clks IMX5_CLK_CKO2_SEL>, <&clks IMX5_CLK_OSC>; assigned-clock-parents = <&clks IMX5_CLK_OSC>; }; From 0407ad56fbbfba2007b3195d6fb22520784677de Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Tue, 5 May 2026 13:02:39 +0200 Subject: [PATCH 559/665] dt-bindings: arm: apple: apple,pmgr: Add t8122 compatible The PMGR blocks on Apple silicon M3 SoCs (t8122) are compatible with the M1 and M2 predecessors. Add "apple,t8122-pmgr" as M3 specific compatible. Acked-by: Rob Herring (Arm) Reviewed-by: Joshua Peisach Reviewed-by: Neal Gompa Signed-off-by: Janne Grunau Link: https://patch.msgid.link/20260505-apple-m3-initial-devicetrees-v2-1-b0c2f3519e0e@jannau.net Signed-off-by: Sven Peter --- Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml index b88f41a225a3..c67b67ba065a 100644 --- a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml +++ b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml @@ -36,7 +36,9 @@ properties: - const: syscon - const: simple-mfd - items: - - const: apple,t6020-pmgr + - enum: + - apple,t6020-pmgr + - apple,t8122-pmgr - const: apple,t8103-pmgr - const: syscon - const: simple-mfd From 161cd94f5b28301d1997f5341328a7cbcf9c95ee Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Thu, 7 May 2026 09:33:07 +0200 Subject: [PATCH 560/665] dt-bindings: power: apple,pmgr-pwrstate: Add t8122 compatible The device power state management of the PMGR blocks on Apple's t8122 SoC (M3) is compatible with the existing driver. Add "apple,t8122-pmgr-pwrstate" as SoC specific compatible under the existing "apple,t8103-pmgr-pwrstate" used by the driver. Acked-by: Rob Herring (Arm) Reviewed-by: Joshua Peisach Reviewed-by: Neal Gompa Signed-off-by: Janne Grunau Link: https://patch.msgid.link/20260507-apple-m3-initial-devicetrees-v3-1-ca07c81b5dc7@jannau.net Signed-off-by: Sven Peter --- .../devicetree/bindings/power/apple,pmgr-pwrstate.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml index caf151880999..c9be097cfba0 100644 --- a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml +++ b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml @@ -43,7 +43,9 @@ properties: - apple,t6000-pmgr-pwrstate - const: apple,pmgr-pwrstate - items: - - const: apple,t6020-pmgr-pwrstate + - enum: + - apple,t6020-pmgr-pwrstate + - apple,t8122-pmgr-pwrstate - const: apple,t8103-pmgr-pwrstate reg: From dfb9cf11f8282b6497164d5ee4542f469396c5ff Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Thu, 7 May 2026 09:33:09 +0200 Subject: [PATCH 561/665] dt-bindings: pwm: apple,s5l-fpwm: Add t8122 compatible MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The PWM controller on the Apple silicon t8122 (M3) SoC is compatible with the existing driver. Add "apple,t8122-fpwm" as SoC specific compatible under "apple,s5l-fpwm" used by the driver. Acked-by: Rob Herring (Arm) Acked-by: Uwe Kleine-König Reviewed-by: Joshua Peisach Reviewed-by: Neal Gompa Signed-off-by: Janne Grunau Link: https://patch.msgid.link/20260507-apple-m3-initial-devicetrees-v3-3-ca07c81b5dc7@jannau.net Signed-off-by: Sven Peter --- Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml b/Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml index d8f4f9ffe884..25ef04b60ca1 100644 --- a/Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml +++ b/Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml @@ -18,6 +18,7 @@ properties: - enum: - apple,t8103-fpwm - apple,t8112-fpwm + - apple,t8122-fpwm - apple,t6000-fpwm - apple,t6020-fpwm - const: apple,s5l-fpwm From 01f38c14423eefcbb764541b03006316ecd6a42f Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Thu, 7 May 2026 09:33:10 +0200 Subject: [PATCH 562/665] dt-bindings: arm: apple: Add M3 based devices The Apple devices with the t8122 SoC (M3) are very similar to their M1 and M2 predecessors. Only the 13-inch Macbook Pro is replaced by a 14-inch version based on the design of the 14-inch Macbook Pro with (M1/M2 Pro/Max). The Mac mini was not offered with M3. Acked-by: Rob Herring (Arm) Reviewed-by: Joshua Peisach Reviewed-by: Neal Gompa Signed-off-by: Janne Grunau Link: https://patch.msgid.link/20260507-apple-m3-initial-devicetrees-v3-4-ca07c81b5dc7@jannau.net Signed-off-by: Sven Peter --- .../devicetree/bindings/arm/apple.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/apple.yaml b/Documentation/devicetree/bindings/arm/apple.yaml index 5c2629ec3d4c..e49403c73f9d 100644 --- a/Documentation/devicetree/bindings/arm/apple.yaml +++ b/Documentation/devicetree/bindings/arm/apple.yaml @@ -96,6 +96,13 @@ description: | - MacBook Pro (13-inch, M2, 2022) - Mac mini (M2, 2023) + Devices based on the "M3" SoC: + + - MacBook Air (13-inch, M3, 2024) + - MacBook Air (15-inch, M3, 2024) + - MacBook Pro (14-inch, M3, 2023) + - iMac (24-inch, M3, 2023) + Devices based on the "M1 Pro", "M1 Max" and "M1 Ultra" SoCs: - MacBook Pro (14-inch, M1 Pro, 2021) @@ -297,6 +304,17 @@ properties: - const: apple,t8112 - const: apple,arm-platform + - description: Apple M3 SoC based platforms + items: + - enum: + - apple,j433 # iMac (24-inch, 2x USB-C, M3, 2023) + - apple,j434 # iMac (24-inch, 4x USB-C, M3, 2023) + - apple,j504 # MacBook Pro (14-inch, M3, 2023) + - apple,j613 # MacBook Air (13-inch, M3, 2024) + - apple,j615 # MacBook Air (15-inch, M3, 2024) + - const: apple,t8122 + - const: apple,arm-platform + - description: Apple M1 Pro SoC based platforms items: - enum: From c65ab4905e5874a1a489c72da4d6e78a6c9b5943 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Thu, 7 May 2026 09:33:11 +0200 Subject: [PATCH 563/665] arm64: dts: apple: Initial t8122 (M3) device trees Add minimal device trees for all t8122 based devices. The devices are - iMac (24-inch, M3, 2023) - MacBook Air (13-inch, M3, 2024) - MacBook Air (15-inch, M3, 2024) - MacBook Pro (14-inch, M3, 2023) The device trees have a minimal set of devices limited to CPU cores, interrupt controller, power states, watchdog, serial, pin controller, i2c and the boot framebuffer. The device trees for the notebooks add a PWM controller for the keyboard LED illumination. The iMacs and the 14-inch device trees add the i2c based Apple cd321x USB Type-C port controller. Co-developed-by: Michael Reeves Signed-off-by: Michael Reeves Reviewed-by: Joshua Peisach Reviewed-by: Neal Gompa Signed-off-by: Janne Grunau Link: https://patch.msgid.link/20260507-apple-m3-initial-devicetrees-v3-5-ca07c81b5dc7@jannau.net Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/Makefile | 5 + arch/arm64/boot/dts/apple/t8122-j433.dts | 19 + arch/arm64/boot/dts/apple/t8122-j434.dts | 19 + arch/arm64/boot/dts/apple/t8122-j504.dts | 37 + arch/arm64/boot/dts/apple/t8122-j613.dts | 35 + arch/arm64/boot/dts/apple/t8122-j615.dts | 35 + arch/arm64/boot/dts/apple/t8122-jxxx.dtsi | 48 + arch/arm64/boot/dts/apple/t8122-pmgr.dtsi | 1149 +++++++++++++++++ .../arm64/boot/dts/apple/t8122-usbpd-i2c.dtsi | 32 + arch/arm64/boot/dts/apple/t8122.dtsi | 444 +++++++ 10 files changed, 1823 insertions(+) create mode 100644 arch/arm64/boot/dts/apple/t8122-j433.dts create mode 100644 arch/arm64/boot/dts/apple/t8122-j434.dts create mode 100644 arch/arm64/boot/dts/apple/t8122-j504.dts create mode 100644 arch/arm64/boot/dts/apple/t8122-j613.dts create mode 100644 arch/arm64/boot/dts/apple/t8122-j615.dts create mode 100644 arch/arm64/boot/dts/apple/t8122-jxxx.dtsi create mode 100644 arch/arm64/boot/dts/apple/t8122-pmgr.dtsi create mode 100644 arch/arm64/boot/dts/apple/t8122-usbpd-i2c.dtsi create mode 100644 arch/arm64/boot/dts/apple/t8122.dtsi diff --git a/arch/arm64/boot/dts/apple/Makefile b/arch/arm64/boot/dts/apple/Makefile index 4eebcd85c90f..6fc3349a5842 100644 --- a/arch/arm64/boot/dts/apple/Makefile +++ b/arch/arm64/boot/dts/apple/Makefile @@ -91,3 +91,8 @@ dtb-$(CONFIG_ARCH_APPLE) += t8112-j413.dtb dtb-$(CONFIG_ARCH_APPLE) += t8112-j415.dtb dtb-$(CONFIG_ARCH_APPLE) += t8112-j473.dtb dtb-$(CONFIG_ARCH_APPLE) += t8112-j493.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8122-j433.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8122-j434.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8122-j504.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8122-j613.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8122-j615.dtb diff --git a/arch/arm64/boot/dts/apple/t8122-j433.dts b/arch/arm64/boot/dts/apple/t8122-j433.dts new file mode 100644 index 000000000000..34205d173a9b --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8122-j433.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iMac (24-inch, 2x USB-C, M3, 2023) + * + * target-type: J433 + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t8122.dtsi" +#include "t8122-usbpd-i2c.dtsi" +#include "t8122-jxxx.dtsi" + +/ { + compatible = "apple,j433", "apple,t8122", "apple,arm-platform"; + model = "Apple iMac (24-inch, 2x USB-C, M3, 2023)"; +}; diff --git a/arch/arm64/boot/dts/apple/t8122-j434.dts b/arch/arm64/boot/dts/apple/t8122-j434.dts new file mode 100644 index 000000000000..ead5afd77efb --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8122-j434.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iMac (24-inch, 4x USB-C, M3, 2023) + * + * target-type: J434 + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t8122.dtsi" +#include "t8122-usbpd-i2c.dtsi" +#include "t8122-jxxx.dtsi" + +/ { + compatible = "apple,j434", "apple,t8122", "apple,arm-platform"; + model = "Apple iMac (24-inch, 4x USB-C, M3, 2023)"; +}; diff --git a/arch/arm64/boot/dts/apple/t8122-j504.dts b/arch/arm64/boot/dts/apple/t8122-j504.dts new file mode 100644 index 000000000000..464491b55b01 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8122-j504.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple MacBook Pro (14-inch, M3, 2023) + * + * target-type: J504 + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t8122.dtsi" +#include "t8122-usbpd-i2c.dtsi" +#include "t8122-jxxx.dtsi" +#include + +/ { + compatible = "apple,j504", "apple,t8122", "apple,arm-platform"; + model = "Apple MacBook Pro (14-inch, M3, 2023)"; + + led-controller { + compatible = "pwm-leds"; + led-0 { + pwms = <&fpwm1 0 40000>; + label = "kbd_backlight"; + function = LED_FUNCTION_KBD_BACKLIGHT; + color = ; + max-brightness = <255>; + default-state = "keep"; + }; + }; +}; + +&fpwm1 { + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/apple/t8122-j613.dts b/arch/arm64/boot/dts/apple/t8122-j613.dts new file mode 100644 index 000000000000..51894ea705e7 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8122-j613.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple MacBook Air (13-inch, M3, 2024) + * + * target-type: J613 + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t8122.dtsi" +#include "t8122-jxxx.dtsi" +#include + +/ { + compatible = "apple,j613", "apple,t8122", "apple,arm-platform"; + model = "Apple MacBook Air (13-inch, M3, 2024)"; + + led-controller { + compatible = "pwm-leds"; + led-0 { + pwms = <&fpwm1 0 40000>; + label = "kbd_backlight"; + function = LED_FUNCTION_KBD_BACKLIGHT; + color = ; + max-brightness = <255>; + default-state = "keep"; + }; + }; +}; + +&fpwm1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t8122-j615.dts b/arch/arm64/boot/dts/apple/t8122-j615.dts new file mode 100644 index 000000000000..2a1970c1bc90 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8122-j615.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple MacBook Air (15-inch, M3, 2024) + * + * target-type: J615 + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t8122.dtsi" +#include "t8122-jxxx.dtsi" +#include + +/ { + compatible = "apple,j615", "apple,t8122", "apple,arm-platform"; + model = "Apple MacBook Air (15-inch, M3, 2024)"; + + led-controller { + compatible = "pwm-leds"; + led-0 { + pwms = <&fpwm1 0 40000>; + label = "kbd_backlight"; + function = LED_FUNCTION_KBD_BACKLIGHT; + color = ; + max-brightness = <255>; + default-state = "keep"; + }; + }; +}; + +&fpwm1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t8122-jxxx.dtsi b/arch/arm64/boot/dts/apple/t8122-jxxx.dtsi new file mode 100644 index 000000000000..dd85f0c9fb1e --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8122-jxxx.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple M3 MacBook Air/Pro and iMac (M3, 2023/2024) + * + * This file contains parts common to all Apple M3 devices using the t8122. + * + * target-type: J433, J434, J504, J613, J615 + * + * Copyright The Asahi Linux Contributors + */ + +/ { + aliases { + serial0 = &serial0; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0"; + + framebuffer0: framebuffer@0 { + compatible = "apple,simple-framebuffer", "simple-framebuffer"; + reg = <0 0 0 0>; /* To be filled by loader */ + power-domains = <&ps_disp_cpu>, <&ps_dptx_ext_phy>; + /* Format properties will be added by loader */ + status = "disabled"; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + /* To be filled by loader */ + }; + + memory@800000000 { + device_type = "memory"; + reg = <0x8 0 0x2 0>; /* To be filled by loader */ + }; +}; + +&serial0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t8122-pmgr.dtsi b/arch/arm64/boot/dts/apple/t8122-pmgr.dtsi new file mode 100644 index 000000000000..64093792e0ad --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8122-pmgr.dtsi @@ -0,0 +1,1149 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple T8122 "M3" SoC + * + * Copyright The Asahi Linux Contributors + */ + +&pmgr { + ps_sbr: power-controller@100 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sbr"; + apple,always-on; /* Core device */ + }; + + ps_msg: power-controller@108 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msg"; + }; + + ps_aic: power-controller@110 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aic"; + apple,always-on; /* Core device */ + }; + + ps_dwi: power-controller@118 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dwi"; + }; + + ps_gpio: power-controller@120 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gpio"; + }; + + ps_pms_busif: power-controller@128 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_busif"; + apple,always-on; /* Core device */ + }; + + ps_pms: power-controller@130 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms"; + apple,always-on; /* Core device */ + }; + + ps_pms_fpwm0: power-controller@138 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_fpwm0"; + power-domains = <&ps_pms>; + }; + + ps_pms_fpwm1: power-controller@140 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_fpwm1"; + power-domains = <&ps_pms>; + }; + + ps_pms_fpwm2: power-controller@148 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_fpwm2"; + power-domains = <&ps_pms>; + }; + + ps_pms_fpwm3: power-controller@150 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x150 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_fpwm3"; + power-domains = <&ps_pms>; + }; + + ps_pms_fpwm4: power-controller@158 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x158 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_fpwm4"; + power-domains = <&ps_pms>; + }; + + ps_pms_c1ppt: power-controller@160 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x160 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_c1ppt"; + }; + + ps_soc_rc: power-controller@168 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "soc_rc"; + }; + + ps_soc_dpe: power-controller@170 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "soc_dpe"; + apple,always-on; + }; + + ps_pmgr_soc_ocla: power-controller@178 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pmgr_soc_ocla"; + power-domains = <&ps_pms>; + }; + + ps_ispsens0: power-controller@180 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens0"; + }; + + ps_ispsens1: power-controller@188 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens1"; + }; + + ps_ispsens2: power-controller@190 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens2"; + }; + + ps_ispsens3: power-controller@198 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens3"; + }; + + ps_aft0: power-controller@1a8 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aft0"; + }; + + ps_ioa0: power-controller@1b0 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ioa0"; + apple,always-on; + }; + + ps_ap_tmm: power-controller@1b8 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ap_tmm"; + }; + + ps_disp_sys: power-controller@1d8 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp_sys"; + apple,always-on; /* TODO: figure out if we can enable PM here */ + }; + + ps_gfx: power-controller@1e0 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gfx"; + }; + + ps_isp_sys: power-controller@1e8 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sys"; + }; + + ps_avd_sys: power-controller@1f0 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "avd_sys"; + }; + + ps_jpg: power-controller@200 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x200 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "jpg"; + }; + + ps_disp_fe: power-controller@208 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x208 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp_fe"; + power-domains = <&ps_disp_sys>; + apple,always-on; /* TODO: figure out if we can enable PM here */ + }; + + ps_sio_cpu: power-controller@210 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x210 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_cpu"; + }; + + ps_fpwm0: power-controller@218 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x218 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "fpwm0"; + }; + + ps_fpwm1: power-controller@220 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x220 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "fpwm1"; + }; + + ps_fpwm2: power-controller@228 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x228 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "fpwm2"; + }; + + ps_i2c0: power-controller@230 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x230 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c0"; + }; + + ps_i2c1: power-controller@238 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x238 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c1"; + }; + + ps_i2c2: power-controller@240 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x240 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c2"; + }; + + ps_i2c3: power-controller@248 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x248 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c3"; + }; + + ps_i2c4: power-controller@250 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x250 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c4"; + }; + + ps_i2c5: power-controller@258 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x258 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c5"; + }; + + ps_i2c6: power-controller@260 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c6"; + }; + + ps_i2c7: power-controller@268 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x268 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c7"; + }; + + ps_i2c8: power-controller@270 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x270 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c8"; + }; + + ps_spi_p: power-controller@278 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x278 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi_p"; + }; + + ps_uart_p: power-controller@280 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x280 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart_p"; + }; + + ps_audio_p: power-controller@288 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x288 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "audio_p"; + }; + + ps_aes: power-controller@290 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x290 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aes"; + }; + + ps_spi0: power-controller@298 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x298 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi0"; + power-domains = <&ps_spi_p>; + }; + + ps_spi1: power-controller@2a0 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi1"; + power-domains = <&ps_spi_p>; + }; + + ps_spi2: power-controller@2a8 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi2"; + power-domains = <&ps_spi_p>; + }; + + ps_spi3: power-controller@2b0 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi3"; + power-domains = <&ps_spi_p>; + }; + + ps_spi4: power-controller@2b8 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi4"; + power-domains = <&ps_spi_p>; + }; + + ps_spi5: power-controller@2c0 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi5"; + power-domains = <&ps_spi_p>; + }; + + ps_qspi: power-controller@2c8 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "qspi"; + power-domains = <&ps_spi_p>; + }; + + ps_uart_n: power-controller@2d0 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart_n"; + power-domains = <&ps_uart_p>; + }; + + ps_uart0: power-controller@2d8 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart0"; + power-domains = <&ps_uart_p>; + }; + + ps_uart1: power-controller@2e0 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart1"; + power-domains = <&ps_uart_p>; + }; + + ps_uart2: power-controller@2e8 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart2"; + power-domains = <&ps_uart_p>; + }; + + ps_uart3: power-controller@2f0 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart3"; + power-domains = <&ps_uart_p>; + }; + + ps_uart4: power-controller@2f8 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart4"; + power-domains = <&ps_uart_p>; + }; + + ps_uart5: power-controller@300 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x300 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart5"; + power-domains = <&ps_uart_p>; + }; + + ps_uart6: power-controller@308 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x308 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart6"; + power-domains = <&ps_uart_p>; + }; + + ps_sio_adma: power-controller@310 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x310 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_adma"; + power-domains = <&ps_fpwm0>; + }; + + ps_dpa0: power-controller@318 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x318 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dpa0"; + power-domains = <&ps_audio_p>; + }; + + ps_dcs0: power-controller@330 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x330 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs0"; + apple,always-on; + }; + + ps_dcs2: power-controller@338 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x338 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs2"; + apple,always-on; + }; + + ps_dcs1: power-controller@340 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x340 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs1"; + apple,always-on; + }; + + ps_dcs3: power-controller@348 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x348 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs3"; + apple,always-on; + }; + + ps_dcs4: power-controller@358 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x358 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs4"; + apple,always-on; + }; + + ps_dcs5: power-controller@360 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x360 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs5"; + apple,always-on; + }; + + ps_dcs6: power-controller@368 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x368 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs6"; + apple,always-on; + }; + + ps_dcs7: power-controller@370 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x370 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs7"; + apple,always-on; + }; + + ps_dpa1: power-controller@378 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x378 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dpa1"; + power-domains = <&ps_audio_p>; + }; + + ps_dpa2: power-controller@380 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x380 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dpa2"; + power-domains = <&ps_audio_p>; + }; + + ps_dpa3: power-controller@388 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x388 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dpa3"; + power-domains = <&ps_audio_p>; + }; + + ps_dpa4: power-controller@390 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x390 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dpa4"; + power-domains = <&ps_audio_p>; + }; + + ps_mca0: power-controller@398 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x398 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca0"; + power-domains = <&ps_sio_adma>, <&ps_audio_p>; + }; + + ps_mca1: power-controller@3a0 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca1"; + power-domains = <&ps_sio_adma>, <&ps_audio_p>; + }; + + ps_mca2: power-controller@3a8 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca2"; + power-domains = <&ps_sio_adma>, <&ps_audio_p>; + }; + + ps_trace_fab: power-controller@3b0 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "trace_fab"; + }; + + ps_mca3: power-controller@3b8 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca3"; + power-domains = <&ps_sio_adma>, <&ps_audio_p>; + }; + + ps_ioa1: power-controller@3c0 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ioa1"; + apple,always-on; + }; + + ps_apcie: power-controller@3f0 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "apcie"; + }; + + ps_ans: power-controller@3f8 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ans"; + }; + + ps_atc0_common: power-controller@400 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x400 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_common"; + }; + + ps_atc1_common: power-controller@408 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x408 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_common"; + }; + + ps_dispext_sys: power-controller@410 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x410 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dispext_sys"; + }; + + ps_venc_sys: power-controller@418 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x418 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_sys"; + }; + + ps_scodec: power-controller@420 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x420 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "scodec"; + }; + + ps_msr: power-controller@428 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x428 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msr"; + power-domains = <&ps_aft0>; + }; + + ps_dptx_ext_phy: power-controller@430 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x430 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dptx_ext_phy"; + }; + + ps_ane_sys: power-controller@438 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x438 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ane_sys"; + }; + + ps_apcie_gp: power-controller@440 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x440 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "apcie_gp"; + power-domains = <&ps_apcie>; + }; + + ps_apcie_st: power-controller@448 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x448 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "apcie_st"; + power-domains = <&ps_ans>, <&ps_apcie>; + }; + + ps_pmp: power-controller@450 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x450 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pmp"; + apple,always-on; + }; + + ps_pms_sram: power-controller@458 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x458 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_sram"; + apple,always-on; + }; + + ps_atc0_pcie: power-controller@460 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x460 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_pcie"; + power-domains = <&ps_atc0_common>; + }; + + ps_atc0_cio: power-controller@468 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x468 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_cio"; + power-domains = <&ps_atc0_common>; + }; + + ps_atc1_pcie: power-controller@470 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x470 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_pcie"; + power-domains = <&ps_atc1_common>; + }; + + ps_atc1_cio: power-controller@478 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x478 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_cio"; + power-domains = <&ps_atc1_common>; + }; + + ps_dispext_fe: power-controller@480 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x480 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dispext_fe"; + power-domains = <&ps_dispext_sys>; + }; + + ps_dispext_cpu: power-controller@488 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x488 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dispext_cpu"; + power-domains = <&ps_dispext_fe>; + apple,min-state = <4>; + }; + + ps_scodec_stream: power-controller@490 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x490 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "scodec_stream"; + power-domains = <&ps_scodec>; + }; + + ps_msr_ase_core: power-controller@498 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x498 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msr_ase_core"; + power-domains = <&ps_msr>; + }; + + ps_apcie_phy_sw: power-controller@4a0 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "apcie_phy_sw"; + power-domains = <&ps_apcie_st>, <&ps_apcie_gp>; + }; + + ps_atc0_cio_pcie: power-controller@4a8 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_cio_pcie"; + power-domains = <&ps_atc0_cio>; + }; + + ps_atc0_cio_usb: power-controller@4b0 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_cio_usb"; + power-domains = <&ps_atc0_cio>; + }; + + ps_atc1_cio_pcie: power-controller@4b8 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_cio_pcie"; + power-domains = <&ps_atc1_cio>; + }; + + ps_atc1_cio_usb: power-controller@4c0 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_cio_usb"; + power-domains = <&ps_atc1_cio>; + }; + + ps_sep: power-controller@c00 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xc00 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sep"; + apple,always-on; + }; + + ps_venc_dma: power-controller@8000 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x8000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_dma"; + power-domains = <&ps_venc_sys>; + }; + + ps_venc_pipe4: power-controller@8008 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x8008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe4"; + power-domains = <&ps_venc_dma>; + }; + + ps_venc_pipe5: power-controller@8010 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x8010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe5"; + power-domains = <&ps_venc_dma>; + }; + + ps_venc_me0: power-controller@8018 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x8018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me0"; + power-domains = <&ps_venc_dma>; + }; + + ps_venc_me1: power-controller@8020 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x8020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me1"; + power-domains = <&ps_venc_me0>; + }; + + ps_disp_cpu: power-controller@10000 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x10000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp_cpu"; + power-domains = <&ps_disp_fe>; + apple,min-state = <4>; + }; +}; + +&pmgr_mini { + + ps_debug_gated: power-controller@0 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "debug_gated"; + apple,always-on; + }; + + ps_nub_spmi0: power-controller@58 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x58 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_spmi0"; + apple,always-on; + }; + + ps_nub_spmi1: power-controller@60 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x60 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_spmi1"; + apple,always-on; + }; + + ps_nub_spmi2: power-controller@68 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x68 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_spmi2"; + apple,always-on; + }; + + ps_nub_spmi_a0: power-controller@70 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x70 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_spmi_a0"; + apple,always-on; + }; + + ps_nub_aon: power-controller@78 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x78 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_aon"; + apple,always-on; + }; + + ps_nub_spi0: power-controller@80 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x80 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_spi0"; + apple,always-on; + }; + + ps_nub_ocla: power-controller@88 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x88 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_ocla"; + apple,always-on; + }; + + ps_nub_gpio: power-controller@90 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x90 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_gpio"; + apple,always-on; + }; + + ps_nub_fabric: power-controller@98 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x98 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_fabric"; + apple,always-on; + }; + + ps_nub_sram: power-controller@a0 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xa0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_sram"; + apple,always-on; + }; + + ps_debug_switch: power-controller@a8 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xa8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "debug_switch"; + apple,always-on; + }; + + ps_atc0_usb_aon: power-controller@b0 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xb0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_usb_aon"; + }; + + ps_atc1_usb_aon: power-controller@b8 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xb8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_usb_aon"; + }; + + ps_atc0_usb: power-controller@c0 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xc0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_usb"; + power-domains = <&ps_atc0_usb_aon>, <&ps_atc0_common>; + }; + + ps_atc1_usb: power-controller@c8 { + compatible = "apple,t8122-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xc8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_usb"; + power-domains = <&ps_atc1_usb_aon>, <&ps_atc1_common>; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t8122-usbpd-i2c.dtsi b/arch/arm64/boot/dts/apple/t8122-usbpd-i2c.dtsi new file mode 100644 index 000000000000..112c5199cabd --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8122-usbpd-i2c.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple M3 MacBook Pro and iMac (M3, 2023) I2C based USB PD controller nodes + * + * This file contains nodes for t8122 devices using I2C based cd321x USB Type-C + * port controllers. The are used in the M3 MacBook Pro and iMacs but not in the + * M3 Macbook Airs. + * + * target-type: J433, J434, J504 + * + * Copyright The Asahi Linux Contributors + */ + +&i2c0 { + status = "okay"; + + hpm0: usb-pd@38 { + compatible = "apple,cd321x"; + reg = <0x38>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; + + hpm1: usb-pd@3f { + compatible = "apple,cd321x"; + reg = <0x3f>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t8122.dtsi b/arch/arm64/boot/dts/apple/t8122.dtsi new file mode 100644 index 000000000000..c6196225e96e --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8122.dtsi @@ -0,0 +1,444 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T8122 "M3" SoC + * + * Other names: H15G + * + * Copyright The Asahi Linux Contributors + */ + +#include +#include +#include +#include +#include +#include + +/ { + compatible = "apple,t8122", "apple,arm-platform"; + + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu_e0>; + }; + core1 { + cpu = <&cpu_e1>; + }; + core2 { + cpu = <&cpu_e2>; + }; + core3 { + cpu = <&cpu_e3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu_p0>; + }; + core1 { + cpu = <&cpu_p1>; + }; + core2 { + cpu = <&cpu_p2>; + }; + core3 { + cpu = <&cpu_p3>; + }; + }; + }; + + cpu_e0: cpu@0 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + }; + + cpu_e1: cpu@1 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + }; + + cpu_e2: cpu@2 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x2>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + }; + + cpu_e3: cpu@3 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x3>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + }; + + cpu_p0: cpu@10100 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10100>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p1: cpu@10101 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10101>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p2: cpu@10102 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10102>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p3: cpu@10103 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10103>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + l2_cache_0: l2-cache-0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x400000>; + }; + + l2_cache_1: l2-cache-1 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x1000000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&aic>; + interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; + interrupts = , + , + , + ; + }; + + clkref: clock-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "clkref"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + + ranges; + nonposted-mmio; + /* Required to get >32-bit DMA via DARTs */ + dma-ranges = <0 0 0 0 0xffffffff 0xffffc000>; + + i2c0: i2c@235010000 { + compatible = "apple,t8122-i2c", "apple,t8103-i2c"; + reg = <0x2 0x35010000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + #address-cells = <0x1>; + #size-cells = <0x0>; + power-domains = <&ps_i2c0>; + status = "disabled"; + }; + + i2c1: i2c@235014000 { + compatible = "apple,t8122-i2c", "apple,t8103-i2c"; + reg = <0x2 0x35014000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + #address-cells = <0x1>; + #size-cells = <0x0>; + power-domains = <&ps_i2c1>; + status = "disabled"; + }; + + i2c2: i2c@235018000 { + compatible = "apple,t8122-i2c", "apple,t8103-i2c"; + reg = <0x2 0x35018000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + #address-cells = <0x1>; + #size-cells = <0x0>; + power-domains = <&ps_i2c2>; + status = "disabled"; + }; + + i2c3: i2c@23501c000 { + compatible = "apple,t8122-i2c", "apple,t8103-i2c"; + reg = <0x2 0x3501c000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + #address-cells = <0x1>; + #size-cells = <0x0>; + power-domains = <&ps_i2c3>; + status = "disabled"; + }; + + i2c4: i2c@235020000 { + compatible = "apple,t8122-i2c", "apple,t8103-i2c"; + reg = <0x2 0x35020000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; + #address-cells = <0x1>; + #size-cells = <0x0>; + power-domains = <&ps_i2c4>; + status = "disabled"; + }; + + fpwm1: pwm@2a1044000 { + compatible = "apple,t8122-fpwm", "apple,s5l-fpwm"; + reg = <0x2 0xa1044000 0x0 0x4000>; + power-domains = <&ps_fpwm1>; + clocks = <&clkref>; + #pwm-cells = <2>; + status = "disabled"; + }; + + serial0: serial@2a1200000 { + compatible = "apple,s5l-uart"; + reg = <0x2 0xa1200000 0x0 0x1000>; + reg-io-width = <4>; + interrupt-parent = <&aic>; + interrupts = ; + /* + * TODO: figure out the clocking properly, there may + * be a third selectable clock. + */ + clocks = <&clkref>, <&clkref>; + clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart0>; + status = "disabled"; + }; + + aic: interrupt-controller@2d1000000 { + compatible = "apple,t8122-aic3"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x2 0xd1000000 0x0 0x184000>, + <0x2 0xd1040000 0x0 0x4>; + reg-names = "core", "event"; + power-domains = <&ps_aic>; + + affinities { + e-core-pmu-affinity { + apple,fiq-index = ; + cpus = <&cpu_e0 &cpu_e1 &cpu_e2 &cpu_e3>; + }; + + p-core-pmu-affinity { + apple,fiq-index = ; + cpus = <&cpu_p0 &cpu_p1 &cpu_p2 &cpu_p3>; + }; + }; + }; + + pmgr: power-management@2d0700000 { + compatible = "apple,t8122-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0xd0700000 0 0x14000>; + /* child nodes are added in t8122-pmgr.dtsi */ + }; + + pinctrl_ap: pinctrl@2c7100000 { + compatible = "apple,t8122-pinctrl", "apple,t8103-pinctrl"; + reg = <0x2 0xc7100000 0x0 0x100000>; + power-domains = <&ps_gpio>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_ap 0 0 224>; + apple,npins = <224>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + + i2c0_pins: i2c0-pins { + pinmux = , + ; + }; + + i2c1_pins: i2c1-pins { + pinmux = , + ; + }; + + i2c2_pins: i2c2-pins { + pinmux = , + ; + }; + + i2c3_pins: i2c3-pins { + pinmux = , + ; + }; + + i2c4_pins: i2c4-pins { + pinmux = , + ; + }; + + }; + + pinctrl_nub: pinctrl@2e41f0000 { + compatible = "apple,t8122-pinctrl", "apple,t8103-pinctrl"; + reg = <0x2 0xe41f0000 0x0 0x4000>; + power-domains = <&ps_nub_gpio>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_nub 0 0 32>; + apple,npins = <32>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + }; + + pmgr_mini: power-management@2e4280000 { + compatible = "apple,t8122-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0xe4280000 0 0x4000>; + /* child nodes are added in t8122-pmgr.dtsi */ + }; + + wdt: watchdog@2e42b0000 { + compatible = "apple,t8122-wdt", "apple,t8103-wdt"; + reg = <0x2 0xe42b0000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + }; + + pinctrl_smc: pinctrl@2ec820000 { + compatible = "apple,t8122-pinctrl", "apple,t8103-pinctrl"; + reg = <0x2 0xec820000 0x0 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_smc 0 0 18>; + apple,npins = <18>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + }; + + pinctrl_aop: pinctrl@2f4824000 { + compatible = "apple,t8122-pinctrl", "apple,t8103-pinctrl"; + reg = <0x2 0xf4824000 0x0 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_aop 0 0 54>; + apple,npins = <54>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + }; + }; +}; + +#include "t8122-pmgr.dtsi" From 85125c5e9a74054e8f3e3c8910a517e34ad53ae1 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 21 May 2026 15:15:39 -0400 Subject: [PATCH 564/665] ARM: dts: imx: add (power|vdd)-supply for related node Add required power-supply and vdd-supply properties to fix below CHECK_DTB warnings: arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dtb: panel (edt,etm0700g0dh6): 'power-supply' is a required property Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts | 9 +++++++++ arch/arm/boot/dts/nxp/imx/imx53-sk-imx53-atm0700d4.dtsi | 1 + arch/arm/boot/dts/nxp/imx/imx53-sk-imx53.dts | 7 +++++++ arch/arm/boot/dts/nxp/imx/imx6q-novena.dts | 1 + 4 files changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts b/arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts index 6210673f93be..2acbc86cabb3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts @@ -84,6 +84,7 @@ panel { pinctrl-0 = <&pinctrl_display_gpio>; pinctrl-names = "default"; enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; + power-supply = <®_3p2v>; port { panel_in: endpoint { @@ -98,6 +99,13 @@ beeper { gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; }; + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_usbh1_vbus: regulator-usbh1-vbus { compatible = "regulator-fixed"; regulator-name = "vbus"; @@ -259,6 +267,7 @@ eeprom@50 { dac@60 { compatible = "microchip,mcp4725"; reg = <0x60>; + vdd-supply = <®_3v3>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-sk-imx53-atm0700d4.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-sk-imx53-atm0700d4.dtsi index e395004e80e6..34cb0c344ff6 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-sk-imx53-atm0700d4.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx53-sk-imx53-atm0700d4.dtsi @@ -10,6 +10,7 @@ / { panel: panel-rgb { compatible = "powertip,ph800480t013-idf02"; + power-supply = <®_5v>; port { panel_rgb_in: endpoint { diff --git a/arch/arm/boot/dts/nxp/imx/imx53-sk-imx53.dts b/arch/arm/boot/dts/nxp/imx/imx53-sk-imx53.dts index 1a00d290092a..ebec88495877 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-sk-imx53.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-sk-imx53.dts @@ -29,6 +29,13 @@ memory@70000000 { reg = <0x70000000 0x20000000>; }; + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + reg_usb1_vbus: regulator-usb-vbus { compatible = "regulator-fixed"; regulator-name = "usb_vbus"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-novena.dts b/arch/arm/boot/dts/nxp/imx/imx6q-novena.dts index 24fc3ff1c70c..cd9a050fa906 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-novena.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-novena.dts @@ -109,6 +109,7 @@ led-heartbeat { panel: panel { compatible = "innolux,n133hse-ea1"; backlight = <&backlight>; + power-supply = <®_lvds_lcd>; }; reg_2p5v: regulator-2p5v { From e1867c85f420271294ccf75d001e1992805b0116 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 21 May 2026 15:15:40 -0400 Subject: [PATCH 565/665] ARM: dts: imx: remove redundant bus-width for video-mux Remove redundant bus-width property according to video-mux.yaml to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6dl-gw51xx.dtb: ipu1_csi0_mux (video-mux): port@4:endpoint: Unevaluated properties are not allowed ('bus-width' was unexpected) from schema $id: http://devicetree.org/schemas/media/video-mux.yaml The bus-width already set at remote endpoint (camera). Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx6dl-gw52xx.dts | 2 -- arch/arm/boot/dts/nxp/imx/imx6dl-gw53xx.dts | 2 -- arch/arm/boot/dts/nxp/imx/imx6dl-gw54xx.dts | 2 -- arch/arm/boot/dts/nxp/imx/imx6q-gw52xx.dts | 2 -- arch/arm/boot/dts/nxp/imx/imx6q-gw53xx.dts | 2 -- arch/arm/boot/dts/nxp/imx/imx6q-gw54xx.dts | 4 ---- arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi | 2 -- arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi | 2 -- arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi | 2 -- arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi | 2 -- 10 files changed, 22 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-gw52xx.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw52xx.dts index 9ea23dd54f3c..62b05fe70cd9 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-gw52xx.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-gw52xx.dts @@ -32,12 +32,10 @@ adv7180_to_ipu1_csi1_mux: endpoint { }; &ipu1_csi1_from_ipu1_csi1_mux { - bus-width = <8>; }; &ipu1_csi1_mux_from_parallel_sensor { remote-endpoint = <&adv7180_to_ipu1_csi1_mux>; - bus-width = <8>; }; &ipu1_csi1 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-gw53xx.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw53xx.dts index 182e8194c249..c1787510d394 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-gw53xx.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-gw53xx.dts @@ -32,12 +32,10 @@ adv7180_to_ipu1_csi1_mux: endpoint { }; &ipu1_csi1_from_ipu1_csi1_mux { - bus-width = <8>; }; &ipu1_csi1_mux_from_parallel_sensor { remote-endpoint = <&adv7180_to_ipu1_csi1_mux>; - bus-width = <8>; }; &ipu1_csi1 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-gw54xx.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw54xx.dts index a106c4e3e329..934b0325e6f5 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-gw54xx.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-gw54xx.dts @@ -32,12 +32,10 @@ adv7180_to_ipu1_csi1_mux: endpoint { }; &ipu1_csi1_from_ipu1_csi1_mux { - bus-width = <8>; }; &ipu1_csi1_mux_from_parallel_sensor { remote-endpoint = <&adv7180_to_ipu1_csi1_mux>; - bus-width = <8>; }; &ipu1_csi1 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-gw52xx.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw52xx.dts index 6e1c493c9c8c..31996ddde117 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-gw52xx.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-gw52xx.dts @@ -32,12 +32,10 @@ adv7180_to_ipu2_csi1_mux: endpoint { }; &ipu2_csi1_from_ipu2_csi1_mux { - bus-width = <8>; }; &ipu2_csi1_mux_from_parallel_sensor { remote-endpoint = <&adv7180_to_ipu2_csi1_mux>; - bus-width = <8>; }; &ipu2_csi1 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-gw53xx.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw53xx.dts index f13df8e9c8c4..f224273fa863 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-gw53xx.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-gw53xx.dts @@ -32,12 +32,10 @@ adv7180_to_ipu2_csi1_mux: endpoint { }; &ipu2_csi1_from_ipu2_csi1_mux { - bus-width = <8>; }; &ipu2_csi1_mux_from_parallel_sensor { remote-endpoint = <&adv7180_to_ipu2_csi1_mux>; - bus-width = <8>; }; &ipu2_csi1 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-gw54xx.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw54xx.dts index d5d46908cf6e..804ee044be52 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-gw54xx.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-gw54xx.dts @@ -90,12 +90,10 @@ tda1997x_to_ipu1_csi0_mux: endpoint { }; &ipu1_csi0_from_ipu1_csi0_mux { - bus-width = <16>; }; &ipu1_csi0_mux_from_parallel_sensor { remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>; - bus-width = <16>; }; &ipu1_csi0 { @@ -104,12 +102,10 @@ &ipu1_csi0 { }; &ipu2_csi1_from_ipu2_csi1_mux { - bus-width = <8>; }; &ipu2_csi1_mux_from_parallel_sensor { remote-endpoint = <&adv7180_to_ipu2_csi1_mux>; - bus-width = <8>; }; &ipu2_csi1 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi index beff5a0f58ab..fb18b87adb44 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi @@ -384,12 +384,10 @@ adv7180_to_ipu1_csi0_mux: endpoint { }; &ipu1_csi0_from_ipu1_csi0_mux { - bus-width = <8>; }; &ipu1_csi0_mux_from_parallel_sensor { remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; - bus-width = <8>; }; &ipu1_csi0 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi index 6136a95b9259..55647c1dacfa 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi @@ -440,12 +440,10 @@ tda1997x_to_ipu1_csi0_mux: endpoint { }; &ipu1_csi0_from_ipu1_csi0_mux { - bus-width = <16>; }; &ipu1_csi0_mux_from_parallel_sensor { remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>; - bus-width = <16>; }; &ipu1_csi0 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi index 552114a69f5b..bdbcad5e35d8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi @@ -397,12 +397,10 @@ adv7180_to_ipu1_csi0_mux: endpoint { }; &ipu1_csi0_from_ipu1_csi0_mux { - bus-width = <8>; }; &ipu1_csi0_mux_from_parallel_sensor { remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; - bus-width = <8>; }; &ipu1_csi0 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi index b9dde0af3b99..40d8887cb8bc 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi @@ -245,12 +245,10 @@ accelerometer@1c { }; &ipu1_csi0_from_ipu1_csi0_mux { - bus-width = <8>; }; &ipu1_csi0_mux_from_parallel_sensor { remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; - bus-width = <8>; }; &ipu1_csi0 { From 202f97ae137bc6e08d2ed685e361c413edc8452a Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 21 May 2026 15:15:41 -0400 Subject: [PATCH 566/665] ARM: dts: imx: Add bus-type for ov5642/ov5640 Add bus-type (MEDIA_BUS_TYPE_PARALLEL) for ov5642/ov5640. i.MX53 and i.MX6UL only supports parallel csi interface. Fix below CHECK_DTBS warnings: arm/boot/dts/nxp/imx/imx53-smd.dtb: ov5642@3c (ovti,ov5642): port:endpoint: 'bus-type' is a required property Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx53-smd.dts | 2 ++ arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi | 1 + 2 files changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx53-smd.dts b/arch/arm/boot/dts/nxp/imx/imx53-smd.dts index 386371c816f4..c4255da157a3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-smd.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-smd.dts @@ -5,6 +5,7 @@ /dts-v1/; #include +#include #include "imx53.dtsi" / { @@ -296,6 +297,7 @@ camera: ov5642@3c { port { ov5642_to_ipu_csi0: endpoint { remote-endpoint = <&ipu_csi0_from_parallel_sensor>; + bus-type = ; bus-width = <8>; hsync-active = <1>; vsync-active = <1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi index 3d147b160ecf..32afe4130e21 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi @@ -217,6 +217,7 @@ camera@3c { port { ov5640_to_parallel: endpoint { remote-endpoint = <¶llel_from_ov5640>; + bus-type = ; bus-width = <8>; data-shift = <2>; /* lines 9:2 are used */ hsync-active = <0>; From 92c200493e1b70faf810b683fc7046d3b1738b15 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 21 May 2026 15:15:42 -0400 Subject: [PATCH 567/665] ARM: dts: imx6qdl-tx6: remove undocumented karo,imx6qdl-tx6-sgtl5000 and keep only simple-audio-card Remove the undocumented and unused compatible karo,imx6qdl-tx6-sgtl5000 and retain only the generic simple-audio-card sound configuration. The karo,imx6qdl-tx6-sgtl5000 compatible is not documented and is not referenced by any in-kernel driver. The audio setup is already fully described using simple-audio-card, which is the standard and supported binding for this hardware configuration. No known users (such as uboot) rely on karo,imx6qdl-tx6-sgtl5000. Fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6dl-tx6dl-comtft.dtb: /sound: failed to match any schema with compatible: ['karo,imx6qdl-tx6-sgtl5000', 'simple-audio-card'] Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi index d29adfef5fdb..18c29f46dac6 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi @@ -148,8 +148,7 @@ reg_usbotg_vbus: regulator-usbotg-vbus { }; sound { - compatible = "karo,imx6qdl-tx6-sgtl5000", - "simple-audio-card"; + compatible = "simple-audio-card"; simple-audio-card,name = "imx6qdl-tx6-sgtl5000-audio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_audmux>; From 256807f42282e4d7d672784c4eacf6ca768920b4 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 21 May 2026 15:15:43 -0400 Subject: [PATCH 568/665] ARM: dts: imx: replace undocumented compatible string edt,edt-ft5x06 with edt,edt-ft5206 The edt,edt-ft5x06 compatible is not referenced in drivers/input/touchscreen/edt-ft5x06.c and is not documented. There is no publicly available datasheet or binding information that distinguishes edt-ft5206/ft5306/ft5406 variants and the driver treats these FT5x06-family controllers with the same configuration model. So switch to the lowest common and documented baseline compatible edt,edt-ft5206. Fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dtb: /soc/bus@60000000/i2c@63fc8000/touchscreen@38: failed to match any schema with compatible: ['edt,edt-ft5x06'] ABI impact consideration: Not affect Linux kernel. The I2C subsystem uses a legacy fallback mechanism where it strips the vendor prefix from the compatible string to derive the client name, resulting in edt-ft5x06 { .name = "edt-ft5x06", .driver_data = (long)&edt_ft5x06_data }, After this, the driver was actively binding to these devices based on the compatible string. Known user (U-Boot) does not parse or use edt,edt-ft* touchscreen compatibles. Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx53-tx53-x03x.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx6q-var-dt6customboard.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-pico.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6ul-pico-hobbit.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx6ul-pico-pi.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx7d-pico-dwarf.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts | 2 +- 14 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts b/arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts index 2acbc86cabb3..aa1c7e5012c6 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts @@ -248,7 +248,7 @@ &i2c1 { status = "okay"; touchscreen@38 { - compatible = "edt,edt-ft5x06"; + compatible = "edt,edt-ft5206"; reg = <0x38>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_edt_ft5x06>; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-tx53-x03x.dts b/arch/arm/boot/dts/nxp/imx/imx53-tx53-x03x.dts index 872cf7e16f20..6a1063c455f0 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-tx53-x03x.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-tx53-x03x.dts @@ -201,7 +201,7 @@ sgtl5000: codec@a { }; polytouch: edt-ft5x06@38 { - compatible = "edt,edt-ft5x06"; + compatible = "edt,edt-ft5206"; reg = <0x38>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_edt_ft5x06_1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-var-dt6customboard.dts b/arch/arm/boot/dts/nxp/imx/imx6q-var-dt6customboard.dts index 0225a621ec7a..ccf6a048c918 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-var-dt6customboard.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-var-dt6customboard.dts @@ -169,7 +169,7 @@ &i2c3 { status = "okay"; touchscreen@38 { - compatible = "edt,edt-ft5x06"; + compatible = "edt,edt-ft5206"; reg = <0x38>; interrupt-parent = <&gpio1>; interrupts = <4 IRQ_TYPE_EDGE_FALLING>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi index 610b2a72fe82..cebfd622df68 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi @@ -256,7 +256,7 @@ touchscreen@4 { }; touchscreen@38 { - compatible = "edt,edt-ft5x06"; + compatible = "edt,edt-ft5206"; reg = <0x38>; interrupt-parent = <&gpio1>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi index ef0c26688446..f8a7218b13ef 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi @@ -405,7 +405,7 @@ touchscreen@4 { }; touchscreen@38 { - compatible = "edt,edt-ft5x06"; + compatible = "edt,edt-ft5206"; reg = <0x38>; interrupt-parent = <&gpio1>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi index 03fe053880ca..fb1c923c46bc 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi @@ -326,7 +326,7 @@ touchscreen@4 { }; touchscreen@38 { - compatible = "edt,edt-ft5x06"; + compatible = "edt,edt-ft5206"; reg = <0x38>; interrupt-parent = <&gpio1>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi index 6a353a99e13d..9fe52e0ca7aa 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi @@ -333,7 +333,7 @@ touchscreen@4 { }; touchscreen@38 { - compatible = "edt,edt-ft5x06"; + compatible = "edt,edt-ft5206"; reg = <0x38>; interrupt-parent = <&gpio1>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-pico.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-pico.dtsi index c39a9ebdaba1..ca4cb986efbc 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-pico.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-pico.dtsi @@ -217,7 +217,7 @@ &i2c2 { status = "okay"; touchscreen@38 { - compatible = "edt,edt-ft5x06"; + compatible = "edt,edt-ft5206"; reg = <0x38>; interrupt-parent = <&gpio5>; interrupts = <31 IRQ_TYPE_EDGE_FALLING>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi index 18c29f46dac6..83c4bf9f9438 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi @@ -296,7 +296,7 @@ sgtl5000: sgtl5000@a { }; polytouch: edt-ft5x06@38 { - compatible = "edt,edt-ft5x06"; + compatible = "edt,edt-ft5206"; reg = <0x38>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_edt_ft5x06>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-pico-hobbit.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-pico-hobbit.dts index bf7dbb4f1f3e..e99ba04216b8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-pico-hobbit.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-pico-hobbit.dts @@ -62,7 +62,7 @@ &i2c3 { status = "okay"; polytouch: touchscreen@38 { - compatible = "edt,edt-ft5x06"; + compatible = "edt,edt-ft5206"; reg = <0x38>; interrupt-parent = <&gpio1>; interrupts = <29 IRQ_TYPE_EDGE_FALLING>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-pico-pi.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-pico-pi.dts index 6cfc943a8fa3..f79090fb2e6e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-pico-pi.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-pico-pi.dts @@ -65,7 +65,7 @@ &i2c3 { status = "okay"; polytouch: touchscreen@38 { - compatible = "edt,edt-ft5x06"; + compatible = "edt,edt-ft5206"; reg = <0x38>; interrupt-parent = <&gpio1>; interrupts = <29 IRQ_TYPE_EDGE_FALLING>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi index dc53f9286ffe..b87f5d6a2d88 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi @@ -321,7 +321,7 @@ sgtl5000: codec@a { }; polytouch: polytouch@38 { - compatible = "edt,edt-ft5x06"; + compatible = "edt,edt-ft5206"; reg = <0x38>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_edt_ft5x06>; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-pico-dwarf.dts b/arch/arm/boot/dts/nxp/imx/imx7d-pico-dwarf.dts index 347dd0fe4f82..fca8aab9d850 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d-pico-dwarf.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-pico-dwarf.dts @@ -70,7 +70,7 @@ pca9554: io-expander@25 { }; touchscreen@38 { - compatible = "edt,edt-ft5x06"; + compatible = "edt,edt-ft5206"; reg = <0x38>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_touchscreen>; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts b/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts index 62221131336f..673bbe49de52 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts @@ -49,7 +49,7 @@ sgtl5000: codec@a { &i2c4 { polytouch: touchscreen@38 { - compatible = "edt,edt-ft5x06"; + compatible = "edt,edt-ft5206"; reg = <0x38>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_touchscreen>; From e6532261b1514d99cfa07db05c1fafaf32ffbfb2 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 21 May 2026 15:15:44 -0400 Subject: [PATCH 569/665] ARM: dts: imx6-display5: replace marvell,88E1510 with ethernet-phy-ieee802.3-c22 Replace the vendor-specific PHY compatible string with the generic ethernet-phy-ieee802.3-c22 compatible. The marvell,88E1510 compatible is listed in whitelist_phys[] and is never matched against a PHY driver. PHY devices are expected to use the generic ethernet-phy-ieee802.3-c22 compatible unless a specific MDIO driver match is required. The 88E1510 is compatible with Clause 22 PHY devices, so use the generic compatible string instead. Fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6q-display5-tianma-tm070-1280x768.dtb: /soc/bus@2100000/ethernet@2188000/mdio/ethernet-phy@0: failed to match any schema with compatible: ['marvell,88E1510'] Known other user (uboot) did not use marvell,88E1510. Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx6q-display5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-display5.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-display5.dtsi index 4e448b4810f2..21e8bbdab4e6 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-display5.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6q-display5.dtsi @@ -208,7 +208,7 @@ mdio { #address-cells = <1>; #size-cells = <0>; ethernet_phy0: ethernet-phy@0 { - compatible = "marvell,88E1510"; + compatible = "ethernet-phy-ieee802.3-c22"; device_type = "ethernet-phy"; /* Set LED0 control: */ /* On - Link, Blink - Activity, Off - No Link */ From 1e2aa1b07bc1c5dd89ec0d14d9fe6f32f9b136c4 Mon Sep 17 00:00:00 2001 From: Lech Perczak Date: Wed, 27 May 2026 12:19:12 +0200 Subject: [PATCH 570/665] ARM: dts: imx7d-pico-pi: add OV5645 camera support Add OV5645 camera device node and enable relevant components in the video capture data path, so output stream can be captured, and the camera itself can be controlled over I2C bus. This is roughly based on descriptions found in downstream kernel tree [1], adapted to match upstream bindings. Link: https://github.com/technexion-android/kernel_imx/blob/ce8fd74abf518dac0a09e8dcb37f3496f6375124/arch/arm/boot/dts/imx7d-pico.dtsi#L874 [1] Signed-off-by: Lech Perczak Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts | 68 ++++++++++++++++++++- 1 file changed, 67 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts b/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts index 673bbe49de52..7a0e4dc5450e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts @@ -19,6 +19,13 @@ led { }; }; + reg_1p5v: regulator-1p5v { + compatible = "regulator-fixed"; + regulator-name = "1P5V"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + }; + sound { compatible = "simple-audio-card"; simple-audio-card,name = "imx7-sgtl5000"; @@ -59,6 +66,33 @@ polytouch: touchscreen@38 { touchscreen-size-x = <800>; touchscreen-size-y = <480>; }; + + camera@3c { + compatible = "ovti,ov5645"; + reg = <0x3c>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_camera>; + + clocks = <&clks IMX7D_CLKO1_ROOT_DIV>; + assigned-clocks = <&clks IMX7D_CLKO1_ROOT_DIV>; + assigned-clock-rates = <24000000>; + + enable-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + + vdda-supply = <®_2p5v>; + vdddo-supply = <®_vref_1v8>; + vddd-supply = <®_1p5v>; + + port { + ov5645_to_mipi_csi2: endpoint { + remote-endpoint = <&mipi_csi2_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; }; &usdhc1 { @@ -93,5 +127,37 @@ MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 >; }; - +}; + +&iomuxc_lpsr { + pinctrl_camera: cameragrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x15 + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x15 + MX7D_PAD_LPSR_GPIO1_IO02__CCM_CLKO1 0x7d + >; + }; +}; + +&csi { + status = "okay"; +}; + +&mipi_csi { + status = "okay"; + + ports { + port@0 { + reg = <0>; + + mipi_csi2_in: endpoint { + remote-endpoint = <&ov5645_to_mipi_csi2>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&video_mux { + status = "okay"; }; From 8c45bf9ae4efcecd2f91bc3e6f567280721fd0fd Mon Sep 17 00:00:00 2001 From: Ronald Claveau Date: Thu, 26 Mar 2026 10:59:17 +0100 Subject: [PATCH 571/665] arm64: dts: amlogic: t7: khadas-vim4: Add power regulators Add voltage regulator nodes describing the VIM4 power tree, required by peripheral nodes such as the SD card controller. Reviewed-by: Neil Armstrong Signed-off-by: Ronald Claveau Link: https://patch.msgid.link/20260326-add-emmc-t7-vim4-v5-6-d3f182b48e9d@aliel.fr [narmstrong: squashed "Remove invalid property fix" from Ronald] Signed-off-by: Neil Armstrong --- .../amlogic/amlogic-t7-a311d2-khadas-vim4.dts | 89 +++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts index f4c953034be3..003b3bcdaf2b 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts @@ -6,6 +6,8 @@ /dts-v1/; #include "amlogic-t7.dtsi" +#include +#include / { model = "Khadas VIM4"; @@ -47,6 +49,93 @@ xtal: xtal-clk { #clock-cells = <0>; }; + dc_in: regulator-dc-in { + compatible = "regulator-fixed"; + regulator-name = "DC_IN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + sd_3v3: regulator-sdcard-3v3 { + compatible = "regulator-fixed"; + regulator-name = "SD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vddao_3v3>; + gpio = <&gpio GPIOD_11 GPIO_ACTIVE_LOW>; + regulator-boot-on; + regulator-always-on; + }; + + vcc5v: regulator-vcc-5v { + compatible = "regulator-fixed"; + regulator-name = "VCC5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_in>; + + gpio = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vcc5v0_usb: regulator-vcc-usb { + compatible = "regulator-fixed"; + regulator-name = "VCC5V0_USB"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v>; + + gpio = <&gpio GPIOY_5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vddao_1v8: regulator-vddao-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + vddao_3v3: regulator-vddao-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_in>; + regulator-always-on; + }; + + vddio_1v8: regulator-vddio-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddio_3v3>; + regulator-always-on; + }; + + vddio_3v3: regulator-vddio-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + vddio_c: regulator-gpio-c { + compatible = "regulator-gpio"; + regulator-name = "VDDIO_C"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vddio_3v3>; + gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>; + states = <1800000 1 + 3300000 0>; + }; }; &uart_a { From 4badf8d60daf72964807f4d8d89ae7f41868d901 Mon Sep 17 00:00:00 2001 From: Nick Xie Date: Wed, 25 Mar 2026 15:06:17 +0800 Subject: [PATCH 572/665] arm64: dts: amlogic: meson-s4: add internal SARADC controller Add the SARADC (Successive Approximation Register ADC) controller node to the Meson S4 SoC dtsi. It uses the S4-specific compatible string with a fallback to the G12A generation, as there are no known hardware differences. Reviewed-by: Martin Blumenstingl Signed-off-by: Nick Xie Link: https://patch.msgid.link/20260325070618.81955-4-nick@khadas.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi index 4a3e9ad82d28..936a5c1353d1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi @@ -77,6 +77,20 @@ pwrc: power-controller { }; }; + saradc: adc@fe026000 { + compatible = "amlogic,meson-s4-saradc", + "amlogic,meson-g12a-saradc"; + reg = <0x0 0xfe026000 0x0 0x48>; + #io-channel-cells = <1>; + interrupts = ; + clocks = <&xtal>, + <&clkc_periphs CLKID_SAR_ADC>, + <&clkc_periphs CLKID_SARADC>, + <&clkc_periphs CLKID_SARADC_SEL>; + clock-names = "clkin", "core", "adc_clk", "adc_sel"; + status = "disabled"; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; From def2d2379668d5e80a41d6d2fb0972f8480d9c2f Mon Sep 17 00:00:00 2001 From: Nick Xie Date: Wed, 25 Mar 2026 15:06:18 +0800 Subject: [PATCH 573/665] arm64: dts: amlogic: meson-s4-s905y4-khadas-vim1s: add Function key support Enable the SARADC controller and add the adc-keys node to support the Function key found on the Khadas VIM1S board. Reviewed-by: Martin Blumenstingl Signed-off-by: Nick Xie Link: https://patch.msgid.link/20260325070618.81955-5-nick@khadas.com Signed-off-by: Neil Armstrong --- .../amlogic/meson-s4-s905y4-khadas-vim1s.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts b/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts index 664d64a267f2..792ab45c4c94 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts +++ b/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts @@ -40,6 +40,20 @@ secmon_reserved: secmon@5000000 { }; }; + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1710000>; + poll-interval = <100>; + + button-function { + label = "Function"; + linux,code = ; + press-threshold-microvolt = <10000>; + }; + }; + emmc_pwrseq: emmc-pwrseq { compatible = "mmc-pwrseq-emmc"; reset-gpios = <&gpio GPIOB_9 GPIO_ACTIVE_LOW>; @@ -278,6 +292,11 @@ brcmf: wifi@1 { }; }; +&saradc { + status = "okay"; + vref-supply = <&vddio_ao1v8>; +}; + &spicc0 { status = "okay"; pinctrl-names = "default"; From 42379e7ee9cc648f3e5a281a3e3849c326daccc0 Mon Sep 17 00:00:00 2001 From: Nick Xie Date: Fri, 27 Mar 2026 17:30:14 +0800 Subject: [PATCH 574/665] arm64: dts: amlogic: meson-s4: add VRTC node Add the Virtual RTC (VRTC) controller node to the Meson S4 SoC dtsi. Signed-off-by: Nick Xie Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260327093016.722095-2-nick@khadas.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi index 936a5c1353d1..2a6fbd530836 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi @@ -59,6 +59,11 @@ psci { method = "smc"; }; + vrtc: rtc@fe010288 { + compatible = "amlogic,meson-vrtc"; + reg = <0x0 0xfe010288 0x0 0x4>; + }; + xtal: xtal-clk { compatible = "fixed-clock"; clock-frequency = <24000000>; From 2e63b271fb62c7a2e9c626bda8d62130abb0e1c9 Mon Sep 17 00:00:00 2001 From: Nick Xie Date: Fri, 27 Mar 2026 17:30:15 +0800 Subject: [PATCH 575/665] arm64: dts: amlogic: meson-s4-s905y4-khadas-vim1s: enable HYM8563 RTC The Khadas VIM1S board has an on-board Haoyu Micro HYM8563 Real Time Clock (RTC) connected to the I2C1 bus. Enable the I2C1 controller and add the RTC child node to support hardware clock persistence. Signed-off-by: Nick Xie Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260327093016.722095-3-nick@khadas.com Signed-off-by: Neil Armstrong --- .../dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts b/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts index 792ab45c4c94..7314e0ab81da 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts +++ b/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts @@ -20,6 +20,8 @@ aliases { mmc0 = &emmc; /* eMMC */ mmc1 = &sd; /* SD card */ mmc2 = &sdio; /* SDIO */ + rtc0 = &rtc; + rtc1 = &vrtc; serial0 = &uart_b; }; @@ -223,6 +225,19 @@ ðmac { phy-mode = "rmii"; }; +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins2>; + clock-frequency = <100000>; + + rtc: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + }; +}; + &ir { status = "okay"; pinctrl-0 = <&remote_pins>; From 217a751eec57827c28cbe5f0f7e5bf95cf98d240 Mon Sep 17 00:00:00 2001 From: Nick Xie Date: Fri, 27 Mar 2026 17:30:16 +0800 Subject: [PATCH 576/665] arm64: dts: amlogic: meson-s4-s905y4-khadas-vim1s: use rc-khadas keymap The Khadas VIM1S board has an onboard IR receiver. Configure the default keymap to "rc-khadas" to support the official Khadas IR remote control. Signed-off-by: Nick Xie Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260327093016.722095-4-nick@khadas.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts b/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts index 7314e0ab81da..99d5df71b9cd 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts +++ b/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts @@ -242,6 +242,7 @@ &ir { status = "okay"; pinctrl-0 = <&remote_pins>; pinctrl-names = "default"; + linux,rc-map-name = "rc-khadas"; }; &pwm_ef { From 68de99550e9ee79f13c4cddb4c482eeb684e9249 Mon Sep 17 00:00:00 2001 From: Jian Hu Date: Thu, 26 Mar 2026 17:26:45 +0800 Subject: [PATCH 577/665] arm64: dts: amlogic: t7: Add clock controller nodes Add the required clock controller nodes for Amlogic T7 SoC family: - SCMI clock controller - PLL clock controller - Peripheral clock controller Signed-off-by: Ronald Claveau Signed-off-by: Jian Hu Link: https://patch.msgid.link/20260326092645.1053261-4-jian.hu@amlogic.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 125 ++++++++++++++++++++ 1 file changed, 125 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi index a54fa2bd5c78..1a00a65db0c6 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi @@ -6,6 +6,9 @@ #include #include #include "amlogic-t7-reset.h" +#include +#include +#include / { interrupt-parent = <&gic>; @@ -201,6 +204,34 @@ pwrc: power-controller { }; }; + sram@f7042000 { + compatible = "mmio-sram"; + reg = <0x0 0xf7042000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0xf7042000 0x100>; + + scmi_shmem: sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x100>; + }; + }; + + firmware { + scmi: scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0x820000c1>; + shmem = <&scmi_shmem>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -226,6 +257,42 @@ apb4: bus@fe000000 { #size-cells = <2>; ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; + clkc_periphs: clock-controller@0 { + compatible = "amlogic,t7-peripherals-clkc"; + reg = <0x0 0x0 0x0 0x1c8>; + #clock-cells = <1>; + clocks = <&xtal>, + <&scmi_clk CLKID_SYS_CLK>, + <&scmi_clk CLKID_FIXED_PLL>, + <&scmi_clk CLKID_FCLK_DIV2>, + <&scmi_clk CLKID_FCLK_DIV2P5>, + <&scmi_clk CLKID_FCLK_DIV3>, + <&scmi_clk CLKID_FCLK_DIV4>, + <&scmi_clk CLKID_FCLK_DIV5>, + <&scmi_clk CLKID_FCLK_DIV7>, + <&hifi CLKID_HIFI_PLL>, + <&gp0 CLKID_GP0_PLL>, + <&gp1 CLKID_GP1_PLL>, + <&mpll CLKID_MPLL1>, + <&mpll CLKID_MPLL2>, + <&mpll CLKID_MPLL3>; + clock-names = "xtal", + "sys", + "fix", + "fdiv2", + "fdiv2p5", + "fdiv3", + "fdiv4", + "fdiv5", + "fdiv7", + "hifi", + "gp0", + "gp1", + "mpll1", + "mpll2", + "mpll3"; + }; + reset: reset-controller@2000 { compatible = "amlogic,t7-reset"; reg = <0x0 0x2000 0x0 0x98>; @@ -513,6 +580,64 @@ uart_a: serial@78000 { status = "disabled"; }; + gp0: clock-controller@8080 { + compatible = "amlogic,t7-gp0-pll"; + reg = <0x0 0x8080 0x0 0x20>; + clocks = <&scmi_clk CLKID_TOP_PLL_OSC>; + clock-names = "in0"; + #clock-cells = <1>; + }; + + gp1: clock-controller@80c0 { + compatible = "amlogic,t7-gp1-pll"; + reg = <0x0 0x80c0 0x0 0x14>; + clocks = <&scmi_clk CLKID_TOP_PLL_OSC>; + clock-names = "in0"; + #clock-cells = <1>; + }; + + hifi: clock-controller@8100 { + compatible = "amlogic,t7-hifi-pll"; + reg = <0x0 0x8100 0x0 0x20>; + clocks = <&scmi_clk CLKID_TOP_PLL_OSC>; + clock-names = "in0"; + #clock-cells = <1>; + }; + + pcie: clock-controller@8140 { + compatible = "amlogic,t7-pcie-pll"; + reg = <0x0 0x8140 0x0 0x1c>; + clocks = <&scmi_clk CLKID_PCIE_OSC>; + clock-names = "in0"; + #clock-cells = <1>; + }; + + mpll: clock-controller@8180 { + compatible = "amlogic,t7-mpll"; + reg = <0x0 0x8180 0x0 0x28>; + clocks = <&scmi_clk CLKID_FIXED_PLL_DCO>; + clock-names = "in0"; + #clock-cells = <1>; + }; + + hdmi: clock-controller@81c0 { + compatible = "amlogic,t7-hdmi-pll"; + reg = <0x0 0x81c0 0x0 0x20>; + clocks = <&scmi_clk CLKID_HDMI_PLL_OSC>; + clock-names = "in0"; + #clock-cells = <1>; + }; + + mclk: clock-controller@8300 { + compatible = "amlogic,t7-mclk-pll"; + reg = <0x0 0x8300 0x0 0x18>; + clocks = <&scmi_clk CLKID_MCLK_PLL_OSC>, + <&xtal>, + <&scmi_clk CLKID_FCLK_50M>; + clock-names = "in0", "in1", "in2"; + #clock-cells = <1>; + }; + sec_ao: ao-secure@10220 { compatible = "amlogic,t7-ao-secure", "amlogic,meson-gx-ao-secure", From bd3454d5087d63dd68145d00bc3034b99e087782 Mon Sep 17 00:00:00 2001 From: Ronald Claveau Date: Thu, 26 Mar 2026 10:59:14 +0100 Subject: [PATCH 578/665] arm64: dts: amlogic: t7: Add MMC controller nodes Add device tree nodes for the three MMC controllers available on the Amlogic T7 SoC, using amlogic,meson-axg-mmc as fallback compatible. All nodes are disabled by default and should be enabled in the board-specific DTS file. Signed-off-by: Ronald Claveau Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260326-add-emmc-t7-vim4-v5-3-d3f182b48e9d@aliel.fr Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 39 +++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi index 1a00a65db0c6..d45f360e3d67 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi @@ -645,6 +645,45 @@ sec_ao: ao-secure@10220 { reg = <0x0 0x10220 0x0 0x140>; amlogic,has-chip-id; }; + + sd_emmc_a: mmc@88000 { + compatible = "amlogic,t7-mmc", "amlogic,meson-axg-mmc"; + reg = <0x0 0x88000 0x0 0x800>; + interrupts = ; + clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_A>, + <&clkc_periphs CLKID_SD_EMMC_A>, + <&scmi_clk CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_A_SEL>; + assigned-clock-parents = <&xtal>; + status = "disabled"; + }; + + sd_emmc_b: mmc@8a000 { + compatible = "amlogic,t7-mmc", "amlogic,meson-axg-mmc"; + reg = <0x0 0x8a000 0x0 0x800>; + interrupts = ; + clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_B>, + <&clkc_periphs CLKID_SD_EMMC_B>, + <&scmi_clk CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_B_SEL>; + assigned-clock-parents = <&xtal>; + status = "disabled"; + }; + + sd_emmc_c: mmc@8c000 { + compatible = "amlogic,t7-mmc", "amlogic,meson-axg-mmc"; + reg = <0x0 0x8c000 0x0 0x800>; + interrupts = ; + clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_C>, + <&clkc_periphs CLKID_SD_EMMC_C>, + <&scmi_clk CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_C_SEL>; + assigned-clock-parents = <&xtal>; + status = "disabled"; + }; }; }; From 97f08cef69118bff9b7901bb1c804e7e326b31bf Mon Sep 17 00:00:00 2001 From: Ronald Claveau Date: Thu, 26 Mar 2026 10:59:16 +0100 Subject: [PATCH 579/665] arm64: dts: amlogic: t7: Add PWM controller nodes Add device tree nodes for the seven PWM controllers available on the Amlogic T7 SoC, using amlogic,meson-s4-pwm as fallback compatible. All nodes are disabled by default and should be enabled in the board-specific DTS file. Co-developed-by: Nick Xie Signed-off-by: Nick Xie Reviewed-by: Neil Armstrong Signed-off-by: Ronald Claveau Link: https://patch.msgid.link/20260326-add-emmc-t7-vim4-v5-5-d3f182b48e9d@aliel.fr Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 63 +++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi index d45f360e3d67..fc23f409fe1d 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi @@ -646,6 +646,69 @@ sec_ao: ao-secure@10220 { amlogic,has-chip-id; }; + pwm_ao_ef: pwm@30000 { + compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm"; + reg = <0x0 0x30000 0x0 0x24>; + clocks = <&clkc_periphs CLKID_PWM_AO_E>, + <&clkc_periphs CLKID_PWM_AO_F>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_ao_gh: pwm@32000 { + compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm"; + reg = <0x0 0x32000 0x0 0x24>; + clocks = <&clkc_periphs CLKID_PWM_AO_G>, + <&clkc_periphs CLKID_PWM_AO_H>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_ab: pwm@58000 { + compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm"; + reg = <0x0 0x58000 0x0 0x24>; + clocks = <&clkc_periphs CLKID_PWM_A>, + <&clkc_periphs CLKID_PWM_B>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_cd: pwm@5a000 { + compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm"; + reg = <0x0 0x5a000 0x0 0x24>; + clocks = <&clkc_periphs CLKID_PWM_C>, + <&clkc_periphs CLKID_PWM_D>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_ef: pwm@5c000 { + compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm"; + reg = <0x0 0x5c000 0x0 0x24>; + clocks = <&clkc_periphs CLKID_PWM_E>, + <&clkc_periphs CLKID_PWM_F>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_ao_ab: pwm@5e000 { + compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm"; + reg = <0x0 0x5e000 0x0 0x24>; + clocks = <&clkc_periphs CLKID_PWM_AO_A>, + <&clkc_periphs CLKID_PWM_AO_B>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_ao_cd: pwm@60000 { + compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm"; + reg = <0x0 0x60000 0x0 0x24>; + clocks = <&clkc_periphs CLKID_PWM_AO_C>, + <&clkc_periphs CLKID_PWM_AO_D>; + #pwm-cells = <3>; + status = "disabled"; + }; + sd_emmc_a: mmc@88000 { compatible = "amlogic,t7-mmc", "amlogic,meson-axg-mmc"; reg = <0x0 0x88000 0x0 0x800>; From 4d2663f85f8dd31eb0b6b02b3cdd2ac0e21b5d51 Mon Sep 17 00:00:00 2001 From: Ronald Claveau Date: Thu, 26 Mar 2026 10:59:18 +0100 Subject: [PATCH 580/665] arm64: dts: amlogic: t7: khadas-vim4: Add SDIO power sequence and WiFi clock Add the SDIO power sequence node using mmc-pwrseq-simple and a 32.768kHz PWM-based clock required by the Wi-Fi module. Reviewed-by: Neil Armstrong Signed-off-by: Ronald Claveau Link: https://patch.msgid.link/20260326-add-emmc-t7-vim4-v5-7-d3f182b48e9d@aliel.fr Signed-off-by: Neil Armstrong --- .../amlogic/amlogic-t7-a311d2-khadas-vim4.dts | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts index 003b3bcdaf2b..994d04f3f5f0 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts @@ -68,6 +68,15 @@ sd_3v3: regulator-sdcard-3v3 { regulator-always-on; }; + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <500>; + power-off-delay-us = <200000>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + vcc5v: regulator-vcc-5v { compatible = "regulator-fixed"; regulator-name = "VCC5V"; @@ -136,6 +145,19 @@ vddio_c: regulator-gpio-c { states = <1800000 1 3300000 0>; }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ab 0 30518 0>; + }; +}; + +&pwm_ab { + status = "okay"; + pinctrl-0 = <&pwm_a_pins>; + pinctrl-names = "default"; }; &uart_a { From 003080cf2c4a3f5a101296ab969bd5d92076b18b Mon Sep 17 00:00:00 2001 From: Ronald Claveau Date: Thu, 26 Mar 2026 10:59:20 +0100 Subject: [PATCH 581/665] arm64: dts: amlogic: t7: khadas-vim4: Add MMC nodes Enable and configure the three MMC controllers for the Khadas VIM4 board: - sd_emmc_a: SDIO interface for the BCM43752 Wi-Fi module - sd_emmc_b: SD card slot - sd_emmc_c: eMMC storage Reviewed-by: Neil Armstrong Signed-off-by: Ronald Claveau Link: https://patch.msgid.link/20260326-add-emmc-t7-vim4-v5-9-d3f182b48e9d@aliel.fr Signed-off-by: Neil Armstrong --- .../amlogic/amlogic-t7-a311d2-khadas-vim4.dts | 88 +++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts index 994d04f3f5f0..69d6118ba57e 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts @@ -15,6 +15,9 @@ / { aliases { serial0 = &uart_a; + mmc0 = &sd_emmc_c; + mmc1 = &sd_emmc_b; + mmc2 = &sd_emmc_a; }; memory@0 { @@ -160,6 +163,91 @@ &pwm_ab { pinctrl-names = "default"; }; +/* SDIO */ +&sd_emmc_a { + status = "okay"; + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + cap-sdio-irq; + max-frequency = <200000000>; + non-removable; + disable-wp; + no-mmc; + no-sd; + + power-domains = <&pwrc PWRC_T7_SDIO_A_ID>; + + keep-power-in-suspend; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddao_1v8>; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm43752-fmac", "brcm,bcm4329-fmac"; + }; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + max-frequency = <200000000>; + disable-wp; + no-sdio; + no-mmc; + + power-domains = <&pwrc PWRC_T7_SDIO_B_ID>; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; + vmmc-supply = <&sd_3v3>; + vqmmc-supply = <&vddio_c>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <200000000>; + disable-wp; + non-removable; + no-sdio; + no-sd; + + power-domains = <&pwrc PWRC_T7_EMMC_ID>; + + vmmc-supply = <&vddio_3v3>; + vqmmc-supply = <&vddio_1v8>; +}; + &uart_a { status = "okay"; clocks = <&xtal>, <&xtal>, <&xtal>; From caaf6ccaec2744aa7ec82f78b05b316d9a8d1857 Mon Sep 17 00:00:00 2001 From: Ronald Claveau Date: Tue, 31 Mar 2026 16:24:05 +0200 Subject: [PATCH 582/665] arm64: dts: amlogic: t7: Fix missing required reset property CHECK_DTBS shows missing reset required property in T7 DTBS. A new CHECK_DTBS with this patch does not show this anymore. Signed-off-by: Ronald Claveau Link: https://patch.msgid.link/20260331-fix-aml-t7-null-reset-v1-2-eb95b625234c@aliel.fr Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi index fc23f409fe1d..62f6b9baad28 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi @@ -717,6 +717,7 @@ sd_emmc_a: mmc@88000 { <&clkc_periphs CLKID_SD_EMMC_A>, <&scmi_clk CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_A>; assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_A_SEL>; assigned-clock-parents = <&xtal>; status = "disabled"; @@ -730,6 +731,7 @@ sd_emmc_b: mmc@8a000 { <&clkc_periphs CLKID_SD_EMMC_B>, <&scmi_clk CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_B>; assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_B_SEL>; assigned-clock-parents = <&xtal>; status = "disabled"; @@ -743,6 +745,7 @@ sd_emmc_c: mmc@8c000 { <&clkc_periphs CLKID_SD_EMMC_C>, <&scmi_clk CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_C>; assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_C_SEL>; assigned-clock-parents = <&xtal>; status = "disabled"; From a63d58bd2ddcdcf592167b5de836de6674698c1f Mon Sep 17 00:00:00 2001 From: Ronald Claveau Date: Wed, 13 May 2026 12:43:54 +0200 Subject: [PATCH 583/665] arm64: dts: amlogic: t7: khadas-vim4: reorder root node Move the xtal-clk node to restore alphabetical ordering. Signed-off-by: Ronald Claveau Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260513-add-kvim4-sysled-v2-2-3ec9779e8875@aliel.fr Signed-off-by: Neil Armstrong --- .../dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts index 69d6118ba57e..fd1b983354a0 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts @@ -45,13 +45,6 @@ secmon_reserved_bl32: secmon@5300000 { }; }; - xtal: xtal-clk { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xtal"; - #clock-cells = <0>; - }; - dc_in: regulator-dc-in { compatible = "regulator-fixed"; regulator-name = "DC_IN"; @@ -155,6 +148,13 @@ wifi32k: wifi32k { clock-frequency = <32768>; pwms = <&pwm_ab 0 30518 0>; }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; }; &pwm_ab { From 61ba02ca4758e7978dc8caf5e1fff3a9f5921a60 Mon Sep 17 00:00:00 2001 From: Ronald Claveau Date: Wed, 13 May 2026 12:43:55 +0200 Subject: [PATCH 584/665] arm64: dts: amlogic: t7: khadas-vim4: add PWM-driven status LED The VIM4 board exposes a status LED wired to the PWM_AO_C_D output. Enable the pwm_ao_cd controller with its pinmux, and declare a pwm-leds node with a heartbeat trigger. Signed-off-by: Ronald Claveau Link: https://patch.msgid.link/20260513-add-kvim4-sysled-v2-3-3ec9779e8875@aliel.fr Signed-off-by: Neil Armstrong --- .../amlogic/amlogic-t7-a311d2-khadas-vim4.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts index fd1b983354a0..c41525a34b72 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts @@ -53,6 +53,16 @@ dc_in: regulator-dc-in { regulator-always-on; }; + pwm-leds { + compatible = "pwm-leds"; + + status { + linux,default-trigger="heartbeat"; + max-brightness = <255>; + pwms = <&pwm_ao_cd 0 30040 0>; + }; + }; + sd_3v3: regulator-sdcard-3v3 { compatible = "regulator-fixed"; regulator-name = "SD_3V3"; @@ -163,6 +173,12 @@ &pwm_ab { pinctrl-names = "default"; }; +&pwm_ao_cd { + status = "okay"; + pinctrl-0 = <&pwm_ao_c_d_pins>; + pinctrl-names = "default"; +}; + /* SDIO */ &sd_emmc_a { status = "okay"; From eec0722a5cac08ba995847c8eb63118cc708560b Mon Sep 17 00:00:00 2001 From: Ronald Claveau Date: Sat, 16 May 2026 19:17:06 +0200 Subject: [PATCH 585/665] arm64: dts: amlogic: t7: Add i2c pinctrl node Add the T7 pinctrl used by the Khadas VIM4 for MCU communication. Reviewed-by: Neil Armstrong Signed-off-by: Ronald Claveau Link: https://patch.msgid.link/20260516-add-mcu-fan-khadas-vim4-v6-6-cccc9b61f465@aliel.fr Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi index 62f6b9baad28..cc371fcd1896 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi @@ -376,6 +376,16 @@ mux { }; }; + i2c0_ao_d_pins: i2c0-ao-d { + mux { + groups = "i2c0_ao_sck_d", + "i2c0_ao_sda_d"; + function = "i2c0_ao"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + pwm_a_pins: pwm-a { mux { groups = "pwm_a"; From 45491ec4438bd667c6fc9a0456ea75e3ca9e1eef Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Thu, 7 May 2026 10:20:58 +0800 Subject: [PATCH 586/665] MAINTAINERS: update Chen Wang's email address Update my email address as my original email provider may block emails in kernel development. Signed-off-by: Chen Wang Link: https://patch.msgid.link/20260507022058.3913-1-chen.wang@linux.dev Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 2fb1c75afd16..521c8ea81d5e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -24931,7 +24931,7 @@ F: drivers/char/sonypi.c F: drivers/platform/x86/sony-laptop.c SOPHGO DEVICETREES and DRIVERS -M: Chen Wang +M: Chen Wang M: Inochi Amaoto L: sophgo@lists.linux.dev W: https://github.com/sophgo/linux/wiki From efe66eed43ef507a5b3784d988842d2e621806e1 Mon Sep 17 00:00:00 2001 From: Joshua Milas Date: Sat, 30 May 2026 13:33:43 -0400 Subject: [PATCH 587/665] dt-bindings: soc: sophgo: add Milk-V Duo S board compatibles Document the compatible strings for the Milk-V Duo S board [1] which uses the SOPHGO SG2000 SoC. Link: https://milkv.io/duo-s [1] Signed-off-by: Joshua Milas Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260530173347.33533-2-josh.milas@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang --- Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml b/Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml index 1c502618de51..0b6fbab48b74 100644 --- a/Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml +++ b/Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml @@ -31,6 +31,10 @@ properties: - milkv,duo-module-01-evb - const: milkv,duo-module-01 - const: sophgo,sg2000 + - items: + - enum: + - milkv,duo-s + - const: sophgo,sg2000 - items: - enum: - sipeed,licheerv-nano-b From 972e8823d93866bc39cf6270bd5ec26d055b9d6f Mon Sep 17 00:00:00 2001 From: Joshua Milas Date: Sat, 30 May 2026 13:33:45 -0400 Subject: [PATCH 588/665] dt-bindings: soc: sophgo: add sg2000 plic and clint documentation Document the compatible strings for the sg2000 interrupt controller and timer. Signed-off-by: Joshua Milas Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260530173347.33533-4-josh.milas@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 2 files changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index e0267223887e..decc43df3c83 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -73,6 +73,7 @@ properties: - allwinner,sun20i-d1-plic - sophgo,cv1800b-plic - sophgo,cv1812h-plic + - sophgo,sg2000-plic - sophgo,sg2002-plic - sophgo,sg2042-plic - sophgo,sg2044-plic diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index 3c16b260db04..e7b5cd8b1803 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -51,6 +51,7 @@ properties: - allwinner,sun20i-d1-clint - sophgo,cv1800b-clint - sophgo,cv1812h-clint + - sophgo,sg2000-clint - sophgo,sg2002-clint - thead,th1520-clint - const: thead,c900-clint From dc98bd71f41db3666aa8505cc8c72d02653d2980 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 1 Jun 2026 18:10:00 +0800 Subject: [PATCH 589/665] arm64: dts: rockchip: enable adc button for Radxa E25 The Radxa E25 board has an ADC button. Enable it. Signed-off-by: Chukun Pan Link: https://patch.msgid.link/20260601101000.2076721-1-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts index 98cfa3abb809..a091c3a44747 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts @@ -1,6 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /dts-v1/; +#include #include "rk3568-radxa-cm3i.dtsi" / { @@ -11,6 +12,19 @@ aliases { mmc1 = &sdmmc0; }; + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + + button-recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <0>; + }; + }; + pwm-leds { compatible = "pwm-leds-multicolor"; From da6662e9933880124ff6e8eea73e73a775d9ac65 Mon Sep 17 00:00:00 2001 From: Alexander Feilke Date: Wed, 27 May 2026 11:37:17 +0200 Subject: [PATCH 590/665] ARM: dts: imx7: add nvmem-layout TQMa7 has board-information located in EEPROM at offset 0x20. Add necessary nodes and properties for nvmem cell. Signed-off-by: Alexander Feilke Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi index 2966a33bc528..020eb0c7c353 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi @@ -151,6 +151,16 @@ m24c64: eeprom@50 { reg = <0x50>; pagesize = <32>; vcc-supply = <&vgen4_reg>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + module_info: module-info@20 { + reg = <0x20 0x60>; + }; + }; }; at24c02: eeprom@56 { From 936bde7f106cac02c07c38894e0596ae25b65398 Mon Sep 17 00:00:00 2001 From: Alice Guo Date: Tue, 19 May 2026 18:55:16 +0800 Subject: [PATCH 591/665] ARM: dts: freescale: add bootph-all to i.MX7ULP watchdog nodes Add the bootph-all property to ULP watchdog nodes for i.MX7ULP, ensuring the watchdog is available during all boot phases. Signed-off-by: Alice Guo Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi b/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi index 880b9a4f32b0..564783735de8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi @@ -297,6 +297,18 @@ smc1: clock-controller@40410000 { clock-names = "divcore", "hsrun_divcore"; }; + wdog2: watchdog@40430000 { + compatible = "fsl,imx7ulp-wdt"; + reg = <0x40430000 0x10000>; + interrupts = ; + clocks = <&pcc2 IMX7ULP_CLK_WDG2>; + assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG2>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; + timeout-sec = <40>; + status = "disabled"; + bootph-all; + }; + pcc3: clock-controller@40b30000 { compatible = "fsl,imx7ulp-pcc3"; reg = <0x40b30000 0x10000>; From 5f3ae9b12a6c523992a7216bbc4420ac33450b79 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 29 May 2026 21:03:51 +0200 Subject: [PATCH 592/665] arm64: dts: rockchip: Add USB nodes for RK3528 Rockchip RK3528 has one USB 3.0 DWC3 controller and oneUSB 2.0 EHCI/OHCI controller and uses an Innosilicon-USB2PHY for USB 2.0. The DWC3 controller additionally uses the Naneng Combo PHY for USB3. Add device tree nodes to describe these USB controllers along with the USB 2.0 PHYs. [moved snps,dis_u2_susphy_quirk here from individual boards, describe both usb2+3 default phy connections, usb2 boards can override] Signed-off-by: Jonas Karlman Signed-off-by: Heiko Stuebner Link: https://patch.msgid.link/20260529190355.4148175-2-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 80 ++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index 77d314716b43..03cd00f88dbb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -336,6 +336,33 @@ pcie_intc: legacy-interrupt-controller { }; }; + usb_host0_xhci: usb@fe500000 { + compatible = "rockchip,rk3528-dwc3", "snps,dwc3"; + reg = <0x0 0xfe500000 0x0 0x400000>; + clocks = <&cru CLK_REF_USB3OTG>, + <&cru CLK_SUSPEND_USB3OTG>, + <&cru ACLK_USB3OTG>; + clock-names = "ref_clk", "suspend_clk", "bus_clk"; + interrupts = ; + power-domains = <&power RK3528_PD_VPU>; + resets = <&cru SRST_A_USB3OTG>; + dr_mode = "otg"; + phys = <&usb2phy_otg>, <&combphy PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis_rxdet_inp3_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + status = "disabled"; + }; + gic: interrupt-controller@fed01000 { compatible = "arm,gic-400"; reg = <0x0 0xfed01000 0 0x1000>, @@ -349,6 +376,30 @@ gic: interrupt-controller@fed01000 { #interrupt-cells = <3>; }; + usb_host0_ehci: usb@ff100000 { + compatible = "generic-ehci"; + reg = <0x0 0xff100000 0x0 0x40000>; + clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>, + <&usb2phy>; + interrupts = ; + phys = <&usb2phy_host>; + phy-names = "usb"; + power-domains = <&power RK3528_PD_VO>; + status = "disabled"; + }; + + usb_host0_ohci: usb@ff140000 { + compatible = "generic-ohci"; + reg = <0x0 0xff140000 0x0 0x40000>; + clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>, + <&usb2phy>; + interrupts = ; + phys = <&usb2phy_host>; + phy-names = "usb"; + power-domains = <&power RK3528_PD_VO>; + status = "disabled"; + }; + qos_crypto_a: qos@ff200000 { compatible = "rockchip,rk3528-qos", "syscon"; reg = <0x0 0xff200000 0x0 0x20>; @@ -1281,6 +1332,35 @@ combphy: phy@ffdc0000 { rockchip,pipe-phy-grf = <&pipe_phy_grf>; status = "disabled"; }; + + usb2phy: usb2phy@ffdf0000 { + compatible = "rockchip,rk3528-usb2phy"; + reg = <0x0 0xffdf0000 0x0 0x10000>; + clocks = <&cru CLK_REF_USBPHY>, <&cru PCLK_USBPHY>; + clock-names = "phyclk", "pclk"; + #clock-cells = <0>; + clock-output-names = "clk_usbphy_480m"; + power-domains = <&power RK3528_PD_VO>; + rockchip,usbgrf = <&vo_grf>; + status = "disabled"; + + usb2phy_otg: otg-port { + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + + usb2phy_host: host-port { + interrupts = ; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + }; }; }; From e897bcf81dd920bf80ace6d98ec6f9645c5b50f2 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 29 May 2026 21:03:52 +0200 Subject: [PATCH 593/665] arm64: dts: rockchip: Enable USB 2.0 ports on Radxa E20C The Radxa E20C has one USB2.0 Type-A HOST port and one USB2.0 Type-C port. The Type-C port is conneced to a FE1.1s_QFN USB hub on the board, with its ports being connected to the XHCI usb controller and an usb-uart bridge. This also means, the XHCI controller can only be used in device-mode. Add support for using the USB 2.0 ports on Radxa E20C. Signed-off-by: Jonas Karlman [set xhci to peripheral and add comment about the outward-facing hub] Signed-off-by: Heiko Stuebner Link: https://patch.msgid.link/20260529190355.4148175-3-heiko@sntech.de --- .../boot/dts/rockchip/rk3528-radxa-e20c.dts | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts index b32452756155..f872b8d20ebc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts @@ -134,6 +134,18 @@ vcc5v0_sys: regulator-5v0-vcc-sys { regulator-max-microvolt = <5000000>; }; + vcc5v0_usb20: regulator-5v0-vcc-usb20 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_en>; + regulator-name = "vcc5v0_usb20"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + vccio_sd: regulator-vccio-sd { compatible = "regulator-gpio"; gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; @@ -273,6 +285,12 @@ sdmmc_vol_ctrl_h: sdmmc-vol-ctrl-h { rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + usb { + usb_host_en: usb-host-en { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pwm1 { @@ -320,3 +338,45 @@ &uart0 { pinctrl-0 = <&uart0m0_xfer>; status = "okay"; }; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +/* + * The usb controller can only work in peripheral mode, as it is + * connected to one of the ports of an outward-facing usb hub. + * + * type_c-port (hub-input) + * | + * usb-hub + * | | + * uart-usb usb-host0 + * | + * uart0 + */ +&usb_host0_xhci { + dr_mode = "peripheral"; + extcon = <&usb2phy>; + maximum-speed = "high-speed"; + phys = <&usb2phy_otg>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usb2phy { + status = "okay"; +}; + +&usb2phy_host { + phy-supply = <&vcc5v0_usb20>; + status = "okay"; +}; + +&usb2phy_otg { + status = "okay"; +}; From 4e55d52f5f3b333a9ff5103099df97291aaeb083 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 29 May 2026 21:03:53 +0200 Subject: [PATCH 594/665] arm64: dts: rockchip: Enable USB ports on Radxa ROCK 2A/2F The ROCK 2A has three USB 2.0 Type-A HOST ports behind an onboard USB hub, and one USB 3.0 Type-A port. And the ROCK 2F has two USB 2.0 Type-A HOST ports behind an onboard USB hub, and one USB 2.0 Type-C OTG port. Add support for using the USB ports on Radxa ROCK 2A/2F. The onboard USB hub handles OHCI so only the EHCI controller is enabled. Signed-off-by: Jonas Karlman Signed-off-by: Heiko Stuebner Link: https://patch.msgid.link/20260529190355.4148175-4-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi | 17 +++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts | 11 +++++++++++ arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts | 12 ++++++++++++ 3 files changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi b/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi index aedc7ee9ee46..501a91f4c23e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi @@ -166,6 +166,10 @@ rfkill { }; }; +&combphy { + status = "okay"; +}; + &cpu0 { cpu-supply = <&vdd_arm>; }; @@ -291,3 +295,16 @@ &uart0 { pinctrl-0 = <&uart0m0_xfer>; status = "okay"; }; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb2phy { + status = "okay"; +}; + +&usb2phy_host { + phy-supply = <&vcc5v0_usb20>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts b/arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts index 0b696d49b71f..5e17ec2758d5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts @@ -79,3 +79,14 @@ usb_otg_en: usb-otg-en { }; }; }; + +&usb_host0_xhci { + dr_mode = "host"; + extcon = <&usb2phy>; + status = "okay"; +}; + +&usb2phy_otg { + phy-supply = <&vcc5v0_usb30_otg>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts b/arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts index 3e2b9b685cb2..f2b021ff5046 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts +++ b/arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts @@ -8,3 +8,15 @@ / { model = "Radxa ROCK 2F"; compatible = "radxa,rock-2f", "rockchip,rk3528"; }; + +&usb_host0_xhci { + extcon = <&usb2phy>; + maximum-speed = "high-speed"; + phys = <&usb2phy_otg>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usb2phy_otg { + status = "okay"; +}; From b6b74087f90a201cfdd6da6a43e7b92dba8370e3 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 29 May 2026 21:03:54 +0200 Subject: [PATCH 595/665] arm64: dts: rockchip: Enable USB 2.0 ports on ArmSoM Sige1 The ArmSoM Sige1 has two USB 2.0 Type-A HOST ports behind an onboard USB hub, and one USB 2.0 Type-C OTG port. Add support for using the USB 2.0 ports on ArmSoM Sige1. The onboard USB hub handles OHCI so only the EHCI controller is enabled. Signed-off-by: Jonas Karlman [added phy-supply for otg port] Signed-off-by: Heiko Stuebner Link: https://patch.msgid.link/20260529190355.4148175-5-heiko@sntech.de --- .../boot/dts/rockchip/rk3528-armsom-sige1.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts b/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts index c41af8fc0c8d..ee4183fb980d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts @@ -480,3 +480,28 @@ bluetooth { vddio-supply = <&vcc_1v8>; }; }; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_xhci { + extcon = <&usb2phy>; + maximum-speed = "high-speed"; + phys = <&usb2phy_otg>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usb2phy { + status = "okay"; +}; + +&usb2phy_host { + status = "okay"; +}; + +&usb2phy_otg { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; From ff660109f4129a13bbdc31bc14ca233ebf0c9450 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 29 May 2026 21:03:55 +0200 Subject: [PATCH 596/665] arm64: dts: rockchip: Enable USB 2.0 ports on NanoPi Zero2 The NanoPi Zero2 has one USB 2.0 Type-A HOST port and one USB 2.0 Type-C OTG port. Add support for using the USB 2.0 ports on NanoPi Zero2. Signed-off-by: Jonas Karlman Signed-off-by: Heiko Stuebner Link: https://patch.msgid.link/20260529190355.4148175-6-heiko@sntech.de --- .../boot/dts/rockchip/rk3528-nanopi-zero2.dts | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts b/arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts index 9f683033c5f3..97d85124d21b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts @@ -338,3 +338,32 @@ &uart0 { pinctrl-0 = <&uart0m0_xfer>; status = "okay"; }; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + extcon = <&usb2phy>; + maximum-speed = "high-speed"; + phys = <&usb2phy_otg>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usb2phy { + status = "okay"; +}; + +&usb2phy_host { + phy-supply = <&usb2_host_5v>; + status = "okay"; +}; + +&usb2phy_otg { + status = "okay"; +}; From 8545eda00fdf3d7e17933ce0f706d005b1bad42d Mon Sep 17 00:00:00 2001 From: Hugo Osvaldo Barrera Date: Tue, 19 May 2026 11:44:39 +0200 Subject: [PATCH 597/665] arm64: dts: rockchip: Fix vcc_sdio regulator max voltage on Pinebook Pro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The vcc_sdio regulator supports 1.8V to 3.4V output range according to its datasheet. The current DT incorrectly limits the max voltage to 3.0V. This limit causes issues issues downstream with u-boot, which refuses to apply the out-of range value, and falls back to the minimum in that range: 1.8V. This is insufficient to power the SD card, so driver initialisation fails and booting from it does not work. Set regulator-max-microvolt to 3400000 µV to match hardware capability. This matches the rk3399-orangepi for the same regulator. Signed-off-by: Hugo Osvaldo Barrera Reviewed-by: Dang Huynh Link: https://patch.msgid.link/20260519094439.7918-1-hugo@whynothugo.nl Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts index b5c05928142c..f21fcdc1b49a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts @@ -526,7 +526,7 @@ vcc_sdio: LDO_REG4 { regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; regulator-state-mem { regulator-on-in-suspend; From 2647eabde8de748ee2c9a2816615d4af3bd4bf9d Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 1 Apr 2026 01:12:48 +0800 Subject: [PATCH 598/665] riscv: dts: sophgo: Add dma-coherent to SG2042 PCIe controllers SG2042's PCIe root complexes are cache-coherent with the CPU. Mark all four PCIe controller nodes (pcie_rc0 through pcie_rc3) as dma-coherent so the kernel uses coherent DMA mappings instead of non-coherent bounce buffering. Cc: stable@vger.kernel.org Signed-off-by: Han Gao Link: https://patch.msgid.link/20260331171248.973014-3-gaohan@iscas.ac.cn Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index 9fddf3f0b3b9..3af770549742 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -417,6 +417,7 @@ pcie_rc0: pcie@7060000000 { vendor-id = <0x1f1c>; device-id = <0x2042>; cdns,no-bar-match-nbits = <48>; + dma-coherent; msi-parent = <&msi>; status = "disabled"; }; @@ -439,6 +440,7 @@ pcie_rc1: pcie@7060800000 { vendor-id = <0x1f1c>; device-id = <0x2042>; cdns,no-bar-match-nbits = <48>; + dma-coherent; msi-parent = <&msi>; status = "disabled"; }; @@ -461,6 +463,7 @@ pcie_rc2: pcie@7062000000 { vendor-id = <0x1f1c>; device-id = <0x2042>; cdns,no-bar-match-nbits = <48>; + dma-coherent; msi-parent = <&msi>; status = "disabled"; }; @@ -483,6 +486,7 @@ pcie_rc3: pcie@7062800000 { vendor-id = <0x1f1c>; device-id = <0x2042>; cdns,no-bar-match-nbits = <48>; + dma-coherent; msi-parent = <&msi>; status = "disabled"; }; From 207cbc477406a72952e27ace2eadbae55164f129 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Sun, 26 Apr 2026 09:34:48 +0800 Subject: [PATCH 599/665] riscv: dts: sophgo: sg2044: use hex for CPU unit address Previous the CPU unit address cpu of sg2044 use decimal, it is not following the general convention for unit addresses of the OF. Convent the unit address to hex to resolve this problem. The introduces a small change for the CPU node name, but it should nothing since there is no direct full-path reference to these CPU nodes. Fixes: 967a94a92aaa ("riscv: dts: add initial Sophgo SG2042 SoC device tree") Reviewed-by: Chen Wang Reviewed-by: Guo Ren Link: https://patch.msgid.link/20260426013449.694435-2-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 236 ++++++++++---------- 1 file changed, 118 insertions(+), 118 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi index 3135409c2149..f66a382c95bd 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi @@ -14,7 +14,7 @@ cpus { cpu0: cpu@0 { compatible = "thead,c920", "riscv"; - reg = <0>; + reg = <0x0>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -50,7 +50,7 @@ cpu0_intc: interrupt-controller { cpu1: cpu@1 { compatible = "thead,c920", "riscv"; - reg = <1>; + reg = <0x1>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -86,7 +86,7 @@ cpu1_intc: interrupt-controller { cpu2: cpu@2 { compatible = "thead,c920", "riscv"; - reg = <2>; + reg = <0x2>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -122,7 +122,7 @@ cpu2_intc: interrupt-controller { cpu3: cpu@3 { compatible = "thead,c920", "riscv"; - reg = <3>; + reg = <0x3>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -158,7 +158,7 @@ cpu3_intc: interrupt-controller { cpu4: cpu@4 { compatible = "thead,c920", "riscv"; - reg = <4>; + reg = <0x4>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -194,7 +194,7 @@ cpu4_intc: interrupt-controller { cpu5: cpu@5 { compatible = "thead,c920", "riscv"; - reg = <5>; + reg = <0x5>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -230,7 +230,7 @@ cpu5_intc: interrupt-controller { cpu6: cpu@6 { compatible = "thead,c920", "riscv"; - reg = <6>; + reg = <0x6>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -266,7 +266,7 @@ cpu6_intc: interrupt-controller { cpu7: cpu@7 { compatible = "thead,c920", "riscv"; - reg = <7>; + reg = <0x7>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -302,7 +302,7 @@ cpu7_intc: interrupt-controller { cpu8: cpu@8 { compatible = "thead,c920", "riscv"; - reg = <8>; + reg = <0x8>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -338,7 +338,7 @@ cpu8_intc: interrupt-controller { cpu9: cpu@9 { compatible = "thead,c920", "riscv"; - reg = <9>; + reg = <0x9>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -372,9 +372,9 @@ cpu9_intc: interrupt-controller { }; }; - cpu10: cpu@10 { + cpu10: cpu@a { compatible = "thead,c920", "riscv"; - reg = <10>; + reg = <0xa>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -408,9 +408,9 @@ cpu10_intc: interrupt-controller { }; }; - cpu11: cpu@11 { + cpu11: cpu@b { compatible = "thead,c920", "riscv"; - reg = <11>; + reg = <0xb>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -444,9 +444,9 @@ cpu11_intc: interrupt-controller { }; }; - cpu12: cpu@12 { + cpu12: cpu@c { compatible = "thead,c920", "riscv"; - reg = <12>; + reg = <0xc>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -480,9 +480,9 @@ cpu12_intc: interrupt-controller { }; }; - cpu13: cpu@13 { + cpu13: cpu@d { compatible = "thead,c920", "riscv"; - reg = <13>; + reg = <0xd>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -516,9 +516,9 @@ cpu13_intc: interrupt-controller { }; }; - cpu14: cpu@14 { + cpu14: cpu@e { compatible = "thead,c920", "riscv"; - reg = <14>; + reg = <0xe>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -552,9 +552,9 @@ cpu14_intc: interrupt-controller { }; }; - cpu15: cpu@15 { + cpu15: cpu@f { compatible = "thead,c920", "riscv"; - reg = <15>; + reg = <0xf>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -588,9 +588,9 @@ cpu15_intc: interrupt-controller { }; }; - cpu16: cpu@16 { + cpu16: cpu@10 { compatible = "thead,c920", "riscv"; - reg = <16>; + reg = <0x10>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -624,9 +624,9 @@ cpu16_intc: interrupt-controller { }; }; - cpu17: cpu@17 { + cpu17: cpu@11 { compatible = "thead,c920", "riscv"; - reg = <17>; + reg = <0x11>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -660,9 +660,9 @@ cpu17_intc: interrupt-controller { }; }; - cpu18: cpu@18 { + cpu18: cpu@12 { compatible = "thead,c920", "riscv"; - reg = <18>; + reg = <0x12>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -696,9 +696,9 @@ cpu18_intc: interrupt-controller { }; }; - cpu19: cpu@19 { + cpu19: cpu@13 { compatible = "thead,c920", "riscv"; - reg = <19>; + reg = <0x13>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -732,9 +732,9 @@ cpu19_intc: interrupt-controller { }; }; - cpu20: cpu@20 { + cpu20: cpu@14 { compatible = "thead,c920", "riscv"; - reg = <20>; + reg = <0x14>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -768,9 +768,9 @@ cpu20_intc: interrupt-controller { }; }; - cpu21: cpu@21 { + cpu21: cpu@15 { compatible = "thead,c920", "riscv"; - reg = <21>; + reg = <0x15>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -804,9 +804,9 @@ cpu21_intc: interrupt-controller { }; }; - cpu22: cpu@22 { + cpu22: cpu@16 { compatible = "thead,c920", "riscv"; - reg = <22>; + reg = <0x16>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -840,9 +840,9 @@ cpu22_intc: interrupt-controller { }; }; - cpu23: cpu@23 { + cpu23: cpu@17 { compatible = "thead,c920", "riscv"; - reg = <23>; + reg = <0x17>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -876,9 +876,9 @@ cpu23_intc: interrupt-controller { }; }; - cpu24: cpu@24 { + cpu24: cpu@18 { compatible = "thead,c920", "riscv"; - reg = <24>; + reg = <0x18>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -912,9 +912,9 @@ cpu24_intc: interrupt-controller { }; }; - cpu25: cpu@25 { + cpu25: cpu@19 { compatible = "thead,c920", "riscv"; - reg = <25>; + reg = <0x19>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -948,9 +948,9 @@ cpu25_intc: interrupt-controller { }; }; - cpu26: cpu@26 { + cpu26: cpu@1a { compatible = "thead,c920", "riscv"; - reg = <26>; + reg = <0x1a>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -984,9 +984,9 @@ cpu26_intc: interrupt-controller { }; }; - cpu27: cpu@27 { + cpu27: cpu@1b { compatible = "thead,c920", "riscv"; - reg = <27>; + reg = <0x1b>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1020,9 +1020,9 @@ cpu27_intc: interrupt-controller { }; }; - cpu28: cpu@28 { + cpu28: cpu@1c { compatible = "thead,c920", "riscv"; - reg = <28>; + reg = <0x1c>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1056,9 +1056,9 @@ cpu28_intc: interrupt-controller { }; }; - cpu29: cpu@29 { + cpu29: cpu@1d { compatible = "thead,c920", "riscv"; - reg = <29>; + reg = <0x1d>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1092,9 +1092,9 @@ cpu29_intc: interrupt-controller { }; }; - cpu30: cpu@30 { + cpu30: cpu@1e { compatible = "thead,c920", "riscv"; - reg = <30>; + reg = <0x1e>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1128,9 +1128,9 @@ cpu30_intc: interrupt-controller { }; }; - cpu31: cpu@31 { + cpu31: cpu@1f { compatible = "thead,c920", "riscv"; - reg = <31>; + reg = <0x1f>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1164,9 +1164,9 @@ cpu31_intc: interrupt-controller { }; }; - cpu32: cpu@32 { + cpu32: cpu@20 { compatible = "thead,c920", "riscv"; - reg = <32>; + reg = <0x20>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1200,9 +1200,9 @@ cpu32_intc: interrupt-controller { }; }; - cpu33: cpu@33 { + cpu33: cpu@21 { compatible = "thead,c920", "riscv"; - reg = <33>; + reg = <0x21>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1236,9 +1236,9 @@ cpu33_intc: interrupt-controller { }; }; - cpu34: cpu@34 { + cpu34: cpu@22 { compatible = "thead,c920", "riscv"; - reg = <34>; + reg = <0x22>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1272,9 +1272,9 @@ cpu34_intc: interrupt-controller { }; }; - cpu35: cpu@35 { + cpu35: cpu@23 { compatible = "thead,c920", "riscv"; - reg = <35>; + reg = <0x23>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1308,9 +1308,9 @@ cpu35_intc: interrupt-controller { }; }; - cpu36: cpu@36 { + cpu36: cpu@24 { compatible = "thead,c920", "riscv"; - reg = <36>; + reg = <0x24>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1344,9 +1344,9 @@ cpu36_intc: interrupt-controller { }; }; - cpu37: cpu@37 { + cpu37: cpu@25 { compatible = "thead,c920", "riscv"; - reg = <37>; + reg = <0x25>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1380,9 +1380,9 @@ cpu37_intc: interrupt-controller { }; }; - cpu38: cpu@38 { + cpu38: cpu@26 { compatible = "thead,c920", "riscv"; - reg = <38>; + reg = <0x26>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1416,9 +1416,9 @@ cpu38_intc: interrupt-controller { }; }; - cpu39: cpu@39 { + cpu39: cpu@27 { compatible = "thead,c920", "riscv"; - reg = <39>; + reg = <0x27>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1452,9 +1452,9 @@ cpu39_intc: interrupt-controller { }; }; - cpu40: cpu@40 { + cpu40: cpu@28 { compatible = "thead,c920", "riscv"; - reg = <40>; + reg = <0x28>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1488,9 +1488,9 @@ cpu40_intc: interrupt-controller { }; }; - cpu41: cpu@41 { + cpu41: cpu@29 { compatible = "thead,c920", "riscv"; - reg = <41>; + reg = <0x29>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1524,9 +1524,9 @@ cpu41_intc: interrupt-controller { }; }; - cpu42: cpu@42 { + cpu42: cpu@2a { compatible = "thead,c920", "riscv"; - reg = <42>; + reg = <0x2a>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1560,9 +1560,9 @@ cpu42_intc: interrupt-controller { }; }; - cpu43: cpu@43 { + cpu43: cpu@2b { compatible = "thead,c920", "riscv"; - reg = <43>; + reg = <0x2b>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1596,9 +1596,9 @@ cpu43_intc: interrupt-controller { }; }; - cpu44: cpu@44 { + cpu44: cpu@2c { compatible = "thead,c920", "riscv"; - reg = <44>; + reg = <0x2c>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1632,9 +1632,9 @@ cpu44_intc: interrupt-controller { }; }; - cpu45: cpu@45 { + cpu45: cpu@2d { compatible = "thead,c920", "riscv"; - reg = <45>; + reg = <0x2d>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1668,9 +1668,9 @@ cpu45_intc: interrupt-controller { }; }; - cpu46: cpu@46 { + cpu46: cpu@2e { compatible = "thead,c920", "riscv"; - reg = <46>; + reg = <0x2e>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1704,9 +1704,9 @@ cpu46_intc: interrupt-controller { }; }; - cpu47: cpu@47 { + cpu47: cpu@2f { compatible = "thead,c920", "riscv"; - reg = <47>; + reg = <0x2f>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1740,9 +1740,9 @@ cpu47_intc: interrupt-controller { }; }; - cpu48: cpu@48 { + cpu48: cpu@30 { compatible = "thead,c920", "riscv"; - reg = <48>; + reg = <0x30>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1776,9 +1776,9 @@ cpu48_intc: interrupt-controller { }; }; - cpu49: cpu@49 { + cpu49: cpu@31 { compatible = "thead,c920", "riscv"; - reg = <49>; + reg = <0x31>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1812,9 +1812,9 @@ cpu49_intc: interrupt-controller { }; }; - cpu50: cpu@50 { + cpu50: cpu@32 { compatible = "thead,c920", "riscv"; - reg = <50>; + reg = <0x32>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1848,9 +1848,9 @@ cpu50_intc: interrupt-controller { }; }; - cpu51: cpu@51 { + cpu51: cpu@33 { compatible = "thead,c920", "riscv"; - reg = <51>; + reg = <0x33>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1884,9 +1884,9 @@ cpu51_intc: interrupt-controller { }; }; - cpu52: cpu@52 { + cpu52: cpu@34 { compatible = "thead,c920", "riscv"; - reg = <52>; + reg = <0x34>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1920,9 +1920,9 @@ cpu52_intc: interrupt-controller { }; }; - cpu53: cpu@53 { + cpu53: cpu@35 { compatible = "thead,c920", "riscv"; - reg = <53>; + reg = <0x35>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1956,9 +1956,9 @@ cpu53_intc: interrupt-controller { }; }; - cpu54: cpu@54 { + cpu54: cpu@36 { compatible = "thead,c920", "riscv"; - reg = <54>; + reg = <0x36>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1992,9 +1992,9 @@ cpu54_intc: interrupt-controller { }; }; - cpu55: cpu@55 { + cpu55: cpu@37 { compatible = "thead,c920", "riscv"; - reg = <55>; + reg = <0x37>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -2028,9 +2028,9 @@ cpu55_intc: interrupt-controller { }; }; - cpu56: cpu@56 { + cpu56: cpu@38 { compatible = "thead,c920", "riscv"; - reg = <56>; + reg = <0x38>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -2064,9 +2064,9 @@ cpu56_intc: interrupt-controller { }; }; - cpu57: cpu@57 { + cpu57: cpu@39 { compatible = "thead,c920", "riscv"; - reg = <57>; + reg = <0x39>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -2100,9 +2100,9 @@ cpu57_intc: interrupt-controller { }; }; - cpu58: cpu@58 { + cpu58: cpu@3a { compatible = "thead,c920", "riscv"; - reg = <58>; + reg = <0x3a>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -2136,9 +2136,9 @@ cpu58_intc: interrupt-controller { }; }; - cpu59: cpu@59 { + cpu59: cpu@3b { compatible = "thead,c920", "riscv"; - reg = <59>; + reg = <0x3b>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -2172,9 +2172,9 @@ cpu59_intc: interrupt-controller { }; }; - cpu60: cpu@60 { + cpu60: cpu@3c { compatible = "thead,c920", "riscv"; - reg = <60>; + reg = <0x3c>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -2208,9 +2208,9 @@ cpu60_intc: interrupt-controller { }; }; - cpu61: cpu@61 { + cpu61: cpu@3d { compatible = "thead,c920", "riscv"; - reg = <61>; + reg = <0x3d>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -2244,9 +2244,9 @@ cpu61_intc: interrupt-controller { }; }; - cpu62: cpu@62 { + cpu62: cpu@3e { compatible = "thead,c920", "riscv"; - reg = <62>; + reg = <0x3e>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -2280,9 +2280,9 @@ cpu62_intc: interrupt-controller { }; }; - cpu63: cpu@63 { + cpu63: cpu@3f { compatible = "thead,c920", "riscv"; - reg = <63>; + reg = <0x3f>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; From a7e658907686528fe06a11828b04a3e42df9ef18 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Sun, 26 Apr 2026 09:34:49 +0800 Subject: [PATCH 600/665] riscv: dts: sophgo: sg2042: use hex for CPU unit address Previous the CPU unit address cpu of sg2042 use decimal, it is not following the general convention for unit addresses of the OF. Convent the unit address to hex to resolve this problem. The introduces a small change for the CPU node name, but it should affect nothing since there is no direct full-path reference to these CPU nodes. Fixes: ae5bac370ed4 ("riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10") Tested-by: Chen Wang # Pioneerbox. Reviewed-by: Guo Ren Reviewed-by: Chen Wang Acked-by: Conor Dooley Tested-by: Chen Wang on Pioneerbox. Link: https://patch.msgid.link/20260426013449.694435-3-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 236 ++++++++++---------- 1 file changed, 118 insertions(+), 118 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi index 509488eee432..fd8906b313d2 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi @@ -263,7 +263,7 @@ cpu0: cpu@0 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <0>; + reg = <0x0>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -291,7 +291,7 @@ cpu1: cpu@1 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <1>; + reg = <0x1>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -319,7 +319,7 @@ cpu2: cpu@2 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <2>; + reg = <0x2>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -347,7 +347,7 @@ cpu3: cpu@3 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <3>; + reg = <0x3>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -375,7 +375,7 @@ cpu4: cpu@4 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <4>; + reg = <0x4>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -403,7 +403,7 @@ cpu5: cpu@5 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <5>; + reg = <0x5>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -431,7 +431,7 @@ cpu6: cpu@6 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <6>; + reg = <0x6>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -459,7 +459,7 @@ cpu7: cpu@7 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <7>; + reg = <0x7>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -487,7 +487,7 @@ cpu8: cpu@8 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <8>; + reg = <0x8>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -515,7 +515,7 @@ cpu9: cpu@9 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <9>; + reg = <0x9>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -533,7 +533,7 @@ cpu9_intc: interrupt-controller { }; }; - cpu10: cpu@10 { + cpu10: cpu@a { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -543,7 +543,7 @@ cpu10: cpu@10 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <10>; + reg = <0xa>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -561,7 +561,7 @@ cpu10_intc: interrupt-controller { }; }; - cpu11: cpu@11 { + cpu11: cpu@b { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -571,7 +571,7 @@ cpu11: cpu@11 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <11>; + reg = <0xb>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -589,7 +589,7 @@ cpu11_intc: interrupt-controller { }; }; - cpu12: cpu@12 { + cpu12: cpu@c { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -599,7 +599,7 @@ cpu12: cpu@12 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <12>; + reg = <0xc>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -617,7 +617,7 @@ cpu12_intc: interrupt-controller { }; }; - cpu13: cpu@13 { + cpu13: cpu@d { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -627,7 +627,7 @@ cpu13: cpu@13 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <13>; + reg = <0xd>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -645,7 +645,7 @@ cpu13_intc: interrupt-controller { }; }; - cpu14: cpu@14 { + cpu14: cpu@e { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -655,7 +655,7 @@ cpu14: cpu@14 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <14>; + reg = <0xe>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -673,7 +673,7 @@ cpu14_intc: interrupt-controller { }; }; - cpu15: cpu@15 { + cpu15: cpu@f { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -683,7 +683,7 @@ cpu15: cpu@15 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <15>; + reg = <0xf>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -701,7 +701,7 @@ cpu15_intc: interrupt-controller { }; }; - cpu16: cpu@16 { + cpu16: cpu@10 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -711,7 +711,7 @@ cpu16: cpu@16 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <16>; + reg = <0x10>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -729,7 +729,7 @@ cpu16_intc: interrupt-controller { }; }; - cpu17: cpu@17 { + cpu17: cpu@11 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -739,7 +739,7 @@ cpu17: cpu@17 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <17>; + reg = <0x11>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -757,7 +757,7 @@ cpu17_intc: interrupt-controller { }; }; - cpu18: cpu@18 { + cpu18: cpu@12 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -767,7 +767,7 @@ cpu18: cpu@18 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <18>; + reg = <0x12>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -785,7 +785,7 @@ cpu18_intc: interrupt-controller { }; }; - cpu19: cpu@19 { + cpu19: cpu@13 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -795,7 +795,7 @@ cpu19: cpu@19 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <19>; + reg = <0x13>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -813,7 +813,7 @@ cpu19_intc: interrupt-controller { }; }; - cpu20: cpu@20 { + cpu20: cpu@14 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -823,7 +823,7 @@ cpu20: cpu@20 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <20>; + reg = <0x14>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -841,7 +841,7 @@ cpu20_intc: interrupt-controller { }; }; - cpu21: cpu@21 { + cpu21: cpu@15 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -851,7 +851,7 @@ cpu21: cpu@21 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <21>; + reg = <0x15>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -869,7 +869,7 @@ cpu21_intc: interrupt-controller { }; }; - cpu22: cpu@22 { + cpu22: cpu@16 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -879,7 +879,7 @@ cpu22: cpu@22 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <22>; + reg = <0x16>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -897,7 +897,7 @@ cpu22_intc: interrupt-controller { }; }; - cpu23: cpu@23 { + cpu23: cpu@17 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -907,7 +907,7 @@ cpu23: cpu@23 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <23>; + reg = <0x17>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -925,7 +925,7 @@ cpu23_intc: interrupt-controller { }; }; - cpu24: cpu@24 { + cpu24: cpu@18 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -935,7 +935,7 @@ cpu24: cpu@24 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <24>; + reg = <0x18>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -953,7 +953,7 @@ cpu24_intc: interrupt-controller { }; }; - cpu25: cpu@25 { + cpu25: cpu@19 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -963,7 +963,7 @@ cpu25: cpu@25 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <25>; + reg = <0x19>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -981,7 +981,7 @@ cpu25_intc: interrupt-controller { }; }; - cpu26: cpu@26 { + cpu26: cpu@1a { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -991,7 +991,7 @@ cpu26: cpu@26 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <26>; + reg = <0x1a>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1009,7 +1009,7 @@ cpu26_intc: interrupt-controller { }; }; - cpu27: cpu@27 { + cpu27: cpu@1b { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1019,7 +1019,7 @@ cpu27: cpu@27 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <27>; + reg = <0x1b>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1037,7 +1037,7 @@ cpu27_intc: interrupt-controller { }; }; - cpu28: cpu@28 { + cpu28: cpu@1c { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1047,7 +1047,7 @@ cpu28: cpu@28 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <28>; + reg = <0x1c>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1065,7 +1065,7 @@ cpu28_intc: interrupt-controller { }; }; - cpu29: cpu@29 { + cpu29: cpu@1d { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1075,7 +1075,7 @@ cpu29: cpu@29 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <29>; + reg = <0x1d>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1093,7 +1093,7 @@ cpu29_intc: interrupt-controller { }; }; - cpu30: cpu@30 { + cpu30: cpu@1e { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1103,7 +1103,7 @@ cpu30: cpu@30 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <30>; + reg = <0x1e>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1121,7 +1121,7 @@ cpu30_intc: interrupt-controller { }; }; - cpu31: cpu@31 { + cpu31: cpu@1f { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1131,7 +1131,7 @@ cpu31: cpu@31 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <31>; + reg = <0x1f>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1149,7 +1149,7 @@ cpu31_intc: interrupt-controller { }; }; - cpu32: cpu@32 { + cpu32: cpu@20 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1159,7 +1159,7 @@ cpu32: cpu@32 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <32>; + reg = <0x20>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1177,7 +1177,7 @@ cpu32_intc: interrupt-controller { }; }; - cpu33: cpu@33 { + cpu33: cpu@21 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1187,7 +1187,7 @@ cpu33: cpu@33 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <33>; + reg = <0x21>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1205,7 +1205,7 @@ cpu33_intc: interrupt-controller { }; }; - cpu34: cpu@34 { + cpu34: cpu@22 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1215,7 +1215,7 @@ cpu34: cpu@34 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <34>; + reg = <0x22>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1233,7 +1233,7 @@ cpu34_intc: interrupt-controller { }; }; - cpu35: cpu@35 { + cpu35: cpu@23 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1243,7 +1243,7 @@ cpu35: cpu@35 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <35>; + reg = <0x23>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1261,7 +1261,7 @@ cpu35_intc: interrupt-controller { }; }; - cpu36: cpu@36 { + cpu36: cpu@24 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1271,7 +1271,7 @@ cpu36: cpu@36 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <36>; + reg = <0x24>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1289,7 +1289,7 @@ cpu36_intc: interrupt-controller { }; }; - cpu37: cpu@37 { + cpu37: cpu@25 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1299,7 +1299,7 @@ cpu37: cpu@37 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <37>; + reg = <0x25>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1317,7 +1317,7 @@ cpu37_intc: interrupt-controller { }; }; - cpu38: cpu@38 { + cpu38: cpu@26 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1327,7 +1327,7 @@ cpu38: cpu@38 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <38>; + reg = <0x26>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1345,7 +1345,7 @@ cpu38_intc: interrupt-controller { }; }; - cpu39: cpu@39 { + cpu39: cpu@27 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1355,7 +1355,7 @@ cpu39: cpu@39 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <39>; + reg = <0x27>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1373,7 +1373,7 @@ cpu39_intc: interrupt-controller { }; }; - cpu40: cpu@40 { + cpu40: cpu@28 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1383,7 +1383,7 @@ cpu40: cpu@40 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <40>; + reg = <0x28>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1401,7 +1401,7 @@ cpu40_intc: interrupt-controller { }; }; - cpu41: cpu@41 { + cpu41: cpu@29 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1411,7 +1411,7 @@ cpu41: cpu@41 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <41>; + reg = <0x29>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1429,7 +1429,7 @@ cpu41_intc: interrupt-controller { }; }; - cpu42: cpu@42 { + cpu42: cpu@2a { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1439,7 +1439,7 @@ cpu42: cpu@42 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <42>; + reg = <0x2a>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1457,7 +1457,7 @@ cpu42_intc: interrupt-controller { }; }; - cpu43: cpu@43 { + cpu43: cpu@2b { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1467,7 +1467,7 @@ cpu43: cpu@43 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <43>; + reg = <0x2b>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1485,7 +1485,7 @@ cpu43_intc: interrupt-controller { }; }; - cpu44: cpu@44 { + cpu44: cpu@2c { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1495,7 +1495,7 @@ cpu44: cpu@44 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <44>; + reg = <0x2c>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1513,7 +1513,7 @@ cpu44_intc: interrupt-controller { }; }; - cpu45: cpu@45 { + cpu45: cpu@2d { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1523,7 +1523,7 @@ cpu45: cpu@45 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <45>; + reg = <0x2d>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1541,7 +1541,7 @@ cpu45_intc: interrupt-controller { }; }; - cpu46: cpu@46 { + cpu46: cpu@2e { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1551,7 +1551,7 @@ cpu46: cpu@46 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <46>; + reg = <0x2e>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1569,7 +1569,7 @@ cpu46_intc: interrupt-controller { }; }; - cpu47: cpu@47 { + cpu47: cpu@2f { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1579,7 +1579,7 @@ cpu47: cpu@47 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <47>; + reg = <0x2f>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1597,7 +1597,7 @@ cpu47_intc: interrupt-controller { }; }; - cpu48: cpu@48 { + cpu48: cpu@30 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1607,7 +1607,7 @@ cpu48: cpu@48 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <48>; + reg = <0x30>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1625,7 +1625,7 @@ cpu48_intc: interrupt-controller { }; }; - cpu49: cpu@49 { + cpu49: cpu@31 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1635,7 +1635,7 @@ cpu49: cpu@49 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <49>; + reg = <0x31>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1653,7 +1653,7 @@ cpu49_intc: interrupt-controller { }; }; - cpu50: cpu@50 { + cpu50: cpu@32 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1663,7 +1663,7 @@ cpu50: cpu@50 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <50>; + reg = <0x32>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1681,7 +1681,7 @@ cpu50_intc: interrupt-controller { }; }; - cpu51: cpu@51 { + cpu51: cpu@33 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1691,7 +1691,7 @@ cpu51: cpu@51 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <51>; + reg = <0x33>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1709,7 +1709,7 @@ cpu51_intc: interrupt-controller { }; }; - cpu52: cpu@52 { + cpu52: cpu@34 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1719,7 +1719,7 @@ cpu52: cpu@52 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <52>; + reg = <0x34>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1737,7 +1737,7 @@ cpu52_intc: interrupt-controller { }; }; - cpu53: cpu@53 { + cpu53: cpu@35 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1747,7 +1747,7 @@ cpu53: cpu@53 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <53>; + reg = <0x35>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1765,7 +1765,7 @@ cpu53_intc: interrupt-controller { }; }; - cpu54: cpu@54 { + cpu54: cpu@36 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1775,7 +1775,7 @@ cpu54: cpu@54 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <54>; + reg = <0x36>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1793,7 +1793,7 @@ cpu54_intc: interrupt-controller { }; }; - cpu55: cpu@55 { + cpu55: cpu@37 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1803,7 +1803,7 @@ cpu55: cpu@55 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <55>; + reg = <0x37>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1821,7 +1821,7 @@ cpu55_intc: interrupt-controller { }; }; - cpu56: cpu@56 { + cpu56: cpu@38 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1831,7 +1831,7 @@ cpu56: cpu@56 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <56>; + reg = <0x38>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1849,7 +1849,7 @@ cpu56_intc: interrupt-controller { }; }; - cpu57: cpu@57 { + cpu57: cpu@39 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1859,7 +1859,7 @@ cpu57: cpu@57 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <57>; + reg = <0x39>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1877,7 +1877,7 @@ cpu57_intc: interrupt-controller { }; }; - cpu58: cpu@58 { + cpu58: cpu@3a { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1887,7 +1887,7 @@ cpu58: cpu@58 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <58>; + reg = <0x3a>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1905,7 +1905,7 @@ cpu58_intc: interrupt-controller { }; }; - cpu59: cpu@59 { + cpu59: cpu@3b { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1915,7 +1915,7 @@ cpu59: cpu@59 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <59>; + reg = <0x3b>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1933,7 +1933,7 @@ cpu59_intc: interrupt-controller { }; }; - cpu60: cpu@60 { + cpu60: cpu@3c { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1943,7 +1943,7 @@ cpu60: cpu@60 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <60>; + reg = <0x3c>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1961,7 +1961,7 @@ cpu60_intc: interrupt-controller { }; }; - cpu61: cpu@61 { + cpu61: cpu@3d { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1971,7 +1971,7 @@ cpu61: cpu@61 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <61>; + reg = <0x3d>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1989,7 +1989,7 @@ cpu61_intc: interrupt-controller { }; }; - cpu62: cpu@62 { + cpu62: cpu@3e { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1999,7 +1999,7 @@ cpu62: cpu@62 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <62>; + reg = <0x3e>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -2017,7 +2017,7 @@ cpu62_intc: interrupt-controller { }; }; - cpu63: cpu@63 { + cpu63: cpu@3f { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -2027,7 +2027,7 @@ cpu63: cpu@63 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <63>; + reg = <0x3f>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; From 903a9364e40563faf4730dc63ad7446246f494ff Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Wed, 8 Apr 2026 00:01:43 +0800 Subject: [PATCH 601/665] riscv: dts: sophgo: reduce SG2042 MSI count to 16 The SG2042 MSI controller has one 32-bit doorbell register, and each bit corresponds to an interrupt. At a glance, it seems that the MSI controller can support 32 interrupts; however the PCI MSI capability only supports 16-bit messages, which makes the high 16 interrupts unusable in such way. Reduce the MSI count to 16 to prevent producing MSI message values that cannot fit 16-bit integers. Signed-off-by: Icenowy Zheng Reviewed-by: Chen Wang Tested-by: Chen Wang on Pioneerbox. Link: https://patch.msgid.link/20260407160143.1182430-1-zhengxingda@iscas.ac.cn Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index 3af770549742..7eab0655f150 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -234,7 +234,7 @@ msi: msi-controller@7030010304 { reg-names = "clr", "doorbell"; msi-controller; #msi-cells = <0>; - msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 32>; + msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 16>; }; rpgate: clock-controller@7030010368 { From b54fcf7a2df1124a21195afde508369e47067a1f Mon Sep 17 00:00:00 2001 From: Akash Sukhavasi Date: Wed, 20 May 2026 16:53:25 -0500 Subject: [PATCH 602/665] arm64: dts: hisilicon: hi3660-hikey960: move role-switch endpoint into connector The rt1711h Type-C controller on the HiKey960 has the USB role-switch endpoint placed as a top-level 'port' node, outside the connector subnode. This triggers two dtbs_check warnings against richtek,rt1711h.yaml: - 'port' does not match any of the regexes: '^pinctrl-[0-9]+$' - connector:ports: 'port@0' is a required property Move the role-switch endpoint into the connector's port@0, which is where usb-connector.yaml expects it. Update the DWC3 remote-endpoint phandle accordingly. The TCPM core (tcpm.c) looks up the role switch starting from the connector fwnode via fwnode_usb_role_switch_get(). With the endpoint inside the connector's port@0, it is found through the primary lookup path rather than the device-level fallback. Cross-compiled for arm64. Verified with dt_binding_check and dtbs_check. Not runtime-tested on hardware. Signed-off-by: Akash Sukhavasi Signed-off-by: Wei Xu --- .../boot/dts/hisilicon/hi3660-hikey960.dts | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index c6056a85ce80..27fb08d348c9 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -550,6 +550,12 @@ usb_con: connector { ports { #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + usb_con_hs: endpoint { + remote-endpoint = <&dwc3_role_switch>; + }; + }; port@1 { reg = <1>; usb_con_ss: endpoint { @@ -558,15 +564,6 @@ usb_con_ss: endpoint { }; }; }; - port { - #address-cells = <1>; - #size-cells = <0>; - - rt1711h_ep: endpoint@0 { - reg = <0>; - remote-endpoint = <&dwc3_role_switch>; - }; - }; }; adv7533: adv7533@39 { @@ -683,7 +680,7 @@ port { #size-cells = <0>; dwc3_role_switch: endpoint@0 { reg = <0>; - remote-endpoint = <&rt1711h_ep>; + remote-endpoint = <&usb_con_hs>; }; dwc3_ss: endpoint@1 { From 8772e1f64c7d69986821d71d8e58fd10594c9aa1 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 13 Feb 2026 12:17:11 -0500 Subject: [PATCH 603/665] dt-bindings: soc: imx: Add fsl,aipi-bus and fsl,emi-bus Add the fsl,aipi-bus and fsl,emi-bus compatible strings for i.MX1 and i.MX2 variants. These compatibles are only intended for existing legacy chips (more than 15 years old) and will not be used for new device trees. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Frank Li --- Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml b/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml index 00bbde203f59..4808065fc911 100644 --- a/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml +++ b/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml @@ -26,8 +26,10 @@ select: compatible: contains: enum: + - fsl,aipi-bus - fsl,aips - fsl,emi + - fsl,emi-bus - fsl,spba-bus required: - compatible @@ -39,8 +41,10 @@ properties: compatible: items: - enum: + - fsl,aipi-bus - fsl,aips - fsl,emi + - fsl,emi-bus - fsl,spba-bus - const: simple-bus From bb020f383caa2c824594a57e54aaa2835bbfb22f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 26 Mar 2026 05:43:21 +0100 Subject: [PATCH 604/665] arm64: dts: imx8mp: Add DT overlays for DH i.MX8M Plus DHCOM SoM and boards Add DT overlays to support DH i.MX8M Plus DHCOM SoM variants and carrier board expansion modules. The following DT overlays are implemented: - SoM: - DH 660-x00 SoM with 1xRMII PHY - DH 660-x00 SoM with 2xRMII PHY - PDK2: - DH 505-200 Display board in edge connector X12 via direct LVDS - DH 531-100 SPI/I2C board in header X21 - DH 531-200 SPI/I2C board in header X22 - DH 560-200 Display board in edge connector X12 - PDK3: - DH 505-200 Display board in edge connector X36 via direct LVDS - DH 531-100 SPI/I2C board in header X40 - DH 531-200 SPI/I2C board in header X41 - DH 560-300 Display board in edge connector X36 - EA muRata 2AE M.2 A/E-Key card in connector X20 - NXP SPF-29853-C1 MINISASTOCSI with OV5640 sensor in connector X31 - NXP SPF-29853-C1 MINISASTOCSI with OV5640 sensor in connector X29 - PicoITX: - DH 626-100 Display board in edge connector X2 Signed-off-by: Marek Vasut Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 115 +++++++++++++++++- ...mx8mp-dhcom-overlay-panel-ch101olhlwh.dtsi | 37 ++++++ .../imx8mp-dhcom-overlay-panel-clock.dtsi | 33 +++++ .../imx8mp-dhcom-overlay-panel-common.dtsi | 31 +++++ .../imx8mp-dhcom-overlay-panel-dpi.dtsi | 35 ++++++ ...8mp-dhcom-overlay-panel-etm0700g0edh6.dtsi | 53 ++++++++ .../imx8mp-dhcom-overlay-panel-lvds.dtsi | 22 ++++ .../imx8mp-dhcom-pdk-overlay-eth2xfast.dtso | 10 ++ ...-pdk2-overlay-505-200-x12-ch101olhlwh.dtso | 40 ++++++ ...imx8mp-dhcom-pdk2-overlay-531-100-x21.dtso | 32 +++++ ...imx8mp-dhcom-pdk2-overlay-531-100-x22.dtso | 32 +++++ ...imx8mp-dhcom-pdk2-overlay-560-300-x12.dtso | 25 ++++ .../boot/dts/freescale/imx8mp-dhcom-pdk2.dts | 2 +- ...-pdk3-overlay-505-200-x36-ch101olhlwh.dtso | 53 ++++++++ ...imx8mp-dhcom-pdk3-overlay-531-100-x40.dtso | 32 +++++ ...imx8mp-dhcom-pdk3-overlay-531-100-x41.dtso | 32 +++++ ...imx8mp-dhcom-pdk3-overlay-560-300-x36.dtso | 24 ++++ ...imx8mp-dhcom-pdk3-overlay-732-100-x36.dtso | 36 ++++++ ...-dhcom-pdk3-overlay-ea-murata-2ae-x20.dtso | 56 +++++++++ ...3-overlay-nxp-spf-29853-c1-ov5640-x29.dtso | 32 +++++ ...3-overlay-nxp-spf-29853-c1-ov5640-x31.dtso | 32 +++++ ...-pdk3-overlay-nxp-spf-29853-c1-ov5640.dtsi | 64 ++++++++++ .../boot/dts/freescale/imx8mp-dhcom-pdk3.dts | 2 +- ...icoitx-overlay-626-100-x2-ch101olhlwh.dtso | 77 ++++++++++++ .../dts/freescale/imx8mp-dhcom-picoitx.dts | 3 + .../imx8mp-dhcom-som-overlay-eth1xfast.dtso | 85 +++++++++++++ .../imx8mp-dhcom-som-overlay-eth2xfast.dtso | 29 +++++ .../boot/dts/freescale/imx8mp-dhcom-som.dtsi | 4 +- 28 files changed, 1021 insertions(+), 7 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-ch101olhlwh.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-clock.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-common.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-dpi.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-etm0700g0edh6.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-lvds.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk-overlay-eth2xfast.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2-overlay-531-100-x21.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2-overlay-531-100-x22.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2-overlay-560-300-x12.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-505-200-x36-ch101olhlwh.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-531-100-x40.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-531-100-x41.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-560-300-x36.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-732-100-x36.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-ea-murata-2ae-x20.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x29.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x31.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-dhcom-som-overlay-eth1xfast.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-dhcom-som-overlay-eth2xfast.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 513f61eb27b8..049eebda314d 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -243,9 +243,118 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-data-modul-edm-sbc.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-model-a.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-som-a-bmb-08.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-drc02.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk2.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-picoitx.dtb + +imx8mp-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh-dtbs := \ + imx8mp-dhcom-pdk2.dtb \ + imx8mp-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtbo + +imx8mp-dhcom-pdk2-overlay-531-100-x21-dtbs := \ + imx8mp-dhcom-pdk2.dtb \ + imx8mp-dhcom-pdk2-overlay-531-100-x21.dtbo + +imx8mp-dhcom-pdk2-overlay-531-100-x22-dtbs := \ + imx8mp-dhcom-pdk2.dtb \ + imx8mp-dhcom-pdk2-overlay-531-100-x22.dtbo + +imx8mp-dhcom-pdk2-overlay-560-300-x12-dtbs := \ + imx8mp-dhcom-pdk2.dtb \ + imx8mp-dhcom-pdk2-overlay-560-300-x12.dtbo + +imx8mp-dhcom-pdk2-overlay-eth1xfast-dtbs := \ + imx8mp-dhcom-pdk2.dtb \ + imx8mp-dhcom-som-overlay-eth1xfast.dtbo + +imx8mp-dhcom-pdk2-overlay-eth2xfast-dtbs := \ + imx8mp-dhcom-pdk2.dtb \ + imx8mp-dhcom-som-overlay-eth2xfast.dtbo \ + imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo + +imx8mp-dhcom-pdk3-overlay-505-200-x36-ch101olhlwh-dtbs := \ + imx8mp-dhcom-pdk3.dtb \ + imx8mp-dhcom-pdk3-overlay-505-200-x36-ch101olhlwh.dtbo + +imx8mp-dhcom-pdk3-overlay-531-100-x40-dtbs := \ + imx8mp-dhcom-pdk3.dtb \ + imx8mp-dhcom-pdk3-overlay-531-100-x40.dtbo + +imx8mp-dhcom-pdk3-overlay-531-100-x41-dtbs := \ + imx8mp-dhcom-pdk3.dtb \ + imx8mp-dhcom-pdk3-overlay-531-100-x41.dtbo + +imx8mp-dhcom-pdk3-overlay-560-300-x36-dtbs := \ + imx8mp-dhcom-pdk3.dtb \ + imx8mp-dhcom-pdk3-overlay-560-300-x36.dtbo + +imx8mp-dhcom-pdk3-overlay-732-100-x36-dtbs := \ + imx8mp-dhcom-pdk3.dtb \ + imx8mp-dhcom-pdk3-overlay-732-100-x36.dtbo + +imx8mp-dhcom-pdk3-overlay-ea-murata-2ae-x20-dtbs := \ + imx8mp-dhcom-pdk3.dtb \ + imx8mp-dhcom-pdk3-overlay-ea-murata-2ae-x20.dtbo + +imx8mp-dhcom-pdk3-overlay-eth1xfast-dtbs := \ + imx8mp-dhcom-pdk3.dtb \ + imx8mp-dhcom-som-overlay-eth1xfast.dtbo + +imx8mp-dhcom-pdk3-overlay-eth2xfast-dtbs := \ + imx8mp-dhcom-pdk3.dtb \ + imx8mp-dhcom-som-overlay-eth2xfast.dtbo \ + imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo + +imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x29-dtbs := \ + imx8mp-dhcom-pdk3.dtb \ + imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x29.dtbo + +imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x31-dtbs := \ + imx8mp-dhcom-pdk3.dtb \ + imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x31.dtbo + +dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-som-overlay-eth1xfast.dtbo \ + imx8mp-dhcom-som-overlay-eth2xfast.dtbo + +dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo + +dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk2.dtb \ + imx8mp-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtb \ + imx8mp-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtbo \ + imx8mp-dhcom-pdk2-overlay-531-100-x21.dtb \ + imx8mp-dhcom-pdk2-overlay-531-100-x21.dtbo \ + imx8mp-dhcom-pdk2-overlay-531-100-x22.dtb \ + imx8mp-dhcom-pdk2-overlay-531-100-x22.dtbo \ + imx8mp-dhcom-pdk2-overlay-560-300-x12.dtb \ + imx8mp-dhcom-pdk2-overlay-560-300-x12.dtbo \ + imx8mp-dhcom-pdk2-overlay-eth1xfast.dtb \ + imx8mp-dhcom-pdk2-overlay-eth2xfast.dtb + +dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb \ + imx8mp-dhcom-pdk3-overlay-505-200-x36-ch101olhlwh.dtb \ + imx8mp-dhcom-pdk3-overlay-505-200-x36-ch101olhlwh.dtbo \ + imx8mp-dhcom-pdk3-overlay-531-100-x40.dtb \ + imx8mp-dhcom-pdk3-overlay-531-100-x40.dtbo \ + imx8mp-dhcom-pdk3-overlay-531-100-x41.dtb \ + imx8mp-dhcom-pdk3-overlay-531-100-x41.dtbo \ + imx8mp-dhcom-pdk3-overlay-560-300-x36.dtb \ + imx8mp-dhcom-pdk3-overlay-560-300-x36.dtbo \ + imx8mp-dhcom-pdk3-overlay-732-100-x36.dtb \ + imx8mp-dhcom-pdk3-overlay-732-100-x36.dtbo \ + imx8mp-dhcom-pdk3-overlay-ea-murata-2ae-x20.dtb \ + imx8mp-dhcom-pdk3-overlay-ea-murata-2ae-x20.dtbo \ + imx8mp-dhcom-pdk3-overlay-eth1xfast.dtb \ + imx8mp-dhcom-pdk3-overlay-eth2xfast.dtb \ + imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x29.dtb \ + imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x29.dtbo \ + imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x31.dtb \ + imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x31.dtbo + +imx8mp-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh-dtbs := \ + imx8mp-dhcom-picoitx.dtb \ + imx8mp-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtbo + +dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-picoitx.dtb \ + imx8mp-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtb \ + imx8mp-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtbo + dtb-$(CONFIG_ARCH_MXC) += imx8mp-edm-g-wb.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-frdm.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-ch101olhlwh.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-ch101olhlwh.dtsi new file mode 100644 index 000000000000..cabda8648e0f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-ch101olhlwh.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2022-2026 Marek Vasut + */ + +&display_bl { + pwms = <&pwm1 0 5000000 0>; +}; + +&i2c_dhpdk_panel { + #address-cells = <1>; + #size-cells = <0>; + + touch_lvds: touchscreen@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <16384>; + touchscreen-size-y = <9600>; + touchscreen-inverted-x; + touchscreen-inverted-y; + }; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&panel { + compatible = "chefree,ch101olhlwh-002"; +}; + +&pwm1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-clock.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-clock.dtsi new file mode 100644 index 000000000000..8e702636a802 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-clock.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2024-2026 Marek Vasut + */ + +#include + +&media_blk_ctrl { + /* + * Sys PLL3 supplies TC9595 RefClk + * Audio PLL2 supplies MEDIA_DISP1_PIX (DSI) + * Video PLL1 supplies MEDIA_DISP2_PIX (LVDS) + */ + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>, + <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, + <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, + <&clk IMX8MP_AUDIO_PLL2>, + <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_AUDIO_PLL2_OUT>, + <&clk IMX8MP_VIDEO_PLL1_OUT>; + assigned-clock-rates = <500000000>, <200000000>, + <0>, <0>, <0>, <0>; +}; + +&tc_bridge { + assigned-clocks = <&clk IMX8MP_CLK_CLKOUT2_SEL>, + <&clk IMX8MP_CLK_CLKOUT2>, + <&clk IMX8MP_SYS_PLL3_OUT>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL3_OUT>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-common.dtsi new file mode 100644 index 000000000000..e8e4b40e2044 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-common.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023-2026 Marek Vasut + */ + +#include +#include +#include +#include + +#include "imx8mp-dhcom-overlay-panel-clock.dtsi" + +&{/} { + display_bl: display-bl { + compatible = "pwm-backlight"; + brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; + default-brightness-level = <8>; + enable-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; /* GPIO G */ + status = "okay"; + }; + + panel: panel { + backlight = <&display_bl>; + power-supply = <®_vdd_3p3v_awo>; + + port { + panel_in: endpoint { + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-dpi.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-dpi.dtsi new file mode 100644 index 000000000000..9c81e9f28852 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-dpi.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2022-2026 Marek Vasut + */ + +#include "imx8mp-dhcom-overlay-panel-common.dtsi" + +&lcdif1 { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; +}; + +&panel_in { + remote-endpoint = <&tc_bridge_out>; +}; + +&tc_bridge { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + tc_bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-etm0700g0edh6.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-etm0700g0edh6.dtsi new file mode 100644 index 000000000000..e3a521343cdf --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-etm0700g0edh6.dtsi @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2022-2026 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include +#include "imx8mp-dhcom-overlay-panel-dpi.dtsi" + +&{/} { + led { + led-0 { + /* LED5 GPIO conflicts with Touchscreen IRQ GPIO-E */ + status = "disabled"; + }; + }; +}; + +&i2c_dhpdk_panel { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dhcom_e>; + /* Touchscreen IRQ GPIO-E conflicts with LED5 GPIO */ + interrupt-parent = <&gpio5>; + interrupts = <22 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ + }; +}; + +&display_bl { + pwms = <&pwm1 0 5000000 PWM_POLARITY_INVERTED>; +}; + +&mipi_dsi { + /* + * This is DSIM PLL frequency, DSI HS clock lane frequency + * is half of the "samsung,burst-clock-frequency" value. + */ + samsung,burst-clock-frequency = <500000000>; +}; + +&panel { + compatible = "edt,etm0700g0edh6"; +}; + +&pwm1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-lvds.dtsi new file mode 100644 index 000000000000..c6e60a99488a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-lvds.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023-2026 Marek Vasut + */ + +#include "imx8mp-dhcom-overlay-panel-common.dtsi" + +&ldb_lvds_ch0 { + remote-endpoint = <&panel_in>; +}; + +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + status = "okay"; +}; + +&panel_in { + remote-endpoint = <&ldb_lvds_ch0>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk-overlay-eth2xfast.dtso b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk-overlay-eth2xfast.dtso new file mode 100644 index 000000000000..0da2b11720db --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk-overlay-eth2xfast.dtso @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2023-2026 Marek Vasut + */ +/dts-v1/; +/plugin/; + +ðphypdk { /* Micrel KSZ9131RNXI */ + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtso b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtso new file mode 100644 index 000000000000..92f92e6700ed --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtso @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2022-2026 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include "imx8mp-dhcom-overlay-panel-lvds.dtsi" +#include "imx8mp-dhcom-overlay-panel-ch101olhlwh.dtsi" + +&{/} { + gpio-keys { + button-1 { + /* BUTTON1 GPIO conflicts with Touchscreen RESET GPIO-B */ + status = "disabled"; + }; + }; + + led { + led-2 { + /* LED7 GPIO conflicts with Touchscreen IRQ GPIO-H */ + status = "disabled"; + }; + }; +}; + +&media_blk_ctrl { + /* + * The Chefree CH101OLHLWH-002 panel requires 71.1 MHz LVDS clock. + * Set IMX8MP_VIDEO_PLL1 to 497.7 MHz , since 497.7 MHz / 7 = 71.1 MHz . + */ + assigned-clock-rates = <500000000>, <200000000>, <0>, <0>, <0>, <497700000>; +}; + +&touch_lvds { + pinctrl-0 = <&pinctrl_dhcom_b &pinctrl_dhcom_h>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2-overlay-531-100-x21.dtso b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2-overlay-531-100-x21.dtso new file mode 100644 index 000000000000..64c730d11e6a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2-overlay-531-100-x21.dtso @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2022-2026 Marek Vasut + */ +/dts-v1/; +/plugin/; + +&ecspi1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + eeprom@0 { + compatible = "microchip,25aa010a", "atmel,at25"; + reg = <0>; + address-width = <8>; + pagesize = <16>; + size = <128>; + spi-max-frequency = <5000000>; + }; +}; + +&i2c5 { + #address-cells = <1>; + #size-cells = <0>; + + eeprom@56 { + compatible = "atmel,24c04"; + reg = <0x56>; + pagesize = <16>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2-overlay-531-100-x22.dtso b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2-overlay-531-100-x22.dtso new file mode 100644 index 000000000000..d789bf07cbb8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2-overlay-531-100-x22.dtso @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2022-2026 Marek Vasut + */ +/dts-v1/; +/plugin/; + +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + eeprom@0 { + compatible = "microchip,25aa010a", "atmel,at25"; + reg = <0>; + address-width = <8>; + pagesize = <16>; + size = <128>; + spi-max-frequency = <5000000>; + }; +}; + +&i2c4 { + #address-cells = <1>; + #size-cells = <0>; + + eeprom@56 { + compatible = "atmel,24c04"; + reg = <0x56>; + pagesize = <16>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2-overlay-560-300-x12.dtso b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2-overlay-560-300-x12.dtso new file mode 100644 index 000000000000..8ca2bd564db2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2-overlay-560-300-x12.dtso @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2022-2026 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include "imx8mp-dhcom-overlay-panel-etm0700g0edh6.dtsi" +#include "imx8mp-pinfunc.h" + +&{/} { + led { + led-0 { + /* LED5 GPIO conflicts with Touchscreen IRQ GPIO-E */ + status = "disabled"; + }; + }; +}; + +&pinctrl_dhcom_e { + fsl,pins = < + /* GPIO_E */ + MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x40000000 + >; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts index 3d18c964a22c..12fcc8f59aba 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts @@ -152,7 +152,7 @@ codec_dai: simple-audio-card,codec { }; }; -&i2c5 { +i2c_dhpdk_panel: &i2c5 { sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-505-200-x36-ch101olhlwh.dtso b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-505-200-x36-ch101olhlwh.dtso new file mode 100644 index 000000000000..397fa17a9ca2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-505-200-x36-ch101olhlwh.dtso @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2022-2026 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include "imx8mp-dhcom-overlay-panel-lvds.dtsi" +#include "imx8mp-dhcom-overlay-panel-ch101olhlwh.dtsi" +#include "imx8mp-pinfunc.h" + +&{/} { + gpio-keys { + button-1 { + /* TA2 GPIO conflicts with Touchscreen RESET GPIO-B */ + status = "disabled"; + }; + + button-2 { + /* TA3 GPIO conflicts with Touchscreen IRQ GPIO-C */ + status = "disabled"; + }; + }; + + led { + led-2 { + /* LED2 GPIO conflicts with BL-ON1 GPIO-G */ + status = "disabled"; + }; + }; +}; + +&media_blk_ctrl { + /* + * The Chefree CH101OLHLWH-002 panel requires 71.1 MHz LVDS clock. + * Set IMX8MP_VIDEO_PLL1 to 497.7 MHz , since 497.7 MHz / 7 = 71.1 MHz . + */ + assigned-clock-rates = <500000000>, <200000000>, <0>, <0>, <0>, <497700000>; +}; + +&pinctrl_dhcom_c { + fsl,pins = < + /* GPIO_C */ + MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x40000000 + >; +}; + +&touch_lvds { + pinctrl-0 = <&pinctrl_dhcom_b &pinctrl_dhcom_c>; + pinctrl-names = "default"; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-531-100-x40.dtso b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-531-100-x40.dtso new file mode 100644 index 000000000000..a319f0d881a5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-531-100-x40.dtso @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2023-2026 Marek Vasut + */ +/dts-v1/; +/plugin/; + +&ecspi1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + eeprom@0 { + compatible = "microchip,25aa010a", "atmel,at25"; + reg = <0>; + address-width = <8>; + pagesize = <16>; + size = <128>; + spi-max-frequency = <5000000>; + }; +}; + +&i2cmuxed0 { + #address-cells = <1>; + #size-cells = <0>; + + eeprom@56 { + compatible = "atmel,24c04"; + reg = <0x56>; + pagesize = <16>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-531-100-x41.dtso b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-531-100-x41.dtso new file mode 100644 index 000000000000..aaddcc88087a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-531-100-x41.dtso @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2023-2026 Marek Vasut + */ +/dts-v1/; +/plugin/; + +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + eeprom@0 { + compatible = "microchip,25aa010a", "atmel,at25"; + reg = <0>; + address-width = <8>; + pagesize = <16>; + size = <128>; + spi-max-frequency = <5000000>; + }; +}; + +&i2c4 { + #address-cells = <1>; + #size-cells = <0>; + + eeprom@56 { + compatible = "atmel,24c04"; + reg = <0x56>; + pagesize = <16>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-560-300-x36.dtso b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-560-300-x36.dtso new file mode 100644 index 000000000000..8e9fba929740 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-560-300-x36.dtso @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2023-2026 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include "imx8mp-dhcom-overlay-panel-etm0700g0edh6.dtsi" + +&{/} { + gpio-keys { + button-3 { + /* TA4 GPIO conflicts with Touchscreen IRQ GPIO-E */ + status = "disabled"; + }; + }; + + led { + led-2 { + /* LED2 GPIO conflicts with BL-ON1 GPIO-G */ + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-732-100-x36.dtso b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-732-100-x36.dtso new file mode 100644 index 000000000000..a527b7abf9a2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-732-100-x36.dtso @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2024-2026 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include "imx8mp-dhcom-overlay-panel-clock.dtsi" + +&lcdif1 { + status = "okay"; +}; + +&mipi_dsi { + samsung,burst-clock-frequency = <1000000000>; + status = "okay"; +}; + +&tc_bridge { + assigned-clock-rates = <26000000>, <26000000>, <416000000>; + toshiba,hpd-pin = <0>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + + endpoint { + toshiba,pre-emphasis = /bits/ 8 <1 1>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-ea-murata-2ae-x20.dtso b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-ea-murata-2ae-x20.dtso new file mode 100644 index 000000000000..92ed69baea45 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-ea-murata-2ae-x20.dtso @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2023-2026 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include +#include + +/* This DTO requires HI00106 SoM variant. */ + +&{/} { + led { + led-0 { + /* LED0 GPIO conflicts with #SDIO_RST GPIO-D */ + status = "disabled"; + }; + }; +}; + +&uart3 { + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + assigned-clock-rates = <80000000>; + + bluetooth { + compatible = "cypress,cyw4373a0-bt"; + max-speed = <4000000>; + }; +}; + +/* SD slot */ +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + broken-cd; + cap-power-off-card; + keep-power-in-suspend; + non-removable; + vmmc-supply = <&buck4>; + + #address-cells = <1>; + #size-cells = <0>; + + wifi@1 { /* muRata 2AE */ + compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + /* + * The "host-wake" interrupt output is by default not + * connected to the SoC, but can be connected on to + * SoC pin on the carrier board. + */ + reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; /* GPIO D */ + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x29.dtso b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x29.dtso new file mode 100644 index 000000000000..44cf737f86cf --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x29.dtso @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2023-2026 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include "imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640.dtsi" + +&mipi_csi_1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_to_mipi_csi2>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&ov5640 { + powerdown-gpios = <&csi2exp 1 GPIO_ACTIVE_HIGH>; + reset-gpios = <&csi2exp 0 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x31.dtso b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x31.dtso new file mode 100644 index 000000000000..f13c254d10c4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x31.dtso @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2023-2026 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include "imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640.dtsi" + +&mipi_csi_0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_to_mipi_csi2>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&ov5640 { + powerdown-gpios = <&csi2exp 2 GPIO_ACTIVE_HIGH>; + reset-gpios = <&csi2exp 3 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640.dtsi new file mode 100644 index 000000000000..4e56547e229e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640.dtsi @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2023-2026 Marek Vasut + */ + +#include +#include + +&{/} { + camera0_1v5_pwr: regulator-camera0-1v5 { + compatible = "regulator-fixed"; + regulator-name = "camera0-1v5-reg"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + camera0_1v8_pwr: regulator-camera0-1v8 { + compatible = "regulator-fixed"; + regulator-name = "camera0-1v8-reg"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + camera0_2v8_pwr: regulator-camera0-2v8 { + compatible = "regulator-fixed"; + regulator-name = "camera0-2v8-reg"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; +}; + +&i2cmuxed0 { + #address-cells = <1>; + #size-cells = <0>; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&clk IMX8MP_CLK_CLKOUT1>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MP_CLK_CLKOUT1_SEL>, + <&clk IMX8MP_CLK_CLKOUT1>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>, <24000000>; + AVDD-supply = <&camera0_2v8_pwr>; + DOVDD-supply = <&camera0_1v8_pwr>; + DVDD-supply = <&camera0_1v5_pwr>; + + port { + ov5640_to_mipi_csi2: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&isi_0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts index 6ad824a7e07e..a6a8262dc6be 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts @@ -165,7 +165,7 @@ i2c-mux@70 { #address-cells = <1>; #size-cells = <0>; - i2cmuxed0: i2c@0 { + i2c_dhpdk_panel: i2cmuxed0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtso b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtso new file mode 100644 index 000000000000..34b060cdeae1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtso @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2024-2026 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include "imx8mp-dhcom-overlay-panel-dpi.dtsi" +#include "imx8mp-dhcom-overlay-panel-ch101olhlwh.dtsi" +#include "imx8mp-pinfunc.h" + +&{/} { + lvds-encoder { + compatible = "onnn,fin3385", "lvds-encoder"; + pclk-sample = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_bridge_in: endpoint { + remote-endpoint = <&tc_bridge_out>; + }; + }; + + port@1 { + reg = <1>; + + lvds_bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; +}; + +&mipi_dsi { + /* + * This is DSIM PLL frequency, DSI HS clock lane frequency + * is half of the "samsung,burst-clock-frequency" value. + */ + samsung,burst-clock-frequency = <900000000>; +}; + +&panel_in { + remote-endpoint = <&lvds_bridge_out>; +}; + +&tc_bridge_out { + remote-endpoint = <&lvds_bridge_in>; +}; + +&touch_lvds { + pinctrl-0 = <&pinctrl_dhcom_b &pinctrl_dhcom_h>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; +}; + +&iomuxc { + /* + * The following DHCOM GPIOs are used on this board. + * Therefore, they have been removed from the list below. + * B: Touch controller #RESET + * H: Touch controller IRQ + * I: Yellow led + */ + pinctrl-0 = <&pinctrl_dhcom_a &pinctrl_dhcom_c &pinctrl_dhcom_d + &pinctrl_dhcom_e &pinctrl_dhcom_f &pinctrl_dhcom_g + &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l + &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o + &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r + &pinctrl_dhcom_s &pinctrl_dhcom_int>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-picoitx.dts b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-picoitx.dts index 703cf0fb3d2b..ac179765d562 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-picoitx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-picoitx.dts @@ -114,6 +114,9 @@ &hdmi_tx_phy { status = "disabled"; }; +i2c_dhpdk_panel: &i2c5 { +}; + &irqsteer_hdmi { status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som-overlay-eth1xfast.dtso b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som-overlay-eth1xfast.dtso new file mode 100644 index 000000000000..49cbf3e44601 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som-overlay-eth1xfast.dtso @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2023-2026 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include + +&eqos { /* First ethernet */ + pinctrl-0 = <&pinctrl_eqos_rmii>; + phy-handle = <ðphy0f>; + phy-mode = "rmii"; + + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, + <&clk IMX8MP_SYS_PLL2_100M>, + <&clk IMX8MP_SYS_PLL2_50M>; + assigned-clock-rates = <0>, <100000000>, <50000000>; +}; + +ðphy0g { /* Micrel KSZ9131RNXI */ + status = "disabled"; +}; + +ðphy0f { /* SMSC LAN8740Ai */ + status = "okay"; +}; + +&fec { /* Second ethernet -- HS connector not populated on 1x RMII PHY SoM */ + status = "disabled"; +}; + +/* No HS connector on this SoM variant, so no HDMI, PCIe and only USB HS. */ + +&hdmi_blk_ctrl { + status = "disabled"; +}; + +&hdmi_pvi { + status = "disabled"; +}; + +&hdmi_tx { + status = "disabled"; +}; + +&hdmi_tx_phy { + status = "disabled"; +}; + +&irqsteer_hdmi { + status = "disabled"; +}; + +&lcdif3 { + status = "disabled"; +}; + +&pcie_phy { + status = "disabled"; +}; + +&pcie { + status = "disabled"; +}; + +/* No WiFi/BT chipset on this SoM variant. */ +&uart2 { + bluetooth { + status = "disabled"; + }; +}; + +&usb_dwc3_0 { + maximum-speed = "high-speed"; +}; + +&usb_dwc3_1 { + maximum-speed = "high-speed"; +}; + +/* No WiFi/BT chipset on this SoM variant. */ +&usdhc1 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som-overlay-eth2xfast.dtso b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som-overlay-eth2xfast.dtso new file mode 100644 index 000000000000..e773a754477c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som-overlay-eth2xfast.dtso @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2023-2026 Marek Vasut + */ +#include "imx8mp-dhcom-som-overlay-eth1xfast.dtso" + +/* Dual RMII 100/Full Fast ethernet on this SoM variant. */ + +ðphy1f { /* SMSC LAN8740Ai */ + status = "okay"; +}; + +&fec { /* Second ethernet */ + pinctrl-0 = <&pinctrl_fec_rmii>; + phy-handle = <ðphy1f>; + phy-mode = "rmii"; + status = "okay"; + + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, + <&clk IMX8MP_SYS_PLL2_100M>, + <&clk IMX8MP_SYS_PLL2_50M>, + <&clk IMX8MP_SYS_PLL2_50M>; + assigned-clock-rates = <0>, <100000000>, <50000000>, <0>; +}; + +/* Resistive touch controller not populated on this one SoM variant. */ +&touch_som { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi index 0a6a60670f76..fdb5960f9c90 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2021-2022 Marek Vasut + * Copyright (C) 2021-2026 Marek Vasut */ #include "imx8mp.dtsi" @@ -398,7 +398,7 @@ channel@7 { /* Voltage over AIN3 and GND. */ }; }; - touchscreen@49 { + touch_som: touchscreen@49 { compatible = "ti,tsc2004"; reg = <0x49>; interrupts-extended = <&gpio4 0 IRQ_TYPE_EDGE_FALLING>; From 37f53f50b36f8bffffb6e69915240daa87e28ab0 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Wed, 22 Apr 2026 17:35:45 +0800 Subject: [PATCH 605/665] arm64: dts: imx8mm: Add Root Port node and PERST property Since describing the PCIe PERST# property under Host Bridge node is now deprecated, it is recommended to add it to the Root Port node, so creating the Root Port node and add the reset-gpios property in Root Port. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 5 +++++ arch/arm64/boot/dts/freescale/imx8mm.dtsi | 11 +++++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index 8be44eaf4e1e..e03aba825c18 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -533,6 +533,7 @@ &pcie_phy { &pcie0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; + /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, <&clk IMX8MM_CLK_PCIE1_AUX>; @@ -559,6 +560,10 @@ &pcie0_ep { status = "disabled"; }; +&pcie0_port0 { + reset-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; +}; + &sai2 { #sound-dai-cells = <0>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 4cc5ad01d0e2..5cf2998d396d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1370,6 +1370,17 @@ pcie0: pcie@33800000 { phys = <&pcie_phy>; phy-names = "pcie-phy"; status = "disabled"; + + pcie0_port0: pcie@0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_ep: pcie-ep@33800000 { From 396fbe9a028db8014f7566c0c023f53f3d0b77eb Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Wed, 22 Apr 2026 17:35:46 +0800 Subject: [PATCH 606/665] arm64: dts: imx8mp: Add Root Port node and PERST property Since describing the PCIe PERST# property under Host Bridge node is now deprecated, it is recommended to add it to the Root Port node, so creating the Root Port node and add the reset-gpios property in Root Port. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 5 +++++ arch/arm64/boot/dts/freescale/imx8mp.dtsi | 11 +++++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 2feb5b18645c..a7f3acdc36d1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -770,6 +770,7 @@ &pcie_phy { &pcie0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; + /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; vpcie-supply = <®_pcie0>; vpcie3v3aux-supply = <®_pcie0>; @@ -783,6 +784,10 @@ &pcie0_ep { status = "disabled"; }; +&pcie0_port0 { + reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; +}; + &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 90d7bb8f5619..5ce2825182fd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -2265,6 +2265,17 @@ pcie0: pcie: pcie@33800000 { phys = <&pcie_phy>; phy-names = "pcie-phy"; status = "disabled"; + + pcie0_port0: pcie@0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_ep: pcie_ep: pcie-ep@33800000 { From 2f42bbebb7bef302b190f8965b7a675268567aa1 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Wed, 22 Apr 2026 17:35:47 +0800 Subject: [PATCH 607/665] arm64: dts: imx8mq: Add Root Port node and PERST property Since describing the PCIe PERST# property under Host Bridge node is now deprecated, it is recommended to add it to the Root Port node, so creating the Root Port node and add the reset-gpios property in Root Port. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 10 +++++++++ arch/arm64/boot/dts/freescale/imx8mq.dtsi | 22 ++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index d48f901487d4..e7d87ea81b69 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -369,6 +369,7 @@ mipi_dsi_out: endpoint { &pcie0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; + /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>; clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, <&pcie0_refclk>, @@ -389,9 +390,14 @@ &pcie0_ep { status = "disabled"; }; +&pcie0_port0 { + reset-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>; +}; + &pcie1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie1>; + /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, <&pcie0_refclk>, @@ -414,6 +420,10 @@ &pcie1_ep { status = "disabled"; }; +&pcie1_port0 { + reset-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; +}; + &pgc_gpu { power-supply = <&sw1a_reg>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 6a25e219832c..e60872aeeb49 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1768,6 +1768,17 @@ pcie0: pcie@33800000 { assigned-clock-rates = <250000000>, <100000000>, <10000000>; status = "disabled"; + + pcie0_port0: pcie@0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_ep: pcie-ep@33800000 { @@ -1846,6 +1857,17 @@ pcie1: pcie@33c00000 { assigned-clock-rates = <250000000>, <100000000>, <10000000>; status = "disabled"; + + pcie1_port0: pcie@0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_ep: pcie-ep@33c00000 { From 5e5bcc5a80a2d802e7d9d1523682b9e054cbbfcf Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Wed, 22 Apr 2026 17:35:48 +0800 Subject: [PATCH 608/665] arm64: dts: imx8dxl/qm/qxp: Add Root Port node and PERST property Since describing the PCIe PERST# property under Host Bridge node is now deprecated, it is recommended to add it to the Root Port node, so creating the Root Port node and add the reset-gpios property in Root Port. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8-ss-hsio.dtsi | 11 ++++++++++ arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 5 +++++ arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 10 +++++++++ .../boot/dts/freescale/imx8qm-ss-hsio.dtsi | 22 +++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 5 +++++ 5 files changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi index 469de8b536b5..009990b2e559 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi @@ -78,6 +78,17 @@ pcieb: pcie@5f010000 { power-domains = <&pd IMX_SC_R_PCIE_B>; fsl,max-link-speed = <3>; status = "disabled"; + + pcieb_port0: pcie@0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcieb_ep: pcie-ep@5f010000 { diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index 441e00903029..78e8d41e6791 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -675,6 +675,7 @@ &pcie0 { phy-names = "pcie-phy"; pinctrl-0 = <&pinctrl_pcieb>; pinctrl-names = "default"; + /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; vpcie-supply = <®_pcieb>; vpcie3v3aux-supply = <®_pcieb>; @@ -689,6 +690,10 @@ &pcie0_ep { status = "disabled"; }; +&pcieb_port0 { + reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; +}; + &sai0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai0>; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index 011a89d85961..f706c86137c0 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -810,6 +810,7 @@ &pciea { phy-names = "pcie-phy"; pinctrl-0 = <&pinctrl_pciea>; pinctrl-names = "default"; + /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; vpcie-supply = <®_pciea>; vpcie3v3aux-supply = <®_pciea>; @@ -817,15 +818,24 @@ &pciea { status = "okay"; }; +&pciea_port0 { + reset-gpios = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; +}; + &pcieb { phys = <&hsio_phy 1 PHY_TYPE_PCIE 1>; phy-names = "pcie-phy"; pinctrl-0 = <&pinctrl_pcieb>; pinctrl-names = "default"; + /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>; status = "disabled"; }; +&pcieb_port0 { + reset-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>; +}; + &qm_pwm_lvds0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm_lvds0>; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi index f2c94cdb682b..2e4fbfe0ca16 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi @@ -41,6 +41,17 @@ pcie0: pciea: pcie@5f000000 { power-domains = <&pd IMX_SC_R_PCIE_A>; fsl,max-link-speed = <3>; status = "disabled"; + + pciea_port0: pcie@0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_ep: pciea_ep: pcie-ep@5f000000 { @@ -91,6 +102,17 @@ pcie1: pcieb: pcie@5f010000 { power-domains = <&pd IMX_SC_R_PCIE_B>; fsl,max-link-speed = <3>; status = "disabled"; + + pcieb_port0: pcie@0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; sata: sata@5f020000 { diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index c07138055229..2af32eca612a 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -730,6 +730,7 @@ &pcie0 { phy-names = "pcie-phy"; pinctrl-0 = <&pinctrl_pcieb>; pinctrl-names = "default"; + /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; vpcie-supply = <®_pcieb>; vpcie3v3aux-supply = <®_pcieb>; @@ -745,6 +746,10 @@ &pcie0_ep { status = "disabled"; }; +&pcieb_port0 { + reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; +}; + &scu_key { status = "okay"; }; From 7db62ff5f4f4388ec2d07c4d460840557cb0c7ab Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Wed, 22 Apr 2026 17:35:49 +0800 Subject: [PATCH 609/665] arm64: dts: imx95: Add Root Port node and PERST property Since describing the PCIe PERST# property under Host Bridge node is now deprecated, it is recommended to add it to the Root Port node, so creating the Root Port node and add the reset-gpios property in Root Port. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- .../boot/dts/freescale/imx95-15x15-evk.dts | 5 +++++ .../boot/dts/freescale/imx95-19x19-evk.dts | 10 +++++++++ arch/arm64/boot/dts/freescale/imx95.dtsi | 22 +++++++++++++++++++ 3 files changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts index e4649d7f9122..7d820a0f80b2 100644 --- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts @@ -553,6 +553,7 @@ &netcmix_blk_ctrl { &pcie0 { pinctrl-0 = <&pinctrl_pcie0>; pinctrl-names = "default"; + /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&gpio5 13 GPIO_ACTIVE_LOW>; vpcie-supply = <®_m2_pwr>; vpcie3v3aux-supply = <®_m2_pwr>; @@ -567,6 +568,10 @@ &pcie0_ep { status = "disabled"; }; +&pcie0_port0 { + reset-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; +}; + &sai1 { assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts index 49400bc9ba91..2e463bc7c601 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -540,6 +540,7 @@ &netc_timer { &pcie0 { pinctrl-0 = <&pinctrl_pcie0>; pinctrl-names = "default"; + /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>; vpcie-supply = <®_pcie0>; vpcie3v3aux-supply = <®_pcie0>; @@ -554,9 +555,14 @@ &pcie0_ep { status = "disabled"; }; +&pcie0_port0 { + reset-gpios = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>; +}; + &pcie1 { pinctrl-0 = <&pinctrl_pcie1>; pinctrl-names = "default"; + /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>; vpcie-supply = <®_slot_pwr>; vpcie3v3aux-supply = <®_slot_pwr>; @@ -570,6 +576,10 @@ &pcie1_ep { status = "disabled"; }; +&pcie1_port0 { + reset-gpios = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>; +}; + &sai1 { #sound-dai-cells = <0>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 3e35c956a4d7..d2aa6e543a09 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -1974,6 +1974,17 @@ pcie0: pcie@4c300000 { iommu-map-mask = <0x1ff>; fsl,max-link-speed = <3>; status = "disabled"; + + pcie0_port0: pcie@0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_ep: pcie-ep@4c300000 { @@ -2051,6 +2062,17 @@ pcie1: pcie@4c380000 { iommu-map-mask = <0x1ff>; fsl,max-link-speed = <3>; status = "disabled"; + + pcie1_port0: pcie@0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_ep: pcie-ep@4c380000 { From 95f5bc1632ab8f243e517357b5da0dd28d1c6c92 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Wed, 13 May 2026 15:25:31 +0200 Subject: [PATCH 610/665] arm64: dts: imx8mp-kontron: Reduce EERAM SPI clock frequency There is an onboard level shifter for the SPI signals that causes additional propagation delay and renders the SPI transmission unreliable at 20 MHz. Reduce the clock frequency to a safe value. Fixes: 946ab10e3f40 ("arm64: dts: Add support for Kontron OSM-S i.MX8MP SoM and BL carrier board") Signed-off-by: Frieder Schrempf Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts b/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts index 0924ac50fd2d..75ae46642782 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts @@ -63,7 +63,7 @@ &ecspi2 { eeram@0 { compatible = "microchip,48l640"; reg = <0>; - spi-max-frequency = <20000000>; + spi-max-frequency = <16000000>; }; }; From afb61965f3dab1505574e9a9b212bb2f367ec5dd Mon Sep 17 00:00:00 2001 From: Khristine Andreea Barbulescu Date: Mon, 18 May 2026 08:35:47 +0200 Subject: [PATCH 611/665] arm64: dts: s32g: add PIT support for s32g2 and s32g3 Add PIT0 and PIT1 for S32G2 and S32G3 SoCs Signed-off-by: Khristine Andreea Barbulescu Reviewed-by: Enric Balletbo i Serra Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 20 +++++++++++++++++++- arch/arm64/boot/dts/freescale/s32g3.dtsi | 20 +++++++++++++++++++- 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index 51d00dac12de..f508b776b4dd 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -3,7 +3,7 @@ * NXP S32G2 SoC family * * Copyright (c) 2021 SUSE LLC - * Copyright 2017-2021, 2024-2025 NXP + * Copyright 2017-2021, 2024-2026 NXP */ #include @@ -417,6 +417,15 @@ edma0: dma-controller@40144000 { clock-names = "dmamux0", "dmamux1"; }; + pit0: timer@40188000 { + compatible = "nxp,s32g2-pit"; + reg = <0x40188000 0x3000>; + interrupts = ; + clocks = <&clks 61>; + clock-names = "pit"; + status = "disabled"; + }; + can0: can@401b4000 { compatible = "nxp,s32g2-flexcan"; reg = <0x401b4000 0xa000>; @@ -622,6 +631,15 @@ edma1: dma-controller@40244000 { clock-names = "dmamux0", "dmamux1"; }; + pit1: timer@40288000 { + compatible = "nxp,s32g2-pit"; + reg = <0x40288000 0x3000>; + interrupts = ; + clocks = <&clks 61>; + clock-names = "pit"; + status = "disabled"; + }; + can2: can@402a8000 { compatible = "nxp,s32g2-flexcan"; reg = <0x402a8000 0xa000>; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index e314f3c7d61d..efe5398e1240 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright 2021-2025 NXP + * Copyright 2021-2026 NXP * * Authors: Ghennadi Procopciuc * Ciprian Costea @@ -475,6 +475,15 @@ edma0: dma-controller@40144000 { clock-names = "dmamux0", "dmamux1"; }; + pit0: pit@40188000 { + compatible = "nxp,s32g3-pit", "nxp,s32g2-pit"; + reg = <0x40188000 0x3000>; + interrupts = ; + clocks = <&clks 61>; + clock-names = "pit"; + status = "disabled"; + }; + can0: can@401b4000 { compatible = "nxp,s32g3-flexcan", "nxp,s32g2-flexcan"; @@ -693,6 +702,15 @@ edma1: dma-controller@40244000 { clock-names = "dmamux0", "dmamux1"; }; + pit1: pit@40288000 { + compatible = "nxp,s32g3-pit", "nxp,s32g2-pit"; + reg = <0x40288000 0x3000>; + interrupts = ; + clocks = <&clks 61>; + clock-names = "pit"; + status = "disabled"; + }; + can2: can@402a8000 { compatible = "nxp,s32g3-flexcan", "nxp,s32g2-flexcan"; From 65c16cd0def939e86552f1b22ffdbd63b69eebe4 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Tue, 19 May 2026 13:54:31 +0800 Subject: [PATCH 612/665] arm64: dts: imx943-evk: Fix PCIe EP vpcie-supply The vpcie-supply property should reference the regulator that controls the actual M.2 power supply, not the W_DISABLE1# signal. On imx943-evk: - reg_m2_wlan controls M.2 W_DISABLE1# signal - reg_m2_pwr controls the actual M.2 power supply Fix the vpcie-supply to use reg_m2_pwr for proper power control in PCIe endpoint mode. Fixes: 1962c596d51c ("arm64: dts: imx943-evk: Add pcie[0,1] and pcie-ep[0,1] support") Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx943-evk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts index fe4fc512d95d..426b5a4ec47c 100644 --- a/arch/arm64/boot/dts/freescale/imx943-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts @@ -1043,7 +1043,7 @@ &pcie0 { &pcie0_ep { pinctrl-0 = <&pinctrl_pcie0>; pinctrl-names = "default"; - vpcie-supply = <®_m2_wlan>; + vpcie-supply = <®_m2_pwr>; status = "disabled"; }; From 7ca25f0fa0a8421bdb4c7fc9125a6fe58040ca31 Mon Sep 17 00:00:00 2001 From: Khristine Andreea Barbulescu Date: Thu, 14 May 2026 10:26:39 +0200 Subject: [PATCH 613/665] arm64: dts: s32g: add SAR ADC support for s32g2 and s32g3 Add ADC0 and ADC1 for S32G2 and S32G3 SoCs. Signed-off-by: Khristine Andreea Barbulescu Reviewed-by: Enric Balletbo i Serra Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 20 ++++++++++++++++++++ arch/arm64/boot/dts/freescale/s32g3.dtsi | 20 ++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index f508b776b4dd..a1f33197b4b0 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -563,6 +563,16 @@ i2c2: i2c@401ec000 { status = "disabled"; }; + adc0: adc@401f8000 { + compatible = "nxp,s32g2-sar-adc"; + reg = <0x401f8000 0x1000>; + interrupts = ; + clocks = <&clks 0x41>; + dmas = <&edma0 0 32>; + dma-names = "rx"; + status = "disabled"; + }; + swt4: watchdog@40200000 { compatible = "nxp,s32g2-swt"; reg = <0x40200000 0x1000>; @@ -735,6 +745,16 @@ i2c4: i2c@402dc000 { status = "disabled"; }; + adc1: adc@402e8000 { + compatible = "nxp,s32g2-sar-adc"; + reg = <0x402e8000 0x1000>; + interrupts = ; + clocks = <&clks 0x41>; + dmas = <&edma1 1 32>; + dma-names = "rx"; + status = "disabled"; + }; + usdhc0: mmc@402f0000 { compatible = "nxp,s32g2-usdhc"; reg = <0x402f0000 0x1000>; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index efe5398e1240..42646b2d16b0 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -626,6 +626,16 @@ i2c2: i2c@401ec000 { status = "disabled"; }; + adc0: adc@401f8000 { + compatible = "nxp,s32g3-sar-adc", "nxp,s32g2-sar-adc"; + reg = <0x401f8000 0x1000>; + interrupts = ; + clocks = <&clks 0x41>; + dmas = <&edma0 0 32>; + dma-names = "rx"; + status = "disabled"; + }; + swt4: watchdog@40200000 { compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; reg = <0x40200000 0x1000>; @@ -810,6 +820,16 @@ i2c4: i2c@402dc000 { status = "disabled"; }; + adc1: adc@402e8000 { + compatible = "nxp,s32g3-sar-adc", "nxp,s32g2-sar-adc"; + reg = <0x402e8000 0x1000>; + interrupts = ; + clocks = <&clks 0x41>; + dmas = <&edma1 1 32>; + dma-names = "rx"; + status = "disabled"; + }; + usdhc0: mmc@402f0000 { compatible = "nxp,s32g3-usdhc", "nxp,s32g2-usdhc"; From 2521addd5df7e8ab805622d4a0eff9735a45fa11 Mon Sep 17 00:00:00 2001 From: Alice Guo Date: Tue, 19 May 2026 18:55:15 +0800 Subject: [PATCH 614/665] arm64: dts: imx94: fix DDR PMU interrupt number The DDR Performance Monitor node was added with incorrect interrupt number 91, which actually belongs to the wdog4 watchdog. Fix it to the correct interrupt number 374. Fixes: e918e5f847b3 ("arm64: dts: imx94: add DDR Perf Monitor node") Signed-off-by: Alice Guo Reviewed-by: Xu Yang Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx94.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi index 589f4aadc742..03889092eaf5 100644 --- a/arch/arm64/boot/dts/freescale/imx94.dtsi +++ b/arch/arm64/boot/dts/freescale/imx94.dtsi @@ -1569,7 +1569,7 @@ netc_emdio: mdio@18,0 { ddr-pmu@4e090dc0 { compatible = "fsl,imx94-ddr-pmu", "fsl,imx93-ddr-pmu"; reg = <0x0 0x4e090dc0 0x0 0x200>; - interrupts = ; + interrupts = ; }; }; }; From 06d40112780e79631537496f37958087ce2704f7 Mon Sep 17 00:00:00 2001 From: Alice Guo Date: Tue, 19 May 2026 18:55:16 +0800 Subject: [PATCH 615/665] arm64: dts: freescale: add bootph-all to watchdog nodes for i.MX platforms Add the bootph-all property to ULP watchdog nodes across multiple i.MX SoC device trees, ensuring the watchdog is available during all boot phases. The affected watchdog nodes are: - imx8ulp: wdog3 - imx91/93: wdog3, wdog4, wdog5 - imx94: wdog3 - imx95: wdog3 - imx952: wdog3 Signed-off-by: Alice Guo Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 1 + arch/arm64/boot/dts/freescale/imx91_93_common.dtsi | 3 +++ arch/arm64/boot/dts/freescale/imx94.dtsi | 12 ++++++++++++ arch/arm64/boot/dts/freescale/imx95.dtsi | 11 +++++++++++ arch/arm64/boot/dts/freescale/imx952.dtsi | 11 +++++++++++ 5 files changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index 17caf3703fb1..c6d1bb9edf38 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -302,6 +302,7 @@ wdog3: watchdog@292a0000 { assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>; assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>; timeout-sec = <40>; + bootph-all; }; cgc1: clock-controller@292c0000 { diff --git a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi index 46a5d2df074d..a1a7e6a0571b 100644 --- a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi +++ b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi @@ -525,6 +525,7 @@ wdog3: watchdog@42490000 { clocks = <&clk IMX93_CLK_WDOG3_GATE>; timeout-sec = <40>; status = "disabled"; + bootph-all; }; wdog4: watchdog@424a0000 { @@ -534,6 +535,7 @@ wdog4: watchdog@424a0000 { clocks = <&clk IMX93_CLK_WDOG4_GATE>; timeout-sec = <40>; status = "disabled"; + bootph-all; }; wdog5: watchdog@424b0000 { @@ -543,6 +545,7 @@ wdog5: watchdog@424b0000 { clocks = <&clk IMX93_CLK_WDOG5_GATE>; timeout-sec = <40>; status = "disabled"; + bootph-all; }; tpm3: pwm@424e0000 { diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi index 03889092eaf5..a6cb5a6e848b 100644 --- a/arch/arm64/boot/dts/freescale/imx94.dtsi +++ b/arch/arm64/boot/dts/freescale/imx94.dtsi @@ -1290,6 +1290,18 @@ wdog3: watchdog@49220000 { timeout-sec = <40>; fsl,ext-reset-output; status = "disabled"; + bootph-all; + }; + + wdog4: watchdog@49230000 { + compatible = "fsl,imx94-wdt", "fsl,imx93-wdt"; + reg = <0x49230000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; + timeout-sec = <40>; + fsl,ext-reset-output; + status = "disabled"; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index d2aa6e543a09..b4ca507b650a 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -795,6 +795,17 @@ wdog3: watchdog@42490000 { clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; timeout-sec = <40>; status = "disabled"; + bootph-all; + }; + + wdog4: watchdog@424a0000 { + compatible = "fsl,imx93-wdt"; + reg = <0x424a0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; + timeout-sec = <40>; + status = "disabled"; + bootph-all; }; tpm3: pwm@424e0000 { diff --git a/arch/arm64/boot/dts/freescale/imx952.dtsi b/arch/arm64/boot/dts/freescale/imx952.dtsi index 8d65c380e1c4..020de00e8285 100644 --- a/arch/arm64/boot/dts/freescale/imx952.dtsi +++ b/arch/arm64/boot/dts/freescale/imx952.dtsi @@ -371,6 +371,17 @@ wdog3: watchdog@420b0000 { clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; timeout-sec = <40>; status = "disabled"; + bootph-all; + }; + + wdog4: watchdog@420c0000 { + compatible = "fsl,imx93-wdt"; + reg = <0x420c0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; + timeout-sec = <40>; + status = "disabled"; + bootph-all; }; tpm3: pwm@42100000 { From dcb42d491e9e7efcac85f780c809d457959b8538 Mon Sep 17 00:00:00 2001 From: Joy Zou Date: Tue, 19 May 2026 19:15:15 +0800 Subject: [PATCH 616/665] arm64: dts: imx91-9x9-qsb: remove unused property clock-frequency from mdio node The clock-frequency property is not implemented. Remove it to clean up the device tree. Signed-off-by: Joy Zou Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts b/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts index 1239bbf579da..9cbfe57be2d3 100644 --- a/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts +++ b/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts @@ -79,7 +79,6 @@ mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; - clock-frequency = <5000000>; ethphy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; From 3086c0a73ef9b45b75e602c05bad74ee7339a489 Mon Sep 17 00:00:00 2001 From: Joy Zou Date: Tue, 19 May 2026 19:15:16 +0800 Subject: [PATCH 617/665] arm64: dts: imx91-9x9-qsb: add pinctrl for wdog3 reset The wdog3 node enables fsl,ext-reset-output to assert an external reset signal upon watchdog timeout, but lacks pinctrl configuration for the physical pad. Without proper pinctrl settings, which could cause the watchdog timeout to fail to reset the board hardware. Add pinctrl configuration to ensure the pin is properly muxed and configured for external watchdog reset functionality. Signed-off-by: Joy Zou Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts b/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts index 9cbfe57be2d3..62549a6de1b6 100644 --- a/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts +++ b/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts @@ -230,6 +230,12 @@ MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e >; }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e + >; + }; }; &lpi2c1 { @@ -419,6 +425,8 @@ &usdhc2 { }; &wdog3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; fsl,ext-reset-output; status = "okay"; }; From 5b9c67b3237c52f55ada7bf1b79909768b12a1b8 Mon Sep 17 00:00:00 2001 From: Joy Zou Date: Tue, 19 May 2026 19:15:17 +0800 Subject: [PATCH 618/665] arm64: dts: imx91-11x11-evk: add pinctrl for wdog3 reset The wdog3 node enables fsl,ext-reset-output to assert an external reset signal upon watchdog timeout, but lacks pinctrl configuration for the physical pad. Without proper pinctrl settings, which could cause the watchdog timeout to fail to reset the board hardware. Add pinctrl configuration to ensure the pin is properly muxed and configured for external watchdog reset functionality. Signed-off-by: Joy Zou Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts index de524f1921de..3fbdcb87a2f3 100644 --- a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts @@ -586,6 +586,8 @@ &usdhc3 { }; &wdog3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; fsl,ext-reset-output; status = "okay"; }; @@ -947,4 +949,10 @@ MX91_PAD_SD3_DATA2__GPIO3_IO24 0x31e MX91_PAD_SD3_DATA3__GPIO3_IO25 0x31e >; }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e + >; + }; }; From 4503ca234c1c5995609f77ce41e66d0f8e08cbfd Mon Sep 17 00:00:00 2001 From: Joy Zou Date: Tue, 19 May 2026 19:15:18 +0800 Subject: [PATCH 619/665] arm64: dts: imx91-11x11-evk: add reset gpios for ethernet PHYs Both the PHYs of the EQOS interface and the FEC interface are supported to be reset by I2C GPIO expander. So add the support to reset PHYs. Signed-off-by: Joy Zou Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts index 3fbdcb87a2f3..5716febb5a50 100644 --- a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts @@ -198,6 +198,9 @@ mdio { ethphy1: ethernet-phy@1 { reg = <1>; + reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; realtek,clkout-disable; }; }; @@ -219,6 +222,9 @@ mdio { ethphy2: ethernet-phy@2 { reg = <2>; + reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; realtek,clkout-disable; }; }; From c2f2b0e494a7bfa97081946ee4fad218b4cdf7bc Mon Sep 17 00:00:00 2001 From: Joy Zou Date: Tue, 19 May 2026 19:15:19 +0800 Subject: [PATCH 620/665] arm64: dts: imx91-9x9-qsb: add reset gpios for ethernet PHYs The PHYs of the EQOS interface is supported to be reset by I2C GPIO expander. So add the support to reset PHYs. Signed-off-by: Joy Zou Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts b/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts index 62549a6de1b6..ea8cf14e0bc6 100644 --- a/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts +++ b/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts @@ -83,6 +83,9 @@ mdio { ethphy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; + reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; realtek,clkout-disable; }; }; From dbecf38e60d4ef08c59836b7bc16e8efca01fc47 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Wed, 20 May 2026 15:22:28 +0800 Subject: [PATCH 621/665] arm64: dts: imx95: Correct PCIe outbound address space configuration Fix the PCIe outbound memory ranges for both pcie0 and pcie1 controllers on i.MX95. The memory window size was incorrectly set to 256MB during initial bring-up, but the hardware supports up to 4GB of outbound address space per controller. Additionally, the ECAM region cannot be mapped as I/O space. Use a memory-mapped region for I/O space instead, and relocate the 1MB I/O region to immediately follow the memory region at offset 0xf0000000 within each window. Update the outbound address space layout per controller as follows: - 3.5GB 64-bit prefetchable memory - 256MB 32-bit non-prefetchable memory - 1MB I/O Fixes: 3b1d5deb29ff ("arm64: dts: imx95: add pcie[0,1] and pcie-ep[0,1] support") Signed-off-by: Richard Zhu Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index b4ca507b650a..d6c549c16047 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -1947,8 +1947,9 @@ pcie0: pcie@4c300000 { <0 0x4c360000 0 0x10000>, <0 0x4c340000 0 0x4000>; reg-names = "dbi", "config", "atu", "app"; - ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>, - <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>; + ranges = <0x43000000 0x9 0x00000000 0x9 0x00000000 0x0 0xe0000000>, + <0x82000000 0x0 0xe0000000 0x9 0xe0000000 0x0 0x10000000>, + <0x81000000 0x0 0x00000000 0x9 0xf0000000 0x0 0x00100000>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -2033,8 +2034,9 @@ pcie1: pcie@4c380000 { <0 0x4c3e0000 0 0x10000>, <0 0x4c3c0000 0 0x4000>; reg-names = "dbi", "config", "atu", "app"; - ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>, - <0x82000000 0 0x10000000 0xa 0x10000000 0 0x10000000>; + ranges = <0x43000000 0xa 0x00000000 0xa 0x00000000 0x0 0xe0000000>, + <0x82000000 0x0 0xe0000000 0xa 0xe0000000 0x0 0x10000000>, + <0x81000000 0x0 0x00000000 0xa 0xf0000000 0x0 0x00100000>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; From 9ed3013970900fc201379b881fcb7e1cadd572c4 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Sun, 24 May 2026 16:54:40 +0200 Subject: [PATCH 622/665] arm64: dts: lx2160a-rev2: extend 32-bit and add 64-bit pci regions LX2160 SoC PCIe controller supports 64-bit memory regions up to 16GB, 32-bit regions up to 3GB and 16-bit regions up to 64k. For each PCIe controller: - extend the existing 32-bit regions to 3GB size - add 64-bit region See [1] and [2] for boot messages showing ranges before and after. On LX2160A Silicon revision 1, the pcie driver fails to program atu for ranges larger than 4GB [3]. Therefore changes are limited to revision 2. Similar memory allocation with similar flags was tested with UEFI and ACPI on pcie3 and pcie5, on a variety of nxp vendor fork versions. Fixes allocation of large, and 64-bit BARs as requested by many PCI cards especially graphics processors or AI accelerators, e.g.: [ 2.941187] pci 0000:01:00.0: BAR 0: no space for [mem size 0x200000000 64bit pref] [ 2.948834] pci 0000:01:00.0: BAR 0: failed to assign [mem size 0x200000000 64bit pref] [1] example of new allocations (pcie5): [ 1.182745] layerscape-pcie 3800000.pcie: host bridge /soc/pcie@3800000 ranges: [ 1.182760] layerscape-pcie 3800000.pcie: MEM 0xa400000000..0xa7ffffffff -> 0xa400000000 [ 1.182771] layerscape-pcie 3800000.pcie: MEM 0xa040000000..0xa0ffffffff -> 0x0040000000 [ 1.182778] layerscape-pcie 3800000.pcie: IO 0xa000010000..0xa00001ffff -> 0x0000000000 [ 1.183642] layerscape-pcie 3800000.pcie: iATU: unroll F, 256 ob, 24 ib, align 4K, limit 4G [ 1.385429] layerscape-pcie 3800000.pcie: PCIe Gen.3 x8 link up [ 1.385481] layerscape-pcie 3800000.pcie: PCI host bridge to bus 0001:00 [ 1.385484] pci_bus 0001:00: root bus resource [bus 00-ff] [ 1.385488] pci_bus 0001:00: root bus resource [mem 0xa400000000-0xa7ffffffff pref] [ 1.385491] pci_bus 0001:00: root bus resource [mem 0xa040000000-0xa0ffffffff] (bus address [0x40000000-0xffffffff]) [ 1.385494] pci_bus 0001:00: root bus resource [io 0x10000-0x1ffff] (bus address [0x0000-0xffff]) [ 1.385516] pci 0001:00:00.0: [1957:8d80] type 01 class 0x060400 PCIe Root Port [ 1.385538] pci 0001:00:00.0: PCI bridge to [bus 01-ff] [ 1.385544] pci 0001:00:00.0: bridge window [io 0x11000-0x11fff] [ 1.385548] pci 0001:00:00.0: bridge window [mem 0xa040000000-0xa0502fffff] [ 1.385605] pci 0001:00:00.0: supports D1 D2 [ 1.385607] pci 0001:00:00.0: PME# supported from D0 D1 D2 D3hot [ 1.386778] pci 0001:01:00.0: [1002:6995] type 00 class 0x030000 PCIe Legacy Endpoint [ 1.387336] pci 0001:01:00.0: BAR 0 [mem 0xa040000000-0xa04fffffff 64bit pref] [ 1.387368] pci 0001:01:00.0: BAR 2 [mem 0xa050000000-0xa0501fffff 64bit pref] [ 1.387385] pci 0001:01:00.0: BAR 4 [io 0x11000-0x110ff] [ 1.387402] pci 0001:01:00.0: BAR 5 [mem 0xa050200000-0xa05023ffff] [ 1.387418] pci 0001:01:00.0: ROM [mem 0xa050240000-0xa05025ffff pref] [ 1.387493] pci 0001:01:00.0: enabling Extended Tags [ 1.388960] pci 0001:01:00.0: supports D1 D2 [2] example of previous allocations (pcie5): [ 1.716744] layerscape-pcie 3800000.pcie: host bridge /soc/pcie@3800000 ranges: [ 1.724060] layerscape-pcie 3800000.pcie: MEM 0xa040000000..0xa07fffffff -> 0x0040000000 [ 1.733277] layerscape-pcie 3800000.pcie: iATU: unroll F, 256 ob, 24 ib, align 4K, limit 4G [ 1.836220] layerscape-pcie 3800000.pcie: PCIe Gen.3 x8 link up [ 1.842186] layerscape-pcie 3800000.pcie: PCI host bridge to bus 0001:00 [ 1.848883] pci_bus 0001:00: root bus resource [bus 00-ff] [ 1.854363] pci_bus 0001:00: root bus resource [mem 0xa040000000-0xa07fffffff] (bus address [0x40000000-0x7fffffff]) [ 1.864892] pci 0001:00:00.0: [1957:8d80] type 01 class 0x060400 PCIe Root Port [ 1.872216] pci 0001:00:00.0: PCI bridge to [bus 01-ff] [ 1.877438] pci 0001:00:00.0: bridge window [io 0x1000-0x1fff] [ 1.883526] pci 0001:00:00.0: bridge window [mem 0xa040000000-0xa0502fffff] [3] error programming atu beyond 4GB: [ 1.716762] layerscape-pcie 3800000.pcie: host bridge /soc/pcie@3800000 ranges: [ 1.724080] layerscape-pcie 3800000.pcie: MEM 0xa400000000..0xa7ffffffff -> 0xa400000000 [ 1.732615] layerscape-pcie 3800000.pcie: MEM 0xa040000000..0xa0ffffffff -> 0x0040000000 [ 1.741142] layerscape-pcie 3800000.pcie: IO 0xa010000000..0xa01000ffff -> 0x0000000000 [ 1.750379] layerscape-pcie 3800000.pcie: iATU: unroll F, 256 ob, 24 ib, align 4K, limit 4G [ 1.759089] layerscape-pcie 3800000.pcie: Failed to set MEM range [mem 0xa400000000-0xa7ffffffff flags 0x2200] [ 1.769089] layerscape-pcie 3800000.pcie: probe with driver layerscape-pcie failed with error -22 [4] pci bootloaderp atching related errors with IORESOURCE_MEM_64 flag: [ 0.967809] layerscape-pcie 3800000.pcie: host bridge /soc/pcie@3800000 ranges: [ 0.967830] layerscape-pcie 3800000.pcie: MEM 0xa400000000..0xa7ffffffff -> 0xa400000000 [ 0.967842] layerscape-pcie 3800000.pcie: MEM 0xa040000000..0xa0ffffffff -> 0x0040000000 [ 0.967849] layerscape-pcie 3800000.pcie: IO 0xa000010000..0xa00001ffff -> 0x0000000000 [ 1.169315] pci 0000:01:00.0: [8086:1572] type 00 class 0x020000 PCIe Endpoint [ 1.169733] pci 0000:01:00.0: BAR 0 [mem 0x00000000-0x00ffffff 64bit pref] [ 1.169771] pci 0000:01:00.0: BAR 3 [mem 0x00000000-0x00007fff 64bit pref] [ 1.169796] pci 0000:01:00.0: ROM [mem 0x00000000-0x0007ffff pref] [ 1.173389] OF: /soc/pcie@3800000: no msi-map translation for id 0x100 on (null) [ 1.173515] OF: /soc/pcie@3800000: no iommu-map translation for id 0x100 on (null) Signed-off-by: Josua Mayer Signed-off-by: Frank Li --- .../boot/dts/freescale/fsl-lx2160a-rev2.dtsi | 48 ++++++++++++++----- 1 file changed, 36 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi index f54005e37924..3570399f9b21 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi @@ -14,8 +14,12 @@ &pcie1 { 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 - 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; + ranges = /* 16-Bit IO Window */ + <0x81000000 0x00 0x00000000 0x80 0x00010000 0x00 0x00010000>, + /* 32-Bit - non-prefetchable */ + <0x82000000 0x00 0x40000000 0x80 0x40000000 0x00 0xc0000000>, + /* 64-Bit - prefetchable - 16GB */ + <0xC3000000 0x84 0x00000000 0x84 0x00000000 0x04 0x00000000>; interrupts = ; interrupt-names = "intr"; @@ -30,8 +34,12 @@ &pcie2 { 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 - 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; + ranges = /* 16-Bit IO Window */ + <0x81000000 0x00 0x00000000 0x88 0x00010000 0x00 0x00010000>, + /* 32-Bit - non-prefetchable */ + <0x82000000 0x00 0x40000000 0x88 0x40000000 0x00 0xc0000000>, + /* 64-Bit - prefetchable - 16GB */ + <0xC3000000 0x8c 0x00000000 0x8c 0x00000000 0x04 0x00000000>; interrupts = ; interrupt-names = "intr"; @@ -46,8 +54,12 @@ &pcie3 { 0x90 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - ranges = <0x81000000 0x0 0x00000000 0x90 0x00010000 0x0 0x00010000 - 0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; + ranges = /* 16-Bit IO Window */ + <0x81000000 0x00 0x00000000 0x90 0x00010000 0x00 0x00010000>, + /* 32-Bit - non-prefetchable */ + <0x82000000 0x00 0x40000000 0x90 0x40000000 0x00 0xc0000000>, + /* 64-Bit - prefetchable - 16GB */ + <0xC3000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; interrupts = ; interrupt-names = "intr"; @@ -63,8 +75,12 @@ &pcie4 { 0x98 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - ranges = <0x81000000 0x0 0x00000000 0x98 0x00010000 0x0 0x00010000 - 0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; + ranges = /* 16-Bit IO Window */ + <0x81000000 0x00 0x00000000 0x98 0x00010000 0x00 0x00010000>, + /* 32-Bit - non-prefetchable */ + <0x82000000 0x00 0x40000000 0x98 0x40000000 0x00 0xc0000000>, + /* 64-Bit - prefetchable - 16GB */ + <0xC3000000 0x9c 0x00000000 0x9c 0x00000000 0x04 0x00000000>; interrupts = ; interrupt-names = "intr"; @@ -79,8 +95,12 @@ &pcie5 { 0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - ranges = <0x81000000 0x0 0x00000000 0xa0 0x00010000 0x0 0x00010000 - 0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; + ranges = /* 16-Bit IO Window */ + <0x81000000 0x00 0x00000000 0xa0 0x00010000 0x00 0x00010000>, + /* 32-Bit - non-prefetchable */ + <0x82000000 0x00 0x40000000 0xa0 0x40000000 0x00 0xc0000000>, + /* 64-Bit - prefetchable - 16GB */ + <0xC3000000 0xa4 0x00000000 0xa4 0x00000000 0x04 0x00000000>; interrupts = ; interrupt-names = "intr"; @@ -95,8 +115,12 @@ &pcie6 { 0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - ranges = <0x81000000 0x0 0x00000000 0xa8 0x00010000 0x0 0x00010000 - 0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; + ranges = /* 16-Bit IO Window */ + <0x81000000 0x00 0x00000000 0xa8 0x00010000 0x00 0x00010000>, + /* 32-Bit - non-prefetchable */ + <0x82000000 0x00 0x40000000 0xa8 0x40000000 0x00 0xc0000000>, + /* 64-Bit - prefetchable - 16GB */ + <0xC3000000 0xac 0x00000000 0xac 0x00000000 0x04 0x00000000>; interrupts = ; interrupt-names = "intr"; From 13a37b30e464503515625ba891018aec0264c7d2 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Sun, 24 May 2026 16:54:41 +0200 Subject: [PATCH 623/665] arm64: dts: lx2162a-clearfog: use rev2 SoC dtsi LX2160A and LX2162A are different packages of the same silicon. While LX2160A had two revisions, LX2162A was released later based on LX2160A revision 2. Commit a8fe6c8dfc40 ("arm64: dts: fsl-lx2160a: add rev2 support") has added a new soc dtsi for revision 2. Update LX2162A Clearfog description to use revision 2 dtsi. Fixes: 5093b190f9ce ("arm64: dts: freescale: Add support for LX2162 SoM & Clearfog Board") # no-stable Signed-off-by: Josua Mayer Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts index 9d50d3e2761d..f95e9c19bfc7 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include "fsl-lx2160a.dtsi" +#include "fsl-lx2160a-rev2.dtsi" #include "fsl-lx2162a-sr-som.dtsi" / { From c1cd1923fe565957aa06ae60178fac5392bef91b Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Sun, 24 May 2026 16:54:42 +0200 Subject: [PATCH 624/665] arm64: dts: lx2162a-clearfog: cleanup superfluous status properties The SoC dtsi has always enabled serdes block 1, enabled dpmac and disabled pcie nodes. Drop the superfluous status properties on these nodes. Further drop crypto alias as SoM dtsi already set it. Signed-off-by: Josua Mayer Signed-off-by: Frank Li --- .../dts/freescale/fsl-lx2162a-clearfog.dts | 21 ------------------- 1 file changed, 21 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts index f95e9c19bfc7..6fd85a5cac94 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts @@ -14,7 +14,6 @@ / { compatible = "solidrun,lx2162a-clearfog", "solidrun,lx2162a-som", "fsl,lx2160a"; aliases { - crypto = &crypto; i2c0 = &i2c0; i2c1 = &i2c2; i2c2 = &i2c4; @@ -124,42 +123,36 @@ &dpmac11 { phys = <&serdes_2 0>; phy-handle = <ðernet_phy3>; phy-connection-type = "sgmii"; - status = "okay"; }; &dpmac12 { phys = <&serdes_2 1>; phy-handle = <ðernet_phy1>; phy-connection-type = "sgmii"; - status = "okay"; }; &dpmac13 { phys = <&serdes_2 6>; phy-handle = <ðernet_phy6>; phy-connection-type = "sgmii"; - status = "okay"; }; &dpmac14 { phys = <&serdes_2 7>; phy-handle = <ðernet_phy8>; phy-connection-type = "sgmii"; - status = "okay"; }; &dpmac15 { phys = <&serdes_2 4>; phy-handle = <ðernet_phy4>; phy-connection-type = "sgmii"; - status = "okay"; }; &dpmac16 { phys = <&serdes_2 5>; phy-handle = <ðernet_phy2>; phy-connection-type = "sgmii"; - status = "okay"; }; &dpmac17 { @@ -170,14 +163,12 @@ &dpmac17 { phys = <&serdes_2 2>; phy-handle = <ðernet_phy5>; phy-connection-type = "sgmii"; - status = "okay"; }; &dpmac18 { phys = <&serdes_2 3>; phy-handle = <ðernet_phy7>; phy-connection-type = "sgmii"; - status = "okay"; }; &emdio1 { @@ -314,14 +305,6 @@ pcieclk_i2c: i2c@2 { }; }; -&pcie3 { - status = "disabled"; -}; - -&pcie4 { - status = "disabled"; -}; - &pcs_mdio3 { status = "okay"; }; @@ -370,10 +353,6 @@ &pcs_mdio18 { status = "okay"; }; -&serdes_1 { - status = "okay"; -}; - &serdes_2 { status = "okay"; }; From 78dc1c1c1941223fc16ccd80e1402e3273321e30 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Sun, 24 May 2026 16:54:43 +0200 Subject: [PATCH 625/665] arm64: dts: lx2162a-clearfog: specify sfp ports led colour and function The LX2162A Clearfog board has a green LED on each of four SFP ports. Describe in device-tree that their colour is green and function "lan". Signed-off-by: Josua Mayer Signed-off-by: Frank Li --- .../boot/dts/freescale/fsl-lx2162a-clearfog.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts index 6fd85a5cac94..99ee2b1c0f13 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts @@ -6,6 +6,8 @@ /dts-v1/; +#include + #include "fsl-lx2160a-rev2.dtsi" #include "fsl-lx2162a-sr-som.dtsi" @@ -38,6 +40,9 @@ leds { compatible = "gpio-leds"; led_sfp_at: led-sfp-at { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* PROC_IRQ5 */ default-state = "off"; linux,default-trigger = "netdev"; @@ -45,6 +50,9 @@ led_sfp_at: led-sfp-at { }; led_sfp_ab: led-sfp-ab { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; /* PROC_IRQ11 */ default-state = "off"; linux,default-trigger = "netdev"; @@ -52,6 +60,9 @@ led_sfp_ab: led-sfp-ab { }; led_sfp_bt: led-sfp-bt { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <3>; gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; /* EVT1_B */ default-state = "off"; linux,default-trigger = "netdev"; @@ -59,6 +70,9 @@ led_sfp_bt: led-sfp-bt { }; led_sfp_bb: led-sfp-bb { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <4>; gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; /* EVT2_B */ default-state = "off"; linux,default-trigger = "netdev"; From 86036ee1aa7b5590fd586d0f34611289bea2f2ea Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Sun, 24 May 2026 16:54:44 +0200 Subject: [PATCH 626/665] dt-bindings: arm: fsl: Add solidrun lx2160a twins board The SolidRun LX2160A Twins board supports two configurations, one with with a single CEX-7 module, and one with two (dual). The single configuration is a specific assembly that maximises connectivity for single cpu by routing some second cpu resources to the first via zero-Ohm resistors. The dual configuration was not yet tested and is intentionally omitted. Initial review strongly suggests that the dual configuration will have different bindings, because from either cpu point of view the board appears different (e.g. different number of sfp, fewer i2c gpio). Add binding for the single variant only. Signed-off-by: Josua Mayer Reviewed-by: Krzysztof Kozlowski Signed-off-by: Frank Li --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 59f7f168bf7c..c52b361d6e6e 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1888,6 +1888,7 @@ properties: - enum: - solidrun,clearfog-cx - solidrun,honeycomb + - solidrun,twins-single - const: solidrun,lx2160a-cex7 - const: fsl,lx2160a From abe655d446a54d3d8ba6a278510d0b358d3f9e24 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Sun, 24 May 2026 16:54:45 +0200 Subject: [PATCH 627/665] arm64: dts: lx2160a-clearfog-itx: remove redundant dts version tag The dts version tag should only appear in the top level dts file. Since the cex-7 module and clearfog-itx are shared code intended for inclusion, drop their dts version tags. Signed-off-by: Josua Mayer Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi | 2 -- arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi | 2 -- 2 files changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi index 90956ffb8ea9..56b74837ddd4 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi @@ -4,8 +4,6 @@ // // Copyright 2019 SolidRun Ltd. -/dts-v1/; - #include "fsl-lx2160a.dtsi" / { diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi index 580ee9b3026e..6388bd60ffdf 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi @@ -5,8 +5,6 @@ // // Copyright 2019 SolidRun Ltd. -/dts-v1/; - #include "fsl-lx2160a-cex7.dtsi" #include From 4ff4d6f348d0bf650ec8c319178825b81ec3f99a Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Sun, 24 May 2026 16:54:46 +0200 Subject: [PATCH 628/665] arm64: dts: lx2160a-clearfog-itx: move shared includes to dts Originally includes were defined hierarchically: - CEX-7 Module includes SoC - Clearfog-CX & Honeycomb common parts include CEX-7 Module - Boards include common parts This makes it difficult to modify the includes on a per-board level, e.g. when adding a new board based on CEX-7 module but revision 2 SoC (which now has its own soc dtsi). Move includes of both SoC and CEX-7 module out of common parts and into each board dts. Signed-off-by: Josua Mayer Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi | 2 -- arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts | 2 ++ arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi | 1 - arch/arm64/boot/dts/freescale/fsl-lx2160a-honeycomb.dts | 2 ++ 4 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi index 56b74837ddd4..7df93bb37d13 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi @@ -4,8 +4,6 @@ // // Copyright 2019 SolidRun Ltd. -#include "fsl-lx2160a.dtsi" - / { model = "SolidRun LX2160A COM Express Type 7 module"; compatible = "solidrun,lx2160a-cex7", "fsl,lx2160a"; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts index 86a9b771428d..802d7611c647 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts @@ -6,6 +6,8 @@ /dts-v1/; +#include "fsl-lx2160a.dtsi" +#include "fsl-lx2160a-cex7.dtsi" #include "fsl-lx2160a-clearfog-itx.dtsi" / { diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi index 6388bd60ffdf..170e5b0034f1 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi @@ -5,7 +5,6 @@ // // Copyright 2019 SolidRun Ltd. -#include "fsl-lx2160a-cex7.dtsi" #include / { diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-honeycomb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-honeycomb.dts index fe19f3009ea5..2b1e13053422 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-honeycomb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-honeycomb.dts @@ -6,6 +6,8 @@ /dts-v1/; +#include "fsl-lx2160a.dtsi" +#include "fsl-lx2160a-cex7.dtsi" #include "fsl-lx2160a-clearfog-itx.dtsi" / { From 76eeabd859b9fbae843dccd44596c03d82c01e5d Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Sun, 24 May 2026 16:54:47 +0200 Subject: [PATCH 629/665] arm64: dts: lx2160a-cex7: add usb hub LX2160A CEX-7 module provides a total of 4 USB ports to the carrier board, one from first usb controller, and 3 from a hub behind the second controller. Both controllers currently have their status set okay in the module's dtsi file. However devices should be disabled by default when incomplete. The first USB controller is only completed by a carrier board featuring a device or USB connector. The second controller hosts a USB hub and should therefore be active. Add description for the USB hub, and enable the first controller only in the carrier board description. Signed-off-by: Josua Mayer Signed-off-by: Frank Li --- .../boot/dts/freescale/fsl-lx2160a-cex7.dtsi | 29 ++++++++++++++++--- .../freescale/fsl-lx2160a-clearfog-itx.dtsi | 4 +++ 2 files changed, 29 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi index 7df93bb37d13..2c86734c39ab 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi @@ -13,6 +13,13 @@ aliases { rtc0 = &com_rtc; }; + v_1_2: regulator-1-2 { + compatible = "regulator-fixed"; + regulator-name = "1v2"; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1200000>; + }; + sb_3v3: regulator-sb3v3 { compatible = "regulator-fixed"; regulator-name = "RT7290"; @@ -181,10 +188,24 @@ &pinmux_i2crv { pinctrl-0 = <&gpio0_14_12_pins>; }; -&usb0 { - status = "okay"; -}; - &usb1 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; + + usb_hub_2_0: hub@1 { + compatible = "usb4b4,6502", "usb4b4,6506"; + reg = <1>; + peer-hub = <&usb_hub_3_0>; + vdd2-supply = <&sb_3v3>; + vdd-supply = <&v_1_2>; + }; + + usb_hub_3_0: hub@2 { + compatible = "usb4b4,6500", "usb4b4,6504"; + reg = <2>; + peer-hub = <&usb_hub_2_0>; + vdd2-supply = <&sb_3v3>; + vdd-supply = <&v_1_2>; + }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi index 170e5b0034f1..4bc151d721dd 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi @@ -142,3 +142,7 @@ &uart0 { &uart1 { status = "okay"; }; + +&usb0 { + status = "okay"; +}; From df70a90b032f641643312aaf32442a2018b4bc3d Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Sun, 24 May 2026 16:54:48 +0200 Subject: [PATCH 630/665] arm64: dts: Add support for LX2160 Twins board in single configuration Add support for the SolidRun LX2160A Twins board in its single cpu configuration. The twins board is designed to host a pair of LX2160A CEX-7 modules, sharing a single PCI-E connector in multi-host mode. It may be assembled in two configurations (different assembly options facilitating signal re-routing), with a single or with dual CEX-7 module. Their marketing names are: - SolidWAN Single LX2160 - SolidWAN Dual LX2160 Add the single configuration, featuring: - 8x SFP (1Gbps) - 8x SFP+ (1/10Gbps) - PCI-E OCP card connector - USB-3.0 front-panel header with single port - microSD - dual hot-swappable power supplies Signed-off-by: Josua Mayer Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../boot/dts/freescale/fsl-lx2160a-cex7.dtsi | 8 +- .../dts/freescale/fsl-lx2160a-half-twins.dts | 830 ++++++++++++++++++ .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 24 +- 4 files changed, 848 insertions(+), 16 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 049eebda314d..aaebad5e6427 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -51,6 +51,8 @@ DTC_FLAGS_fsl-lx2160a-bluebox3-rev-a := -Wno-interrupt_map dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-bluebox3-rev-a.dtb DTC_FLAGS_fsl-lx2160a-clearfog-cx := -Wno-interrupt_map dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-clearfog-cx.dtb +DTC_FLAGS_fsl-lx2160a-half-twins := -Wno-interrupt_map +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-half-twins.dtb DTC_FLAGS_fsl-lx2160a-honeycomb := -Wno-interrupt_map dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-honeycomb.dtb DTC_FLAGS_fsl-lx2160a-qds := -Wno-interrupt_map diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi index 2c86734c39ab..16caa281ece0 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi @@ -65,7 +65,7 @@ i2c-mux@77 { #size-cells = <0>; reg = <0x77>; - i2c@0 { + ddr_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; @@ -91,7 +91,7 @@ eeprom@57 { }; }; - i2c@1 { + fan_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; @@ -102,7 +102,7 @@ fan-temperature-ctrlr@18 { }; }; - i2c@2 { + power_i2c: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; @@ -113,7 +113,7 @@ regulator@5c { }; }; - i2c@3 { + i2c_smb: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts new file mode 100644 index 000000000000..d16e27307275 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts @@ -0,0 +1,830 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Device Tree file for single LX2160A CEX-7 on Twins board. +// +// Copyright 2022 SolidRun Ltd. + +/dts-v1/; + +#include + +#include "fsl-lx2160a-rev2.dtsi" +#include "fsl-lx2160a-cex7.dtsi" + +/ { + compatible = "solidrun,twins-single", "solidrun,lx2160a-cex7", "fsl,lx2160a"; + model = "SolidRun LX2160A SolidWAN Single"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &expander0; + gpio5 = &expander1; + gpio6 = &expander2; + gpio7 = &expander3; + i2c0 = &i2c0; + i2c1 = &i2c2; + i2c2 = &i2c4; + i2c3 = &fan_i2c; + i2c4 = &power_i2c; + i2c5 = &i2c_smb; + i2c6 = &sfp0_i2c; + i2c7 = &sfp1_i2c; + i2c8 = &sfp2_i2c; + i2c9 = &sfp3_i2c; + i2c10 = &twins_sfp_c1_at_i2c; + i2c11 = &twins_sfp_c1_ab_i2c; + i2c12 = &twins_sfp_c1_bt_i2c; + i2c13 = &twins_sfp_c1_bb_i2c; + i2c14 = &twins_sfp_c2_at_i2c; + i2c15 = &twins_sfp_c2_ab_i2c; + i2c16 = &twins_sfp_c2_bt_i2c; + i2c17 = &twins_sfp_c2_bb_i2c; + i2c18 = &twins_sfp_c3_at_i2c; + i2c19 = &twins_sfp_c3_ab_i2c; + i2c20 = &twins_sfp_c3_bt_i2c; + i2c21 = &twins_sfp_c3_bb_i2c; + i2c22 = &htwins_sfp_c3_at_i2c; + i2c23 = &htwins_sfp_c3_ab_i2c; + i2c24 = &htwins_sfp_c3_bt_i2c; + i2c25 = &htwins_sfp_c3_bb_i2c; + i2c26 = &ddr_i2c; + mmc0 = &esdhc0; + mmc1 = &esdhc1; + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led_ht_c3_bt: led-sfp-1 { + color = ; + default-state = "off"; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + gpios = <&expander3 14 GPIO_ACTIVE_LOW>; + trigger-sources = <&dpmac5>; + linux,default-trigger = "netdev"; + }; + + led_ht_c3_bb: led-sfp-2 { + color = ; + default-state = "off"; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + gpios = <&expander3 13 GPIO_ACTIVE_LOW>; + trigger-sources = <&dpmac15>; + linux,default-trigger = "netdev"; + }; + + led_ht_c3_at: led-sfp-3 { + color = ; + default-state = "off"; + function = LED_FUNCTION_LAN; + function-enumerator = <3>; + gpios = <&expander3 11 GPIO_ACTIVE_LOW>; + trigger-sources = <&dpmac6>; + linux,default-trigger = "netdev"; + }; + + led_ht_c3_ab: led-sfp-4 { + color = ; + default-state = "off"; + function = LED_FUNCTION_LAN; + function-enumerator = <4>; + gpios = <&expander3 12 GPIO_ACTIVE_LOW>; + trigger-sources = <&dpmac11>; + linux,default-trigger = "netdev"; + }; + + led_c1_bt: led-sfp-9 { + color = ; + default-state = "off"; + function = LED_FUNCTION_LAN; + function-enumerator = <9>; + gpios = <&expander1 4 GPIO_ACTIVE_LOW>; + trigger-sources = <&dpmac4>; + linux,default-trigger = "netdev"; + }; + + led_c1_bb: led-sfp-10 { + color = ; + default-state = "off"; + function = LED_FUNCTION_LAN; + function-enumerator = <10>; + gpios = <&expander1 3 GPIO_ACTIVE_LOW>; + trigger-sources = <&dpmac17>; + linux,default-trigger = "netdev"; + }; + + led_c1_at: led-sfp-11 { + color = ; + default-state = "off"; + function = LED_FUNCTION_LAN; + function-enumerator = <11>; + gpios = <&expander1 1 GPIO_ACTIVE_LOW>; + trigger-sources = <&dpmac3>; + linux,default-trigger = "netdev"; + }; + + led_c1_ab: led-sfp-12 { + color = ; + default-state = "off"; + function = LED_FUNCTION_LAN; + function-enumerator = <12>; + gpios = <&expander1 2 GPIO_ACTIVE_LOW>; + trigger-sources = <&dpmac12>; + linux,default-trigger = "netdev"; + }; + + led_c2_bt: led-sfp-13 { + color = ; + default-state = "off"; + function = LED_FUNCTION_LAN; + function-enumerator = <13>; + gpios = <&expander1 10 GPIO_ACTIVE_LOW>; + trigger-sources = <&dpmac8>; + linux,default-trigger = "netdev"; + }; + + led_c2_bb: led-sfp-14 { + color = ; + default-state = "off"; + function = LED_FUNCTION_LAN; + function-enumerator = <14>; + gpios = <&expander1 9 GPIO_ACTIVE_LOW>; + trigger-sources = <&dpmac16>; + linux,default-trigger = "netdev"; + }; + + led_c2_at: led-sfp-15 { + color = ; + default-state = "off"; + function = LED_FUNCTION_LAN; + function-enumerator = <15>; + gpios = <&expander1 5 GPIO_ACTIVE_LOW>; + trigger-sources = <&dpmac7>; + linux,default-trigger = "netdev"; + }; + + led_c2_ab: led-sfp-16 { + color = ; + default-state = "off"; + function = LED_FUNCTION_LAN; + function-enumerator = <16>; + gpios = <&expander1 6 GPIO_ACTIVE_LOW>; + trigger-sources = <&dpmac18>; + linux,default-trigger = "netdev"; + }; + + led_c3_bt: led-sfp-17 { + color = ; + default-state = "off"; + function = LED_FUNCTION_LAN; + function-enumerator = <17>; + gpios = <&expander1 14 GPIO_ACTIVE_LOW>; + trigger-sources = <&dpmac10>; + linux,default-trigger = "netdev"; + }; + + led_c3_bb: led-sfp-18 { + color = ; + default-state = "off"; + function = LED_FUNCTION_LAN; + function-enumerator = <18>; + gpios = <&expander1 13 GPIO_ACTIVE_LOW>; + trigger-sources = <&dpmac14>; + linux,default-trigger = "netdev"; + }; + + led_c3_at: led-sfp-19 { + color = ; + default-state = "off"; + function = LED_FUNCTION_LAN; + function-enumerator = <19>; + gpios = <&expander1 11 GPIO_ACTIVE_LOW>; + trigger-sources = <&dpmac9>; + linux,default-trigger = "netdev"; + }; + + led_c3_ab: led-sfp-20 { + color = ; + default-state = "off"; + function = LED_FUNCTION_LAN; + function-enumerator = <20>; + gpios = <&expander1 12 GPIO_ACTIVE_LOW>; + trigger-sources = <&dpmac13>; + linux,default-trigger = "netdev"; + }; + + led-status { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <0>; + gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + led-status-twin { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + }; + + led-fault { + color = ; + default-state = "off"; + function = LED_FUNCTION_FAULT; + function-enumerator = <0>; + gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + panic-indicator; + }; + + led-fault-twin { + color = ; + default-state = "off"; + function = LED_FUNCTION_FAULT; + function-enumerator = <1>; + gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; + }; + }; + + mux-controller { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + /* + * This gpio controlled mux can route the tacho signals of 6 PWM FAN connectors + * to the tacho inputs of both CEX-7 modules (twins). + * + * The first twin controls this mux and monitors four fan connectors, two intended + * for itself, and two for the OCP card. + * + * The second twin monitors only two fan connectors intended for itself. + * + * The table below maps selector GPIO states to monitored fan connector per twin: + * + * | SEL1 | SEL0 | Twin 1 | Twin 2 | + * | ---: | ---: | :------| ------ | + * | 0 | 0 | J10 | J5024 | + * | 0 | 1 | J5016 | J5024 | + * | 1 | 0 | J5026 | J5025 | + * | 1 | 1 | J5013 | J5025 | + */ + mux-gpios = <&expander0 8 GPIO_ACTIVE_HIGH>, /* SEL0 */ + <&expander0 15 GPIO_ACTIVE_HIGH>; /* SEL1 */ + }; + + ht_c3_bt_sfp: sfp-1 { + compatible = "sff,sfp"; + i2c-bus = <&htwins_sfp_c3_bt_i2c>; + maximum-power-milliwatt = <2000>; + mod-def0-gpios = <&expander2 13 GPIO_ACTIVE_LOW>; + }; + + ht_c3_bb_sfp: sfp-2 { + compatible = "sff,sfp"; + i2c-bus = <&htwins_sfp_c3_bb_i2c>; + maximum-power-milliwatt = <2000>; + mod-def0-gpios = <&expander2 14 GPIO_ACTIVE_LOW>; + }; + + ht_c3_at_sfp: sfp-3 { + compatible = "sff,sfp"; + i2c-bus = <&htwins_sfp_c3_at_i2c>; + maximum-power-milliwatt = <2000>; + mod-def0-gpios = <&expander2 11 GPIO_ACTIVE_LOW>; + }; + + ht_c3_ab_sfp: sfp-4 { + compatible = "sff,sfp"; + i2c-bus = <&htwins_sfp_c3_ab_i2c>; + maximum-power-milliwatt = <2000>; + mod-def0-gpios = <&expander2 12 GPIO_ACTIVE_LOW>; + }; + + c1_bt_sfp: sfp-9 { + compatible = "sff,sfp"; + i2c-bus = <&twins_sfp_c1_bt_i2c>; + maximum-power-milliwatt = <2000>; + mod-def0-gpios = <&expander0 3 GPIO_ACTIVE_LOW>; + }; + + c1_bb_sfp: sfp-10 { + compatible = "sff,sfp"; + i2c-bus = <&twins_sfp_c1_bb_i2c>; + maximum-power-milliwatt = <2000>; + mod-def0-gpios = <&expander0 4 GPIO_ACTIVE_LOW>; + }; + + c1_at_sfp: sfp-11 { + compatible = "sff,sfp"; + i2c-bus = <&twins_sfp_c1_at_i2c>; + maximum-power-milliwatt = <2000>; + mod-def0-gpios = <&expander0 1 GPIO_ACTIVE_LOW>; + }; + + c1_ab_sfp: sfp-12 { + compatible = "sff,sfp"; + i2c-bus = <&twins_sfp_c1_ab_i2c>; + maximum-power-milliwatt = <2000>; + mod-def0-gpios = <&expander0 2 GPIO_ACTIVE_LOW>; + }; + + c2_bt_sfp: sfp-13 { + compatible = "sff,sfp"; + i2c-bus = <&twins_sfp_c2_bt_i2c>; + maximum-power-milliwatt = <2000>; + mod-def0-gpios = <&expander0 9 GPIO_ACTIVE_LOW>; + }; + + c2_bb_sfp: sfp-14 { + compatible = "sff,sfp"; + i2c-bus = <&twins_sfp_c2_bb_i2c>; + maximum-power-milliwatt = <2000>; + mod-def0-gpios = <&expander0 10 GPIO_ACTIVE_LOW>; + }; + + c2_at_sfp: sfp-15 { + compatible = "sff,sfp"; + i2c-bus = <&twins_sfp_c2_at_i2c>; + maximum-power-milliwatt = <2000>; + mod-def0-gpios = <&expander0 5 GPIO_ACTIVE_LOW>; + }; + + c2_ab_sfp: sfp-16 { + compatible = "sff,sfp"; + i2c-bus = <&twins_sfp_c2_ab_i2c>; + maximum-power-milliwatt = <2000>; + mod-def0-gpios = <&expander0 6 GPIO_ACTIVE_LOW>; + }; + + c3_bt_sfp: sfp-17 { + compatible = "sff,sfp"; + i2c-bus = <&twins_sfp_c3_bt_i2c>; + maximum-power-milliwatt = <2000>; + mod-def0-gpios = <&expander0 13 GPIO_ACTIVE_LOW>; + }; + + c3_bb_sfp: sfp-18 { + compatible = "sff,sfp"; + i2c-bus = <&twins_sfp_c3_bb_i2c>; + maximum-power-milliwatt = <2000>; + mod-def0-gpios = <&expander0 14 GPIO_ACTIVE_LOW>; + }; + + c3_at_sfp: sfp-19 { + compatible = "sff,sfp"; + i2c-bus = <&twins_sfp_c3_at_i2c>; + maximum-power-milliwatt = <2000>; + mod-def0-gpios = <&expander0 11 GPIO_ACTIVE_LOW>; + }; + + c3_ab_sfp: sfp-20 { + compatible = "sff,sfp"; + i2c-bus = <&twins_sfp_c3_ab_i2c>; + maximum-power-milliwatt = <2000>; + mod-def0-gpios = <&expander0 12 GPIO_ACTIVE_LOW>; + }; +}; + +/* + * This board supports industrial grade temperatures, + * the LX2160A SoC maximum junction temperature is 105°C. + * + * Raise thermal thresholds to allow operation near maximum temperature. + */ +&ccn_dpaa_alert { + temperature = <100000>; +}; + +&ccn_dpaa_crit { + temperature = <105000>; +}; + +&cluster2_3_alert { + temperature = <100000>; +}; + +&cluster2_3_crit { + temperature = <105000>; +}; + +&cluster4_alert { + temperature = <100000>; +}; + +&cluster4_crit { + temperature = <105000>; +}; + +&cluster5_alert { + temperature = <100000>; +}; + +&cluster5_crit { + temperature = <105000>; +}; + +&cluster6_7_alert { + temperature = <100000>; +}; + +&cluster6_7_crit { + temperature = <105000>; +}; + +&dce_qbman_alert { + temperature = <100000>; +}; + +&dce_qbman_crit { + temperature = <105000>; +}; + +/* sfp port 11 */ +&dpmac3 { + managed = "in-band-status"; + phys = <&serdes_1 7>; + sfp = <&c1_at_sfp>; +}; + +/* sfp port 9 */ +&dpmac4 { + managed = "in-band-status"; + phys = <&serdes_1 6>; + sfp = <&c1_bt_sfp>; +}; + +/* sfp port 1 */ +&dpmac5 { + managed = "in-band-status"; + phys = <&serdes_1 5>; + sfp = <&ht_c3_bt_sfp>; +}; + +/* sfp port 3 */ +&dpmac6 { + managed = "in-band-status"; + phys = <&serdes_1 4>; + sfp = <&ht_c3_at_sfp>; +}; + +/* sfp port 15 */ +&dpmac7 { + managed = "in-band-status"; + phys = <&serdes_1 3>; + sfp = <&c2_at_sfp>; +}; + +/* sfp port 13 */ +&dpmac8 { + managed = "in-band-status"; + phys = <&serdes_1 2>; + sfp = <&c2_bt_sfp>; +}; + +/* sfp port 19 */ +&dpmac9 { + managed = "in-band-status"; + phys = <&serdes_1 1>; + sfp = <&c3_at_sfp>; +}; + +/* sfp port 17 */ +&dpmac10 { + managed = "in-band-status"; + phys = <&serdes_1 0>; + sfp = <&c3_bt_sfp>; +}; + +/* sfp port 4 */ +&dpmac11 { + managed = "in-band-status"; + phys = <&serdes_2 0>; + sfp = <&ht_c3_ab_sfp>; +}; + +/* sfp port 12 */ +&dpmac12 { + managed = "in-band-status"; + phys = <&serdes_2 1>; + sfp = <&c1_ab_sfp>; +}; + +/* sfp port 20 */ +&dpmac13 { + managed = "in-band-status"; + phys = <&serdes_2 6>; + sfp = <&c3_ab_sfp>; +}; + +/* sfp port 18 */ +&dpmac14 { + managed = "in-band-status"; + phys = <&serdes_2 7>; + sfp = <&c3_bb_sfp>; +}; + +/* sfp port 2 */ +&dpmac15 { + managed = "in-band-status"; + phys = <&serdes_2 4>; + sfp = <&ht_c3_bb_sfp>; +}; + +/* sfp port 14 */ +&dpmac16 { + managed = "in-band-status"; + phys = <&serdes_2 5>; + sfp = <&c2_bb_sfp>; +}; + +/* sfp port 10 */ +&dpmac17 { + /* override connection to on-COM phy */ + /delete-property/ phy-handle; + /delete-property/ phy-connection-type; + managed = "in-band-status"; + phys = <&serdes_2 2>; + sfp = <&c1_bb_sfp>; +}; + +/* sfp port 16 */ +&dpmac18 { + managed = "in-band-status"; + phys = <&serdes_2 3>; + sfp = <&c2_ab_sfp>; +}; + +&esdhc0 { + pinctrl-0 = <&esdhc0_cd_wp_pins>, <&esdhc0_cmd_data30_clk_vsel_pins>; + pinctrl-names = "default"; + /* + * Disable 1.8V modes so that microsd state is same between + * power-on-reset, u-boot and linux. + * This avoids sporadic read errors after hard reset with some cards. + */ + no-1-8-v; + status = "okay"; +}; + +&i2c2 { + expander0: gpio@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + }; + + expander1: gpio@21 { + compatible = "nxp,pca9555"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + }; + + expander2: gpio@24 { + compatible = "nxp,pca9555"; + reg = <0x24>; + #gpio-cells = <2>; + gpio-controller; + }; + + expander3: gpio@25 { + compatible = "nxp,pca9555"; + reg = <0x25>; + #gpio-cells = <2>; + gpio-controller; + }; + + /* Half twins configuration; take over c3 from the other twin side */ + i2c-mux@73 { + compatible = "nxp,pca9547"; + reg = <0x73>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + htwins_sfp_c3_at_i2c: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + + htwins_sfp_c3_ab_i2c: i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + htwins_sfp_c3_bt_i2c: i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + }; + + htwins_sfp_c3_bb_i2c: i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + i2c-mux@76 { + compatible = "nxp,pca9547"; + reg = <0x76>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + twins_sfp_c1_at_i2c: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + twins_sfp_c1_ab_i2c: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + twins_sfp_c1_bt_i2c: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + + twins_sfp_c1_bb_i2c: i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + twins_sfp_c2_at_i2c: i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + }; + + twins_sfp_c2_ab_i2c: i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + i2c-mux@77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + twins_sfp_c2_bt_i2c: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + twins_sfp_c2_bb_i2c: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + twins_sfp_c3_at_i2c: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + + twins_sfp_c3_ab_i2c: i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + twins_sfp_c3_bt_i2c: i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + }; + + twins_sfp_c3_bb_i2c: i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&pcie5 { + status = "okay"; +}; + +&pcs_mdio3 { + status = "okay"; +}; + +&pcs_mdio4 { + status = "okay"; +}; + +&pcs_mdio5 { + status = "okay"; +}; + +&pcs_mdio6 { + status = "okay"; +}; + +&pcs_mdio7 { + status = "okay"; +}; + +&pcs_mdio8 { + status = "okay"; +}; + +&pcs_mdio9 { + status = "okay"; +}; + +&pcs_mdio10 { + status = "okay"; +}; + +&pcs_mdio11 { + status = "okay"; +}; + +&pcs_mdio12 { + status = "okay"; +}; + +&pcs_mdio13 { + status = "okay"; +}; + +&pcs_mdio14 { + status = "okay"; +}; + +&pcs_mdio15 { + status = "okay"; +}; + +&pcs_mdio16 { + status = "okay"; +}; + +&pcs_mdio17 { + status = "okay"; +}; + +&pcs_mdio18 { + status = "okay"; +}; + +&rgmii_phy1 { + /* + * COM has a phy at address 1 connected to SoC Ethernet Controller 1. + * It competes for WRIOP MAC17, and no connector has been wired. + */ + status = "disabled"; +}; + +&serdes_2 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&wriop_alert { + temperature = <100000>; +}; + +&wriop_crit { + temperature = <105000>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 479982948ee5..1d73abffa6b7 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -499,13 +499,13 @@ ddr-ctrl5-thermal { thermal-sensors = <&tmu 1>; trips { - ddr-cluster5-alert { + cluster5_alert: ddr-cluster5-alert { temperature = <85000>; hysteresis = <2000>; type = "passive"; }; - ddr-cluster5-crit { + cluster5_crit: ddr-cluster5-crit { temperature = <95000>; hysteresis = <2000>; type = "critical"; @@ -519,13 +519,13 @@ wriop-thermal { thermal-sensors = <&tmu 2>; trips { - wriop-alert { + wriop_alert: wriop-alert { temperature = <85000>; hysteresis = <2000>; type = "passive"; }; - wriop-crit { + wriop_crit: wriop-crit { temperature = <95000>; hysteresis = <2000>; type = "critical"; @@ -539,13 +539,13 @@ dce-thermal { thermal-sensors = <&tmu 3>; trips { - dce-qbman-alert { + dce_qbman_alert: dce-qbman-alert { temperature = <85000>; hysteresis = <2000>; type = "passive"; }; - dce-qbman-crit { + dce_qbman_crit: dce-qbman-crit { temperature = <95000>; hysteresis = <2000>; type = "critical"; @@ -559,13 +559,13 @@ ccn-thermal { thermal-sensors = <&tmu 4>; trips { - ccn-dpaa-alert { + ccn_dpaa_alert: ccn-dpaa-alert { temperature = <85000>; hysteresis = <2000>; type = "passive"; }; - ccn-dpaa-crit { + ccn_dpaa_crit: ccn-dpaa-crit { temperature = <95000>; hysteresis = <2000>; type = "critical"; @@ -579,13 +579,13 @@ cluster4-thermal { thermal-sensors = <&tmu 5>; trips { - clust4-hsio3-alert { + cluster4_alert: clust4-hsio3-alert { temperature = <85000>; hysteresis = <2000>; type = "passive"; }; - clust4-hsio3-crit { + cluster4_crit: clust4-hsio3-crit { temperature = <95000>; hysteresis = <2000>; type = "critical"; @@ -599,13 +599,13 @@ cluster2-3-thermal { thermal-sensors = <&tmu 6>; trips { - cluster2-3-alert { + cluster2_3_alert: cluster2-3-alert { temperature = <85000>; hysteresis = <2000>; type = "passive"; }; - cluster2-3-crit { + cluster2_3_crit: cluster2-3-crit { temperature = <95000>; hysteresis = <2000>; type = "critical"; From 40c28b9c9fa6ac39f89265b0d9cae10bd85610fb Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Sun, 24 May 2026 14:03:09 +0200 Subject: [PATCH 631/665] dt-bindings: arm: fsl: Add SolidRun i.MX8DXL SoM and HummingBoard Add binding for the SolidRun i.MX8DXL based System on Module, and the reference HummingBoard Telematics. Acked-by: Krzysztof Kozlowski Signed-off-by: Josua Mayer Signed-off-by: Frank Li --- Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index c52b361d6e6e..279e9a7e5f9e 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1398,6 +1398,13 @@ properties: - fsl,imx8dxl-evk # i.MX8DXL EVK Board - const: fsl,imx8dxl + - description: SolidRun i.MX8DXL SoM based boards + items: + - enum: + - solidrun,imx8dxl-hummingboard-telematics # SolidRun i.MX8DXL SoM EVK Board + - const: solidrun,imx8dxl-sr-som + - const: fsl,imx8dxl + - description: i.MX8QXP/i.MX8DX Boards with Toradex Colibri iMX8X Modules items: - enum: From ef873f01a1b18820734b00bffa00d878de0e0bb0 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Sun, 24 May 2026 14:03:10 +0200 Subject: [PATCH 632/665] arm64: dts: imx8dxl: Add SolidRun SoM and HummingBoard Add support for the SolidRun i.MX8DXL System-on-Module (revision 2.1) and its corresponding evaluation carrier board, the HummingBoard Telematics (revision 2.0). The SoM features: - eMMC - GNSS with 1PPS - V2X DSRC Radio - Secure Element for V2X Applications - Inertial Sensor - Pressure Sensor - Compass The HummingBoard Telematics carrier board features: - Cellular Modem - WiFi & Bluetooth - RTC with backup battery - CAN - 100Base-TX Ethernet - 100Base-T1 Ethernet - Multi-interface I/O connector - Multi-interface add-on board connector The multi-interface I/O connector supplies power and provides basic I/O (Console UART, 100Base-TX, 100Base-T1, CAN, and power-supply logic level GPIOs). The SolidRun Evaluation Kit includes a suitable cable and adapter board that breaks these out into RJ45, USB Type-A, microUSB Console, and Terminal Block connectors. The multi-interface add-on board connector provides additional interfaces (5x 100Base-T1, 2x SGMII, USB 2.0 shared with the cellular modem, CAN, MDIO, SPI, UART, PCIe, I2C, and GPIO). These add-on interfaces are disabled by default in the base device tree and are intended to be enabled and extended via device tree overlays. Note that a few components physically present on the SoM were omitted from this description due to a lack of upstream bindings and drivers: - Pressure Sensor - V2X DSRC Radio - Secure Element Acked-by: Andrew Lunn Signed-off-by: Josua Mayer Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../imx8dxl-hummingboard-telematics.dts | 560 ++++++++++++++++++ .../boot/dts/freescale/imx8dxl-sr-som.dtsi | 458 ++++++++++++++ 3 files changed, 1020 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-hummingboard-telematics.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-sr-som.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index aaebad5e6427..8473ebb44537 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -113,6 +113,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb imx8dxl-evk-pcie-ep-dtbs += imx8dxl-evk.dtb imx-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk-pcie-ep.dtb +DTC_FLAGS_imx8dxl-hummingboard-telematics := -@ +dtb-$(CONFIG_ARCH_MXC) += imx8dxl-hummingboard-telematics.dtb dtb-$(CONFIG_ARCH_MXC) += imx8dxp-tqma8xdp-mba8xx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8dxp-tqma8xdps-mb-smarc-2.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-hummingboard-telematics.dts b/arch/arm64/boot/dts/freescale/imx8dxl-hummingboard-telematics.dts new file mode 100644 index 000000000000..3095dc87f188 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-hummingboard-telematics.dts @@ -0,0 +1,560 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022-2026 Josua Mayer + */ + +/dts-v1/; + +#include "imx8dxl-sr-som.dtsi" + +/ { + compatible = "solidrun,imx8dxl-hummingboard-telematics", + "solidrun,imx8dxl-sr-som", "fsl,imx8dxl"; + model = "SolidRun i.MX8DXL HummingBoard Telematics"; + + aliases { + /* override ethernet aliases from imx8dxl.dtsi */ + ethernet0 = &eqos; + ethernet1 = &switch_port1; + ethernet2 = &switch_port2; + ethernet3 = &switch_port3; + ethernet4 = &switch_port4; + ethernet5 = &switch_port5; + ethernet6 = &switch_port6; + ethernet7 = &switch_port7; + ethernet8 = &switch_port8; + ethernet9 = &switch_port9; + ethernet10 = &switch_port10; + gpio8 = &tca6408_u2; + mmc2 = &usdhc3; + rtc0 = &carrier_rtc; + rtc1 = &rtc; + serial1 = &lpuart1; + }; + + osc_32k: clock-osc-32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + v_1_1: regulator-1-1 { + compatible = "regulator-fixed"; + regulator-name = "1v1"; + pinctrl-0 = <®ulator_1v1_pins>; + pinctrl-names = "default"; + regulator-always-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1100000>; + vin-supply = <&v_5_0>; + gpio = <&lsio_gpio4 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + v_5_0: regulator-5-0 { + compatible = "regulator-fixed"; + regulator-name = "5v0"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + }; + + /* can transceiver builtin regulator (STBN1 pin) */ + reg_flexcan1_stby: regulator-flexcan1-standby { + compatible = "regulator-fixed"; + regulator-name = "flexcan1-standby"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + gpio = <&tca6408_u2 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + /* can transceiver builtin regulator (STBN2 pin) */ + reg_flexcan2_stby: regulator-flexcan2-standby { + compatible = "regulator-fixed"; + regulator-name = "flexcan2-standby"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + gpio = <&tca6408_u2 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + modem_vbat: regulator-modem-vbat { + compatible = "regulator-fixed"; + regulator-name = "modem-vbat"; + pinctrl-0 = <®ulator_modem_vbat_pins>; + pinctrl-names = "default"; + regulator-max-microvolt = <3600000>; + regulator-min-microvolt = <3600000>; + vin-supply = <&v_5_0>; + gpio = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * Cellular Modem uses VBAT, RESET_N and PWRKEY for + * power-sequencing. USB core does not currently + * support this, keep vbat on permanently and let + * userspace deal with reset/pwrkey. + */ + regulator-always-on; + regulator-boot-on; + }; + + vbus1: regulator-vbus-1 { + compatible = "regulator-fixed"; + regulator-name = "vbus1"; + pinctrl-0 = <®ulator_usb1_vbus_pins>; + pinctrl-names = "default"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + gpio = <&lsio_gpio0 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usdhc3_pwrseq: usdhc3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_LOW>; + }; +}; + +&dma_apbh { + status = "disabled"; +}; + +&eqos { + /* delays are added by connected ethernet-switch cpu port */ + phy-mode = "rgmii-id"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + pinctrl-0 = <&eqos_pins>; + pinctrl-names = "default"; + status = "okay"; + + fixed-link { + full-duplex; + speed = <1000>; + }; +}; + +&flexcan1 { + pinctrl-0 = <&flexcan1_pins>; + pinctrl-names = "default"; + xceiver-supply = <®_flexcan1_stby>; + status = "okay"; + + can-transceiver { + max-bitrate = <5000000>; + }; +}; + +&flexcan2 { + pinctrl-0 = <&flexcan2_pins>; + pinctrl-names = "default"; + xceiver-supply = <®_flexcan2_stby>; + status = "okay"; + + can-transceiver { + max-bitrate = <5000000>; + }; +}; + +&i2c2 { + /* routed to J14: SDA(51), SCL(53) */ + + /* regulator@18 */ + + tca6408_u2: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + #interrupt-cells = <2>; + interrupt-controller; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = "DIG_IN1", "DIG_IN2", "CAN_STNB1", "CAN_STNB2", + "DIG_OUT1", "DIG_OUT2", "", ""; + interrupts-extended = <&lsio_gpio0 20 IRQ_TYPE_EDGE_FALLING>; + pinctrl-0 = <&tca6408_u2_int_pins>; + pinctrl-names = "default"; + }; + + carrier_rtc: rtc@32 { + compatible = "epson,rx8111"; + reg = <0x32>; + }; +}; + +&iomuxc { + bluetooth_pins: pinctrl-bluetooth-grp { + fsl,pins = < + /* BT_REG_ON: io without pull (module integrates pd) */ + IMX8DXL_SPI3_SCK_LSIO_GPIO0_IO13 0x0000061 + >; + }; + + eqos_pins: pinctrl-eqos-grp { + fsl,pins = < + /* MDIO to Switch */ + /* enet0 mdio pads supplied with 3.3v */ + /* IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT */ + IMX8DXL_ENET0_MDC_CONN_EQOS_MDC 0x06000020 + IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO 0x06000020 + /* RGMII to Switch */ + IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x06000020 + IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC 0x06000020 + IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 0x06000020 + IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 0x06000020 + IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 0x06000020 + IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 0x06000020 + IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC 0x06000020 + IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL 0x06000020 + IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 0x06000020 + IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 0x06000020 + IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 0x06000020 + IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 0x06000020 + >; + }; + + flexcan1_pins: pinctrl-flexcan1-grp { + fsl,pins = < + IMX8DXL_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x00000021 + IMX8DXL_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x00000021 + >; + }; + + flexcan2_pins: pinctrl-flexcan2-grp { + fsl,pins = < + IMX8DXL_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x00000021 + IMX8DXL_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x00000021 + >; + }; + + lpspi0_pins: pinctrl-lpspi0-grp { + fsl,pins = < + IMX8DXL_SPI0_SCK_ADMA_SPI0_SCK 0x600004c + IMX8DXL_SPI0_SDO_ADMA_SPI0_SDO 0x600004c + IMX8DXL_SPI0_SDI_ADMA_SPI0_SDI 0x600004c + IMX8DXL_SPI0_CS0_LSIO_GPIO1_IO08 0x0000021 + IMX8DXL_SPI0_CS1_LSIO_GPIO1_IO07 0x0000021 + >; + }; + + lpuart1_pins: pinctrl-lpuart1-grp { + fsl,pins = < + IMX8DXL_UART1_RX_ADMA_UART1_RX 0x06000020 + IMX8DXL_UART1_TX_ADMA_UART1_TX 0x06000020 + IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020 + IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020 + >; + }; + + modem_pins: pinctrl-lte-grp { + fsl,pins = < + /* modem RESET_N: io open drain drive 2mA */ + IMX8DXL_ADC_IN3_LSIO_GPIO1_IO11 0x2000061 + + /* modem PWRKEY: io open drain with pull-up, drive 2mA */ + IMX8DXL_ADC_IN2_LSIO_GPIO1_IO12 0x2000021 + >; + }; + + regulator_1v1_pins: pinctrl-regulator-1-1-grp { + fsl,pins = < + /* SW_PE: io without pull-up */ + IMX8DXL_USB_SS3_TC2_LSIO_GPIO4_IO05 0x0000061 + >; + }; + + regulator_modem_vbat_pins: pinctrl-regulator-modem-vbat-grp { + fsl,pins = < + /* + * RF_PWR: io without pull-up, + * has either external pull-up (R1117) or pull-down (R1118). + * With pull-up Modem will boot at system power-up, + * with pull-down modem will enter power-down mode once + * vbat is enabled -> toggle pwrkey to boot modem. + * Hence pull-up (R1117) is preferred. + */ + IMX8DXL_SPI3_SDO_LSIO_GPIO0_IO14 0x0000061 + >; + }; + + regulator_usb1_vbus_pins: pinctrl-regulator-usb1-vbus-grp { + fsl,pins = < + /* regulator enable: open-drain with pull-up & low drive strength */ + IMX8DXL_SPI3_CS0_LSIO_GPIO0_IO16 0x2000021 + >; + }; + + switch_pins: pinctrl-switch-grp { + fsl,pins = < + /* SW_RSTn: io without pull-up */ + IMX8DXL_USB_SS3_TC0_LSIO_GPIO4_IO03 0x0000021 + + /* SW_CORE_RSTn: io without pull-up */ + IMX8DXL_USB_SS3_TC1_LSIO_GPIO4_IO04 0x0000021 + + /* INT_N: io without pull-up */ + IMX8DXL_USB_SS3_TC3_LSIO_GPIO4_IO06 0x0000021 + >; + }; + + tca6408_u2_int_pins: pinctrl-tca6408-u2-int-grp { + fsl,pins = < + /* gpio-expander interrupt: io with pull-up */ + IMX8DXL_MCLK_OUT0_LSIO_GPIO0_IO20 0x0000021 + >; + }; + + usdhc3_pins: pinctrl-usdhc3-grp { + fsl,pins = < + IMX8DXL_ENET0_RGMII_TXC_CONN_USDHC2_CLK 0x06000040 + IMX8DXL_ENET0_RGMII_TX_CTL_CONN_USDHC2_CMD 0x00000021 + IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC2_DATA0 0x00000021 + IMX8DXL_ENET0_RGMII_TXD1_CONN_USDHC2_DATA1 0x00000021 + IMX8DXL_ENET0_RGMII_TXD2_CONN_USDHC2_DATA2 0x00000021 + IMX8DXL_ENET0_RGMII_TXD3_CONN_USDHC2_DATA3 0x00000021 + >; + }; + + wifi_pins: pinctrl-wifi-grp { + fsl,pins = < + /* WL_REG_ON: io without pull (module integrates pd) */ + IMX8DXL_SPI3_SDI_LSIO_GPIO0_IO15 0x0000061 + >; + }; +}; + +&lpspi0 { + cs-gpios = <&lsio_gpio1 8 GPIO_ACTIVE_LOW>, <&lsio_gpio1 7 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&lpspi0_pins>, <&switch_pins>; + pinctrl-names = "default"; + status = "okay"; + + ethernet-switch@0 { + compatible = "nxp,sja1110a"; + reg = <0>; + reset-gpios = <&lsio_gpio4 3 GPIO_ACTIVE_LOW>; + spi-max-frequency = <4000000>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* 100Base-TX on connector J26 */ + switch_port1: port@1 { + reg = <0x1>; + phy-handle = <&switch_port1_base_tx_phy>; + phy-mode = "internal"; + }; + + /* CPU */ + switch_port2: port@2 { + reg = <0x2>; + ethernet = <&eqos>; + phy-mode = "rgmii-id"; + rx-internal-delay-ps = <2000>; + tx-internal-delay-ps = <2000>; + + fixed-link { + full-duplex; + speed = <1000>; + }; + }; + + /* sgmii on addon board connector J21 */ + switch_port3: port@3 { + reg = <0x3>; + status = "disabled"; + }; + + /* sgmii on addon board connector J21 */ + switch_port4: port@4 { + reg = <0x4>; + status = "disabled"; + }; + + /* 100base-t1 on addon board connector J21 */ + switch_port5: port@5 { + reg = <0x5>; + phy-handle = <&switch_port5_base_t1_phy>; + phy-mode = "internal"; + status = "disabled"; + }; + + /* 100base-t1 on addon board connector J21 */ + switch_port6: port@6 { + reg = <0x6>; + phy-handle = <&switch_port6_base_t1_phy>; + phy-mode = "internal"; + status = "disabled"; + }; + + /* 100base-t1 on addon board connector J21 */ + switch_port7: port@7 { + reg = <0x7>; + phy-handle = <&switch_port7_base_t1_phy>; + phy-mode = "internal"; + status = "disabled"; + }; + + /* 100base-t1 on addon board connector J21 */ + switch_port8: port@8 { + reg = <0x8>; + phy-handle = <&switch_port8_base_t1_phy>; + phy-mode = "internal"; + status = "disabled"; + }; + + /* 100base-t1 on addon board connector J21 */ + switch_port9: port@9 { + reg = <0x9>; + phy-handle = <&switch_port9_base_t1_phy>; + phy-mode = "internal"; + status = "disabled"; + }; + + /* 100Base-T1 on connector J26 */ + switch_port10: port@a { + reg = <0xa>; + phy-handle = <&switch_port10_base_t1_phy>; + phy-mode = "internal"; + }; + }; + + mdios { + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + compatible = "nxp,sja1110-base-t1-mdio"; + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + /* 100base-t1 on addon board connector J21 */ + switch_port5_base_t1_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x1>; + status = "disabled"; + }; + + /* 100base-t1 on addon board connector J21 */ + switch_port6_base_t1_phy: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x2>; + status = "disabled"; + }; + + /* 100base-t1 on addon board connector J21 */ + switch_port7_base_t1_phy: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x3>; + status = "disabled"; + }; + + /* 100base-t1 on addon board connector J21 */ + switch_port8_base_t1_phy: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x4>; + status = "disabled"; + }; + + /* 100base-t1 on addon board connector J21 */ + switch_port9_base_t1_phy: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x5>; + status = "disabled"; + }; + + /* 100Base-T1 on connector J26 */ + switch_port10_base_t1_phy: ethernet-phy@6 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x6>; + }; + }; + + mdio@1 { + compatible = "nxp,sja1110-base-tx-mdio"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* 100Base-TX on connector J26 */ + switch_port1_base_tx_phy: ethernet-phy@1 { + reg = <0x1>; + }; + }; + }; + }; +}; + +/* bluetooth */ +&lpuart1 { + pinctrl-0 = <&lpuart1_pins>, <&bluetooth_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&osc_32k>; + clock-names = "lpo"; + /* Murata 1MW module supports max. 3M baud */ + max-speed = <3000000>; + shutdown-gpios = <&lsio_gpio0 13 GPIO_ACTIVE_HIGH>; + /* link fixed supplies to avoid fall-back lookup by name */ + vbat-supply = <&v_3_3>; + vddio-supply = <&v_1_8>; + }; +}; + +&lsio_gpio1 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "CELL_RESET_N", "CELL_PWRKEY", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&usbotg1 { + dr_mode = "host"; + vbus-supply = <&vbus1>; +}; + +/* cellular modem */ +&usbotg2 { + #address-cells = <1>; + #size-cells = <0>; + adp-disable; + disable-over-current; + dr_mode = "host"; + hnp-disable; + pinctrl-0 = <&modem_pins>; + pinctrl-names = "default"; + power-active-high; + srp-disable; + vbus-supply = <&v_5_0>; + status = "okay"; + + usb-device@1 { + compatible = "usb2c7c,125"; + reg = <1>; + vbus-supply = <&v_3_3>; + vdd-supply = <&modem_vbat>; + }; +}; + +&usbphy2 { + status = "okay"; +}; + +/* WiFi */ +&usdhc3 { + bus-width = <4>; + cap-sdio-irq; + mmc-pwrseq = <&usdhc3_pwrseq>; + non-removable; + no-sd; + pinctrl-0 = <&usdhc3_pins>, <&wifi_pins>; + pinctrl-names = "default"; + vmmc-supply = <&v_3_3>; + vqmmc-supply = <&v_1_8>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-sr-som.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-sr-som.dtsi new file mode 100644 index 000000000000..93a0eb4d7f77 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-sr-som.dtsi @@ -0,0 +1,458 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022-2026 Josua Mayer + */ + +#include "imx8dxl.dtsi" +/ { + compatible = "solidrun,imx8dxl-sr-som", "fsl,imx8dxl"; + model = "SolidRun i.MX8DXL SoM"; + + aliases { + i2c2 = &i2c2; + i2c3 = &i2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &lpuart0; + serial2 = &lpuart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + imx8dxl-cm4 { + compatible = "fsl,imx8qxp-cm4"; + clocks = <&clk_dummy>; + mboxes = <&lsio_mu5 0 1 &lsio_mu5 1 1 &lsio_mu5 3 1>; + mbox-names = "tx", "rx", "rxdb"; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; + power-domains = <&pd IMX_SC_R_M4_0_PID0>, <&pd IMX_SC_R_M4_0_MU_1A>; + fsl,entry-address = <0x34fe0000>; + fsl,resource-id = ; + }; + + pps { + compatible = "pps-gpio"; + gpios = <&lsio_gpio2 6 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&gnss_pps_pins>; + pinctrl-names = "default"; + }; + + v_1_2: regulator-1-2 { + compatible = "regulator-fixed"; + regulator-name = "1v2"; + pinctrl-0 = <®ulator_1_2_pins>; + pinctrl-names = "default"; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1200000>; + gpio = <&lsio_gpio1 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + v_1_6: regulator-1-6 { + compatible = "regulator-fixed"; + regulator-name = "1v6"; + pinctrl-0 = <®ulator_1_6_pins>; + pinctrl-names = "default"; + regulator-max-microvolt = <1600000>; + regulator-min-microvolt = <1600000>; + vin-supply = <&v_1_8>; + gpio = <&lsio_gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + v_1_8: regulator-1-8 { + compatible = "regulator-fixed"; + regulator-name = "1v8"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + }; + + v_1_8_se: regulator-1-8-secure-element { + compatible = "regulator-fixed"; + regulator-name = "1v8-se"; + pinctrl-0 = <®ulator_1_8_se_pins>; + pinctrl-names = "default"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + vin-supply = <&v_1_8>; + gpio = <&lsio_gpio3 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + v_3_3: regulator-3-3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x98000000 0 0x14000000>; + reusable; + size = <0 0x14000000>; + linux,cma-default; + }; + + vdev0vring0: memory0@90000000 { + reg = <0 0x90000000 0 0x8000>; + no-map; + }; + + vdev0vring1: memory@90008000 { + reg = <0 0x90008000 0 0x8000>; + no-map; + }; + + vdev1vring0: memory@90010000 { + reg = <0 0x90010000 0 0x8000>; + no-map; + }; + + vdev1vring1: memory@90018000 { + reg = <0 0x90018000 0 0x8000>; + no-map; + }; + + rsc_table: memory-rsc-table@900ff000 { + reg = <0 0x900ff000 0 0x1000>; + no-map; + }; + + vdevbuffer: memory-vdevbuffer@90400000 { + compatible = "shared-dma-pool"; + reg = <0 0x90400000 0 0x100000>; + no-map; + }; + + /* + * Memory reserved for optee usage. Please do not use. + * This will be automatically added to dtb if OP-TEE is installed. + * optee@96000000 { + * reg = <0 0x96000000 0 0x2000000>; + * no-map; + * }; + */ + }; + + memory@80000000 { + reg = <0x00000000 0x80000000 0 0x40000000>; + device_type = "memory"; + }; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-0 = <&i2c2_pins>; + pinctrl-1 = <&i2c2_gpio_pins>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&lsio_gpio3 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&lsio_gpio3 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-0 = <&i2c3_pins>; + pinctrl-1 = <&i2c3_gpio_pins>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&lsio_gpio3 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&lsio_gpio3 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + magnetometer@1e { + compatible = "st,iis2mdc"; + reg = <0x1e>; + interrupt-parent = <&lsio_gpio2>; + interrupts = <10 IRQ_TYPE_EDGE_RISING>; + pinctrl-0 = <&magnetometer_pins>; + pinctrl-names = "default"; + st,drdy-int-pin = <1>; + }; + + /* pressure-sensor@5c */ + + inertial-sensor@6b { + compatible = "st,ism330dhcx"; + reg = <0x6b>; + interrupt-parent = <&lsio_gpio2>; + interrupts = <11 IRQ_TYPE_EDGE_RISING>; + pinctrl-0 = <&imu_pins>; + pinctrl-names = "default"; + st,drdy-int-pin = <1>; + }; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_hog>; + pinctrl-names = "default"; + + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD 0x000014a0 + >; + }; + + dsrc_pins: pinctrl-dsrc-grp { + fsl,pins = < + /* reset: io without pull */ + IMX8DXL_ADC_IN0_LSIO_GPIO1_IO10 0x0000060 + + /* + * boot0: io without pull + * After reset, this pin selects radio boot media: + * - 0: flash spi + * - 1: slave sdio + * Once the firmware boots however, the radio controls + * this pin for flow-control to signal readiness. + */ + IMX8DXL_ADC_IN1_LSIO_GPIO1_IO09 0x0000060 + >; + }; + + gnss_pins: pinctrl-gnss-grp { + fsl,pins = < + /* gps reset: input with pull-up */ + IMX8DXL_SNVS_TAMPER_OUT4_LSIO_GPIO2_IO08_IN 0x0000021 + /* gps interrupt: io without pull-up */ + IMX8DXL_SNVS_TAMPER_IN0_LSIO_GPIO2_IO09_IN 0x0000061 + >; + }; + + gnss_pps_pins: pinctrl-gnss-pps-grp { + fsl,pins = < + /* gps timepulse: input without pull-up */ + IMX8DXL_SNVS_TAMPER_OUT2_LSIO_GPIO2_IO06_IN 0x0000061 + >; + }; + + i2c2_gpio_pins: pinctrl-i2c2-gpio-grp { + fsl,pins = < + /* io with pull-up and weak drive */ + IMX8DXL_SPI1_SCK_LSIO_GPIO3_IO00 0x00000021 + /* io with pull-up, weak drive, open-drain */ + IMX8DXL_SPI1_SDO_LSIO_GPIO3_IO01 0x02000021 + >; + }; + + i2c2_pins: pinctrl-i2c2-grp { + fsl,pins = < + /* io with pull-up and weak drive */ + IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 0x06000021 + IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL 0x06000021 + >; + }; + + i2c3_gpio_pins: pinctrl-i2c3-gpio-grp { + fsl,pins = < + /* io with pull-up and weak drive */ + IMX8DXL_SPI1_CS0_LSIO_GPIO3_IO03 0x00000021 + /* io with pull-up, weak drive, open-drain */ + IMX8DXL_SPI1_SDI_LSIO_GPIO3_IO02 0x02000021 + >; + }; + + i2c3_pins: pinctrl-i2c3-grp { + fsl,pins = < + /* io with pull-up and weak drive */ + IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA 0x06000021 + IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL 0x06000021 + >; + }; + + imu_pins: pinctrl-imu-grp { + fsl,pins = < + /* interrupt: io with pull-down */ + IMX8DXL_SNVS_TAMPER_IN2_LSIO_GPIO2_IO11_IN 0x0000041 + >; + }; + + lpspi2_pins: pinctrl-lpspi2-grp { + fsl,pins = < + IMX8DXL_USDHC1_RESET_B_ADMA_SPI2_SCK 0x600004c + IMX8DXL_USDHC1_VSELECT_ADMA_SPI2_SDO 0x600004c + IMX8DXL_USDHC1_WP_ADMA_SPI2_SDI 0x600004c + IMX8DXL_USDHC1_CD_B_LSIO_GPIO4_IO22 0x6000021 + >; + }; + + lpuart0_pins: pinctrl-lpuart0-grp { + fsl,pins = < + IMX8DXL_UART0_RX_ADMA_UART0_RX 0x06000020 + IMX8DXL_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + + lpuart2_pins: pinctrl-lpuart2-grp { + fsl,pins = < + IMX8DXL_UART2_TX_ADMA_UART2_TX 0x06000020 + IMX8DXL_UART2_RX_ADMA_UART2_RX 0x06000020 + >; + }; + + magnetometer_pins: pinctrl-magnetometer-grp { + fsl,pins = < + /* interrupt: io with pull-down */ + IMX8DXL_SNVS_TAMPER_IN1_LSIO_GPIO2_IO10_IN 0x0000041 + >; + }; + + regulator_1_2_pins: pinctrl-regulator-1-2-grp { + fsl,pins = < + /* io without pull-up */ + /* has etxernal pull-down */ + IMX8DXL_ADC_IN5_LSIO_GPIO1_IO13 0x0000061 + >; + }; + + regulator_1_6_pins: pinctrl-regulator-1-6-grp { + fsl,pins = < + /* io without pull-up */ + /* has etxernal pull-down */ + IMX8DXL_ADC_IN4_LSIO_GPIO1_IO14 0x0000061 + >; + }; + + regulator_1_8_se_pins: pinctrl-regulator-1-8-secure-element-grp { + fsl,pins = < + /* v2x-secure-element power switch: io with pull-down */ + IMX8DXL_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x0000041 + >; + }; + + se_pins: pinctrl-secure-element-grp { + fsl,pins = < + /* v2x-secure-element reset: io with pull-up */ + IMX8DXL_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x0000021 + + /* + * v2x-secure-element gpio0: io with pull-up + * pulled low by sxf after boot indicating ready for commands + */ + IMX8DXL_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x0000021 + + /* v2x-secure-element gpio1: io with pull-up */ + IMX8DXL_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x0000021 + >; + }; + + usdhc1_pins: pinctrl-usdhc1-grp { + fsl,pins = < + IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + IMX8DXL_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000061 + >; + }; + + usdhc2_pins: pinctrl-usdhc2-grp { + fsl,pins = < + IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000040 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + >; + }; +}; + +&lpspi2 { + cs-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; + num-cs = <1>; + pinctrl-0 = <&lpspi2_pins>, <&se_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* console */ +&lpuart0 { + pinctrl-0 = <&lpuart0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* gnss */ +&lpuart2 { + pinctrl-0 = <&lpuart2_pins>, <&gnss_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&lsio_gpio3 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "SXF_RST", "SXF_GPIO0", "SXF_GPIO1", "", "", + "", "", "", "", "", "", "", ""; +}; + +&lsio_mu5 { + status = "okay"; +}; + +/* OTG port for boot */ +&usbotg1 { + adp-disable; + disable-over-current; + dr_mode = "peripheral"; + hnp-disable; + power-active-high; + srp-disable; + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; + +/* eMMC */ +&usdhc1 { + bus-width = <8>; + cap-mmc-hw-reset; + non-removable; + no-sd; + no-sdio; + pinctrl-0 = <&usdhc1_pins>; + pinctrl-1 = <&usdhc1_pins>; + pinctrl-2 = <&usdhc1_pins>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + vmmc-supply = <&v_3_3>; + vqmmc-supply = <&v_1_8>; + status = "okay"; +}; + +/* DSRC Radio */ +&usdhc2 { + bus-width = <4>; + keep-power-in-suspend; + max-frequency = <40000000>; + non-removable; + no-sd; + pinctrl-0 = <&usdhc2_pins>, <&dsrc_pins>; + pinctrl-names = "default"; + vmmc-supply = <&v_3_3>; + vqmmc-supply = <&v_1_8>; + status = "okay"; +}; From 7122bf640f679c84eb0cd5fecec356f0317c0c5f Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Fri, 29 May 2026 00:05:50 +0200 Subject: [PATCH 633/665] arm64: dts: imx95-var-dart-sonata: add TPM reset GPIO Add the reset GPIO for the TPM device on the Sonata carrier board and label the node accordingly. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts b/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts index 0f3d2e488f4a..d2c7d83e1624 100644 --- a/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts +++ b/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts @@ -274,6 +274,8 @@ pca6408_2: gpio@21 { st33ktpm2xi2c: tpm@2e { compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; reg = <0x2e>; + label = "tpm"; + reset-gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>; }; }; From 8f678b02bef832553622da6fac63ccb8b7af7942 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Thu, 28 May 2026 18:03:58 +0200 Subject: [PATCH 634/665] arm64: dts: imx95-var-dart-sonata: add CAN controller Add the MCP251xFD CAN controller connected to LPSPI7 chip select 1 on the Sonata carrier board. Add the second SPI chip select GPIO and describe the CAN interrupt and pinctrl configuration. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../dts/freescale/imx95-var-dart-sonata.dts | 27 ++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts b/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts index d2c7d83e1624..7a58ad38ffb4 100644 --- a/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts +++ b/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts @@ -168,6 +168,10 @@ &flexcan1 { status = "okay"; }; +&gpio1 { + status = "okay"; +}; + &lpi2c3 { clock-frequency = <400000>; pinctrl-names = "default", "gpio", "sleep"; @@ -282,7 +286,8 @@ st33ktpm2xi2c: tpm@2e { &lpspi7 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpspi7>; - cs-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>, + <&gpio1 7 GPIO_ACTIVE_LOW>; status = "okay"; /* Resistive touch controller */ @@ -308,6 +313,19 @@ ads7846: touchscreen@0 { ti,settle-delay-usec = /bits/ 16 <150>; ti,keep-vref-on; }; + + /* CAN controller */ + can0: can@1 { + compatible = "microchip,mcp251xfd"; + reg = <1>; + clocks = <&clk_osc_can0>; + interrupt-parent = <&gpio5>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + microchip,rx-int-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can>; + spi-max-frequency = <12000000>; + }; }; /* Console */ @@ -444,6 +462,13 @@ IMX95_PAD_GPIO_IO37__GPIO5_IO_BIT17 0x31e >; }; + pinctrl_can: cangrp { + fsl,pins = < + IMX95_PAD_GPIO_IO35__GPIO5_IO_BIT15 0x31e + IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22 0x31e + >; + }; + pinctrl_captouch: captouchgrp { fsl,pins = < IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x31e From 65210e81f7837a871a17237d15e4b1191d5e8771 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 28 May 2026 14:03:24 +0200 Subject: [PATCH 635/665] arm64: dts: s32g3: Fix SWT8 watchdog address Add missing hex annotation to fix the SWT8 watchdog address in 'reg' property, as reported by dtc W=1: s32g3.dtsi:863.27-869.5: Warning (simple_bus_reg): /soc@0/watchdog@40500000: simple-bus unit address format error, expected "269fb20" Lack of hex '0x' meant address would be interpreted as decimal thus completely different value used as this device MMIO. If device was enabled this could lead to corruption of other device address space and broken boot. Cc: stable@vger.kernel.org Fixes: 6db84f042745 ("arm64: dts: s32g3: Add the Software Timer Watchdog (SWT) nodes") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Daniel Lezcano Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/s32g3.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index 42646b2d16b0..6a1e0665d73e 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -900,7 +900,7 @@ gmac0mdio: mdio { swt8: watchdog@40500000 { compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; - reg = <40500000 0x1000>; + reg = <0x40500000 0x1000>; clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; clock-names = "counter", "module", "register"; status = "disabled"; From a1b81a560ef71db7dbe7eea4584c2424f1368b38 Mon Sep 17 00:00:00 2001 From: Khristine Andreea Barbulescu Date: Tue, 2 Jun 2026 12:23:51 +0200 Subject: [PATCH 636/665] arm64: dts: s32g: add PWM support for s32g2 and s32g3 Add PWM0 and PWM1 for S32G2 and S32G3 SoCs Reviewed-by: Enric Balletbo i Serra Signed-off-by: Khristine Andreea Barbulescu Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 26 +++++++ arch/arm64/boot/dts/freescale/s32g3.dtsi | 28 +++++++ .../boot/dts/freescale/s32gxxxa-evb.dtsi | 78 ++++++++++++++++++- 3 files changed, 131 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index a1f33197b4b0..809019ea0e29 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -563,6 +563,19 @@ i2c2: i2c@401ec000 { status = "disabled"; }; + pwm0: pwm@401f4000 { + compatible = "nxp,s32g2-ftm-pwm"; + reg = <0x401f4000 0x1000>; + #pwm-cells = <3>; + clocks = <&clks 5>, + <&clks 6>, + <&clks 5>, + <&clks 5>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + status = "disabled"; + }; + adc0: adc@401f8000 { compatible = "nxp,s32g2-sar-adc"; reg = <0x401f8000 0x1000>; @@ -745,6 +758,19 @@ i2c4: i2c@402dc000 { status = "disabled"; }; + pwm1: pwm@402e4000 { + compatible = "nxp,s32g2-ftm-pwm"; + reg = <0x402e4000 0x1000>; + #pwm-cells = <3>; + clocks = <&clks 7>, + <&clks 8>, + <&clks 7>, + <&clks 7>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + status = "disabled"; + }; + adc1: adc@402e8000 { compatible = "nxp,s32g2-sar-adc"; reg = <0x402e8000 0x1000>; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index 6a1e0665d73e..22e80fc03f9c 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -626,6 +626,20 @@ i2c2: i2c@401ec000 { status = "disabled"; }; + pwm0: pwm@401f4000 { + compatible = "nxp,s32g3-ftm-pwm", + "nxp,s32g2-ftm-pwm"; + reg = <0x401f4000 0x1000>; + #pwm-cells = <3>; + clocks = <&clks 5>, + <&clks 6>, + <&clks 5>, + <&clks 5>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + status = "disabled"; + }; + adc0: adc@401f8000 { compatible = "nxp,s32g3-sar-adc", "nxp,s32g2-sar-adc"; reg = <0x401f8000 0x1000>; @@ -820,6 +834,20 @@ i2c4: i2c@402dc000 { status = "disabled"; }; + pwm1: pwm@402e4000 { + compatible = "nxp,s32g3-ftm-pwm", + "nxp,s32g2-ftm-pwm"; + reg = <0x402e4000 0x1000>; + #pwm-cells = <3>; + clocks = <&clks 7>, + <&clks 8>, + <&clks 7>, + <&clks 7>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + status = "disabled"; + }; + adc1: adc@402e8000 { compatible = "nxp,s32g3-sar-adc", "nxp,s32g2-sar-adc"; reg = <0x402e8000 0x1000>; diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi index 803ff4531077..be7b645afa2d 100644 --- a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright 2024 NXP + * Copyright 2024, 2026 NXP * * Authors: Ciprian Marian Costea * Ghennadi Procopciuc @@ -245,6 +245,70 @@ dspi5-grp4 { bias-pull-up; }; }; + + ftm0_pins: ftm0-pins { + ftm0-grp0 { + pinmux = <0x2912>; + }; + + ftm0-grp1 { + pinmux = <0x122>, + <0xb42>; + output-enable; + input-enable; + }; + + ftm0-grp2 { + pinmux = <0xb13>, + <0xb53>; + output-enable; + input-enable; + }; + + ftm0-grp3 { + pinmux = <0x2904>; + }; + + ftm0-grp4 { + pinmux = <0x2925>; + }; + + ftm0-grp5 { + pinmux = <0x2936>; + }; + }; + + ftm1_pins: ftm1-pins { + ftm1-grp0 { + pinmux = <0x1d3>; + output-enable; + input-enable; + }; + + ftm1-grp1 { + pinmux = <0x29b4>; + }; + + ftm1-grp2 { + pinmux = <0x29c3>; + }; + + ftm1-grp3 { + pinmux = <0x1f4>; + output-enable; + input-enable; + }; + + ftm1-grp4 { + pinmux = <0x202>; + output-enable; + input-enable; + }; + + ftm1-grp5 { + pinmux = <0x29d2>; + }; + }; }; &can0 { @@ -293,6 +357,18 @@ &i2c4 { status = "okay"; }; +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&ftm0_pins>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&ftm1_pins>; + status = "okay"; +}; + &spi1 { pinctrl-0 = <&dspi1_pins>; pinctrl-names = "default"; From 91793f1429d26bf84dbbd7480d5c791703c0f9be Mon Sep 17 00:00:00 2001 From: Joseph Guo Date: Tue, 2 Jun 2026 12:45:15 +0900 Subject: [PATCH 637/665] dt-bindings: arm: fsl: Add i.MX95 19x19 FRDM PRO board Add the i.MX95 19x19 FRDM PRO board in the binding document. Reviewed-by: Daniel Baluta Acked-by: Conor Dooley Signed-off-by: Joseph Guo Signed-off-by: Frank Li --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 279e9a7e5f9e..a2cb7e43d657 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1498,6 +1498,7 @@ properties: - fsl,imx95-15x15-evk # i.MX95 15x15 EVK Board - fsl,imx95-15x15-frdm # i.MX95 15x15 FRDM Board - fsl,imx95-19x19-evk # i.MX95 19x19 EVK Board + - fsl,imx95-19x19-frdm-pro # i.MX95 19x19 FRDM PRO Board - toradex,verdin-imx95-19x19-evk # i.MX95 Verdin Evaluation Kit (EVK) - const: fsl,imx95 From 815fe2e0e65b42569f8c68dfa256c89db72e0b18 Mon Sep 17 00:00:00 2001 From: Joseph Guo Date: Tue, 2 Jun 2026 12:45:16 +0900 Subject: [PATCH 638/665] arm64: dts: freescale: add i.MX95 19x19 FRDM PRO board dts NXP i.MX95 19x19 FRDM PRO is cost-effective with extensive expansion capabilities based on the i.MX95 19x19 SoC. It is designed for AI and robotic situation. Difference with i.MX95 15x15 FRDM: - Use i.MX95 19x19 package - Support 2 KEY-M M.2 PCIE - 10G ETH interface - Secure Element interface Add device tree for this board. Including: - LPUART1 and LPUART5 - NETC - USB - 2 M-Key M.2 PCIe - uSDHC1, uSDHC2 and uSDHC3 - FlexCAN1 and FlexCAN3 (CAN1 is reserved by M7) - LPI2C3, LPI2C4 and their child nodes - Watchdog3 - SAI, MQS, MICFIL Signed-off-by: Joseph Guo Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx95-19x19-frdm-pro.dts | 1021 +++++++++++++++++ 2 files changed, 1022 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx95-19x19-frdm-pro.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 8473ebb44537..b975cf82d82d 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -636,6 +636,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-frdm.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-sof.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-frdm-pro.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-toradex-smarc-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596sa-mb-smarc-2.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-var-dart-sonata.dtb diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-frdm-pro.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-frdm-pro.dts new file mode 100644 index 000000000000..b87a26b0d7fc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-frdm-pro.dts @@ -0,0 +1,1021 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 NXP + */ + +/dts-v1/; + +#include +#include +#include "imx95.dtsi" + +#define FALLING_EDGE 1 +#define RISING_EDGE 2 + +#define BRD_SM_CTRL_SD3_WAKE 0x8000 /*!< PCAL6408A-0 */ +#define BRD_SM_CTRL_PCIE1_WAKE 0x8001 /*!< PCAL6408A-4 */ +#define BRD_SM_CTRL_BT_WAKE 0x8002 /*!< PCAL6408A-5 */ +#define BRD_SM_CTRL_PCIE2_WAKE 0x8003 /*!< PCAL6408A-6 */ +#define BRD_SM_CTRL_BUTTON 0x8004 /*!< PCAL6408A-7 */ + +/ { + model = "NXP FRDM-IMX95-PRO"; + compatible = "fsl,imx95-19x19-frdm-pro", "fsl,imx95"; + + aliases { + ethernet0 = &enetc_port0; + ethernet1 = &enetc_port1; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + i2c3 = &lpi2c4; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &lpuart1; + serial4 = &lpuart5; + }; + + bt_sco_codec: bt-sco-codec { + compatible = "linux,bt-sco"; + #sound-dai-cells = <1>; + }; + + flexcan1_phy: can-phy0 { + compatible = "nxp,tja1057"; + #phy-cells = <0>; + max-bitrate = <5000000>; + silent-gpios = <&i2c4_gpio_expander_22 11 GPIO_ACTIVE_HIGH>; + }; + + flexcan3_phy: can-phy2 { + compatible = "nxp,tja1057"; + #phy-cells = <0>; + max-bitrate = <5000000>; + silent-gpios = <&i2c4_gpio_expander_22 13 GPIO_ACTIVE_HIGH>; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + stdout-path = &lpuart1; + }; + + reg_vref_1v8: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "+V1.8_SW"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_SW"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + }; + + reg_dcdc_3v3: regulator-dcdc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "DCDC_3V3"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + vin-supply = <®_dcdc_5v>; + gpio = <&i2c4_gpio_expander_22 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_dcdc_5v: regulator-dcdc-5v { + compatible = "regulator-fixed"; + regulator-name = "DCDC_5V"; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + gpio = <&i2c4_gpio_expander_22 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_exp_1v8: regulator-exp-1v8 { + compatible = "regulator-fixed"; + regulator-name = "EXP_1V8"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + gpio = <&i2c4_gpio_expander_22 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_exp_3v3: regulator-exp-3v3 { + compatible = "regulator-fixed"; + regulator-name = "EXP_3V3"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + vin-supply = <®_dcdc_3v3>; + gpio = <&i2c4_gpio_expander_22 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_exp_5v: regulator-exp-5v { + compatible = "regulator-fixed"; + regulator-name = "EXP_5V"; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + vin-supply = <®_dcdc_5v>; + gpio = <&i2c4_gpio_expander_22 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_exp_12v: regulator-exp-12v { + compatible = "regulator-fixed"; + regulator-name = "VCCEXP_12V"; + regulator-always-on; + regulator-max-microvolt = <12000000>; + regulator-min-microvolt = <12000000>; + gpio = <&i2c4_gpio_expander_22 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_m2_mkey_1_pwr: regulator-m2-mkey-1-pwr { + compatible = "regulator-fixed"; + regulator-name = "M.2-power-mkey-1"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + gpio = <&i2c3_gpio_expander_20 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_m2_mkey_2_pwr: regulator-m2-mkey-2-pwr { + compatible = "regulator-fixed"; + regulator-name = "M.2-power-mkey-2"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + gpio = <&i2c3_gpio_expander_20 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_m2_ekey_pwr: regulator-m2-pwr { + compatible = "regulator-fixed"; + regulator-name = "M.2-power-ekey"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + gpio = <&i2c4_gpio_expander_22 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VDD_SD2_3V3"; + off-on-delay-us = <12000>; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible = "regulator-fixed"; + regulator-name = "WLAN_EN"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + vin-supply = <®_m2_ekey_pwr>; + gpio = <&i2c4_gpio_expander_22 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * IW612 wifi chip needs more delay than other wifi chips to complete + * the host interface initialization after power up, otherwise the + * internal state of IW612 may be unstable, resulting in the failure of + * the SDIO3.0 switch voltage. + */ + startup-delay-us = <20000>; + }; + + reg_usb_vbus: regulator-vbus { + compatible = "regulator-fixed"; + regulator-name = "USB_VBUS"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + gpio = <&i2c4_gpio_expander_22 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x7F000000>; + reusable; + size = <0 0x3c000000>; + linux,cma-default; + }; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-inversion; + simple-audio-card,bitclock-master = <&btcpu>; + simple-audio-card,format = "dsp_a"; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,name = "bt-sco-audio"; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + + btcpu: simple-audio-card,cpu { + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + sound-dai = <&sai5>; + }; + }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + + pri-dai-link { + format = "i2s"; + link-name = "micfil hifi"; + + cpu { + sound-dai = <&micfil>; + }; + }; + }; + + sound-mqs { + compatible = "audio-graph-card2"; + links = <&sai1_port1>; + label = "mqs-audio"; + }; + + usdhc3_pwrseq: usdhc3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&i2c4_gpio_expander_22 9 GPIO_ACTIVE_LOW>; + }; + + memory@80000000 { + reg = <0x0 0x80000000 0 0x80000000>; + device_type = "memory"; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&enetc_port0 { + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_enetc0>; + pinctrl-names = "default"; + status = "okay"; +}; + +&enetc_port1 { + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_enetc1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&flexcan1 { + phys = <&flexcan1_phy>; + pinctrl-0 = <&pinctrl_flexcan1>; + pinctrl-names = "default"; + status = "reserved"; +}; + +&flexcan3 { + phys = <&flexcan3_phy>; + pinctrl-0 = <&pinctrl_flexcan3>; + pinctrl-names = "default"; + status = "okay"; +}; + +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-names = "default"; + status = "okay"; + + i2c3_gpio_expander_20: i2c3-gpio-expander@20 { + compatible = "nxp,pcal6416"; + reg = <0x20>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio5>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + pinctrl-0 = <&pinctrl_pcal6416>; + pinctrl-names = "default"; + }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + interrupt-parent = <&gpio5>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_ptn5110>; + pinctrl-names = "default"; + + typec_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <0>; + power-role = "dual"; + self-powered; + sink-pdos = ; + source-pdos = ; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec_con_hs: endpoint { + remote-endpoint = <&usb3_data_hs>; + }; + }; + + port@1 { + reg = <1>; + + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; +}; + +&lpi2c4 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c4>; + pinctrl-names = "default"; + status = "okay"; + + i2c4_gpio_expander_22: i2c4-gpio-expander@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = "USB2 Power Enable", + "DCDC5V Enable", + "", + "SE Enable", + "", + "EXP 5V Enable", + "EXP 3V3 Enable", + "WIFI Power Enable", + "M2 DIS1 B", + "WIFI SD3 Reset", + "EXP 1V8 Enable", + "CAN1 Standby", + "M2 DIS2", + "CAN2 Standby", + "ETH 10G IO4", + "ETH 10G IO3", + "SPI3/GPIO select", + "EXP 12V Enable", + "DCDC 3V3 Enable", + "PCIE1 Reset", + "", + "ETH 10G CLK Enable", + "LVDS to HDMI converter IT6263 reset", + ""; + + /* When high, select lpspi; When low, select gpio. */ + lpspi-gpio-sel-hog { + gpios = <16 GPIO_ACTIVE_HIGH>; + gpio-hog; + output-high; + }; + }; +}; + +&lpuart1 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&lpuart5 { + /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&micfil { + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_PDM>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <49152000>; + #sound-dai-cells = <0>; + pinctrl-0 = <&pinctrl_pdm>; + pinctrl-names = "default"; + status = "okay"; +}; + +&mqs1 { + clocks = <&scmi_clk IMX95_CLK_SAI1>; + clock-names = "mclk"; + pinctrl-0 = <&pinctrl_mqs1>; + pinctrl-names = "default"; + status = "okay"; + + mqs1_port: port { + mqs1_ep: endpoint { + dai-format = "left_j"; + remote-endpoint = <&sai1_port1_ep>; + }; + }; +}; + +&netc_blk_ctrl { + status = "okay"; +}; + +&netc_emdio { + pinctrl-0 = <&pinctrl_emdio>; + pinctrl-names = "default"; + status = "okay"; + + ethphy0: ethernet-phy@1 { + reg = <1>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&i2c3_gpio_expander_20 1 GPIO_ACTIVE_LOW>; + }; + + ethphy1: ethernet-phy@2 { + reg = <2>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&i2c3_gpio_expander_20 2 GPIO_ACTIVE_LOW>; + }; +}; + +&netc_timer { + status = "okay"; +}; + +&netcmix_blk_ctrl { + status = "okay"; +}; + +&pcie0 { + pinctrl-0 = <&pinctrl_pcie0>; + pinctrl-names = "default"; + reset-gpio = <&i2c4_gpio_expander_22 19 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_m2_mkey_1_pwr>; + status = "okay"; +}; + +&pcie1 { + pinctrl-0 = <&pinctrl_pcie1>; + pinctrl-names = "default"; + reset-gpio = <&i2c3_gpio_expander_20 9 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_m2_mkey_2_pwr>; + status = "okay"; +}; + +&sai1 { + clocks = <&scmi_clk IMX95_CLK_BUSAON>, <&dummy>, + <&scmi_clk IMX95_CLK_SAI1>, <&dummy>, + <&dummy>, <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI1>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <24576000>; + #sound-dai-cells = <0>; + fsl,sai-mclk-direction-output; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* leave unconnected - no RX in the context of MQS */ + port@0 { + reg = <0>; + + endpoint { + }; + }; + + sai1_port1: port@1 { + reg = <1>; + mclk-fs = <512>; + + sai1_port1_ep: endpoint { + dai-format = "left_j"; + system-clock-direction-out; + bitclock-master; + frame-master; + remote-endpoint = <&mqs1_ep>; + }; + }; + }; +}; + +&sai5 { + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI5>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <12288000>; + #sound-dai-cells = <0>; + pinctrl-0 = <&pinctrl_sai5>; + pinctrl-names = "default"; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&scmi_iomuxc { + pinctrl-0 = <&pinctrl_hog>; + pinctrl-names = "default"; + + pinctrl_emdio: emdiogrp { + fsl,pins = < + IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x50e + IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e + >; + }; + + pinctrl_enetc0: enetc0grp { + fsl,pins = < + IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e + IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e + IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e + IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e + IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e + IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e + IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e + IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e + IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e + IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e + IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e + IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e + >; + }; + + pinctrl_enetc1: enetc1grp { + fsl,pins = < + IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x50e + IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x50e + IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x50e + IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x50e + IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e + IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x58e + IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e + IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x58e + IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e + IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e + IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e + IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x57e + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + IMX95_PAD_SAI1_TXD0__AONMIX_TOP_CAN1_TX 0x39e + IMX95_PAD_SAI1_TXC__AONMIX_TOP_CAN1_RX 0x39e + >; + }; + + pinctrl_flexcan3: flexcan3grp { + fsl,pins = < + IMX95_PAD_CCM_CLKO3__CAN3_TX 0x39e + IMX95_PAD_CCM_CLKO4__CAN3_RX 0x39e + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x31e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = < + IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e + IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e + >; + }; + + pinctrl_mqs1: mqs1grp { + fsl,pins = < + IMX95_PAD_SAI1_TXFS__AONMIX_TOP_MQS1_LEFT 0x31e + IMX95_PAD_SAI1_RXD0__AONMIX_TOP_MQS1_RIGHT 0x31e + >; + }; + + pinctrl_pcal6416: pcal6416grp { + fsl,pins = < + IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x4000031e + >; + }; + + pinctrl_pcie1: pcie1grp { + fsl,pins = < + IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x4000031e + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e + IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x31e + >; + }; + + pinctrl_ptn5110: ptn5110grp { + fsl,pins = < + IMX95_PAD_XSPI1_DQS__GPIO5_IO_BIT8 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0 0x31e + IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK 0x31e + IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC 0x31e + IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e + IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + IMX95_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + IMX95_PAD_DAP_TDI__LPUART5_RX 0x31e + IMX95_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + IMX95_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe + >; + }; +}; + +&scmi_misc { + nxp,ctrl-ids = ; +}; + +&thermal_zones { + pf09-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 2>; + + trips { + pf09_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf09_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + pf53arm-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 4>; + + cooling-maps { + map0 { + cooling-device = <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + trip = <&pf5301_alert>; + }; + }; + + trips { + pf5301_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf5301_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + pf53soc-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 3>; + + trips { + pf5302_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf5302_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; +}; + +&usb2 { + disable-over-current; + dr_mode = "host"; + vbus-supply = <®_usb_vbus>; + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + adp-disable; + dr_mode = "otg"; + hnp-disable; + role-switch-default-mode = "peripheral"; + srp-disable; + usb-role-switch; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status = "okay"; + + port { + usb3_data_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&usb3_phy { + orientation-switch; + fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <17>; + fsl,phy-pcs-tx-swing-full-percent = <100>; + fsl,phy-tx-preemp-amp-tune-microamp = <600>; + fsl,phy-tx-vboost-level-microvolt = <1156>; + fsl,phy-tx-vref-tune-percent = <100>; + status = "okay"; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; +}; + +&usdhc1 { + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc1>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + status = "okay"; +}; + +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + bus-width = <4>; + keep-power-in-suspend; + mmc-pwrseq = <&usdhc3_pwrseq>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc3_vmmc>; + wakeup-source; + status = "okay"; +}; + +&wdog3 { + status = "okay"; +}; From 748835fcb2eb2120234aef9556d282272501b96b Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 2 Jun 2026 11:33:30 +0200 Subject: [PATCH 639/665] arm64: dts: tqma8mpql-mba8mpxl: configure sai clock in audio codec as well With deferrable card binding the sound card driver tries to get the mclk configuration before it is setup in sai3 node. Fix this by setting the sai clock config for the audio codec as well. Fixes: d8f9d8126582 ("arm64: dts: imx8mp: Add analog audio output on i.MX8MP TQMa8MPxL/MBa8MPxL") Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index 890d1e525a48..6b0f944095e7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -609,6 +609,9 @@ tlv320aic3x04: audio-codec@18 { reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>; iov-supply = <®_vcc_1v8>; ldoin-supply = <®_vcc_3v3>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; }; se97_1c: temperature-sensor@1c { From 7858ac80e277ea28cb21313d396bea15e25ef53d Mon Sep 17 00:00:00 2001 From: Franz Schnyder Date: Thu, 21 May 2026 19:11:04 +0200 Subject: [PATCH 640/665] dt-bindings: arm: fsl: add Aquila iMX95 Add DT compatible strings for the Aquila i.MX95 SoM and its supported carrier boards: the Aquila Development Board and the Clover carrier board. Link: https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95 Link: https://www.toradex.com/products/carrier-board/aquila-development-board-kit Link: https://www.toradex.com/products/carrier-board/clover Acked-by: Conor Dooley Signed-off-by: Franz Schnyder Signed-off-by: Frank Li --- Documentation/devicetree/bindings/arm/fsl.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index a2cb7e43d657..263068dd7017 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1515,6 +1515,14 @@ properties: - const: phytec,imx95-phycore-fpsc # phyCORE-i.MX 95 FPSC - const: fsl,imx95 + - description: Toradex Boards with Aquila iMX95 Modules + items: + - enum: + - toradex,aquila-imx95-clover # Aquila iMX95 Module on Clover Board + - toradex,aquila-imx95-dev # Aquila iMX95 Module on Aquila Development Board + - const: toradex,aquila-imx95 # Aquila iMX95 Module + - const: fsl,imx95 + - description: Toradex Boards with SMARC iMX95 Modules items: - const: toradex,smarc-imx95-dev # Toradex SMARC iMX95 on Toradex SMARC Development Board From d5c082ba23db712b1f3f28bee7de34d6b9a05d91 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jo=C3=A3o=20Paulo=20Gon=C3=A7alves?= Date: Thu, 21 May 2026 19:11:05 +0200 Subject: [PATCH 641/665] arm64: dts: freescale: add Aquila iMX95 support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for the Toradex Aquila iMX95 and its development carrier board. The module consists of an NXP i.MX95 family SoC, up to 16GB LPDDR5 RAM, up to 128GB of storage, a USB 3.2 OTG and USB 2.0 Host, a Gigabit Ethernet PHY, a 10 Gigabit Ethernet interface, an I2C EEPROM and Temperature Sensor, an RX8130 RTC, one Quad lane CSI interface, one Quad lane DSI or CSI interface, one LVDS interface (one or two channels), and some optional addons: DisplayPort (through a DSI-DP bridge), TPM 2.0, and a WiFi/BT module. Link: https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95 Link: https://www.toradex.com/products/carrier-board/aquila-development-board-kit Signed-off-by: João Paulo Gonçalves Co-developed-by: Emanuele Ghidoli Signed-off-by: Emanuele Ghidoli Co-developed-by: Francesco Dolcini Signed-off-by: Francesco Dolcini Co-developed-by: Antoine Gouby Signed-off-by: Antoine Gouby Co-developed-by: Ernest Van Hoecke Signed-off-by: Ernest Van Hoecke Co-developed-by: Franz Schnyder Signed-off-by: Franz Schnyder Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx95-aquila-dev.dts | 389 ++++++ .../boot/dts/freescale/imx95-aquila.dtsi | 1160 +++++++++++++++++ 3 files changed, 1550 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx95-aquila-dev.dts create mode 100644 arch/arm64/boot/dts/freescale/imx95-aquila.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index b975cf82d82d..a4c54290f082 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -637,6 +637,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-frdm.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-sof.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-frdm-pro.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-aquila-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-toradex-smarc-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596sa-mb-smarc-2.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-var-dart-sonata.dtb diff --git a/arch/arm64/boot/dts/freescale/imx95-aquila-dev.dts b/arch/arm64/boot/dts/freescale/imx95-aquila-dev.dts new file mode 100644 index 000000000000..3df17700b632 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-aquila-dev.dts @@ -0,0 +1,389 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/aquila-development-board-kit + */ + +/dts-v1/; + +#include +#include +#include "imx95-aquila.dtsi" + +/ { + model = "Aquila iMX95 on Aquila Development Board"; + compatible = "toradex,aquila-imx95-dev", + "toradex,aquila-imx95", + "fsl,imx95"; + + aliases { + eeprom1 = &carrier_eeprom; + }; + + dp_1_connector: dp0-connector { + compatible = "dp-connector"; + dp-pwr-supply = <®_dp_3p3v>; + type = "full-size"; + + port { + dp_1_connector_in: endpoint { + remote-endpoint = <&dsi2dp_out>; + }; + }; + }; + + reg_carrier_1p8v: regulator-carrier-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-carrier 1V8"; + }; + + reg_dp_3p3v: regulator-dp-3p3v { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_21_dp>; + /* Aquila GPIO_21_DP */ + gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "DP_3V3"; + startup-delay-us = <10000>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "aquila-wm8904"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Microphone Jack", "MICBIAS", + "IN1L", "Microphone Jack", + "IN1R", "Digital Mic"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Microphone", "Digital Mic", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904_1a>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + }; +}; + +/* Aquila ADC_[1-4] */ +&adc1 { + status = "okay"; +}; + +/* Aquila CTRL_WAKE1_MICO# */ +&aquila_key_wake { + status = "okay"; +}; + +&dsi2dp_out { + remote-endpoint = <&dp_1_connector_in>; +}; + +/* Aquila ETH_1 */ +&enetc_port0 { + status = "okay"; +}; + +/* Aquila CAN_1 */ +&flexcan1 { + status = "okay"; +}; + +/* Aquila CAN_2 */ +&flexcan2 { + status = "okay"; +}; + +/* Aquila CAN_3 */ +&flexcan3 { + status = "okay"; +}; + +/* Aquila CAN_4 */ +&flexcan4 { + status = "okay"; +}; + +/* Aquila QSPI_1 */ +&flexspi1 { + pinctrl-0 = <&pinctrl_flexspi1_4bit>, + <&pinctrl_qspi_cs1>; + + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <66000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_8>; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_1>, + <&pinctrl_gpio_2>, + <&pinctrl_gpio_3>, + <&pinctrl_gpio_4>, + <&pinctrl_gpio_5>, + <&pinctrl_gpio_6>, + <&pinctrl_gpio_7>; +}; + +/* Aquila I2C_1 */ +&lpi2c2 { + status = "okay"; + + fan_controller: fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + #pwm-cells = <2>; + + fan { + cooling-levels = <255>; + pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>; + }; + }; + + wm8904_1a: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2_mclk>; + clocks = <&scmi_clk IMX95_CLK_SAI2>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + AVDD-supply = <®_carrier_1p8v>; + CPVDD-supply = <®_carrier_1p8v>; + DBVDD-supply = <®_carrier_1p8v>; + DCVDD-supply = <®_carrier_1p8v>; + MICVDD-supply = <®_carrier_1p8v>; + wlf,drc-cfg-names = "default", "peaklimiter"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>; + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; + wlf,in1r-as-dmicdat2; + }; + + /* Current measurement into module VCC */ + hwmon@41 { + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + + temperature-sensor@4f { + compatible = "ti,tmp1075"; + reg = <0x4f>; + }; + + /* USB-C OTG (TCPC USB PD PHY) */ + tcpc@52 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x52>; + interrupt-parent = <&som_gpio_expander_1>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + op-sink-microwatt = <0>; + power-role = "dual"; + self-powered; + sink-pdos = ; + source-pdos = ; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec_con_hs: endpoint { + remote-endpoint = <&usb1_con_hs>; + }; + }; + + port@1 { + reg = <1>; + + typec_con_ss: endpoint { + remote-endpoint = <&usb1_con_ss>; + }; + }; + }; + }; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Aquila I2C_2 */ +&i3c2 { + status = "okay"; +}; + +/* Aquila I2C_4_CSI1 */ +&lpi2c4 { + status = "okay"; +}; + +/* Aquila I2C_6 */ +&lpi2c5 { + status = "okay"; +}; + +/* Aquila I2C_3_DSI1/I2C_5_CSI2 */ +&lpi2c8 { + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9543"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + /* I2C on DSI Connector Pin #4 and #6 */ + i2c_dsi_0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* I2C on DSI Connector Pin #52 and #54 */ + i2c_dsi_1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +/* Aquila SPI_1 */ +&lpspi6 { + status = "okay"; +}; + +/* Aquila UART_3, used as the Linux Console */ +&lpuart1 { + status = "okay"; +}; + +/* Aquila UART_4 */ +&lpuart2 { + status = "okay"; +}; + +/* Aquila UART_1 */ +&lpuart3 { + status = "okay"; +}; + +/* Aquila UART_2 as RS485 */ +&lpuart7 { + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; + + status = "okay"; +}; + +/* Aquila PCIE_1 */ +&pcie0 { + status = "okay"; +}; + +/* Aquila I2S_1 */ +&sai2 { + status = "okay"; +}; + +/* Aquila PWM_1 */ +&tpm3 { + status = "okay"; +}; + +/* Aquila PWM_2 */ +&tpm6 { + status = "okay"; +}; + +/* Aquila PWM_3_DSI and PWM_4_DP */ +&tpm5 { + status = "okay"; +}; + +/* Aquila USB_2, optional Bluetooth USB */ +&usb2 { + status = "okay"; +}; + +/* Aquila USB_1 */ +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + status = "okay"; + + port { + usb1_con_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&usb3_phy { + orientation-switch; + + status = "okay"; + + port { + usb1_con_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; +}; + +/* Aquila SD_1 */ +&usdhc2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-aquila.dtsi b/arch/arm64/boot/dts/freescale/imx95-aquila.dtsi new file mode 100644 index 000000000000..69dc962a24a1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-aquila.dtsi @@ -0,0 +1,1160 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95 + */ + +#include +#include "imx95.dtsi" + +/ { + aliases { + can0 = &flexcan1; + can1 = &flexcan2; + can2 = &flexcan3; + can3 = &flexcan4; + eeprom0 = &som_eeprom; + ethernet0 = &enetc_port0; + i2c0 = &lpi2c3; + i2c1 = &lpi2c2; + i2c2 = &i3c2; + i2c3 = &lpi2c8; + i2c4 = &lpi2c4; + i2c6 = &lpi2c5; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + rtc0 = &rtc_i2c; + rtc1 = &scmi_bbm; + serial0 = &lpuart3; + serial1 = &lpuart7; + serial2 = &lpuart1; + serial3 = &lpuart2; + usb0 = &usb3; + usb1 = &usb2; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + aquila_key_wake: gpio-key-wakeup { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_wake1_mico>; + + status = "disabled"; + + key-wakeup { + /* Aquila CTRL_WAKE1_MICO# */ + gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + label = "Wake Up"; + wakeup-source; + linux,code = ; + }; + }; + + clk_dsi2dp_refclk: clock-dsi2dp-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; + + clk_dsi2dp_refclk_en: clock-dsi2dp-refclk-en { + compatible = "gpio-gate-clock"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_dp_clk_en>; + clocks = <&clk_dsi2dp_refclk>; + #clock-cells = <0>; + /* CTRL_DP_CLK_EN */ + enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + }; + + clk_serdes_eth_ref: clock-serdes-eth-ref { + compatible = "gpio-gate-clock"; + #clock-cells = <0>; + /* CTRL_ETH_REF_CLK_STBY */ + enable-gpios = <&som_gpio_expander_0 6 GPIO_ACTIVE_LOW>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-module +V1.8"; + }; + + reg_dp_1p2v: regulator-dp-1p2v { + compatible = "regulator-fixed"; + /* CTRL_DP_BRIDGE_EN */ + gpios = <&som_gpio_expander_0 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1200000>; + regulator-name = "On-module +V1.2_DP"; + vin-supply = <®_1p8v>; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + /* Aquila USB_1_EN */ + gpios = <&som_gpio_expander_0 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "USB_1_EN"; + }; + + reg_usb2_vbus: regulator-usb2-vbus { + compatible = "regulator-fixed"; + /* Aquila USB_2_EN */ + gpios = <&som_gpio_expander_0 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "USB_2_H_EN"; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1_pwr_en>; + /* Aquila SD_1_PWR_EN */ + gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <100000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "SD_1_PWR_EN"; + startup-delay-us = <20000>; + }; + + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { + compatible = "regulator-gpio"; + /* PMIC_SD_1_VSEL */ + gpios = <&som_gpio_expander_1 9 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "PMIC_SD_1_VSEL"; + states = <1800000 0x1>, + <3300000 0x0>; + }; + + remoteproc-cm7 { + compatible = "fsl,imx95-cm7"; + mboxes = <&mu7 0 1 &mu7 1 1 &mu7 3 1>; + mbox-names = "tx", "rx", "rxdb"; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>, <&m7_reserved>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x80000000 0 0x7f000000>; + linux,cma-default; + }; + + m7_reserved: memory@80000000 { + reg = <0 0x80000000 0 0x1000000>; + no-map; + }; + + rsc_table: rsc-table@88220000 { + reg = <0 0x88220000 0 0x1000>; + no-map; + }; + + vdev0vring0: vdev0vring0@88000000 { + reg = <0 0x88000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@88008000 { + reg = <0 0x88008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@88010000 { + reg = <0 0x88010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@88018000 { + reg = <0 0x88018000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer@88020000 { + compatible = "shared-dma-pool"; + reg = <0 0x88020000 0 0x100000>; + no-map; + }; + }; +}; + +/* Aquila ADC_[1-4] */ +&adc1 { + vref-supply = <®_1p8v>; +}; + +/* Aquila ETH_1 */ +&enetc_port0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc0>; + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; +}; + +/* Aquila CAN_1 */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; +}; + +/* Aquila CAN_2 */ +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; +}; + +/* Aquila CAN_3 */ +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; +}; + +/* Aquila CAN_4 */ +&flexcan4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan4>; +}; + +/* Aquila QSPI_1 */ +&flexspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi1_8bit>, + <&pinctrl_qspi_cs1>; +}; + +&gpio1 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "AQUILA_C24", /* 10 */ + "", + "AQUILA_B17", + "CTRL_GPIO_EXP_INT#", + "AQUILA_B18"; + + status = "okay"; +}; + +&gpio2 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "AQUILA_B42", + "", + "AQUILA_B43"; +}; + +&gpio3 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "AQUILA_A11", + "", /* 20 */ + "AQUILA_B57", + "AQUILA_B19"; +}; + +&gpio4 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "AQUILA_C22", + "AQUILA_C21", + "AQUILA_C20", + "", /* 20 */ + "", + "", + "AQUILA_C23", + "AQUILA_D23", + "AQUILA_D24", + "", + "AQUILA_D25"; +}; + +&gpio5 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "AQUILA_B44", + "AQUILA_B45"; +}; + +/* Aquila I2C_2 */ +&i3c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i3c2>; + i2c-scl-hz = <100000>; +}; + +/* Aquila I2C_1 */ +&lpi2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2_gpio>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* On-module I2C - I2C_SOM */ +&lpi2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c3>, <&pinctrl_ctrl_gpio_exp_int>; + pinctrl-1 = <&pinctrl_lpi2c3_gpio>, <&pinctrl_ctrl_gpio_exp_int>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + status = "okay"; + + som_gpio_expander_0: gpio@20 { + compatible = "nxp,pcal6408"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = + "AQUILA_C38", /* 0 */ + "PCIE_2_RESET#", + "AQUILA_B77", + "USB_2_H_EN", + "BT_DISABLE#", + "WIFI_DISABLE#", + "CTRL_ETH_REF_CLK_STBY", + "CTRL_DP_BRIDGE_EN"; + }; + + som_gpio_expander_1: gpio@21 { + compatible = "nxp,pcal6416"; + reg = <0x21>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio1>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = + "AQUILA_C1", /* 0 */ + "AQUILA_C2", + "AQUILA_C3", + "AQUILA_C4", + "AQUILA_C36", + "AQUILA_B74", + "AQUILA_B75", + "USB_2_H_OC#", + "AQUILA_B81", + "PMIC_SD_1_VSEL", + "ETH_1_INT#", /* 10 */ + "CTRL_TPM_INT#", + "SPI_2_CS2_TPM", + "PCIE_WAKE_WIFI#", + "WIFI_WAKE_BT", + "WIFI_WAKEUP_HOST"; + }; + + som_dsi2dp_bridge: bridge@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + clocks = <&clk_dsi2dp_refclk_en>; + clock-names = "refclk"; + vcc-supply = <®_dp_1p2v>; + vcca-supply = <®_dp_1p2v>; + vccio-supply = <®_1p8v>; + vpll-supply = <®_1p8v>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi2dp_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + + dsi2dp_out: endpoint { + data-lanes = <3 2 1 0>; + }; + }; + }; + }; + + rtc_i2c: rtc@32 { + compatible = "epson,rx8130"; + reg = <0x32>; + }; + + temperature-sensor@48 { + compatible = "ti,tmp1075"; + reg = <0x48>; + }; + + som_eeprom: eeprom@50 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +/* Aquila I2C_4_CSI1 */ +&lpi2c4 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c4>; + pinctrl-1 = <&pinctrl_lpi2c4_gpio>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + scl-gpios = <&gpio2 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* Aquila I2C_6 */ +&lpi2c5 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c5>; + pinctrl-1 = <&pinctrl_lpi2c5_gpio>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + scl-gpios = <&gpio2 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* Aquila I2C_3_DSI1/I2C_5_CSI2 */ +&lpi2c8 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c8>; + pinctrl-1 = <&pinctrl_lpi2c8_gpio>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + scl-gpios = <&gpio2 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* Aquila SPI_2 */ +&lpspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi4>; + cs-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>, + <&som_gpio_expander_1 12 GPIO_ACTIVE_LOW>; + + status = "okay"; + + som_tpm: tpm@1 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0x1>; + interrupt-parent = <&som_gpio_expander_1>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + /* + * Maximum TPM-supported speed is 18.5 MHz, limited to 12 MHz + * here as lpspi4's per-clock (2x the max speed) is 24 MHz. + */ + spi-max-frequency = <12000000>; + }; +}; + +/* Aquila SPI_1 */ +&lpspi6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi6>; + cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; +}; + +/* Aquila UART_3, used as the Linux Console */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +/* Aquila UART_4 */ +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; + +/* Aquila UART_1 */ +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; +}; + +/* Aquila UART_2 */ +&lpuart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + uart-has-rtscts; +}; + +&mu7 { + status = "okay"; +}; + +/* Aquila ETH_2_XGMII_MDIO, shared between all ethernet ports */ +&netc_emdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emdio>; + + status = "okay"; + + ethphy1: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&som_gpio_expander_1>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + }; +}; + +&netcmix_blk_ctrl { + status = "okay"; +}; + +&netc_blk_ctrl { + status = "okay"; +}; + +&netc_timer { + status = "okay"; +}; + +/* Aquila PCIE_1 */ +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpios = <&som_gpio_expander_0 0 GPIO_ACTIVE_LOW>; +}; + +/* On-module Wi-Fi or Aquila PCIE_2 */ +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + reset-gpios = <&som_gpio_expander_0 1 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +/* Aquila I2S_1 */ +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI2>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <12288000>; + #sound-dai-cells = <0>; + fsl,sai-mclk-direction-output; +}; + +&scmi_bbm { + linux,code = ; +}; + +&thermal_zones { + /* PF09 Main PMIC */ + pf09-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 2>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + /* PF53 VDD_ARM PMIC */ + pf53-arm-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 4>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + /* PF53 VDD_SOC PMIC */ + pf53-soc-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 3>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; +}; + +/* Aquila PWM_1 */ +&tpm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; +}; + +/* Aquila PWM_2 */ +&tpm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; +}; + +/* Aquila PWM_3_DSI and PWM_4_DP */ +&tpm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3_dsi>, <&pinctrl_pwm4_dp>; +}; + +/* Aquila USB_2, optional Bluetooth USB */ +&usb2 { + dr_mode = "host"; + vbus-supply = <®_usb2_vbus>; +}; + +/* Aquila USB_1 */ +&usb3 { + fsl,disable-port-power-control; +}; + +&usb3_dwc3 { + dr_mode = "otg"; + adp-disable; + hnp-disable; + srp-disable; + usb-role-switch; +}; + +&usb3_phy { + vbus-supply = <®_usb1_vbus>; +}; + +/* On-module eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + + status = "okay"; +}; + +/* Aquila SD_1 */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_sd1_cd_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_sd1_cd_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>,<&pinctrl_sd1_cd_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_sd1_cd_gpio>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <®_usdhc2_vqmmc>; +}; + +&wdog3 { + fsl,ext-reset-output; + + status = "okay"; +}; + +&scmi_iomuxc { + /* Aquila CTRL_WAKE1_MICO# */ + pinctrl_ctrl_wake1_mico: ctrlwake1micogrp { + fsl,pins = ; /* Aquila D6 */ + }; + + pinctrl_ctrl_dp_clk_en: dpclkengrp { + fsl,pins = ; /* CTRL_DP_CLK_EN */ + }; + + /* Aquila ETH_2_XGMII_MDIO */ + pinctrl_emdio: emdiogrp { + fsl,pins = , /* Aquila B90 */ + ; /* Aquila B89 */ + }; + + /* Aquila ETH_1 */ + pinctrl_enetc0: enetc0grp { + fsl,pins = , /* ENET1_TX_CTL */ + , /* ENET1_TXC */ + , /* ENET1_TDO */ + , /* ENET1_TD1 */ + , /* ENET1_TD2 */ + , /* ENET1_TD3 */ + , /* ENET1_RX_CTL */ + , /* ENET1_RXC */ + , /* ENET1_RD0 */ + , /* ENET1_RD1 */ + , /* ENET1_RD2 */ + ; /* ENET1_RD3 */ + }; + + /* Aquila CAN_1 */ + pinctrl_flexcan1: flexcan1grp { + fsl,pins = , /* Aquila B48 */ + ; /* Aquila B49 */ + }; + + /* Aquila CAN_2 */ + pinctrl_flexcan2: flexcan2grp { + fsl,pins = , /* Aquila B50 */ + ; /* Aquila B51 */ + }; + + /* Aquila CAN_3 */ + pinctrl_flexcan3: flexcan3grp { + fsl,pins = , /* Aquila B53 */ + ; /* Aquila B54 */ + }; + + /* Aquila CAN_4 */ + pinctrl_flexcan4: flexcan4grp { + fsl,pins = , /* Aquila B55 */ + ; /* Aquila B56 */ + }; + + /* Aquila QSPI_1 (4 bit) */ + pinctrl_flexspi1_4bit: flexspi14bitgrp { + fsl,pins = , /* Aquila B65 */ + , /* Aquila B68 */ + , /* Aquila B67 */ + , /* Aquila B61 */ + , /* Aquila B60 */ + ; /* Aquila B63 */ + }; + + /* Aquila QSPI_1 (8 bit) */ + pinctrl_flexspi1_8bit: flexspi18bitgrp { + fsl,pins = , /* Aquila B65 */ + , /* Aquila B68 */ + , /* Aquila B67 */ + , /* Aquila B61 */ + , /* Aquila B60 */ + , /* Aquila B70 */ + , /* Aquila B71 */ + , /* Aquila B72 */ + , /* Aquila B73 */ + ; /* Aquila B63 */ + }; + + /* Aquila GPIO_01 */ + pinctrl_gpio_1: gpio1grp { + fsl,pins = ; /* Aquila D23 */ + }; + + /* Aquila GPIO_02 */ + pinctrl_gpio_2: gpio2grp { + fsl,pins = ; /* Aquila D24 */ + }; + + /* Aquila GPIO_03 */ + pinctrl_gpio_3: gpio3grp { + fsl,pins = ; /* Aquila D25 */ + }; + + /* Aquila GPIO_04 */ + pinctrl_gpio_4: gpio4grp { + fsl,pins = ; /* Aquila C20 */ + }; + + /* Aquila GPIO_05 */ + pinctrl_gpio_5: gpio5grp { + fsl,pins = ; /* Aquila C21 */ + }; + + /* Aquila GPIO_06 */ + pinctrl_gpio_6: gpio6grp { + fsl,pins = ; /* Aquila C22 */ + }; + + /* Aquila GPIO_07 */ + pinctrl_gpio_7: gpio7grp { + fsl,pins = ; /* Aquila C23 */ + }; + + /* Aquila GPIO_08 */ + pinctrl_gpio_8: gpio8grp { + fsl,pins = ; /* Aquila C24 */ + }; + + /* Aquila GPIO_09_CSI_1 */ + pinctrl_gpio_9_csi_1: gpio9csi1grp { + fsl,pins = ; /* Aquila B17 */ + }; + + /* Aquila GPIO_10_CSI_1 */ + pinctrl_gpio_10_csi_1: gpio10csi1grp { + fsl,pins = ; /* Aquila B18 */ + }; + + /* Aquila GPIO_11_CSI_1 */ + pinctrl_gpio_11_csi_1: gpio11csi1grp { + fsl,pins = ; /* Aquila A11*/ + }; + + /* Aquila GPIO_12_CSI_1 */ + pinctrl_gpio_12_csi_1: gpio12csi1grp { + fsl,pins = ; /* Aquila B19 */ + }; + + /* Aquila GPIO_17_DSI_1 */ + pinctrl_gpio_17_dsi_1: gpio17dsi1grp { + fsl,pins = ; /* Aquila B42 */ + }; + + /* Aquila GPIO_18_DSI_1 */ + pinctrl_gpio_18_dsi_1: gpio18dsi1grp { + fsl,pins = ; /* Aquila B43 */ + }; + + /* Aquila GPIO_19_DSI_1 */ + pinctrl_gpio_19_dsi_1: gpio19dsi1grp { + fsl,pins = ; /* Aquila B44 */ + }; + + /* Aquila GPIO_20_DSI_1 */ + pinctrl_gpio_20_dsi_1: gpio20dsi1grp { + fsl,pins = ; /* Aquila B45 */ + }; + + /* Aquila GPIO_21_DP */ + pinctrl_gpio_21_dp: gpio21dpgrp { + fsl,pins = ; /* Aquila B57 */ + }; + + pinctrl_ctrl_gpio_exp_int: gpioexpintgrp { + fsl,pins = ; /* CTRL_GPIO_EXP_INT# */ + }; + + /* Aquila I2C_2 */ + pinctrl_i3c2: i3c2cgrp { + fsl,pins = , /* Aquila C17 */ + ; /* Aquila C16 */ + }; + + /* Aquila I2C_1 as GPIOs */ + pinctrl_lpi2c2_gpio: lpi2c2gpiogrp { + fsl,pins = , /* Aquila D8 */ + ; /* Aquila D7 */ + }; + + /* Aquila I2C_1 */ + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = , /* Aquila D8 */ + ; /* Aquila D7 */ + }; + + /* On-module I2C as GPIOs */ + pinctrl_lpi2c3_gpio: lpi2c3gpiogrp { + fsl,pins = , /* I2C_SOM_SDA */ + ; /* I2C_SOM_SCL */ + }; + + /* On-module I2C */ + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = , /* I2C_SOM_SDA */ + ; /* I2C_SOM_SCL */ + }; + + /* Aquila I2C_4_CSI1 as GPIO */ + pinctrl_lpi2c4_gpio: lpi2c4gpiogrp { + fsl,pins = , /* Aquila A12 */ + ; /* Aquila A13 */ + }; + + /* Aquila I2C_4_CSI1 */ + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = , /* Aquila A12 */ + ; /* Aquila A13 */ + }; + + /* Aquila I2C_6 as GPIO */ + pinctrl_lpi2c5_gpio: lpi2c5gpiogrp { + fsl,pins = , /* Aquila C18 */ + ; /* Aquila C19 */ + }; + + /* Aquila I2C_6 */ + pinctrl_lpi2c5: lpi2c5grp { + fsl,pins = , /* Aquila C18 */ + ; /* Aquila C19 */ + }; + + /* Aquila I2C_3_DSI1/I2C_5_CSI2 as GPIO */ + pinctrl_lpi2c8_gpio: lpi2c8gpiogrp { + fsl,pins = , /* Aquila C5/B40 */ + ; /* Aquila C6/B41 */ + }; + + /* Aquila I2C_3_DSI1/I2C_5_CSI2 */ + pinctrl_lpi2c8: lpi2c8grp { + fsl,pins = , /* Aquila C5/B40 */ + ; /* Aquila C6/B41 */ + }; + + /* Aquila SPI_2 */ + pinctrl_lpspi4: lpspi4grp { + fsl,pins = , /* Aquila D16 */ + , /* Aquila D15 */ + , /* Aquila D17 */ + ; /* Aquila D14 */ + }; + + /* Aquila SPI_1 */ + pinctrl_lpspi6: lpspi6grp { + fsl,pins = , /* Aquila D9 */ + , /* Aquila D10 */ + , /* Aquila D11 */ + ; /* Aquila D12 */ + }; + + /* Aquila PCIE_1 */ + pinctrl_pcie0: pcie0grp { + fsl,pins = ; /* Aquila C37 */ + }; + + /* Aquila PCIE_2 */ + pinctrl_pcie1: pcie1grp { + fsl,pins = ; /* Aquila C34 */ + }; + + /* Aquila QSPI_1_CS1# */ + pinctrl_qspi_cs1: qspics1grp { + fsl,pins = ; /* Aquila B66 */ + }; + + /* Aquila QSPI_1_CS2# as GPIO */ + pinctrl_qspi_cs2_gpio: qspics2gpiogrp { + fsl,pins = ; /* Aquila B62 */ + }; + + /* Aquila I2S_1 */ + pinctrl_sai2: sai2grp { + fsl,pins = , /* Aquila B21 */ + , /* Aquila B20 */ + , /* Aquila B23 */ + ; /* Aquila B22 */ + }; + + pinctrl_sai2_mclk: sai2mclkgrp { + fsl,pins = ; /* Aquila B24 */ + }; + + /* Aquila SD_1_CD# as GPIO */ + pinctrl_sd1_cd_gpio: sd1cdgpiogrp { + fsl,pins = ; /* Aquila A1 */ + }; + + /* Aquila SD_1_PWR_EN */ + pinctrl_sd1_pwr_en: sd1pwrengpiogrp { + fsl,pins = ; /* Aquila A6 */ + }; + + /* Aquila PWM_1 */ + pinctrl_pwm1: tpm3ch3grp { + fsl,pins = ; /* Aquila C25 */ + }; + + /* Aquila PWM_3_DSI as GPIO */ + pinctrl_pwm3_dsi_gpio: tpm5ch0gpiogrp { + fsl,pins = ; /* Aquila B46 */ + }; + + /* Aquila PWM_3_DSI */ + pinctrl_pwm3_dsi: tpm5ch0grp { + fsl,pins = ; /* Aquila B46 */ + }; + + /* Aquila PWM_4_DP */ + pinctrl_pwm4_dp: tpm5ch3grp { + fsl,pins = ; /* Aquila B58 */ + }; + + /* Aquila PWM_2 */ + pinctrl_pwm2: tpm6ch0grp { + fsl,pins = ; /* Aquila C26 */ + }; + + /* Aquila UART_3 */ + pinctrl_uart1: uart1grp { + fsl,pins = , /* Aquila D20 */ + ; /* Aquila D19 */ + }; + + /* Aquila UART_4 */ + pinctrl_uart2: uart2grp { + fsl,pins = , /* Aquila D22 */ + ; /* Aquila D21 */ + }; + + /* Aquila UART_1 */ + pinctrl_uart3: uart3grp { + fsl,pins = , /* Aquila B37 */ + , /* Aquila B35 */ + , /* Aquila B36 */ + ; /* Aquila B38 */ + }; + + /* Aquila UART_2 */ + pinctrl_uart7: uart7grp { + fsl,pins = , /* Aquila B33 */ + , /* Aquila B31 */ + , /* Aquila B32 */ + ; /* Aquila B34 */ + }; + + /* On-module eMMC */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = , /* eMMC_CLK */ + , /* eMMC_CMD */ + , /* eMMC_DATA0 */ + , /* eMMC_DATA1 */ + , /* eMMC_DATA2 */ + , /* eMMC_DATA3 */ + , /* eMMC_DATA4 */ + , /* eMMC_DATA5 */ + , /* eMMC_DATA6 */ + , /* eMMC_DATA7 */ + ; /* eMMC_STROBE */ + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = , /* eMMC_CLK */ + , /* eMMC_CMD */ + , /* eMMC_DATA0 */ + , /* eMMC_DATA1 */ + , /* eMMC_DATA2 */ + , /* eMMC_DATA3 */ + , /* eMMC_DATA4 */ + , /* eMMC_DATA5 */ + , /* eMMC_DATA6 */ + , /* eMMC_DATA7 */ + ; /* eMMC_STROBE */ + }; + + /* Aquila SD_1 */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = , /* Aquila A5 */ + , /* Aquila A7 */ + , /* Aquila A3 */ + , /* Aquila A2 */ + , /* Aquila A10 */ + ; /* Aquila A8 */ + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = , /* Aquila A5 */ + , /* Aquila A7 */ + , /* Aquila A3 */ + , /* Aquila A2 */ + , /* Aquila A10 */ + ; /* Aquila A8 */ + }; + + pinctrl_usdhc2_sleep: usdhc2-sleepgrp { + fsl,pins = , /* Aquila A5 */ + , /* Aquila A7 */ + , /* Aquila A3 */ + , /* Aquila A2 */ + , /* Aquila A10 */ + ; /* Aquila A8 */ + }; +}; From 3f519121e120a5264fb5638afd6a2aab44db11a3 Mon Sep 17 00:00:00 2001 From: Antoine Gouby Date: Thu, 21 May 2026 19:11:06 +0200 Subject: [PATCH 642/665] arm64: dts: freescale: imx95-aquila: Add Clover carrier board Add support for the Aquila i.MX95 SoM mated with the Clover carrier board. Clover is a low-cost carrier board for the Aquila family featuring a small form factor (Nano-ITX 120mm x 120mm) and built for volume production. Link: https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95 Link: https://www.toradex.com/products/carrier-board/clover Signed-off-by: Antoine Gouby Signed-off-by: Franz Schnyder Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx95-aquila-clover.dts | 285 ++++++++++++++++++ 2 files changed, 286 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx95-aquila-clover.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index a4c54290f082..79abdfa3cbe3 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -637,6 +637,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-frdm.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-sof.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-frdm-pro.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-aquila-clover.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-aquila-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-toradex-smarc-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596sa-mb-smarc-2.dtb diff --git a/arch/arm64/boot/dts/freescale/imx95-aquila-clover.dts b/arch/arm64/boot/dts/freescale/imx95-aquila-clover.dts new file mode 100644 index 000000000000..fd9304331446 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-aquila-clover.dts @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/clover + */ + +/dts-v1/; + +#include +#include +#include "imx95-aquila.dtsi" + +/ { + model = "Aquila iMX95 on Aquila Clover Board"; + compatible = "toradex,aquila-imx95-clover", + "toradex,aquila-imx95", + "fsl,imx95"; + + aliases { + eeprom1 = &carrier_eeprom; + }; + + dp_1_connector: dp0-connector { + compatible = "dp-connector"; + dp-pwr-supply = <®_dp_3p3v>; + type = "full-size"; + + port { + dp_1_connector_in: endpoint { + remote-endpoint = <&dsi2dp_out>; + }; + }; + }; + + reg_dp_3p3v: regulator-dp-3p3v { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_21_dp>; + /* Aquila GPIO_21_DP */ + gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "DP_3V3"; + startup-delay-us = <10000>; + }; +}; + +/* Aquila ADC_[1-4] */ +&adc1 { + status = "okay"; +}; + +/* Aquila CTRL_WAKE1_MICO# */ +&aquila_key_wake { + status = "okay"; +}; + +&dsi2dp_out { + remote-endpoint = <&dp_1_connector_in>; +}; + +/* Aquila ETH_1 */ +&enetc_port0 { + status = "okay"; +}; + +/* Aquila CAN_1 */ +&flexcan1 { + status = "okay"; +}; + +/* Aquila CAN_2 */ +&flexcan2 { + status = "okay"; +}; + +/* Aquila CAN_3 */ +&flexcan3 { + status = "okay"; +}; + +/* Aquila CAN_4 */ +&flexcan4 { + status = "okay"; +}; + +/* Aquila QSPI_1 */ +&flexspi1 { + pinctrl-0 = <&pinctrl_flexspi1_4bit>, + <&pinctrl_qspi_cs1>; + + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <66000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_1>, + <&pinctrl_gpio_2>, + <&pinctrl_gpio_3>, + <&pinctrl_gpio_4>; +}; + +/* Aquila I2C_2 */ +&i3c2 { + status = "okay"; +}; + +/* Aquila I2C_1 */ +&lpi2c2 { + status = "okay"; + + fan_controller: fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + #pwm-cells = <2>; + + fan { + cooling-levels = <255>; + pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>; + }; + }; + + temperature-sensor@4f { + compatible = "ti,tmp1075"; + reg = <0x4f>; + }; + + /* USB-C OTG (TCPC USB PD PHY) */ + tcpc@52 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x52>; + interrupt-parent = <&som_gpio_expander_1>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + op-sink-microwatt = <0>; + power-role = "dual"; + self-powered; + sink-pdos = ; + source-pdos = ; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec_con_hs: endpoint { + remote-endpoint = <&usb1_con_hs>; + }; + }; + + port@1 { + reg = <1>; + + typec_con_ss: endpoint { + remote-endpoint = <&usb1_con_ss>; + }; + }; + }; + }; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Aquila I2C_6 */ +&lpi2c5 { + status = "okay"; +}; + +/* Aquila SPI_1 */ +&lpspi6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi6 &pinctrl_gpio_5>; + cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>, <&gpio4 18 GPIO_ACTIVE_LOW>; + + status = "okay"; + + tpm@1 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_6>; + interrupt-parent = <&gpio4>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <12000000>; + }; +}; + +/* Aquila UART_3, used as the Linux Console */ +&lpuart1 { + status = "okay"; +}; + +/* Aquila UART_4 */ +&lpuart2 { + status = "okay"; +}; + +/* Aquila UART_1 */ +&lpuart3 { + status = "okay"; +}; + +/* Aquila UART_2 */ +&lpuart7 { + status = "okay"; +}; + +/* Aquila PCIE_1 */ +&pcie0 { + status = "okay"; +}; + +/* Aquila PWM_1 */ +&tpm3 { + status = "okay"; +}; + +/* Aquila PWM_3_DSI and PWM_4_DP */ +&tpm5 { + status = "okay"; +}; + +/* Aquila PWM_2 */ +&tpm6 { + status = "okay"; +}; + +/* Aquila USB_2, optional Bluetooth USB */ +&usb2 { + status = "okay"; +}; + +/* Aquila USB_1 */ +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + status = "okay"; + + port { + usb1_con_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&usb3_phy { + orientation-switch; + + status = "okay"; + + port { + usb1_con_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; +}; + +/* Aquila SD_1 */ +&usdhc2 { + status = "okay"; +}; From 5b19ca527471903920d713bc48518a036a95bf6b Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Thu, 28 May 2026 12:15:56 +0200 Subject: [PATCH 643/665] arm64: dts: imx8mp-kontron: Fix GPIO for display power switch The GPIO that controls the power supply for the LVDS display connector has changed between early prototypes and the current production design of the hardware. Reflect this change in the devicetree to properly switch on the panel supply. This was working before even with the wrong GPIO due to the bidirectional level shifter used on the board which drives the EN signal high even when the input has a (weak) pull down configured as reset condition of the SoC pad. As a result the display was working but the supply was always on. Tested on BL i.MX8MP to show the correct voltage level on the level shifter input. Fixes: 946ab10e3f40 ("arm64: dts: Add support for Kontron OSM-S i.MX8MP SoM and BL carrier board") Signed-off-by: Frieder Schrempf Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts b/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts index 75ae46642782..29ce863403b8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts @@ -49,7 +49,9 @@ pwm-beeper { reg_vcc_panel: regulator-vcc-panel { compatible = "regulator-fixed"; - gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_vcc_panel>; + gpio = <&gpio5 3 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-max-microvolt = <3300000>; regulator-min-microvolt = <3300000>; @@ -172,7 +174,7 @@ &gpio4 { &gpio5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio5>; - gpio-line-names = "I2S_BITCLK", "I2S_A_DATA_OUT", "I2S_MCLK", "PWM_2", + gpio-line-names = "I2S_BITCLK", "I2S_A_DATA_OUT", "I2S_MCLK", "VCC_PANEL_EN", "PWM_1", "PWM_0", "SPI_A_SCK", "CAN_ADDR1", "CAN_ADDR0", "SPI_A_CS0", "SPI_B_SCK", "SPI_B_SDO", "SPI_B_SDI", "SPI_B_CS0", "I2C_A_SCL", "I2C_A_SDA", @@ -329,4 +331,10 @@ MX8MP_IOMUXC_ECSPI1_MOSI__GPIO5_IO07 0x46 /* CAN_ADR0 */ MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x46 /* CAN_ADR1 */ >; }; + + pinctrl_reg_vcc_panel: regvccpanelgrp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x46 + >; + }; }; From 41b45d26d207a15886806fa300eded53fe303abe Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Tue, 19 May 2026 13:39:42 +0800 Subject: [PATCH 644/665] arm64: dts: imx943-evk-sdwifi: add a new dtso to support SDIW612 WiFi Add a new imx943-evk-sdwifi.dtso to support SDIW612 WiFi chip on imx943-evk board, the default imx943-evk.dtb is used to support PCIE AW693 WiFi. Use separate dts for SDIW612 and PCIe AW693 WiFi to avoid the shared regulator between SDIO and PCIe buses, the random probe order between the two buses may break the PCIe initialization sequence which cause AW693 has probability of failing to detect. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 3 +++ .../boot/dts/freescale/imx943-evk-sdwifi.dtso | 15 +++++++++++++++ arch/arm64/boot/dts/freescale/imx943-evk.dts | 2 +- 3 files changed, 19 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/freescale/imx943-evk-sdwifi.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 79abdfa3cbe3..03988f0eae30 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -631,6 +631,9 @@ imx943-evk-pcie0-ep-dtbs += imx943-evk.dtb imx-pcie0-ep.dtbo imx943-evk-pcie1-ep-dtbs += imx943-evk.dtb imx-pcie1-ep.dtbo dtb-$(CONFIG_ARCH_MXC) += imx943-evk-pcie0-ep.dtb imx943-evk-pcie1-ep.dtb +imx943-evk-sdwifi-dtbs := imx943-evk.dtb imx943-evk-sdwifi.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx943-evk-sdwifi.dtb + dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-ab2.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-frdm.dtb diff --git a/arch/arm64/boot/dts/freescale/imx943-evk-sdwifi.dtso b/arch/arm64/boot/dts/freescale/imx943-evk-sdwifi.dtso new file mode 100644 index 000000000000..59cc1c27b9b9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx943-evk-sdwifi.dtso @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 NXP + */ + +/dts-v1/; +/plugin/; + +&pcie0 { + status = "disabled"; +}; + +&usdhc3 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts index 426b5a4ec47c..7cfd42468950 100644 --- a/arch/arm64/boot/dts/freescale/imx943-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts @@ -1153,7 +1153,7 @@ &usdhc3 { keep-power-in-suspend; non-removable; wakeup-source; - status = "okay"; + status = "disabled"; }; &wdog3 { From 08886fa69c0f56f886b63d7835da0632ea4082f7 Mon Sep 17 00:00:00 2001 From: Nora Schiffer Date: Tue, 24 Feb 2026 16:25:23 +0100 Subject: [PATCH 645/665] arm64: dts: freescale: fsl-ls1028a-tqmls1028a-mbls1028a: switch mmc aliases All modern TQ-Systems boards follow the convention that mmc0 is the eMMC and mmc1 is the SD-card when both interfaces exist, reducing differences between boards for both documentation and U-Boot code (which uses the same Device Trees). Adjust the recently added MBLS1028A Device Tree accordingly. Fixes: 0538ca1f102d ("arm64: dts: ls1028a: Add mbls1028a and mbls1028a-ind devicetrees") Signed-off-by: Nora Schiffer Reviewed-by: Alexander Stein Reviewed-by: Frank Li Signed-off-by: Frank Li --- .../boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a.dtsi index cf338b2e8006..426a81e1743f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a.dtsi @@ -17,8 +17,8 @@ aliases { gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; - mmc0 = &esdhc; /* SD-Card */ - mmc1 = &esdhc1; /* eMMC */ + mmc0 = &esdhc1; /* eMMC */ + mmc1 = &esdhc; /* SD-Card */ serial0 = &duart0; serial1 = &duart1; }; From 4faac185cc5035b93b6637e0ce77891877f7192c Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Fri, 29 May 2026 15:48:50 +0200 Subject: [PATCH 646/665] arm64: dts: imx91-var-som-symphony: fix RGB_SEL handling RGB_SEL is a board-level signal driven by the PCAL6408 GPIO expander on the Symphony carrier board. The signal needs to be driven high on the i.MX91 variant to keep the board in the expected display configuration. Move the handling of this line from a fixed regulator tied to the PCAL6408 supply to a GPIO hog on the correct GPIO expander. Fixes: b3292129dcef ("arm64: dts: imx91-var-som: Add support for Variscite Symphony board") Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../dts/freescale/imx91-var-som-symphony.dts | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx91-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx91-var-som-symphony.dts index ac9fed58357e..c1e6c9978275 100644 --- a/arch/arm64/boot/dts/freescale/imx91-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx91-var-som-symphony.dts @@ -97,13 +97,6 @@ reg_fec_phy: regulator-fec-phy { regulator-always-on; }; - reg_rgb_sel: regulator-rgb-enable { - compatible = "regulator-fixed"; - regulator-name = "RGBSEL"; - gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; @@ -258,7 +251,6 @@ pca6408: gpio@21 { #interrupt-cells = <2>; interrupt-parent = <&gpio2>; interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - vcc-supply = <®_rgb_sel>; wakeup-source; tpm-enable-hog { @@ -267,6 +259,14 @@ tpm-enable-hog { output-high; line-name = "tpm_en"; }; + + /* RGB_SEL */ + lvds-brg-enable-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "lvds_brg_en"; + }; }; /* USB Type-C Controller */ From 6dc737d7dad1d69da4b3e71c5125287a2481042b Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Wed, 3 Jun 2026 10:25:00 +0200 Subject: [PATCH 647/665] arm64: dts: imx93-var-som-symphony: add TPM support Add the ST33KTPM2XI2C TPM device on the Symphony carrier board. The TPM reset line is driven through a PCAL6408 GPIO expander, so add the expander on the I2C bus and describe the TPM reset GPIO. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../boot/dts/freescale/imx93-var-som-symphony.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts index c0842fb3cfa3..c736127c7115 100644 --- a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts @@ -208,6 +208,21 @@ &lpi2c1 { sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; status = "okay"; + pcal6408: gpio@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + + st33ktpm2xi2c: tpm@2e { + compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + label = "tpm"; + reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>; + }; + /* Capacitive touch controller */ ft5x06_ts: touchscreen@38 { compatible = "edt,edt-ft5206"; From cca15b4590ce47af01a2490ef531ccfa9eab7838 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Wed, 3 Jun 2026 10:25:01 +0200 Subject: [PATCH 648/665] arm64: dts: imx93-var-som-symphony: enable UART7 Enable UART7 on the Symphony carrier board and add its pinctrl configuration. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../boot/dts/freescale/imx93-var-som-symphony.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts index c736127c7115..77377127c18c 100644 --- a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts @@ -35,6 +35,7 @@ aliases { serial3 = &lpuart4; serial4 = &lpuart5; serial5 = &lpuart6; + serial6 = &lpuart7; }; @@ -305,6 +306,12 @@ &lpuart6 { status = "okay"; }; +&lpuart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + status = "okay"; +}; + &usbotg1 { dr_mode = "otg"; hnp-disable; @@ -441,6 +448,13 @@ MX93_PAD_GPIO_IO04__LPUART6_TX 0x31e >; }; + pinctrl_uart7: uart7grp { + fsl,pins = < + MX93_PAD_GPIO_IO09__LPUART7_RX 0x31e + MX93_PAD_GPIO_IO08__LPUART7_TX 0x31e + >; + }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < MX93_PAD_GPIO_IO18__GPIO2_IO18 0x31e From 17f1681fc7b7a5e1ef4756d33d399f28dd372a28 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Wed, 3 Jun 2026 10:25:02 +0200 Subject: [PATCH 649/665] arm64: dts: imx93-var-som-symphony: keep RGB_SEL low Keep the RGB_SEL line driven low on the Symphony carrier board. This avoids leaving the line floating and ensures the board remains in the expected display configuration. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts index 77377127c18c..c835394468ef 100644 --- a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts @@ -215,6 +215,14 @@ pcal6408: gpio@21 { gpio-controller; #gpio-cells = <2>; status = "okay"; + + /* RGB_SEL */ + lvds-brg-enable-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "lvds_brg_en"; + }; }; st33ktpm2xi2c: tpm@2e { From 4b1433a0d11d7a8f9ccda39b9e36a263170d3a7f Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Wed, 3 Jun 2026 10:25:03 +0200 Subject: [PATCH 650/665] arm64: dts: imx93-var-som-symphony: enable TPM3 PWM Enable TPM3 on the Symphony carrier board and add the pinctrl states for the PWM output and sleep configuration. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../dts/freescale/imx93-var-som-symphony.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts index c835394468ef..56f8744c861a 100644 --- a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts @@ -320,6 +320,13 @@ &lpuart7 { status = "okay"; }; +&tpm3 { + pinctrl-0 = <&pinctrl_tpm3>; + pinctrl-1 = <&pinctrl_tpm3_sleep>; + pinctrl-names = "default", "sleep"; + status = "okay"; +}; + &usbotg1 { dr_mode = "otg"; hnp-disable; @@ -442,6 +449,18 @@ MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e >; }; + pinctrl_tpm3: tpm3grp { + fsl,pins = < + MX93_PAD_GPIO_IO24__TPM3_CH3 0x51e + >; + }; + + pinctrl_tpm3_sleep: tpm3sleepgrp { + fsl,pins = < + MX93_PAD_GPIO_IO24__GPIO2_IO24 0x51e + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX93_PAD_UART1_RXD__LPUART1_RX 0x31e From b3c52872bfa2de6f4f1862cbeef8204394bb09b7 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Wed, 3 Jun 2026 10:25:04 +0200 Subject: [PATCH 651/665] arm64: dts: imx93-var-som-symphony: enable ADC Enable ADC1 on the Symphony carrier board and describe its 1.8 V reference supply. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts index 56f8744c861a..409c7e74ffe3 100644 --- a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts @@ -159,6 +159,11 @@ led-0 { }; }; +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + /* Use external instead of internal RTC*/ &bbnsm_rtc { status = "disabled"; From c10cfc952215644956284a42fa7b7860dfbcb5f5 Mon Sep 17 00:00:00 2001 From: Florijan Plohl Date: Wed, 3 Jun 2026 08:15:01 +0200 Subject: [PATCH 652/665] arm64: dts: imx{91,93}-phyboard-segin: Add peb-av-18 overlays Add overlay for the PHYTEC Audio/Video adapter module PEB-AV-18 on phyBOARD-Segin-i.MX91/93 boards. The supported AC220 display is Powertip PH800480T032-ZHC19 panel with a backlight and Ilitek touch-screen controller. Signed-off-by: Florijan Plohl Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 6 ++ .../imx91-93-phyboard-segin-peb-av-18.dtsi | 93 +++++++++++++++++++ .../imx91-phyboard-segin-peb-av-18.dtso | 57 ++++++++++++ .../imx93-phyboard-segin-peb-av-18.dtso | 57 ++++++++++++ 4 files changed, 213 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx91-93-phyboard-segin-peb-av-18.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx91-phyboard-segin-peb-av-18.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-av-18.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 03988f0eae30..8ddaab127ab9 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -563,6 +563,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-frdm.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-frdm-s.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin.dtb + +imx91-phyboard-segin-peb-av-18-dtbs += imx91-phyboard-segin.dtb imx91-phyboard-segin-peb-av-18.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin-peb-av-18.dtb + dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca.dtb imx91-tqma9131-mba91xxca-lvds-tm070jvhg33-dtbs := imx91-tqma9131-mba91xxca.dtb imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtbo @@ -598,6 +602,7 @@ imx93-phyboard-nash-jtag-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-nash-jta imx93-phyboard-nash-peb-wlbt-07-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-nash-peb-wlbt-07.dtbo imx93-phyboard-nash-pwm-fan-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-nash-pwm-fan.dtbo imx93-phyboard-segin-peb-av-02-dtbs += imx93-phyboard-segin.dtb imx93-phyboard-segin-peb-av-02.dtbo +imx93-phyboard-segin-peb-av-18-dtbs += imx93-phyboard-segin.dtb imx93-phyboard-segin-peb-av-18.dtbo imx93-phyboard-segin-peb-eval-01-dtbs += imx93-phyboard-segin.dtb imx93-phyboard-segin-peb-eval-01.dtbo imx93-phyboard-segin-peb-wlbt-05-dtbs += imx93-phyboard-segin.dtb imx93-phyboard-segin-peb-wlbt-05.dtbo imx93-phycore-rpmsg-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-segin.dtb imx93-phycore-rpmsg.dtbo @@ -605,6 +610,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash-jtag.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash-peb-wlbt-07.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash-pwm-fan.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin-peb-av-02.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin-peb-av-18.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin-peb-eval-01.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin-peb-wlbt-05.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-phycore-rpmsg.dtb diff --git a/arch/arm64/boot/dts/freescale/imx91-93-phyboard-segin-peb-av-18.dtsi b/arch/arm64/boot/dts/freescale/imx91-93-phyboard-segin-peb-av-18.dtsi new file mode 100644 index 000000000000..53d5cbcd798b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-93-phyboard-segin-peb-av-18.dtsi @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2026 PHYTEC Messtechnik GmbH + * + * Author: Florijan Plohl + */ + +#include +#include +#include + +/dts-v1/; +/plugin/; + +&{/} { + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <5>; + power-supply = <®_vcc_3v3_con>; + pwms = <&pwm7 0 5000000 0>; + }; + + panel { + compatible = "powertip,ph800480t032-zhc19"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel>; + + backlight = <&backlight>; + enable-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; + power-supply = <®_vcc_3v3_con>; + + port { + panel_in: endpoint { + remote-endpoint = <&dpi_to_panel>; + }; + }; + }; + + pwm7: pwm-7 { + compatible = "pwm-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm7>; + gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + #pwm-cells = <3>; + }; + + reg_vcc_3v3_con: regulator-vcc-3v3-con { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3_CON"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + }; +}; + +&dpi_bridge { + status = "okay"; +}; + +&dpi_to_panel { + remote-endpoint = <&panel_in>; + bus-width = <18>; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + assigned-clocks = <&clk IMX93_CLK_VIDEO_PLL>; + assigned-clock-rates = <27272728>; + status = "okay"; +}; + +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@41 { + compatible = "ilitek,ili2130"; + reg = <0x41>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touchscreen>; + interrupt-parent = <&gpio4>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + wakeup-source; + }; +}; + +&media_blk_ctrl { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx91-phyboard-segin-peb-av-18.dtso b/arch/arm64/boot/dts/freescale/imx91-phyboard-segin-peb-av-18.dtso new file mode 100644 index 000000000000..35edf9b0fb0f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-phyboard-segin-peb-av-18.dtso @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2026 PHYTEC Messtechnik GmbH + * + * Author: Florijan Plohl + */ + +#include "imx91-pinfunc.h" +#include "imx91-93-phyboard-segin-peb-av-18.dtsi" + +&iomuxc { + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x57e + MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x51e + MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x51e + MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x51e + MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0 0x51e + MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1 0x51e + MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2 0x51e + MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3 0x51e + MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4 0x51e + MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5 0x51e + MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6 0x51e + MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7 0x51e + MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8 0x51e + MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9 0x51e + MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x51e + MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x51e + MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x51e + MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x51e + MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x51e + MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x51e + MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x51e + MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x51e + >; + }; + + pinctrl_panel: panelgrp { + fsl,pins = < + MX91_PAD_CCM_CLKO4__GPIO4_IO29 0x1133e + >; + }; + + pinctrl_pwm7: pwm7grp { + fsl,pins = < + MX91_PAD_CCM_CLKO3__GPIO4_IO28 0x1133e + >; + }; + + pinctrl_touchscreen: touchscreengrp { + fsl,pins = < + MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x11e + MX91_PAD_ENET1_RD2__GPIO4_IO12 0x1133e + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-av-18.dtso b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-av-18.dtso new file mode 100644 index 000000000000..11f7d7502be4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-av-18.dtso @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2026 PHYTEC Messtechnik GmbH + * + * Author: Florijan Plohl + */ + +#include "imx93-pinfunc.h" +#include "imx91-93-phyboard-segin-peb-av-18.dtsi" + +&iomuxc { + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x57e + MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x51e + MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x51e + MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x51e + MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x51e + MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x51e + MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x51e + MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x51e + MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x51e + MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x51e + MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x51e + MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x51e + MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x51e + MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x51e + MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x51e + MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x51e + MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x51e + MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x51e + MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x51e + MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x51e + MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x51e + MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x51e + >; + }; + + pinctrl_panel: panelgrp { + fsl,pins = < + MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x1133e + >; + }; + + pinctrl_pwm7: pwm7grp { + fsl,pins = < + MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x1133e + >; + }; + + pinctrl_touchscreen: touchscreengrp { + fsl,pins = < + MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x11e + MX93_PAD_ENET1_RD2__GPIO4_IO12 0x1133e + >; + }; +}; From 7c2a29d72f9595c876b6dccb47fa2540e09f1972 Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Mon, 18 May 2026 17:33:30 +0200 Subject: [PATCH 653/665] dt-bindings: media: sun6i-a31-csi: Add optional interconnect properties An interconnect can be attached to the sun6i-a31-csi device, which is useful to attach the dma memory offset. Add related properties. Signed-off-by: Paul Kocialkowski Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260518153339.619947-2-paulk@sys-base.io Signed-off-by: Chen-Yu Tsai --- .../devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml index 1aa5775ba2bc..978ef2dc0ae7 100644 --- a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml +++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml @@ -40,6 +40,12 @@ properties: resets: maxItems: 1 + interconnects: + maxItems: 1 + + interconnect-names: + const: dma-mem + port: $ref: /schemas/graph.yaml#/$defs/port-base description: Parallel input port, connect to a parallel sensor From 64659ee650018e0120ad4ed56160f346ac76dc17 Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Mon, 18 May 2026 17:33:31 +0200 Subject: [PATCH 654/665] dt-bindings: media: sun6i-a31-isp: Add optional interconnect properties An interconnect can be attached to the sun6i-a31-isp device, which is useful to attach the dma memory offset. Add related properties. Signed-off-by: Paul Kocialkowski Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260518153339.619947-3-paulk@sys-base.io [wens@kernel.org: Corrected sun6i-a31-csi to sun6i-a31-isp in commit log] Signed-off-by: Chen-Yu Tsai --- .../devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml index 3ea4a4290f23..c0d7accc7bbe 100644 --- a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml +++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml @@ -36,6 +36,12 @@ properties: resets: maxItems: 1 + interconnects: + maxItems: 1 + + interconnect-names: + const: dma-mem + ports: $ref: /schemas/graph.yaml#/properties/ports From 9e8019bd2f55ecd47efa15f7ab4fa49a919d96c5 Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Mon, 18 May 2026 17:33:36 +0200 Subject: [PATCH 655/665] ARM: dts: sun8i: a83t: Add MIPI CSI-2 controller node MIPI CSI-2 is supported on the A83T with a dedicated controller that covers both the protocol and D-PHY. It is connected to the only CSI receiver with a fwnode graph link. Note that the CSI receiver supports both this MIPI CSI-2 source and a parallel source. An empty port with a label for the MIPI CSI-2 sensor input is also defined for convenience. Signed-off-by: Paul Kocialkowski Reviewed-by: Jernej Skrabec Link: https://patch.msgid.link/20260518153339.619947-8-paulk@sys-base.io Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 43 +++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi index 6f88d8764e6a..cc107c6030de 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi @@ -1062,6 +1062,49 @@ csi: camera@1cb0000 { clock-names = "bus", "mod", "ram"; resets = <&ccu RST_BUS_CSI>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + csi_in_mipi_csi2: endpoint { + remote-endpoint = <&mipi_csi2_out_csi>; + }; + }; + }; + }; + + mipi_csi2: csi@1cb1000 { + compatible = "allwinner,sun8i-a83t-mipi-csi2"; + reg = <0x01cb1000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI_SCLK>, + <&ccu CLK_MIPI_CSI>, + <&ccu CLK_CSI_MISC>; + clock-names = "bus", "mod", "mipi", "misc"; + resets = <&ccu RST_BUS_CSI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_in: port@0 { + reg = <0>; + }; + + mipi_csi2_out: port@1 { + reg = <1>; + + mipi_csi2_out_csi: endpoint { + remote-endpoint = <&csi_in_mipi_csi2>; + }; + }; + }; }; hdmi: hdmi@1ee0000 { From a186a9742dc5d53a364934325aacf7fba726341a Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Sat, 23 May 2026 15:02:30 +0100 Subject: [PATCH 656/665] arm64: dts: allwinner: Add EL2 virtual timer interrupt The ARMv8.2 based CPUs used in the A523 SoC (and derivatives) are missing the EL2 virtual timer interrupt. Add it. Reviewed-by: Andre Przywara Tested-by: Andre Przywara Signed-off-by: Marc Zyngier Link: https://patch.msgid.link/20260523140242.586031-6-maz@kernel.org Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi index 5afa8d92acbf..d3c47966e8fc 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -101,7 +101,8 @@ timer { interrupts = , , , - ; + , + ; }; soc { From e53b4d7b3ed109a64e0e3b440518d1b2ac18a05b Mon Sep 17 00:00:00 2001 From: Michal Piekos Date: Sat, 16 May 2026 07:34:16 +0200 Subject: [PATCH 657/665] arm64: dts: allwinner: a523: add gpadc node Describe GPADC block on Allwinner A523. Tested on Radxa Cubie A5E: - 2 connected channels are showing voltages in agreement with schematics. BOOT-SEL-ADC ~500mV BOM-ADC ~1800mV - 3rd channel exposed on 40pin header is showing correct voltages when connected to known voltage source. Signed-off-by: Michal Piekos Link: https://patch.msgid.link/20260516-sunxi-a523-gpadc-v3-3-a3a04cff2620@mmpsystems.pl Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi index d3c47966e8fc..321a03da77da 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -341,6 +341,19 @@ ledc: led-controller@2008000 { status = "disabled"; }; + gpadc: adc@2009000 { + compatible = "allwinner,sun55i-a523-gpadc"; + reg = <0x2009000 0x400>; + clocks = <&ccu CLK_BUS_GPADC0>, <&ccu CLK_GPADC0>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_GPADC0>; + interrupts = ; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + wdt: watchdog@2050000 { compatible = "allwinner,sun55i-a523-wdt"; reg = <0x2050000 0x20>; From 34efd73379ff9f36ed598ade7406a1aaddd03d7b Mon Sep 17 00:00:00 2001 From: Ryan Chen Date: Tue, 9 Jun 2026 10:47:18 +0800 Subject: [PATCH 658/665] dt-bindings: arm: aspeed: Add AST2700 board compatible Add device tree compatible string for AST2700 based boards ("aspeed,ast2700-evb" and "aspeed,ast2700") to the Aspeed SoC board bindings. This allows proper schema validation and enables support for AST2700 platforms. Signed-off-by: Ryan Chen Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20260609-upstream_ast2700-v9-1-f631752f0cb1@aspeedtech.com Signed-off-by: Arnd Bergmann --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index 9ba195b8f22d..dd7996960de3 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -119,4 +119,10 @@ properties: - ufispace,ncplite-bmc - const: aspeed,ast2600 + - description: AST2700 based boards + items: + - enum: + - aspeed,ast2700-evb + - const: aspeed,ast2700 + additionalProperties: true From df6f379eb4ac78e51d582aa7e8683bf8d5468dfe Mon Sep 17 00:00:00 2001 From: Ryan Chen Date: Tue, 9 Jun 2026 10:47:19 +0800 Subject: [PATCH 659/665] arm64: Kconfig: Add ASPEED SoC family Kconfig support Add support for ASPEED SoC family like ast27XX 8th generation ASPEED BMCs. Signed-off-by: Ryan Chen Link: https://lore.kernel.org/r/20260609-upstream_ast2700-v9-2-f631752f0cb1@aspeedtech.com Signed-off-by: Arnd Bergmann --- arch/arm64/Kconfig.platforms | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 72c812e76b0b..5c18e507b9b8 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -48,6 +48,12 @@ config ARCH_ARTPEC help This enables support for the ARMv8 based ARTPEC SoC Family. +config ARCH_ASPEED + bool "Aspeed SoC family" + help + This enables support for ASPEED's SoC family, such as the + ast27XX 8th generation Baseboard Management Controller (BMC). + config ARCH_AXIADO bool "Axiado SoC Family" select GPIOLIB From e77bb5dc57593a4698aaacd57a776728cf552e73 Mon Sep 17 00:00:00 2001 From: Ryan Chen Date: Tue, 9 Jun 2026 10:47:20 +0800 Subject: [PATCH 660/665] arm64: dts: aspeed: Add initial AST27xx SoC device tree Add initial device tree support for the ASPEED AST27xx family, the 8th-generation Baseboard Management Controller (BMC) SoCs. AST27xx SOC Family - https://www.aspeedtech.com/server_ast2700/ - https://www.aspeedtech.com/server_ast2720/ - https://www.aspeedtech.com/server_ast2750/ The AST27xx features a dual-SoC architecture consisting of two dies, referred to as SoC0 and SoC1 - interconnected through an internal proprietary bus. Both SoCs share the same address decoding scheme, while each maintains independent clock and reset domains. - SoC0 (CPU die): contains a quad-core Cortex-A35 cluster and two Cortex-M4 cores, along with high-speed peripherals. - SoC1 (I/O die): includes the BootMCU (responsible for system boot) and its own clock/reset domains low-speed peripherals. The device tree describes the SoC0 and SoC1 domains and their peripheral layouts. Signed-off-by: Ryan Chen Link: https://lore.kernel.org/r/20260609-upstream_ast2700-v9-3-f631752f0cb1@aspeedtech.com Signed-off-by: Arnd Bergmann --- MAINTAINERS | 1 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/aspeed/Makefile | 4 + .../aspeed/aspeed-evb-flash-layout-128.dtsi | 32 + arch/arm64/boot/dts/aspeed/aspeed-g7-a35.dtsi | 196 +++ .../dts/aspeed/aspeed-g7-soc0-pinctrl.dtsi | 225 ++++ .../arm64/boot/dts/aspeed/aspeed-g7-soc0.dtsi | 230 ++++ .../dts/aspeed/aspeed-g7-soc1-pinctrl.dtsi | 1113 +++++++++++++++++ .../arm64/boot/dts/aspeed/aspeed-g7-soc1.dtsi | 557 +++++++++ arch/arm64/boot/dts/aspeed/ast2700-evb.dts | 65 + 10 files changed, 2424 insertions(+) create mode 100644 arch/arm64/boot/dts/aspeed/Makefile create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-evb-flash-layout-128.dtsi create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7-a35.dtsi create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7-soc0-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7-soc0.dtsi create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7-soc1-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7-soc1.dtsi create mode 100644 arch/arm64/boot/dts/aspeed/ast2700-evb.dts diff --git a/MAINTAINERS b/MAINTAINERS index 229e486fb9a8..2e48312d27cd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2612,6 +2612,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux.git F: Documentation/devicetree/bindings/arm/aspeed/ F: arch/arm/boot/dts/aspeed/ F: arch/arm/mach-aspeed/ +F: arch/arm64/boot/dts/aspeed/ N: aspeed ARM/AXIADO ARCHITECTURE diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 98ec8f1b76e4..fc726b215f12 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -9,6 +9,7 @@ subdir-y += amlogic subdir-y += apm subdir-y += apple subdir-y += arm +subdir-y += aspeed subdir-y += axiado subdir-y += bitmain subdir-y += blaize diff --git a/arch/arm64/boot/dts/aspeed/Makefile b/arch/arm64/boot/dts/aspeed/Makefile new file mode 100644 index 000000000000..ffe7e15017cc --- /dev/null +++ b/arch/arm64/boot/dts/aspeed/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +dtb-$(CONFIG_ARCH_ASPEED) += \ + ast2700-evb.dtb diff --git a/arch/arm64/boot/dts/aspeed/aspeed-evb-flash-layout-128.dtsi b/arch/arm64/boot/dts/aspeed/aspeed-evb-flash-layout-128.dtsi new file mode 100644 index 000000000000..b54915f06efd --- /dev/null +++ b/arch/arm64/boot/dts/aspeed/aspeed-evb-flash-layout-128.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT + +partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + u-boot@0 { + reg = <0x0 0x400000>; // 4MB + label = "u-boot"; + }; + + u-boot-env@400000 { + reg = <0x400000 0x20000>; // 128KB + label = "u-boot-env"; + }; + + kernel@420000 { + reg = <0x420000 0x900000>; // 9MB + label = "kernel"; + }; + + rofs@d20000 { + reg = <0xd20000 0x52E0000>; // 82.875MB + label = "rofs"; + }; + + rwfs@6000000 { + reg = <0x6000000 0x2000000>; // 32MB + label = "rwfs"; + }; +}; diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7-a35.dtsi b/arch/arm64/boot/dts/aspeed/aspeed-g7-a35.dtsi new file mode 100644 index 000000000000..ef283d95649a --- /dev/null +++ b/arch/arm64/boot/dts/aspeed/aspeed-g7-a35.dtsi @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree Source for AST27xx SoC Family + * + * Copyright (C) 2026 ASPEED Technology Inc. + */ + +#include + +/ { + compatible = "aspeed,ast2700"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x2>; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x3>; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2>; + }; + + l2: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <1024>; + }; + }; + + secondary { + #address-cells = <2>; + /* https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/of/address.c?h=v6.16#n491 */ + #size-cells = <0>; + /* https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/of/address.c?h=v6.16#n430 */ + + ssp_nvic: interrupt-controller@1,e000e100 { + compatible = "arm,v7m-nvic"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <1 0xe000e100>; + arm,num-irq-priority-bits = <3>; + status = "disabled"; + }; + }; + + tertiary { + #address-cells = <2>; + #size-cells = <0>; + + tsp_nvic: interrupt-controller@2,e000e100 { + compatible = "arm,v7m-nvic"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <2 0xe000e100>; + arm,num-irq-priority-bits = <3>; + status = "disabled"; + }; + }; + + bootmcu { + bootmcu_hlic: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + status = "disabled"; + }; + }; + + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + atf: trusted-firmware-a@430000000 { + reg = <0x4 0x30000000 0x0 0x80000>; + no-map; + }; + + optee_core: optee-core@430080000 { + reg = <0x4 0x30080000 0x0 0x1000000>; + no-map; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a35-pmu"; + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + arm,cpu-registers-not-fw-configured; + always-on; + }; + + gic: interrupt-controller@12200000 { + compatible = "arm,gic-v3"; + reg = <0 0x12200000 0 0x10000>, /* GICD */ + <0 0x12280000 0 0x80000>, /* GICR */ + <0 0x40440000 0 0x1000>; /* GICC */ + interrupts = ; + #interrupt-cells = <3>; + interrupt-controller; + }; + + soc0: bus@10000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x4000000>; + }; + + soc1: bus@14000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x14000000 0x0 0x14000000 0x2 0xec000000>; + }; +}; + +#include "aspeed-g7-soc0.dtsi" +#include "aspeed-g7-soc1.dtsi" diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7-soc0-pinctrl.dtsi b/arch/arm64/boot/dts/aspeed/aspeed-g7-soc0-pinctrl.dtsi new file mode 100644 index 000000000000..ed58ee41973b --- /dev/null +++ b/arch/arm64/boot/dts/aspeed/aspeed-g7-soc0-pinctrl.dtsi @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +// Copyright 2025 ASPEED Corp. + +&pinctrl0 { + pinctrl_emmc_default: emmc-default-state { + function = "EMMC"; + groups = "EMMCG1"; + }; + pinctrl_emmcg4_default: emmcg4-default-state { + function = "EMMC"; + groups = "EMMCG4"; + }; + pinctrl_emmcg8_default: emmcg8-default-state { + function = "EMMC"; + groups = "EMMCG8"; + }; + pinctrl_emmcwpn_default: emmcwpn-default-state { + function = "EMMC"; + groups = "EMMCWPN"; + }; + pinctrl_emmccdn_default: emmccdn-default-state { + function = "EMMC"; + groups = "EMMCCDN"; + }; + pinctrl_vb1_default: vb1-default-state { + function = "VB"; + groups = "VB1"; + }; + pinctrl_vb0_default: vb0-default-state { + function = "VB"; + groups = "VB0"; + }; + pinctrl_tsprstn_default: tsprstn-default-state { + function = "TSPRSTN"; + groups = "TSPRSTN"; + }; + pinctrl_ufsclki_default: ufsclki-default-state { + function = "UFSCLKI"; + groups = "UFSCLKI"; + }; + pinctrl_vgaddc_default: vgaddc-default-state { + function = "VGADDC"; + groups = "VGADDC"; + }; + pinctrl_usb3axhd_default: usb3axhd-default-state { + function = "USB3AXHD"; + groups = "USB3A"; + }; + pinctrl_usb3axhpd_default: usb3axhpd-default-state { + function = "USB3AXHPD"; + groups = "USB3A"; + }; + pinctrl_usb3axh_default: usb3axh-default-state { + function = "USB3AXH"; + groups = "USB3AAP"; + }; + pinctrl_usb3axhp_default: usb3axhp-default-state { + function = "USB3AXHP"; + groups = "USB3AAP"; + }; + pinctrl_usb3axh2b_default: usb3axh2b-default-state { + function = "USB3AXH2B"; + groups = "USB3ABP"; + }; + pinctrl_usb3axhp2b_default: usb3axhp2b-default-state { + function = "USB3AXHP2B"; + groups = "USB3ABP"; + }; + pinctrl_usb2axhd1_default: usb2axhd1-default-state { + function = "USB2AXHD1"; + groups = "USB2A"; + }; + pinctrl_usb2axhpd1_default: usb2axhpd1-default-state { + function = "USB2AXHPD1"; + groups = "USB2A"; + }; + pinctrl_usb2ad1_default: usb2ad1-default-state { + function = "USB2AD1"; + groups = "USB2ADAP"; + }; + pinctrl_usb2axh_default: usb2axh-default-state { + function = "USB2AXH"; + groups = "USB2AAP"; + }; + pinctrl_usb2axhp_default: usb2axhp-default-state { + function = "USB2AXHP"; + groups = "USB2AAP"; + }; + pinctrl_usb2axh2b_default: usb2axh2b-default-state { + function = "USB2AXH2B"; + groups = "USB2ABP"; + }; + pinctrl_usb2axhp2b_default: usb2axhp2b-default-state { + function = "USB2AXHP2B"; + groups = "USB2ABP"; + }; + pinctrl_usb2ahpd0_default: usb2ahpd0-default-state { + function = "USB2AHPD0"; + groups = "USB2AH"; + }; + pinctrl_usb2ad0_default: usb2ad0-default-state { + function = "USB2AD0"; + groups = "USB2AHAP"; + }; + pinctrl_usb2ah_default: usb2ah-default-state { + function = "USB2AH"; + groups = "USB2AHAP"; + }; + pinctrl_usb2ahp_default: usb2ahp-default-state { + function = "USB2AHP"; + groups = "USB2AHAP"; + }; + pinctrl_usb3bxhd_default: usb3bxhd-default-state { + function = "USB3BXHD"; + groups = "USB3B"; + }; + pinctrl_usb3bxhpd_default: usb3bxhpd-default-state { + function = "USB3BXHPD"; + groups = "USB3B"; + }; + pinctrl_usb3bxh_default: usb3bxh-default-state { + function = "USB3BXH"; + groups = "USB3BBP"; + }; + pinctrl_usb3bxhp_default: usb3bxhp-default-state { + function = "USB3BXHP"; + groups = "USB3BBP"; + }; + pinctrl_usb3bxh2a_default: usb3bxh2a-default-state { + function = "USB3BXH2A"; + groups = "USB3BAP"; + }; + pinctrl_usb3bxhp2a_default: usb3bxhp2a-default-state { + function = "USB3BXHP2A"; + groups = "USB3BAP"; + }; + pinctrl_usb2bxhd1_default: usb2bxhd1-default-state { + function = "USB2BXHD1"; + groups = "USB2B"; + }; + pinctrl_usb2bxhpd1_default: usb2bxhpd1-default-state { + function = "USB2BXHPD1"; + groups = "USB2B"; + }; + pinctrl_usb2bd1_default: usb2bd1-default-state { + function = "USB2BD1"; + groups = "USB2BDBP"; + }; + pinctrl_usb2bxh_default: usb2bxh-default-state { + function = "USB2BXH"; + groups = "USB2BBP"; + }; + pinctrl_usb2bxhp_default: usb2bxhp-default-state { + function = "USB2BXHP"; + groups = "USB2BBP"; + }; + pinctrl_usb2bxh2a_default: usb2bxh2a-default-state { + function = "USB2BXH2A"; + groups = "USB2BAP"; + }; + pinctrl_usb2bxhp2a_default: usb2bxhp2a-default-state { + function = "USB2BXHP2A"; + groups = "USB2BAP"; + }; + pinctrl_usb2bhpd0_default: usb2bhpd0-default-state { + function = "USB2BHPD0"; + groups = "USB2BH"; + }; + pinctrl_usb2bd0_default: usb2bd0-default-state { + function = "USB2BD0"; + groups = "USB2BHBP"; + }; + pinctrl_usb2bh_default: usb2bh-default-state { + function = "USB2BH"; + groups = "USB2BHBP"; + }; + pinctrl_usb2bhp_default: usb2bhp-default-state { + function = "USB2BHP"; + groups = "USB2BHBP"; + }; + pinctrl_jtagm0_default: jtagm0-default-state { + function = "JTAGM0"; + groups = "JTAG0"; + }; + pinctrl_jtag_psp_default: jtag-psp-default-state { + function = "JTAGPSP"; + groups = "JTAG0"; + }; + pinctrl_jtag_ssp_default: jtag-ssp-default-state { + function = "JTAGSSP"; + groups = "JTAG0"; + }; + pinctrl_jtag_tsp_default: jtag-tsp-default-state { + function = "JTAGTSP"; + groups = "JTAG0"; + }; + pinctrl_jtag_ddr_default: jtag-ddr-default-state { + function = "JTAGDDR"; + groups = "JTAG0"; + }; + pinctrl_jtag_usb3a_default: jtag-usb3a-default-state { + function = "JTAGUSB3A"; + groups = "JTAG0"; + }; + pinctrl_jtag_usb3b_default: jtag-usb3b-default-state { + function = "JTAGUSB3B"; + groups = "JTAG0"; + }; + pinctrl_jtag_pciea_default: jtag-pciea-default-state { + function = "JTAGPCIEA"; + groups = "JTAG0"; + }; + pinctrl_jtag_pcieb_default: jtag-pcieb-default-state { + function = "JTAGPCIEB"; + groups = "JTAG0"; + }; + pinctrl_pcierc0_perst_default: pcierc0-perst-default-state { + function = "PCIERC0PERST"; + groups = "PCIERC0PERST"; + }; + pinctrl_pcierc1_perst_default: pcierc1-perst-default-state { + function = "PCIERC1PERST"; + groups = "PCIERC1PERST"; + }; +}; diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7-soc0.dtsi b/arch/arm64/boot/dts/aspeed/aspeed-g7-soc0.dtsi new file mode 100644 index 000000000000..db42db2592e0 --- /dev/null +++ b/arch/arm64/boot/dts/aspeed/aspeed-g7-soc0.dtsi @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree Source for AST27xx SoC Family Main Domain peripherals + * + * Copyright (C) 2026 ASPEED Technology Inc. + */ + +#include +#include +#include + +&soc0 { + sram0: sram@10000000 { + compatible = "mmio-sram"; + reg = <0x0 0x10000000 0x0 0x20000>; + ranges = <0x0 0x0 0x10000000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + + soc0-sram@0 { + reg = <0x0 0x20000>; + export; + }; + }; + + vhuba1: usb-vhub@12011000 { + compatible = "aspeed,ast2700-usb-vhub"; + reg = <0x0 0x12011000 0x0 0x820>; + interrupts-extended = <&intc0 32>; + clocks = <&syscon0 SCU0_CLK_GATE_PORTAUSB2CLK>; + resets = <&syscon0 SCU0_RESET_PORTA_VHUB>; + aspeed,vhub-downstream-ports = <7>; + aspeed,vhub-generic-endpoints = <21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2axhpd1_default>; + status = "disabled"; + }; + + vhubb1: usb-vhub@12021000 { + compatible = "aspeed,ast2700-usb-vhub"; + reg = <0x0 0x12021000 0x0 0x820>; + interrupts-extended = <&intc0 36>; + clocks = <&syscon0 SCU0_CLK_GATE_PORTBUSB2CLK>; + resets = <&syscon0 SCU0_RESET_PORTB_VHUB>; + aspeed,vhub-downstream-ports = <7>; + aspeed,vhub-generic-endpoints = <21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2bxhpd1_default>; + status = "disabled"; + }; + + uhci0: usb@12040000 { + compatible = "aspeed,ast2700-uhci", "generic-uhci"; + reg = <0x0 0x12040000 0x0 0x100>; + interrupts-extended = <&intc0 10>; + #ports = <2>; + clocks = <&syscon0 SCU0_CLK_GATE_UHCICLK>; + resets = <&syscon0 SCU0_RESET_UHCI>; + status = "disabled"; + }; + + vhuba0: usb-vhub@12060000 { + compatible = "aspeed,ast2700-usb-vhub"; + reg = <0x0 0x12060000 0x0 0x820>; + interrupts-extended = <&intc0 33>; + clocks = <&syscon0 SCU0_CLK_GATE_PORTAUSB2CLK>; + resets = <&syscon0 SCU0_RESET_PORTA_VHUB_EHCI>; + aspeed,vhub-downstream-ports = <7>; + aspeed,vhub-generic-endpoints = <21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2ad0_default>; + status = "disabled"; + }; + + ehci0: usb@12061000 { + compatible = "aspeed,ast2700-ehci", "generic-ehci"; + reg = <0x0 0x12061000 0x0 0x100>; + interrupts-extended = <&intc0 33>; + clocks = <&syscon0 SCU0_CLK_GATE_PORTAUSB2CLK>; + resets = <&syscon0 SCU0_RESET_PORTA_VHUB_EHCI>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2ah_default>; + status = "disabled"; + }; + + vhubb0: usb-vhub@12062000 { + compatible = "aspeed,ast2700-usb-vhub"; + reg = <0x0 0x12062000 0x0 0x820>; + interrupts-extended = <&intc0 37>; + clocks = <&syscon0 SCU0_CLK_GATE_PORTBUSB2CLK>; + resets = <&syscon0 SCU0_RESET_PORTB_VHUB_EHCI>; + aspeed,vhub-downstream-ports = <7>; + aspeed,vhub-generic-endpoints = <21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2bd0_default>; + status = "disabled"; + }; + + ehci1: usb@12063000 { + compatible = "aspeed,ast2700-ehci", "generic-ehci"; + reg = <0x0 0x12063000 0x0 0x100>; + interrupts-extended = <&intc0 37>; + clocks = <&syscon0 SCU0_CLK_GATE_PORTBUSB2CLK>; + resets = <&syscon0 SCU0_RESET_PORTB_VHUB_EHCI>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2bh_default>; + status = "disabled"; + }; + + emmc_controller: sdc@12090000 { + compatible = "aspeed,ast2700-sd-controller", "aspeed,ast2600-sd-controller"; + reg = <0 0x12090000 0 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x12090000 0x10000>; + clocks = <&syscon0 SCU0_CLK_GATE_EMMCCLK>; + resets = <&syscon0 SCU0_RESET_EMMC>; + status = "disabled"; + + emmc: sdhci@100 { + compatible = "aspeed,ast2700-sdhci", "aspeed,ast2600-sdhci"; + reg = <0x100 0x100>; + sdhci,auto-cmd12; + interrupts-extended = <&intc0 15>; + clocks = <&syscon0 SCU0_CLK_GATE_EMMCCLK>; + status = "disabled"; + }; + }; + + intc0: interrupt-controller@12100000 { + compatible = "aspeed,ast2700-intc0"; + reg = <0x0 0x12100000 0x0 0x3c00>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + aspeed,interrupt-ranges = + <0 128 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* linear range 1 to 1*/ + <144 8 &gic GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, /* sw int SSP */ + <152 8 &gic GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, /* sw int TSP */ + <192 10 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* M0-M9 intm */ + <208 10 &gic GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, /* M30-M39 intm */ + <224 10 &gic GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* M40-M49 intm */ + <256 128 &ssp_nvic 0 0 >, /* linear to SSP */ + <384 10 &ssp_nvic 160 0 >, /* cascaded to SSP via M10-M19 */ + <400 8 &ssp_nvic 144 0 >, /* sw int PSP */ + <408 8 &ssp_nvic 152 0 >, /* sw int TSP */ + <426 128 &tsp_nvic 0 0 >, /* linear to TSP */ + <554 10 &tsp_nvic 160 0 >, /* cascaded to TSP via M20-M29 */ + <570 8 &tsp_nvic 144 0 >, /* sw int PSP */ + <578 8 &tsp_nvic 152 0 >; /* sw int TSP */ + }; + + syscon0: syscon@12c02000 { + compatible = "aspeed,ast2700-scu0", "syscon", "simple-mfd"; + reg = <0x0 0x12c02000 0x0 0x1000>; + ranges = <0x0 0x0 0x12c02000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + #clock-cells = <1>; + #reset-cells = <1>; + + silicon-id@0 { + compatible = "aspeed,ast2700-silicon-id", "aspeed,silicon-id"; + reg = <0x0 0x4>; + }; + + scu_ic0: interrupt-controller@1d0 { + compatible = "aspeed,ast2700-scu-ic0"; + reg = <0x1d0 0xc>; + interrupts-extended = <&intc0 97>; + #interrupt-cells = <1>; + interrupt-controller; + }; + + scu_ic1: interrupt-controller@1e0 { + compatible = "aspeed,ast2700-scu-ic1"; + reg = <0x1e0 0xc>; + interrupts-extended = <&intc0 98>; + #interrupt-cells = <1>; + interrupt-controller; + }; + + pinctrl0: pinctrl@400 { + compatible = "aspeed,ast2700-soc0-pinctrl"; + reg = <0x400 0x318>; + }; + }; + + gpio0: gpio@12c11000 { + #gpio-cells = <2>; + gpio-controller; + compatible = "aspeed,ast2700-gpio"; + reg = <0x0 0x12c11000 0x0 0x1000>; + interrupts-extended = <&intc0 11>; + gpio-ranges = <&pinctrl0 0 0 12>; + ngpios = <12>; + clocks = <&syscon0 SCU0_CLK_APB>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart4: serial@12c1a000 { + compatible = "ns16550a"; + reg = <0x0 0x12c1a000 0x0 0x1000>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon0 SCU0_CLK_GATE_UART4CLK>; + interrupts-extended = <&intc0 8>; + no-loopback-test; + status = "disabled"; + }; + + mbox0: mbox@12c1c200 { + compatible = "aspeed,ast2700-mailbox"; + reg = <0x0 0x12c1c200 0x0 0x100>, <0x0 0x12c1c300 0x0 0x100>; + reg-names = "tx", "rx"; + interrupts-extended = <&intc0 103>; + #mbox-cells = <1>; + }; + + mbox1: mbox@12c1c600 { + compatible = "aspeed,ast2700-mailbox"; + reg = <0x0 0x12c1c600 0x0 0x100>, <0x0 0x12c1c700 0x0 0x100>; + reg-names = "tx", "rx"; + interrupts-extended = <&intc0 107>; + #mbox-cells = <1>; + }; +}; + +#include "aspeed-g7-soc0-pinctrl.dtsi" diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7-soc1-pinctrl.dtsi b/arch/arm64/boot/dts/aspeed/aspeed-g7-soc1-pinctrl.dtsi new file mode 100644 index 000000000000..72d93323593d --- /dev/null +++ b/arch/arm64/boot/dts/aspeed/aspeed-g7-soc1-pinctrl.dtsi @@ -0,0 +1,1113 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +// Copyright 2025 ASPEED Corp. + +&pinctrl1 { + pinctrl_sgpm0_default: sgpm0-default-state { + function = "SGPM0"; + groups = "SGPM0"; + }; + + pinctrl_dsgpm0_default: dsgpm0-default-state { + function = "SGPM0"; + groups = "DSGPM0"; + }; + + pinctrl_sgpm1_default: sgpm1-default-state { + function = "SGPM1"; + groups = "SGPM1"; + }; + + pinctrl_sgps_default: sgps-default-state { + function = "SGPS"; + groups = "SGPS"; + }; + + pinctrl_adc0_default: adc0-default-state { + function = "ADC0"; + groups = "ADC0"; + }; + + pinctrl_adc1_default: adc1-default-state { + function = "ADC1"; + groups = "ADC1"; + }; + + pinctrl_adc2_default: adc2-default-state { + function = "ADC2"; + groups = "ADC2"; + }; + + pinctrl_adc3_default: adc3-default-state { + function = "ADC3"; + groups = "ADC3"; + }; + + pinctrl_adc4_default: adc4-default-state { + function = "ADC4"; + groups = "ADC4"; + }; + + pinctrl_adc5_default: adc5-default-state { + function = "ADC5"; + groups = "ADC5"; + }; + + pinctrl_adc6_default: adc6-default-state { + function = "ADC6"; + groups = "ADC6"; + }; + + pinctrl_adc7_default: adc7-default-state { + function = "ADC7"; + groups = "ADC7"; + }; + + pinctrl_adc8_default: adc8-default-state { + function = "ADC8"; + groups = "ADC8"; + }; + + pinctrl_adc9_default: adc9-default-state { + function = "ADC9"; + groups = "ADC9"; + }; + + pinctrl_adc10_default: adc10-default-state { + function = "ADC10"; + groups = "ADC10"; + }; + + pinctrl_adc11_default: adc11-default-state { + function = "ADC11"; + groups = "ADC11"; + }; + + pinctrl_adc12_default: adc12-default-state { + function = "ADC12"; + groups = "ADC12"; + }; + + pinctrl_adc13_default: adc13-default-state { + function = "ADC13"; + groups = "ADC13"; + }; + + pinctrl_adc14_default: adc14-default-state { + function = "ADC14"; + groups = "ADC14"; + }; + + pinctrl_adc15_default: adc15-default-state { + function = "ADC15"; + groups = "ADC15"; + }; + + pinctrl_pwm0_default: pwm0-default-state { + function = "PWM0"; + groups = "PWM0"; + }; + + pinctrl_pwm1_default: pwm1-default-state { + function = "PWM1"; + groups = "PWM1"; + }; + + pinctrl_pwm2_default: pwm2-default-state { + function = "PWM2"; + groups = "PWM2"; + }; + + pinctrl_pwm3_default: pwm3-default-state { + function = "PWM3"; + groups = "PWM3"; + }; + + pinctrl_pwm4_default: pwm4-default-state { + function = "PWM4"; + groups = "PWM4"; + }; + + pinctrl_pwm5_default: pwm5-default-state { + function = "PWM5"; + groups = "PWM5"; + }; + + pinctrl_pwm6_default: pwm6-default-state { + function = "PWM6"; + groups = "PWM6"; + }; + + pinctrl_pwm7_default: pwm7-default-state { + function = "PWM7"; + groups = "PWM7"; + }; + + pinctrl_pwm8_default: pwm8-default-state { + function = "PWM8"; + groups = "PWM8"; + }; + + pinctrl_pwm9_default: pwm9-default-state { + function = "PWM9"; + groups = "PWM9"; + }; + + pinctrl_pwm10_default: pwm10-default-state { + function = "PWM10"; + groups = "PWM10"; + }; + + pinctrl_pwm11_default: pwm11-default-state { + function = "PWM11"; + groups = "PWM11"; + }; + + pinctrl_pwm12_default: pwm12-default-state { + function = "PWM12"; + groups = "PWM12"; + }; + + pinctrl_pwm13_default: pwm13-default-state { + function = "PWM13"; + groups = "PWM13"; + }; + + pinctrl_pwm14_default: pwm14-default-state { + function = "PWM14"; + groups = "PWM14"; + }; + + pinctrl_pwm15_default: pwm15-default-state { + function = "PWM15"; + groups = "PWM15"; + }; + + pinctrl_tach0_default: tach0-default-state { + function = "TACH0"; + groups = "TACH0"; + }; + + pinctrl_tach1_default: tach1-default-state { + function = "TACH1"; + groups = "TACH1"; + }; + + pinctrl_tach2_default: tach2-default-state { + function = "TACH2"; + groups = "TACH2"; + }; + + pinctrl_tach3_default: tach3-default-state { + function = "TACH3"; + groups = "TACH3"; + }; + + pinctrl_tach4_default: tach4-default-state { + function = "TACH4"; + groups = "TACH4"; + }; + + pinctrl_tach5_default: tach5-default-state { + function = "TACH5"; + groups = "TACH5"; + }; + + pinctrl_tach6_default: tach6-default-state { + function = "TACH6"; + groups = "TACH6"; + }; + + pinctrl_tach7_default: tach7-default-state { + function = "TACH7"; + groups = "TACH7"; + }; + + pinctrl_tach8_default: tach8-default-state { + function = "TACH8"; + groups = "TACH8"; + }; + + pinctrl_tach9_default: tach9-default-state { + function = "TACH9"; + groups = "TACH9"; + }; + + pinctrl_tach10_default: tach10-default-state { + function = "TACH10"; + groups = "TACH10"; + }; + + pinctrl_tach11_default: tach11-default-state { + function = "TACH11"; + groups = "TACH11"; + }; + + pinctrl_tach12_default: tach12-default-state { + function = "TACH12"; + groups = "TACH12"; + }; + + pinctrl_tach13_default: tach13-default-state { + function = "TACH13"; + groups = "TACH13"; + }; + + pinctrl_tach14_default: tach14-default-state { + function = "TACH14"; + groups = "TACH14"; + }; + + pinctrl_tach15_default: tach15-default-state { + function = "TACH15"; + groups = "TACH15"; + }; + + pinctrl_jtagm1_default: jtagm1-default-state { + function = "JTAGM1"; + groups = "JTAGM1"; + }; + + pinctrl_mdio0_default: mdio0-default-state { + function = "MDIO0"; + groups = "MDIO0"; + }; + + pinctrl_mdio1_default: mdio1-default-state { + function = "MDIO1"; + groups = "MDIO1"; + }; + + pinctrl_mdio2_default: mdio2-default-state { + function = "MDIO2"; + groups = "MDIO2"; + }; + + pinctrl_rgmii0_default: rgmii0-default-state { + function = "RGMII0"; + groups = "RGMII0"; + }; + + pinctrl_rgmii1_default: rgmii1-default-state { + function = "RGMII1"; + groups = "RGMII1"; + }; + + pinctrl_rmii0_default: rmii0-default-state { + function = "RMII0"; + groups = "RMII0"; + }; + + pinctrl_rmii0_rclko_default: rmii0-rclko-default-state { + function = "RMII0RCLKO"; + groups = "RMII0RCLKO"; + }; + + pinctrl_rmii1_default: rmii1-default-state { + function = "RMII1"; + groups = "RMII1"; + }; + + pinctrl_rmii1_rclko_default: rmii1-rclko-default-state { + function = "RMII1RCLKO"; + groups = "RMII1RCLKO"; + }; + + pinctrl_sgmii_default: sgmii-default-state { + function = "SGMII"; + groups = "SGMII"; + }; + + pinctrl_fwspi_quad_default: fwspi-quad-default-state { + function = "FWQSPI"; + groups = "FWQSPI"; + }; + + pinctrl_fsi0_default: fsi0-default-state { + function = "FSI0"; + groups = "FSI0"; + }; + + pinctrl_fsi1_default: fsi1-default-state { + function = "FSI1"; + groups = "FSI1"; + }; + + pinctrl_fsi2_default: fsi2-default-state { + function = "FSI2"; + groups = "FSI2"; + }; + + pinctrl_fsi3_default: fsi3-default-state { + function = "FSI3"; + groups = "FSI3"; + }; + + pinctrl_spi0_default: spi0-default-state { + function = "SPI0"; + groups = "SPI0"; + }; + + pinctrl_spi0_quad_default: spi0-quad-default-state { + function = "QSPI0"; + groups = "QSPI0"; + }; + + pinctrl_spi0_cs1_default: spi0-cs1-default-state { + function = "SPI0CS1"; + groups = "SPI0CS1"; + }; + + pinctrl_spi1_default: spi1-default-state { + function = "SPI1"; + groups = "SPI1"; + }; + + pinctrl_spi1_quad_default: spi1-quad-default-state { + function = "QSPI1"; + groups = "QSPI1"; + }; + + pinctrl_spi1_cs1_default: spi1-cs1-default-state { + function = "SPI1CS1"; + groups = "SPI1CS1"; + }; + + pinctrl_spi2_default: spi2-default-state { + function = "SPI2"; + groups = "SPI2"; + }; + + pinctrl_spi2_quad_default: spi2-quad-default-state { + function = "QSPI2"; + groups = "QSPI2"; + }; + + pinctrl_spi2_cs1_default: spi2-cs1-default-state { + function = "SPI2CS1"; + groups = "SPI2CS1"; + }; + + pinctrl_espi0_default: espi0-default-state { + function = "ESPI0"; + groups = "ESPI0"; + }; + + pinctrl_espi1_default: espi1-default-state { + function = "ESPI1"; + groups = "ESPI1"; + }; + + pinctrl_lpc0_default: lpc0-default-state { + function = "LPC0"; + groups = "LPC0"; + }; + + pinctrl_lpc1_default: lpc1-default-state { + function = "LPC1"; + groups = "LPC1"; + }; + + pinctrl_vpi_default: vpi-default-state { + function = "VPI"; + groups = "VPI"; + }; + + pinctrl_sd_default: sd-default-state { + function = "SD"; + groups = "SD"; + }; + + pinctrl_hvi3c0_default: hvi3c0-default-state { + function = "I3C0"; + groups = "HVI3C0"; + }; + + pinctrl_hvi3c1_default: hvi3c1-default-state { + function = "I3C1"; + groups = "HVI3C1"; + }; + + pinctrl_hvi3c2_default: hvi3c2-default-state { + function = "I3C2"; + groups = "HVI3C2"; + }; + + pinctrl_hvi3c3_default: hvi3c3-default-state { + function = "I3C3"; + groups = "HVI3C3"; + }; + + pinctrl_i3c4_default: i3c4-default-state { + function = "I3C4"; + groups = "I3C4"; + }; + + pinctrl_i3c5_default: i3c5-default-state { + function = "I3C5"; + groups = "I3C5"; + }; + + pinctrl_i3c6_default: i3c6-default-state { + function = "I3C6"; + groups = "I3C6"; + }; + + pinctrl_i3c7_default: i3c7-default-state { + function = "I3C7"; + groups = "I3C7"; + }; + + pinctrl_i3c8_default: i3c8-default-state { + function = "I3C8"; + groups = "I3C8"; + }; + + pinctrl_i3c9_default: i3c9-default-state { + function = "I3C9"; + groups = "I3C9"; + }; + + pinctrl_i3c10_default: i3c10-default-state { + function = "I3C10"; + groups = "I3C10"; + }; + + pinctrl_i3c11_default: i3c11-default-state { + function = "I3C11"; + groups = "I3C11"; + }; + + pinctrl_hvi3c12_default: hvi3c12-default-state { + function = "I3C12"; + groups = "HVI3C12"; + }; + + pinctrl_hvi3c13_default: hvi3c13-default-state { + function = "I3C13"; + groups = "HVI3C13"; + }; + + pinctrl_hvi3c14_default: hvi3c14-default-state { + function = "I3C14"; + groups = "HVI3C14"; + }; + + pinctrl_hvi3c15_default: hvi3c15-default-state { + function = "I3C15"; + groups = "HVI3C15"; + }; + + pinctrl_tach0_default: tach0-default-state { + function = "TACH0"; + groups = "TACH0"; + }; + + pinctrl_tach1_default: tach1-default-state { + function = "TACH1"; + groups = "TACH1"; + }; + + pinctrl_tach2_default: tach2-default-state { + function = "TACH2"; + groups = "TACH2"; + }; + + pinctrl_tach3_default: tach3-default-state { + function = "TACH3"; + groups = "TACH3"; + }; + + pinctrl_tach4_default: tach4-default-state { + function = "TACH4"; + groups = "TACH4"; + }; + + pinctrl_tach5_default: tach5-default-state { + function = "TACH5"; + groups = "TACH5"; + }; + + pinctrl_tach6_default: tach6-default-state { + function = "TACH6"; + groups = "TACH6"; + }; + + pinctrl_tach7_default: tach7-default-state { + function = "TACH7"; + groups = "TACH7"; + }; + + pinctrl_tach8_default: tach8-default-state { + function = "TACH8"; + groups = "TACH8"; + }; + + pinctrl_tach9_default: tach9-default-state { + function = "TACH9"; + groups = "TACH9"; + }; + + pinctrl_tach10_default: tach10-default-state { + function = "TACH10"; + groups = "TACH10"; + }; + + pinctrl_tach11_default: tach11-default-state { + function = "TACH11"; + groups = "TACH11"; + }; + + pinctrl_tach12_default: tach12-default-state { + function = "TACH12"; + groups = "TACH12"; + }; + + pinctrl_tach13_default: tach13-default-state { + function = "TACH13"; + groups = "TACH13"; + }; + + pinctrl_tach14_default: tach14-default-state { + function = "TACH14"; + groups = "TACH14"; + }; + + pinctrl_tach15_default: tach15-default-state { + function = "TACH15"; + groups = "TACH15"; + }; + + pinctrl_thru0_default: thru0-default-state { + function = "THRU0"; + groups = "THRU0"; + }; + + pinctrl_thru1_default: thru1-default-state { + function = "THRU1"; + groups = "THRU1"; + }; + + pinctrl_thru2_default: thru2-default-state { + function = "THRU2"; + groups = "THRU2"; + }; + + pinctrl_thru3_default: thru3-default-state { + function = "THRU3"; + groups = "THRU3"; + }; + + pinctrl_ncts5_default: ncts5-default-state { + function = "NCTS5"; + groups = "NCTS5"; + }; + + pinctrl_ndcd5_default: ndcd5-default-state { + function = "NDCD5"; + groups = "NDCD5"; + }; + + pinctrl_ndsr5_default: ndsr5-default-state { + function = "NDSR5"; + groups = "NDSR5"; + }; + + pinctrl_nri5_default: nri5-default-state { + function = "NRI5"; + groups = "NRI5"; + }; + + pinctrl_i2c0_default: i2c0-default-state { + function = "I2C0"; + groups = "I2C0"; + }; + + pinctrl_i2c1_default: i2c1-default-state { + function = "I2C1"; + groups = "I2C1"; + }; + + pinctrl_i2c2_default: i2c2-default-state { + function = "I2C2"; + groups = "I2C2"; + }; + + pinctrl_i2c3_default: i2c3-default-state { + function = "I2C3"; + groups = "I2C3"; + }; + + pinctrl_i2c4_default: i2c4-default-state { + function = "I2C4"; + groups = "I2C4"; + }; + + pinctrl_i2c5_default: i2c5-default-state { + function = "I2C5"; + groups = "I2C5"; + }; + + pinctrl_i2c6_default: i2c6-default-state { + function = "I2C6"; + groups = "I2C6"; + }; + + pinctrl_i2c7_default: i2c7-default-state { + function = "I2C7"; + groups = "I2C7"; + }; + + pinctrl_i2c8_default: i2c8-default-state { + function = "I2C8"; + groups = "I2C8"; + }; + + pinctrl_i2c9_default: i2c9-default-state { + function = "I2C9"; + groups = "I2C9"; + }; + + pinctrl_i2c10_default: i2c10-default-state { + function = "I2C10"; + groups = "I2C10"; + }; + + pinctrl_i2c11_default: i2c11-default-state { + function = "I2C11"; + groups = "I2C11"; + }; + + pinctrl_i2c12_default: i2c12-default-state { + function = "I2C12"; + groups = "I2C12"; + }; + + pinctrl_i2c13_default: i2c13-default-state { + function = "I2C13"; + groups = "I2C13"; + }; + + pinctrl_i2c14_default: i2c14-default-state { + function = "I2C14"; + groups = "I2C14"; + }; + + pinctrl_i2c15_default: i2c15-default-state { + function = "I2C15"; + groups = "I2C15"; + }; + + pinctrl_salt0_default: salt0-default-state { + function = "SALT0"; + groups = "SALT0"; + }; + + pinctrl_salt1_default: salt1-default-state { + function = "SALT1"; + groups = "SALT1"; + }; + + pinctrl_salt2_default: salt2-default-state { + function = "SALT2"; + groups = "SALT2"; + }; + + pinctrl_salt3_default: salt3-default-state { + function = "SALT3"; + groups = "SALT3"; + }; + + pinctrl_salt4_default: salt4-default-state { + function = "SALT4"; + groups = "SALT4"; + }; + + pinctrl_salt5_default: salt5-default-state { + function = "SALT5"; + groups = "SALT5"; + }; + + pinctrl_salt6_default: salt6-default-state { + function = "SALT6"; + groups = "SALT6"; + }; + + pinctrl_salt7_default: salt7-default-state { + function = "SALT7"; + groups = "SALT7"; + }; + + pinctrl_salt8_default: salt8-default-state { + function = "SALT8"; + groups = "SALT8"; + }; + + pinctrl_salt9_default: salt9-default-state { + function = "SALT9"; + groups = "SALT9"; + }; + + pinctrl_salt10_default: salt10-default-state { + function = "SALT10"; + groups = "SALT10"; + }; + + pinctrl_salt11_default: salt11-default-state { + function = "SALT11"; + groups = "SALT11"; + }; + + pinctrl_salt12_default: salt12-default-state { + function = "SALT12"; + groups = "SALT12"; + }; + + pinctrl_salt13_default: salt13-default-state { + function = "SALT13"; + groups = "SALT13"; + }; + + pinctrl_salt14_default: salt14-default-state { + function = "SALT14"; + groups = "SALT14"; + }; + + pinctrl_salt15_default: salt15-default-state { + function = "SALT15"; + groups = "SALT15"; + }; + + pinctrl_ltpipsi2c0_default: ltpipsi2c0-default-state { + function = "I2C0"; + groups = "LTPI_PS_I2C0"; + }; + + pinctrl_ltpipsi2c1_default: ltpipsi2c1-default-state { + function = "I2C1"; + groups = "LTPI_PS_I2C1"; + }; + + pinctrl_ltpipsi2c2_default: ltpipsi2c2-default-state { + function = "I2C2"; + groups = "LTPI_PS_I2C2"; + }; + + pinctrl_ltpipsi2c3_default: ltpipsi2c3-default-state { + function = "I2C3"; + groups = "LTPI_PS_I2C3"; + }; + + pinctrl_can_default: can-default-state { + function = "CANBUS"; + groups = "CANBUS"; + }; + + pinctrl_di2c0_default: di2c0-default-state { + function = "I2C0"; + groups = "DI2C0"; + }; + + pinctrl_di2c1_default: di2c1-default-state { + function = "I2C1"; + groups = "DI2C1"; + }; + + pinctrl_di2c2_default: di2c2-default-state { + function = "I2C2"; + groups = "DI2C2"; + }; + + pinctrl_di2c3_default: di2c3-default-state { + function = "I2C3"; + groups = "DI2C3"; + }; + pinctrl_di2c8_default: di2c8-default-state { + function = "I2C8"; + groups = "DI2C8"; + }; + + pinctrl_di2c9_default: di2c9-default-state { + function = "I2C9"; + groups = "DI2C9"; + }; + + pinctrl_di2c10_default: di2c10-default-state { + function = "I2C10"; + groups = "DI2C10"; + }; + + pinctrl_di2c11_default: di2c11-default-state { + function = "I2C11"; + groups = "DI2C11"; + }; + + pinctrl_di2c12_default: di2c12-default-state { + function = "I2C12"; + groups = "DI2C12"; + }; + + pinctrl_di2c13_default: di2c13-default-state { + function = "I2C13"; + groups = "DI2C13"; + }; + + pinctrl_di2c14_default: di2c14-default-state { + function = "I2C14"; + groups = "DI2C14"; + }; + + pinctrl_di2c15_default: di2c15-default-state { + function = "I2C15"; + groups = "DI2C15"; + }; + + pinctrl_ncts0_default: ncts0-default-state { + function = "NCTS0"; + groups = "NCTS0"; + }; + + pinctrl_ndcd0_default: ndcd0-default-state { + function = "NDCD0"; + groups = "NDCD0"; + }; + + pinctrl_ndsr0_default: ndsr0-default-state { + function = "NDSR0"; + groups = "NDSR0"; + }; + + pinctrl_nri0_default: nri0-default-state { + function = "NRI0"; + groups = "NRI0"; + }; + + pinctrl_ndtr0_default: ndtr0-default-state { + function = "NDTR0"; + groups = "NDTR0"; + }; + + pinctrl_nrts0_default: nrts0-default-state { + function = "NRTS0"; + groups = "NRTS0"; + }; + + pinctrl_uart0_default: uart0-default-state { + function = "UART0"; + groups = "UART0"; + }; + + pinctrl_ncts1_default: ncts1-default-state { + function = "NCTS1"; + groups = "NCTS1"; + }; + + pinctrl_ndcd1_default: ndcd1-default-state { + function = "NDCD1"; + groups = "NDCD1"; + }; + + pinctrl_ndsr1_default: ndsr1-default-state { + function = "NDSR1"; + groups = "NDSR1"; + }; + + pinctrl_nri1_default: nri1-default-state { + function = "NRI1"; + groups = "NRI1"; + }; + + pinctrl_ndtr1_default: ndtr1-default-state { + function = "NDTR1"; + groups = "NDTR1"; + }; + + pinctrl_nrts1_default: nrts1-default-state { + function = "NRTS1"; + groups = "NRTS1"; + }; + + pinctrl_uart1_default: uart1-default-state { + function = "UART1"; + groups = "UART1"; + }; + + pinctrl_uart2_default: uart2-default-state { + function = "UART2"; + groups = "UART2"; + }; + + pinctrl_uart3_default: uart3-default-state { + function = "UART3"; + groups = "UART3"; + }; + + pinctrl_ncts5_default: ncts5-default-state { + function = "NCTS5"; + groups = "NCTS5"; + }; + + pinctrl_ndcd5_default: ndcd5-default-state { + function = "NDCD5"; + groups = "NDCD5"; + }; + + pinctrl_ndsr5_default: ndsr5-default-state { + function = "NDSR5"; + groups = "NDSR5"; + }; + + pinctrl_nri5_default: nri5-default-state { + function = "NRI5"; + groups = "NRI5"; + }; + + pinctrl_ndtr5_default: ndtr5-default-state { + function = "NDTR5"; + groups = "NDTR5"; + }; + + pinctrl_nrts5_default: nrts5-default-state { + function = "NRTS5"; + groups = "NRTS5"; + }; + + pinctrl_uart5_default: uart5-default-state { + function = "UART5"; + groups = "UART5"; + }; + + pinctrl_ncts6_default: ncts6-default-state { + function = "NCTS6"; + groups = "NCTS6"; + }; + + pinctrl_ndcd6_default: ndcd6-default-state { + function = "NDCD6"; + groups = "NDCD6"; + }; + + pinctrl_ndsr6_default: ndsr6-default-state { + function = "NDSR6"; + groups = "NDSR6"; + }; + + pinctrl_nri6_default: nri6-default-state { + function = "NRI6"; + groups = "NRI6"; + }; + + pinctrl_ndtr6_default: ndtr6-default-state { + function = "NDTR6"; + groups = "NDTR6"; + }; + + pinctrl_nrts6_default: nrts6-default-state { + function = "NRTS6"; + groups = "NRTS6"; + }; + + pinctrl_uart6_default: uart6-default-state { + function = "UART6"; + groups = "UART6"; + }; + + pinctrl_uart7_default: uart7-default-state { + function = "UART7"; + groups = "UART7"; + }; + + pinctrl_uart8_default: uart8-default-state { + function = "UART8"; + groups = "UART8"; + }; + + pinctrl_uart9_default: uart9-default-state { + function = "UART9"; + groups = "UART9"; + }; + + pinctrl_uart10_default: uart10-default-state { + function = "UART10"; + groups = "UART10"; + }; + + pinctrl_uart11_default: uart11-default-state { + function = "UART11"; + groups = "UART11"; + }; + + pinctrl_pcierc2_perst_default: pcierc2-perst-default-state { + function = "PCIERC"; + groups = "PE2SGRSTN"; + }; + + pinctrl_usb2cud_default: usb2cud-default-state { + function = "USB2C"; + groups = "USB2CUD"; + }; + + pinctrl_usb2cd_default: usb2cd-default-state { + function = "USB2C"; + groups = "USB2CD"; + }; + + pinctrl_usb2ch_default: usb2ch-default-state { + function = "USB2C"; + groups = "USB2CH"; + }; + + pinctrl_usb2cu_default: usb2cu-default-state { + function = "USB2C"; + groups = "USB2CU"; + }; + + pinctrl_usb2dd_default: usb2dd-default-state { + function = "USB2D"; + groups = "USB2DD"; + }; + + pinctrl_usb2dh_default: usb2dh-default-state { + function = "USB2D"; + groups = "USB2DH"; + }; + + pinctrl_wdtrst0n_default: wdtrst0n-default-state { + function = "WDTRST0N"; + groups = "WDTRST0N"; + }; + + pinctrl_wdtrst1n_default: wdtrst1n-default-state { + function = "WDTRST1N"; + groups = "WDTRST1N"; + }; + + pinctrl_wdtrst2n_default: wdtrst2n-default-state { + function = "WDTRST2N"; + groups = "WDTRST2N"; + }; + + pinctrl_wdtrst3n_default: wdtrst3n-default-state { + function = "WDTRST3N"; + groups = "WDTRST3N"; + }; + + pinctrl_wdtrst4n_default: wdtrst4n-default-state { + function = "WDTRST4N"; + groups = "WDTRST4N"; + }; + + pinctrl_wdtrst5n_default: wdtrst5n-default-state { + function = "WDTRST5N"; + groups = "WDTRST5N"; + }; + + pinctrl_wdtrst6n_default: wdtrst6n-default-state { + function = "WDTRST6N"; + groups = "WDTRST6N"; + }; + + pinctrl_wdtrst7n_default: wdtrst7n-default-state { + function = "WDTRST7N"; + groups = "WDTRST7N"; + }; +}; diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7-soc1.dtsi b/arch/arm64/boot/dts/aspeed/aspeed-g7-soc1.dtsi new file mode 100644 index 000000000000..bc990f79e693 --- /dev/null +++ b/arch/arm64/boot/dts/aspeed/aspeed-g7-soc1.dtsi @@ -0,0 +1,557 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree Source for AST27xx SoC Family Main Domain peripherals + * + * Copyright (C) 2026 ASPEED Technology Inc. + */ + +#include +#include +#include + +&soc1 { + fmc: spi@14000000 { + reg = <0x0 0x14000000 0x0 0xc4>, <0x1 0x00000000 0x0 0x80000000>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2700-fmc"; + status = "disabled"; + clocks = <&syscon1 SCU1_CLK_AHB>; + interrupts-extended = <&intc1 121>; + num-cs = <3>; + + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; + status = "disabled"; + }; + + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; + status = "disabled"; + }; + + flash@2 { + reg = < 2 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; + status = "disabled"; + }; + }; + + spi0: spi@14010000 { + reg = <0x0 0x14010000 0x0 0xc4>, <0x1 0x80000000 0x0 0x80000000>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2700-spi"; + clocks = <&syscon1 SCU1_CLK_AHB>; + interrupts-extended = <&intc1 122>; + status = "disabled"; + num-cs = <2>; + + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; + status = "disabled"; + }; + + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; + status = "disabled"; + }; + }; + + spi1: spi@14020000 { + reg = <0x0 0x14020000 0x0 0xc4>, <0x2 0x00000000 0x0 0x80000000>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2700-spi"; + clocks = <&syscon1 SCU1_CLK_AHB>; + interrupts-extended = <&intc1 123>; + status = "disabled"; + num-cs = <2>; + + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; + status = "disabled"; + }; + + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; + status = "disabled"; + }; + }; + + spi2: spi@14030000 { + reg = <0x0 0x14030000 0x0 0x1f0>, <0x2 0x80000000 0x0 0x80000000>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2700-spi"; + clocks = <&syscon1 SCU1_CLK_AHB>; + resets = <&syscon1 SCU1_RESET_SPI2>; + interrupts-extended = <&intc1 124>; + num-cs = <2>; + status = "disabled"; + }; + + mdio0: mdio@14040000 { + compatible = "aspeed,ast2700-mdio", "aspeed,ast2600-mdio"; + reg = <0 0x14040000 0 0x8>; + resets = <&syscon1 SCU1_RESET_MII>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio0_default>; + status = "disabled"; + }; + + mdio1: mdio@14040008 { + compatible = "aspeed,ast2700-mdio", "aspeed,ast2600-mdio"; + reg = <0 0x14040008 0 0x8>; + resets = <&syscon1 SCU1_RESET_MII>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio1_default>; + status = "disabled"; + }; + + mdio2: mdio@14040010 { + compatible = "aspeed,ast2700-mdio", "aspeed,ast2600-mdio"; + reg = <0 0x14040010 0 0x8>; + resets = <&syscon1 SCU1_RESET_MII>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio2_default>; + status = "disabled"; + }; + + sdio_controller: sdc@14080000 { + compatible = "aspeed,ast2700-sd-controller", "aspeed,ast2600-sd-controller"; + reg = <0 0x14080000 0 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x14080000 0x10000>; + clocks = <&syscon1 SCU1_CLK_GATE_SDCLK>; + resets = <&syscon1 SCU1_RESET_SD>; + status = "disabled"; + + sdhci: sdhci@100 { + compatible = "aspeed,ast2700-sdhci", "aspeed,ast2600-sdhci"; + reg = <0x100 0x100>; + sdhci,auto-cmd12; + interrupts-extended = <&intc1 161>; + clocks = <&syscon1 SCU1_CLK_GATE_SDCLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd_default>; + status = "disabled"; + }; + }; + + pwm_tach: pwm-tach-controller@140c0000 { + compatible = "aspeed,ast2700-pwm-tach", "aspeed,ast2600-pwm-tach"; + reg = <0x0 0x140c0000 0 0x100>; + clocks = <&syscon1 SCU1_CLK_AHB>; + resets = <&syscon1 SCU1_RESET_PWM>; + #pwm-cells = <3>; + status = "disabled"; + }; + + uhci1: usb@14110000 { + compatible = "aspeed,ast2700-uhci", "generic-uhci"; + reg = <0x0 0x14110000 0x0 0x100>; + interrupts-extended = <&intc1 155>; + #ports = <2>; + clocks = <&syscon1 SCU1_CLK_GATE_UHCICLK>; + resets = <&syscon1 SCU1_RESET_UHCI>; + status = "disabled"; + }; + + vhubc: usb-vhub@14120000 { + compatible = "aspeed,ast2700-usb-vhub"; + reg = <0x0 0x14120000 0x0 0x820>; + interrupts-extended = <&intc1 156>; + clocks = <&syscon1 SCU1_CLK_GATE_PORTCUSB2CLK>; + resets = <&syscon1 SCU1_RESET_PORTC_VHUB_EHCI>; + aspeed,vhub-downstream-ports = <7>; + aspeed,vhub-generic-endpoints = <21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2cd_default>; + status = "disabled"; + }; + + ehci2: usb@14121000 { + compatible = "aspeed,ast2700-ehci", "generic-ehci"; + reg = <0x0 0x14121000 0x0 0x100>; + interrupts-extended = <&intc1 156>; + clocks = <&syscon1 SCU1_CLK_GATE_PORTCUSB2CLK>; + resets = <&syscon1 SCU1_RESET_PORTC_VHUB_EHCI>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2ch_default>; + status = "disabled"; + }; + + vhubd: usb-vhub@14122000 { + compatible = "aspeed,ast2700-usb-vhub"; + reg = <0x0 0x14122000 0x0 0x820>; + interrupts-extended = <&intc1 157>; + clocks = <&syscon1 SCU1_CLK_GATE_PORTDUSB2CLK>; + resets = <&syscon1 SCU1_RESET_PORTD_VHUB_EHCI>; + aspeed,vhub-downstream-ports = <7>; + aspeed,vhub-generic-endpoints = <21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2dd_default>; + status = "disabled"; + }; + + ehci3: usb@14123000 { + compatible = "aspeed,ast2700-ehci", "generic-ehci"; + reg = <0x0 0x14123000 0x0 0x100>; + interrupts-extended = <&intc1 157>; + clocks = <&syscon1 SCU1_CLK_GATE_PORTDUSB2CLK>; + resets = <&syscon1 SCU1_RESET_PORTD_VHUB_EHCI>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2dh_default>; + status = "disabled"; + }; + + sram1: sram@14b80000 { + compatible = "mmio-sram"; + reg = <0x0 0x14b80000 0x0 0x40000>; + ranges = <0x0 0x0 0x14b80000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + + soc1-sram@0 { + reg = <0x0 0x40000>; + export; + }; + }; + + adc0: adc@14c00000 { + compatible = "aspeed,ast2700-adc0"; + reg = <0x0 0x14c00000 0 0x100>; + clocks = <&syscon1 SCU1_CLK_AHB>; + resets = <&syscon1 SCU1_RESET_ADC>; + interrupts-extended = <&intc1 80>; + #io-channel-cells = <1>; + status = "disabled"; + }; + + adc1: adc@14c00100 { + compatible = "aspeed,ast2700-adc1"; + reg = <0x0 0x14c00100 0x0 0x100>; + clocks = <&syscon1 SCU1_CLK_AHB>; + resets = <&syscon1 SCU1_RESET_ADC>; + interrupts-extended = <&intc1 80>; + #io-channel-cells = <1>; + status = "disabled"; + }; + + syscon1: syscon@14c02000 { + compatible = "aspeed,ast2700-scu1", "syscon", "simple-mfd"; + reg = <0x0 0x14c02000 0x0 0x1000>; + ranges = <0x0 0x0 0x14c02000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + #clock-cells = <1>; + #reset-cells = <1>; + + scu_ic2: interrupt-controller@100 { + compatible = "aspeed,ast2700-scu-ic2"; + reg = <0x100 0x8>; + interrupts-extended = <&intc1 160>; + #interrupt-cells = <1>; + interrupt-controller; + }; + + scu_ic3: interrupt-controller@108 { + compatible = "aspeed,ast2700-scu-ic3"; + reg = <0x108 0x8>; + interrupts-extended = <&intc1 186>; + #interrupt-cells = <1>; + interrupt-controller; + }; + + pinctrl1: pinctrl@400 { + compatible = "aspeed,ast2700-soc1-pinctrl"; + reg = <0x400 0x2a0>; + }; + }; + + gpio1: gpio@14c0b000 { + #gpio-cells = <2>; + gpio-controller; + compatible = "aspeed,ast2700-gpio"; + reg = <0x0 0x14c0b000 0x0 0x1000>; + interrupts-extended = <&intc1 82>; + gpio-ranges = <&pinctrl1 0 0 216>; + ngpios = <216>; + clocks = <&syscon1 SCU1_CLK_AHB>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sgpiom0: sgpiom@14c0c000 { + #gpio-cells = <2>; + gpio-controller; + compatible = "aspeed,ast2700-sgpiom"; + reg = <0x0 0x14c0c000 0x0 0x100>; + interrupts-extended = <&intc1 85>; + ngpios = <256>; + clocks = <&syscon1 SCU1_CLK_APB>; + interrupt-controller; + #interrupt-cells = <2>; + bus-frequency = <12000000>; + status = "disabled"; + }; + + sgpiom1: sgpiom@14c0d000 { + #gpio-cells = <2>; + gpio-controller; + compatible = "aspeed,ast2700-sgpiom"; + reg = <0x0 0x14c0d000 0x0 0x100>; + interrupts-extended = <&intc1 88>; + ngpios = <256>; + clocks = <&syscon1 SCU1_CLK_APB>; + interrupt-controller; + #interrupt-cells = <2>; + bus-frequency = <12000000>; + status = "disabled"; + }; + + intc1: interrupt-controller@14c18000 { + compatible = "aspeed,ast2700-intc1"; + reg = <0 0x14c18000 0 0x400>; + interrupt-controller; + interrupt-parent = <&intc0>; + #interrupt-cells = <1>; + aspeed,interrupt-ranges = + <0 6 &intc0 480>, /* M0 ~ M5 */ + <10 6 &intc0 490>, /* M10 ~ M15 */ + <20 6 &intc0 500>, /* M20 ~ M25 */ + <30 6 &intc0 510>, /* M30 ~ M35 */ + <40 6 &intc0 520>, /* M40 ~ M45 */ + <50 1 &bootmcu_hlic 11>; /* only 1 pin to BootMCU */ + }; + + uart0: serial@14c33000 { + compatible = "ns16550a"; + reg = <0x0 0x14c33000 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART0CLK>; + interrupts-extended = <&intc1 135>; + no-loopback-test; + status = "disabled"; + }; + + uart1: serial@14c33100 { + compatible = "ns16550a"; + reg = <0x0 0x14c33100 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART1CLK>; + interrupts-extended = <&intc1 136>; + no-loopback-test; + status = "disabled"; + }; + + uart2: serial@14c33200 { + compatible = "ns16550a"; + reg = <0x0 0x14c33200 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART2CLK>; + interrupts-extended = <&intc1 137>; + no-loopback-test; + status = "disabled"; + }; + + uart3: serial@14c33300 { + compatible = "ns16550a"; + reg = <0x0 0x14c33300 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART3CLK>; + interrupts-extended = <&intc1 138>; + no-loopback-test; + status = "disabled"; + }; + + uart5: serial@14c33400 { + compatible = "ns16550a"; + reg = <0x0 0x14c33400 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART5CLK>; + interrupts-extended = <&intc1 139>; + no-loopback-test; + status = "disabled"; + }; + + uart6: serial@14c33500 { + compatible = "ns16550a"; + reg = <0x0 0x14c33500 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART6CLK>; + interrupts-extended = <&intc1 140>; + no-loopback-test; + status = "disabled"; + }; + + uart7: serial@14c33600 { + compatible = "ns16550a"; + reg = <0x0 0x14c33600 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART7CLK>; + interrupts-extended = <&intc1 141>; + no-loopback-test; + status = "disabled"; + }; + + uart8: serial@14c33700 { + compatible = "ns16550a"; + reg = <0x0 0x14c33700 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART8CLK>; + interrupts-extended = <&intc1 142>; + no-loopback-test; + status = "disabled"; + }; + + uart9: serial@14c33800 { + compatible = "ns16550a"; + reg = <0x0 0x14c33800 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART9CLK>; + interrupts-extended = <&intc1 143>; + no-loopback-test; + status = "disabled"; + }; + + uart10: serial@14c33900 { + compatible = "ns16550a"; + reg = <0x0 0x14c33900 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART10CLK>; + interrupts-extended = <&intc1 144>; + no-loopback-test; + status = "disabled"; + }; + + uart11: serial@14c33a00 { + compatible = "ns16550a"; + reg = <0x0 0x14c33a00 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART11CLK>; + interrupts-extended = <&intc1 145>; + no-loopback-test; + status = "disabled"; + }; + + uart12: serial@14c33b00 { + compatible = "ns16550a"; + reg = <0x0 0x14c33b00 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART12CLK>; + interrupts-extended = <&intc1 146>; + no-loopback-test; + status = "disabled"; + }; + + uart13: serial@14c33c00 { + compatible = "ns16550a"; + reg = <0x0 0x14c33c00 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_UART13>; + interrupts-extended = <&intc1 23>; + no-loopback-test; + status = "disabled"; + }; + + uart14: serial@14c33d00 { + compatible = "ns16550a"; + reg = <0x0 0x14c33d00 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_UART14>; + interrupts-extended = <&intc1 55>; + no-loopback-test; + status = "disabled"; + }; + + wdt0: watchdog@14c37000 { + compatible = "aspeed,ast2700-wdt"; + reg = <0x0 0x14c37000 0x0 0x80>; + }; + + wdt1: watchdog@14c37080 { + compatible = "aspeed,ast2700-wdt"; + reg = <0x0 0x14c37080 0x0 0x80>; + }; + + wdt2: watchdog@14c37100 { + compatible = "aspeed,ast2700-wdt"; + reg = <0x0 0x14c37100 0x0 0x80>; + status = "disabled"; + }; + + wdt3: watchdog@14c37180 { + compatible = "aspeed,ast2700-wdt"; + reg = <0x0 0x14c37180 0x0 0x80>; + status = "disabled"; + }; + + mbox2: mbox@14c39200 { + compatible = "aspeed,ast2700-mailbox"; + reg = <0x0 0x14c39200 0x0 0x100>, <0x0 0x14c39300 0x0 0x100>; + reg-names = "tx", "rx"; + interrupts-extended = <&intc1 177>; + #mbox-cells = <1>; + }; + + fsim0: fsi@21800000 { + compatible = "aspeed,ast2700-fsi-master"; + reg = <0x0 0x21800000 0x0 0x94>; + interrupts-extended = <&intc1 166>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fsi0_default>; + clocks = <&syscon1 SCU1_CLK_GATE_FSICLK>; + resets = <&syscon1 SCU1_RESET_FSI>; + status = "disabled"; + }; + + fsim1: fsi@23800000 { + compatible = "aspeed,ast2700-fsi-master"; + reg = <0x0 0x23800000 0x0 0x94>; + interrupts-extended = <&intc1 167>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fsi2_default>; + clocks = <&syscon1 SCU1_CLK_GATE_FSICLK>; + resets = <&syscon1 SCU1_RESET_FSI>; + status = "disabled"; + }; +}; + +#include "aspeed-g7-soc1-pinctrl.dtsi" diff --git a/arch/arm64/boot/dts/aspeed/ast2700-evb.dts b/arch/arm64/boot/dts/aspeed/ast2700-evb.dts new file mode 100644 index 000000000000..fe8f0b80fb2c --- /dev/null +++ b/arch/arm64/boot/dts/aspeed/ast2700-evb.dts @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree Source AST2700 EVB + * + * Copyright (C) 2026 ASPEED Technology Inc. + */ + +/dts-v1/; +#include "aspeed-g7-a35.dtsi" + +/ { + model = "AST2700 EVB"; + compatible = "aspeed,ast2700-evb", "aspeed,ast2700"; + + aliases { + serial0 = &uart12; /* console port */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@400000000 { + device_type = "memory"; + reg = <0x4 0x00000000 0x0 0x40000000>; + }; +}; + +&fmc { + status = "okay"; + pinctrl-0 = <&pinctrl_fwspi_quad_default>; + pinctrl-names = "default"; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; +#include "aspeed-evb-flash-layout-128.dtsi" + }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "fmc0:1"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + + flash@2 { + status = "disabled"; + m25p,fast-read; + label = "fmc0:2"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&uart12 { + status = "okay"; +}; From de8c602d5a2180c737e55dcd3dbcbf9dcc4af292 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Wed, 10 Jun 2026 13:45:23 +0200 Subject: [PATCH 661/665] arm64: dts: lx2160a-rev2: avoid 32-bit pcie window system ram overlap A 3GB non-prefetchable PCIe bus window can overlap with inbound DMA addresses for low system RAM, so DMA transactions may be routed to a BAR on the same host bridge instead of memory. Change the 32-bit non-prefetchable PCIe window back from 3GB to 1GB on all controllers, avoiding that overlap while keeping the added 64-bit prefetchable region. This partially reverts commit 9ed301397090 ("arm64: dts: lx2160a-rev2: extend 32-bit and add 64-bit pci regions"). Fixes: 9ed301397090 ("arm64: dts: lx2160a-rev2: extend 32-bit and add 64-bit pci regions") Reported-by: Arnd Bergmann Closes: https://lore.kernel.org/r/9e6326f6-dad1-4169-a63c-e62ee5b341f2@app.fastmail.com Signed-off-by: Josua Mayer Acked-by: Arnd Bergmann Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi index 3570399f9b21..3d2637fee2d3 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi @@ -17,7 +17,7 @@ &pcie1 { ranges = /* 16-Bit IO Window */ <0x81000000 0x00 0x00000000 0x80 0x00010000 0x00 0x00010000>, /* 32-Bit - non-prefetchable */ - <0x82000000 0x00 0x40000000 0x80 0x40000000 0x00 0xc0000000>, + <0x82000000 0x00 0x40000000 0x80 0x40000000 0x00 0x40000000>, /* 64-Bit - prefetchable - 16GB */ <0xC3000000 0x84 0x00000000 0x84 0x00000000 0x04 0x00000000>; @@ -37,7 +37,7 @@ &pcie2 { ranges = /* 16-Bit IO Window */ <0x81000000 0x00 0x00000000 0x88 0x00010000 0x00 0x00010000>, /* 32-Bit - non-prefetchable */ - <0x82000000 0x00 0x40000000 0x88 0x40000000 0x00 0xc0000000>, + <0x82000000 0x00 0x40000000 0x88 0x40000000 0x00 0x40000000>, /* 64-Bit - prefetchable - 16GB */ <0xC3000000 0x8c 0x00000000 0x8c 0x00000000 0x04 0x00000000>; @@ -57,7 +57,7 @@ &pcie3 { ranges = /* 16-Bit IO Window */ <0x81000000 0x00 0x00000000 0x90 0x00010000 0x00 0x00010000>, /* 32-Bit - non-prefetchable */ - <0x82000000 0x00 0x40000000 0x90 0x40000000 0x00 0xc0000000>, + <0x82000000 0x00 0x40000000 0x90 0x40000000 0x00 0x40000000>, /* 64-Bit - prefetchable - 16GB */ <0xC3000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; @@ -78,7 +78,7 @@ &pcie4 { ranges = /* 16-Bit IO Window */ <0x81000000 0x00 0x00000000 0x98 0x00010000 0x00 0x00010000>, /* 32-Bit - non-prefetchable */ - <0x82000000 0x00 0x40000000 0x98 0x40000000 0x00 0xc0000000>, + <0x82000000 0x00 0x40000000 0x98 0x40000000 0x00 0x40000000>, /* 64-Bit - prefetchable - 16GB */ <0xC3000000 0x9c 0x00000000 0x9c 0x00000000 0x04 0x00000000>; @@ -98,7 +98,7 @@ &pcie5 { ranges = /* 16-Bit IO Window */ <0x81000000 0x00 0x00000000 0xa0 0x00010000 0x00 0x00010000>, /* 32-Bit - non-prefetchable */ - <0x82000000 0x00 0x40000000 0xa0 0x40000000 0x00 0xc0000000>, + <0x82000000 0x00 0x40000000 0xa0 0x40000000 0x00 0x40000000>, /* 64-Bit - prefetchable - 16GB */ <0xC3000000 0xa4 0x00000000 0xa4 0x00000000 0x04 0x00000000>; @@ -118,7 +118,7 @@ &pcie6 { ranges = /* 16-Bit IO Window */ <0x81000000 0x00 0x00000000 0xa8 0x00010000 0x00 0x00010000>, /* 32-Bit - non-prefetchable */ - <0x82000000 0x00 0x40000000 0xa8 0x40000000 0x00 0xc0000000>, + <0x82000000 0x00 0x40000000 0xa8 0x40000000 0x00 0x40000000>, /* 64-Bit - prefetchable - 16GB */ <0xC3000000 0xac 0x00000000 0xac 0x00000000 0x04 0x00000000>; From 6b81aa0c8a4f038712fa549e4d44d8279eeb0440 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 27 Mar 2026 11:30:06 +0000 Subject: [PATCH 662/665] arm64: dts: allwinner: a523: Add missing GPIO interrupt Even though the Allwinner A523 SoC implements 10 GPIO banks, it has actually registers for 11 IRQ banks, and even an interrupt assigned to the first, non-implemented IRQ bank. Add that first interrupt to the list of GPIO interrupts, to correct the association between IRQs and GPIO banks. This fixes GPIO IRQ operation on boards with A523 SoCs, as seen by broken SD card detect functionality, for instance. Signed-off-by: Andre Przywara Fixes: 35ac96f79664 ("arm64: dts: allwinner: Add Allwinner A523 .dtsi file") Reviewed-by: Chen-Yu Tsai Reviewed-by: Jernej Skrabec Link: https://patch.msgid.link/20260327113006.3135663-4-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi index 321a03da77da..ca6a16807049 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -129,7 +129,8 @@ gpu: gpu@1800000 { pio: pinctrl@2000000 { compatible = "allwinner,sun55i-a523-pinctrl"; reg = <0x2000000 0x800>; - interrupts = , + interrupts = , + , , , , From 88c0120853e96b66d57eff33e06409f49457eec5 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 5 Mar 2026 13:06:29 -0500 Subject: [PATCH 663/665] dt-bindings: display/lvds-codec: add ti,sn65lvds93 Add compatible string for TI SN65LVDS93. Similar to SN65LVDS83 but with an industrial temperature range. Acked-by: Krzysztof Kozlowski Signed-off-by: Hugo Villeneuve Acked-by: Conor Dooley Signed-off-by: Frank Li --- Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml b/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml index 7586d681bcc6..8270772c09a3 100644 --- a/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml +++ b/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml @@ -38,6 +38,7 @@ properties: - ti,ds90c185 # For the TI DS90C185 FPD-Link Serializer - ti,ds90c187 # For the TI DS90C187 FPD-Link Serializer - ti,sn75lvds83 # For the TI SN75LVDS83 FlatLink transmitter + - ti,sn75lvds93 # For the TI SN75LVDS93 FlatLink transmitter - const: lvds-encoder # Generic LVDS encoder compatible fallback - items: - enum: From 6191a61ec9d9d8f1d1d1d6bfcb6d303be76c2804 Mon Sep 17 00:00:00 2001 From: Albert Yang Date: Fri, 12 Jun 2026 08:40:23 +0800 Subject: [PATCH 664/665] arm64: dts: bst: enable eMMC controller in C1200 Add mmc0 node for the DWCMSHC SDHCI controller with basic configuration (disabled by default) and fixed clock definition in bstc1200.dtsi. Enable mmc0 with board-specific configuration including 8-bit bus width and reserved SRAM bounce buffer on the CDCU1.0 ADAS 4C2G board. The bounce buffer in reserved SRAM addresses hardware constraints where the eMMC controller cannot access main system memory through SMMU due to a hardware bug, and all DRAM is located outside the 4GB boundary. Signed-off-by: Albert Yang Acked-by: Gordon Ge Signed-off-by: Gordon Ge --- .../dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts | 19 +++++++++++++++++++ arch/arm64/boot/dts/bst/bstc1200.dtsi | 18 ++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts b/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts index 5eb9ef369d8c..178ad4bf4f0a 100644 --- a/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts +++ b/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts @@ -17,6 +17,25 @@ memory@810000000 { <0x8 0xc0000000 0x1 0x0>, <0xc 0x00000000 0x0 0x40000000>; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mmc0_reserved: mmc0-reserved@5160000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x5160000 0x0 0x10000>; + no-map; + }; + }; +}; + +&mmc0 { + bus-width = <8>; + memory-region = <&mmc0_reserved>; + non-removable; + status = "okay"; }; &uart0 { diff --git a/arch/arm64/boot/dts/bst/bstc1200.dtsi b/arch/arm64/boot/dts/bst/bstc1200.dtsi index dd13c6bfc3c8..9660d8396e27 100644 --- a/arch/arm64/boot/dts/bst/bstc1200.dtsi +++ b/arch/arm64/boot/dts/bst/bstc1200.dtsi @@ -7,6 +7,12 @@ / { #address-cells = <2>; #size-cells = <2>; + clk_mmc: clock-4000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <4000000>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -72,6 +78,18 @@ uart0: serial@20008000 { status = "disabled"; }; + mmc0: mmc@22200000 { + compatible = "bst,c1200-sdhci"; + reg = <0x0 0x22200000 0x0 0x1000>, + <0x0 0x23006000 0x0 0x1000>; + clocks = <&clk_mmc>; + clock-names = "core"; + dma-coherent; + interrupts = ; + max-frequency = <200000000>; + status = "disabled"; + }; + gic: interrupt-controller@32800000 { compatible = "arm,gic-v3"; reg = <0x0 0x32800000 0x0 0x10000>, From 9e84fd546dc3f9f97bfbf2717c2d71d878a4f46f Mon Sep 17 00:00:00 2001 From: Ryan Chen Date: Fri, 12 Jun 2026 18:03:27 +0930 Subject: [PATCH 665/665] arm64: dts: aspeed: Fix duplicate pinctrl labels and address scheme A report from shashiko-bot highlighted some concerns concurrent to application of the series[1]. Fix duplicate pinctrl_tach{0-15} and pinctrl_n{cts,dcd,dsr,ri}5 labels in aspeed-g7-soc1-pinctrl.dtsi. These didn't cause errors from dtc because dtc accepts duplicate labels for duplicate nodes specified through a node reference[2]. Drop the cpu-index from secondary/tertiary container nodes: reduce the "#address-cells" from 2 to 1 and update unit-addresses and reg accordingly. The 2-cell scheme was proposed in an early mailing list sketch to prompt discussion[3], but the design evolved in ways that made it unnecessary. Also remove URL comments from the DTS. The links were to comments in the kernel sources with discussion justifying the approach, but are not necessary to carry forward. [arj: Extend discussion in the commit message] Link: https://lore.kernel.org/all/20260609025708.ADBFE1F00893@smtp.kernel.org/ [1] Link: https://lore.kernel.org/all/b226339bb2abe42ce23e90eadbc654b426131083.camel@codeconstruct.com.au/ [2] Link: https://lore.kernel.org/all/1a2ca78746e00c2ec4bfc2953a897c48376ed36f.camel@codeconstruct.com.au/ [3] Suggested-by: Andrew Jeffery Fixes: e77bb5dc5759 ("arm64: dts: aspeed: Add initial AST27xx SoC device tree") Signed-off-by: Ryan Chen Link: https://patch.msgid.link/20260611-dtsi_fix-v1-1-ef2b7cd86d6d@aspeedtech.com Signed-off-by: Andrew Jeffery Link: https://lore.kernel.org/r/20260612-aspeed-arm64-dt-v1-1-d1d1a4737905@codeconstruct.com.au Signed-off-by: Arnd Bergmann --- arch/arm64/boot/dts/aspeed/aspeed-g7-a35.dtsi | 14 ++- .../dts/aspeed/aspeed-g7-soc1-pinctrl.dtsi | 102 ------------------ 2 files changed, 6 insertions(+), 110 deletions(-) diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7-a35.dtsi b/arch/arm64/boot/dts/aspeed/aspeed-g7-a35.dtsi index ef283d95649a..58193c3c3696 100644 --- a/arch/arm64/boot/dts/aspeed/aspeed-g7-a35.dtsi +++ b/arch/arm64/boot/dts/aspeed/aspeed-g7-a35.dtsi @@ -84,32 +84,30 @@ l2: l2-cache0 { }; secondary { - #address-cells = <2>; - /* https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/of/address.c?h=v6.16#n491 */ + #address-cells = <1>; #size-cells = <0>; - /* https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/of/address.c?h=v6.16#n430 */ - ssp_nvic: interrupt-controller@1,e000e100 { + ssp_nvic: interrupt-controller@e000e100 { compatible = "arm,v7m-nvic"; #interrupt-cells = <2>; #address-cells = <0>; interrupt-controller; - reg = <1 0xe000e100>; + reg = <0xe000e100>; arm,num-irq-priority-bits = <3>; status = "disabled"; }; }; tertiary { - #address-cells = <2>; + #address-cells = <1>; #size-cells = <0>; - tsp_nvic: interrupt-controller@2,e000e100 { + tsp_nvic: interrupt-controller@e000e100 { compatible = "arm,v7m-nvic"; #interrupt-cells = <2>; #address-cells = <0>; interrupt-controller; - reg = <2 0xe000e100>; + reg = <0xe000e100>; arm,num-irq-priority-bits = <3>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7-soc1-pinctrl.dtsi b/arch/arm64/boot/dts/aspeed/aspeed-g7-soc1-pinctrl.dtsi index 72d93323593d..6edf14617b09 100644 --- a/arch/arm64/boot/dts/aspeed/aspeed-g7-soc1-pinctrl.dtsi +++ b/arch/arm64/boot/dts/aspeed/aspeed-g7-soc1-pinctrl.dtsi @@ -496,87 +496,6 @@ pinctrl_hvi3c15_default: hvi3c15-default-state { function = "I3C15"; groups = "HVI3C15"; }; - - pinctrl_tach0_default: tach0-default-state { - function = "TACH0"; - groups = "TACH0"; - }; - - pinctrl_tach1_default: tach1-default-state { - function = "TACH1"; - groups = "TACH1"; - }; - - pinctrl_tach2_default: tach2-default-state { - function = "TACH2"; - groups = "TACH2"; - }; - - pinctrl_tach3_default: tach3-default-state { - function = "TACH3"; - groups = "TACH3"; - }; - - pinctrl_tach4_default: tach4-default-state { - function = "TACH4"; - groups = "TACH4"; - }; - - pinctrl_tach5_default: tach5-default-state { - function = "TACH5"; - groups = "TACH5"; - }; - - pinctrl_tach6_default: tach6-default-state { - function = "TACH6"; - groups = "TACH6"; - }; - - pinctrl_tach7_default: tach7-default-state { - function = "TACH7"; - groups = "TACH7"; - }; - - pinctrl_tach8_default: tach8-default-state { - function = "TACH8"; - groups = "TACH8"; - }; - - pinctrl_tach9_default: tach9-default-state { - function = "TACH9"; - groups = "TACH9"; - }; - - pinctrl_tach10_default: tach10-default-state { - function = "TACH10"; - groups = "TACH10"; - }; - - pinctrl_tach11_default: tach11-default-state { - function = "TACH11"; - groups = "TACH11"; - }; - - pinctrl_tach12_default: tach12-default-state { - function = "TACH12"; - groups = "TACH12"; - }; - - pinctrl_tach13_default: tach13-default-state { - function = "TACH13"; - groups = "TACH13"; - }; - - pinctrl_tach14_default: tach14-default-state { - function = "TACH14"; - groups = "TACH14"; - }; - - pinctrl_tach15_default: tach15-default-state { - function = "TACH15"; - groups = "TACH15"; - }; - pinctrl_thru0_default: thru0-default-state { function = "THRU0"; groups = "THRU0"; @@ -940,27 +859,6 @@ pinctrl_uart3_default: uart3-default-state { function = "UART3"; groups = "UART3"; }; - - pinctrl_ncts5_default: ncts5-default-state { - function = "NCTS5"; - groups = "NCTS5"; - }; - - pinctrl_ndcd5_default: ndcd5-default-state { - function = "NDCD5"; - groups = "NDCD5"; - }; - - pinctrl_ndsr5_default: ndsr5-default-state { - function = "NDSR5"; - groups = "NDSR5"; - }; - - pinctrl_nri5_default: nri5-default-state { - function = "NRI5"; - groups = "NRI5"; - }; - pinctrl_ndtr5_default: ndtr5-default-state { function = "NDTR5"; groups = "NDTR5";