From 6c0dceaae604cff7b54c9a90409b28990645c103 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 17 Oct 2016 00:42:43 +0900 Subject: [PATCH 1/7] ARM: dts: uniphier: increase register region size of sysctrl node The System Control node has 0x10000 byte of registers. The current reg size must be expanded to use the cpufreq driver because the registers controlling CPU frequency are located at offset 0x8000. Signed-off-by: Masahiro Yamada --- arch/arm/boot/dts/uniphier-common32.dtsi | 2 +- arch/arm/boot/dts/uniphier-sld3.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/uniphier-common32.dtsi b/arch/arm/boot/dts/uniphier-common32.dtsi index 8c8a85176b64..d067f38fa21d 100644 --- a/arch/arm/boot/dts/uniphier-common32.dtsi +++ b/arch/arm/boot/dts/uniphier-common32.dtsi @@ -183,7 +183,7 @@ pinctrl: pinctrl { sysctrl@61840000 { compatible = "socionext,uniphier-sysctrl", "simple-mfd", "syscon"; - reg = <0x61840000 0x4000>; + reg = <0x61840000 0x10000>; sys_clk: clock { #clock-cells = <1>; diff --git a/arch/arm/boot/dts/uniphier-sld3.dtsi b/arch/arm/boot/dts/uniphier-sld3.dtsi index 5fa96c939b5c..35c18197d94f 100644 --- a/arch/arm/boot/dts/uniphier-sld3.dtsi +++ b/arch/arm/boot/dts/uniphier-sld3.dtsi @@ -271,7 +271,7 @@ usb3: usb@5a830100 { sysctrl@f1840000 { compatible = "socionext,uniphier-sysctrl", "simple-mfd", "syscon"; - reg = <0xf1840000 0x4000>; + reg = <0xf1840000 0x10000>; sys_clk: clock { compatible = "socionext,uniphier-sld3-clock"; From 35167e27f2b7f50538dfb81f144ccb8dd89adcac Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 27 Oct 2016 01:37:38 +0900 Subject: [PATCH 2/7] ARM: dts: uniphier: add CPU clocks and OPP table for Pro5 SoC Add a CPU clock to every CPU node and a CPU OPP table to use the generic cpufreq driver. Signed-off-by: Masahiro Yamada Acked-by: Viresh Kumar --- arch/arm/boot/dts/uniphier-pro5.dtsi | 74 ++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi index 5357ea9c14b1..5bd6068ac14b 100644 --- a/arch/arm/boot/dts/uniphier-pro5.dtsi +++ b/arch/arm/boot/dts/uniphier-pro5.dtsi @@ -56,16 +56,90 @@ cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + clocks = <&sys_clk 32>; enable-method = "psci"; next-level-cache = <&l2>; + operating-points-v2 = <&cpu_opp>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + clocks = <&sys_clk 32>; enable-method = "psci"; next-level-cache = <&l2>; + operating-points-v2 = <&cpu_opp>; + }; + }; + + cpu_opp: opp_table { + compatible = "operating-points-v2"; + opp-shared; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + clock-latency-ns = <300>; + }; + opp@116667000 { + opp-hz = /bits/ 64 <116667000>; + clock-latency-ns = <300>; + }; + opp@150000000 { + opp-hz = /bits/ 64 <150000000>; + clock-latency-ns = <300>; + }; + opp@175000000 { + opp-hz = /bits/ 64 <175000000>; + clock-latency-ns = <300>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + clock-latency-ns = <300>; + }; + opp@233334000 { + opp-hz = /bits/ 64 <233334000>; + clock-latency-ns = <300>; + }; + opp@300000000 { + opp-hz = /bits/ 64 <300000000>; + clock-latency-ns = <300>; + }; + opp@350000000 { + opp-hz = /bits/ 64 <350000000>; + clock-latency-ns = <300>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + clock-latency-ns = <300>; + }; + opp@466667000 { + opp-hz = /bits/ 64 <466667000>; + clock-latency-ns = <300>; + }; + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + clock-latency-ns = <300>; + }; + opp@700000000 { + opp-hz = /bits/ 64 <700000000>; + clock-latency-ns = <300>; + }; + opp@800000000 { + opp-hz = /bits/ 64 <800000000>; + clock-latency-ns = <300>; + }; + opp@933334000 { + opp-hz = /bits/ 64 <933334000>; + clock-latency-ns = <300>; + }; + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + clock-latency-ns = <300>; + }; + opp@1400000000 { + opp-hz = /bits/ 64 <1400000000>; + clock-latency-ns = <300>; }; }; From 7a8a6588219dba5b47ebd4fa74ec2c1d81f0ee9f Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 27 Oct 2016 01:37:39 +0900 Subject: [PATCH 3/7] ARM: dts: uniphier: add CPU clocks and OPP table for PXs2 SoC Add a CPU clock to every CPU node and a CPU OPP table to use the generic cpufreq driver. Signed-off-by: Masahiro Yamada Acked-by: Viresh Kumar --- arch/arm/boot/dts/uniphier-pxs2.dtsi | 46 ++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi index 950f07ba0337..83ba3e60b4bd 100644 --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi @@ -56,32 +56,78 @@ cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + clocks = <&sys_clk 32>; enable-method = "psci"; next-level-cache = <&l2>; + operating-points-v2 = <&cpu_opp>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + clocks = <&sys_clk 32>; enable-method = "psci"; next-level-cache = <&l2>; + operating-points-v2 = <&cpu_opp>; }; cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <2>; + clocks = <&sys_clk 32>; enable-method = "psci"; next-level-cache = <&l2>; + operating-points-v2 = <&cpu_opp>; }; cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <3>; + clocks = <&sys_clk 32>; enable-method = "psci"; next-level-cache = <&l2>; + operating-points-v2 = <&cpu_opp>; + }; + }; + + cpu_opp: opp_table { + compatible = "operating-points-v2"; + opp-shared; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + clock-latency-ns = <300>; + }; + opp@150000000 { + opp-hz = /bits/ 64 <150000000>; + clock-latency-ns = <300>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + clock-latency-ns = <300>; + }; + opp@300000000 { + opp-hz = /bits/ 64 <300000000>; + clock-latency-ns = <300>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + clock-latency-ns = <300>; + }; + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + clock-latency-ns = <300>; + }; + opp@800000000 { + opp-hz = /bits/ 64 <800000000>; + clock-latency-ns = <300>; + }; + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + clock-latency-ns = <300>; }; }; From 2752bcaa1a9495573ed799c208309a8fba135f3d Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 31 Oct 2016 16:29:24 +0900 Subject: [PATCH 4/7] ARM: dts: uniphier: make 32bit SoC DTSI linear I notice some mistakes in the SoC DTSI; wrong interrupts properties of timer nodes, mismatch between the node name and the compatible for sdctrl block. Given those problems fixed, the common parts among SoCs are less than I had first expected. The more and more property overrides are making the SoC DTSI unreadable. Stretch out the SoC DTSI files and fix the following: - Fix the 3rd cell of the interrupts property of the timer nodes for Pro4, Pro5, PXs2 - Fix the node name mioctrl to sdctrl for Pro5, PXs2 - Fix the second region of l2 node for PXs2 Signed-off-by: Masahiro Yamada --- arch/arm/boot/dts/uniphier-common32.dtsi | 199 ------------ arch/arm/boot/dts/uniphier-ld4.dtsi | 386 ++++++++++++++-------- arch/arm/boot/dts/uniphier-pro4.dtsi | 390 +++++++++++++++-------- arch/arm/boot/dts/uniphier-pro5.dtsi | 372 ++++++++++++++------- arch/arm/boot/dts/uniphier-pxs2.dtsi | 365 ++++++++++++++------- arch/arm/boot/dts/uniphier-sld8.dtsi | 373 ++++++++++++++-------- 6 files changed, 1249 insertions(+), 836 deletions(-) delete mode 100644 arch/arm/boot/dts/uniphier-common32.dtsi diff --git a/arch/arm/boot/dts/uniphier-common32.dtsi b/arch/arm/boot/dts/uniphier-common32.dtsi deleted file mode 100644 index d067f38fa21d..000000000000 --- a/arch/arm/boot/dts/uniphier-common32.dtsi +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Device Tree Source commonly used by UniPhier ARM SoCs - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/include/ "skeleton.dtsi" - -/ { - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - clocks { - refclk: ref { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&intc>; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - interrupts = <0 33 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&peri_clk 0>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - interrupts = <0 35 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&peri_clk 1>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - clocks = <&peri_clk 2>; - }; - - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - interrupts = <0 177 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - clocks = <&peri_clk 3>; - }; - - system_bus: system-bus@58c00000 { - compatible = "socionext,uniphier-system-bus"; - status = "disabled"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_system_bus>; - }; - - smpctrl@59800000 { - compatible = "socionext,uniphier-smpctrl"; - reg = <0x59801000 0x400>; - }; - - mioctrl@59810000 { - compatible = "socionext,uniphier-mioctrl", - "simple-mfd", "syscon"; - reg = <0x59810000 0x800>; - - mio_clk: clock { - #clock-cells = <1>; - }; - - mio_rst: reset { - #reset-cells = <1>; - }; - }; - - perictrl@59820000 { - compatible = "socionext,uniphier-perictrl", - "simple-mfd", "syscon"; - reg = <0x59820000 0x200>; - - peri_clk: clock { - #clock-cells = <1>; - }; - - peri_rst: reset { - #reset-cells = <1>; - }; - }; - - timer@60000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x60000200 0x20>; - interrupts = <1 11 0x104>; - clocks = <&arm_timer_clk>; - }; - - timer@60000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x60000600 0x20>; - interrupts = <1 13 0x104>; - clocks = <&arm_timer_clk>; - }; - - intc: interrupt-controller@60001000 { - compatible = "arm,cortex-a9-gic"; - reg = <0x60001000 0x1000>, - <0x60000100 0x100>; - #interrupt-cells = <3>; - interrupt-controller; - }; - - soc-glue@5f800000 { - compatible = "socionext,uniphier-soc-glue", - "simple-mfd", "syscon"; - reg = <0x5f800000 0x2000>; - - pinctrl: pinctrl { - /* specify compatible in each SoC DTSI */ - }; - }; - - sysctrl@61840000 { - compatible = "socionext,uniphier-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x10000>; - - sys_clk: clock { - #clock-cells = <1>; - }; - - sys_rst: reset { - #reset-cells = <1>; - }; - }; - }; -}; - -/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi index 95f342c9d9c1..a7c494d7c43a 100644 --- a/arch/arm/boot/dts/uniphier-ld4.dtsi +++ b/arch/arm/boot/dts/uniphier-ld4.dtsi @@ -43,7 +43,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -/include/ "uniphier-common32.dtsi" +/include/ "skeleton.dtsi" / { compatible = "socionext,uniphier-ld4"; @@ -61,147 +61,267 @@ cpu@0 { }; }; + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + clocks { + refclk: ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + arm_timer_clk: arm_timer_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <50000000>; }; }; -}; -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(512 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - - i2c0: i2c@58400000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58400000 0x40>; + soc { + compatible = "simple-bus"; #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - clock-frequency = <100000>; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; + + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, + <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(512 * 1024)>; + cache-sets = <256>; + cache-line-size = <128>; + cache-level = <2>; + }; + + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + interrupts = <0 33 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&peri_clk 0>; + }; + + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + interrupts = <0 35 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&peri_clk 1>; + }; + + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + interrupts = <0 37 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + clocks = <&peri_clk 2>; + }; + + serial3: serial@54006b00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x40>; + interrupts = <0 29 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + clocks = <&peri_clk 3>; + }; + + i2c0: i2c@58400000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58400000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&peri_clk 4>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58480000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58480000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&peri_clk 5>; + clock-frequency = <100000>; + }; + + /* chip-internal connection for DMD */ + i2c2: i2c@58500000 { + compatible = "socionext,uniphier-i2c"; + reg = <0x58500000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&peri_clk 6>; + clock-frequency = <400000>; + }; + + i2c3: i2c@58580000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58580000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&peri_clk 7>; + clock-frequency = <100000>; + }; + + system_bus: system-bus@58c00000 { + compatible = "socionext,uniphier-system-bus"; + status = "disabled"; + reg = <0x58c00000 0x400>; + #address-cells = <2>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_system_bus>; + }; + + smpctrl@59800000 { + compatible = "socionext,uniphier-smpctrl"; + reg = <0x59801000 0x400>; + }; + + mioctrl@59810000 { + compatible = "socionext,uniphier-ld4-mioctrl", + "simple-mfd", "syscon"; + reg = <0x59810000 0x800>; + + mio_clk: clock { + compatible = "socionext,uniphier-ld4-mio-clock"; + #clock-cells = <1>; + }; + + mio_rst: reset { + compatible = "socionext,uniphier-ld4-mio-reset"; + #reset-cells = <1>; + }; + }; + + perictrl@59820000 { + compatible = "socionext,uniphier-ld4-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + peri_clk: clock { + compatible = "socionext,uniphier-ld4-peri-clock"; + #clock-cells = <1>; + }; + + peri_rst: reset { + compatible = "socionext,uniphier-ld4-peri-reset"; + #reset-cells = <1>; + }; + }; + + usb0: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + interrupts = <0 80 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, + <&mio_rst 12>; + }; + + usb1: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + interrupts = <0 81 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, + <&mio_rst 13>; + }; + + usb2: usb@5a820100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a820100 0x100>; + interrupts = <0 82 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, + <&mio_rst 14>; + }; + + soc-glue@5f800000 { + compatible = "socionext,uniphier-ld4-soc-glue", + "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-ld4-pinctrl"; + }; + }; + + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; + interrupts = <1 11 0x104>; + clocks = <&arm_timer_clk>; + }; + + timer@60000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x60000600 0x20>; + interrupts = <1 13 0x104>; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@60001000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x60001000 0x1000>, + <0x60000100 0x100>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + sysctrl@61840000 { + compatible = "socionext,uniphier-ld4-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x10000>; + + sys_clk: clock { + compatible = "socionext,uniphier-ld4-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset { + compatible = "socionext,uniphier-ld4-reset"; + #reset-cells = <1>; + }; + }; }; - - i2c1: i2c@58480000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58480000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - clock-frequency = <100000>; - }; - - /* chip-internal connection for DMD */ - i2c2: i2c@58500000 { - compatible = "socionext,uniphier-i2c"; - reg = <0x58500000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&peri_clk 6>; - clock-frequency = <400000>; - }; - - i2c3: i2c@58580000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58580000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - clock-frequency = <100000>; - }; - - usb0: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; - resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>; - }; - - usb1: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; - resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>; - }; - - usb2: usb@5a820100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a820100 0x100>; - interrupts = <0 82 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; - resets = <&mio_rst 7>, <&mio_rst 10>, <&mio_rst 14>, <&sys_rst 8>; - }; - }; -&refclk { - clock-frequency = <24576000>; -}; - -&serial3 { - interrupts = <0 29 4>; -}; - -&mio_clk { - compatible = "socionext,uniphier-ld4-mio-clock"; -}; - -&mio_rst { - compatible = "socionext,uniphier-ld4-mio-reset"; - resets = <&sys_rst 7>; -}; - -&peri_clk { - compatible = "socionext,uniphier-ld4-peri-clock"; -}; - -&peri_rst { - compatible = "socionext,uniphier-ld4-peri-reset"; -}; - -&pinctrl { - compatible = "socionext,uniphier-ld4-pinctrl"; -}; - -&sys_clk { - compatible = "socionext,uniphier-ld4-clock"; -}; - -&sys_rst { - compatible = "socionext,uniphier-ld4-reset"; -}; +/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi index ba700267ad66..e960b09ff01c 100644 --- a/arch/arm/boot/dts/uniphier-pro4.dtsi +++ b/arch/arm/boot/dts/uniphier-pro4.dtsi @@ -43,7 +43,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -/include/ "uniphier-common32.dtsi" +/include/ "skeleton.dtsi" / { compatible = "socionext,uniphier-pro4"; @@ -69,155 +69,279 @@ cpu@1 { }; }; + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + clocks { + refclk: ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + arm_timer_clk: arm_timer_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <50000000>; }; }; -}; -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(768 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; + soc { + compatible = "simple-bus"; #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - clock-frequency = <100000>; - }; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - clock-frequency = <100000>; - }; + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, + <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(768 * 1024)>; + cache-sets = <256>; + cache-line-size = <128>; + cache-level = <2>; + }; - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&peri_clk 6>; - clock-frequency = <100000>; - }; + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + interrupts = <0 33 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&peri_clk 0>; + }; - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - clock-frequency = <100000>; - }; + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + interrupts = <0 35 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&peri_clk 1>; + }; - /* i2c4 does not exist */ + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + interrupts = <0 37 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + clocks = <&peri_clk 2>; + }; - /* chip-internal connection for DMD */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&peri_clk 9>; - clock-frequency = <400000>; - }; + serial3: serial@54006b00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x40>; + interrupts = <0 177 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + clocks = <&peri_clk 3>; + }; - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&peri_clk 10>; - clock-frequency = <400000>; - }; + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&peri_clk 4>; + clock-frequency = <100000>; + }; - usb2: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; - resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>; - }; + i2c1: i2c@58781000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&peri_clk 5>; + clock-frequency = <100000>; + }; - usb3: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb3>; - clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; - resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>; + i2c2: i2c@58782000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58782000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&peri_clk 6>; + clock-frequency = <100000>; + }; + + i2c3: i2c@58783000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&peri_clk 7>; + clock-frequency = <100000>; + }; + + /* i2c4 does not exist */ + + /* chip-internal connection for DMD */ + i2c5: i2c@58785000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 25 4>; + clocks = <&peri_clk 9>; + clock-frequency = <400000>; + }; + + /* chip-internal connection for HDMI */ + i2c6: i2c@58786000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58786000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 26 4>; + clocks = <&peri_clk 10>; + clock-frequency = <400000>; + }; + + system_bus: system-bus@58c00000 { + compatible = "socionext,uniphier-system-bus"; + status = "disabled"; + reg = <0x58c00000 0x400>; + #address-cells = <2>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_system_bus>; + }; + + smpctrl@59800000 { + compatible = "socionext,uniphier-smpctrl"; + reg = <0x59801000 0x400>; + }; + + mioctrl@59810000 { + compatible = "socionext,uniphier-pro4-mioctrl", + "simple-mfd", "syscon"; + reg = <0x59810000 0x800>; + + mio_clk: clock { + compatible = "socionext,uniphier-pro4-mio-clock"; + #clock-cells = <1>; + }; + + mio_rst: reset { + compatible = "socionext,uniphier-pro4-mio-reset"; + #reset-cells = <1>; + }; + }; + + perictrl@59820000 { + compatible = "socionext,uniphier-pro4-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + peri_clk: clock { + compatible = "socionext,uniphier-pro4-peri-clock"; + #clock-cells = <1>; + }; + + peri_rst: reset { + compatible = "socionext,uniphier-pro4-peri-reset"; + #reset-cells = <1>; + }; + }; + + usb2: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + interrupts = <0 80 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, + <&mio_rst 12>; + }; + + usb3: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + interrupts = <0 81 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3>; + clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, + <&mio_rst 13>; + }; + + soc-glue@5f800000 { + compatible = "socionext,uniphier-pro4-soc-glue", + "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-pro4-pinctrl"; + }; + }; + + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; + interrupts = <1 11 0x304>; + clocks = <&arm_timer_clk>; + }; + + timer@60000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x60000600 0x20>; + interrupts = <1 13 0x304>; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@60001000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x60001000 0x1000>, + <0x60000100 0x100>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + sysctrl@61840000 { + compatible = "socionext,uniphier-pro4-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x10000>; + + sys_clk: clock { + compatible = "socionext,uniphier-pro4-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset { + compatible = "socionext,uniphier-pro4-reset"; + #reset-cells = <1>; + }; + }; }; }; -&refclk { - clock-frequency = <25000000>; -}; - -&mio_clk { - compatible = "socionext,uniphier-pro4-mio-clock"; -}; - -&mio_rst { - compatible = "socionext,uniphier-pro4-mio-reset"; - resets = <&sys_rst 7>; -}; - -&peri_clk { - compatible = "socionext,uniphier-pro4-peri-clock"; -}; - -&peri_rst { - compatible = "socionext,uniphier-pro4-peri-reset"; -}; - -&pinctrl { - compatible = "socionext,uniphier-pro4-pinctrl"; -}; - -&sys_clk { - compatible = "socionext,uniphier-pro4-clock"; -}; - -&sys_rst { - compatible = "socionext,uniphier-pro4-reset"; -}; +/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi index 5bd6068ac14b..dbc5e5333163 100644 --- a/arch/arm/boot/dts/uniphier-pro5.dtsi +++ b/arch/arm/boot/dts/uniphier-pro5.dtsi @@ -43,7 +43,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -/include/ "uniphier-common32.dtsi" +/include/ "skeleton.dtsi" / { compatible = "socionext,uniphier-pro5"; @@ -143,144 +143,268 @@ opp@1400000000 { }; }; + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + clocks { + refclk: ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + arm_timer_clk: arm_timer_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <50000000>; }; }; -}; -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>; - interrupts = <0 190 4>, <0 191 4>; - cache-unified; - cache-size = <(2 * 1024 * 1024)>; - cache-sets = <512>; - cache-line-size = <128>; - cache-level = <2>; - next-level-cache = <&l3>; - }; - - l3: l3-cache@500c8000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(2 * 1024 * 1024)>; - cache-sets = <512>; - cache-line-size = <256>; - cache-level = <3>; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; + soc { + compatible = "simple-bus"; #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - clock-frequency = <100000>; - }; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - clock-frequency = <100000>; - }; + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, + <0x506c0000 0x400>; + interrupts = <0 190 4>, <0 191 4>; + cache-unified; + cache-size = <(2 * 1024 * 1024)>; + cache-sets = <512>; + cache-line-size = <128>; + cache-level = <2>; + next-level-cache = <&l3>; + }; - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&peri_clk 6>; - clock-frequency = <100000>; - }; + l3: l3-cache@500c8000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, + <0x506c8000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(2 * 1024 * 1024)>; + cache-sets = <512>; + cache-line-size = <256>; + cache-level = <3>; + }; - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - clock-frequency = <100000>; - }; + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + interrupts = <0 33 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&peri_clk 0>; + }; - /* i2c4 does not exist */ + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + interrupts = <0 35 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&peri_clk 1>; + }; - /* chip-internal connection for DMD */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&peri_clk 9>; - clock-frequency = <400000>; - }; + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + interrupts = <0 37 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + clocks = <&peri_clk 2>; + }; - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&peri_clk 10>; - clock-frequency = <400000>; + serial3: serial@54006b00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x40>; + interrupts = <0 177 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + clocks = <&peri_clk 3>; + }; + + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&peri_clk 4>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58781000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&peri_clk 5>; + clock-frequency = <100000>; + }; + + i2c2: i2c@58782000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58782000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&peri_clk 6>; + clock-frequency = <100000>; + }; + + i2c3: i2c@58783000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&peri_clk 7>; + clock-frequency = <100000>; + }; + + /* i2c4 does not exist */ + + /* chip-internal connection for DMD */ + i2c5: i2c@58785000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 25 4>; + clocks = <&peri_clk 9>; + clock-frequency = <400000>; + }; + + /* chip-internal connection for HDMI */ + i2c6: i2c@58786000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58786000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 26 4>; + clocks = <&peri_clk 10>; + clock-frequency = <400000>; + }; + + system_bus: system-bus@58c00000 { + compatible = "socionext,uniphier-system-bus"; + status = "disabled"; + reg = <0x58c00000 0x400>; + #address-cells = <2>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_system_bus>; + }; + + smpctrl@59800000 { + compatible = "socionext,uniphier-smpctrl"; + reg = <0x59801000 0x400>; + }; + + sdctrl@59810000 { + compatible = "socionext,uniphier-pro5-sdctrl", + "simple-mfd", "syscon"; + reg = <0x59810000 0x800>; + + sd_clk: clock { + compatible = "socionext,uniphier-pro5-sd-clock"; + #clock-cells = <1>; + }; + + sd_rst: reset { + compatible = "socionext,uniphier-pro5-sd-reset"; + #reset-cells = <1>; + }; + }; + + perictrl@59820000 { + compatible = "socionext,uniphier-pro5-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + peri_clk: clock { + compatible = "socionext,uniphier-pro5-peri-clock"; + #clock-cells = <1>; + }; + + peri_rst: reset { + compatible = "socionext,uniphier-pro5-peri-reset"; + #reset-cells = <1>; + }; + }; + + soc-glue@5f800000 { + compatible = "socionext,uniphier-pro5-soc-glue", + "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-pro5-pinctrl"; + }; + }; + + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; + interrupts = <1 11 0x304>; + clocks = <&arm_timer_clk>; + }; + + timer@60000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x60000600 0x20>; + interrupts = <1 13 0x304>; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@60001000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x60001000 0x1000>, + <0x60000100 0x100>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + sysctrl@61840000 { + compatible = "socionext,uniphier-pro5-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x10000>; + + sys_clk: clock { + compatible = "socionext,uniphier-pro5-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset { + compatible = "socionext,uniphier-pro5-reset"; + #reset-cells = <1>; + }; + }; }; }; -&refclk { - clock-frequency = <20000000>; -}; - -&mio_clk { - compatible = "socionext,uniphier-pro5-sd-clock"; -}; - -&mio_rst { - compatible = "socionext,uniphier-pro5-sd-reset"; -}; - -&peri_clk { - compatible = "socionext,uniphier-pro5-peri-clock"; -}; - -&peri_rst { - compatible = "socionext,uniphier-pro5-peri-reset"; -}; - -&pinctrl { - compatible = "socionext,uniphier-pro5-pinctrl"; -}; - -&sys_clk { - compatible = "socionext,uniphier-pro5-clock"; -}; - -&sys_rst { - compatible = "socionext,uniphier-pro5-reset"; -}; +/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi index 83ba3e60b4bd..e9e031d63c1a 100644 --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi @@ -43,7 +43,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -/include/ "uniphier-common32.dtsi" +/include/ "skeleton.dtsi" / { compatible = "socionext,uniphier-pxs2"; @@ -131,141 +131,264 @@ opp@1200000000 { }; }; + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + clocks { + refclk: ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + arm_timer_clk: arm_timer_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <50000000>; }; }; -}; -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; - cache-unified; - cache-size = <(1280 * 1024)>; - cache-sets = <512>; - cache-line-size = <128>; - cache-level = <2>; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; + soc { + compatible = "simple-bus"; #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - clock-frequency = <100000>; - }; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - clock-frequency = <100000>; - }; + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, + <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; + cache-unified; + cache-size = <(1280 * 1024)>; + cache-sets = <512>; + cache-line-size = <128>; + cache-level = <2>; + }; - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - interrupts = <0 43 4>; - clocks = <&peri_clk 6>; - clock-frequency = <100000>; - }; + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + interrupts = <0 33 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&peri_clk 0>; + }; - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - clock-frequency = <100000>; - }; + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + interrupts = <0 35 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&peri_clk 1>; + }; - /* chip-internal connection for DMD */ - i2c4: i2c@58784000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58784000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 45 4>; - clocks = <&peri_clk 8>; - clock-frequency = <400000>; - }; + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + interrupts = <0 37 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + clocks = <&peri_clk 2>; + }; - /* chip-internal connection for STM */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&peri_clk 9>; - clock-frequency = <400000>; - }; + serial3: serial@54006b00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x40>; + interrupts = <0 177 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + clocks = <&peri_clk 3>; + }; - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&peri_clk 10>; - clock-frequency = <400000>; + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&peri_clk 4>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58781000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&peri_clk 5>; + clock-frequency = <100000>; + }; + + i2c2: i2c@58782000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58782000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&peri_clk 6>; + clock-frequency = <100000>; + }; + + i2c3: i2c@58783000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&peri_clk 7>; + clock-frequency = <100000>; + }; + + /* chip-internal connection for DMD */ + i2c4: i2c@58784000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58784000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 45 4>; + clocks = <&peri_clk 8>; + clock-frequency = <400000>; + }; + + /* chip-internal connection for STM */ + i2c5: i2c@58785000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 25 4>; + clocks = <&peri_clk 9>; + clock-frequency = <400000>; + }; + + /* chip-internal connection for HDMI */ + i2c6: i2c@58786000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58786000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 26 4>; + clocks = <&peri_clk 10>; + clock-frequency = <400000>; + }; + + system_bus: system-bus@58c00000 { + compatible = "socionext,uniphier-system-bus"; + status = "disabled"; + reg = <0x58c00000 0x400>; + #address-cells = <2>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_system_bus>; + }; + + smpctrl@59800000 { + compatible = "socionext,uniphier-smpctrl"; + reg = <0x59801000 0x400>; + }; + + sdctrl@59810000 { + compatible = "socionext,uniphier-pxs2-sdctrl", + "simple-mfd", "syscon"; + reg = <0x59810000 0x800>; + + sd_clk: clock { + compatible = "socionext,uniphier-pxs2-sd-clock"; + #clock-cells = <1>; + }; + + sd_rst: reset { + compatible = "socionext,uniphier-pxs2-sd-reset"; + #reset-cells = <1>; + }; + }; + + perictrl@59820000 { + compatible = "socionext,uniphier-pxs2-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + peri_clk: clock { + compatible = "socionext,uniphier-pxs2-peri-clock"; + #clock-cells = <1>; + }; + + peri_rst: reset { + compatible = "socionext,uniphier-pxs2-peri-reset"; + #reset-cells = <1>; + }; + }; + + soc-glue@5f800000 { + compatible = "socionext,uniphier-pxs2-soc-glue", + "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-pxs2-pinctrl"; + }; + }; + + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; + interrupts = <1 11 0xf04>; + clocks = <&arm_timer_clk>; + }; + + timer@60000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x60000600 0x20>; + interrupts = <1 13 0xf04>; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@60001000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x60001000 0x1000>, + <0x60000100 0x100>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + sysctrl@61840000 { + compatible = "socionext,uniphier-pxs2-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x10000>; + + sys_clk: clock { + compatible = "socionext,uniphier-pxs2-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset { + compatible = "socionext,uniphier-pxs2-reset"; + #reset-cells = <1>; + }; + }; }; }; -&refclk { - clock-frequency = <25000000>; -}; - -&mio_clk { - compatible = "socionext,uniphier-pxs2-sd-clock"; -}; - -&mio_rst { - compatible = "socionext,uniphier-pxs2-sd-reset"; -}; - -&peri_clk { - compatible = "socionext,uniphier-pxs2-peri-clock"; -}; - -&peri_rst { - compatible = "socionext,uniphier-pxs2-peri-reset"; -}; - -&pinctrl { - compatible = "socionext,uniphier-pxs2-pinctrl"; -}; - -&sys_clk { - compatible = "socionext,uniphier-pxs2-clock"; -}; - -&sys_rst { - compatible = "socionext,uniphier-pxs2-reset"; -}; +/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi index d8cf0e7e11ea..b2c980ead7f0 100644 --- a/arch/arm/boot/dts/uniphier-sld8.dtsi +++ b/arch/arm/boot/dts/uniphier-sld8.dtsi @@ -43,7 +43,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -/include/ "uniphier-common32.dtsi" +/include/ "skeleton.dtsi" / { compatible = "socionext,uniphier-sld8"; @@ -61,146 +61,267 @@ cpu@0 { }; }; + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + clocks { + refclk: ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + arm_timer_clk: arm_timer_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <50000000>; }; }; -}; -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(256 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - - i2c0: i2c@58400000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58400000 0x40>; + soc { + compatible = "simple-bus"; #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - clock-frequency = <100000>; - }; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; - i2c1: i2c@58480000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58480000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - clock-frequency = <100000>; - }; + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, + <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(256 * 1024)>; + cache-sets = <256>; + cache-line-size = <128>; + cache-level = <2>; + }; - /* chip-internal connection for DMD */ - i2c2: i2c@58500000 { - compatible = "socionext,uniphier-i2c"; - reg = <0x58500000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&peri_clk 6>; - clock-frequency = <400000>; - }; + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + interrupts = <0 33 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&peri_clk 0>; + }; - i2c3: i2c@58580000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58580000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - clock-frequency = <100000>; - }; + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + interrupts = <0 35 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&peri_clk 1>; + }; - usb0: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; - resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>; - }; + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + interrupts = <0 37 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + clocks = <&peri_clk 2>; + }; - usb1: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; - resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>; - }; + serial3: serial@54006b00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x40>; + interrupts = <0 29 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + clocks = <&peri_clk 3>; + }; - usb2: usb@5a820100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a820100 0x100>; - interrupts = <0 82 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; - resets = <&mio_rst 7>, <&mio_rst 10>, <&mio_rst 14>, <&sys_rst 8>; + i2c0: i2c@58400000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58400000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&peri_clk 4>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58480000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58480000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&peri_clk 5>; + clock-frequency = <100000>; + }; + + /* chip-internal connection for DMD */ + i2c2: i2c@58500000 { + compatible = "socionext,uniphier-i2c"; + reg = <0x58500000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&peri_clk 6>; + clock-frequency = <400000>; + }; + + i2c3: i2c@58580000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58580000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&peri_clk 7>; + clock-frequency = <100000>; + }; + + system_bus: system-bus@58c00000 { + compatible = "socionext,uniphier-system-bus"; + status = "disabled"; + reg = <0x58c00000 0x400>; + #address-cells = <2>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_system_bus>; + }; + + smpctrl@59800000 { + compatible = "socionext,uniphier-smpctrl"; + reg = <0x59801000 0x400>; + }; + + mioctrl@59810000 { + compatible = "socionext,uniphier-sld8-mioctrl", + "simple-mfd", "syscon"; + reg = <0x59810000 0x800>; + + mio_clk: clock { + compatible = "socionext,uniphier-sld8-mio-clock"; + #clock-cells = <1>; + }; + + mio_rst: reset { + compatible = "socionext,uniphier-sld8-mio-reset"; + #reset-cells = <1>; + }; + }; + + perictrl@59820000 { + compatible = "socionext,uniphier-sld8-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + peri_clk: clock { + compatible = "socionext,uniphier-sld8-peri-clock"; + #clock-cells = <1>; + }; + + peri_rst: reset { + compatible = "socionext,uniphier-sld8-peri-reset"; + #reset-cells = <1>; + }; + }; + + usb0: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + interrupts = <0 80 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, + <&mio_rst 12>; + }; + + usb1: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + interrupts = <0 81 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, + <&mio_rst 13>; + }; + + usb2: usb@5a820100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a820100 0x100>; + interrupts = <0 82 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, + <&mio_rst 14>; + }; + + soc-glue@5f800000 { + compatible = "socionext,uniphier-sld8-soc-glue", + "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-sld8-pinctrl"; + }; + }; + + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; + interrupts = <1 11 0x104>; + clocks = <&arm_timer_clk>; + }; + + timer@60000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x60000600 0x20>; + interrupts = <1 13 0x104>; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@60001000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x60001000 0x1000>, + <0x60000100 0x100>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + sysctrl@61840000 { + compatible = "socionext,uniphier-sld8-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x10000>; + + sys_clk: clock { + compatible = "socionext,uniphier-sld8-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset { + compatible = "socionext,uniphier-sld8-reset"; + #reset-cells = <1>; + }; + }; }; }; -&refclk { - clock-frequency = <25000000>; -}; - -&serial3 { - interrupts = <0 29 4>; -}; - -&mio_clk { - compatible = "socionext,uniphier-sld8-mio-clock"; -}; - -&mio_rst { - compatible = "socionext,uniphier-sld8-mio-reset"; - resets = <&sys_rst 7>; -}; - -&peri_clk { - compatible = "socionext,uniphier-sld8-peri-clock"; -}; - -&peri_rst { - compatible = "socionext,uniphier-sld8-peri-reset"; -}; - -&pinctrl { - compatible = "socionext,uniphier-sld8-pinctrl"; -}; - -&sys_clk { - compatible = "socionext,uniphier-sld8-clock"; -}; - -&sys_rst { - compatible = "socionext,uniphier-sld8-reset"; -}; +/include/ "uniphier-pinctrl.dtsi" From 29ad7f49628eee53cda9319eeabbffaf39598a75 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 4 Nov 2016 09:53:53 +0900 Subject: [PATCH 5/7] ARM: dts: uniphier: remove redundant serial fifo-size properties These are the default of the optional property. No need to describe them explicitly. Signed-off-by: Masahiro Yamada --- arch/arm/boot/dts/uniphier-sld3.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/boot/dts/uniphier-sld3.dtsi b/arch/arm/boot/dts/uniphier-sld3.dtsi index 35c18197d94f..5f57a96e4e13 100644 --- a/arch/arm/boot/dts/uniphier-sld3.dtsi +++ b/arch/arm/boot/dts/uniphier-sld3.dtsi @@ -135,7 +135,6 @@ serial0: serial@54006800 { reg = <0x54006800 0x40>; interrupts = <0 33 4>; clocks = <&sys_clk 0>; - fifo-size = <64>; }; serial1: serial@54006900 { @@ -144,7 +143,6 @@ serial1: serial@54006900 { reg = <0x54006900 0x40>; interrupts = <0 35 4>; clocks = <&sys_clk 0>; - fifo-size = <64>; }; serial2: serial@54006a00 { @@ -153,7 +151,6 @@ serial2: serial@54006a00 { reg = <0x54006a00 0x40>; interrupts = <0 37 4>; clocks = <&sys_clk 0>; - fifo-size = <64>; }; i2c0: i2c@58400000 { From 64f4896592b5ac830bc0c7daf91ea21100eb54be Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 11 Oct 2016 15:26:06 +0900 Subject: [PATCH 6/7] ARM: dts: uniphier: add clocks/resets to EHCI nodes of sLD3 SoC Now, the clock/reset controller driver is available for this SoC. Signed-off-by: Masahiro Yamada --- arch/arm/boot/dts/uniphier-sld3.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/uniphier-sld3.dtsi b/arch/arm/boot/dts/uniphier-sld3.dtsi index 5f57a96e4e13..a75189f7d8fe 100644 --- a/arch/arm/boot/dts/uniphier-sld3.dtsi +++ b/arch/arm/boot/dts/uniphier-sld3.dtsi @@ -242,6 +242,9 @@ usb0: usb@5a800100 { status = "disabled"; reg = <0x5a800100 0x100>; interrupts = <0 80 4>; + clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, + <&mio_rst 12>; }; usb1: usb@5a810100 { @@ -249,6 +252,9 @@ usb1: usb@5a810100 { status = "disabled"; reg = <0x5a810100 0x100>; interrupts = <0 81 4>; + clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, + <&mio_rst 13>; }; usb2: usb@5a820100 { @@ -256,6 +262,9 @@ usb2: usb@5a820100 { status = "disabled"; reg = <0x5a820100 0x100>; interrupts = <0 82 4>; + clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, + <&mio_rst 14>; }; usb3: usb@5a830100 { @@ -263,6 +272,9 @@ usb3: usb@5a830100 { status = "disabled"; reg = <0x5a830100 0x100>; interrupts = <0 83 4>; + clocks = <&mio_clk 7>, <&mio_clk 11>, <&mio_clk 15>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 11>, + <&mio_rst 15>; }; sysctrl@f1840000 { From 13b4a6190b25c7bf69239bbc212d256656ada7b9 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Sat, 5 Nov 2016 16:28:26 +0900 Subject: [PATCH 7/7] ARM: dts: uniphier: make compatible of syscon nodes SoC-specific These hardware blocks are SoC-specific, so their compatible strings should be SoC-specific as well. This change has no impact on the actual behavior since it is controlled by the generic "simple-mfd", "syscon" compatible strings. Signed-off-by: Masahiro Yamada --- arch/arm/boot/dts/uniphier-sld3.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/uniphier-sld3.dtsi b/arch/arm/boot/dts/uniphier-sld3.dtsi index a75189f7d8fe..9fad6bd2db8a 100644 --- a/arch/arm/boot/dts/uniphier-sld3.dtsi +++ b/arch/arm/boot/dts/uniphier-sld3.dtsi @@ -222,7 +222,7 @@ smpctrl@59800000 { }; mioctrl@59810000 { - compatible = "socionext,uniphier-mioctrl", + compatible = "socionext,uniphier-sld3-mioctrl", "simple-mfd", "syscon"; reg = <0x59810000 0x800>; @@ -278,7 +278,7 @@ usb3: usb@5a830100 { }; sysctrl@f1840000 { - compatible = "socionext,uniphier-sysctrl", + compatible = "socionext,uniphier-sld3-sysctrl", "simple-mfd", "syscon"; reg = <0xf1840000 0x10000>;