mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-05-09 03:10:30 -04:00
Merge tag 'mtd/for-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
Pull MTD updates from Miquel Raynal:
"MTD core:
- Fix refcounting for unpartitioned MTDs
- Fix misspelled function parameter 'section'
- Remove unneeded break
- cmdline parser: Fix parsing of part-names with colons
- mtdpart: Fix misdocumented function parameter 'mtd'
MTD devices:
- phram:
- Allow the user to set the erase page size
- File headers are not good candidates for kernel-doc
- physmap-bt1-rom: Fix __iomem addrspace removal warning
- plat-ram: correctly free memory on error path in platram_probe()
- powernv_flash: Add function names to headers and fix 'dev'
- docg3: Fix kernel-doc 'bad line' and 'excessive doc' issues
UBI cleanup fixes:
- gluebi: Fix misnamed function parameter documentation
- wl: Fix a couple of kernel-doc issues
- eba: Fix a couple of misdocumentation issues
- kapi: Correct documentation for 'ubi_leb_read_sg's 'sgl' parameter
- Document 'ubi_num' in struct mtd_dev_param
Generic NAND core ECC management:
- Add an I/O request tweaking mechanism
- Entire rework of the software BCH ECC driver, creation of a real
ECC engine, getting rid of raw NAND structures, migration to more
generic prototypes, misc fixes and style cleanup. Moved now to the
Generic NAND layer.
- Entire rework of the software Hamming ECC driver, creation of a
real ECC engine, getting rid of raw NAND structures, misc renames,
comment updates, cleanup, and style fixes. Moved now to the generic
NAND layer.
- Necessary plumbing at the NAND level to retrieve generic NAND ECC
engines (softwares and on-die).
- Update of the bindings.
Raw NAND core:
- Geting rid of the chip->ecc.priv entry.
- Fix miscellaneous typos in kernel-doc
Raw NAND controller drivers:
- Arasan: Document 'anfc_op's 'buf' member
- AU1550: Ensure the presence of the right includes
- Brcmnand: Demote non-conformant kernel-doc headers
- Cafe: Remove superfluous param doc and add another
- Davinci: Do not use extra dereferencing
- Diskonchip: Marking unused variables as __always_unused
- GPMI:
- Fix the driver only sense CS0 R/B issue
- Fix the random DMA timeout issue
- Use a single line for of_device_id
- Use of_device_get_match_data()
- Fix reference count leak in gpmi ops
- Cleanup makefile
- Fix binding matching of clocks on different SoCs
- Ingenic: remove redundant get_device() in ingenic_ecc_get()
- Intel LGM: New NAND controller driver
- Marvell: Drop useless line
- Meson:
- Fix a resource leak in init
- Fix meson_nfc_dma_buffer_release() arguments
- mxc:
- Use device_get_match_data()
- Use a single line for of_device_id
- Remove platform data support
- Omap:
- Fix a bunch of kernel-doc misdemeanours
- Finish ELM half populated function header, demote empty ones
- s3c2410: Add documentation for 2 missing struct members
- Sunxi: Document 'sunxi_nfc's 'caps' member
- Qcom:
- Add support for SDX55
- Support for IPQ6018 QPIC NAND controller
- Fix DMA sync on FLASH_STATUS register read
- Rockchip: New NAND controller driver for RK3308, RK2928 and others
- Sunxi: Add MDMA support
ONENAND:
- bbt: Fix expected kernel-doc formatting
- Fix some kernel-doc misdemeanours
- Fix expected kernel-doc formatting
- Use mtd->oops_panic_write as condition
SPI-NAND core:
- Creation of a SPI-NAND on-die ECC engine
- Move ECC related definitions earlier in the driver
- Fix typo in comment
- Fill a default ECC provider/algorithm
- Remove outdated comment
- Fix OOB read
- Allow the case where there is no ECC engine
- Use the external ECC engine logic
SPI-NAND chip drivers:
- Micron:
- Add support for MT29F2G01AAAED
- Use more specific names
- Macronix:
- Add support for MX35LFxG24AD
- Add support for MX35LFxGE4AD
- Toshiba: Demote non-conformant kernel-doc header
SPI-NOR core:
- Initial support for stateful Octal DTR mode using volatile settings
- Preliminary support for JEDEC 251 (xSPI) and JEDEC 216D standards
- Support for Cypress Semper flash
- Support to specify ECC block size of SPI NOR flashes
- Fixes to avoid clearing of non-volatile Block Protection bits at
probe
- hisi-sfc: Demote non-conformant kernel-doc"
* tag 'mtd/for-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (120 commits)
mtd: spinand: macronix: Add support for MX35LFxG24AD
mtd: rawnand: rockchip: NFC driver for RK3308, RK2928 and others
dt-bindings: mtd: Describe Rockchip RK3xxx NAND flash controller
mtd: rawnand: gpmi: Use a single line for of_device_id
mtd: rawnand: gpmi: Fix the random DMA timeout issue
mtd: rawnand: gpmi: Fix the driver only sense CS0 R/B issue
mtd: rawnand: qcom: Add NAND controller support for SDX55
dt-bindings: qcom_nandc: Add SDX55 QPIC NAND documentation
mtd: rawnand: mxc: Use a single line for of_device_id
mtd: rawnand: mxc: Use device_get_match_data()
mtd: rawnand: meson: Fix a resource leak in init
mtd: rawnand: gpmi: Use of_device_get_match_data()
mtd: rawnand: Add NAND controller support on Intel LGM SoC
dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC
mtd: spinand: micron: Add support for MT29F2G01AAAED
mtd: spinand: micron: Use more specific names
mtd: rawnand: gpmi: fix reference count leak in gpmi ops
dt-bindings: mtd: gpmi-nand: Fix matching of clocks on different SoCs
mtd: spinand: macronix: Add support for MX35LFxGE4AD
mtd: plat-ram: correctly free memory on error path in platram_probe()
...
This commit is contained in:
Linus Torvalds
73
include/linux/mtd/nand-ecc-sw-bch.h
Normal file
73
include/linux/mtd/nand-ecc-sw-bch.h
Normal file
@@ -0,0 +1,73 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright © 2011 Ivan Djelic <ivan.djelic@parrot.com>
|
||||
*
|
||||
* This file is the header for the NAND BCH ECC implementation.
|
||||
*/
|
||||
|
||||
#ifndef __MTD_NAND_ECC_SW_BCH_H__
|
||||
#define __MTD_NAND_ECC_SW_BCH_H__
|
||||
|
||||
#include <linux/mtd/nand.h>
|
||||
#include <linux/bch.h>
|
||||
|
||||
/**
|
||||
* struct nand_ecc_sw_bch_conf - private software BCH ECC engine structure
|
||||
* @req_ctx: Save request context and tweak the original request to fit the
|
||||
* engine needs
|
||||
* @code_size: Number of bytes needed to store a code (one code per step)
|
||||
* @nsteps: Number of steps
|
||||
* @calc_buf: Buffer to use when calculating ECC bytes
|
||||
* @code_buf: Buffer to use when reading (raw) ECC bytes from the chip
|
||||
* @bch: BCH control structure
|
||||
* @errloc: error location array
|
||||
* @eccmask: XOR ecc mask, allows erased pages to be decoded as valid
|
||||
*/
|
||||
struct nand_ecc_sw_bch_conf {
|
||||
struct nand_ecc_req_tweak_ctx req_ctx;
|
||||
unsigned int code_size;
|
||||
unsigned int nsteps;
|
||||
u8 *calc_buf;
|
||||
u8 *code_buf;
|
||||
struct bch_control *bch;
|
||||
unsigned int *errloc;
|
||||
unsigned char *eccmask;
|
||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_BCH)
|
||||
|
||||
int nand_ecc_sw_bch_calculate(struct nand_device *nand,
|
||||
const unsigned char *buf, unsigned char *code);
|
||||
int nand_ecc_sw_bch_correct(struct nand_device *nand, unsigned char *buf,
|
||||
unsigned char *read_ecc, unsigned char *calc_ecc);
|
||||
int nand_ecc_sw_bch_init_ctx(struct nand_device *nand);
|
||||
void nand_ecc_sw_bch_cleanup_ctx(struct nand_device *nand);
|
||||
struct nand_ecc_engine *nand_ecc_sw_bch_get_engine(void);
|
||||
|
||||
#else /* !CONFIG_MTD_NAND_ECC_SW_BCH */
|
||||
|
||||
static inline int nand_ecc_sw_bch_calculate(struct nand_device *nand,
|
||||
const unsigned char *buf,
|
||||
unsigned char *code)
|
||||
{
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
static inline int nand_ecc_sw_bch_correct(struct nand_device *nand,
|
||||
unsigned char *buf,
|
||||
unsigned char *read_ecc,
|
||||
unsigned char *calc_ecc)
|
||||
{
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
static inline int nand_ecc_sw_bch_init_ctx(struct nand_device *nand)
|
||||
{
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
static inline void nand_ecc_sw_bch_cleanup_ctx(struct nand_device *nand) {}
|
||||
|
||||
#endif /* CONFIG_MTD_NAND_ECC_SW_BCH */
|
||||
|
||||
#endif /* __MTD_NAND_ECC_SW_BCH_H__ */
|
||||
91
include/linux/mtd/nand-ecc-sw-hamming.h
Normal file
91
include/linux/mtd/nand-ecc-sw-hamming.h
Normal file
@@ -0,0 +1,91 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2000-2010 Steven J. Hill <sjhill@realitydiluted.com>
|
||||
* David Woodhouse <dwmw2@infradead.org>
|
||||
* Thomas Gleixner <tglx@linutronix.de>
|
||||
*
|
||||
* This file is the header for the NAND Hamming ECC implementation.
|
||||
*/
|
||||
|
||||
#ifndef __MTD_NAND_ECC_SW_HAMMING_H__
|
||||
#define __MTD_NAND_ECC_SW_HAMMING_H__
|
||||
|
||||
#include <linux/mtd/nand.h>
|
||||
|
||||
/**
|
||||
* struct nand_ecc_sw_hamming_conf - private software Hamming ECC engine structure
|
||||
* @req_ctx: Save request context and tweak the original request to fit the
|
||||
* engine needs
|
||||
* @code_size: Number of bytes needed to store a code (one code per step)
|
||||
* @nsteps: Number of steps
|
||||
* @calc_buf: Buffer to use when calculating ECC bytes
|
||||
* @code_buf: Buffer to use when reading (raw) ECC bytes from the chip
|
||||
* @sm_order: Smart Media special ordering
|
||||
*/
|
||||
struct nand_ecc_sw_hamming_conf {
|
||||
struct nand_ecc_req_tweak_ctx req_ctx;
|
||||
unsigned int code_size;
|
||||
unsigned int nsteps;
|
||||
u8 *calc_buf;
|
||||
u8 *code_buf;
|
||||
unsigned int sm_order;
|
||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING)
|
||||
|
||||
int nand_ecc_sw_hamming_init_ctx(struct nand_device *nand);
|
||||
void nand_ecc_sw_hamming_cleanup_ctx(struct nand_device *nand);
|
||||
int ecc_sw_hamming_calculate(const unsigned char *buf, unsigned int step_size,
|
||||
unsigned char *code, bool sm_order);
|
||||
int nand_ecc_sw_hamming_calculate(struct nand_device *nand,
|
||||
const unsigned char *buf,
|
||||
unsigned char *code);
|
||||
int ecc_sw_hamming_correct(unsigned char *buf, unsigned char *read_ecc,
|
||||
unsigned char *calc_ecc, unsigned int step_size,
|
||||
bool sm_order);
|
||||
int nand_ecc_sw_hamming_correct(struct nand_device *nand, unsigned char *buf,
|
||||
unsigned char *read_ecc,
|
||||
unsigned char *calc_ecc);
|
||||
|
||||
#else /* !CONFIG_MTD_NAND_ECC_SW_HAMMING */
|
||||
|
||||
static inline int nand_ecc_sw_hamming_init_ctx(struct nand_device *nand)
|
||||
{
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
static inline void nand_ecc_sw_hamming_cleanup_ctx(struct nand_device *nand) {}
|
||||
|
||||
static inline int ecc_sw_hamming_calculate(const unsigned char *buf,
|
||||
unsigned int step_size,
|
||||
unsigned char *code, bool sm_order)
|
||||
{
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
static inline int nand_ecc_sw_hamming_calculate(struct nand_device *nand,
|
||||
const unsigned char *buf,
|
||||
unsigned char *code)
|
||||
{
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
static inline int ecc_sw_hamming_correct(unsigned char *buf,
|
||||
unsigned char *read_ecc,
|
||||
unsigned char *calc_ecc,
|
||||
unsigned int step_size, bool sm_order)
|
||||
{
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
static inline int nand_ecc_sw_hamming_correct(struct nand_device *nand,
|
||||
unsigned char *buf,
|
||||
unsigned char *read_ecc,
|
||||
unsigned char *calc_ecc)
|
||||
{
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_MTD_NAND_ECC_SW_HAMMING */
|
||||
|
||||
#endif /* __MTD_NAND_ECC_SW_HAMMING_H__ */
|
||||
@@ -277,6 +277,58 @@ int nand_ecc_prepare_io_req(struct nand_device *nand,
|
||||
int nand_ecc_finish_io_req(struct nand_device *nand,
|
||||
struct nand_page_io_req *req);
|
||||
bool nand_ecc_is_strong_enough(struct nand_device *nand);
|
||||
struct nand_ecc_engine *nand_ecc_get_sw_engine(struct nand_device *nand);
|
||||
struct nand_ecc_engine *nand_ecc_get_on_die_hw_engine(struct nand_device *nand);
|
||||
|
||||
#if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING)
|
||||
struct nand_ecc_engine *nand_ecc_sw_hamming_get_engine(void);
|
||||
#else
|
||||
static inline struct nand_ecc_engine *nand_ecc_sw_hamming_get_engine(void)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
#endif /* CONFIG_MTD_NAND_ECC_SW_HAMMING */
|
||||
|
||||
#if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_BCH)
|
||||
struct nand_ecc_engine *nand_ecc_sw_bch_get_engine(void);
|
||||
#else
|
||||
static inline struct nand_ecc_engine *nand_ecc_sw_bch_get_engine(void)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
#endif /* CONFIG_MTD_NAND_ECC_SW_BCH */
|
||||
|
||||
/**
|
||||
* struct nand_ecc_req_tweak_ctx - Help for automatically tweaking requests
|
||||
* @orig_req: Pointer to the original IO request
|
||||
* @nand: Related NAND device, to have access to its memory organization
|
||||
* @page_buffer_size: Real size of the page buffer to use (can be set by the
|
||||
* user before the tweaking mechanism initialization)
|
||||
* @oob_buffer_size: Real size of the OOB buffer to use (can be set by the
|
||||
* user before the tweaking mechanism initialization)
|
||||
* @spare_databuf: Data bounce buffer
|
||||
* @spare_oobbuf: OOB bounce buffer
|
||||
* @bounce_data: Flag indicating a data bounce buffer is used
|
||||
* @bounce_oob: Flag indicating an OOB bounce buffer is used
|
||||
*/
|
||||
struct nand_ecc_req_tweak_ctx {
|
||||
struct nand_page_io_req orig_req;
|
||||
struct nand_device *nand;
|
||||
unsigned int page_buffer_size;
|
||||
unsigned int oob_buffer_size;
|
||||
void *spare_databuf;
|
||||
void *spare_oobbuf;
|
||||
bool bounce_data;
|
||||
bool bounce_oob;
|
||||
};
|
||||
|
||||
int nand_ecc_init_req_tweaking(struct nand_ecc_req_tweak_ctx *ctx,
|
||||
struct nand_device *nand);
|
||||
void nand_ecc_cleanup_req_tweaking(struct nand_ecc_req_tweak_ctx *ctx);
|
||||
void nand_ecc_tweak_req(struct nand_ecc_req_tweak_ctx *ctx,
|
||||
struct nand_page_io_req *req);
|
||||
void nand_ecc_restore_req(struct nand_ecc_req_tweak_ctx *ctx,
|
||||
struct nand_page_io_req *req);
|
||||
|
||||
/**
|
||||
* struct nand_ecc - Information relative to the ECC
|
||||
@@ -884,6 +936,10 @@ bool nanddev_isreserved(struct nand_device *nand, const struct nand_pos *pos);
|
||||
int nanddev_erase(struct nand_device *nand, const struct nand_pos *pos);
|
||||
int nanddev_markbad(struct nand_device *nand, const struct nand_pos *pos);
|
||||
|
||||
/* ECC related functions */
|
||||
int nanddev_ecc_engine_init(struct nand_device *nand);
|
||||
void nanddev_ecc_engine_cleanup(struct nand_device *nand);
|
||||
|
||||
/* BBT related functions */
|
||||
enum nand_bbt_block_status {
|
||||
NAND_BBT_BLOCK_STATUS_UNKNOWN,
|
||||
|
||||
@@ -1,66 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright © 2011 Ivan Djelic <ivan.djelic@parrot.com>
|
||||
*
|
||||
* This file is the header for the NAND BCH ECC implementation.
|
||||
*/
|
||||
|
||||
#ifndef __MTD_NAND_BCH_H__
|
||||
#define __MTD_NAND_BCH_H__
|
||||
|
||||
struct mtd_info;
|
||||
struct nand_chip;
|
||||
struct nand_bch_control;
|
||||
|
||||
#if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_BCH)
|
||||
|
||||
static inline int mtd_nand_has_bch(void) { return 1; }
|
||||
|
||||
/*
|
||||
* Calculate BCH ecc code
|
||||
*/
|
||||
int nand_bch_calculate_ecc(struct nand_chip *chip, const u_char *dat,
|
||||
u_char *ecc_code);
|
||||
|
||||
/*
|
||||
* Detect and correct bit errors
|
||||
*/
|
||||
int nand_bch_correct_data(struct nand_chip *chip, u_char *dat,
|
||||
u_char *read_ecc, u_char *calc_ecc);
|
||||
/*
|
||||
* Initialize BCH encoder/decoder
|
||||
*/
|
||||
struct nand_bch_control *nand_bch_init(struct mtd_info *mtd);
|
||||
/*
|
||||
* Release BCH encoder/decoder resources
|
||||
*/
|
||||
void nand_bch_free(struct nand_bch_control *nbc);
|
||||
|
||||
#else /* !CONFIG_MTD_NAND_ECC_SW_BCH */
|
||||
|
||||
static inline int mtd_nand_has_bch(void) { return 0; }
|
||||
|
||||
static inline int
|
||||
nand_bch_calculate_ecc(struct nand_chip *chip, const u_char *dat,
|
||||
u_char *ecc_code)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
static inline int
|
||||
nand_bch_correct_data(struct nand_chip *chip, unsigned char *buf,
|
||||
unsigned char *read_ecc, unsigned char *calc_ecc)
|
||||
{
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
static inline struct nand_bch_control *nand_bch_init(struct mtd_info *mtd)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline void nand_bch_free(struct nand_bch_control *nbc) {}
|
||||
|
||||
#endif /* CONFIG_MTD_NAND_ECC_SW_BCH */
|
||||
|
||||
#endif /* __MTD_NAND_BCH_H__ */
|
||||
@@ -1,39 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2000-2010 Steven J. Hill <sjhill@realitydiluted.com>
|
||||
* David Woodhouse <dwmw2@infradead.org>
|
||||
* Thomas Gleixner <tglx@linutronix.de>
|
||||
*
|
||||
* This file is the header for the ECC algorithm.
|
||||
*/
|
||||
|
||||
#ifndef __MTD_NAND_ECC_H__
|
||||
#define __MTD_NAND_ECC_H__
|
||||
|
||||
struct nand_chip;
|
||||
|
||||
/*
|
||||
* Calculate 3 byte ECC code for eccsize byte block
|
||||
*/
|
||||
void __nand_calculate_ecc(const u_char *dat, unsigned int eccsize,
|
||||
u_char *ecc_code, bool sm_order);
|
||||
|
||||
/*
|
||||
* Calculate 3 byte ECC code for 256/512 byte block
|
||||
*/
|
||||
int nand_calculate_ecc(struct nand_chip *chip, const u_char *dat,
|
||||
u_char *ecc_code);
|
||||
|
||||
/*
|
||||
* Detect and correct a 1 bit error for eccsize byte block
|
||||
*/
|
||||
int __nand_correct_data(u_char *dat, u_char *read_ecc, u_char *calc_ecc,
|
||||
unsigned int eccsize, bool sm_order);
|
||||
|
||||
/*
|
||||
* Detect and correct a 1 bit error for 256/512 byte block
|
||||
*/
|
||||
int nand_correct_data(struct nand_chip *chip, u_char *dat, u_char *read_ecc,
|
||||
u_char *calc_ecc);
|
||||
|
||||
#endif /* __MTD_NAND_ECC_H__ */
|
||||
@@ -302,7 +302,6 @@ static const struct nand_ecc_caps __name = { \
|
||||
* @prepad: padding information for syndrome based ECC generators
|
||||
* @postpad: padding information for syndrome based ECC generators
|
||||
* @options: ECC specific options (see NAND_ECC_XXX flags defined above)
|
||||
* @priv: pointer to private ECC control data
|
||||
* @calc_buf: buffer for calculated ECC, size is oobsize.
|
||||
* @code_buf: buffer for ECC read from flash, size is oobsize.
|
||||
* @hwctl: function to control hardware ECC generator. Must only
|
||||
@@ -355,7 +354,6 @@ struct nand_ecc_ctrl {
|
||||
int prepad;
|
||||
int postpad;
|
||||
unsigned int options;
|
||||
void *priv;
|
||||
u8 *calc_buf;
|
||||
u8 *code_buf;
|
||||
void (*hwctl)(struct nand_chip *chip, int mode);
|
||||
@@ -1286,7 +1284,8 @@ static inline bool nand_is_slc(struct nand_chip *chip)
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the opcode's address should be sent only on the lower 8 bits
|
||||
* nand_opcode_8bits - Check if the opcode's address should be sent only on the
|
||||
* lower 8 bits
|
||||
* @command: opcode to check
|
||||
*/
|
||||
static inline int nand_opcode_8bits(unsigned int command)
|
||||
@@ -1303,6 +1302,20 @@ static inline int nand_opcode_8bits(unsigned int command)
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rawnand_sw_hamming_init(struct nand_chip *chip);
|
||||
int rawnand_sw_hamming_calculate(struct nand_chip *chip,
|
||||
const unsigned char *buf,
|
||||
unsigned char *code);
|
||||
int rawnand_sw_hamming_correct(struct nand_chip *chip,
|
||||
unsigned char *buf,
|
||||
unsigned char *read_ecc,
|
||||
unsigned char *calc_ecc);
|
||||
void rawnand_sw_hamming_cleanup(struct nand_chip *chip);
|
||||
int rawnand_sw_bch_init(struct nand_chip *chip);
|
||||
int rawnand_sw_bch_correct(struct nand_chip *chip, unsigned char *buf,
|
||||
unsigned char *read_ecc, unsigned char *calc_ecc);
|
||||
void rawnand_sw_bch_cleanup(struct nand_chip *chip);
|
||||
|
||||
int nand_check_erased_ecc_chunk(void *data, int datalen,
|
||||
void *ecc, int ecclen,
|
||||
void *extraoob, int extraooblen,
|
||||
|
||||
@@ -9,7 +9,6 @@
|
||||
#define _MTD_SHARPSL_H
|
||||
|
||||
#include <linux/mtd/rawnand.h>
|
||||
#include <linux/mtd/nand_ecc.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
|
||||
struct sharpsl_nand_platform_data {
|
||||
|
||||
@@ -51,6 +51,8 @@
|
||||
#define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
|
||||
#define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
|
||||
#define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */
|
||||
#define SPINOR_OP_SRSTEN 0x66 /* Software Reset Enable */
|
||||
#define SPINOR_OP_SRST 0x99 /* Software Reset */
|
||||
|
||||
/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
|
||||
#define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
|
||||
@@ -182,6 +184,7 @@ enum spi_nor_protocol {
|
||||
SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
|
||||
SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
|
||||
SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
|
||||
SNOR_PROTO_8_8_8_DTR = SNOR_PROTO_DTR(8, 8, 8),
|
||||
};
|
||||
|
||||
static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
|
||||
@@ -228,7 +231,7 @@ struct spi_nor_hwcaps {
|
||||
* then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
|
||||
* (Slow) Read.
|
||||
*/
|
||||
#define SNOR_HWCAPS_READ_MASK GENMASK(14, 0)
|
||||
#define SNOR_HWCAPS_READ_MASK GENMASK(15, 0)
|
||||
#define SNOR_HWCAPS_READ BIT(0)
|
||||
#define SNOR_HWCAPS_READ_FAST BIT(1)
|
||||
#define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
|
||||
@@ -245,11 +248,12 @@ struct spi_nor_hwcaps {
|
||||
#define SNOR_HWCAPS_READ_4_4_4 BIT(9)
|
||||
#define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
|
||||
|
||||
#define SNOR_HWCAPS_READ_OCTAL GENMASK(14, 11)
|
||||
#define SNOR_HWCAPS_READ_OCTAL GENMASK(15, 11)
|
||||
#define SNOR_HWCAPS_READ_1_1_8 BIT(11)
|
||||
#define SNOR_HWCAPS_READ_1_8_8 BIT(12)
|
||||
#define SNOR_HWCAPS_READ_8_8_8 BIT(13)
|
||||
#define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
|
||||
#define SNOR_HWCAPS_READ_8_8_8_DTR BIT(15)
|
||||
|
||||
/*
|
||||
* Page Program capabilities.
|
||||
@@ -260,18 +264,19 @@ struct spi_nor_hwcaps {
|
||||
* JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
|
||||
* implements such commands.
|
||||
*/
|
||||
#define SNOR_HWCAPS_PP_MASK GENMASK(22, 16)
|
||||
#define SNOR_HWCAPS_PP BIT(16)
|
||||
#define SNOR_HWCAPS_PP_MASK GENMASK(23, 16)
|
||||
#define SNOR_HWCAPS_PP BIT(16)
|
||||
|
||||
#define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
|
||||
#define SNOR_HWCAPS_PP_1_1_4 BIT(17)
|
||||
#define SNOR_HWCAPS_PP_1_4_4 BIT(18)
|
||||
#define SNOR_HWCAPS_PP_4_4_4 BIT(19)
|
||||
#define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
|
||||
#define SNOR_HWCAPS_PP_1_1_4 BIT(17)
|
||||
#define SNOR_HWCAPS_PP_1_4_4 BIT(18)
|
||||
#define SNOR_HWCAPS_PP_4_4_4 BIT(19)
|
||||
|
||||
#define SNOR_HWCAPS_PP_OCTAL GENMASK(22, 20)
|
||||
#define SNOR_HWCAPS_PP_1_1_8 BIT(20)
|
||||
#define SNOR_HWCAPS_PP_1_8_8 BIT(21)
|
||||
#define SNOR_HWCAPS_PP_8_8_8 BIT(22)
|
||||
#define SNOR_HWCAPS_PP_OCTAL GENMASK(23, 20)
|
||||
#define SNOR_HWCAPS_PP_1_1_8 BIT(20)
|
||||
#define SNOR_HWCAPS_PP_1_8_8 BIT(21)
|
||||
#define SNOR_HWCAPS_PP_8_8_8 BIT(22)
|
||||
#define SNOR_HWCAPS_PP_8_8_8_DTR BIT(23)
|
||||
|
||||
#define SNOR_HWCAPS_X_X_X (SNOR_HWCAPS_READ_2_2_2 | \
|
||||
SNOR_HWCAPS_READ_4_4_4 | \
|
||||
@@ -279,10 +284,14 @@ struct spi_nor_hwcaps {
|
||||
SNOR_HWCAPS_PP_4_4_4 | \
|
||||
SNOR_HWCAPS_PP_8_8_8)
|
||||
|
||||
#define SNOR_HWCAPS_X_X_X_DTR (SNOR_HWCAPS_READ_8_8_8_DTR | \
|
||||
SNOR_HWCAPS_PP_8_8_8_DTR)
|
||||
|
||||
#define SNOR_HWCAPS_DTR (SNOR_HWCAPS_READ_1_1_1_DTR | \
|
||||
SNOR_HWCAPS_READ_1_2_2_DTR | \
|
||||
SNOR_HWCAPS_READ_1_4_4_DTR | \
|
||||
SNOR_HWCAPS_READ_1_8_8_DTR)
|
||||
SNOR_HWCAPS_READ_1_8_8_DTR | \
|
||||
SNOR_HWCAPS_READ_8_8_8_DTR)
|
||||
|
||||
#define SNOR_HWCAPS_ALL (SNOR_HWCAPS_READ_MASK | \
|
||||
SNOR_HWCAPS_PP_MASK)
|
||||
@@ -318,6 +327,22 @@ struct spi_nor_controller_ops {
|
||||
int (*erase)(struct spi_nor *nor, loff_t offs);
|
||||
};
|
||||
|
||||
/**
|
||||
* enum spi_nor_cmd_ext - describes the command opcode extension in DTR mode
|
||||
* @SPI_NOR_EXT_NONE: no extension. This is the default, and is used in Legacy
|
||||
* SPI mode
|
||||
* @SPI_NOR_EXT_REPEAT: the extension is same as the opcode
|
||||
* @SPI_NOR_EXT_INVERT: the extension is the bitwise inverse of the opcode
|
||||
* @SPI_NOR_EXT_HEX: the extension is any hex value. The command and opcode
|
||||
* combine to form a 16-bit opcode.
|
||||
*/
|
||||
enum spi_nor_cmd_ext {
|
||||
SPI_NOR_EXT_NONE = 0,
|
||||
SPI_NOR_EXT_REPEAT,
|
||||
SPI_NOR_EXT_INVERT,
|
||||
SPI_NOR_EXT_HEX,
|
||||
};
|
||||
|
||||
/*
|
||||
* Forward declarations that are used internally by the core and manufacturer
|
||||
* drivers.
|
||||
@@ -345,6 +370,7 @@ struct spi_nor_flash_parameter;
|
||||
* @program_opcode: the program opcode
|
||||
* @sst_write_second: used by the SST write operation
|
||||
* @flags: flag options for the current SPI NOR (SNOR_F_*)
|
||||
* @cmd_ext_type: the command opcode extension type for DTR mode.
|
||||
* @read_proto: the SPI protocol for read operations
|
||||
* @write_proto: the SPI protocol for write operations
|
||||
* @reg_proto: the SPI protocol for read_reg/write_reg/erase operations
|
||||
@@ -376,6 +402,7 @@ struct spi_nor {
|
||||
enum spi_nor_protocol reg_proto;
|
||||
bool sst_write_second;
|
||||
u32 flags;
|
||||
enum spi_nor_cmd_ext cmd_ext_type;
|
||||
|
||||
const struct spi_nor_controller_ops *controller_ops;
|
||||
|
||||
@@ -406,7 +433,7 @@ static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
|
||||
* @name: the chip type name
|
||||
* @hwcaps: the hardware capabilities supported by the controller driver
|
||||
*
|
||||
* The drivers can use this fuction to scan the SPI NOR.
|
||||
* The drivers can use this function to scan the SPI NOR.
|
||||
* In the scanning, it will try to get all the necessary information to
|
||||
* fill the mtd_info{} and the spi_nor{}.
|
||||
*
|
||||
|
||||
@@ -286,6 +286,15 @@ struct spinand_ecc_info {
|
||||
#define SPINAND_HAS_QE_BIT BIT(0)
|
||||
#define SPINAND_HAS_CR_FEAT_BIT BIT(1)
|
||||
|
||||
/**
|
||||
* struct spinand_ondie_ecc_conf - private SPI-NAND on-die ECC engine structure
|
||||
* @status: status of the last wait operation that will be used in case
|
||||
* ->get_status() is not populated by the spinand device.
|
||||
*/
|
||||
struct spinand_ondie_ecc_conf {
|
||||
u8 status;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct spinand_info - Structure used to describe SPI NAND chips
|
||||
* @model: model name
|
||||
|
||||
@@ -1,19 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Sascha Hauer, kernel@pengutronix.de
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_NAND_H
|
||||
#define __ASM_ARCH_NAND_H
|
||||
|
||||
#include <linux/mtd/partitions.h>
|
||||
|
||||
struct mxc_nand_platform_data {
|
||||
unsigned int width; /* data bus width in bytes */
|
||||
unsigned int hw_ecc:1; /* 0 if suppress hardware ECC */
|
||||
unsigned int flash_bbt:1; /* set to 1 to use a flash based bbt */
|
||||
struct mtd_partition *parts; /* partition table */
|
||||
int nr_parts; /* size of parts */
|
||||
};
|
||||
#endif /* __ASM_ARCH_NAND_H */
|
||||
Reference in New Issue
Block a user