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arm64: dts: qcom: sm8450: add display hardware devices
Add devices tree nodes describing display hardware on SM8450: - Display Clock Controller - MDSS - MDP - two DSI controllers and DSI PHYs This does not provide support for DP controllers present on SM8450. Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221207012803.114959-3-dmitry.baryshkov@linaro.org
This commit is contained in:
Dmitry Baryshkov
committed by
Bjorn Andersson
Bjorn Andersson
parent
a5ac24ba17
commit
a6dd1206e4
@@ -2646,6 +2646,281 @@ camcc: clock-controller@ade0000 {
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status = "disabled";
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status = "disabled";
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};
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};
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mdss: display-subsystem@ae00000 {
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compatible = "qcom,sm8450-mdss";
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reg = <0 0x0ae00000 0 0x1000>;
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reg-names = "mdss";
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/* same path used twice */
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interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
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<&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>;
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interconnect-names = "mdp0-mem", "mdp1-mem";
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resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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power-domains = <&dispcc MDSS_GDSC>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&gcc GCC_DISP_HF_AXI_CLK>,
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<&gcc GCC_DISP_SF_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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iommus = <&apps_smmu 0x2800 0x402>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "disabled";
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mdss_mdp: display-controller@ae01000 {
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compatible = "qcom,sm8450-dpu";
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reg = <0 0x0ae01000 0 0x8f000>,
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<0 0x0aeb0000 0 0x2008>;
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reg-names = "mdp", "vbif";
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clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
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<&gcc GCC_DISP_SF_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>,
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<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
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clock-names = "bus",
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"nrt_bus",
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"iface",
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"lut",
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"core",
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"vsync";
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assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
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assigned-clock-rates = <19200000>;
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operating-points-v2 = <&mdp_opp_table>;
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power-domains = <&rpmhpd SM8450_MMCX>;
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interrupt-parent = <&mdss>;
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interrupts = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dpu_intf1_out: endpoint {
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remote-endpoint = <&mdss_dsi0_in>;
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};
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};
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port@1 {
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reg = <1>;
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dpu_intf2_out: endpoint {
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remote-endpoint = <&mdss_dsi1_in>;
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};
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};
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};
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mdp_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-172000000 {
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opp-hz = /bits/ 64 <172000000>;
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required-opps = <&rpmhpd_opp_low_svs_d1>;
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};
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opp-200000000 {
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opp-hz = /bits/ 64 <200000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-325000000 {
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opp-hz = /bits/ 64 <325000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-375000000 {
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opp-hz = /bits/ 64 <375000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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opp-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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required-opps = <&rpmhpd_opp_nom>;
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};
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};
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};
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mdss_dsi0: dsi@ae94000 {
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compatible = "qcom,mdss-dsi-ctrl";
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reg = <0 0x0ae94000 0 0x400>;
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reg-names = "dsi_ctrl";
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interrupt-parent = <&mdss>;
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interrupts = <4>;
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clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
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<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
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<&dispcc DISP_CC_MDSS_ESC0_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&gcc GCC_DISP_HF_AXI_CLK>;
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clock-names = "byte",
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"byte_intf",
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"pixel",
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"core",
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"iface",
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"bus";
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assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
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assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
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operating-points-v2 = <&mdss_dsi_opp_table>;
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power-domains = <&rpmhpd SM8450_MMCX>;
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phys = <&mdss_dsi0_phy>;
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phy-names = "dsi";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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mdss_dsi0_in: endpoint {
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remote-endpoint = <&dpu_intf1_out>;
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};
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};
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port@1 {
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reg = <1>;
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mdss_dsi0_out: endpoint {
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};
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};
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};
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mdss_dsi_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-187500000 {
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opp-hz = /bits/ 64 <187500000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-300000000 {
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opp-hz = /bits/ 64 <300000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-358000000 {
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opp-hz = /bits/ 64 <358000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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};
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};
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mdss_dsi0_phy: phy@ae94400 {
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compatible = "qcom,dsi-phy-5nm-8450";
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reg = <0 0x0ae94400 0 0x200>,
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<0 0x0ae94600 0 0x280>,
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<0 0x0ae94900 0 0x260>;
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reg-names = "dsi_phy",
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"dsi_phy_lane",
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"dsi_pll";
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#clock-cells = <1>;
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#phy-cells = <0>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "iface", "ref";
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status = "disabled";
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};
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mdss_dsi1: dsi@ae96000 {
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compatible = "qcom,mdss-dsi-ctrl";
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reg = <0 0x0ae96000 0 0x400>;
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reg-names = "dsi_ctrl";
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interrupt-parent = <&mdss>;
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interrupts = <5>;
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clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
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<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
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<&dispcc DISP_CC_MDSS_ESC1_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&gcc GCC_DISP_HF_AXI_CLK>;
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clock-names = "byte",
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"byte_intf",
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"pixel",
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"core",
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"iface",
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"bus";
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assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
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assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
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operating-points-v2 = <&mdss_dsi_opp_table>;
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power-domains = <&rpmhpd SM8450_MMCX>;
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phys = <&mdss_dsi1_phy>;
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phy-names = "dsi";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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mdss_dsi1_in: endpoint {
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remote-endpoint = <&dpu_intf2_out>;
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};
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};
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port@1 {
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reg = <1>;
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mdss_dsi1_out: endpoint {
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};
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};
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};
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};
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mdss_dsi1_phy: phy@ae96400 {
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compatible = "qcom,dsi-phy-5nm-8450";
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reg = <0 0x0ae96400 0 0x200>,
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<0 0x0ae96600 0 0x280>,
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<0 0x0ae96900 0 0x260>;
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reg-names = "dsi_phy",
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"dsi_phy_lane",
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"dsi_pll";
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#clock-cells = <1>;
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#phy-cells = <0>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "iface", "ref";
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status = "disabled";
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};
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};
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dispcc: clock-controller@af00000 {
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dispcc: clock-controller@af00000 {
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compatible = "qcom,sm8450-dispcc";
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compatible = "qcom,sm8450-dispcc";
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reg = <0 0x0af00000 0 0x20000>;
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reg = <0 0x0af00000 0 0x20000>;
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@@ -2653,10 +2928,10 @@ dispcc: clock-controller@af00000 {
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<&rpmhcc RPMH_CXO_CLK_A>,
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<&rpmhcc RPMH_CXO_CLK_A>,
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<&gcc GCC_DISP_AHB_CLK>,
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<&gcc GCC_DISP_AHB_CLK>,
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<&sleep_clk>,
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<&sleep_clk>,
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<0>, /* dsi0 */
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<&mdss_dsi0_phy 0>,
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<0>,
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<&mdss_dsi0_phy 1>,
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<0>, /* dsi1 */
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<&mdss_dsi1_phy 0>,
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<0>,
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<&mdss_dsi1_phy 1>,
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<0>, /* dp0 */
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<0>, /* dp0 */
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<0>,
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<0>,
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<0>, /* dp1 */
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<0>, /* dp1 */
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