From 041d2acb68fb7220b8c7f8097da4f0915447f238 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= Date: Fri, 19 Jun 2026 18:14:10 +0200 Subject: [PATCH 01/18] pwm: mc33xs2410: Initialize spi_device_id arrays using member names MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit While being less compact, using named initializers allows to more easily see which members of the structs are assigned which value without having to lookup the declaration of the struct. And it's also more robust against changes to the struct definition. The mentioned robustness is relevant for a planned change to struct spi_device_id that replaces .driver_data by an anonymous union. This patch doesn't modify the compiled array, only its representation in source form benefits. Signed-off-by: Uwe Kleine-König (The Capable Hub) Link: https://patch.msgid.link/3fc7783506cc6429b8942cb7294926a6d4cb353e.1781885606.git.u.kleine-koenig@baylibre.com Signed-off-by: Uwe Kleine-König --- drivers/pwm/pwm-mc33xs2410.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-mc33xs2410.c b/drivers/pwm/pwm-mc33xs2410.c index 6d99e3ff7239..9f89b60dda78 100644 --- a/drivers/pwm/pwm-mc33xs2410.c +++ b/drivers/pwm/pwm-mc33xs2410.c @@ -381,7 +381,7 @@ static int mc33xs2410_probe(struct spi_device *spi) } static const struct spi_device_id mc33xs2410_spi_id[] = { - { "mc33xs2410" }, + { .name = "mc33xs2410" }, { } }; MODULE_DEVICE_TABLE(spi, mc33xs2410_spi_id); From 1a4920940ebfd8d907858abd8f8dd09b13752946 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= Date: Wed, 17 Jun 2026 11:41:50 +0200 Subject: [PATCH 02/18] pwm: Use named initializers for platform_device_id arrays MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Named initializers are better readable and more robust to changes of the struct definition. This robustness is relevant for a planned change to struct platform_device_id replacing .driver_data by an anonymous union. While touching these arrays drop a comma after a list terminator. Signed-off-by: Uwe Kleine-König (The Capable Hub) Reviewed-by: Laurent Pinchart Link: https://patch.msgid.link/b515eb1644e793d019163fd2a717d3fccef857f5.1781689255.git.u.kleine-koenig@baylibre.com Signed-off-by: Uwe Kleine-König --- drivers/pwm/pwm-adp5585.c | 4 ++-- drivers/pwm/pwm-pxa.c | 12 ++++++------ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/pwm/pwm-adp5585.c b/drivers/pwm/pwm-adp5585.c index 806f8d79b0d7..f4aa74b44ed2 100644 --- a/drivers/pwm/pwm-adp5585.c +++ b/drivers/pwm/pwm-adp5585.c @@ -203,8 +203,8 @@ static const struct adp5585_pwm_chip adp5589_pwm_chip_info = { }; static const struct platform_device_id adp5585_pwm_id_table[] = { - { "adp5585-pwm", (kernel_ulong_t)&adp5585_pwm_chip_info }, - { "adp5589-pwm", (kernel_ulong_t)&adp5589_pwm_chip_info }, + { .name = "adp5585-pwm", .driver_data = (kernel_ulong_t)&adp5585_pwm_chip_info }, + { .name = "adp5589-pwm", .driver_data = (kernel_ulong_t)&adp5589_pwm_chip_info }, { /* Sentinel */ } }; MODULE_DEVICE_TABLE(platform, adp5585_pwm_id_table); diff --git a/drivers/pwm/pwm-pxa.c b/drivers/pwm/pwm-pxa.c index 80d2fa10919f..b844bb2dd92e 100644 --- a/drivers/pwm/pwm-pxa.c +++ b/drivers/pwm/pwm-pxa.c @@ -32,12 +32,12 @@ #define HAS_SECONDARY_PWM 0x10 static const struct platform_device_id pwm_id_table[] = { - /* PWM has_secondary_pwm? */ - { "pxa25x-pwm", 0 }, - { "pxa27x-pwm", HAS_SECONDARY_PWM }, - { "pxa168-pwm", 0 }, - { "pxa910-pwm", 0 }, - { }, + /* PWM has_secondary_pwm? */ + { .name = "pxa25x-pwm", .driver_data = 0 }, + { .name = "pxa27x-pwm", .driver_data = HAS_SECONDARY_PWM }, + { .name = "pxa168-pwm", .driver_data = 0 }, + { .name = "pxa910-pwm", .driver_data = 0 }, + { } }; MODULE_DEVICE_TABLE(platform, pwm_id_table); From 7945aa98486f0ed3f7f53592f159039d443bd686 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= Date: Sun, 5 Jul 2026 10:39:08 +0200 Subject: [PATCH 03/18] pwm: pxa: Depend on OF and simplify accordingly MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SoCs that this driver actually works on all imply OF already. (ARM selects USE_OF unless some archs are enabled that cannot be selected together with ARCH_PXA or ARCH_MMP, ARM64 and RISCV select OF.) With OF known to be enabled a few conditionals in the driver can be simplified. Signed-off-by: Uwe Kleine-König (The Capable Hub) Link: https://patch.msgid.link/20260705083910.3502207-2-u.kleine-koenig@baylibre.com Signed-off-by: Uwe Kleine-König --- drivers/pwm/Kconfig | 2 +- drivers/pwm/pwm-pxa.c | 10 ++-------- 2 files changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index e8886a9b64d9..729776086879 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -569,7 +569,7 @@ config PWM_PCA9685 config PWM_PXA tristate "PXA PWM support" depends on ARCH_PXA || ARCH_MMP || ARCH_SPACEMIT || COMPILE_TEST - depends on HAS_IOMEM + depends on HAS_IOMEM && OF help Generic PWM framework driver for PXA. diff --git a/drivers/pwm/pwm-pxa.c b/drivers/pwm/pwm-pxa.c index b844bb2dd92e..157735d0d054 100644 --- a/drivers/pwm/pwm-pxa.c +++ b/drivers/pwm/pwm-pxa.c @@ -137,7 +137,6 @@ static const struct pwm_ops pxa_pwm_ops = { .apply = pxa_pwm_apply, }; -#ifdef CONFIG_OF /* * Device tree users must create one device instance for each PWM channel. * Hence we dispense with the HAS_SECONDARY_PWM and "tell" the original driver @@ -152,9 +151,6 @@ static const struct of_device_id pwm_of_match[] = { { } }; MODULE_DEVICE_TABLE(of, pwm_of_match); -#else -#define pwm_of_match NULL -#endif static int pwm_probe(struct platform_device *pdev) { @@ -166,7 +162,7 @@ static int pwm_probe(struct platform_device *pdev) struct reset_control *rst; int ret = 0; - if (IS_ENABLED(CONFIG_OF) && id == NULL) + if (id == NULL) id = of_device_get_match_data(dev); if (id == NULL) @@ -192,9 +188,7 @@ static int pwm_probe(struct platform_device *pdev) return PTR_ERR(rst); chip->ops = &pxa_pwm_ops; - - if (IS_ENABLED(CONFIG_OF)) - chip->of_xlate = of_pwm_single_xlate; + chip->of_xlate = of_pwm_single_xlate; pc->mmio_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(pc->mmio_base)) From 97ba86ba8d5f84136bbe1e1824f0a28e1c39b02f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= Date: Sun, 5 Jul 2026 17:14:13 +0200 Subject: [PATCH 04/18] pwm: pca9685: Drop unused assignment of acpi_device_id driver data MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The driver explicitly set the .driver_data member of struct acpi_device_id to zero without relying on that value. Drop this unused assignment. This patch doesn't modify the compiled array, only its representation in source form benefits. Signed-off-by: Uwe Kleine-König (The Capable Hub) Link: https://patch.msgid.link/7e5fbc8c03527d50fd78b2b89ff22843ea1b84e6.1783263835.git.ukleinek@kernel.org Signed-off-by: Uwe Kleine-König --- drivers/pwm/pwm-pca9685.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-pca9685.c b/drivers/pwm/pwm-pca9685.c index a02255a64ea8..617a74de68c7 100644 --- a/drivers/pwm/pwm-pca9685.c +++ b/drivers/pwm/pwm-pca9685.c @@ -544,7 +544,7 @@ static const struct i2c_device_id pca9685_id[] = { MODULE_DEVICE_TABLE(i2c, pca9685_id); static const struct acpi_device_id pca9685_acpi_ids[] = { - { "INT3492", 0 }, + { "INT3492" }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(acpi, pca9685_acpi_ids); From 5ab2c51c888f6b3a351b40fdfe6c381e2b972ab6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= Date: Sun, 5 Jul 2026 17:14:14 +0200 Subject: [PATCH 05/18] pwm: Use named initializers for arrays of acpi_device_id MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit While being less compact, using named initializers allows to more easily see which members of the structs are assigned which value without having to lookup the declaration of the struct. And it's also more robust against changes to the struct definition. The mentioned robustness is relevant for a planned change to struct acpi_device_id that replaces .driver_data by an anonymous union. This patch doesn't modify the compiled arrays, only their representation in source form benefits. Signed-off-by: Uwe Kleine-König (The Capable Hub) Link: https://patch.msgid.link/1a03da9625e1e6bf2befa13c64525e2dfa2243e7.1783263835.git.ukleinek@kernel.org Signed-off-by: Uwe Kleine-König --- drivers/pwm/pwm-loongson.c | 2 +- drivers/pwm/pwm-lpss-platform.c | 8 ++++---- drivers/pwm/pwm-pca9685.c | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pwm/pwm-loongson.c b/drivers/pwm/pwm-loongson.c index 31a57edecfd0..f2fb35b7af2b 100644 --- a/drivers/pwm/pwm-loongson.c +++ b/drivers/pwm/pwm-loongson.c @@ -269,7 +269,7 @@ static const struct of_device_id pwm_loongson_of_ids[] = { MODULE_DEVICE_TABLE(of, pwm_loongson_of_ids); static const struct acpi_device_id pwm_loongson_acpi_ids[] = { - { "LOON0006" }, + { .id = "LOON0006" }, { } }; MODULE_DEVICE_TABLE(acpi, pwm_loongson_acpi_ids); diff --git a/drivers/pwm/pwm-lpss-platform.c b/drivers/pwm/pwm-lpss-platform.c index 653ec9d0c8bf..0d4f8bf04e9f 100644 --- a/drivers/pwm/pwm-lpss-platform.c +++ b/drivers/pwm/pwm-lpss-platform.c @@ -59,10 +59,10 @@ static int pwm_lpss_probe_platform(struct platform_device *pdev) } static const struct acpi_device_id pwm_lpss_acpi_match[] = { - { "80860F09", (unsigned long)&pwm_lpss_byt_info }, - { "80862288", (unsigned long)&pwm_lpss_bsw_info }, - { "80862289", (unsigned long)&pwm_lpss_bsw_info }, - { "80865AC8", (unsigned long)&pwm_lpss_bxt_info }, + { .id = "80860F09", .driver_data = (unsigned long)&pwm_lpss_byt_info }, + { .id = "80862288", .driver_data = (unsigned long)&pwm_lpss_bsw_info }, + { .id = "80862289", .driver_data = (unsigned long)&pwm_lpss_bsw_info }, + { .id = "80865AC8", .driver_data = (unsigned long)&pwm_lpss_bxt_info }, { }, }; MODULE_DEVICE_TABLE(acpi, pwm_lpss_acpi_match); diff --git a/drivers/pwm/pwm-pca9685.c b/drivers/pwm/pwm-pca9685.c index 617a74de68c7..0982ba4f566c 100644 --- a/drivers/pwm/pwm-pca9685.c +++ b/drivers/pwm/pwm-pca9685.c @@ -544,7 +544,7 @@ static const struct i2c_device_id pca9685_id[] = { MODULE_DEVICE_TABLE(i2c, pca9685_id); static const struct acpi_device_id pca9685_acpi_ids[] = { - { "INT3492" }, + { .id = "INT3492" }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(acpi, pca9685_acpi_ids); From 8dd1524f69c1fde82bd20a4607ceabbd8b5403c4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= Date: Sun, 5 Jul 2026 17:14:15 +0200 Subject: [PATCH 06/18] pwm: Unify coding style of acpi_device_id arrays MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use no comma after the array terminator. Signed-off-by: Uwe Kleine-König (The Capable Hub) Link: https://patch.msgid.link/7a4d998e12ac6fa084d1ee29ecb29d51ab7a5e5c.1783263835.git.ukleinek@kernel.org Signed-off-by: Uwe Kleine-König --- drivers/pwm/pwm-lpss-platform.c | 2 +- drivers/pwm/pwm-pca9685.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-lpss-platform.c b/drivers/pwm/pwm-lpss-platform.c index 0d4f8bf04e9f..529daec1cd3f 100644 --- a/drivers/pwm/pwm-lpss-platform.c +++ b/drivers/pwm/pwm-lpss-platform.c @@ -63,7 +63,7 @@ static const struct acpi_device_id pwm_lpss_acpi_match[] = { { .id = "80862288", .driver_data = (unsigned long)&pwm_lpss_bsw_info }, { .id = "80862289", .driver_data = (unsigned long)&pwm_lpss_bsw_info }, { .id = "80865AC8", .driver_data = (unsigned long)&pwm_lpss_bxt_info }, - { }, + { } }; MODULE_DEVICE_TABLE(acpi, pwm_lpss_acpi_match); diff --git a/drivers/pwm/pwm-pca9685.c b/drivers/pwm/pwm-pca9685.c index 0982ba4f566c..8babd29f161c 100644 --- a/drivers/pwm/pwm-pca9685.c +++ b/drivers/pwm/pwm-pca9685.c @@ -545,7 +545,7 @@ MODULE_DEVICE_TABLE(i2c, pca9685_id); static const struct acpi_device_id pca9685_acpi_ids[] = { { .id = "INT3492" }, - { /* sentinel */ }, + { /* sentinel */ } }; MODULE_DEVICE_TABLE(acpi, pca9685_acpi_ids); From eff04f2a6b5374db0ac4959a3d1827418d2170c7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= Date: Sun, 5 Jul 2026 17:14:16 +0200 Subject: [PATCH 07/18] pwm: Unify coding style of of_device_id arrays MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - Use a single space in a of_device_id array terminator; A single space after the opening { and before the closing } in non-empty initializers; - No comma after an array terminator; - Also no trailing comma after a named initializer if (and only if) the closing } is on the same line; Signed-off-by: Uwe Kleine-König (The Capable Hub) Reviewed-by: Geert Uytterhoeven # renesas Reviewed-by: Chen Wang Link: https://patch.msgid.link/20de6cd60c2938aad2d21397b92742849418ab1b.1783263835.git.ukleinek@kernel.org Signed-off-by: Uwe Kleine-König --- drivers/pwm/pwm-apple.c | 2 +- drivers/pwm/pwm-argon-fan-hat.c | 2 +- drivers/pwm/pwm-atmel-hlcdc.c | 15 ++++++--------- drivers/pwm/pwm-atmel-tcb.c | 6 +++--- drivers/pwm/pwm-atmel.c | 3 +-- drivers/pwm/pwm-bcm-iproc.c | 2 +- drivers/pwm/pwm-bcm-kona.c | 2 +- drivers/pwm/pwm-bcm2835.c | 2 +- drivers/pwm/pwm-berlin.c | 2 +- drivers/pwm/pwm-brcmstb.c | 2 +- drivers/pwm/pwm-clk.c | 2 +- drivers/pwm/pwm-clps711x.c | 2 +- drivers/pwm/pwm-cros-ec.c | 2 +- drivers/pwm/pwm-hibvt.c | 2 +- drivers/pwm/pwm-imx-tpm.c | 2 +- drivers/pwm/pwm-imx1.c | 2 +- drivers/pwm/pwm-imx27.c | 2 +- drivers/pwm/pwm-ipq.c | 4 ++-- drivers/pwm/pwm-jz4740.c | 2 +- drivers/pwm/pwm-lp3943.c | 2 +- drivers/pwm/pwm-lpc18xx-sct.c | 2 +- drivers/pwm/pwm-lpc32xx.c | 2 +- drivers/pwm/pwm-mediatek.c | 2 +- drivers/pwm/pwm-meson.c | 9 ++++----- drivers/pwm/pwm-mtk-disp.c | 8 ++++---- drivers/pwm/pwm-mxs.c | 2 +- drivers/pwm/pwm-omap-dmtimer.c | 4 ++-- drivers/pwm/pwm-pca9685.c | 2 +- drivers/pwm/pwm-pxa.c | 8 ++++---- drivers/pwm/pwm-raspberrypi-poe.c | 2 +- drivers/pwm/pwm-rcar.c | 4 ++-- drivers/pwm/pwm-renesas-tpu.c | 10 +++++----- drivers/pwm/pwm-rockchip.c | 8 ++++---- drivers/pwm/pwm-rzg2l-gpt.c | 2 +- drivers/pwm/pwm-samsung.c | 2 +- drivers/pwm/pwm-sifive.c | 2 +- drivers/pwm/pwm-sl28cpld.c | 2 +- drivers/pwm/pwm-sophgo-sg2042.c | 7 +++---- drivers/pwm/pwm-sprd.c | 4 ++-- drivers/pwm/pwm-sti.c | 2 +- drivers/pwm/pwm-stm32-lp.c | 4 ++-- drivers/pwm/pwm-stm32.c | 6 +++--- drivers/pwm/pwm-sun4i.c | 2 +- drivers/pwm/pwm-sunplus.c | 4 ++-- drivers/pwm/pwm-tiecap.c | 6 +++--- drivers/pwm/pwm-tiehrpwm.c | 2 +- drivers/pwm/pwm-twl-led.c | 2 +- drivers/pwm/pwm-twl.c | 2 +- drivers/pwm/pwm-visconti.c | 2 +- drivers/pwm/pwm-vt8500.c | 2 +- drivers/pwm/pwm-xilinx.c | 4 ++-- 51 files changed, 87 insertions(+), 93 deletions(-) diff --git a/drivers/pwm/pwm-apple.c b/drivers/pwm/pwm-apple.c index 6e58aca2f13c..3c8ae739ffdb 100644 --- a/drivers/pwm/pwm-apple.c +++ b/drivers/pwm/pwm-apple.c @@ -142,7 +142,7 @@ static int apple_pwm_probe(struct platform_device *pdev) static const struct of_device_id apple_pwm_of_match[] = { { .compatible = "apple,s5l-fpwm" }, - {} + { } }; MODULE_DEVICE_TABLE(of, apple_pwm_of_match); diff --git a/drivers/pwm/pwm-argon-fan-hat.c b/drivers/pwm/pwm-argon-fan-hat.c index 2c59bd142d40..b480663e87d5 100644 --- a/drivers/pwm/pwm-argon-fan-hat.c +++ b/drivers/pwm/pwm-argon-fan-hat.c @@ -89,7 +89,7 @@ static int argon_fan_hat_i2c_probe(struct i2c_client *i2c) static const struct of_device_id argon_fan_hat_dt_ids[] = { { .compatible = "argon40,fan-hat" }, - { }, + { } }; MODULE_DEVICE_TABLE(of, argon_fan_hat_dt_ids); diff --git a/drivers/pwm/pwm-atmel-hlcdc.c b/drivers/pwm/pwm-atmel-hlcdc.c index 387a0d1fa4f2..1ba2c9a049b9 100644 --- a/drivers/pwm/pwm-atmel-hlcdc.c +++ b/drivers/pwm/pwm-atmel-hlcdc.c @@ -217,23 +217,20 @@ static const struct of_device_id atmel_hlcdc_dt_ids[] = { .compatible = "atmel,at91sam9n12-hlcdc", /* 9n12 has same errata as 9x5 HLCDC PWM */ .data = &atmel_hlcdc_pwm_at91sam9x5_errata, - }, - { + }, { .compatible = "atmel,at91sam9x5-hlcdc", .data = &atmel_hlcdc_pwm_at91sam9x5_errata, - }, - { + }, { .compatible = "atmel,sama5d2-hlcdc", - }, - { + }, { .compatible = "atmel,sama5d3-hlcdc", .data = &atmel_hlcdc_pwm_sama5d3_errata, - }, - { + }, { .compatible = "atmel,sama5d4-hlcdc", .data = &atmel_hlcdc_pwm_sama5d3_errata, + }, { + .compatible = "microchip,sam9x60-hlcdc", }, - { .compatible = "microchip,sam9x60-hlcdc", }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, atmel_hlcdc_dt_ids); diff --git a/drivers/pwm/pwm-atmel-tcb.c b/drivers/pwm/pwm-atmel-tcb.c index a765ef279b51..f74a42d75b81 100644 --- a/drivers/pwm/pwm-atmel-tcb.c +++ b/drivers/pwm/pwm-atmel-tcb.c @@ -374,9 +374,9 @@ static struct atmel_tcb_config tcb_sama5d2_config = { }; static const struct of_device_id atmel_tcb_of_match[] = { - { .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, }, - { .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, }, - { .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, }, + { .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config }, + { .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config }, + { .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config }, { /* sentinel */ } }; diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c index 06d22d0f7b26..86918523d821 100644 --- a/drivers/pwm/pwm-atmel.c +++ b/drivers/pwm/pwm-atmel.c @@ -441,9 +441,8 @@ static const struct of_device_id atmel_pwm_dt_ids[] = { }, { .compatible = "microchip,sam9x60-pwm", .data = &mchp_sam9x60_pwm_data, - }, { - /* sentinel */ }, + { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids); diff --git a/drivers/pwm/pwm-bcm-iproc.c b/drivers/pwm/pwm-bcm-iproc.c index f4c9f10e490e..dc1e792b1e08 100644 --- a/drivers/pwm/pwm-bcm-iproc.c +++ b/drivers/pwm/pwm-bcm-iproc.c @@ -230,7 +230,7 @@ static int iproc_pwmc_probe(struct platform_device *pdev) static const struct of_device_id bcm_iproc_pwmc_dt[] = { { .compatible = "brcm,iproc-pwm" }, - { }, + { } }; MODULE_DEVICE_TABLE(of, bcm_iproc_pwmc_dt); diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c index 022c078aae84..ecfa3e3707f4 100644 --- a/drivers/pwm/pwm-bcm-kona.c +++ b/drivers/pwm/pwm-bcm-kona.c @@ -319,7 +319,7 @@ static int kona_pwmc_probe(struct platform_device *pdev) static const struct of_device_id bcm_kona_pwmc_dt[] = { { .compatible = "brcm,kona-pwm" }, - { }, + { } }; MODULE_DEVICE_TABLE(of, bcm_kona_pwmc_dt); diff --git a/drivers/pwm/pwm-bcm2835.c b/drivers/pwm/pwm-bcm2835.c index 532903da521f..a4fbf9cfc6f7 100644 --- a/drivers/pwm/pwm-bcm2835.c +++ b/drivers/pwm/pwm-bcm2835.c @@ -165,7 +165,7 @@ static DEFINE_SIMPLE_DEV_PM_OPS(bcm2835_pwm_pm_ops, bcm2835_pwm_suspend, bcm2835_pwm_resume); static const struct of_device_id bcm2835_pwm_of_match[] = { - { .compatible = "brcm,bcm2835-pwm", }, + { .compatible = "brcm,bcm2835-pwm" }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, bcm2835_pwm_of_match); diff --git a/drivers/pwm/pwm-berlin.c b/drivers/pwm/pwm-berlin.c index 858d36991374..5db4d41a7442 100644 --- a/drivers/pwm/pwm-berlin.c +++ b/drivers/pwm/pwm-berlin.c @@ -191,7 +191,7 @@ static const struct pwm_ops berlin_pwm_ops = { static const struct of_device_id berlin_pwm_match[] = { { .compatible = "marvell,berlin-pwm" }, - { }, + { } }; MODULE_DEVICE_TABLE(of, berlin_pwm_match); diff --git a/drivers/pwm/pwm-brcmstb.c b/drivers/pwm/pwm-brcmstb.c index 82d27d07ba91..790ef7ffbbe5 100644 --- a/drivers/pwm/pwm-brcmstb.c +++ b/drivers/pwm/pwm-brcmstb.c @@ -222,7 +222,7 @@ static const struct pwm_ops brcmstb_pwm_ops = { }; static const struct of_device_id brcmstb_pwm_of_match[] = { - { .compatible = "brcm,bcm7038-pwm", }, + { .compatible = "brcm,bcm7038-pwm" }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, brcmstb_pwm_of_match); diff --git a/drivers/pwm/pwm-clk.c b/drivers/pwm/pwm-clk.c index f8f5af57acba..1907f2f10e5c 100644 --- a/drivers/pwm/pwm-clk.c +++ b/drivers/pwm/pwm-clk.c @@ -119,7 +119,7 @@ static void pwm_clk_remove(struct platform_device *pdev) } static const struct of_device_id pwm_clk_dt_ids[] = { - { .compatible = "clk-pwm", }, + { .compatible = "clk-pwm" }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, pwm_clk_dt_ids); diff --git a/drivers/pwm/pwm-clps711x.c b/drivers/pwm/pwm-clps711x.c index 2c92ce754872..1ce12ee0329b 100644 --- a/drivers/pwm/pwm-clps711x.c +++ b/drivers/pwm/pwm-clps711x.c @@ -91,7 +91,7 @@ static int clps711x_pwm_probe(struct platform_device *pdev) } static const struct of_device_id clps711x_pwm_dt_ids[] = { - { .compatible = "cirrus,ep7209-pwm", }, + { .compatible = "cirrus,ep7209-pwm" }, { } }; MODULE_DEVICE_TABLE(of, clps711x_pwm_dt_ids); diff --git a/drivers/pwm/pwm-cros-ec.c b/drivers/pwm/pwm-cros-ec.c index 67cfa17f58e0..08a24a45c76d 100644 --- a/drivers/pwm/pwm-cros-ec.c +++ b/drivers/pwm/pwm-cros-ec.c @@ -267,7 +267,7 @@ static int cros_ec_pwm_probe(struct platform_device *pdev) static const struct of_device_id cros_ec_pwm_of_match[] = { { .compatible = "google,cros-ec-pwm" }, { .compatible = "google,cros-ec-pwm-type" }, - {}, + { } }; MODULE_DEVICE_TABLE(of, cros_ec_pwm_of_match); #endif diff --git a/drivers/pwm/pwm-hibvt.c b/drivers/pwm/pwm-hibvt.c index e02ee6383dbc..29ad8d0b5536 100644 --- a/drivers/pwm/pwm-hibvt.c +++ b/drivers/pwm/pwm-hibvt.c @@ -266,7 +266,7 @@ static const struct of_device_id hibvt_pwm_of_match[] = { .data = &hi3559v100_shub_soc_info }, { .compatible = "hisilicon,hi3559v100-pwm", .data = &hi3559v100_soc_info }, - { } + { } }; MODULE_DEVICE_TABLE(of, hibvt_pwm_of_match); diff --git a/drivers/pwm/pwm-imx-tpm.c b/drivers/pwm/pwm-imx-tpm.c index 80fdb3303400..c20753a36d6d 100644 --- a/drivers/pwm/pwm-imx-tpm.c +++ b/drivers/pwm/pwm-imx-tpm.c @@ -442,7 +442,7 @@ static DEFINE_SIMPLE_DEV_PM_OPS(imx_tpm_pwm_pm, pwm_imx_tpm_suspend, pwm_imx_tpm_resume); static const struct of_device_id imx_tpm_pwm_dt_ids[] = { - { .compatible = "fsl,imx7ulp-pwm", }, + { .compatible = "fsl,imx7ulp-pwm" }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, imx_tpm_pwm_dt_ids); diff --git a/drivers/pwm/pwm-imx1.c b/drivers/pwm/pwm-imx1.c index d5535d208005..075d46180dff 100644 --- a/drivers/pwm/pwm-imx1.c +++ b/drivers/pwm/pwm-imx1.c @@ -151,7 +151,7 @@ static const struct pwm_ops pwm_imx1_ops = { }; static const struct of_device_id pwm_imx1_dt_ids[] = { - { .compatible = "fsl,imx1-pwm", }, + { .compatible = "fsl,imx1-pwm" }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, pwm_imx1_dt_ids); diff --git a/drivers/pwm/pwm-imx27.c b/drivers/pwm/pwm-imx27.c index c8b801fcb525..7c1ad15008d2 100644 --- a/drivers/pwm/pwm-imx27.c +++ b/drivers/pwm/pwm-imx27.c @@ -378,7 +378,7 @@ static const struct pwm_ops pwm_imx27_ops = { }; static const struct of_device_id pwm_imx27_dt_ids[] = { - { .compatible = "fsl,imx27-pwm", }, + { .compatible = "fsl,imx27-pwm" }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, pwm_imx27_dt_ids); diff --git a/drivers/pwm/pwm-ipq.c b/drivers/pwm/pwm-ipq.c index c53373948136..6b7aec566f7e 100644 --- a/drivers/pwm/pwm-ipq.c +++ b/drivers/pwm/pwm-ipq.c @@ -245,8 +245,8 @@ static int ipq_pwm_probe(struct platform_device *pdev) } static const struct of_device_id pwm_ipq_dt_match[] = { - { .compatible = "qcom,ipq6018-pwm", }, - {} + { .compatible = "qcom,ipq6018-pwm" }, + { } }; MODULE_DEVICE_TABLE(of, pwm_ipq_dt_match); diff --git a/drivers/pwm/pwm-jz4740.c b/drivers/pwm/pwm-jz4740.c index e0b5966fc7fe..0db1474c7c8c 100644 --- a/drivers/pwm/pwm-jz4740.c +++ b/drivers/pwm/pwm-jz4740.c @@ -261,7 +261,7 @@ static const struct of_device_id jz4740_pwm_dt_ids[] = { { .compatible = "ingenic,jz4740-pwm", .data = &jz4740_soc_info }, { .compatible = "ingenic,jz4725b-pwm", .data = &jz4725b_soc_info }, { .compatible = "ingenic,x1000-pwm", .data = &x1000_soc_info }, - {}, + { } }; MODULE_DEVICE_TABLE(of, jz4740_pwm_dt_ids); diff --git a/drivers/pwm/pwm-lp3943.c b/drivers/pwm/pwm-lp3943.c index 90b0733c00c1..10537e74be28 100644 --- a/drivers/pwm/pwm-lp3943.c +++ b/drivers/pwm/pwm-lp3943.c @@ -296,7 +296,7 @@ static int lp3943_pwm_probe(struct platform_device *pdev) #ifdef CONFIG_OF static const struct of_device_id lp3943_pwm_of_match[] = { - { .compatible = "ti,lp3943-pwm", }, + { .compatible = "ti,lp3943-pwm" }, { } }; MODULE_DEVICE_TABLE(of, lp3943_pwm_of_match); diff --git a/drivers/pwm/pwm-lpc18xx-sct.c b/drivers/pwm/pwm-lpc18xx-sct.c index 1e614b2a0227..4a1950635850 100644 --- a/drivers/pwm/pwm-lpc18xx-sct.c +++ b/drivers/pwm/pwm-lpc18xx-sct.c @@ -330,7 +330,7 @@ static const struct pwm_ops lpc18xx_pwm_ops = { static const struct of_device_id lpc18xx_pwm_of_match[] = { { .compatible = "nxp,lpc1850-sct-pwm" }, - {} + { } }; MODULE_DEVICE_TABLE(of, lpc18xx_pwm_of_match); diff --git a/drivers/pwm/pwm-lpc32xx.c b/drivers/pwm/pwm-lpc32xx.c index c748537e57d1..19ec53648f40 100644 --- a/drivers/pwm/pwm-lpc32xx.c +++ b/drivers/pwm/pwm-lpc32xx.c @@ -155,7 +155,7 @@ static int lpc32xx_pwm_probe(struct platform_device *pdev) } static const struct of_device_id lpc32xx_pwm_dt_ids[] = { - { .compatible = "nxp,lpc3220-pwm", }, + { .compatible = "nxp,lpc3220-pwm" }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, lpc32xx_pwm_dt_ids); diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c index 992137a27750..0bb49be657b7 100644 --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c @@ -627,7 +627,7 @@ static const struct of_device_id pwm_mediatek_of_match[] = { { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data }, { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data }, { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data }, - { }, + { } }; MODULE_DEVICE_TABLE(of, pwm_mediatek_of_match); diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index 8c6bf3d49753..20e6cd07127c 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -596,15 +596,14 @@ static const struct of_device_id meson_pwm_matches[] = { { .compatible = "amlogic,meson8-pwm-v2", .data = &pwm_meson8_v2_data - }, - { + }, { .compatible = "amlogic,meson-axg-pwm-v2", .data = &pwm_meson_axg_v2_data - }, - { + }, { .compatible = "amlogic,meson-g12-pwm-v2", .data = &pwm_meson_axg_v2_data }, + /* The following compatibles are obsolete */ { .compatible = "amlogic,meson8b-pwm", @@ -642,7 +641,7 @@ static const struct of_device_id meson_pwm_matches[] = { .compatible = "amlogic,meson-s4-pwm", .data = &pwm_s4_data }, - {}, + { } }; MODULE_DEVICE_TABLE(of, meson_pwm_matches); diff --git a/drivers/pwm/pwm-mtk-disp.c b/drivers/pwm/pwm-mtk-disp.c index bafd6b6195f6..b5409e15dac8 100644 --- a/drivers/pwm/pwm-mtk-disp.c +++ b/drivers/pwm/pwm-mtk-disp.c @@ -295,10 +295,10 @@ static const struct mtk_pwm_data mt8183_pwm_data = { }; static const struct of_device_id mtk_disp_pwm_of_match[] = { - { .compatible = "mediatek,mt2701-disp-pwm", .data = &mt2701_pwm_data}, - { .compatible = "mediatek,mt6595-disp-pwm", .data = &mt8173_pwm_data}, - { .compatible = "mediatek,mt8173-disp-pwm", .data = &mt8173_pwm_data}, - { .compatible = "mediatek,mt8183-disp-pwm", .data = &mt8183_pwm_data}, + { .compatible = "mediatek,mt2701-disp-pwm", .data = &mt2701_pwm_data }, + { .compatible = "mediatek,mt6595-disp-pwm", .data = &mt8173_pwm_data }, + { .compatible = "mediatek,mt8173-disp-pwm", .data = &mt8173_pwm_data }, + { .compatible = "mediatek,mt8183-disp-pwm", .data = &mt8183_pwm_data }, { } }; MODULE_DEVICE_TABLE(of, mtk_disp_pwm_of_match); diff --git a/drivers/pwm/pwm-mxs.c b/drivers/pwm/pwm-mxs.c index 8cad214b1c29..e1a3df6549fc 100644 --- a/drivers/pwm/pwm-mxs.c +++ b/drivers/pwm/pwm-mxs.c @@ -163,7 +163,7 @@ static int mxs_pwm_probe(struct platform_device *pdev) } static const struct of_device_id mxs_pwm_dt_ids[] = { - { .compatible = "fsl,imx23-pwm", }, + { .compatible = "fsl,imx23-pwm" }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mxs_pwm_dt_ids); diff --git a/drivers/pwm/pwm-omap-dmtimer.c b/drivers/pwm/pwm-omap-dmtimer.c index 1858a77401f8..51830a87275c 100644 --- a/drivers/pwm/pwm-omap-dmtimer.c +++ b/drivers/pwm/pwm-omap-dmtimer.c @@ -444,8 +444,8 @@ static void pwm_omap_dmtimer_remove(struct platform_device *pdev) } static const struct of_device_id pwm_omap_dmtimer_of_match[] = { - {.compatible = "ti,omap-dmtimer-pwm"}, - {} + { .compatible = "ti,omap-dmtimer-pwm" }, + { } }; MODULE_DEVICE_TABLE(of, pwm_omap_dmtimer_of_match); diff --git a/drivers/pwm/pwm-pca9685.c b/drivers/pwm/pwm-pca9685.c index 8babd29f161c..a2792b803643 100644 --- a/drivers/pwm/pwm-pca9685.c +++ b/drivers/pwm/pwm-pca9685.c @@ -550,7 +550,7 @@ static const struct acpi_device_id pca9685_acpi_ids[] = { MODULE_DEVICE_TABLE(acpi, pca9685_acpi_ids); static const struct of_device_id pca9685_dt_ids[] = { - { .compatible = "nxp,pca9685-pwm", }, + { .compatible = "nxp,pca9685-pwm" }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, pca9685_dt_ids); diff --git a/drivers/pwm/pwm-pxa.c b/drivers/pwm/pwm-pxa.c index 157735d0d054..07f5e09f1b1a 100644 --- a/drivers/pwm/pwm-pxa.c +++ b/drivers/pwm/pwm-pxa.c @@ -144,10 +144,10 @@ static const struct pwm_ops pxa_pwm_ops = { * supported identically. */ static const struct of_device_id pwm_of_match[] = { - { .compatible = "marvell,pxa250-pwm", .data = &pwm_id_table[0]}, - { .compatible = "marvell,pxa270-pwm", .data = &pwm_id_table[0]}, - { .compatible = "marvell,pxa168-pwm", .data = &pwm_id_table[0]}, - { .compatible = "marvell,pxa910-pwm", .data = &pwm_id_table[0]}, + { .compatible = "marvell,pxa250-pwm", .data = &pwm_id_table[0] }, + { .compatible = "marvell,pxa270-pwm", .data = &pwm_id_table[0] }, + { .compatible = "marvell,pxa168-pwm", .data = &pwm_id_table[0] }, + { .compatible = "marvell,pxa910-pwm", .data = &pwm_id_table[0] }, { } }; MODULE_DEVICE_TABLE(of, pwm_of_match); diff --git a/drivers/pwm/pwm-raspberrypi-poe.c b/drivers/pwm/pwm-raspberrypi-poe.c index 8921e7ea2cea..7cea6561c730 100644 --- a/drivers/pwm/pwm-raspberrypi-poe.c +++ b/drivers/pwm/pwm-raspberrypi-poe.c @@ -177,7 +177,7 @@ static int raspberrypi_pwm_probe(struct platform_device *pdev) } static const struct of_device_id raspberrypi_pwm_of_match[] = { - { .compatible = "raspberrypi,firmware-poe-pwm", }, + { .compatible = "raspberrypi,firmware-poe-pwm" }, { } }; MODULE_DEVICE_TABLE(of, raspberrypi_pwm_of_match); diff --git a/drivers/pwm/pwm-rcar.c b/drivers/pwm/pwm-rcar.c index 578dbdd2d5a7..1733cd700693 100644 --- a/drivers/pwm/pwm-rcar.c +++ b/drivers/pwm/pwm-rcar.c @@ -248,8 +248,8 @@ static void rcar_pwm_remove(struct platform_device *pdev) } static const struct of_device_id rcar_pwm_of_table[] = { - { .compatible = "renesas,pwm-rcar", }, - { }, + { .compatible = "renesas,pwm-rcar" }, + { } }; MODULE_DEVICE_TABLE(of, rcar_pwm_of_table); diff --git a/drivers/pwm/pwm-renesas-tpu.c b/drivers/pwm/pwm-renesas-tpu.c index 2196080b4177..140fd0bcb93f 100644 --- a/drivers/pwm/pwm-renesas-tpu.c +++ b/drivers/pwm/pwm-renesas-tpu.c @@ -479,11 +479,11 @@ static int tpu_probe(struct platform_device *pdev) #ifdef CONFIG_OF static const struct of_device_id tpu_of_table[] = { - { .compatible = "renesas,tpu-r8a73a4", }, - { .compatible = "renesas,tpu-r8a7740", }, - { .compatible = "renesas,tpu-r8a7790", }, - { .compatible = "renesas,tpu", }, - { }, + { .compatible = "renesas,tpu-r8a73a4" }, + { .compatible = "renesas,tpu-r8a7740" }, + { .compatible = "renesas,tpu-r8a7790" }, + { .compatible = "renesas,tpu" }, + { } }; MODULE_DEVICE_TABLE(of, tpu_of_table); diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm-rockchip.c index 67b85bdb491b..050ca8aad0ca 100644 --- a/drivers/pwm/pwm-rockchip.c +++ b/drivers/pwm/pwm-rockchip.c @@ -292,10 +292,10 @@ static const struct rockchip_pwm_data pwm_data_v3 = { }; static const struct of_device_id rockchip_pwm_dt_ids[] = { - { .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1}, - { .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2}, - { .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop}, - { .compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v3}, + { .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1 }, + { .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2 }, + { .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop }, + { .compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v3 }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids); diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index dfa1d11a48a8..ac8399b96ad1 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -437,7 +437,7 @@ static int rzg2l_gpt_probe(struct platform_device *pdev) } static const struct of_device_id rzg2l_gpt_of_table[] = { - { .compatible = "renesas,rzg2l-gpt", }, + { .compatible = "renesas,rzg2l-gpt" }, { /* Sentinel */ } }; MODULE_DEVICE_TABLE(of, rzg2l_gpt_of_table); diff --git a/drivers/pwm/pwm-samsung.c b/drivers/pwm/pwm-samsung.c index 951b38ff5f8e..331e81f1594a 100644 --- a/drivers/pwm/pwm-samsung.c +++ b/drivers/pwm/pwm-samsung.c @@ -501,7 +501,7 @@ static const struct of_device_id samsung_pwm_matches[] = { { .compatible = "samsung,s5p6440-pwm", .data = &s5p64x0_variant }, { .compatible = "samsung,s5pc100-pwm", .data = &s5pc100_variant }, { .compatible = "samsung,exynos4210-pwm", .data = &s5p64x0_variant }, - {}, + { } }; MODULE_DEVICE_TABLE(of, samsung_pwm_matches); diff --git a/drivers/pwm/pwm-sifive.c b/drivers/pwm/pwm-sifive.c index 4a07315b0744..d5000ea9084a 100644 --- a/drivers/pwm/pwm-sifive.c +++ b/drivers/pwm/pwm-sifive.c @@ -356,7 +356,7 @@ static void pwm_sifive_remove(struct platform_device *dev) static const struct of_device_id pwm_sifive_of_match[] = { { .compatible = "sifive,pwm0" }, - {}, + { } }; MODULE_DEVICE_TABLE(of, pwm_sifive_of_match); diff --git a/drivers/pwm/pwm-sl28cpld.c b/drivers/pwm/pwm-sl28cpld.c index 934378d6a002..ba6bec0b9289 100644 --- a/drivers/pwm/pwm-sl28cpld.c +++ b/drivers/pwm/pwm-sl28cpld.c @@ -245,7 +245,7 @@ static int sl28cpld_pwm_probe(struct platform_device *pdev) static const struct of_device_id sl28cpld_pwm_of_match[] = { { .compatible = "kontron,sl28cpld-pwm" }, - {} + { } }; MODULE_DEVICE_TABLE(of, sl28cpld_pwm_of_match); diff --git a/drivers/pwm/pwm-sophgo-sg2042.c b/drivers/pwm/pwm-sophgo-sg2042.c index 7d07b0ca7d29..0b6461172e6a 100644 --- a/drivers/pwm/pwm-sophgo-sg2042.c +++ b/drivers/pwm/pwm-sophgo-sg2042.c @@ -225,11 +225,10 @@ static const struct sg2042_chip_data sg2044_chip_data = { static const struct of_device_id sg2042_pwm_ids[] = { { .compatible = "sophgo,sg2042-pwm", - .data = &sg2042_chip_data - }, - { + .data = &sg2042_chip_data, + }, { .compatible = "sophgo,sg2044-pwm", - .data = &sg2044_chip_data + .data = &sg2044_chip_data, }, { } }; diff --git a/drivers/pwm/pwm-sprd.c b/drivers/pwm/pwm-sprd.c index 4c76ca5e4cdd..88928f9e7557 100644 --- a/drivers/pwm/pwm-sprd.c +++ b/drivers/pwm/pwm-sprd.c @@ -277,8 +277,8 @@ static int sprd_pwm_probe(struct platform_device *pdev) } static const struct of_device_id sprd_pwm_of_match[] = { - { .compatible = "sprd,ums512-pwm", }, - { }, + { .compatible = "sprd,ums512-pwm" }, + { } }; MODULE_DEVICE_TABLE(of, sprd_pwm_of_match); diff --git a/drivers/pwm/pwm-sti.c b/drivers/pwm/pwm-sti.c index 3b702b8f0c7f..e5c3cf594571 100644 --- a/drivers/pwm/pwm-sti.c +++ b/drivers/pwm/pwm-sti.c @@ -625,7 +625,7 @@ static int sti_pwm_probe(struct platform_device *pdev) } static const struct of_device_id sti_pwm_of_match[] = { - { .compatible = "st,sti-pwm", }, + { .compatible = "st,sti-pwm" }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, sti_pwm_of_match); diff --git a/drivers/pwm/pwm-stm32-lp.c b/drivers/pwm/pwm-stm32-lp.c index 4789eafb8bac..2aa88f4985f5 100644 --- a/drivers/pwm/pwm-stm32-lp.c +++ b/drivers/pwm/pwm-stm32-lp.c @@ -412,8 +412,8 @@ static DEFINE_SIMPLE_DEV_PM_OPS(stm32_pwm_lp_pm_ops, stm32_pwm_lp_suspend, stm32_pwm_lp_resume); static const struct of_device_id stm32_pwm_lp_of_match[] = { - { .compatible = "st,stm32-pwm-lp", }, - {}, + { .compatible = "st,stm32-pwm-lp" }, + { } }; MODULE_DEVICE_TABLE(of, stm32_pwm_lp_of_match); diff --git a/drivers/pwm/pwm-stm32.c b/drivers/pwm/pwm-stm32.c index c708e4a7ad70..ea5a51a2800f 100644 --- a/drivers/pwm/pwm-stm32.c +++ b/drivers/pwm/pwm-stm32.c @@ -918,9 +918,9 @@ static int stm32_pwm_resume(struct device *dev) static DEFINE_SIMPLE_DEV_PM_OPS(stm32_pwm_pm_ops, stm32_pwm_suspend, stm32_pwm_resume); static const struct of_device_id stm32_pwm_of_match[] = { - { .compatible = "st,stm32-pwm", }, - { .compatible = "st,stm32mp25-pwm", }, - { /* end node */ }, + { .compatible = "st,stm32-pwm" }, + { .compatible = "st,stm32mp25-pwm" }, + { /* end node */ } }; MODULE_DEVICE_TABLE(of, stm32_pwm_of_match); diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index 6c5591ca868b..0752152b1470 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -369,7 +369,7 @@ static const struct of_device_id sun4i_pwm_dt_ids[] = { .data = &sun50i_h6_pwm_data, }, { /* sentinel */ - }, + } }; MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids); diff --git a/drivers/pwm/pwm-sunplus.c b/drivers/pwm/pwm-sunplus.c index b342b843247b..b578f3f1a3a3 100644 --- a/drivers/pwm/pwm-sunplus.c +++ b/drivers/pwm/pwm-sunplus.c @@ -214,8 +214,8 @@ static int sunplus_pwm_probe(struct platform_device *pdev) } static const struct of_device_id sunplus_pwm_of_match[] = { - { .compatible = "sunplus,sp7021-pwm", }, - {} + { .compatible = "sunplus,sp7021-pwm" }, + { } }; MODULE_DEVICE_TABLE(of, sunplus_pwm_of_match); diff --git a/drivers/pwm/pwm-tiecap.c b/drivers/pwm/pwm-tiecap.c index 67cc5e8bdb0e..3751737ead43 100644 --- a/drivers/pwm/pwm-tiecap.c +++ b/drivers/pwm/pwm-tiecap.c @@ -211,9 +211,9 @@ static const struct pwm_ops ecap_pwm_ops = { }; static const struct of_device_id ecap_of_match[] = { - { .compatible = "ti,am3352-ecap" }, - { .compatible = "ti,am33xx-ecap" }, - {}, + { .compatible = "ti,am3352-ecap" }, + { .compatible = "ti,am33xx-ecap" }, + { } }; MODULE_DEVICE_TABLE(of, ecap_of_match); diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c index 2533c95b0ba9..3a53489f0b98 100644 --- a/drivers/pwm/pwm-tiehrpwm.c +++ b/drivers/pwm/pwm-tiehrpwm.c @@ -407,7 +407,7 @@ static const struct pwm_ops ehrpwm_pwm_ops = { static const struct of_device_id ehrpwm_of_match[] = { { .compatible = "ti,am3352-ehrpwm" }, { .compatible = "ti,am33xx-ehrpwm" }, - {}, + { } }; MODULE_DEVICE_TABLE(of, ehrpwm_of_match); diff --git a/drivers/pwm/pwm-twl-led.c b/drivers/pwm/pwm-twl-led.c index a555cc3be4b3..e1b6871af81e 100644 --- a/drivers/pwm/pwm-twl-led.c +++ b/drivers/pwm/pwm-twl-led.c @@ -338,7 +338,7 @@ static int twl_pwmled_probe(struct platform_device *pdev) static const struct of_device_id twl_pwmled_of_match[] = { { .compatible = "ti,twl4030-pwmled" }, { .compatible = "ti,twl6030-pwmled" }, - { }, + { } }; MODULE_DEVICE_TABLE(of, twl_pwmled_of_match); #endif diff --git a/drivers/pwm/pwm-twl.c b/drivers/pwm/pwm-twl.c index 8f981ffff4b4..99c1caf4f19c 100644 --- a/drivers/pwm/pwm-twl.c +++ b/drivers/pwm/pwm-twl.c @@ -362,7 +362,7 @@ static int twl_pwm_probe(struct platform_device *pdev) static const struct of_device_id twl_pwm_of_match[] = { { .compatible = "ti,twl4030-pwm" }, { .compatible = "ti,twl6030-pwm" }, - { }, + { } }; MODULE_DEVICE_TABLE(of, twl_pwm_of_match); #endif diff --git a/drivers/pwm/pwm-visconti.c b/drivers/pwm/pwm-visconti.c index 28fae4979e3f..830aef483bd0 100644 --- a/drivers/pwm/pwm-visconti.c +++ b/drivers/pwm/pwm-visconti.c @@ -156,7 +156,7 @@ static int visconti_pwm_probe(struct platform_device *pdev) } static const struct of_device_id visconti_pwm_of_match[] = { - { .compatible = "toshiba,visconti-pwm", }, + { .compatible = "toshiba,visconti-pwm" }, { } }; MODULE_DEVICE_TABLE(of, visconti_pwm_of_match); diff --git a/drivers/pwm/pwm-vt8500.c b/drivers/pwm/pwm-vt8500.c index 016c82d65527..3f2c8031a626 100644 --- a/drivers/pwm/pwm-vt8500.c +++ b/drivers/pwm/pwm-vt8500.c @@ -227,7 +227,7 @@ static const struct pwm_ops vt8500_pwm_ops = { }; static const struct of_device_id vt8500_pwm_dt_ids[] = { - { .compatible = "via,vt8500-pwm", }, + { .compatible = "via,vt8500-pwm" }, { /* Sentinel */ } }; MODULE_DEVICE_TABLE(of, vt8500_pwm_dt_ids); diff --git a/drivers/pwm/pwm-xilinx.c b/drivers/pwm/pwm-xilinx.c index 52c241982807..fa2d10e658dd 100644 --- a/drivers/pwm/pwm-xilinx.c +++ b/drivers/pwm/pwm-xilinx.c @@ -281,8 +281,8 @@ static int xilinx_pwm_probe(struct platform_device *pdev) } static const struct of_device_id xilinx_pwm_of_match[] = { - { .compatible = "xlnx,xps-timer-1.00.a", }, - {}, + { .compatible = "xlnx,xps-timer-1.00.a" }, + { } }; MODULE_DEVICE_TABLE(of, xilinx_pwm_of_match); From 0062b71a3e5464a4ec0e8c8fd0034413ca90e45d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= Date: Sun, 5 Jul 2026 17:14:17 +0200 Subject: [PATCH 08/18] pwm: lpss-pci: Unify coding style of pci_device_id array MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Don't use a comma after an array terminator. Signed-off-by: Uwe Kleine-König (The Capable Hub) Link: https://patch.msgid.link/235336ce4e90ca7568303119b6f09fb77adca45c.1783263835.git.ukleinek@kernel.org Signed-off-by: Uwe Kleine-König --- drivers/pwm/pwm-lpss-pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-lpss-pci.c b/drivers/pwm/pwm-lpss-pci.c index 3a0fd6593520..bcbfda1a6624 100644 --- a/drivers/pwm/pwm-lpss-pci.c +++ b/drivers/pwm/pwm-lpss-pci.c @@ -57,7 +57,7 @@ static const struct pci_device_id pwm_lpss_pci_ids[] = { { PCI_VDEVICE(INTEL, 0x2289), .driver_data = (unsigned long)&pwm_lpss_bsw_info }, { PCI_VDEVICE(INTEL, 0x31c8), .driver_data = (unsigned long)&pwm_lpss_bxt_info }, { PCI_VDEVICE(INTEL, 0x5ac8), .driver_data = (unsigned long)&pwm_lpss_bxt_info }, - { }, + { } }; MODULE_DEVICE_TABLE(pci, pwm_lpss_pci_ids); From b4772201070d8a4b459eff4a42f6c28058d84d2d Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 1 Jul 2026 12:20:30 +0900 Subject: [PATCH 09/18] dt-bindings: pwm: Document Tegra264 controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a new compatible string for the PWM controller found on Tegra264. The controller is similar to earlier generations but not compatible with them. Signed-off-by: Thierry Reding [mperttunen: Drop extra Tegra194 compatible string] Acked-by: Rob Herring (Arm) Signed-off-by: Mikko Perttunen Tested-by: Jon Hunter Reviewed-by: Jon Hunter Link: https://patch.msgid.link/20260701-t264-pwm-v6-1-2718f61f411f@nvidia.com Signed-off-by: Uwe Kleine-König --- Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.yaml b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.yaml index 41cea4979132..cb2f36e7b5d6 100644 --- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.yaml @@ -16,6 +16,7 @@ properties: - enum: - nvidia,tegra20-pwm - nvidia,tegra186-pwm + - nvidia,tegra264-pwm - items: - enum: From dbd80899658a86ac6f1058909ce7b474120b4acf Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Wed, 1 Jul 2026 12:20:31 +0900 Subject: [PATCH 10/18] pwm: tegra: Prefix driver-local macros and functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Prefix driver-local defines and functions with tegra_/TEGRA_ to clearly distinguish them from any general PWM related symbols. Signed-off-by: Mikko Perttunen Tested-by: Jon Hunter Reviewed-by: Jon Hunter Link: https://patch.msgid.link/20260701-t264-pwm-v6-2-2718f61f411f@nvidia.com Signed-off-by: Uwe Kleine-König --- drivers/pwm/pwm-tegra.c | 54 ++++++++++++++++++++--------------------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index 172063b51d44..f8c5495a56a6 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -51,11 +51,11 @@ #include -#define PWM_ENABLE (1 << 31) -#define PWM_DUTY_WIDTH 8 -#define PWM_DUTY_SHIFT 16 -#define PWM_SCALE_WIDTH 13 -#define PWM_SCALE_SHIFT 0 +#define TEGRA_PWM_ENABLE (1 << 31) +#define TEGRA_PWM_DUTY_WIDTH 8 +#define TEGRA_PWM_DUTY_SHIFT 16 +#define TEGRA_PWM_SCALE_WIDTH 13 +#define TEGRA_PWM_SCALE_SHIFT 0 struct tegra_pwm_soc { unsigned int num_channels; @@ -81,12 +81,12 @@ static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip) return pwmchip_get_drvdata(chip); } -static inline u32 pwm_readl(struct tegra_pwm_chip *pc, unsigned int offset) +static inline u32 tegra_pwm_readl(struct tegra_pwm_chip *pc, unsigned int offset) { return readl(pc->regs + (offset << 4)); } -static inline void pwm_writel(struct tegra_pwm_chip *pc, unsigned int offset, u32 value) +static inline void tegra_pwm_writel(struct tegra_pwm_chip *pc, unsigned int offset, u32 value) { writel(value, pc->regs + (offset << 4)); } @@ -102,22 +102,22 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, /* * Convert from duty_ns / period_ns to a fixed number of duty ticks - * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the + * per (1 << TEGRA_PWM_DUTY_WIDTH) cycles and make sure to round to the * nearest integer during division. */ - c *= (1 << PWM_DUTY_WIDTH); + c *= (1 << TEGRA_PWM_DUTY_WIDTH); c = DIV_ROUND_CLOSEST_ULL(c, period_ns); - val = (u32)c << PWM_DUTY_SHIFT; + val = (u32)c << TEGRA_PWM_DUTY_SHIFT; /* - * min period = max clock limit >> PWM_DUTY_WIDTH + * min period = max clock limit >> TEGRA_PWM_DUTY_WIDTH */ if (period_ns < pc->min_period_ns) return -EINVAL; /* - * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH) + * Compute the prescaler value for which (1 << TEGRA_PWM_DUTY_WIDTH) * cycles at the PWM clock rate will take period_ns nanoseconds. * * num_channels: If single instance of PWM controller has multiple @@ -131,7 +131,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, */ if (pc->soc->num_channels == 1) { /* - * Rate is multiplied with 2^PWM_DUTY_WIDTH so that it matches + * Rate is multiplied with 2^TEGRA_PWM_DUTY_WIDTH so that it matches * with the maximum possible rate that the controller can * provide. Any further lower value can be derived by setting * PFM bits[0:12]. @@ -141,7 +141,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, * source clock rate as required_clk_rate, PWM controller will * be able to configure the requested period. */ - required_clk_rate = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << PWM_DUTY_WIDTH, + required_clk_rate = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << TEGRA_PWM_DUTY_WIDTH, period_ns); if (required_clk_rate > clk_round_rate(pc->clk, required_clk_rate)) @@ -163,9 +163,9 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, pc->clk_rate = clk_get_rate(pc->clk); } - /* Consider precision in PWM_SCALE_WIDTH rate calculation */ + /* Consider precision in TEGRA_PWM_SCALE_WIDTH rate calculation */ rate = mul_u64_u64_div_u64(pc->clk_rate, period_ns, - (u64)NSEC_PER_SEC << PWM_DUTY_WIDTH); + (u64)NSEC_PER_SEC << TEGRA_PWM_DUTY_WIDTH); /* * Since the actual PWM divider is the register's frequency divider @@ -181,10 +181,10 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, * Make sure that the rate will fit in the register's frequency * divider field. */ - if (rate >> PWM_SCALE_WIDTH) + if (rate >> TEGRA_PWM_SCALE_WIDTH) return -EINVAL; - val |= rate << PWM_SCALE_SHIFT; + val |= rate << TEGRA_PWM_SCALE_SHIFT; /* * If the PWM channel is disabled, make sure to turn on the clock @@ -195,9 +195,9 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, if (err) return err; } else - val |= PWM_ENABLE; + val |= TEGRA_PWM_ENABLE; - pwm_writel(pc, pwm->hwpwm, val); + tegra_pwm_writel(pc, pwm->hwpwm, val); /* * If the PWM is not enabled, turn the clock off again to save power. @@ -218,9 +218,9 @@ static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) if (rc) return rc; - val = pwm_readl(pc, pwm->hwpwm); - val |= PWM_ENABLE; - pwm_writel(pc, pwm->hwpwm, val); + val = tegra_pwm_readl(pc, pwm->hwpwm); + val |= TEGRA_PWM_ENABLE; + tegra_pwm_writel(pc, pwm->hwpwm, val); return 0; } @@ -230,9 +230,9 @@ static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); u32 val; - val = pwm_readl(pc, pwm->hwpwm); - val &= ~PWM_ENABLE; - pwm_writel(pc, pwm->hwpwm, val); + val = tegra_pwm_readl(pc, pwm->hwpwm); + val &= ~TEGRA_PWM_ENABLE; + tegra_pwm_writel(pc, pwm->hwpwm, val); pm_runtime_put_sync(pwmchip_parent(chip)); } @@ -318,7 +318,7 @@ static int tegra_pwm_probe(struct platform_device *pdev) /* Set minimum limit of PWM period for the IP */ pc->min_period_ns = - (NSEC_PER_SEC / (pc->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1; + (NSEC_PER_SEC / (pc->soc->max_frequency >> TEGRA_PWM_DUTY_WIDTH)) + 1; pc->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm"); if (IS_ERR(pc->rst)) { From d6bf1d39c3413a44712cba461d47d31e0cec51d7 Mon Sep 17 00:00:00 2001 From: Yi-Wei Wang Date: Wed, 1 Jul 2026 12:20:32 +0900 Subject: [PATCH 11/18] pwm: tegra: Avoid hard-coded max clock frequency MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The clock driving the Tegra PWM IP can be sourced from different parent clocks. Hence, let dev_pm_opp_set_rate() set the max clock rate based upon the current parent clock that can be specified via device-tree. After this, the Tegra194 SoC data becomes redundant, so get rid of it. Signed-off-by: Yi-Wei Wang Reviewed-by: Thierry Reding Co-developed-by: Mikko Perttunen Signed-off-by: Mikko Perttunen Tested-by: Jon Hunter Reviewed-by: Jon Hunter Link: https://patch.msgid.link/20260701-t264-pwm-v6-3-2718f61f411f@nvidia.com Signed-off-by: Uwe Kleine-König --- drivers/pwm/pwm-tegra.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index f8c5495a56a6..3eef299c51f8 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -59,9 +59,6 @@ struct tegra_pwm_soc { unsigned int num_channels; - - /* Maximum IP frequency for given SoCs */ - unsigned long max_frequency; }; struct tegra_pwm_chip { @@ -303,7 +300,7 @@ static int tegra_pwm_probe(struct platform_device *pdev) return ret; /* Set maximum frequency of the IP */ - ret = dev_pm_opp_set_rate(&pdev->dev, pc->soc->max_frequency); + ret = dev_pm_opp_set_rate(&pdev->dev, ULONG_MAX); if (ret < 0) { dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret); goto put_pm; @@ -315,10 +312,15 @@ static int tegra_pwm_probe(struct platform_device *pdev) * so that PWM period can be calculated more accurately. */ pc->clk_rate = clk_get_rate(pc->clk); + if (pc->clk_rate < (1 << TEGRA_PWM_DUTY_WIDTH)) { + dev_err(&pdev->dev, "clock maximum frequency out of range\n"); + ret = -ERANGE; + goto put_pm; + } /* Set minimum limit of PWM period for the IP */ pc->min_period_ns = - (NSEC_PER_SEC / (pc->soc->max_frequency >> TEGRA_PWM_DUTY_WIDTH)) + 1; + (NSEC_PER_SEC / (pc->clk_rate >> TEGRA_PWM_DUTY_WIDTH)) + 1; pc->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm"); if (IS_ERR(pc->rst)) { @@ -397,23 +399,16 @@ static int __maybe_unused tegra_pwm_runtime_resume(struct device *dev) static const struct tegra_pwm_soc tegra20_pwm_soc = { .num_channels = 4, - .max_frequency = 48000000UL, }; static const struct tegra_pwm_soc tegra186_pwm_soc = { .num_channels = 1, - .max_frequency = 102000000UL, -}; - -static const struct tegra_pwm_soc tegra194_pwm_soc = { - .num_channels = 1, - .max_frequency = 408000000UL, }; static const struct of_device_id tegra_pwm_of_match[] = { { .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc }, { .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc }, - { .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc }, + { .compatible = "nvidia,tegra194-pwm", .data = &tegra186_pwm_soc }, { } }; MODULE_DEVICE_TABLE(of, tegra_pwm_of_match); From 83a4cadc7ae5512262930bbbc2d802e8eef1dc93 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Wed, 1 Jul 2026 12:20:33 +0900 Subject: [PATCH 12/18] pwm: tegra: Modify read/write accessors for multi-register channel MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On Tegra264, each PWM instance has two registers (per channel, of which there is one). Update the tegra_pwm_readl/tegra_pwm_writel helper functions to take channel (as struct pwm_device *) and offset separately. Signed-off-by: Mikko Perttunen Tested-by: Jon Hunter Reviewed-by: Jon Hunter Link: https://patch.msgid.link/20260701-t264-pwm-v6-4-2718f61f411f@nvidia.com Signed-off-by: Uwe Kleine-König --- drivers/pwm/pwm-tegra.c | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index 3eef299c51f8..55a3e8657013 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -57,6 +57,8 @@ #define TEGRA_PWM_SCALE_WIDTH 13 #define TEGRA_PWM_SCALE_SHIFT 0 +#define TEGRA_PWM_CSR_0 0 + struct tegra_pwm_soc { unsigned int num_channels; }; @@ -78,14 +80,18 @@ static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip) return pwmchip_get_drvdata(chip); } -static inline u32 tegra_pwm_readl(struct tegra_pwm_chip *pc, unsigned int offset) +static inline u32 tegra_pwm_readl(struct pwm_device *pwm, unsigned int offset) { - return readl(pc->regs + (offset << 4)); + struct tegra_pwm_chip *chip = to_tegra_pwm_chip(pwm->chip); + + return readl(chip->regs + (pwm->hwpwm * 16) + offset); } -static inline void tegra_pwm_writel(struct tegra_pwm_chip *pc, unsigned int offset, u32 value) +static inline void tegra_pwm_writel(struct pwm_device *pwm, unsigned int offset, u32 value) { - writel(value, pc->regs + (offset << 4)); + struct tegra_pwm_chip *chip = to_tegra_pwm_chip(pwm->chip); + + writel(value, chip->regs + (pwm->hwpwm * 16) + offset); } static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, @@ -194,7 +200,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, } else val |= TEGRA_PWM_ENABLE; - tegra_pwm_writel(pc, pwm->hwpwm, val); + tegra_pwm_writel(pwm, TEGRA_PWM_CSR_0, val); /* * If the PWM is not enabled, turn the clock off again to save power. @@ -207,7 +213,6 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) { - struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); int rc = 0; u32 val; @@ -215,21 +220,20 @@ static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) if (rc) return rc; - val = tegra_pwm_readl(pc, pwm->hwpwm); + val = tegra_pwm_readl(pwm, TEGRA_PWM_CSR_0); val |= TEGRA_PWM_ENABLE; - tegra_pwm_writel(pc, pwm->hwpwm, val); + tegra_pwm_writel(pwm, TEGRA_PWM_CSR_0, val); return 0; } static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) { - struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); u32 val; - val = tegra_pwm_readl(pc, pwm->hwpwm); + val = tegra_pwm_readl(pwm, TEGRA_PWM_CSR_0); val &= ~TEGRA_PWM_ENABLE; - tegra_pwm_writel(pc, pwm->hwpwm, val); + tegra_pwm_writel(pwm, TEGRA_PWM_CSR_0, val); pm_runtime_put_sync(pwmchip_parent(chip)); } From b9a6f48de9a4816d5f5fc9adacfe7f3433012d2b Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Wed, 1 Jul 2026 12:20:34 +0900 Subject: [PATCH 13/18] pwm: tegra: Parametrize duty and scale field widths MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tegra264 has wider fields for the duty and scale register fields. Parameterize the scale field width. The depth value becomes disconnected from the duty field width, so define it separately and remove the duty field width definition. Co-developed-by: Yi-Wei Wang Signed-off-by: Yi-Wei Wang Signed-off-by: Mikko Perttunen Tested-by: Jon Hunter Reviewed-by: Jon Hunter Link: https://patch.msgid.link/20260701-t264-pwm-v6-5-2718f61f411f@nvidia.com Signed-off-by: Uwe Kleine-König --- drivers/pwm/pwm-tegra.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index 55a3e8657013..ad75e4ee3410 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -52,15 +52,17 @@ #include #define TEGRA_PWM_ENABLE (1 << 31) -#define TEGRA_PWM_DUTY_WIDTH 8 #define TEGRA_PWM_DUTY_SHIFT 16 -#define TEGRA_PWM_SCALE_WIDTH 13 #define TEGRA_PWM_SCALE_SHIFT 0 #define TEGRA_PWM_CSR_0 0 +#define TEGRA_PWM_DEPTH 256 + struct tegra_pwm_soc { unsigned int num_channels; + + unsigned int scale_width; }; struct tegra_pwm_chip { @@ -105,22 +107,22 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, /* * Convert from duty_ns / period_ns to a fixed number of duty ticks - * per (1 << TEGRA_PWM_DUTY_WIDTH) cycles and make sure to round to the + * per TEGRA_PWM_DEPTH cycles and make sure to round to the * nearest integer during division. */ - c *= (1 << TEGRA_PWM_DUTY_WIDTH); + c *= TEGRA_PWM_DEPTH; c = DIV_ROUND_CLOSEST_ULL(c, period_ns); val = (u32)c << TEGRA_PWM_DUTY_SHIFT; /* - * min period = max clock limit >> TEGRA_PWM_DUTY_WIDTH + * min period = max clock limit / TEGRA_PWM_DEPTH */ if (period_ns < pc->min_period_ns) return -EINVAL; /* - * Compute the prescaler value for which (1 << TEGRA_PWM_DUTY_WIDTH) + * Compute the prescaler value for which TEGRA_PWM_DEPTH * cycles at the PWM clock rate will take period_ns nanoseconds. * * num_channels: If single instance of PWM controller has multiple @@ -134,7 +136,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, */ if (pc->soc->num_channels == 1) { /* - * Rate is multiplied with 2^TEGRA_PWM_DUTY_WIDTH so that it matches + * Rate is multiplied with TEGRA_PWM_DEPTH so that it matches * with the maximum possible rate that the controller can * provide. Any further lower value can be derived by setting * PFM bits[0:12]. @@ -144,7 +146,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, * source clock rate as required_clk_rate, PWM controller will * be able to configure the requested period. */ - required_clk_rate = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << TEGRA_PWM_DUTY_WIDTH, + required_clk_rate = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * TEGRA_PWM_DEPTH, period_ns); if (required_clk_rate > clk_round_rate(pc->clk, required_clk_rate)) @@ -166,9 +168,9 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, pc->clk_rate = clk_get_rate(pc->clk); } - /* Consider precision in TEGRA_PWM_SCALE_WIDTH rate calculation */ + /* Consider precision in scale_width rate calculation */ rate = mul_u64_u64_div_u64(pc->clk_rate, period_ns, - (u64)NSEC_PER_SEC << TEGRA_PWM_DUTY_WIDTH); + (u64)NSEC_PER_SEC * TEGRA_PWM_DEPTH); /* * Since the actual PWM divider is the register's frequency divider @@ -184,7 +186,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, * Make sure that the rate will fit in the register's frequency * divider field. */ - if (rate >> TEGRA_PWM_SCALE_WIDTH) + if (rate >> pc->soc->scale_width) return -EINVAL; val |= rate << TEGRA_PWM_SCALE_SHIFT; @@ -316,7 +318,7 @@ static int tegra_pwm_probe(struct platform_device *pdev) * so that PWM period can be calculated more accurately. */ pc->clk_rate = clk_get_rate(pc->clk); - if (pc->clk_rate < (1 << TEGRA_PWM_DUTY_WIDTH)) { + if (pc->clk_rate < TEGRA_PWM_DEPTH) { dev_err(&pdev->dev, "clock maximum frequency out of range\n"); ret = -ERANGE; goto put_pm; @@ -324,7 +326,7 @@ static int tegra_pwm_probe(struct platform_device *pdev) /* Set minimum limit of PWM period for the IP */ pc->min_period_ns = - (NSEC_PER_SEC / (pc->clk_rate >> TEGRA_PWM_DUTY_WIDTH)) + 1; + (NSEC_PER_SEC / (pc->clk_rate / TEGRA_PWM_DEPTH)) + 1; pc->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm"); if (IS_ERR(pc->rst)) { @@ -403,10 +405,12 @@ static int __maybe_unused tegra_pwm_runtime_resume(struct device *dev) static const struct tegra_pwm_soc tegra20_pwm_soc = { .num_channels = 4, + .scale_width = 13, }; static const struct tegra_pwm_soc tegra186_pwm_soc = { .num_channels = 1, + .scale_width = 13, }; static const struct of_device_id tegra_pwm_of_match[] = { From 82dcd68f7246eeacbc2ef614b82e284a50b2b8bb Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Wed, 1 Jul 2026 12:20:35 +0900 Subject: [PATCH 14/18] pwm: tegra: Add support for Tegra264 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tegra264 changes the register layout to accommodate wider fields for duty and scale, and adds configurable depth which will be supported in a later patch. The enable bit also moves from CSR_0 to a separate CSR_1 register. To support the new enable register location, introduce an enable_reg field in struct tegra_pwm_soc that identifies which register contains the PWM_ENABLE bit. tegra_pwm_enable() and tegra_pwm_disable() read/write this field accordingly, and tegra_pwm_config() skips OR-ing PWM_ENABLE into its CSR_0 write on SoCs where the enable bit is not in CSR_0. Update the top comment to describe the register layout in more detail. Co-developed-by: Yi-Wei Wang Signed-off-by: Yi-Wei Wang Signed-off-by: Mikko Perttunen Tested-by: Jon Hunter Reviewed-by: Jon Hunter Link: https://patch.msgid.link/20260701-t264-pwm-v6-6-2718f61f411f@nvidia.com Signed-off-by: Uwe Kleine-König --- drivers/pwm/pwm-tegra.c | 91 ++++++++++++++++++++++++++++++++--------- 1 file changed, 72 insertions(+), 19 deletions(-) diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index ad75e4ee3410..5cdbe120ba2d 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -7,23 +7,62 @@ * Copyright (c) 2010-2020, NVIDIA Corporation. * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer * - * Overview of Tegra Pulse Width Modulator Register: - * 1. 13-bit: Frequency division (SCALE) - * 2. 8-bit : Pulse division (DUTY) - * 3. 1-bit : Enable bit + * Overview of Tegra Pulse Width Modulator Register + * CSR_0 of Tegra20, Tegra186, and Tegra194: + * +-------+-------+-----------------------------------------------------------+ + * | Bit | Field | Description | + * +-------+-------+-----------------------------------------------------------+ + * | 31 | ENB | Enable Pulse width modulator. | + * | | | 0 = DISABLE, 1 = ENABLE. | + * +-------+-------+-----------------------------------------------------------+ + * | 30:16 | PWM_0 | Pulse width that needs to be programmed. | + * | | | 0 = Always low. | + * | | | 1 = 1 / 256 pulse high. | + * | | | 2 = 2 / 256 pulse high. | + * | | | N = N / 256 pulse high. | + * | | | Only 8 bits are usable [23:16]. | + * | | | Bit[24] can be programmed to 1 to achieve 100% duty | + * | | | cycle. In this case the other bits [23:16] are set to | + * | | | don’t care. | + * +-------+-------+-----------------------------------------------------------+ + * | 12:0 | PFM_0 | Frequency divider that needs to be programmed, also known | + * | | | as SCALE. Division by (1 + PFM_0). | + * +-------+-------+-----------------------------------------------------------+ * - * The PWM clock frequency is divided by 256 before subdividing it based - * on the programmable frequency division value to generate the required - * frequency for PWM output. The maximum output frequency that can be - * achieved is (max rate of source clock) / 256. - * e.g. if source clock rate is 408 MHz, maximum output frequency can be: - * 408 MHz/256 = 1.6 MHz. + * CSR_0 of Tegra264: + * +-------+-------+-----------------------------------------------------------+ + * | Bit | Field | Description | + * +-------+-------+-----------------------------------------------------------+ + * | 31:16 | PWM_0 | Pulse width that needs to be programmed. | + * | | | 0 = Always low. | + * | | | 1 = 1 / (1 + CSR_1.DEPTH) pulse high. | + * | | | 2 = 2 / (1 + CSR_1.DEPTH) pulse high. | + * | | | N = N / (1 + CSR_1.DEPTH) pulse high. | + * +-------+-------+-----------------------------------------------------------+ + * | 15:0 | PFM_0 | Frequency divider that needs to be programmed, also known | + * | | | as SCALE. Division by (1 + PFM_0). | + * +-------+-------+-----------------------------------------------------------+ + * + * CSR_1 of Tegra264: + * +-------+-------+-----------------------------------------------------------+ + * | Bit | Field | Description | + * +-------+-------+-----------------------------------------------------------+ + * | 31 | ENB | Enable Pulse width modulator. | + * | | | 0 = DISABLE, 1 = ENABLE. | + * +-------+-------+-----------------------------------------------------------+ + * | 30:15 | DEPTH | Depth for pulse width modulator. This controls the pulse | + * | | | time generated. Division by (1 + CSR_1.DEPTH). | + * +-------+-------+-----------------------------------------------------------+ + * + * The PWM clock frequency is divided by DEPTH = (1 + CSR_1.DEPTH) before + * subdividing it based on the programmable frequency division value to + * generate the required frequency for PWM output. DEPTH is fixed to 256 + * before Tegra264. The maximum output frequency that can be achieved is + * (max rate of source clock) / DEPTH. + * e.g. if source clock rate is 408 MHz, and DEPTH = 256, maximum output + * frequency can be: 408 MHz / 256 ~= 1.6 MHz. * This 1.6 MHz frequency can further be divided using SCALE value in PWM. * - * PWM pulse width: 8 bits are usable [23:16] for varying pulse width. - * To achieve 100% duty cycle, program Bit [24] of this register to - * 1’b1. In which case the other bits [23:16] are set to don't care. - * * Limitations: * - When PWM is disabled, the output is driven to inactive. * - It does not allow the current PWM period to complete and @@ -56,11 +95,13 @@ #define TEGRA_PWM_SCALE_SHIFT 0 #define TEGRA_PWM_CSR_0 0 +#define TEGRA_PWM_CSR_1 4 #define TEGRA_PWM_DEPTH 256 struct tegra_pwm_soc { unsigned int num_channels; + unsigned int enable_reg; unsigned int scale_width; }; @@ -199,8 +240,9 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, err = pm_runtime_resume_and_get(pwmchip_parent(chip)); if (err) return err; - } else + } else if (pc->soc->enable_reg == TEGRA_PWM_CSR_0) { val |= TEGRA_PWM_ENABLE; + } tegra_pwm_writel(pwm, TEGRA_PWM_CSR_0, val); @@ -215,6 +257,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) { + struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); int rc = 0; u32 val; @@ -222,20 +265,21 @@ static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) if (rc) return rc; - val = tegra_pwm_readl(pwm, TEGRA_PWM_CSR_0); + val = tegra_pwm_readl(pwm, pc->soc->enable_reg); val |= TEGRA_PWM_ENABLE; - tegra_pwm_writel(pwm, TEGRA_PWM_CSR_0, val); + tegra_pwm_writel(pwm, pc->soc->enable_reg, val); return 0; } static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) { + struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); u32 val; - val = tegra_pwm_readl(pwm, TEGRA_PWM_CSR_0); + val = tegra_pwm_readl(pwm, pc->soc->enable_reg); val &= ~TEGRA_PWM_ENABLE; - tegra_pwm_writel(pwm, TEGRA_PWM_CSR_0, val); + tegra_pwm_writel(pwm, pc->soc->enable_reg, val); pm_runtime_put_sync(pwmchip_parent(chip)); } @@ -405,18 +449,27 @@ static int __maybe_unused tegra_pwm_runtime_resume(struct device *dev) static const struct tegra_pwm_soc tegra20_pwm_soc = { .num_channels = 4, + .enable_reg = TEGRA_PWM_CSR_0, .scale_width = 13, }; static const struct tegra_pwm_soc tegra186_pwm_soc = { .num_channels = 1, + .enable_reg = TEGRA_PWM_CSR_0, .scale_width = 13, }; +static const struct tegra_pwm_soc tegra264_pwm_soc = { + .num_channels = 1, + .enable_reg = TEGRA_PWM_CSR_1, + .scale_width = 16, +}; + static const struct of_device_id tegra_pwm_of_match[] = { { .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc }, { .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc }, { .compatible = "nvidia,tegra194-pwm", .data = &tegra186_pwm_soc }, + { .compatible = "nvidia,tegra264-pwm", .data = &tegra264_pwm_soc }, { } }; MODULE_DEVICE_TABLE(of, tegra_pwm_of_match); From 3f9e76c1628fadf92922afee4d3a9d3871de7420 Mon Sep 17 00:00:00 2001 From: Markus Elfring Date: Fri, 5 Jun 2026 16:12:53 +0200 Subject: [PATCH 15/18] pwm: Use seq_putc() calls in pwm_dbg_show() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Single characters should occasionally be put into a sequence. Thus use the corresponding function `seq_putc()`. The source code was transformed by using the Coccinelle software. Signed-off-by: Markus Elfring Link: https://patch.msgid.link/5cc95f1d-a9f4-4ba4-8411-56cfb16d996a@web.de [ukleinek: fixup for a third instance, originally addressed differently] Link: https://patch.msgid.link/03062fdb-cc4f-47c7-a007-4ac67ded6377@web.de Signed-off-by: Uwe Kleine-König --- drivers/pwm/core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c index be4885da85b6..2a050ff4608b 100644 --- a/drivers/pwm/core.c +++ b/drivers/pwm/core.c @@ -2647,14 +2647,14 @@ static void pwm_dbg_show(struct pwm_chip *chip, struct seq_file *s) if (test_bit(PWMF_REQUESTED, &pwm->flags)) seq_puts(s, " requested"); - seq_puts(s, "\n"); + seq_putc(s, '\n'); seq_printf(s, " requested configuration: %3sabled, %llu/%llu ns, %s polarity", state.enabled ? "en" : "dis", state.duty_cycle, state.period, state.polarity ? "inverse" : "normal"); if (state.usage_power) seq_puts(s, ", usage_power"); - seq_puts(s, "\n"); + seq_putc(s, '\n'); if (pwmchip_supports_waveform(chip)) { struct pwm_waveform wf; @@ -2677,7 +2677,7 @@ static void pwm_dbg_show(struct pwm_chip *chip, struct seq_file *s) seq_printf(s, " actual configuration: read out error: %pe", ERR_PTR(err)); } - seq_puts(s, "\n"); + seq_putc(s, '\n'); } } From d3aca8a2ca5d078a7bc9a3fcb3f418a18a2431a4 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 4 Jun 2026 10:56:35 +0100 Subject: [PATCH 16/18] pwm: rzg2l-gpt: Drop unused rzg2l_gpt_chip parameter from rzg2l_gpt_calculate_prescale() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The rzg2l_gpt parameter was passed to rzg2l_gpt_calculate_prescale() but never used inside the function. Remove it and update the sole call site accordingly. Signed-off-by: Biju Das Link: https://patch.msgid.link/20260604095647.108654-6-biju.das.jz@bp.renesas.com Signed-off-by: Uwe Kleine-König --- drivers/pwm/pwm-rzg2l-gpt.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index ac8399b96ad1..1569f3ba8c53 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -118,8 +118,7 @@ static void rzg2l_gpt_modify(struct rzg2l_gpt_chip *rzg2l_gpt, u32 reg, u32 clr, (rzg2l_gpt_read(rzg2l_gpt, reg) & ~clr) | set); } -static u8 rzg2l_gpt_calculate_prescale(struct rzg2l_gpt_chip *rzg2l_gpt, - u64 period_ticks) +static u8 rzg2l_gpt_calculate_prescale(u64 period_ticks) { u32 prescaled_period_ticks; u8 prescale; @@ -286,7 +285,7 @@ static int rzg2l_gpt_config(struct pwm_chip *chip, struct pwm_device *pwm, } } - prescale = rzg2l_gpt_calculate_prescale(rzg2l_gpt, period_ticks); + prescale = rzg2l_gpt_calculate_prescale(period_ticks); pv = rzg2l_gpt_calculate_pv_or_dc(period_ticks, prescale); duty_ticks = mul_u64_u64_div_u64(state->duty_cycle, rzg2l_gpt->rate_khz, USEC_PER_SEC); From 3aeb2997680ecbce5564b6aa9a56c6d4f1fed209 Mon Sep 17 00:00:00 2001 From: Francis Laniel Date: Wed, 3 Jun 2026 19:09:09 +0300 Subject: [PATCH 17/18] rust: pwm: replace `core::mem::zeroed` with `pin_init::zeroed` MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All types in `bindings` implement `Zeroable` if they can, so use `pin_init::zeroed` instead of relying on `unsafe` code. If this ends up not compiling in the future, something in bindgen or on the C side changed and is most likely incorrect. Suggested-by: Benno Lossin Link: https://github.com/Rust-for-Linux/linux/issues/1189 Reviewed-by: Alexandre Courbot Acked-by: Michal Wilczynski Signed-off-by: Francis Laniel Link: https://patch.msgid.link/20260603160910.159307-1-laniel_francis@privacyrequired.com Signed-off-by: Uwe Kleine-König --- rust/kernel/pwm.rs | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/rust/kernel/pwm.rs b/rust/kernel/pwm.rs index 6c9d667009ef..3427b7d93a03 100644 --- a/rust/kernel/pwm.rs +++ b/rust/kernel/pwm.rs @@ -494,9 +494,7 @@ pub(crate) fn as_raw(&self) -> *const bindings::pwm_ops { /// This is used to bridge Rust trait implementations to the C `struct pwm_ops` /// expected by the kernel. pub const fn create_pwm_ops() -> PwmOpsVTable { - // SAFETY: `core::mem::zeroed()` is unsafe. For `pwm_ops`, all fields are - // `Option` or data, so a zeroed pattern (None/0) is valid initially. - let mut ops: bindings::pwm_ops = unsafe { core::mem::zeroed() }; + let mut ops: bindings::pwm_ops = pin_init::zeroed(); ops.request = Some(Adapter::::request_callback); ops.capture = Some(Adapter::::capture_callback); From b4e94b0418ad6dbe62b6ca53369159ed3d9f0d8c Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Tue, 21 Jul 2026 00:49:27 -0700 Subject: [PATCH 18/18] pwm: th1520: use vertical import style MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Convert `use` imports to vertical layout for better readability and maintainability. Signed-off-by: Guru Das Srinagesh Reviewed-by: Michal Wilczynski Link: https://patch.msgid.link/20260721-pwm-rust-vert-imp-v2-1-9f91547f5e07@gurudas.dev Signed-off-by: Uwe Kleine-König --- drivers/pwm/pwm_th1520.rs | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/pwm/pwm_th1520.rs b/drivers/pwm/pwm_th1520.rs index 3e3fa51ccef9..543bd8dea846 100644 --- a/drivers/pwm/pwm_th1520.rs +++ b/drivers/pwm/pwm_th1520.rs @@ -23,15 +23,21 @@ use core::ops::Deref; use kernel::{ clk::Clk, - device::{Bound, Core, Device}, + device::{ + Bound, + Core, + Device, // + }, devres, io::{ mem::IoMem, Io, // }, - of, platform, + of, + platform, prelude::*, - pwm, time, + pwm, + time, // }; const TH1520_MAX_PWM_NUM: u32 = 6;