From 9be3b7bb7ddd4e8ed466f41c6f43de34424aeb8c Mon Sep 17 00:00:00 2001 From: Ivaylo Ivanov Date: Sun, 14 Sep 2025 14:44:55 +0300 Subject: [PATCH 001/107] dt-bindings: pinctrl: samsung: add exynos8890 compatible Document the pinctrl compatible for the exynos8890 SoC. Let the driver handle our clocks for pinctrl as well. Signed-off-by: Ivaylo Ivanov Reviewed-by: Krzysztof Kozlowski Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml index f1094d65e846..076d960a62c9 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml @@ -52,6 +52,7 @@ properties: - samsung,exynos7870-pinctrl - samsung,exynos7885-pinctrl - samsung,exynos850-pinctrl + - samsung,exynos8890-pinctrl - samsung,exynos8895-pinctrl - samsung,exynos9810-pinctrl - samsung,exynos990-pinctrl @@ -133,7 +134,9 @@ allOf: properties: compatible: contains: - const: google,gs101-pinctrl + enum: + - google,gs101-pinctrl + - samsung,exynos8890-pinctrl then: required: - clocks From f416d35e6522f0c08d4e866e5d6930bfd504e645 Mon Sep 17 00:00:00 2001 From: Ivaylo Ivanov Date: Sun, 14 Sep 2025 14:44:56 +0300 Subject: [PATCH 002/107] dt-bindings: pinctrl: samsung: add exynos8890-wakeup-eint compatible Add a dedicated compatible for exynos8890. Signed-off-by: Ivaylo Ivanov Signed-off-by: Krzysztof Kozlowski --- .../bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml index dd11c73a55da..f3c433015b12 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml @@ -41,6 +41,7 @@ properties: - samsung,exynos7870-wakeup-eint - samsung,exynos7885-wakeup-eint - samsung,exynos850-wakeup-eint + - samsung,exynos8890-wakeup-eint - samsung,exynos8895-wakeup-eint - const: samsung,exynos7-wakeup-eint - items: From 5b6b7d39cee69373dc61ca22164d616e4faf60c6 Mon Sep 17 00:00:00 2001 From: Ivaylo Ivanov Date: Sun, 14 Sep 2025 14:44:57 +0300 Subject: [PATCH 003/107] pinctrl: samsung: add exynos8890 SoC pinctrl configuration Add support for the pin-controller found on the exynos8890 SoC, used in Samsung Galaxy S7. Signed-off-by: Ivaylo Ivanov Reviewed-by: Igor Belwon Signed-off-by: Krzysztof Kozlowski --- .../pinctrl/samsung/pinctrl-exynos-arm64.c | 157 ++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + 3 files changed, 160 insertions(+) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index 323487dfa8c2..3258147decca 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -1485,6 +1485,163 @@ const struct samsung_pinctrl_of_match_data exynosautov920_of_data __initconst = .num_ctrl = ARRAY_SIZE(exynosautov920_pin_ctrl), }; +/* pin banks of exynos8890 pin-controller 0 (ALIVE) */ +static const struct samsung_pin_bank_data exynos8890_pin_banks0[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS7870_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), + EXYNOS7870_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), + EXYNOS7870_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), + EXYNOS7870_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), +}; + +/* pin banks of exynos8890 pin-controller 1 (AUD) */ +static const struct samsung_pin_bank_data exynos8890_pin_banks1[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS8895_PIN_BANK_EINTG(7, 0x000, "gph0", 0x00), +}; + +/* pin banks of exynos8890 pin-controller 2 (CCORE) */ +static const struct samsung_pin_bank_data exynos8890_pin_banks2[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS8895_PIN_BANK_EINTG(2, 0x000, "etc0", 0x00), +}; + +/* pin banks of exynos8890 pin-controller 3 (ESE) */ +static const struct samsung_pin_bank_data exynos8890_pin_banks3[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS8895_PIN_BANK_EINTG(5, 0x000, "gpf3", 0x00), +}; + +/* pin banks of exynos8890 pin-controller 4 (FP) */ +static const struct samsung_pin_bank_data exynos8890_pin_banks4[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS8895_PIN_BANK_EINTG(4, 0x000, "gpf2", 0x00), +}; + +/* pin banks of exynos8890 pin-controller 5 (FSYS0) */ +static const struct samsung_pin_bank_data exynos8890_pin_banks5[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS8895_PIN_BANK_EINTG(4, 0x000, "gpi1", 0x00), + EXYNOS8895_PIN_BANK_EINTG(8, 0x020, "gpi2", 0x04), +}; + +/* pin banks of exynos8890 pin-controller 6 (FSYS1) */ +static const struct samsung_pin_bank_data exynos8890_pin_banks6[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS8895_PIN_BANK_EINTG(7, 0x000, "gpj0", 0x00), +}; + +/* pin banks of exynos8890 pin-controller 7 (NFC) */ +static const struct samsung_pin_bank_data exynos8890_pin_banks7[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpf0", 0x00), +}; + +/* pin banks of exynos8890 pin-controller 8 (PERIC0) */ +static const struct samsung_pin_bank_data exynos8890_pin_banks8[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS8895_PIN_BANK_EINTG(6, 0x000, "gpi0", 0x00), + EXYNOS8895_PIN_BANK_EINTG(8, 0x020, "gpd0", 0x04), + EXYNOS8895_PIN_BANK_EINTG(6, 0x040, "gpd1", 0x08), + EXYNOS8895_PIN_BANK_EINTG(4, 0x060, "gpd2", 0x0c), + EXYNOS8895_PIN_BANK_EINTG(4, 0x080, "gpd3", 0x10), + EXYNOS8895_PIN_BANK_EINTG(2, 0x0A0, "gpb1", 0x14), + EXYNOS8895_PIN_BANK_EINTG(2, 0x0C0, "gpb2", 0x18), + EXYNOS8895_PIN_BANK_EINTG(3, 0x0E0, "gpb0", 0x1c), + EXYNOS8895_PIN_BANK_EINTG(5, 0x100, "gpc0", 0x20), + EXYNOS8895_PIN_BANK_EINTG(5, 0x120, "gpc1", 0x24), + EXYNOS8895_PIN_BANK_EINTG(6, 0x140, "gpc2", 0x28), + EXYNOS8895_PIN_BANK_EINTG(8, 0x160, "gpc3", 0x2c), + EXYNOS8895_PIN_BANK_EINTG(4, 0x180, "gpk0", 0x30), + EXYNOS8895_PIN_BANK_EINTG(7, 0x1A0, "etc1", 0x34), +}; + +/* pin banks of exynos8890 pin-controller 9 (PERIC1) */ +static const struct samsung_pin_bank_data exynos8890_pin_banks9[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS8895_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), + EXYNOS8895_PIN_BANK_EINTG(8, 0x020, "gpe5", 0x04), + EXYNOS8895_PIN_BANK_EINTG(8, 0x040, "gpe6", 0x08), + EXYNOS8895_PIN_BANK_EINTG(8, 0x060, "gpj1", 0x0c), + EXYNOS8895_PIN_BANK_EINTG(2, 0x080, "gpj2", 0x10), + EXYNOS8895_PIN_BANK_EINTG(8, 0x0A0, "gpe2", 0x14), + EXYNOS8895_PIN_BANK_EINTG(8, 0x0C0, "gpe3", 0x18), + EXYNOS8895_PIN_BANK_EINTG(8, 0x0E0, "gpe4", 0x1c), + EXYNOS8895_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20), + EXYNOS8895_PIN_BANK_EINTG(4, 0x120, "gpe7", 0x24), + EXYNOS8895_PIN_BANK_EINTG(3, 0x140, "gpg0", 0x28), +}; + +/* pin banks of exynos8890 pin-controller 10 (TOUCH) */ +static const struct samsung_pin_bank_data exynos8890_pin_banks10[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpf1", 0x00), +}; + +static const struct samsung_pin_ctrl exynos8890_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 Alive data */ + .pin_banks = exynos8890_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos8890_pin_banks0), + .eint_wkup_init = exynos_eint_wkup_init, + }, { + /* pin-controller instance 1 AUD data */ + .pin_banks = exynos8890_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos8890_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 2 CCORE data */ + .pin_banks = exynos8890_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos8890_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 3 ESE data */ + .pin_banks = exynos8890_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos8890_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 4 FP data */ + .pin_banks = exynos8890_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos8890_pin_banks4), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 5 FSYS0 data */ + .pin_banks = exynos8890_pin_banks5, + .nr_banks = ARRAY_SIZE(exynos8890_pin_banks5), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 6 FSYS1 data */ + .pin_banks = exynos8890_pin_banks6, + .nr_banks = ARRAY_SIZE(exynos8890_pin_banks6), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 7 NFC data */ + .pin_banks = exynos8890_pin_banks7, + .nr_banks = ARRAY_SIZE(exynos8890_pin_banks7), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 8 PERIC0 data */ + .pin_banks = exynos8890_pin_banks8, + .nr_banks = ARRAY_SIZE(exynos8890_pin_banks8), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 9 PERIC1 data */ + .pin_banks = exynos8890_pin_banks9, + .nr_banks = ARRAY_SIZE(exynos8890_pin_banks9), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 10 TOUCH data */ + .pin_banks = exynos8890_pin_banks10, + .nr_banks = ARRAY_SIZE(exynos8890_pin_banks10), + .eint_gpio_init = exynos_eint_gpio_init, + }, +}; + +const struct samsung_pinctrl_of_match_data exynos8890_of_data __initconst = { + .ctrl = exynos8890_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos8890_pin_ctrl), +}; + /* pin banks of exynos8895 pin-controller 0 (ALIVE) */ static const struct samsung_pin_bank_data exynos8895_pin_banks0[] __initconst = { EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa0", 0x00), diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index c099195fc464..7974122799c4 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1498,6 +1498,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = &exynos7885_of_data }, { .compatible = "samsung,exynos850-pinctrl", .data = &exynos850_of_data }, + { .compatible = "samsung,exynos8890-pinctrl", + .data = &exynos8890_of_data }, { .compatible = "samsung,exynos8895-pinctrl", .data = &exynos8895_of_data }, { .compatible = "samsung,exynos9810-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index 3e8ef91d94a3..d00079ad673c 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -395,6 +395,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7_of_data; extern const struct samsung_pinctrl_of_match_data exynos7870_of_data; extern const struct samsung_pinctrl_of_match_data exynos7885_of_data; extern const struct samsung_pinctrl_of_match_data exynos850_of_data; +extern const struct samsung_pinctrl_of_match_data exynos8890_of_data; extern const struct samsung_pinctrl_of_match_data exynos8895_of_data; extern const struct samsung_pinctrl_of_match_data exynos9810_of_data; extern const struct samsung_pinctrl_of_match_data exynos990_of_data; From e671a1bb5d1cf9ca4dbab61b9a3e1e77579f99ba Mon Sep 17 00:00:00 2001 From: SeonGu Kang Date: Wed, 17 Sep 2025 12:30:03 +0530 Subject: [PATCH 004/107] dt-bindings: pinctrl: samsung: Add compatible for ARTPEC-9 SoC Document the compatible string for ARTPEC-9 SoC pinctrl block, which is similar to other Samsung SoC pinctrl blocks. Signed-off-by: SeonGu Kang Signed-off-by: Ravi Patel Acked-by: Conor Dooley Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml index 076d960a62c9..ddc5e2efff21 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml @@ -36,6 +36,7 @@ properties: compatible: enum: - axis,artpec8-pinctrl + - axis,artpec9-pinctrl - google,gs101-pinctrl - samsung,s3c64xx-pinctrl - samsung,s5pv210-pinctrl From 3cfc60e09bdc95483875f0b63cfdc23aea67135b Mon Sep 17 00:00:00 2001 From: SeonGu Kang Date: Wed, 17 Sep 2025 12:30:04 +0530 Subject: [PATCH 005/107] pinctrl: samsung: Add ARTPEC-9 SoC specific configuration Add Axis ARTPEC-9 SoC specific configuration data to enable pinctrl. Signed-off-by: SeonGu Kang Signed-off-by: Ravi Patel Signed-off-by: Krzysztof Kozlowski --- .../pinctrl/samsung/pinctrl-exynos-arm64.c | 49 +++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + 3 files changed, 52 insertions(+) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index 3258147decca..627dca504d7a 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -2023,3 +2023,52 @@ const struct samsung_pinctrl_of_match_data artpec8_of_data __initconst = { .ctrl = artpec8_pin_ctrl, .num_ctrl = ARRAY_SIZE(artpec8_pin_ctrl), }; + +/* pin banks of artpec9 pin-controller (FSYS0) */ +static const struct samsung_pin_bank_data artpec9_pin_banks0[] __initconst = { + ARTPEC_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00), + ARTPEC_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04), + ARTPEC_PIN_BANK_EINTG(8, 0x040, "gpe0", 0x08), + ARTPEC_PIN_BANK_EINTG(8, 0x060, "gpe1", 0x0c), + ARTPEC_PIN_BANK_EINTG(8, 0x080, "gpe2", 0x10), + ARTPEC_PIN_BANK_EINTG(8, 0x0a0, "gpe3", 0x14), + ARTPEC_PIN_BANK_EINTG(2, 0x0c0, "gpe4", 0x18), + ARTPEC_PIN_BANK_EINTG(8, 0x0e0, "gps0", 0x1c), + ARTPEC_PIN_BANK_EINTG(8, 0x100, "gps1", 0x20), + ARTPEC_PIN_BANK_EINTG(5, 0x120, "gpi0", 0x24), +}; + +/* pin banks of artpec9 pin-controller (FSYS1) */ +static const struct samsung_pin_bank_data artpec9_pin_banks1[] __initconst = { + ARTPEC_PIN_BANK_EINTG(2, 0x000, "gpu0", 0x00), +}; + +/* pin banks of artpec9 pin-controller (PERIC) */ +static const struct samsung_pin_bank_data artpec9_pin_banks2[] __initconst = { + ARTPEC_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + ARTPEC_PIN_BANK_EINTG(8, 0x020, "gpa1", 0x04), +}; + +static const struct samsung_pin_ctrl artpec9_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 FSYS0 data */ + .pin_banks = artpec9_pin_banks0, + .nr_banks = ARRAY_SIZE(artpec9_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 1 FSYS1 data */ + .pin_banks = artpec9_pin_banks1, + .nr_banks = ARRAY_SIZE(artpec9_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 2 PERIC data */ + .pin_banks = artpec9_pin_banks2, + .nr_banks = ARRAY_SIZE(artpec9_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + }, +}; + +const struct samsung_pinctrl_of_match_data artpec9_of_data __initconst = { + .ctrl = artpec9_pin_ctrl, + .num_ctrl = ARRAY_SIZE(artpec9_pin_ctrl), +}; diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 7974122799c4..e374effba25a 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1484,6 +1484,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { #ifdef CONFIG_PINCTRL_EXYNOS_ARM64 { .compatible = "axis,artpec8-pinctrl", .data = &artpec8_of_data }, + { .compatible = "axis,artpec9-pinctrl", + .data = &artpec9_of_data }, { .compatible = "google,gs101-pinctrl", .data = &gs101_of_data }, { .compatible = "samsung,exynos2200-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index d00079ad673c..0f7b2ea98158 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -382,6 +382,7 @@ struct samsung_pmx_func { /* list of all exported SoC specific data */ extern const struct samsung_pinctrl_of_match_data artpec8_of_data; +extern const struct samsung_pinctrl_of_match_data artpec9_of_data; extern const struct samsung_pinctrl_of_match_data exynos2200_of_data; extern const struct samsung_pinctrl_of_match_data exynos3250_of_data; extern const struct samsung_pinctrl_of_match_data exynos4210_of_data; From d8d357b8a54f02ac5177ae5a69e0b47ea1cf584f Mon Sep 17 00:00:00 2001 From: Igor Belwon Date: Mon, 15 Sep 2025 14:46:23 +0200 Subject: [PATCH 006/107] dt-bindings: pinctrl: mediatek: Document MT6878 pin controller bindings Add device-tree bindings for the pin controller and the EINT controller found in the MediaTek MT6878 SoC. Signed-off-by: Igor Belwon Reviewed-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- .../pinctrl/mediatek,mt6878-pinctrl.yaml | 211 ++++++++++++++++++ 1 file changed, 211 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt6878-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6878-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6878-pinctrl.yaml new file mode 100644 index 000000000000..8d44194a7938 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6878-pinctrl.yaml @@ -0,0 +1,211 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6878-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6878 Pin Controller + +maintainers: + - AngeloGioacchino Del Regno + - Igor Belwon + +description: + The MediaTek MT6878 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt6878-pinctrl + + reg: + items: + - description: pin controller base + - description: bl group IO + - description: bm group IO + - description: br group IO + - description: bl1 group IO + - description: br1 group IO + - description: lm group IO + - description: lt group IO + - description: rm group IO + - description: rt group IO + - description: EINT controller E block + - description: EINT controller S block + - description: EINT controller W block + - description: EINT controller C block + + reg-names: + items: + - const: base + - const: bl + - const: bm + - const: br + - const: bl1 + - const: br1 + - const: lm + - const: lt + - const: rm + - const: rt + - const: eint-e + - const: eint-s + - const: eint-w + - const: eint-c + + gpio-controller: true + + '#gpio-cells': + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-line-names: + maxItems: 216 + + interrupts: + description: The interrupt outputs to sysirq + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +# PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^pins': + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + description: + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + + properties: + pinmux: + description: + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux are defined as macros in + arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h for this SoC. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + drive-strength-microamp: + enum: [125, 250, 500, 1000] + + bias-pull-down: + oneOf: + - type: boolean + - enum: [75000, 5000] + description: Pull down RSEL type resistance values (in ohms) + description: + For normal pull down type there is no need to specify a resistance + value, hence this can be specified as a boolean property. + For RSEL pull down type a resistance value (in ohms) can be added. + + bias-pull-up: + oneOf: + - type: boolean + - enum: [10000, 5000, 4000, 3000] + description: Pull up RSEL type resistance values (in ohms) + description: + For normal pull up type there is no need to specify a resistance + value, hence this can be specified as a boolean property. + For RSEL pull up type a resistance value (in ohms) can be added. + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + #include + #define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) + #define PINMUX_GPIO99__FUNC_SCL0 (MTK_PIN_NO(99) | 1) + #define PINMUX_GPIO100__FUNC_SDA0 (MTK_PIN_NO(100) | 1) + + pio: pinctrl@10005000 { + compatible = "mediatek,mt6878-pinctrl"; + reg = <0x10005000 0x1000>, + <0x11d10000 0x1000>, + <0x11d30000 0x1000>, + <0x11d40000 0x1000>, + <0x11d50000 0x1000>, + <0x11d60000 0x1000>, + <0x11e20000 0x1000>, + <0x11e30000 0x1000>, + <0x11eb0000 0x1000>, + <0x11ec0000 0x1000>, + <0x11ce0000 0x1000>, + <0x11de0000 0x1000>, + <0x11e60000 0x1000>, + <0x1c01e000 0x1000>; + reg-names = "base", "bl", "bm", "br", "bl1", "br1", + "lm", "lt", "rm", "rt", "eint-e", "eint-s", + "eint-w", "eint-c"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 220>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + + gpio-pins { + pins { + pinmux = ; + bias-pull-up = <4000>; + drive-strength = <6>; + }; + }; + + i2c0-pins { + pins-bus { + pinmux = , + ; + bias-pull-down = <75000>; + drive-strength-microamp = <1000>; + }; + }; + }; From 18349bfb391aa32ec7bb2c3496e1239196a51545 Mon Sep 17 00:00:00 2001 From: Igor Belwon Date: Mon, 15 Sep 2025 14:46:24 +0200 Subject: [PATCH 007/107] pinctrl: mediatek: Add debounce times for MT6878 MT6878 uses different debounce times than other SoCs. Add them to the EINT driver. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Igor Belwon Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/mtk-eint.c | 5 +++++ drivers/pinctrl/mediatek/mtk-eint.h | 1 + 2 files changed, 6 insertions(+) diff --git a/drivers/pinctrl/mediatek/mtk-eint.c b/drivers/pinctrl/mediatek/mtk-eint.c index 9f175c73613f..c8c5097c11c4 100644 --- a/drivers/pinctrl/mediatek/mtk-eint.c +++ b/drivers/pinctrl/mediatek/mtk-eint.c @@ -66,6 +66,11 @@ const unsigned int debounce_time_mt6795[] = { }; EXPORT_SYMBOL_GPL(debounce_time_mt6795); +const unsigned int debounce_time_mt6878[] = { + 156, 313, 625, 1250, 20000, 40000, 80000, 160000, 320000, 640000, 0 +}; +EXPORT_SYMBOL_GPL(debounce_time_mt6878); + static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint, unsigned int eint_num, unsigned int offset) diff --git a/drivers/pinctrl/mediatek/mtk-eint.h b/drivers/pinctrl/mediatek/mtk-eint.h index fc31a4c0c77b..3cdd6f6310cd 100644 --- a/drivers/pinctrl/mediatek/mtk-eint.h +++ b/drivers/pinctrl/mediatek/mtk-eint.h @@ -52,6 +52,7 @@ struct mtk_eint_pin { extern const unsigned int debounce_time_mt2701[]; extern const unsigned int debounce_time_mt6765[]; extern const unsigned int debounce_time_mt6795[]; +extern const unsigned int debounce_time_mt6878[]; struct mtk_eint; From 89c13ea3ab6ddf2b526915aa4190aec72cd202ed Mon Sep 17 00:00:00 2001 From: Igor Belwon Date: Mon, 15 Sep 2025 14:46:25 +0200 Subject: [PATCH 008/107] pinctrl: mediatek: Add support for MT6878 pinctrl Add driver support for the pin controller found in the MediaTek Dimensity 7300 (MT6878) SoC. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Igor Belwon Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/Kconfig | 10 + drivers/pinctrl/mediatek/Makefile | 1 + drivers/pinctrl/mediatek/pinctrl-mt6878.c | 1478 +++++++++++ drivers/pinctrl/mediatek/pinctrl-mtk-mt6878.h | 2248 +++++++++++++++++ 4 files changed, 3737 insertions(+) create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt6878.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt6878.h diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 5b191e12a8aa..4819617d9368 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -181,6 +181,16 @@ config PINCTRL_MT6797 default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_PARIS +config PINCTRL_MT6878 + bool "MediaTek MT6878 pin control" + depends on OF + depends on ARM64 || COMPILE_TEST + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK_PARIS + help + Say yes here to support pin controller and gpio driver + on the MediaTek MT6878 SoC. + config PINCTRL_MT6893 bool "MediaTek Dimensity MT6893 pin control" depends on OF diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index 5d4646939ba3..ae765bd99965 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o obj-$(CONFIG_PINCTRL_MT6779) += pinctrl-mt6779.o obj-$(CONFIG_PINCTRL_MT6795) += pinctrl-mt6795.o obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o +obj-$(CONFIG_PINCTRL_MT6878) += pinctrl-mt6878.o obj-$(CONFIG_PINCTRL_MT6893) += pinctrl-mt6893.o obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6878.c b/drivers/pinctrl/mediatek/pinctrl-mt6878.c new file mode 100644 index 000000000000..b59ae089128a --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt6878.c @@ -0,0 +1,1478 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 MediaTek Inc. + * Author: Light Hsieh + * + * Copyright (C) 2025 Igor Belwon + */ + +#include +#include "pinctrl-mtk-mt6878.h" +#include "pinctrl-paris.h" + +/* MT6878 have multiple bases to program pin configuration listed as the below: + * GPIO_BASE: 0x10005000 + * IOCFG_BL_BASE: 0x11D10000 + * IOCFG_BM_BASE: 0x11D30000 + * IOCFG_BR_BASE: 0x11D40000 + * IOCFG_BL1_BASE: 0x11D50000 + * IOCFG_BR1_BASE: 0x11D60000 + * IOCFG_LM_BASE: 0x11E20000 + * IOCFG_LT_BASE: 0x11E30000 + * IOCFG_RM_BASE: 0x11EB0000 + * IOCFG_RT_BASE: 0x11EC0000 + * _i_based could be used to indicate what base the pin should be mapped into. + */ + +#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \ + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \ + 32, 0) + +#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \ + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \ + 32, 1) + +static const struct mtk_pin_field_calc mt6878_pin_mode_range[] = { + PIN_FIELD(0, 195, 0x300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt6878_pin_dir_range[] = { + PIN_FIELD(0, 195, 0x0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6878_pin_di_range[] = { + PIN_FIELD(0, 195, 0x200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6878_pin_do_range[] = { + PIN_FIELD(0, 195, 0x100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6878_pin_ies_range[] = { + PIN_FIELD_BASE(0, 0, 3, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(1, 1, 3, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(2, 2, 3, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, 3, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(4, 4, 3, 0x0070, 0x10, 13, 1), + PIN_FIELD_BASE(5, 5, 3, 0x0070, 0x10, 14, 1), + PIN_FIELD_BASE(6, 6, 4, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(7, 7, 4, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(8, 8, 4, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(9, 9, 4, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(10, 10, 4, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(11, 11, 4, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(12, 12, 4, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(13, 13, 6, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(14, 14, 6, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(15, 15, 6, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(16, 16, 6, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(17, 17, 6, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(18, 18, 6, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(19, 19, 3, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(20, 20, 3, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(21, 21, 3, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(22, 22, 3, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(23, 23, 3, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(24, 24, 5, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(25, 25, 3, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(26, 26, 3, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(27, 27, 3, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(28, 28, 3, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(29, 29, 6, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(30, 30, 6, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(31, 31, 6, 0x0070, 0x10, 13, 1), + PIN_FIELD_BASE(32, 32, 6, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(33, 33, 9, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(34, 34, 9, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(35, 35, 9, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(36, 36, 8, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(37, 37, 8, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, 8, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(39, 39, 8, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(40, 40, 8, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(41, 41, 4, 0x0050, 0x10, 20, 1), + PIN_FIELD_BASE(42, 42, 4, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(43, 43, 4, 0x0050, 0x10, 19, 1), + PIN_FIELD_BASE(44, 44, 4, 0x0050, 0x10, 21, 1), + PIN_FIELD_BASE(45, 45, 4, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(46, 46, 4, 0x0050, 0x10, 22, 1), + PIN_FIELD_BASE(47, 47, 4, 0x0050, 0x10, 23, 1), + PIN_FIELD_BASE(48, 48, 3, 0x0070, 0x10, 25, 1), + PIN_FIELD_BASE(49, 49, 3, 0x0070, 0x10, 23, 1), + PIN_FIELD_BASE(50, 50, 3, 0x0070, 0x10, 26, 1), + PIN_FIELD_BASE(51, 51, 3, 0x0070, 0x10, 24, 1), + PIN_FIELD_BASE(52, 52, 3, 0x0070, 0x10, 17, 1), + PIN_FIELD_BASE(53, 53, 3, 0x0070, 0x10, 18, 1), + PIN_FIELD_BASE(54, 54, 3, 0x0070, 0x10, 15, 1), + PIN_FIELD_BASE(55, 55, 3, 0x0070, 0x10, 16, 1), + PIN_FIELD_BASE(56, 56, 5, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(57, 57, 5, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(58, 58, 3, 0x0070, 0x10, 22, 1), + PIN_FIELD_BASE(59, 59, 3, 0x0070, 0x10, 21, 1), + PIN_FIELD_BASE(60, 60, 8, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(61, 61, 8, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(62, 62, 8, 0x0090, 0x10, 24, 1), + PIN_FIELD_BASE(63, 63, 8, 0x0090, 0x10, 23, 1), + PIN_FIELD_BASE(64, 64, 8, 0x0090, 0x10, 25, 1), + PIN_FIELD_BASE(65, 65, 8, 0x0090, 0x10, 26, 1), + PIN_FIELD_BASE(66, 66, 8, 0x0090, 0x10, 28, 1), + PIN_FIELD_BASE(67, 67, 8, 0x0090, 0x10, 27, 1), + PIN_FIELD_BASE(68, 68, 5, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(69, 69, 5, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(70, 70, 5, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(71, 71, 5, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(72, 72, 5, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(73, 73, 5, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(74, 74, 5, 0x0040, 0x10, 13, 1), + PIN_FIELD_BASE(75, 75, 5, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(76, 76, 5, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(77, 77, 2, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(78, 78, 2, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(79, 79, 2, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(80, 80, 2, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(81, 81, 2, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(82, 82, 2, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(83, 83, 2, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(84, 84, 2, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(85, 85, 2, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(86, 86, 2, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(87, 87, 2, 0x0040, 0x10, 14, 1), + PIN_FIELD_BASE(88, 88, 2, 0x0040, 0x10, 13, 1), + PIN_FIELD_BASE(89, 89, 4, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(90, 90, 4, 0x0050, 0x10, 24, 1), + PIN_FIELD_BASE(91, 91, 4, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(92, 92, 8, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(93, 93, 8, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(94, 94, 8, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(95, 95, 8, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(96, 96, 8, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(97, 97, 1, 0x0070, 0x10, 19, 1), + PIN_FIELD_BASE(98, 98, 1, 0x0070, 0x10, 18, 1), + PIN_FIELD_BASE(99, 99, 1, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(100, 100, 1, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(101, 101, 1, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(102, 102, 1, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(103, 103, 1, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(104, 104, 1, 0x0070, 0x10, 13, 1), + PIN_FIELD_BASE(105, 105, 1, 0x0070, 0x10, 14, 1), + PIN_FIELD_BASE(106, 106, 1, 0x0070, 0x10, 15, 1), + PIN_FIELD_BASE(107, 107, 1, 0x0070, 0x10, 16, 1), + PIN_FIELD_BASE(108, 108, 1, 0x0070, 0x10, 17, 1), + PIN_FIELD_BASE(109, 109, 1, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(110, 110, 1, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(111, 111, 1, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(112, 112, 1, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(113, 113, 1, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(114, 114, 1, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(115, 115, 1, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(116, 116, 1, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(117, 117, 1, 0x0070, 0x10, 20, 1), + PIN_FIELD_BASE(118, 118, 1, 0x0070, 0x10, 21, 1), + PIN_FIELD_BASE(119, 119, 1, 0x0070, 0x10, 22, 1), + PIN_FIELD_BASE(120, 120, 1, 0x0070, 0x10, 23, 1), + PIN_FIELD_BASE(121, 121, 1, 0x0070, 0x10, 24, 1), + PIN_FIELD_BASE(122, 122, 1, 0x0070, 0x10, 25, 1), + PIN_FIELD_BASE(123, 123, 1, 0x0070, 0x10, 26, 1), + PIN_FIELD_BASE(124, 124, 1, 0x0070, 0x10, 27, 1), + PIN_FIELD_BASE(125, 125, 8, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(126, 126, 8, 0x0090, 0x10, 29, 1), + PIN_FIELD_BASE(127, 127, 8, 0x0090, 0x10, 30, 1), + PIN_FIELD_BASE(128, 128, 8, 0x0090, 0x10, 31, 1), + PIN_FIELD_BASE(129, 129, 8, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(130, 130, 8, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(131, 131, 6, 0x0070, 0x10, 14, 1), + PIN_FIELD_BASE(132, 132, 6, 0x0070, 0x10, 17, 1), + PIN_FIELD_BASE(133, 133, 8, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(134, 134, 8, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(135, 135, 6, 0x0070, 0x10, 15, 1), + PIN_FIELD_BASE(136, 136, 6, 0x0070, 0x10, 18, 1), + PIN_FIELD_BASE(137, 137, 6, 0x0070, 0x10, 16, 1), + PIN_FIELD_BASE(138, 138, 6, 0x0070, 0x10, 19, 1), + PIN_FIELD_BASE(139, 139, 6, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(140, 140, 6, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(141, 141, 6, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(142, 142, 6, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(143, 143, 8, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(144, 144, 8, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(145, 145, 5, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(146, 146, 5, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(147, 147, 3, 0x0070, 0x10, 19, 1), + PIN_FIELD_BASE(148, 148, 3, 0x0070, 0x10, 20, 1), + PIN_FIELD_BASE(149, 149, 8, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(150, 150, 8, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(151, 151, 8, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(152, 152, 8, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(153, 153, 2, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(154, 154, 2, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(155, 155, 2, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(156, 156, 9, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(157, 157, 9, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(158, 158, 9, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(159, 159, 9, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(160, 160, 4, 0x0050, 0x10, 26, 1), + PIN_FIELD_BASE(161, 161, 4, 0x0050, 0x10, 25, 1), + PIN_FIELD_BASE(162, 162, 4, 0x0050, 0x10, 28, 1), + PIN_FIELD_BASE(163, 163, 4, 0x0050, 0x10, 27, 1), + PIN_FIELD_BASE(164, 164, 4, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(165, 165, 4, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(166, 166, 4, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(167, 167, 4, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(168, 168, 4, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(169, 169, 4, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(170, 170, 4, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(171, 171, 4, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(172, 172, 9, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(173, 173, 9, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(174, 174, 9, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(175, 175, 9, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(176, 176, 9, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(177, 177, 9, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(178, 178, 9, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(179, 179, 9, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(180, 180, 9, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(181, 181, 9, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(182, 182, 9, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(183, 183, 9, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(184, 184, 7, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(185, 185, 7, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(186, 186, 7, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(187, 187, 7, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(188, 188, 7, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(189, 189, 7, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(190, 190, 7, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(191, 191, 7, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(192, 192, 7, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(193, 193, 7, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(194, 194, 7, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(195, 195, 7, 0x0040, 0x10, 9, 1), +}; + +static const struct mtk_pin_field_calc mt6878_pin_smt_range[] = { + PIN_FIELD_BASE(0, 0, 3, 0x00e0, 0x10, 16, 1), + PIN_FIELD_BASE(1, 1, 3, 0x00e0, 0x10, 16, 1), + PIN_FIELD_BASE(2, 2, 3, 0x00e0, 0x10, 15, 1), + PIN_FIELD_BASE(3, 3, 3, 0x00e0, 0x10, 15, 1), + PIN_FIELD_BASE(4, 4, 3, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(5, 5, 3, 0x00e0, 0x10, 10, 1), + PIN_FIELD_BASE(6, 6, 4, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(7, 7, 4, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(8, 8, 4, 0x00b0, 0x10, 11, 1), + PIN_FIELD_BASE(9, 9, 4, 0x00b0, 0x10, 11, 1), + PIN_FIELD_BASE(10, 10, 4, 0x00b0, 0x10, 11, 1), + PIN_FIELD_BASE(11, 11, 4, 0x00b0, 0x10, 11, 1), + PIN_FIELD_BASE(12, 12, 4, 0x00b0, 0x10, 11, 1), + PIN_FIELD_BASE(13, 13, 6, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(14, 14, 6, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(15, 15, 6, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(16, 16, 6, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(17, 17, 6, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(18, 18, 6, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(19, 19, 3, 0x00e0, 0x10, 0, 1), + PIN_FIELD_BASE(20, 20, 3, 0x00e0, 0x10, 1, 1), + PIN_FIELD_BASE(21, 21, 3, 0x00e0, 0x10, 2, 1), + PIN_FIELD_BASE(22, 22, 3, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(23, 23, 3, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(24, 24, 5, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(25, 25, 3, 0x00e0, 0x10, 5, 1), + PIN_FIELD_BASE(26, 26, 3, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(27, 27, 3, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(28, 28, 3, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(29, 29, 6, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(30, 30, 6, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(31, 31, 6, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(32, 32, 6, 0x00e0, 0x10, 5, 1), + PIN_FIELD_BASE(33, 33, 9, 0x00f0, 0x10, 0, 1), + PIN_FIELD_BASE(34, 34, 9, 0x00f0, 0x10, 1, 1), + PIN_FIELD_BASE(35, 35, 9, 0x00f0, 0x10, 2, 1), + PIN_FIELD_BASE(36, 36, 8, 0x0130, 0x10, 0, 1), + PIN_FIELD_BASE(37, 37, 8, 0x0130, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, 8, 0x0130, 0x10, 2, 1), + PIN_FIELD_BASE(39, 39, 8, 0x0130, 0x10, 3, 1), + PIN_FIELD_BASE(40, 40, 8, 0x0130, 0x10, 4, 1), + PIN_FIELD_BASE(41, 41, 4, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(42, 42, 4, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(43, 43, 4, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(44, 44, 4, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(45, 45, 4, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(46, 46, 4, 0x00b0, 0x10, 12, 1), + PIN_FIELD_BASE(47, 47, 4, 0x00b0, 0x10, 12, 1), + PIN_FIELD_BASE(48, 48, 3, 0x00e0, 0x10, 16, 1), + PIN_FIELD_BASE(49, 49, 3, 0x00e0, 0x10, 16, 1), + PIN_FIELD_BASE(50, 50, 3, 0x00e0, 0x10, 14, 1), + PIN_FIELD_BASE(51, 51, 3, 0x00e0, 0x10, 14, 1), + PIN_FIELD_BASE(52, 52, 3, 0x00e0, 0x10, 12, 1), + PIN_FIELD_BASE(53, 53, 3, 0x00e0, 0x10, 13, 1), + PIN_FIELD_BASE(54, 54, 3, 0x00e0, 0x10, 17, 1), + PIN_FIELD_BASE(55, 55, 3, 0x00e0, 0x10, 11, 1), + PIN_FIELD_BASE(56, 56, 5, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(57, 57, 5, 0x00b0, 0x10, 9, 1), + PIN_FIELD_BASE(58, 58, 3, 0x00e0, 0x10, 21, 1), + PIN_FIELD_BASE(59, 59, 3, 0x00e0, 0x10, 20, 1), + PIN_FIELD_BASE(60, 60, 8, 0x0130, 0x10, 20, 1), + PIN_FIELD_BASE(61, 61, 8, 0x0130, 0x10, 21, 1), + PIN_FIELD_BASE(62, 62, 8, 0x0130, 0x10, 23, 1), + PIN_FIELD_BASE(63, 63, 8, 0x0130, 0x10, 22, 1), + PIN_FIELD_BASE(64, 64, 8, 0x0130, 0x10, 24, 1), + PIN_FIELD_BASE(65, 65, 8, 0x0130, 0x10, 25, 1), + PIN_FIELD_BASE(66, 66, 8, 0x0130, 0x10, 27, 1), + PIN_FIELD_BASE(67, 67, 8, 0x0130, 0x10, 26, 1), + PIN_FIELD_BASE(68, 68, 5, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(69, 69, 5, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(70, 70, 5, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(71, 71, 5, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(72, 72, 5, 0x00b0, 0x10, 10, 1), + PIN_FIELD_BASE(73, 73, 5, 0x00b0, 0x10, 11, 1), + PIN_FIELD_BASE(74, 74, 5, 0x00b0, 0x10, 13, 1), + PIN_FIELD_BASE(75, 75, 5, 0x00b0, 0x10, 12, 1), + PIN_FIELD_BASE(76, 76, 5, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(77, 77, 2, 0x00e0, 0x10, 0, 1), + PIN_FIELD_BASE(78, 78, 2, 0x00e0, 0x10, 1, 1), + PIN_FIELD_BASE(79, 79, 2, 0x00e0, 0x10, 2, 1), + PIN_FIELD_BASE(80, 80, 2, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(81, 81, 2, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(82, 82, 2, 0x00e0, 0x10, 5, 1), + PIN_FIELD_BASE(83, 83, 2, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(84, 84, 2, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(85, 85, 2, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(86, 86, 2, 0x00e0, 0x10, 10, 1), + PIN_FIELD_BASE(87, 87, 2, 0x00e0, 0x10, 12, 1), + PIN_FIELD_BASE(88, 88, 2, 0x00e0, 0x10, 11, 1), + PIN_FIELD_BASE(89, 89, 4, 0x00b0, 0x10, 12, 1), + PIN_FIELD_BASE(90, 90, 4, 0x00b0, 0x10, 13, 1), + PIN_FIELD_BASE(91, 91, 4, 0x00b0, 0x10, 12, 1), + PIN_FIELD_BASE(92, 92, 8, 0x0130, 0x10, 5, 1), + PIN_FIELD_BASE(93, 93, 8, 0x0130, 0x10, 6, 1), + PIN_FIELD_BASE(94, 94, 8, 0x0130, 0x10, 7, 1), + PIN_FIELD_BASE(95, 95, 8, 0x0130, 0x10, 8, 1), + PIN_FIELD_BASE(96, 96, 8, 0x0130, 0x10, 9, 1), + PIN_FIELD_BASE(97, 97, 1, 0x0120, 0x10, 25, 1), + PIN_FIELD_BASE(98, 98, 1, 0x0120, 0x10, 25, 1), + PIN_FIELD_BASE(99, 99, 1, 0x0120, 0x10, 0, 1), + PIN_FIELD_BASE(100, 100, 1, 0x0120, 0x10, 1, 1), + PIN_FIELD_BASE(101, 101, 1, 0x0120, 0x10, 10, 1), + PIN_FIELD_BASE(102, 102, 1, 0x0120, 0x10, 11, 1), + PIN_FIELD_BASE(103, 103, 1, 0x0120, 0x10, 12, 1), + PIN_FIELD_BASE(104, 104, 1, 0x0120, 0x10, 13, 1), + PIN_FIELD_BASE(105, 105, 1, 0x0120, 0x10, 14, 1), + PIN_FIELD_BASE(106, 106, 1, 0x0120, 0x10, 15, 1), + PIN_FIELD_BASE(107, 107, 1, 0x0120, 0x10, 16, 1), + PIN_FIELD_BASE(108, 108, 1, 0x0120, 0x10, 17, 1), + PIN_FIELD_BASE(109, 109, 1, 0x0120, 0x10, 2, 1), + PIN_FIELD_BASE(110, 110, 1, 0x0120, 0x10, 3, 1), + PIN_FIELD_BASE(111, 111, 1, 0x0120, 0x10, 4, 1), + PIN_FIELD_BASE(112, 112, 1, 0x0120, 0x10, 5, 1), + PIN_FIELD_BASE(113, 113, 1, 0x0120, 0x10, 6, 1), + PIN_FIELD_BASE(114, 114, 1, 0x0120, 0x10, 7, 1), + PIN_FIELD_BASE(115, 115, 1, 0x0120, 0x10, 8, 1), + PIN_FIELD_BASE(116, 116, 1, 0x0120, 0x10, 9, 1), + PIN_FIELD_BASE(117, 117, 1, 0x0120, 0x10, 18, 1), + PIN_FIELD_BASE(118, 118, 1, 0x0120, 0x10, 19, 1), + PIN_FIELD_BASE(119, 119, 1, 0x0120, 0x10, 20, 1), + PIN_FIELD_BASE(120, 120, 1, 0x0120, 0x10, 21, 1), + PIN_FIELD_BASE(121, 121, 1, 0x0120, 0x10, 22, 1), + PIN_FIELD_BASE(122, 122, 1, 0x0120, 0x10, 23, 1), + PIN_FIELD_BASE(123, 123, 1, 0x0120, 0x10, 24, 1), + PIN_FIELD_BASE(124, 124, 1, 0x0120, 0x10, 24, 1), + PIN_FIELD_BASE(125, 125, 8, 0x0130, 0x10, 19, 1), + PIN_FIELD_BASE(126, 126, 8, 0x0130, 0x10, 28, 1), + PIN_FIELD_BASE(127, 127, 8, 0x0130, 0x10, 29, 1), + PIN_FIELD_BASE(128, 128, 8, 0x0130, 0x10, 30, 1), + PIN_FIELD_BASE(129, 129, 8, 0x0130, 0x10, 10, 1), + PIN_FIELD_BASE(130, 130, 8, 0x0130, 0x10, 13, 1), + PIN_FIELD_BASE(131, 131, 6, 0x00e0, 0x10, 10, 1), + PIN_FIELD_BASE(132, 132, 6, 0x00e0, 0x10, 13, 1), + PIN_FIELD_BASE(133, 133, 8, 0x0130, 0x10, 11, 1), + PIN_FIELD_BASE(134, 134, 8, 0x0130, 0x10, 14, 1), + PIN_FIELD_BASE(135, 135, 6, 0x00e0, 0x10, 11, 1), + PIN_FIELD_BASE(136, 136, 6, 0x00e0, 0x10, 14, 1), + PIN_FIELD_BASE(137, 137, 6, 0x00e0, 0x10, 12, 1), + PIN_FIELD_BASE(138, 138, 6, 0x00e0, 0x10, 15, 1), + PIN_FIELD_BASE(139, 139, 6, 0x00e0, 0x10, 0, 1), + PIN_FIELD_BASE(140, 140, 6, 0x00e0, 0x10, 2, 1), + PIN_FIELD_BASE(141, 141, 6, 0x00e0, 0x10, 1, 1), + PIN_FIELD_BASE(142, 142, 6, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(143, 143, 8, 0x0130, 0x10, 12, 1), + PIN_FIELD_BASE(144, 144, 8, 0x0130, 0x10, 15, 1), + PIN_FIELD_BASE(145, 145, 5, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(146, 146, 5, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(147, 147, 3, 0x00e0, 0x10, 18, 1), + PIN_FIELD_BASE(148, 148, 3, 0x00e0, 0x10, 19, 1), + PIN_FIELD_BASE(149, 149, 8, 0x0130, 0x10, 16, 1), + PIN_FIELD_BASE(150, 150, 8, 0x0130, 0x10, 17, 1), + PIN_FIELD_BASE(151, 151, 8, 0x0130, 0x10, 18, 1), + PIN_FIELD_BASE(152, 152, 8, 0x0130, 0x10, 18, 1), + PIN_FIELD_BASE(153, 153, 2, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(154, 154, 2, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(155, 155, 2, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(156, 156, 9, 0x00f0, 0x10, 7, 1), + PIN_FIELD_BASE(157, 157, 9, 0x00f0, 0x10, 8, 1), + PIN_FIELD_BASE(158, 158, 9, 0x00f0, 0x10, 9, 1), + PIN_FIELD_BASE(159, 159, 9, 0x00f0, 0x10, 10, 1), + PIN_FIELD_BASE(160, 160, 4, 0x00b0, 0x10, 13, 1), + PIN_FIELD_BASE(161, 161, 4, 0x00b0, 0x10, 13, 1), + PIN_FIELD_BASE(162, 162, 4, 0x00b0, 0x10, 13, 1), + PIN_FIELD_BASE(163, 163, 4, 0x00b0, 0x10, 9, 1), + PIN_FIELD_BASE(164, 164, 4, 0x00b0, 0x10, 10, 1), + PIN_FIELD_BASE(165, 165, 4, 0x00b0, 0x10, 10, 1), + PIN_FIELD_BASE(166, 166, 4, 0x00b0, 0x10, 10, 1), + PIN_FIELD_BASE(167, 167, 4, 0x00b0, 0x10, 10, 1), + PIN_FIELD_BASE(168, 168, 4, 0x00b0, 0x10, 10, 1), + PIN_FIELD_BASE(169, 169, 4, 0x00b0, 0x10, 10, 1), + PIN_FIELD_BASE(170, 170, 4, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(171, 171, 4, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(172, 172, 9, 0x00f0, 0x10, 5, 1), + PIN_FIELD_BASE(173, 173, 9, 0x00f0, 0x10, 5, 1), + PIN_FIELD_BASE(174, 174, 9, 0x00f0, 0x10, 5, 1), + PIN_FIELD_BASE(175, 175, 9, 0x00f0, 0x10, 5, 1), + PIN_FIELD_BASE(176, 176, 9, 0x00f0, 0x10, 5, 1), + PIN_FIELD_BASE(177, 177, 9, 0x00f0, 0x10, 5, 1), + PIN_FIELD_BASE(178, 178, 9, 0x00f0, 0x10, 6, 1), + PIN_FIELD_BASE(179, 179, 9, 0x00f0, 0x10, 6, 1), + PIN_FIELD_BASE(180, 180, 9, 0x00f0, 0x10, 6, 1), + PIN_FIELD_BASE(181, 181, 9, 0x00f0, 0x10, 3, 1), + PIN_FIELD_BASE(182, 182, 9, 0x00f0, 0x10, 4, 1), + PIN_FIELD_BASE(183, 183, 9, 0x00f0, 0x10, 5, 1), + PIN_FIELD_BASE(184, 184, 7, 0x00d0, 0x10, 10, 1), + PIN_FIELD_BASE(185, 185, 7, 0x00d0, 0x10, 0, 1), + PIN_FIELD_BASE(186, 186, 7, 0x00d0, 0x10, 1, 1), + PIN_FIELD_BASE(187, 187, 7, 0x00d0, 0x10, 11, 1), + PIN_FIELD_BASE(188, 188, 7, 0x00d0, 0x10, 2, 1), + PIN_FIELD_BASE(189, 189, 7, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(190, 190, 7, 0x00d0, 0x10, 4, 1), + PIN_FIELD_BASE(191, 191, 7, 0x00d0, 0x10, 5, 1), + PIN_FIELD_BASE(192, 192, 7, 0x00d0, 0x10, 6, 1), + PIN_FIELD_BASE(193, 193, 7, 0x00d0, 0x10, 7, 1), + PIN_FIELD_BASE(194, 194, 7, 0x00d0, 0x10, 8, 1), + PIN_FIELD_BASE(195, 195, 7, 0x00d0, 0x10, 9, 1), +}; + +static const struct mtk_pin_field_calc mt6878_pin_pu_range[] = { + PIN_FIELD_BASE(0, 0, 3, 0x00b0, 0x10, 9, 1), + PIN_FIELD_BASE(1, 1, 3, 0x00b0, 0x10, 10, 1), + PIN_FIELD_BASE(2, 2, 3, 0x00b0, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, 3, 0x00b0, 0x10, 12, 1), + PIN_FIELD_BASE(4, 4, 3, 0x00b0, 0x10, 13, 1), + PIN_FIELD_BASE(5, 5, 3, 0x00b0, 0x10, 14, 1), + PIN_FIELD_BASE(6, 6, 4, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(7, 7, 4, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(8, 8, 4, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(9, 9, 4, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(10, 10, 4, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(11, 11, 4, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(12, 12, 4, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(13, 13, 6, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(14, 14, 6, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(15, 15, 6, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(16, 16, 6, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(17, 17, 6, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(18, 18, 6, 0x00b0, 0x10, 9, 1), + PIN_FIELD_BASE(19, 19, 3, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(20, 20, 3, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(21, 21, 3, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(22, 22, 3, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(23, 23, 3, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(24, 24, 5, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(25, 25, 3, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(26, 26, 3, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(27, 27, 3, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(28, 28, 3, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(29, 29, 6, 0x00b0, 0x10, 10, 1), + PIN_FIELD_BASE(30, 30, 6, 0x00b0, 0x10, 12, 1), + PIN_FIELD_BASE(31, 31, 6, 0x00b0, 0x10, 13, 1), + PIN_FIELD_BASE(32, 32, 6, 0x00b0, 0x10, 11, 1), + PIN_FIELD_BASE(36, 36, 8, 0x00d0, 0x10, 0, 1), + PIN_FIELD_BASE(37, 37, 8, 0x00d0, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, 8, 0x00d0, 0x10, 2, 1), + PIN_FIELD_BASE(39, 39, 8, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(40, 40, 8, 0x00d0, 0x10, 4, 1), + PIN_FIELD_BASE(41, 41, 4, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(42, 42, 4, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(43, 43, 4, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(44, 44, 4, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(45, 45, 4, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(46, 46, 4, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(47, 47, 4, 0x0090, 0x10, 23, 1), + PIN_FIELD_BASE(48, 48, 3, 0x00b0, 0x10, 25, 1), + PIN_FIELD_BASE(49, 49, 3, 0x00b0, 0x10, 23, 1), + PIN_FIELD_BASE(50, 50, 3, 0x00b0, 0x10, 26, 1), + PIN_FIELD_BASE(51, 51, 3, 0x00b0, 0x10, 24, 1), + PIN_FIELD_BASE(52, 52, 3, 0x00b0, 0x10, 17, 1), + PIN_FIELD_BASE(53, 53, 3, 0x00b0, 0x10, 18, 1), + PIN_FIELD_BASE(54, 54, 3, 0x00b0, 0x10, 15, 1), + PIN_FIELD_BASE(55, 55, 3, 0x00b0, 0x10, 16, 1), + PIN_FIELD_BASE(56, 56, 5, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(57, 57, 5, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(58, 58, 3, 0x00b0, 0x10, 22, 1), + PIN_FIELD_BASE(59, 59, 3, 0x00b0, 0x10, 21, 1), + PIN_FIELD_BASE(60, 60, 8, 0x00d0, 0x10, 21, 1), + PIN_FIELD_BASE(61, 61, 8, 0x00d0, 0x10, 22, 1), + PIN_FIELD_BASE(62, 62, 8, 0x00d0, 0x10, 24, 1), + PIN_FIELD_BASE(63, 63, 8, 0x00d0, 0x10, 23, 1), + PIN_FIELD_BASE(64, 64, 8, 0x00d0, 0x10, 25, 1), + PIN_FIELD_BASE(65, 65, 8, 0x00d0, 0x10, 26, 1), + PIN_FIELD_BASE(66, 66, 8, 0x00d0, 0x10, 28, 1), + PIN_FIELD_BASE(67, 67, 8, 0x00d0, 0x10, 27, 1), + PIN_FIELD_BASE(68, 68, 5, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(69, 69, 5, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(70, 70, 5, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(71, 71, 5, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(72, 72, 5, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(73, 73, 5, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(74, 74, 5, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(75, 75, 5, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(76, 76, 5, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(89, 89, 4, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(90, 90, 4, 0x0090, 0x10, 24, 1), + PIN_FIELD_BASE(91, 91, 4, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(92, 92, 8, 0x00d0, 0x10, 5, 1), + PIN_FIELD_BASE(93, 93, 8, 0x00d0, 0x10, 6, 1), + PIN_FIELD_BASE(94, 94, 8, 0x00d0, 0x10, 7, 1), + PIN_FIELD_BASE(95, 95, 8, 0x00d0, 0x10, 8, 1), + PIN_FIELD_BASE(96, 96, 8, 0x00d0, 0x10, 9, 1), + PIN_FIELD_BASE(99, 99, 1, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(100, 100, 1, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(101, 101, 1, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(102, 102, 1, 0x00c0, 0x10, 11, 1), + PIN_FIELD_BASE(103, 103, 1, 0x00c0, 0x10, 12, 1), + PIN_FIELD_BASE(104, 104, 1, 0x00c0, 0x10, 13, 1), + PIN_FIELD_BASE(105, 105, 1, 0x00c0, 0x10, 14, 1), + PIN_FIELD_BASE(106, 106, 1, 0x00c0, 0x10, 15, 1), + PIN_FIELD_BASE(107, 107, 1, 0x00c0, 0x10, 16, 1), + PIN_FIELD_BASE(108, 108, 1, 0x00c0, 0x10, 17, 1), + PIN_FIELD_BASE(109, 109, 1, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(110, 110, 1, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(111, 111, 1, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(112, 112, 1, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(113, 113, 1, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(114, 114, 1, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(115, 115, 1, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(116, 116, 1, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(125, 125, 8, 0x00d0, 0x10, 20, 1), + PIN_FIELD_BASE(126, 126, 8, 0x00d0, 0x10, 29, 1), + PIN_FIELD_BASE(127, 127, 8, 0x00d0, 0x10, 30, 1), + PIN_FIELD_BASE(128, 128, 8, 0x00d0, 0x10, 31, 1), + PIN_FIELD_BASE(129, 129, 8, 0x00d0, 0x10, 10, 1), + PIN_FIELD_BASE(130, 130, 8, 0x00d0, 0x10, 13, 1), + PIN_FIELD_BASE(131, 131, 6, 0x00b0, 0x10, 14, 1), + PIN_FIELD_BASE(132, 132, 6, 0x00b0, 0x10, 17, 1), + PIN_FIELD_BASE(133, 133, 8, 0x00d0, 0x10, 11, 1), + PIN_FIELD_BASE(134, 134, 8, 0x00d0, 0x10, 14, 1), + PIN_FIELD_BASE(135, 135, 6, 0x00b0, 0x10, 15, 1), + PIN_FIELD_BASE(136, 136, 6, 0x00b0, 0x10, 18, 1), + PIN_FIELD_BASE(137, 137, 6, 0x00b0, 0x10, 16, 1), + PIN_FIELD_BASE(138, 138, 6, 0x00b0, 0x10, 19, 1), + PIN_FIELD_BASE(139, 139, 6, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(140, 140, 6, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(141, 141, 6, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(142, 142, 6, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(143, 143, 8, 0x00d0, 0x10, 12, 1), + PIN_FIELD_BASE(144, 144, 8, 0x00d0, 0x10, 15, 1), + PIN_FIELD_BASE(145, 145, 5, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(146, 146, 5, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(147, 147, 3, 0x00b0, 0x10, 19, 1), + PIN_FIELD_BASE(148, 148, 3, 0x00b0, 0x10, 20, 1), + PIN_FIELD_BASE(149, 149, 8, 0x00d0, 0x10, 16, 1), + PIN_FIELD_BASE(150, 150, 8, 0x00d0, 0x10, 17, 1), + PIN_FIELD_BASE(151, 151, 8, 0x00d0, 0x10, 18, 1), + PIN_FIELD_BASE(152, 152, 8, 0x00d0, 0x10, 19, 1), + PIN_FIELD_BASE(156, 156, 9, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(157, 157, 9, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(158, 158, 9, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(159, 159, 9, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(160, 160, 4, 0x0090, 0x10, 26, 1), + PIN_FIELD_BASE(161, 161, 4, 0x0090, 0x10, 25, 1), + PIN_FIELD_BASE(162, 162, 4, 0x0090, 0x10, 30, 1), + PIN_FIELD_BASE(163, 163, 4, 0x0090, 0x10, 29, 1), + PIN_FIELD_BASE(164, 164, 4, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(165, 165, 4, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(166, 166, 4, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(167, 167, 4, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(168, 168, 4, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(169, 169, 4, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(170, 170, 4, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(171, 171, 4, 0x0090, 0x10, 2, 1), +}; + +static const struct mtk_pin_field_calc mt6878_pin_pd_range[] = { + PIN_FIELD_BASE(0, 0, 3, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(1, 1, 3, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(2, 2, 3, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, 3, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(4, 4, 3, 0x00a0, 0x10, 13, 1), + PIN_FIELD_BASE(5, 5, 3, 0x00a0, 0x10, 14, 1), + PIN_FIELD_BASE(6, 6, 4, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(7, 7, 4, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(8, 8, 4, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(9, 9, 4, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(10, 10, 4, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(11, 11, 4, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(12, 12, 4, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(13, 13, 6, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(14, 14, 6, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(15, 15, 6, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(16, 16, 6, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(17, 17, 6, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(18, 18, 6, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(19, 19, 3, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(20, 20, 3, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(21, 21, 3, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(22, 22, 3, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(23, 23, 3, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(24, 24, 5, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(25, 25, 3, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(26, 26, 3, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(27, 27, 3, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(28, 28, 3, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(29, 29, 6, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(30, 30, 6, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(31, 31, 6, 0x00a0, 0x10, 13, 1), + PIN_FIELD_BASE(32, 32, 6, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(36, 36, 8, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(37, 37, 8, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, 8, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(39, 39, 8, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(40, 40, 8, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(41, 41, 4, 0x0080, 0x10, 20, 1), + PIN_FIELD_BASE(42, 42, 4, 0x0080, 0x10, 17, 1), + PIN_FIELD_BASE(43, 43, 4, 0x0080, 0x10, 19, 1), + PIN_FIELD_BASE(44, 44, 4, 0x0080, 0x10, 21, 1), + PIN_FIELD_BASE(45, 45, 4, 0x0080, 0x10, 18, 1), + PIN_FIELD_BASE(46, 46, 4, 0x0080, 0x10, 22, 1), + PIN_FIELD_BASE(47, 47, 4, 0x0080, 0x10, 23, 1), + PIN_FIELD_BASE(48, 48, 3, 0x00a0, 0x10, 25, 1), + PIN_FIELD_BASE(49, 49, 3, 0x00a0, 0x10, 23, 1), + PIN_FIELD_BASE(50, 50, 3, 0x00a0, 0x10, 26, 1), + PIN_FIELD_BASE(51, 51, 3, 0x00a0, 0x10, 24, 1), + PIN_FIELD_BASE(52, 52, 3, 0x00a0, 0x10, 17, 1), + PIN_FIELD_BASE(53, 53, 3, 0x00a0, 0x10, 18, 1), + PIN_FIELD_BASE(54, 54, 3, 0x00a0, 0x10, 15, 1), + PIN_FIELD_BASE(55, 55, 3, 0x00a0, 0x10, 16, 1), + PIN_FIELD_BASE(56, 56, 5, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(57, 57, 5, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(58, 58, 3, 0x00a0, 0x10, 22, 1), + PIN_FIELD_BASE(59, 59, 3, 0x00a0, 0x10, 21, 1), + PIN_FIELD_BASE(60, 60, 8, 0x00c0, 0x10, 21, 1), + PIN_FIELD_BASE(61, 61, 8, 0x00c0, 0x10, 22, 1), + PIN_FIELD_BASE(62, 62, 8, 0x00c0, 0x10, 24, 1), + PIN_FIELD_BASE(63, 63, 8, 0x00c0, 0x10, 23, 1), + PIN_FIELD_BASE(64, 64, 8, 0x00c0, 0x10, 25, 1), + PIN_FIELD_BASE(65, 65, 8, 0x00c0, 0x10, 26, 1), + PIN_FIELD_BASE(66, 66, 8, 0x00c0, 0x10, 28, 1), + PIN_FIELD_BASE(67, 67, 8, 0x00c0, 0x10, 27, 1), + PIN_FIELD_BASE(68, 68, 5, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(69, 69, 5, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(70, 70, 5, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(71, 71, 5, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(72, 72, 5, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(73, 73, 5, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(74, 74, 5, 0x0070, 0x10, 13, 1), + PIN_FIELD_BASE(75, 75, 5, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(76, 76, 5, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(89, 89, 4, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(90, 90, 4, 0x0080, 0x10, 24, 1), + PIN_FIELD_BASE(91, 91, 4, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(92, 92, 8, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(93, 93, 8, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(94, 94, 8, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(95, 95, 8, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(96, 96, 8, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(99, 99, 1, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(100, 100, 1, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(101, 101, 1, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(102, 102, 1, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(103, 103, 1, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(104, 104, 1, 0x00a0, 0x10, 13, 1), + PIN_FIELD_BASE(105, 105, 1, 0x00a0, 0x10, 14, 1), + PIN_FIELD_BASE(106, 106, 1, 0x00a0, 0x10, 15, 1), + PIN_FIELD_BASE(107, 107, 1, 0x00a0, 0x10, 16, 1), + PIN_FIELD_BASE(108, 108, 1, 0x00a0, 0x10, 17, 1), + PIN_FIELD_BASE(109, 109, 1, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(110, 110, 1, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(111, 111, 1, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(112, 112, 1, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(113, 113, 1, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(114, 114, 1, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(115, 115, 1, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(116, 116, 1, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(125, 125, 8, 0x00c0, 0x10, 20, 1), + PIN_FIELD_BASE(126, 126, 8, 0x00c0, 0x10, 29, 1), + PIN_FIELD_BASE(127, 127, 8, 0x00c0, 0x10, 30, 1), + PIN_FIELD_BASE(128, 128, 8, 0x00c0, 0x10, 31, 1), + PIN_FIELD_BASE(129, 129, 8, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(130, 130, 8, 0x00c0, 0x10, 13, 1), + PIN_FIELD_BASE(131, 131, 6, 0x00a0, 0x10, 14, 1), + PIN_FIELD_BASE(132, 132, 6, 0x00a0, 0x10, 17, 1), + PIN_FIELD_BASE(133, 133, 8, 0x00c0, 0x10, 11, 1), + PIN_FIELD_BASE(134, 134, 8, 0x00c0, 0x10, 14, 1), + PIN_FIELD_BASE(135, 135, 6, 0x00a0, 0x10, 15, 1), + PIN_FIELD_BASE(136, 136, 6, 0x00a0, 0x10, 18, 1), + PIN_FIELD_BASE(137, 137, 6, 0x00a0, 0x10, 16, 1), + PIN_FIELD_BASE(138, 138, 6, 0x00a0, 0x10, 19, 1), + PIN_FIELD_BASE(139, 139, 6, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(140, 140, 6, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(141, 141, 6, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(142, 142, 6, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(143, 143, 8, 0x00c0, 0x10, 12, 1), + PIN_FIELD_BASE(144, 144, 8, 0x00c0, 0x10, 15, 1), + PIN_FIELD_BASE(145, 145, 5, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(146, 146, 5, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(147, 147, 3, 0x00a0, 0x10, 19, 1), + PIN_FIELD_BASE(148, 148, 3, 0x00a0, 0x10, 20, 1), + PIN_FIELD_BASE(149, 149, 8, 0x00c0, 0x10, 16, 1), + PIN_FIELD_BASE(150, 150, 8, 0x00c0, 0x10, 17, 1), + PIN_FIELD_BASE(151, 151, 8, 0x00c0, 0x10, 18, 1), + PIN_FIELD_BASE(152, 152, 8, 0x00c0, 0x10, 19, 1), + PIN_FIELD_BASE(156, 156, 9, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(157, 157, 9, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(158, 158, 9, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(159, 159, 9, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(160, 160, 4, 0x0080, 0x10, 26, 1), + PIN_FIELD_BASE(161, 161, 4, 0x0080, 0x10, 25, 1), + PIN_FIELD_BASE(162, 162, 4, 0x0080, 0x10, 30, 1), + PIN_FIELD_BASE(163, 163, 4, 0x0080, 0x10, 29, 1), + PIN_FIELD_BASE(164, 164, 4, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(165, 165, 4, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(166, 166, 4, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(167, 167, 4, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(168, 168, 4, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(169, 169, 4, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(170, 170, 4, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(171, 171, 4, 0x0080, 0x10, 2, 1), +}; + +static const struct mtk_pin_field_calc mt6878_pin_pupd_range[] = { + PIN_FIELD_BASE(33, 33, 9, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(34, 34, 9, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(35, 35, 9, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(77, 77, 2, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(78, 78, 2, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(79, 79, 2, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(80, 80, 2, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(81, 81, 2, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(82, 82, 2, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(83, 83, 2, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(84, 84, 2, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(85, 85, 2, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(86, 86, 2, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(87, 87, 2, 0x0070, 0x10, 14, 1), + PIN_FIELD_BASE(88, 88, 2, 0x0070, 0x10, 13, 1), + PIN_FIELD_BASE(97, 97, 1, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(98, 98, 1, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(117, 117, 1, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(118, 118, 1, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(119, 119, 1, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(120, 120, 1, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(121, 121, 1, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(122, 122, 1, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(123, 123, 1, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(124, 124, 1, 0x00b0, 0x10, 9, 1), + PIN_FIELD_BASE(153, 153, 2, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(154, 154, 2, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(155, 155, 2, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(172, 172, 9, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(173, 173, 9, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(174, 174, 9, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(175, 175, 9, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(176, 176, 9, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(177, 177, 9, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(178, 178, 9, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(179, 179, 9, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(180, 180, 9, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(181, 181, 9, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(182, 182, 9, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(183, 183, 9, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(184, 184, 7, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(185, 185, 7, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(186, 186, 7, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(187, 187, 7, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(188, 188, 7, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(189, 189, 7, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(190, 190, 7, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(191, 191, 7, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(192, 192, 7, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(193, 193, 7, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(194, 194, 7, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(195, 195, 7, 0x0070, 0x10, 9, 1), +}; + +static const struct mtk_pin_field_calc mt6878_pin_r0_range[] = { + PIN_FIELD_BASE(33, 33, 9, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(34, 34, 9, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(35, 35, 9, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(77, 77, 2, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(78, 78, 2, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(79, 79, 2, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(80, 80, 2, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(81, 81, 2, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(82, 82, 2, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(83, 83, 2, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(84, 84, 2, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(85, 85, 2, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(86, 86, 2, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(87, 87, 2, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(88, 88, 2, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(97, 97, 1, 0x00d0, 0x10, 1, 1), + PIN_FIELD_BASE(98, 98, 1, 0x00d0, 0x10, 0, 1), + PIN_FIELD_BASE(117, 117, 1, 0x00d0, 0x10, 2, 1), + PIN_FIELD_BASE(118, 118, 1, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(119, 119, 1, 0x00d0, 0x10, 4, 1), + PIN_FIELD_BASE(120, 120, 1, 0x00d0, 0x10, 5, 1), + PIN_FIELD_BASE(121, 121, 1, 0x00d0, 0x10, 6, 1), + PIN_FIELD_BASE(122, 122, 1, 0x00d0, 0x10, 7, 1), + PIN_FIELD_BASE(123, 123, 1, 0x00d0, 0x10, 8, 1), + PIN_FIELD_BASE(124, 124, 1, 0x00d0, 0x10, 9, 1), + PIN_FIELD_BASE(153, 153, 2, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(154, 154, 2, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(155, 155, 2, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(172, 172, 9, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(173, 173, 9, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(174, 174, 9, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(175, 175, 9, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(176, 176, 9, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(177, 177, 9, 0x00b0, 0x10, 9, 1), + PIN_FIELD_BASE(178, 178, 9, 0x00b0, 0x10, 10, 1), + PIN_FIELD_BASE(179, 179, 9, 0x00b0, 0x10, 11, 1), + PIN_FIELD_BASE(180, 180, 9, 0x00b0, 0x10, 12, 1), + PIN_FIELD_BASE(181, 181, 9, 0x00b0, 0x10, 13, 1), + PIN_FIELD_BASE(182, 182, 9, 0x00b0, 0x10, 14, 1), + PIN_FIELD_BASE(183, 183, 9, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(184, 184, 7, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(185, 185, 7, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(186, 186, 7, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(187, 187, 7, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(188, 188, 7, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(189, 189, 7, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(190, 190, 7, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(191, 191, 7, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(192, 192, 7, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(193, 193, 7, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(194, 194, 7, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(195, 195, 7, 0x0080, 0x10, 9, 1), +}; + +static const struct mtk_pin_field_calc mt6878_pin_r1_range[] = { + PIN_FIELD_BASE(33, 33, 9, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(34, 34, 9, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(35, 35, 9, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(77, 77, 2, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(78, 78, 2, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(79, 79, 2, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(80, 80, 2, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(81, 81, 2, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(82, 82, 2, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(83, 83, 2, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(84, 84, 2, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(85, 85, 2, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(86, 86, 2, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(87, 87, 2, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(88, 88, 2, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(97, 97, 1, 0x00e0, 0x10, 1, 1), + PIN_FIELD_BASE(98, 98, 1, 0x00e0, 0x10, 0, 1), + PIN_FIELD_BASE(117, 117, 1, 0x00e0, 0x10, 2, 1), + PIN_FIELD_BASE(118, 118, 1, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(119, 119, 1, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(120, 120, 1, 0x00e0, 0x10, 5, 1), + PIN_FIELD_BASE(121, 121, 1, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(122, 122, 1, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(123, 123, 1, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(124, 124, 1, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(153, 153, 2, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(154, 154, 2, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(155, 155, 2, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(172, 172, 9, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(173, 173, 9, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(174, 174, 9, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(175, 175, 9, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(176, 176, 9, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(177, 177, 9, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(178, 178, 9, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(179, 179, 9, 0x00c0, 0x10, 11, 1), + PIN_FIELD_BASE(180, 180, 9, 0x00c0, 0x10, 12, 1), + PIN_FIELD_BASE(181, 181, 9, 0x00c0, 0x10, 13, 1), + PIN_FIELD_BASE(182, 182, 9, 0x00c0, 0x10, 14, 1), + PIN_FIELD_BASE(183, 183, 9, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(184, 184, 7, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(185, 185, 7, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(186, 186, 7, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(187, 187, 7, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(188, 188, 7, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(189, 189, 7, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(190, 190, 7, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(191, 191, 7, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(192, 192, 7, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(193, 193, 7, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(194, 194, 7, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(195, 195, 7, 0x0090, 0x10, 9, 1), +}; + +static const struct mtk_pin_field_calc mt6878_pin_drv_range[] = { + PIN_FIELD_BASE(0, 0, 3, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(1, 1, 3, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(2, 2, 3, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(3, 3, 3, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(4, 4, 3, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(5, 5, 3, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(6, 6, 4, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(7, 7, 4, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(8, 8, 4, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(9, 9, 4, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(10, 10, 4, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(11, 11, 4, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(12, 12, 4, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(13, 13, 6, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(14, 14, 6, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(15, 15, 6, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(16, 16, 6, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(17, 17, 6, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(18, 18, 6, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(19, 19, 3, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(20, 20, 3, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(21, 21, 3, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(22, 22, 3, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(23, 23, 3, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(24, 24, 5, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(25, 25, 3, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(26, 26, 3, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(27, 27, 3, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(28, 28, 3, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(29, 29, 6, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(30, 30, 6, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(31, 31, 6, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(32, 32, 6, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(33, 33, 9, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(34, 34, 9, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(35, 35, 9, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(36, 36, 8, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(37, 37, 8, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(38, 38, 8, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(39, 39, 8, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(40, 40, 8, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(41, 41, 4, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(42, 42, 4, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(43, 43, 4, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(44, 44, 4, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(45, 45, 4, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(46, 46, 4, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(47, 47, 4, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(48, 48, 3, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(49, 49, 3, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(50, 50, 3, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(51, 51, 3, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(52, 52, 3, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(53, 53, 3, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(54, 54, 3, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(55, 55, 3, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(56, 56, 5, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(57, 57, 5, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(58, 58, 3, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(59, 59, 3, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(60, 60, 8, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(61, 61, 8, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(62, 62, 8, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(63, 63, 8, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(64, 64, 8, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(65, 65, 8, 0x0020, 0x10, 15, 3), + PIN_FIELD_BASE(66, 66, 8, 0x0020, 0x10, 21, 3), + PIN_FIELD_BASE(67, 67, 8, 0x0020, 0x10, 18, 3), + PIN_FIELD_BASE(68, 68, 5, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(69, 69, 5, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(70, 70, 5, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(71, 71, 5, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(72, 72, 5, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(73, 73, 5, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(74, 74, 5, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(75, 75, 5, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(76, 76, 5, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(77, 77, 2, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(78, 78, 2, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(79, 79, 2, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(80, 80, 2, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(81, 81, 2, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(82, 82, 2, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(83, 83, 2, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(84, 84, 2, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(85, 85, 2, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(86, 86, 2, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(87, 87, 2, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(88, 88, 2, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(89, 89, 4, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(90, 90, 4, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(91, 91, 4, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(92, 92, 8, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(93, 93, 8, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(94, 94, 8, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(95, 95, 8, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(96, 96, 8, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(97, 97, 1, 0x0020, 0x10, 18, 3), + PIN_FIELD_BASE(98, 98, 1, 0x0020, 0x10, 15, 3), + PIN_FIELD_BASE(99, 99, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(100, 100, 1, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(101, 101, 1, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(102, 102, 1, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(103, 103, 1, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(104, 104, 1, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(105, 105, 1, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(106, 106, 1, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(107, 107, 1, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(108, 108, 1, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(109, 109, 1, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(110, 110, 1, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(111, 111, 1, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(112, 112, 1, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(113, 113, 1, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(114, 114, 1, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(115, 115, 1, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(116, 116, 1, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(117, 117, 1, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(118, 118, 1, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(119, 119, 1, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(120, 120, 1, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(121, 121, 1, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(122, 122, 1, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(123, 123, 1, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(124, 124, 1, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(125, 125, 8, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(126, 126, 8, 0x0020, 0x10, 24, 3), + PIN_FIELD_BASE(127, 127, 8, 0x0020, 0x10, 27, 3), + PIN_FIELD_BASE(128, 128, 8, 0x0030, 0x10, 0, 3), + PIN_FIELD_BASE(129, 129, 8, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(130, 130, 8, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(131, 131, 6, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(132, 132, 6, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(133, 133, 8, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(134, 134, 8, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(135, 135, 6, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(136, 136, 6, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(137, 137, 6, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(138, 138, 6, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(139, 139, 6, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(140, 140, 6, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(141, 141, 6, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(142, 142, 6, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(143, 143, 8, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(144, 144, 8, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(145, 145, 5, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(146, 146, 5, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(147, 147, 3, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(148, 148, 3, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(149, 149, 8, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(150, 150, 8, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(151, 151, 8, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(152, 152, 8, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(153, 153, 2, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(154, 154, 2, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(155, 155, 2, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(156, 156, 9, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(157, 157, 9, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(158, 158, 9, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(159, 159, 9, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(160, 160, 4, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(161, 161, 4, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(162, 162, 4, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(163, 163, 4, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(164, 164, 4, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(165, 165, 4, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(166, 166, 4, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(167, 167, 4, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(168, 168, 4, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(169, 169, 4, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(170, 170, 4, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(171, 171, 4, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(172, 172, 9, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(173, 173, 9, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(174, 174, 9, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(175, 175, 9, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(176, 176, 9, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(177, 177, 9, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(178, 178, 9, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(179, 179, 9, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(180, 180, 9, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(181, 181, 9, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(182, 182, 9, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(183, 183, 9, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(184, 184, 7, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(185, 185, 7, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(186, 186, 7, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(187, 187, 7, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(188, 188, 7, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(189, 189, 7, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(190, 190, 7, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(191, 191, 7, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(192, 192, 7, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(193, 193, 7, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(194, 194, 7, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(195, 195, 7, 0x0000, 0x10, 27, 3), +}; + +static const struct mtk_pin_field_calc mt6878_pin_drv_adv_range[] = { + PIN_FIELD_BASE(19, 19, 3, 0x0030, 0x10, 0, 3), + PIN_FIELD_BASE(24, 24, 5, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(25, 25, 3, 0x0030, 0x10, 3, 3), + PIN_FIELD_BASE(26, 26, 3, 0x0030, 0x10, 6, 3), + PIN_FIELD_BASE(52, 52, 3, 0x0030, 0x10, 12, 3), + PIN_FIELD_BASE(53, 53, 3, 0x0030, 0x10, 15, 3), + PIN_FIELD_BASE(55, 55, 3, 0x0030, 0x10, 9, 3), + PIN_FIELD_BASE(60, 60, 8, 0x0050, 0x10, 12, 3), + PIN_FIELD_BASE(61, 61, 8, 0x0050, 0x10, 15, 3), + PIN_FIELD_BASE(62, 62, 8, 0x0050, 0x10, 21, 3), + PIN_FIELD_BASE(63, 63, 8, 0x0050, 0x10, 18, 3), + PIN_FIELD_BASE(64, 64, 8, 0x0050, 0x10, 24, 3), + PIN_FIELD_BASE(65, 65, 8, 0x0050, 0x10, 27, 3), + PIN_FIELD_BASE(66, 66, 8, 0x0060, 0x10, 3, 3), + PIN_FIELD_BASE(67, 67, 8, 0x0060, 0x10, 0, 3), + PIN_FIELD_BASE(92, 92, 8, 0x0040, 0x10, 0, 3), + PIN_FIELD_BASE(93, 93, 8, 0x0040, 0x10, 3, 3), + PIN_FIELD_BASE(94, 94, 8, 0x0040, 0x10, 6, 3), + PIN_FIELD_BASE(95, 95, 8, 0x0040, 0x10, 9, 3), + PIN_FIELD_BASE(96, 96, 8, 0x0040, 0x10, 12, 3), + PIN_FIELD_BASE(125, 125, 8, 0x0050, 0x10, 9, 3), + PIN_FIELD_BASE(126, 126, 8, 0x0060, 0x10, 6, 3), + PIN_FIELD_BASE(127, 127, 8, 0x0060, 0x10, 9, 3), + PIN_FIELD_BASE(128, 128, 8, 0x0060, 0x10, 12, 3), + PIN_FIELD_BASE(129, 129, 8, 0x0040, 0x10, 15, 3), + PIN_FIELD_BASE(130, 130, 8, 0x0040, 0x10, 24, 3), + PIN_FIELD_BASE(131, 131, 6, 0x0030, 0x10, 12, 3), + PIN_FIELD_BASE(132, 132, 6, 0x0030, 0x10, 21, 3), + PIN_FIELD_BASE(133, 133, 8, 0x0040, 0x10, 18, 3), + PIN_FIELD_BASE(134, 134, 8, 0x0040, 0x10, 27, 3), + PIN_FIELD_BASE(135, 135, 6, 0x0030, 0x10, 15, 3), + PIN_FIELD_BASE(136, 136, 6, 0x0030, 0x10, 24, 3), + PIN_FIELD_BASE(137, 137, 6, 0x0030, 0x10, 18, 3), + PIN_FIELD_BASE(138, 138, 6, 0x0030, 0x10, 27, 3), + PIN_FIELD_BASE(139, 139, 6, 0x0030, 0x10, 0, 3), + PIN_FIELD_BASE(140, 140, 6, 0x0030, 0x10, 6, 3), + PIN_FIELD_BASE(141, 141, 6, 0x0030, 0x10, 3, 3), + PIN_FIELD_BASE(142, 142, 6, 0x0030, 0x10, 9, 3), + PIN_FIELD_BASE(143, 143, 8, 0x0040, 0x10, 21, 3), + PIN_FIELD_BASE(144, 144, 8, 0x0050, 0x10, 0, 3), + PIN_FIELD_BASE(145, 145, 5, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(146, 146, 5, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(147, 147, 3, 0x0030, 0x10, 18, 3), + PIN_FIELD_BASE(148, 148, 3, 0x0030, 0x10, 21, 3), + PIN_FIELD_BASE(149, 149, 8, 0x0050, 0x10, 3, 3), + PIN_FIELD_BASE(150, 150, 8, 0x0050, 0x10, 6, 3), + PIN_FIELD_BASE(156, 156, 9, 0x0020, 0x10, 0, 5), + PIN_FIELD_BASE(157, 157, 9, 0x0020, 0x10, 5, 5), + PIN_FIELD_BASE(158, 158, 9, 0x0020, 0x10, 10, 5), + PIN_FIELD_BASE(159, 159, 9, 0x0020, 0x10, 15, 5), +}; + +static const struct mtk_pin_field_calc mt6878_pin_rsel_range[] = { + PIN_FIELD_BASE(19, 19, 3, 0x00d0, 0x10, 0, 3), + PIN_FIELD_BASE(24, 24, 5, 0x00a0, 0x10, 0, 3), + PIN_FIELD_BASE(25, 25, 3, 0x00d0, 0x10, 3, 3), + PIN_FIELD_BASE(26, 26, 3, 0x00d0, 0x10, 6, 3), + PIN_FIELD_BASE(52, 52, 3, 0x00d0, 0x10, 12, 3), + PIN_FIELD_BASE(53, 53, 3, 0x00d0, 0x10, 15, 3), + PIN_FIELD_BASE(55, 55, 3, 0x00d0, 0x10, 9, 3), + PIN_FIELD_BASE(60, 60, 8, 0x0110, 0x10, 12, 3), + PIN_FIELD_BASE(61, 61, 8, 0x0110, 0x10, 15, 3), + PIN_FIELD_BASE(62, 62, 8, 0x0110, 0x10, 21, 3), + PIN_FIELD_BASE(63, 63, 8, 0x0110, 0x10, 18, 3), + PIN_FIELD_BASE(64, 64, 8, 0x0110, 0x10, 24, 3), + PIN_FIELD_BASE(65, 65, 8, 0x0110, 0x10, 27, 3), + PIN_FIELD_BASE(66, 66, 8, 0x0120, 0x10, 3, 3), + PIN_FIELD_BASE(67, 67, 8, 0x0120, 0x10, 0, 3), + PIN_FIELD_BASE(92, 92, 8, 0x0100, 0x10, 0, 3), + PIN_FIELD_BASE(93, 93, 8, 0x0100, 0x10, 3, 3), + PIN_FIELD_BASE(94, 94, 8, 0x0100, 0x10, 6, 3), + PIN_FIELD_BASE(95, 95, 8, 0x0100, 0x10, 9, 3), + PIN_FIELD_BASE(96, 96, 8, 0x0100, 0x10, 12, 3), + PIN_FIELD_BASE(125, 125, 8, 0x0110, 0x10, 9, 3), + PIN_FIELD_BASE(126, 126, 8, 0x0120, 0x10, 6, 3), + PIN_FIELD_BASE(127, 127, 8, 0x0120, 0x10, 9, 3), + PIN_FIELD_BASE(128, 128, 8, 0x0120, 0x10, 12, 3), + PIN_FIELD_BASE(129, 129, 8, 0x0100, 0x10, 15, 3), + PIN_FIELD_BASE(130, 130, 8, 0x0100, 0x10, 24, 3), + PIN_FIELD_BASE(131, 131, 6, 0x00d0, 0x10, 12, 3), + PIN_FIELD_BASE(132, 132, 6, 0x00d0, 0x10, 21, 3), + PIN_FIELD_BASE(133, 133, 8, 0x0100, 0x10, 18, 3), + PIN_FIELD_BASE(134, 134, 8, 0x0100, 0x10, 27, 3), + PIN_FIELD_BASE(135, 135, 6, 0x00d0, 0x10, 15, 3), + PIN_FIELD_BASE(136, 136, 6, 0x00d0, 0x10, 24, 3), + PIN_FIELD_BASE(137, 137, 6, 0x00d0, 0x10, 18, 3), + PIN_FIELD_BASE(138, 138, 6, 0x00d0, 0x10, 27, 3), + PIN_FIELD_BASE(139, 139, 6, 0x00d0, 0x10, 0, 3), + PIN_FIELD_BASE(140, 140, 6, 0x00d0, 0x10, 6, 3), + PIN_FIELD_BASE(141, 141, 6, 0x00d0, 0x10, 3, 3), + PIN_FIELD_BASE(142, 142, 6, 0x00d0, 0x10, 9, 3), + PIN_FIELD_BASE(143, 143, 8, 0x0100, 0x10, 21, 3), + PIN_FIELD_BASE(144, 144, 8, 0x0110, 0x10, 0, 3), + PIN_FIELD_BASE(145, 145, 5, 0x00a0, 0x10, 3, 3), + PIN_FIELD_BASE(146, 146, 5, 0x00a0, 0x10, 6, 3), + PIN_FIELD_BASE(147, 147, 3, 0x00d0, 0x10, 18, 3), + PIN_FIELD_BASE(148, 148, 3, 0x00d0, 0x10, 21, 3), + PIN_FIELD_BASE(149, 149, 8, 0x0110, 0x10, 3, 3), + PIN_FIELD_BASE(150, 150, 8, 0x0110, 0x10, 6, 3), +}; + +static const unsigned int mt6878_pull_type[] = { + MTK_PULL_PU_PD_TYPE /* 0 */, + MTK_PULL_PU_PD_TYPE /* 1 */, + MTK_PULL_PU_PD_TYPE /* 2 */, + MTK_PULL_PU_PD_TYPE /* 3 */, + MTK_PULL_PU_PD_TYPE /* 4 */, + MTK_PULL_PU_PD_TYPE /* 5 */, + MTK_PULL_PU_PD_TYPE /* 6 */, + MTK_PULL_PU_PD_TYPE /* 7 */, + MTK_PULL_PU_PD_TYPE /* 8 */, + MTK_PULL_PU_PD_TYPE /* 9 */, + MTK_PULL_PU_PD_TYPE /* 10 */, + MTK_PULL_PU_PD_TYPE /* 11 */, + MTK_PULL_PU_PD_TYPE /* 12 */, + MTK_PULL_PU_PD_TYPE /* 13 */, + MTK_PULL_PU_PD_TYPE /* 14 */, + MTK_PULL_PU_PD_TYPE /* 15 */, + MTK_PULL_PU_PD_TYPE /* 16 */, + MTK_PULL_PU_PD_TYPE /* 17 */, + MTK_PULL_PU_PD_TYPE /* 18 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 19 */, + MTK_PULL_PU_PD_TYPE /* 20 */, + MTK_PULL_PU_PD_TYPE /* 21 */, + MTK_PULL_PU_PD_TYPE /* 22 */, + MTK_PULL_PU_PD_TYPE /* 23 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 24 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 25 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 26 */, + MTK_PULL_PU_PD_TYPE /* 27 */, + MTK_PULL_PU_PD_TYPE /* 28 */, + MTK_PULL_PU_PD_TYPE /* 29 */, + MTK_PULL_PU_PD_TYPE /* 30 */, + MTK_PULL_PU_PD_TYPE /* 31 */, + MTK_PULL_PU_PD_TYPE /* 32 */, + MTK_PULL_PUPD_R1R0_TYPE /* 33 */, + MTK_PULL_PUPD_R1R0_TYPE /* 34 */, + MTK_PULL_PUPD_R1R0_TYPE /* 35 */, + MTK_PULL_PU_PD_TYPE /* 36 */, + MTK_PULL_PU_PD_TYPE /* 37 */, + MTK_PULL_PU_PD_TYPE /* 38 */, + MTK_PULL_PU_PD_TYPE /* 39 */, + MTK_PULL_PU_PD_TYPE /* 40 */, + MTK_PULL_PU_PD_TYPE /* 41 */, + MTK_PULL_PU_PD_TYPE /* 42 */, + MTK_PULL_PU_PD_TYPE /* 43 */, + MTK_PULL_PU_PD_TYPE /* 44 */, + MTK_PULL_PU_PD_TYPE /* 45 */, + MTK_PULL_PU_PD_TYPE /* 46 */, + MTK_PULL_PU_PD_TYPE /* 47 */, + MTK_PULL_PU_PD_TYPE /* 48 */, + MTK_PULL_PU_PD_TYPE /* 49 */, + MTK_PULL_PU_PD_TYPE /* 50 */, + MTK_PULL_PU_PD_TYPE /* 51 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 52 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 53 */, + MTK_PULL_PU_PD_TYPE /* 54 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 55 */, + MTK_PULL_PU_PD_TYPE /* 56 */, + MTK_PULL_PU_PD_TYPE /* 57 */, + MTK_PULL_PU_PD_TYPE /* 58 */, + MTK_PULL_PU_PD_TYPE /* 59 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 60 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 61 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 62 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 63 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 64 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 65 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 66 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 67 */, + MTK_PULL_PU_PD_TYPE /* 68 */, + MTK_PULL_PU_PD_TYPE /* 69 */, + MTK_PULL_PU_PD_TYPE /* 70 */, + MTK_PULL_PU_PD_TYPE /* 71 */, + MTK_PULL_PU_PD_TYPE /* 72 */, + MTK_PULL_PU_PD_TYPE /* 73 */, + MTK_PULL_PU_PD_TYPE /* 74 */, + MTK_PULL_PU_PD_TYPE /* 75 */, + MTK_PULL_PU_PD_TYPE /* 76 */, + MTK_PULL_PUPD_R1R0_TYPE /* 77 */, + MTK_PULL_PUPD_R1R0_TYPE /* 78 */, + MTK_PULL_PUPD_R1R0_TYPE /* 79 */, + MTK_PULL_PUPD_R1R0_TYPE /* 80 */, + MTK_PULL_PUPD_R1R0_TYPE /* 81 */, + MTK_PULL_PUPD_R1R0_TYPE /* 82 */, + MTK_PULL_PUPD_R1R0_TYPE /* 83 */, + MTK_PULL_PUPD_R1R0_TYPE /* 84 */, + MTK_PULL_PUPD_R1R0_TYPE /* 85 */, + MTK_PULL_PUPD_R1R0_TYPE /* 86 */, + MTK_PULL_PUPD_R1R0_TYPE /* 87 */, + MTK_PULL_PUPD_R1R0_TYPE /* 88 */, + MTK_PULL_PU_PD_TYPE /* 89 */, + MTK_PULL_PU_PD_TYPE /* 90 */, + MTK_PULL_PU_PD_TYPE /* 91 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 92 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 93 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 94 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 95 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 96 */, + MTK_PULL_PUPD_R1R0_TYPE /* 97 */, + MTK_PULL_PUPD_R1R0_TYPE /* 98 */, + MTK_PULL_PU_PD_TYPE /* 99 */, + MTK_PULL_PU_PD_TYPE /* 100 */, + MTK_PULL_PU_PD_TYPE /* 101 */, + MTK_PULL_PU_PD_TYPE /* 102 */, + MTK_PULL_PU_PD_TYPE /* 103 */, + MTK_PULL_PU_PD_TYPE /* 104 */, + MTK_PULL_PU_PD_TYPE /* 105 */, + MTK_PULL_PU_PD_TYPE /* 106 */, + MTK_PULL_PU_PD_TYPE /* 107 */, + MTK_PULL_PU_PD_TYPE /* 108 */, + MTK_PULL_PU_PD_TYPE /* 109 */, + MTK_PULL_PU_PD_TYPE /* 110 */, + MTK_PULL_PU_PD_TYPE /* 111 */, + MTK_PULL_PU_PD_TYPE /* 112 */, + MTK_PULL_PU_PD_TYPE /* 113 */, + MTK_PULL_PU_PD_TYPE /* 114 */, + MTK_PULL_PU_PD_TYPE /* 115 */, + MTK_PULL_PU_PD_TYPE /* 116 */, + MTK_PULL_PUPD_R1R0_TYPE /* 117 */, + MTK_PULL_PUPD_R1R0_TYPE /* 118 */, + MTK_PULL_PUPD_R1R0_TYPE /* 119 */, + MTK_PULL_PUPD_R1R0_TYPE /* 120 */, + MTK_PULL_PUPD_R1R0_TYPE /* 121 */, + MTK_PULL_PUPD_R1R0_TYPE /* 122 */, + MTK_PULL_PUPD_R1R0_TYPE /* 123 */, + MTK_PULL_PUPD_R1R0_TYPE /* 124 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 125 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 126 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 127 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 128 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 129 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 130 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 131 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 132 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 133 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 134 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 135 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 136 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 137 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 138 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 139 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 140 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 141 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 142 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 143 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 144 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 145 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 146 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 147 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 148 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 149 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 150 */, + MTK_PULL_PU_PD_TYPE /* 151 */, + MTK_PULL_PU_PD_TYPE /* 152 */, + MTK_PULL_PUPD_R1R0_TYPE /* 153 */, + MTK_PULL_PUPD_R1R0_TYPE /* 154 */, + MTK_PULL_PUPD_R1R0_TYPE /* 155 */, + MTK_PULL_PU_PD_TYPE /* 156 */, + MTK_PULL_PU_PD_TYPE /* 157 */, + MTK_PULL_PU_PD_TYPE /* 158 */, + MTK_PULL_PU_PD_TYPE /* 159 */, + MTK_PULL_PU_PD_TYPE /* 160 */, + MTK_PULL_PU_PD_TYPE /* 161 */, + MTK_PULL_PU_PD_TYPE /* 162 */, + MTK_PULL_PU_PD_TYPE /* 163 */, + MTK_PULL_PU_PD_TYPE /* 164 */, + MTK_PULL_PU_PD_TYPE /* 165 */, + MTK_PULL_PU_PD_TYPE /* 166 */, + MTK_PULL_PU_PD_TYPE /* 167 */, + MTK_PULL_PU_PD_TYPE /* 168 */, + MTK_PULL_PU_PD_TYPE /* 169 */, + MTK_PULL_PU_PD_TYPE /* 170 */, + MTK_PULL_PU_PD_TYPE /* 171 */, + MTK_PULL_PUPD_R1R0_TYPE /* 172 */, + MTK_PULL_PUPD_R1R0_TYPE /* 173 */, + MTK_PULL_PUPD_R1R0_TYPE /* 174 */, + MTK_PULL_PUPD_R1R0_TYPE /* 175 */, + MTK_PULL_PUPD_R1R0_TYPE /* 176 */, + MTK_PULL_PUPD_R1R0_TYPE /* 177 */, + MTK_PULL_PUPD_R1R0_TYPE /* 178 */, + MTK_PULL_PUPD_R1R0_TYPE /* 179 */, + MTK_PULL_PUPD_R1R0_TYPE /* 180 */, + MTK_PULL_PUPD_R1R0_TYPE /* 181 */, + MTK_PULL_PUPD_R1R0_TYPE /* 182 */, + MTK_PULL_PUPD_R1R0_TYPE /* 183 */, + MTK_PULL_PUPD_R1R0_TYPE /* 184 */, + MTK_PULL_PUPD_R1R0_TYPE /* 185 */, + MTK_PULL_PUPD_R1R0_TYPE /* 186 */, + MTK_PULL_PUPD_R1R0_TYPE /* 187 */, + MTK_PULL_PUPD_R1R0_TYPE /* 188 */, + MTK_PULL_PUPD_R1R0_TYPE /* 189 */, + MTK_PULL_PUPD_R1R0_TYPE /* 190 */, + MTK_PULL_PUPD_R1R0_TYPE /* 191 */, + MTK_PULL_PUPD_R1R0_TYPE /* 192 */, + MTK_PULL_PUPD_R1R0_TYPE /* 193 */, + MTK_PULL_PUPD_R1R0_TYPE /* 194 */, + MTK_PULL_PUPD_R1R0_TYPE /* 195 */, +}; + +static const char * const mt6878_pinctrl_register_base_names[] = { + "gpio", "iocfg_bl", "iocfg_bm", "iocfg_br", + "iocfg_bl1", "iocfg_br1", "iocfg_lm", "iocfg_lt", + "iocfg_rm", "iocfg_rt", +}; + +static const struct mtk_eint_hw mt6878_eint_hw = { + .port_mask = 31, + .ports = 1, + .ap_num = 216, + .db_cnt = 36, + .db_time = debounce_time_mt6878, +}; + +static const struct mtk_pin_reg_calc mt6878_reg_cals[PINCTRL_PIN_REG_MAX] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6878_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6878_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6878_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6878_pin_do_range), + [PINCTRL_PIN_REG_SR] = MTK_RANGE(mt6878_pin_dir_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt6878_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt6878_pin_ies_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt6878_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt6878_pin_pd_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt6878_pin_drv_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt6878_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt6878_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt6878_pin_r1_range), + [PINCTRL_PIN_REG_DRV_ADV] = MTK_RANGE(mt6878_pin_drv_adv_range), + [PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt6878_pin_rsel_range), +}; + +static const struct mtk_pin_soc mt6878_data = { + .reg_cal = mt6878_reg_cals, + .pins = mtk_pins_mt6878, + .npins = ARRAY_SIZE(mtk_pins_mt6878), + .ngrps = ARRAY_SIZE(mtk_pins_mt6878), + .eint_pin = eint_pins_mt6878, + .eint_hw = &mt6878_eint_hw, + .nfuncs = 8, + .gpio_m = 0, + .base_names = mt6878_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt6878_pinctrl_register_base_names), + .bias_set_combo = mtk_pinconf_bias_set_combo, + .bias_get_combo = mtk_pinconf_bias_get_combo, + .pull_type = mt6878_pull_type, + .adv_drive_get = mtk_pinconf_adv_drive_get, + .adv_drive_set = mtk_pinconf_adv_drive_set, +}; + +static const struct of_device_id mt6878_pinctrl_of_match[] = { + { .compatible = "mediatek,mt6878-pinctrl", .data = &mt6878_data }, + { } +}; + +static struct platform_driver mt6878_pinctrl_driver = { + .driver = { + .name = "mt6878-pinctrl", + .of_match_table = mt6878_pinctrl_of_match, + .pm = pm_sleep_ptr(&mtk_paris_pinctrl_pm_ops), + }, + .probe = mtk_paris_pinctrl_probe, +}; + +static int __init mt6878_pinctrl_init(void) +{ + return platform_driver_register(&mt6878_pinctrl_driver); +} +arch_initcall(mt6878_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT6878 Pinctrl Driver"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6878.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6878.h new file mode 100644 index 000000000000..a251af00eff1 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6878.h @@ -0,0 +1,2248 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 MediaTek Inc. + * Author: Light Hsieh + * + * Copyright (C) 2025 Igor Belwon + */ + +#ifndef __PINCTRL_MTK_MT6878_H +#define __PINCTRL_MTK_MT6878_H + +#include "pinctrl-paris.h" + +static const struct mtk_pin_desc mtk_pins_mt6878[] = { + MTK_PIN( + 0, "GPIO0", + MTK_EINT_FUNCTION(0, 0), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO0"), + MTK_FUNCTION(1, "TP_GPIO0_AO"), + MTK_FUNCTION(2, "SRCLKENA1"), + MTK_FUNCTION(7, "DBG_MON_A3") + ), + MTK_PIN( + 1, "GPIO1", + MTK_EINT_FUNCTION(0, 1), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO1"), + MTK_FUNCTION(1, "TP_GPIO1_AO"), + MTK_FUNCTION(2, "SRCLKENA1"), + MTK_FUNCTION(3, "SRCLKENA2"), + MTK_FUNCTION(5, "IDDIG"), + MTK_FUNCTION(7, "DBG_MON_A4") + ), + MTK_PIN( + 2, "GPIO2", + MTK_EINT_FUNCTION(0, 2), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO2"), + MTK_FUNCTION(1, "TP_GPIO2_AO"), + MTK_FUNCTION(2, "SRCLKENAI0"), + MTK_FUNCTION(4, "SCP_DMIC_CLK"), + MTK_FUNCTION(5, "DMIC_CLK"), + MTK_FUNCTION(7, "DBG_MON_A5") + ), + MTK_PIN( + 3, "GPIO3", + MTK_EINT_FUNCTION(0, 3), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO3"), + MTK_FUNCTION(1, "TP_GPIO3_AO"), + MTK_FUNCTION(2, "SRCLKENAI1"), + MTK_FUNCTION(4, "SCP_DMIC_DAT"), + MTK_FUNCTION(5, "DMIC_DAT"), + MTK_FUNCTION(7, "DBG_MON_A6") + ), + MTK_PIN( + 4, "GPIO4", + MTK_EINT_FUNCTION(0, 4), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO4"), + MTK_FUNCTION(1, "SPI7_CLK"), + MTK_FUNCTION(2, "TP_GPIO4_AO"), + MTK_FUNCTION(3, "ANT_SEL0"), + MTK_FUNCTION(5, "DMIC1_CLK"), + MTK_FUNCTION(6, "MD_INT4"), + MTK_FUNCTION(7, "DBG_MON_A7") + ), + MTK_PIN( + 5, "GPIO5", + MTK_EINT_FUNCTION(0, 5), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO5"), + MTK_FUNCTION(1, "SPI7_CSB"), + MTK_FUNCTION(2, "TP_GPIO5_AO"), + MTK_FUNCTION(3, "ANT_SEL1"), + MTK_FUNCTION(5, "DMIC1_DAT"), + MTK_FUNCTION(6, "MD_INT0"), + MTK_FUNCTION(7, "DBG_MON_A8") + ), + MTK_PIN( + 6, "GPIO6", + MTK_EINT_FUNCTION(0, 6), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO6"), + MTK_FUNCTION(1, "SPI7_MO"), + MTK_FUNCTION(2, "TP_GPIO6_AO"), + MTK_FUNCTION(3, "ANT_SEL2"), + MTK_FUNCTION(4, "MD32_0_GPIO0"), + MTK_FUNCTION(6, "MD_INT3"), + MTK_FUNCTION(7, "DBG_MON_B0") + ), + MTK_PIN( + 7, "GPIO7", + MTK_EINT_FUNCTION(0, 7), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO7"), + MTK_FUNCTION(1, "SPI7_MI"), + MTK_FUNCTION(2, "TP_GPIO7_AO"), + MTK_FUNCTION(3, "ANT_SEL3"), + MTK_FUNCTION(4, "MD32_1_GPIO0") + ), + MTK_PIN( + 8, "GPIO8", + MTK_EINT_FUNCTION(0, 8), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO8"), + MTK_FUNCTION(2, "SCP_JTAG0_TRSTN_VLP"), + MTK_FUNCTION(3, "SPM_JTAG_TRSTN_VLP"), + MTK_FUNCTION(4, "SSPM_JTAG_TRSTN_VLP"), + MTK_FUNCTION(5, "HFRP_JTAG0_TRSTN"), + MTK_FUNCTION(6, "IO_JTAG_TRSTN"), + MTK_FUNCTION(7, "CONN_BGF_MCU_TDI") + ), + MTK_PIN( + 9, "GPIO9", + MTK_EINT_FUNCTION(0, 9), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO9"), + MTK_FUNCTION(2, "SCP_JTAG0_TCK_VLP"), + MTK_FUNCTION(3, "SPM_JTAG_TCK_VLP"), + MTK_FUNCTION(4, "SSPM_JTAG_TCK_VLP"), + MTK_FUNCTION(5, "HFRP_JTAG0_TCK"), + MTK_FUNCTION(6, "IO_JTAG_TCK"), + MTK_FUNCTION(7, "CONN_BGF_MCU_TRST_B") + ), + MTK_PIN( + 10, "GPIO10", + MTK_EINT_FUNCTION(0, 10), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO10"), + MTK_FUNCTION(2, "SCP_JTAG0_TMS_VLP"), + MTK_FUNCTION(3, "SPM_JTAG_TMS_VLP"), + MTK_FUNCTION(4, "SSPM_JTAG_TMS_VLP"), + MTK_FUNCTION(5, "HFRP_JTAG0_TMS"), + MTK_FUNCTION(6, "IO_JTAG_TMS"), + MTK_FUNCTION(7, "CONN_BGF_MCU_TCK") + ), + MTK_PIN( + 11, "GPIO11", + MTK_EINT_FUNCTION(0, 11), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO11"), + MTK_FUNCTION(2, "SCP_JTAG0_TDI_VLP"), + MTK_FUNCTION(3, "SPM_JTAG_TDI_VLP"), + MTK_FUNCTION(4, "SSPM_JTAG_TDI_VLP"), + MTK_FUNCTION(5, "HFRP_JTAG0_TDI"), + MTK_FUNCTION(6, "IO_JTAG_TDI"), + MTK_FUNCTION(7, "CONN_BGF_MCU_TDO") + ), + MTK_PIN( + 12, "GPIO12", + MTK_EINT_FUNCTION(0, 12), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO12"), + MTK_FUNCTION(2, "SCP_JTAG0_TDO_VLP"), + MTK_FUNCTION(3, "SPM_JTAG_TDO_VLP"), + MTK_FUNCTION(4, "SSPM_JTAG_TDO_VLP"), + MTK_FUNCTION(5, "HFRP_JTAG0_TDO"), + MTK_FUNCTION(6, "IO_JTAG_TDO"), + MTK_FUNCTION(7, "CONN_BGF_MCU_TMS") + ), + MTK_PIN( + 13, "GPIO13", + MTK_EINT_FUNCTION(0, 13), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO13"), + MTK_FUNCTION(1, "MFG_EB_JTAG_TDI"), + MTK_FUNCTION(2, "CONN_WF_MCU_TDI"), + MTK_FUNCTION(3, "SCP_JTAG0_TDI_VCORE"), + MTK_FUNCTION(5, "SPM_JTAG_TDI_VCORE"), + MTK_FUNCTION(6, "MCUPM_JTAG_TDI") + ), + MTK_PIN( + 14, "GPIO14", + MTK_EINT_FUNCTION(0, 14), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO14"), + MTK_FUNCTION(1, "MFG_EB_JTAG_TRSTN"), + MTK_FUNCTION(2, "CONN_WF_MCU_TRST_B"), + MTK_FUNCTION(3, "SCP_JTAG0_TRSTN_VCORE"), + MTK_FUNCTION(5, "SPM_JTAG_TRSTN_VCORE"), + MTK_FUNCTION(6, "MCUPM_JTAG_TRSTN") + ), + MTK_PIN( + 15, "GPIO15", + MTK_EINT_FUNCTION(0, 15), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO15"), + MTK_FUNCTION(1, "MFG_EB_JTAG_TCK"), + MTK_FUNCTION(2, "CONN_WF_MCU_TCK"), + MTK_FUNCTION(3, "SCP_JTAG0_TCK_VCORE"), + MTK_FUNCTION(5, "SPM_JTAG_TCK_VCORE"), + MTK_FUNCTION(6, "MCUPM_JTAG_TCK") + ), + MTK_PIN( + 16, "GPIO16", + MTK_EINT_FUNCTION(0, 16), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO16"), + MTK_FUNCTION(1, "MFG_EB_JTAG_TDO"), + MTK_FUNCTION(2, "CONN_WF_MCU_TDO"), + MTK_FUNCTION(3, "SCP_JTAG0_TDO_VCORE"), + MTK_FUNCTION(5, "SPM_JTAG_TDO_VCORE"), + MTK_FUNCTION(6, "MCUPM_JTAG_TDO") + ), + MTK_PIN( + 17, "GPIO17", + MTK_EINT_FUNCTION(0, 17), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO17"), + MTK_FUNCTION(1, "MFG_EB_JTAG_TMS"), + MTK_FUNCTION(2, "CONN_WF_MCU_TMS"), + MTK_FUNCTION(3, "SCP_JTAG0_TMS_VCORE"), + MTK_FUNCTION(5, "SPM_JTAG_TMS_VCORE"), + MTK_FUNCTION(6, "MCUPM_JTAG_TMS") + ), + MTK_PIN( + 18, "GPIO18", + MTK_EINT_FUNCTION(0, 18), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO18"), + MTK_FUNCTION(2, "CONN_BT_TXD"), + MTK_FUNCTION(3, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(6, "GPS_L1_ELNA_EN") + ), + MTK_PIN( + 19, "GPIO19", + MTK_EINT_FUNCTION(0, 19), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO19"), + MTK_FUNCTION(1, "PWM_0"), + MTK_FUNCTION(3, "SDA10"), + MTK_FUNCTION(4, "MD32_0_GPIO0"), + MTK_FUNCTION(5, "EXT_FRAME_SYNC"), + MTK_FUNCTION(7, "DBG_MON_A9") + ), + MTK_PIN( + 20, "GPIO20", + MTK_EINT_FUNCTION(0, 20), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO20"), + MTK_FUNCTION(1, "PWM_1"), + MTK_FUNCTION(2, "SPI4_CLK"), + MTK_FUNCTION(4, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(6, "DAP_SONIC_SWCK"), + MTK_FUNCTION(7, "DBG_MON_A10") + ), + MTK_PIN( + 21, "GPIO21", + MTK_EINT_FUNCTION(0, 21), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO21"), + MTK_FUNCTION(1, "PWM_2"), + MTK_FUNCTION(2, "SPI4_CSB"), + MTK_FUNCTION(4, "GPS_L5_ELNA_EN"), + MTK_FUNCTION(5, "IDDIG"), + MTK_FUNCTION(6, "DAP_SONIC_SWD"), + MTK_FUNCTION(7, "DBG_MON_A11") + ), + MTK_PIN( + 22, "GPIO22", + MTK_EINT_FUNCTION(0, 22), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO22"), + MTK_FUNCTION(1, "PWM_3"), + MTK_FUNCTION(2, "SPI4_MO"), + MTK_FUNCTION(4, "EXT_FRAME_SYNC"), + MTK_FUNCTION(5, "VBUSVALID"), + MTK_FUNCTION(6, "DAP_MD32_SWCK"), + MTK_FUNCTION(7, "DBG_MON_A12") + ), + MTK_PIN( + 23, "GPIO23", + MTK_EINT_FUNCTION(0, 23), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO23"), + MTK_FUNCTION(2, "SPI4_MI"), + MTK_FUNCTION(4, "MD32_1_GPIO0"), + MTK_FUNCTION(5, "USB_DRVVBUS"), + MTK_FUNCTION(6, "DAP_MD32_SWD"), + MTK_FUNCTION(7, "DBG_MON_A13") + ), + MTK_PIN( + 24, "GPIO24", + MTK_EINT_FUNCTION(0, 24), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO24"), + MTK_FUNCTION(1, "GPS_L5_ELNA_EN"), + MTK_FUNCTION(2, "SCL12"), + MTK_FUNCTION(3, "SCL10"), + MTK_FUNCTION(4, "CMVREF0"), + MTK_FUNCTION(5, "CONN_WIFI_TXD"), + MTK_FUNCTION(6, "CMFLASH0"), + MTK_FUNCTION(7, "DBG_MON_A14") + ), + MTK_PIN( + 25, "GPIO25", + MTK_EINT_FUNCTION(0, 25), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO25"), + MTK_FUNCTION(1, "SPI6_CLK"), + MTK_FUNCTION(2, "SCL11"), + MTK_FUNCTION(4, "CMVREF1"), + MTK_FUNCTION(6, "CMFLASH1"), + MTK_FUNCTION(7, "DBG_MON_A15") + ), + MTK_PIN( + 26, "GPIO26", + MTK_EINT_FUNCTION(0, 26), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO26"), + MTK_FUNCTION(1, "SPI6_CSB"), + MTK_FUNCTION(2, "SDA11"), + MTK_FUNCTION(3, "USB_DRVVBUS"), + MTK_FUNCTION(4, "CMVREF2"), + MTK_FUNCTION(6, "CMFLASH2"), + MTK_FUNCTION(7, "DBG_MON_A16") + ), + MTK_PIN( + 27, "GPIO27", + MTK_EINT_FUNCTION(0, 27), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO27"), + MTK_FUNCTION(1, "SPI6_MO"), + MTK_FUNCTION(3, "VBUSVALID"), + MTK_FUNCTION(4, "CMVREF3"), + MTK_FUNCTION(5, "DMIC1_CLK"), + MTK_FUNCTION(6, "CMFLASH3"), + MTK_FUNCTION(7, "DBG_MON_A17") + ), + MTK_PIN( + 28, "GPIO28", + MTK_EINT_FUNCTION(0, 28), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO28"), + MTK_FUNCTION(1, "SPI6_MI"), + MTK_FUNCTION(3, "IDDIG"), + MTK_FUNCTION(5, "DMIC1_DAT"), + MTK_FUNCTION(6, "CMFLASH0"), + MTK_FUNCTION(7, "DBG_MON_A18") + ), + MTK_PIN( + 29, "GPIO29", + MTK_EINT_FUNCTION(0, 29), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO29"), + MTK_FUNCTION(1, "I2SIN2_BCK"), + MTK_FUNCTION(2, "TP_UTXD1_VCORE"), + MTK_FUNCTION(3, "MD_UTXD0"), + MTK_FUNCTION(4, "SSPM_UTXD_AO_VCORE"), + MTK_FUNCTION(5, "MD32_1_TXD"), + MTK_FUNCTION(6, "CONN_BT_TXD"), + MTK_FUNCTION(7, "PTA_TXD") + ), + MTK_PIN( + 30, "GPIO30", + MTK_EINT_FUNCTION(0, 30), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO30"), + MTK_FUNCTION(1, "I2SIN2_LRCK"), + MTK_FUNCTION(2, "TP_URXD1_VCORE"), + MTK_FUNCTION(3, "MD_URXD0"), + MTK_FUNCTION(4, "SSPM_URXD_AO_VCORE"), + MTK_FUNCTION(5, "MD32_1_RXD"), + MTK_FUNCTION(7, "PTA_RXD") + ), + MTK_PIN( + 31, "GPIO31", + MTK_EINT_FUNCTION(0, 31), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO31"), + MTK_FUNCTION(1, "I2SOUT2_DO"), + MTK_FUNCTION(2, "TP_UTXD2_VCORE"), + MTK_FUNCTION(3, "MD_UTXD1"), + MTK_FUNCTION(4, "HFRP_UTXD1"), + MTK_FUNCTION(5, "MD32_0_TXD"), + MTK_FUNCTION(6, "CONN_WIFI_TXD"), + MTK_FUNCTION(7, "CONN_BGF_UART0_TXD") + ), + MTK_PIN( + 32, "GPIO32", + MTK_EINT_FUNCTION(0, 32), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO32"), + MTK_FUNCTION(1, "I2SIN2_DI"), + MTK_FUNCTION(2, "TP_URXD2_VCORE"), + MTK_FUNCTION(3, "MD_URXD1"), + MTK_FUNCTION(4, "HFRP_URXD1"), + MTK_FUNCTION(5, "MD32_0_RXD"), + MTK_FUNCTION(7, "CONN_BGF_UART0_RXD") + ), + MTK_PIN( + 33, "GPIO33", + MTK_EINT_FUNCTION(0, 33), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO33"), + MTK_FUNCTION(1, "ANT_SEL0"), + MTK_FUNCTION(3, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(4, "SCL1"), + MTK_FUNCTION(5, "CONN_BPI_BUS18_ANT1"), + MTK_FUNCTION(6, "MD_UCTS0") + ), + MTK_PIN( + 34, "GPIO34", + MTK_EINT_FUNCTION(0, 34), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO34"), + MTK_FUNCTION(1, "ANT_SEL1"), + MTK_FUNCTION(3, "GPS_L5_ELNA_EN"), + MTK_FUNCTION(4, "SDA1"), + MTK_FUNCTION(5, "CONN_BPI_BUS19_ANT2"), + MTK_FUNCTION(6, "MD_URTS0") + ), + MTK_PIN( + 35, "GPIO35", + MTK_EINT_FUNCTION(0, 35), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO35"), + MTK_FUNCTION(1, "ANT_SEL2"), + MTK_FUNCTION(2, "SSPM_JTAG_TCK_VCORE"), + MTK_FUNCTION(3, "UDI_TCK"), + MTK_FUNCTION(5, "CONN_BPI_BUS20_ANT3"), + MTK_FUNCTION(6, "MD_UCTS1") + ), + MTK_PIN( + 36, "GPIO36", + MTK_EINT_FUNCTION(0, 36), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO36"), + MTK_FUNCTION(1, "ANT_SEL3"), + MTK_FUNCTION(2, "SSPM_JTAG_TRSTN_VCORE"), + MTK_FUNCTION(3, "UDI_NTRST"), + MTK_FUNCTION(5, "CONN_BPI_BUS21_ANT4"), + MTK_FUNCTION(6, "MD_URTS1") + ), + MTK_PIN( + 37, "GPIO37", + MTK_EINT_FUNCTION(0, 37), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO37"), + MTK_FUNCTION(1, "ANT_SEL4"), + MTK_FUNCTION(2, "SSPM_JTAG_TDI_VCORE"), + MTK_FUNCTION(3, "UDI_TDI"), + MTK_FUNCTION(6, "TP_UCTS1_VCORE") + ), + MTK_PIN( + 38, "GPIO38", + MTK_EINT_FUNCTION(0, 38), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO38"), + MTK_FUNCTION(1, "ANT_SEL5"), + MTK_FUNCTION(2, "SSPM_JTAG_TMS_VCORE"), + MTK_FUNCTION(3, "UDI_TMS"), + MTK_FUNCTION(6, "TP_URTS1_VCORE") + ), + MTK_PIN( + 39, "GPIO39", + MTK_EINT_FUNCTION(0, 39), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO39"), + MTK_FUNCTION(1, "ANT_SEL6"), + MTK_FUNCTION(2, "SSPM_JTAG_TDO_VCORE"), + MTK_FUNCTION(3, "UDI_TDO"), + MTK_FUNCTION(5, "CLKM3") + ), + MTK_PIN( + 40, "GPIO40", + MTK_EINT_FUNCTION(0, 40), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO40"), + MTK_FUNCTION(1, "ANT_SEL7"), + MTK_FUNCTION(2, "PMSR_SMAP"), + MTK_FUNCTION(3, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(4, "CONN_WIFI_TXD"), + MTK_FUNCTION(5, "GPS_PPS") + ), + MTK_PIN( + 41, "GPIO41", + MTK_EINT_FUNCTION(0, 41), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO41"), + MTK_FUNCTION(1, "I2SIN1_MCK"), + MTK_FUNCTION(2, "IDDIG"), + MTK_FUNCTION(3, "GPS_PPS"), + MTK_FUNCTION(4, "HFRP_UCTS1"), + MTK_FUNCTION(5, "TP_UCTS2_VCORE"), + MTK_FUNCTION(6, "ANT_SEL8"), + MTK_FUNCTION(7, "DBG_MON_B1") + ), + MTK_PIN( + 42, "GPIO42", + MTK_EINT_FUNCTION(0, 42), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO42"), + MTK_FUNCTION(1, "I2SIN1_BCK"), + MTK_FUNCTION(2, "I2SIN4_BCK"), + MTK_FUNCTION(4, "HFRP_URTS1"), + MTK_FUNCTION(5, "TP_URTS2_VCORE"), + MTK_FUNCTION(6, "ANT_SEL9"), + MTK_FUNCTION(7, "DBG_MON_B2") + ), + MTK_PIN( + 43, "GPIO43", + MTK_EINT_FUNCTION(0, 43), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO43"), + MTK_FUNCTION(1, "I2SIN1_LRCK"), + MTK_FUNCTION(2, "I2SIN4_LRCK"), + MTK_FUNCTION(6, "ANT_SEL10"), + MTK_FUNCTION(7, "DBG_MON_B3") + ), + MTK_PIN( + 44, "GPIO44", + MTK_EINT_FUNCTION(0, 44), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO44"), + MTK_FUNCTION(1, "I2SOUT1_DO"), + MTK_FUNCTION(2, "I2SOUT4_DATA0"), + MTK_FUNCTION(6, "ANT_SEL11"), + MTK_FUNCTION(7, "DBG_MON_B4") + ), + MTK_PIN( + 45, "GPIO45", + MTK_EINT_FUNCTION(0, 45), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO45"), + MTK_FUNCTION(1, "I2SIN1_DI"), + MTK_FUNCTION(2, "I2SIN4_DATA0"), + MTK_FUNCTION(5, "AGPS_SYNC"), + MTK_FUNCTION(6, "ANT_SEL12"), + MTK_FUNCTION(7, "DBG_MON_B5") + ), + MTK_PIN( + 46, "GPIO46", + MTK_EINT_FUNCTION(0, 46), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO46"), + MTK_FUNCTION(1, "MD_INT1_C2K_UIM0_HOT_PLUG"), + MTK_FUNCTION(2, "MD_INT2_C2K_UIM1_HOT_PLUG"), + MTK_FUNCTION(3, "SRCLKENAI0"), + MTK_FUNCTION(5, "SSPM_UTXD_AO_VLP"), + MTK_FUNCTION(6, "MD_MCIF_UTXD0"), + MTK_FUNCTION(7, "DBG_MON_B6") + ), + MTK_PIN( + 47, "GPIO47", + MTK_EINT_FUNCTION(0, 47), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO47"), + MTK_FUNCTION(1, "MD_INT2_C2K_UIM1_HOT_PLUG"), + MTK_FUNCTION(2, "MD_INT1_C2K_UIM0_HOT_PLUG"), + MTK_FUNCTION(3, "SRCLKENAI1"), + MTK_FUNCTION(4, "SRCLKENA1"), + MTK_FUNCTION(5, "SSPM_URXD_AO_VLP"), + MTK_FUNCTION(6, "MD_MCIF_URXD0"), + MTK_FUNCTION(7, "DBG_MON_B7") + ), + MTK_PIN( + 48, "GPIO48", + MTK_EINT_FUNCTION(0, 48), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO48"), + MTK_FUNCTION(1, "UTXD0"), + MTK_FUNCTION(3, "MD_UTXD1"), + MTK_FUNCTION(4, "HFRP_UTXD1"), + MTK_FUNCTION(5, "MD32_0_TXD") + ), + MTK_PIN( + 49, "GPIO49", + MTK_EINT_FUNCTION(0, 49), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO49"), + MTK_FUNCTION(1, "URXD0"), + MTK_FUNCTION(3, "MD_URXD1"), + MTK_FUNCTION(4, "HFRP_URXD1"), + MTK_FUNCTION(5, "MD32_0_RXD") + ), + MTK_PIN( + 50, "GPIO50", + MTK_EINT_FUNCTION(0, 50), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO50"), + MTK_FUNCTION(1, "MD_UTXD0"), + MTK_FUNCTION(2, "TP_UTXD1_VLP"), + MTK_FUNCTION(3, "CONN_BGF_UART0_TXD"), + MTK_FUNCTION(4, "SSPM_UTXD_AO_VLP"), + MTK_FUNCTION(5, "MD_MCIF_UTXD0"), + MTK_FUNCTION(6, "TP_UTXD2_VLP"), + MTK_FUNCTION(7, "UTXD1") + ), + MTK_PIN( + 51, "GPIO51", + MTK_EINT_FUNCTION(0, 51), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO51"), + MTK_FUNCTION(1, "MD_URXD0"), + MTK_FUNCTION(2, "TP_URXD1_VLP"), + MTK_FUNCTION(3, "CONN_BGF_UART0_RXD"), + MTK_FUNCTION(4, "SSPM_URXD_AO_VLP"), + MTK_FUNCTION(5, "MD_MCIF_URXD0"), + MTK_FUNCTION(6, "TP_URXD2_VLP"), + MTK_FUNCTION(7, "URXD1") + ), + MTK_PIN( + 52, "GPIO52", + MTK_EINT_FUNCTION(0, 52), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO52"), + MTK_FUNCTION(1, "KPROW0"), + MTK_FUNCTION(2, "CMFLASH0"), + MTK_FUNCTION(3, "SDA12"), + MTK_FUNCTION(4, "DSI_TE1") + ), + MTK_PIN( + 53, "GPIO53", + MTK_EINT_FUNCTION(0, 53), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO53"), + MTK_FUNCTION(1, "KPROW1"), + MTK_FUNCTION(2, "CMFLASH1"), + MTK_FUNCTION(3, "SCL12"), + MTK_FUNCTION(4, "LCM_RST1"), + MTK_FUNCTION(6, "EXTIF0_ACT") + ), + MTK_PIN( + 54, "GPIO54", + MTK_EINT_FUNCTION(0, 54), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO54"), + MTK_FUNCTION(1, "KPCOL0_VLP"), + MTK_FUNCTION(7, "KPCOL0_VLP") + ), + MTK_PIN( + 55, "GPIO55", + MTK_EINT_FUNCTION(0, 55), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO55"), + MTK_FUNCTION(1, "KPCOL1"), + MTK_FUNCTION(3, "SDA12"), + MTK_FUNCTION(4, "DISP_PWM1"), + MTK_FUNCTION(7, "JTRSTN_SEL1_VCORE") + ), + MTK_PIN( + 56, "GPIO56", + MTK_EINT_FUNCTION(0, 56), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO56"), + MTK_FUNCTION(1, "SPI0_CLK"), + MTK_FUNCTION(7, "JTCK_SEL1_VCORE") + ), + MTK_PIN( + 57, "GPIO57", + MTK_EINT_FUNCTION(0, 57), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO57"), + MTK_FUNCTION(1, "SPI0_CSB"), + MTK_FUNCTION(7, "JTMS_SEL1_VCORE") + ), + MTK_PIN( + 58, "GPIO58", + MTK_EINT_FUNCTION(0, 58), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO58"), + MTK_FUNCTION(1, "SPI0_MO"), + MTK_FUNCTION(7, "JTDO_SEL1_VCORE") + ), + MTK_PIN( + 59, "GPIO59", + MTK_EINT_FUNCTION(0, 59), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO59"), + MTK_FUNCTION(1, "SPI0_MI"), + MTK_FUNCTION(7, "JTDI_SEL1_VCORE") + ), + MTK_PIN( + 60, "GPIO60", + MTK_EINT_FUNCTION(0, 60), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO60"), + MTK_FUNCTION(1, "SCP_SPI1_CK"), + MTK_FUNCTION(2, "SPI1_CLK"), + MTK_FUNCTION(4, "SCP_SCL3"), + MTK_FUNCTION(5, "TP_GPIO0_AO"), + MTK_FUNCTION(6, "UTXD0"), + MTK_FUNCTION(7, "TP_UTXD2_VLP") + ), + MTK_PIN( + 61, "GPIO61", + MTK_EINT_FUNCTION(0, 61), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO61"), + MTK_FUNCTION(1, "SCP_SPI1_CS"), + MTK_FUNCTION(2, "SPI1_CSB"), + MTK_FUNCTION(5, "TP_GPIO1_AO"), + MTK_FUNCTION(6, "URXD0"), + MTK_FUNCTION(7, "TP_URXD2_VLP") + ), + MTK_PIN( + 62, "GPIO62", + MTK_EINT_FUNCTION(0, 62), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO62"), + MTK_FUNCTION(1, "SCP_SPI1_MO"), + MTK_FUNCTION(2, "SPI1_MO"), + MTK_FUNCTION(3, "SCP_SCL3"), + MTK_FUNCTION(4, "SCP_SDA3"), + MTK_FUNCTION(5, "TP_GPIO2_AO"), + MTK_FUNCTION(7, "DBG_MON_B29") + ), + MTK_PIN( + 63, "GPIO63", + MTK_EINT_FUNCTION(0, 63), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO63"), + MTK_FUNCTION(1, "SCP_SPI1_MI"), + MTK_FUNCTION(2, "SPI1_MI"), + MTK_FUNCTION(3, "SCP_SDA3"), + MTK_FUNCTION(5, "TP_GPIO3_AO"), + MTK_FUNCTION(7, "DBG_MON_B30") + ), + MTK_PIN( + 64, "GPIO64", + MTK_EINT_FUNCTION(0, 64), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO64"), + MTK_FUNCTION(1, "SCP_SPI2_CK"), + MTK_FUNCTION(2, "SPI2_CLK"), + MTK_FUNCTION(4, "SCP_SCL2"), + MTK_FUNCTION(5, "TP_GPIO4_AO") + ), + MTK_PIN( + 65, "GPIO65", + MTK_EINT_FUNCTION(0, 65), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO65"), + MTK_FUNCTION(1, "SCP_SPI2_CS"), + MTK_FUNCTION(2, "SPI2_CSB"), + MTK_FUNCTION(5, "TP_GPIO5_AO"), + MTK_FUNCTION(7, "DBG_MON_B31") + ), + MTK_PIN( + 66, "GPIO66", + MTK_EINT_FUNCTION(0, 66), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO66"), + MTK_FUNCTION(1, "SCP_SPI2_MO"), + MTK_FUNCTION(2, "SPI2_MO"), + MTK_FUNCTION(3, "SCP_SCL2"), + MTK_FUNCTION(4, "SCP_SDA2"), + MTK_FUNCTION(5, "TP_GPIO6_AO") + ), + MTK_PIN( + 67, "GPIO67", + MTK_EINT_FUNCTION(0, 67), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO67"), + MTK_FUNCTION(1, "SCP_SPI2_MI"), + MTK_FUNCTION(2, "SPI2_MI"), + MTK_FUNCTION(3, "SCP_SDA2"), + MTK_FUNCTION(5, "TP_GPIO7_AO") + ), + MTK_PIN( + 68, "GPIO68", + MTK_EINT_FUNCTION(0, 68), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO68"), + MTK_FUNCTION(1, "SCP_SPI3_CK"), + MTK_FUNCTION(2, "SPI3_CLK"), + MTK_FUNCTION(3, "MD_INT4"), + MTK_FUNCTION(4, "SCP_SCL4"), + MTK_FUNCTION(5, "TP_GPIO8_AO"), + MTK_FUNCTION(7, "DBG_MON_A19") + ), + MTK_PIN( + 69, "GPIO69", + MTK_EINT_FUNCTION(0, 69), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO69"), + MTK_FUNCTION(1, "SCP_SPI3_CS"), + MTK_FUNCTION(2, "SPI3_CSB"), + MTK_FUNCTION(3, "MD_INT3"), + MTK_FUNCTION(5, "TP_GPIO9_AO"), + MTK_FUNCTION(7, "DBG_MON_A20") + ), + MTK_PIN( + 70, "GPIO70", + MTK_EINT_FUNCTION(0, 70), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO70"), + MTK_FUNCTION(1, "SCP_SPI3_MO"), + MTK_FUNCTION(2, "SPI3_MO"), + MTK_FUNCTION(3, "SCP_SCL4"), + MTK_FUNCTION(4, "SCP_SDA4"), + MTK_FUNCTION(5, "TP_GPIO10_AO"), + MTK_FUNCTION(7, "DBG_MON_A21") + ), + MTK_PIN( + 71, "GPIO71", + MTK_EINT_FUNCTION(0, 71), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO71"), + MTK_FUNCTION(1, "SCP_SPI3_MI"), + MTK_FUNCTION(2, "SPI3_MI"), + MTK_FUNCTION(3, "SCP_SDA4"), + MTK_FUNCTION(4, "MD_INT0"), + MTK_FUNCTION(5, "TP_GPIO11_AO"), + MTK_FUNCTION(7, "DBG_MON_A22") + ), + MTK_PIN( + 72, "GPIO72", + MTK_EINT_FUNCTION(0, 72), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO72"), + MTK_FUNCTION(1, "SPI5_CLK"), + MTK_FUNCTION(2, "SCP_SPI0_CK"), + MTK_FUNCTION(3, "UCTS2"), + MTK_FUNCTION(4, "MBISTREADEN_TRIGGER"), + MTK_FUNCTION(5, "TP_GPIO12_AO"), + MTK_FUNCTION(6, "EXTIF0_ACT"), + MTK_FUNCTION(7, "DAP_SONIC_SWCK") + ), + MTK_PIN( + 73, "GPIO73", + MTK_EINT_FUNCTION(0, 73), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO73"), + MTK_FUNCTION(1, "SPI5_CSB"), + MTK_FUNCTION(2, "SCP_SPI0_CS"), + MTK_FUNCTION(3, "URTS2"), + MTK_FUNCTION(4, "MBISTWRITEEN_TRIGGER"), + MTK_FUNCTION(5, "TP_GPIO13_AO"), + MTK_FUNCTION(6, "EXTIF0_PRI"), + MTK_FUNCTION(7, "DAP_SONIC_SWD") + ), + MTK_PIN( + 74, "GPIO74", + MTK_EINT_FUNCTION(0, 74), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO74"), + MTK_FUNCTION(1, "SPI5_MO"), + MTK_FUNCTION(2, "SCP_SPI0_MO"), + MTK_FUNCTION(3, "UTXD2"), + MTK_FUNCTION(4, "TP_UTXD2_VCORE"), + MTK_FUNCTION(5, "TP_GPIO14_AO"), + MTK_FUNCTION(6, "EXTIF0_GNT_B"), + MTK_FUNCTION(7, "DAP_MD32_SWCK") + ), + MTK_PIN( + 75, "GPIO75", + MTK_EINT_FUNCTION(0, 75), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO75"), + MTK_FUNCTION(1, "SPI5_MI"), + MTK_FUNCTION(2, "SCP_SPI0_MI"), + MTK_FUNCTION(3, "URXD2"), + MTK_FUNCTION(4, "TP_URXD2_VCORE"), + MTK_FUNCTION(5, "TP_GPIO15_AO"), + MTK_FUNCTION(7, "DAP_MD32_SWD") + ), + MTK_PIN( + 76, "GPIO76", + MTK_EINT_FUNCTION(0, 76), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO76"), + MTK_FUNCTION(1, "AP_GOOD"), + MTK_FUNCTION(3, "CONN_WIFI_TXD"), + MTK_FUNCTION(4, "GPS_PPS"), + MTK_FUNCTION(5, "PMSR_SMAP"), + MTK_FUNCTION(6, "AGPS_SYNC") + ), + MTK_PIN( + 77, "GPIO77", + MTK_EINT_FUNCTION(0, 77), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO77"), + MTK_FUNCTION(1, "MSDC1_CLK"), + MTK_FUNCTION(2, "MD1_SIM2_SCLK"), + MTK_FUNCTION(3, "UDI_TCK"), + MTK_FUNCTION(4, "CONN_DSP_JCK"), + MTK_FUNCTION(6, "TSFDC_EN"), + MTK_FUNCTION(7, "SSPM_JTAG_TCK_VCORE") + ), + MTK_PIN( + 78, "GPIO78", + MTK_EINT_FUNCTION(0, 78), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO78"), + MTK_FUNCTION(1, "MSDC1_CMD"), + MTK_FUNCTION(2, "CONN_WF_MCU_AICE_TMSC"), + MTK_FUNCTION(3, "UDI_TMS"), + MTK_FUNCTION(4, "CONN_DSP_JMS"), + MTK_FUNCTION(6, "TSFDC_VCO_RST"), + MTK_FUNCTION(7, "SSPM_JTAG_TMS_VCORE") + ), + MTK_PIN( + 79, "GPIO79", + MTK_EINT_FUNCTION(0, 79), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO79"), + MTK_FUNCTION(1, "MSDC1_DAT0"), + MTK_FUNCTION(2, "MD1_SIM2_SRST"), + MTK_FUNCTION(3, "UDI_TDI"), + MTK_FUNCTION(4, "CONN_DSP_JDI"), + MTK_FUNCTION(6, "TSFDC_TSSEL2"), + MTK_FUNCTION(7, "SSPM_JTAG_TDI_VCORE") + ), + MTK_PIN( + 80, "GPIO80", + MTK_EINT_FUNCTION(0, 80), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO80"), + MTK_FUNCTION(1, "MSDC1_DAT1"), + MTK_FUNCTION(2, "MD1_SIM2_SIO"), + MTK_FUNCTION(3, "UDI_TDO"), + MTK_FUNCTION(4, "CONN_DSP_JDO"), + MTK_FUNCTION(6, "TSFDC_TSSEL1"), + MTK_FUNCTION(7, "SSPM_JTAG_TDO_VCORE") + ), + MTK_PIN( + 81, "GPIO81", + MTK_EINT_FUNCTION(0, 81), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO81"), + MTK_FUNCTION(1, "MSDC1_DAT2"), + MTK_FUNCTION(2, "CONN_WF_MCU_AICE_TCKC"), + MTK_FUNCTION(3, "UDI_NTRST"), + MTK_FUNCTION(4, "CONN_BGF_MCU_AICE_TCKC"), + MTK_FUNCTION(5, "MIPI3_D_SDATA"), + MTK_FUNCTION(6, "TSFDC_TSSEL0"), + MTK_FUNCTION(7, "SSPM_JTAG_TRSTN_VCORE") + ), + MTK_PIN( + 82, "GPIO82", + MTK_EINT_FUNCTION(0, 82), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO82"), + MTK_FUNCTION(1, "MSDC1_DAT3"), + MTK_FUNCTION(3, "CONN_BGF_MCU_AICE_TMSC"), + MTK_FUNCTION(4, "CONN_DSP_JINTP"), + MTK_FUNCTION(5, "MIPI3_D_SCLK"), + MTK_FUNCTION(6, "TSFDC_RCK_SELB") + ), + MTK_PIN( + 83, "GPIO83", + MTK_EINT_FUNCTION(0, 83), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO83"), + MTK_FUNCTION(1, "MD1_SIM1_SCLK"), + MTK_FUNCTION(6, "TSFDC_26M") + ), + MTK_PIN( + 84, "GPIO84", + MTK_EINT_FUNCTION(0, 84), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO84"), + MTK_FUNCTION(1, "MD1_SIM1_SRST"), + MTK_FUNCTION(3, "SPM_JTAG_TCK_VCORE"), + MTK_FUNCTION(4, "APU_JTAG_TCK"), + MTK_FUNCTION(6, "TSFDC_SDO"), + MTK_FUNCTION(7, "CONN_DSP_L5_JCK") + ), + MTK_PIN( + 85, "GPIO85", + MTK_EINT_FUNCTION(0, 85), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO85"), + MTK_FUNCTION(1, "MD1_SIM1_SIO"), + MTK_FUNCTION(3, "SPM_JTAG_TRSTN_VCORE"), + MTK_FUNCTION(4, "APU_JTAG_TRST"), + MTK_FUNCTION(6, "TSFDC_FOUT"), + MTK_FUNCTION(7, "CONN_DSP_L5_JINTP") + ), + MTK_PIN( + 86, "GPIO86", + MTK_EINT_FUNCTION(0, 86), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO86"), + MTK_FUNCTION(1, "MD1_SIM2_SCLK"), + MTK_FUNCTION(3, "SPM_JTAG_TDI_VCORE"), + MTK_FUNCTION(4, "APU_JTAG_TDI"), + MTK_FUNCTION(6, "TSFDC_SCK"), + MTK_FUNCTION(7, "CONN_DSP_L5_JDI") + ), + MTK_PIN( + 87, "GPIO87", + MTK_EINT_FUNCTION(0, 87), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO87"), + MTK_FUNCTION(1, "MD1_SIM2_SRST"), + MTK_FUNCTION(3, "SPM_JTAG_TMS_VCORE"), + MTK_FUNCTION(4, "APU_JTAG_TMS"), + MTK_FUNCTION(6, "TSFDC_SDI"), + MTK_FUNCTION(7, "CONN_DSP_L5_JMS") + ), + MTK_PIN( + 88, "GPIO88", + MTK_EINT_FUNCTION(0, 88), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO88"), + MTK_FUNCTION(1, "MD1_SIM2_SIO"), + MTK_FUNCTION(3, "SPM_JTAG_TDO_VCORE"), + MTK_FUNCTION(4, "APU_JTAG_TDO"), + MTK_FUNCTION(6, "TSFDC_SCF"), + MTK_FUNCTION(7, "CONN_DSP_L5_JDO") + ), + MTK_PIN( + 89, "GPIO89", + MTK_EINT_FUNCTION(0, 89), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO89"), + MTK_FUNCTION(1, "DSI_TE"), + MTK_FUNCTION(7, "DBG_MON_B8") + ), + MTK_PIN( + 90, "GPIO90", + MTK_EINT_FUNCTION(0, 90), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO90"), + MTK_FUNCTION(1, "LCM_RST"), + MTK_FUNCTION(7, "DBG_MON_B9") + ), + MTK_PIN( + 91, "GPIO91", + MTK_EINT_FUNCTION(0, 91), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO91"), + MTK_FUNCTION(1, "DISP_PWM"), + MTK_FUNCTION(7, "DBG_MON_B10") + ), + MTK_PIN( + 92, "GPIO92", + MTK_EINT_FUNCTION(0, 92), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO92"), + MTK_FUNCTION(1, "CMMCLK0"), + MTK_FUNCTION(7, "DBG_MON_A23") + ), + MTK_PIN( + 93, "GPIO93", + MTK_EINT_FUNCTION(0, 93), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO93"), + MTK_FUNCTION(1, "CMMCLK1"), + MTK_FUNCTION(7, "DBG_MON_A24") + ), + MTK_PIN( + 94, "GPIO94", + MTK_EINT_FUNCTION(0, 94), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO94"), + MTK_FUNCTION(1, "CMMCLK2"), + MTK_FUNCTION(7, "DBG_MON_A25") + ), + MTK_PIN( + 95, "GPIO95", + MTK_EINT_FUNCTION(0, 95), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO95"), + MTK_FUNCTION(1, "CMMCLK3"), + MTK_FUNCTION(5, "MD32_1_TXD"), + MTK_FUNCTION(6, "PTA_TXD"), + MTK_FUNCTION(7, "DBG_MON_A26") + ), + MTK_PIN( + 96, "GPIO96", + MTK_EINT_FUNCTION(0, 96), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO96"), + MTK_FUNCTION(1, "CMMCLK4"), + MTK_FUNCTION(5, "MD32_1_RXD"), + MTK_FUNCTION(6, "PTA_RXD"), + MTK_FUNCTION(7, "DBG_MON_A27") + ), + MTK_PIN( + 97, "GPIO97", + MTK_EINT_FUNCTION(0, 97), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO97"), + MTK_FUNCTION(1, "MD_UCNT_A_TGL") + ), + MTK_PIN( + 98, "GPIO98", + MTK_EINT_FUNCTION(0, 98), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO98"), + MTK_FUNCTION(1, "DIGRF_IRQ") + ), + MTK_PIN( + 99, "GPIO99", + MTK_EINT_FUNCTION(0, 99), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO99"), + MTK_FUNCTION(1, "BPI_BUS0"), + MTK_FUNCTION(4, "MFG_TSFDC_EN"), + MTK_FUNCTION(6, "ANT_SEL0"), + MTK_FUNCTION(7, "DBG_MON_B11") + ), + MTK_PIN( + 100, "GPIO100", + MTK_EINT_FUNCTION(0, 100), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO100"), + MTK_FUNCTION(1, "BPI_BUS1"), + MTK_FUNCTION(4, "MFG_TSFDC_VCO_RST"), + MTK_FUNCTION(6, "ANT_SEL1"), + MTK_FUNCTION(7, "DBG_MON_B12") + ), + MTK_PIN( + 101, "GPIO101", + MTK_EINT_FUNCTION(0, 101), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO101"), + MTK_FUNCTION(1, "BPI_BUS2"), + MTK_FUNCTION(3, "DMIC1_CLK"), + MTK_FUNCTION(4, "MFG_TSFDC_TSSEL2"), + MTK_FUNCTION(6, "ANT_SEL2"), + MTK_FUNCTION(7, "DBG_MON_B13") + ), + MTK_PIN( + 102, "GPIO102", + MTK_EINT_FUNCTION(0, 102), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO102"), + MTK_FUNCTION(1, "BPI_BUS3"), + MTK_FUNCTION(3, "DMIC1_DAT"), + MTK_FUNCTION(4, "MFG_TSFDC_TSSEL1"), + MTK_FUNCTION(6, "ANT_SEL3"), + MTK_FUNCTION(7, "DBG_MON_B14") + ), + MTK_PIN( + 103, "GPIO103", + MTK_EINT_FUNCTION(0, 103), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO103"), + MTK_FUNCTION(1, "BPI_BUS4"), + MTK_FUNCTION(4, "MFG_TSFDC_TSSEL0"), + MTK_FUNCTION(6, "ANT_SEL4"), + MTK_FUNCTION(7, "DBG_MON_B15") + ), + MTK_PIN( + 104, "GPIO104", + MTK_EINT_FUNCTION(0, 104), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO104"), + MTK_FUNCTION(1, "BPI_BUS5"), + MTK_FUNCTION(4, "MFG_TSFDC_RCK_SELB"), + MTK_FUNCTION(6, "ANT_SEL5"), + MTK_FUNCTION(7, "DBG_MON_B16") + ), + MTK_PIN( + 105, "GPIO105", + MTK_EINT_FUNCTION(0, 105), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO105"), + MTK_FUNCTION(1, "BPI_BUS6"), + MTK_FUNCTION(2, "CONN_BPI_BUS6"), + MTK_FUNCTION(6, "ANT_SEL6"), + MTK_FUNCTION(7, "DBG_MON_B17") + ), + MTK_PIN( + 106, "GPIO106", + MTK_EINT_FUNCTION(0, 106), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO106"), + MTK_FUNCTION(1, "BPI_BUS7"), + MTK_FUNCTION(2, "CONN_BPI_BUS7"), + MTK_FUNCTION(4, "MFG_TSFDC_SDO"), + MTK_FUNCTION(5, "AUD_DAC_26M_CLK"), + MTK_FUNCTION(6, "ANT_SEL7"), + MTK_FUNCTION(7, "DBG_MON_B18") + ), + MTK_PIN( + 107, "GPIO107", + MTK_EINT_FUNCTION(0, 107), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO107"), + MTK_FUNCTION(1, "BPI_BUS8"), + MTK_FUNCTION(2, "CONN_BPI_BUS8"), + MTK_FUNCTION(4, "MFG_TSFDC_FOUT"), + MTK_FUNCTION(5, "I2SOUT4_DATA0"), + MTK_FUNCTION(6, "ANT_SEL8"), + MTK_FUNCTION(7, "DBG_MON_B19") + ), + MTK_PIN( + 108, "GPIO108", + MTK_EINT_FUNCTION(0, 108), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO108"), + MTK_FUNCTION(1, "BPI_BUS9"), + MTK_FUNCTION(2, "CONN_BPI_BUS9"), + MTK_FUNCTION(5, "I2SOUT4_DATA1"), + MTK_FUNCTION(6, "ANT_SEL9"), + MTK_FUNCTION(7, "DBG_MON_B20") + ), + MTK_PIN( + 109, "GPIO109", + MTK_EINT_FUNCTION(0, 109), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO109"), + MTK_FUNCTION(1, "BPI_BUS10"), + MTK_FUNCTION(2, "CONN_BPI_BUS10"), + MTK_FUNCTION(5, "I2SOUT4_DATA2"), + MTK_FUNCTION(6, "ANT_SEL10"), + MTK_FUNCTION(7, "DBG_MON_B21") + ), + MTK_PIN( + 110, "GPIO110", + MTK_EINT_FUNCTION(0, 110), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO110"), + MTK_FUNCTION(1, "BPI_BUS11"), + MTK_FUNCTION(2, "CONN_BPI_BUS11_OLAT0"), + MTK_FUNCTION(5, "I2SOUT4_DATA3"), + MTK_FUNCTION(6, "ANT_SEL11"), + MTK_FUNCTION(7, "DBG_MON_B22") + ), + MTK_PIN( + 111, "GPIO111", + MTK_EINT_FUNCTION(0, 111), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO111"), + MTK_FUNCTION(1, "BPI_BUS12"), + MTK_FUNCTION(2, "CONN_BPI_BUS12_OLAT1"), + MTK_FUNCTION(3, "CLKM0"), + MTK_FUNCTION(5, "I2SIN4_BCK"), + MTK_FUNCTION(6, "ANT_SEL12"), + MTK_FUNCTION(7, "DBG_MON_B23") + ), + MTK_PIN( + 112, "GPIO112", + MTK_EINT_FUNCTION(0, 112), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO112"), + MTK_FUNCTION(1, "BPI_BUS13"), + MTK_FUNCTION(2, "CONN_BPI_BUS13_OLAT2"), + MTK_FUNCTION(3, "CLKM1"), + MTK_FUNCTION(5, "I2SIN4_DATA0"), + MTK_FUNCTION(6, "ANT_SEL13"), + MTK_FUNCTION(7, "DBG_MON_B24") + ), + MTK_PIN( + 113, "GPIO113", + MTK_EINT_FUNCTION(0, 113), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO113"), + MTK_FUNCTION(1, "BPI_BUS14"), + MTK_FUNCTION(2, "CONN_BPI_BUS14_OLAT3"), + MTK_FUNCTION(3, "CLKM2"), + MTK_FUNCTION(5, "I2SIN4_DATA1"), + MTK_FUNCTION(6, "ANT_SEL14"), + MTK_FUNCTION(7, "DBG_MON_B25") + ), + MTK_PIN( + 114, "GPIO114", + MTK_EINT_FUNCTION(0, 114), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO114"), + MTK_FUNCTION(1, "BPI_BUS15"), + MTK_FUNCTION(2, "CONN_BPI_BUS15_OLAT4"), + MTK_FUNCTION(3, "CLKM3"), + MTK_FUNCTION(5, "I2SIN4_DATA2"), + MTK_FUNCTION(6, "ANT_SEL15"), + MTK_FUNCTION(7, "DBG_MON_B26") + ), + MTK_PIN( + 115, "GPIO115", + MTK_EINT_FUNCTION(0, 115), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO115"), + MTK_FUNCTION(1, "BPI_BUS16"), + MTK_FUNCTION(2, "CONN_BPI_BUS16_OLAT5"), + MTK_FUNCTION(5, "I2SIN4_DATA3"), + MTK_FUNCTION(6, "ANT_SEL16"), + MTK_FUNCTION(7, "DBG_MON_B27") + ), + MTK_PIN( + 116, "GPIO116", + MTK_EINT_FUNCTION(0, 116), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO116"), + MTK_FUNCTION(1, "BPI_BUS17"), + MTK_FUNCTION(2, "CONN_BPI_BUS17_ANT0"), + MTK_FUNCTION(5, "I2SIN4_LRCK"), + MTK_FUNCTION(6, "ANT_SEL17"), + MTK_FUNCTION(7, "DBG_MON_B28") + ), + MTK_PIN( + 117, "GPIO117", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO117"), + MTK_FUNCTION(1, "MIPI0_D_SCLK"), + MTK_FUNCTION(2, "CONN_MIPI0_SCLK"), + MTK_FUNCTION(3, "BPI_BUS18"), + MTK_FUNCTION(6, "ANT_SEL18") + ), + MTK_PIN( + 118, "GPIO118", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO118"), + MTK_FUNCTION(1, "MIPI0_D_SDATA"), + MTK_FUNCTION(2, "CONN_MIPI0_SDATA"), + MTK_FUNCTION(3, "BPI_BUS19"), + MTK_FUNCTION(6, "ANT_SEL19") + ), + MTK_PIN( + 119, "GPIO119", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO119"), + MTK_FUNCTION(1, "MIPI1_D_SCLK"), + MTK_FUNCTION(2, "CONN_MIPI1_SCLK"), + MTK_FUNCTION(3, "BPI_BUS20"), + MTK_FUNCTION(6, "ANT_SEL20") + ), + MTK_PIN( + 120, "GPIO120", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO120"), + MTK_FUNCTION(1, "MIPI1_D_SDATA"), + MTK_FUNCTION(2, "CONN_MIPI1_SDATA"), + MTK_FUNCTION(3, "BPI_BUS21"), + MTK_FUNCTION(6, "ANT_SEL21") + ), + MTK_PIN( + 121, "GPIO121", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO121"), + MTK_FUNCTION(1, "MIPI2_D_SCLK"), + MTK_FUNCTION(2, "MIPI4_D_SCLK"), + MTK_FUNCTION(3, "BPI_BUS22"), + MTK_FUNCTION(6, "MD_GPS_L1_BLANK") + ), + MTK_PIN( + 122, "GPIO122", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO122"), + MTK_FUNCTION(1, "MIPI2_D_SDATA"), + MTK_FUNCTION(2, "MIPI4_D_SDATA"), + MTK_FUNCTION(3, "BPI_BUS23"), + MTK_FUNCTION(6, "MD_GPS_L5_BLANK") + ), + MTK_PIN( + 123, "GPIO123", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO123"), + MTK_FUNCTION(1, "MIPI_M_SCLK") + ), + MTK_PIN( + 124, "GPIO124", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO124"), + MTK_FUNCTION(1, "MIPI_M_SDATA") + ), + MTK_PIN( + 125, "GPIO125", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO125"), + MTK_FUNCTION(1, "SCL0"), + MTK_FUNCTION(2, "SCP_SCL4"), + MTK_FUNCTION(3, "TP_UTXD2_VLP"), + MTK_FUNCTION(4, "TP_UCTS1_VLP"), + MTK_FUNCTION(5, "TP_GPIO4_AO"), + MTK_FUNCTION(6, "UTXD2") + ), + MTK_PIN( + 126, "GPIO126", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO126"), + MTK_FUNCTION(1, "SDA0"), + MTK_FUNCTION(2, "SCP_SDA4"), + MTK_FUNCTION(3, "TP_URXD2_VLP"), + MTK_FUNCTION(4, "TP_URTS1_VLP"), + MTK_FUNCTION(5, "TP_GPIO5_AO"), + MTK_FUNCTION(6, "URXD2") + ), + MTK_PIN( + 127, "GPIO127", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO127"), + MTK_FUNCTION(1, "SCL1"), + MTK_FUNCTION(2, "SCP_SCL5"), + MTK_FUNCTION(3, "TP_UCTS2_VLP"), + MTK_FUNCTION(4, "TP_UTXD1_VLP"), + MTK_FUNCTION(5, "TP_GPIO6_AO"), + MTK_FUNCTION(6, "MD_MCIF_UTXD0") + ), + MTK_PIN( + 128, "GPIO128", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO128"), + MTK_FUNCTION(1, "SDA1"), + MTK_FUNCTION(2, "SCP_SDA5"), + MTK_FUNCTION(3, "TP_URTS2_VLP"), + MTK_FUNCTION(4, "TP_URXD1_VLP"), + MTK_FUNCTION(5, "TP_GPIO7_AO"), + MTK_FUNCTION(6, "MD_MCIF_URXD0") + ), + MTK_PIN( + 129, "GPIO129", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO129"), + MTK_FUNCTION(1, "SCL2") + ), + MTK_PIN( + 130, "GPIO130", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO130"), + MTK_FUNCTION(1, "SDA2") + ), + MTK_PIN( + 131, "GPIO131", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO131"), + MTK_FUNCTION(1, "SCL3"), + MTK_FUNCTION(3, "TP_UTXD2_VCORE"), + MTK_FUNCTION(6, "SSPM_UTXD_AO_VCORE") + ), + MTK_PIN( + 132, "GPIO132", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO132"), + MTK_FUNCTION(1, "SDA3"), + MTK_FUNCTION(3, "TP_URXD2_VCORE"), + MTK_FUNCTION(6, "SSPM_URXD_AO_VCORE") + ), + MTK_PIN( + 133, "GPIO133", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO133"), + MTK_FUNCTION(1, "SCL4") + ), + MTK_PIN( + 134, "GPIO134", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO134"), + MTK_FUNCTION(1, "SDA4") + ), + MTK_PIN( + 135, "GPIO135", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO135"), + MTK_FUNCTION(1, "SCL5") + ), + MTK_PIN( + 136, "GPIO136", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO136"), + MTK_FUNCTION(1, "SDA5") + ), + MTK_PIN( + 137, "GPIO137", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO137"), + MTK_FUNCTION(1, "SCL6") + ), + MTK_PIN( + 138, "GPIO138", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO138"), + MTK_FUNCTION(1, "SDA6") + ), + MTK_PIN( + 139, "GPIO139", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO139"), + MTK_FUNCTION(1, "SCL7"), + MTK_FUNCTION(3, "TP_UTXD1_VCORE"), + MTK_FUNCTION(4, "MD_UTXD0"), + MTK_FUNCTION(6, "UTXD1") + ), + MTK_PIN( + 140, "GPIO140", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO140"), + MTK_FUNCTION(1, "SDA7"), + MTK_FUNCTION(3, "TP_URXD1_VCORE"), + MTK_FUNCTION(4, "MD_URXD0"), + MTK_FUNCTION(6, "URXD1") + ), + MTK_PIN( + 141, "GPIO141", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO141"), + MTK_FUNCTION(1, "SCL8") + ), + MTK_PIN( + 142, "GPIO142", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO142"), + MTK_FUNCTION(1, "SDA8") + ), + MTK_PIN( + 143, "GPIO143", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO143"), + MTK_FUNCTION(1, "SCL9"), + MTK_FUNCTION(2, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(3, "HFRP_UTXD1"), + MTK_FUNCTION(4, "CONN_BGF_MCU_AICE_TMSC"), + MTK_FUNCTION(5, "CONN_WF_MCU_AICE_TMSC"), + MTK_FUNCTION(7, "MBISTREADEN_TRIGGER") + ), + MTK_PIN( + 144, "GPIO144", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO144"), + MTK_FUNCTION(1, "SDA9"), + MTK_FUNCTION(2, "GPS_L5_ELNA_EN"), + MTK_FUNCTION(3, "HFRP_URXD1"), + MTK_FUNCTION(4, "CONN_BGF_MCU_AICE_TCKC"), + MTK_FUNCTION(5, "CONN_WF_MCU_AICE_TCKC"), + MTK_FUNCTION(7, "MBISTWRITEEN_TRIGGER") + ), + MTK_PIN( + 145, "GPIO145", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO145"), + MTK_FUNCTION(1, "SCL10"), + MTK_FUNCTION(2, "SCP_SCL0"), + MTK_FUNCTION(5, "TP_GPIO8_AO") + ), + MTK_PIN( + 146, "GPIO146", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO146"), + MTK_FUNCTION(1, "SDA10"), + MTK_FUNCTION(2, "SCP_SDA0"), + MTK_FUNCTION(5, "TP_GPIO9_AO") + ), + MTK_PIN( + 147, "GPIO147", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO147"), + MTK_FUNCTION(1, "SCL11"), + MTK_FUNCTION(2, "SCP_SCL1"), + MTK_FUNCTION(3, "SCP_DMIC_CLK"), + MTK_FUNCTION(4, "DMIC_CLK"), + MTK_FUNCTION(5, "TP_GPIO10_AO"), + MTK_FUNCTION(6, "EXTIF0_PRI") + ), + MTK_PIN( + 148, "GPIO148", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO148"), + MTK_FUNCTION(1, "SDA11"), + MTK_FUNCTION(2, "SCP_SDA1"), + MTK_FUNCTION(3, "SCP_DMIC_DAT"), + MTK_FUNCTION(4, "DMIC_DAT"), + MTK_FUNCTION(5, "TP_GPIO11_AO"), + MTK_FUNCTION(6, "EXTIF0_GNT_B") + ), + MTK_PIN( + 149, "GPIO149", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO149"), + MTK_FUNCTION(1, "KPROW2"), + MTK_FUNCTION(2, "PWM_VLP"), + MTK_FUNCTION(4, "MD_INT0"), + MTK_FUNCTION(5, "TP_GPIO12_AO"), + MTK_FUNCTION(6, "SCL0"), + MTK_FUNCTION(7, "DBG_MON_A28") + ), + MTK_PIN( + 150, "GPIO150", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO150"), + MTK_FUNCTION(1, "KPCOL2"), + MTK_FUNCTION(2, "PWM_VLP"), + MTK_FUNCTION(3, "CMMCLK5"), + MTK_FUNCTION(4, "MD_INT3"), + MTK_FUNCTION(5, "TP_GPIO13_AO"), + MTK_FUNCTION(6, "SDA0") + ), + MTK_PIN( + 151, "GPIO151", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO151"), + MTK_FUNCTION(1, "SRCLKENAI0"), + MTK_FUNCTION(4, "MD_INT4"), + MTK_FUNCTION(5, "TP_GPIO14_AO"), + MTK_FUNCTION(7, "DBG_MON_A29") + ), + MTK_PIN( + 152, "GPIO152", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO152"), + MTK_FUNCTION(1, "SRCLKENAI1"), + MTK_FUNCTION(4, "SPMI_M_TRIG_FLAG"), + MTK_FUNCTION(5, "TP_GPIO15_AO"), + MTK_FUNCTION(7, "DBG_MON_A30") + ), + MTK_PIN( + 153, "GPIO153", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO153"), + MTK_FUNCTION(1, "MD1_SIM2_SCLK"), + MTK_FUNCTION(2, "DISP_PWM1"), + MTK_FUNCTION(4, "SPMI_P_TRIG_FLAG"), + MTK_FUNCTION(7, "DBG_MON_A0") + ), + MTK_PIN( + 154, "GPIO154", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO154"), + MTK_FUNCTION(1, "MD1_SIM2_SRST"), + MTK_FUNCTION(2, "LCM_RST1"), + MTK_FUNCTION(3, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(4, "CMFLASH2"), + MTK_FUNCTION(5, "MBISTREADEN_TRIGGER"), + MTK_FUNCTION(7, "DBG_MON_A1") + ), + MTK_PIN( + 155, "GPIO155", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO155"), + MTK_FUNCTION(1, "MD1_SIM2_SIO"), + MTK_FUNCTION(2, "DSI_TE1"), + MTK_FUNCTION(3, "GPS_L5_ELNA_EN"), + MTK_FUNCTION(4, "CMFLASH3"), + MTK_FUNCTION(5, "MBISTWRITEEN_TRIGGER"), + MTK_FUNCTION(7, "DBG_MON_A2") + ), + MTK_PIN( + 156, "GPIO156", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO156"), + MTK_FUNCTION(1, "SPMI_M_SCL") + ), + MTK_PIN( + 157, "GPIO157", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO157"), + MTK_FUNCTION(1, "SPMI_M_SDA") + ), + MTK_PIN( + 158, "GPIO158", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO158"), + MTK_FUNCTION(1, "SPMI_P_SCL") + ), + MTK_PIN( + 159, "GPIO159", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO159"), + MTK_FUNCTION(1, "SPMI_P_SDA") + ), + MTK_PIN( + 160, "GPIO160", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO160"), + MTK_FUNCTION(1, "SRCLKENA0") + ), + MTK_PIN( + 161, "GPIO161", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO161"), + MTK_FUNCTION(1, "SCP_VREQ_VAO") + ), + MTK_PIN( + 162, "GPIO162", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO162"), + MTK_FUNCTION(1, "RTC32K_CK") + ), + MTK_PIN( + 163, "GPIO163", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO163"), + MTK_FUNCTION(1, "WATCHDOG") + ), + MTK_PIN( + 164, "GPIO164", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO164"), + MTK_FUNCTION(1, "AUD_CLK_MOSI"), + MTK_FUNCTION(3, "AUD_CLK_MOSI") + ), + MTK_PIN( + 165, "GPIO165", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO165"), + MTK_FUNCTION(1, "AUD_SYNC_MOSI") + ), + MTK_PIN( + 166, "GPIO166", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO166"), + MTK_FUNCTION(1, "AUD_DAT_MOSI0"), + MTK_FUNCTION(3, "AUD_DAT_MOSI0") + ), + MTK_PIN( + 167, "GPIO167", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO167"), + MTK_FUNCTION(1, "AUD_DAT_MOSI1"), + MTK_FUNCTION(3, "AUD_DAT_MOSI1") + ), + MTK_PIN( + 168, "GPIO168", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO168"), + MTK_FUNCTION(1, "AUD_NLE_MOSI0"), + MTK_FUNCTION(2, "AUD_SYNC_MISO") + ), + MTK_PIN( + 169, "GPIO169", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO169"), + MTK_FUNCTION(1, "AUD_NLE_MOSI1"), + MTK_FUNCTION(2, "AUD_CLK_MISO"), + MTK_FUNCTION(3, "AUD_CLK_MISO") + ), + MTK_PIN( + 170, "GPIO170", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO170"), + MTK_FUNCTION(1, "AUD_DAT_MISO0"), + MTK_FUNCTION(2, "VOW_DAT_MISO"), + MTK_FUNCTION(3, "AUD_DAT_MISO0") + ), + MTK_PIN( + 171, "GPIO171", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO171"), + MTK_FUNCTION(1, "AUD_DAT_MISO1"), + MTK_FUNCTION(2, "VOW_CLK_MISO"), + MTK_FUNCTION(3, "AUD_DAT_MISO1") + ), + MTK_PIN( + 172, "GPIO172", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO172"), + MTK_FUNCTION(1, "CONN_TOP_CLK"), + MTK_FUNCTION(7, "DBG_MON_A31") + ), + MTK_PIN( + 173, "GPIO173", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO173"), + MTK_FUNCTION(1, "CONN_TOP_DATA") + ), + MTK_PIN( + 174, "GPIO174", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO174"), + MTK_FUNCTION(1, "CONN_BT_CLK") + ), + MTK_PIN( + 175, "GPIO175", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO175"), + MTK_FUNCTION(1, "CONN_BT_DATA") + ), + MTK_PIN( + 176, "GPIO176", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO176"), + MTK_FUNCTION(1, "CONN_HRST_B") + ), + MTK_PIN( + 177, "GPIO177", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO177"), + MTK_FUNCTION(1, "CONN_WB_PTA") + ), + MTK_PIN( + 178, "GPIO178", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO178"), + MTK_FUNCTION(1, "CONN_WF_CTRL0") + ), + MTK_PIN( + 179, "GPIO179", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO179"), + MTK_FUNCTION(1, "CONN_WF_CTRL1") + ), + MTK_PIN( + 180, "GPIO180", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO180"), + MTK_FUNCTION(1, "CONN_WF_CTRL2") + ), + MTK_PIN( + 181, "GPIO181", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO181"), + MTK_FUNCTION(1, "CONN_WF_CTRL3"), + MTK_FUNCTION(2, "CONN_TOP_CLK_2"), + MTK_FUNCTION(3, "GPS_L1_ELNA_EN") + ), + MTK_PIN( + 182, "GPIO182", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO182"), + MTK_FUNCTION(1, "CONN_WF_CTRL4"), + MTK_FUNCTION(2, "CONN_TOP_DATA_2"), + MTK_FUNCTION(3, "GPS_L5_ELNA_EN") + ), + MTK_PIN( + 183, "GPIO183", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO183"), + MTK_FUNCTION(1, "CONN_HRST_B_2") + ), + MTK_PIN( + 184, "GPIO184", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO184"), + MTK_FUNCTION(1, "MSDC0_DSL"), + MTK_FUNCTION(3, "ANT_SEL13") + ), + MTK_PIN( + 185, "GPIO185", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO185"), + MTK_FUNCTION(1, "MSDC0_CLK"), + MTK_FUNCTION(2, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(3, "ANT_SEL14") + ), + MTK_PIN( + 186, "GPIO186", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO186"), + MTK_FUNCTION(1, "MSDC0_CMD"), + MTK_FUNCTION(2, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(3, "ANT_SEL15"), + MTK_FUNCTION(5, "I2SOUT4_DATA0") + ), + MTK_PIN( + 187, "GPIO187", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO187"), + MTK_FUNCTION(1, "MSDC0_RSTB"), + MTK_FUNCTION(2, "GPS_L5_ELNA_EN"), + MTK_FUNCTION(3, "ANT_SEL16"), + MTK_FUNCTION(5, "I2SOUT4_DATA1") + ), + MTK_PIN( + 188, "GPIO188", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO188"), + MTK_FUNCTION(1, "MSDC0_DAT0"), + MTK_FUNCTION(3, "ANT_SEL17"), + MTK_FUNCTION(5, "I2SOUT4_DATA2") + ), + MTK_PIN( + 189, "GPIO189", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO189"), + MTK_FUNCTION(1, "MSDC0_DAT1"), + MTK_FUNCTION(3, "ANT_SEL18"), + MTK_FUNCTION(5, "I2SOUT4_DATA3") + ), + MTK_PIN( + 190, "GPIO190", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO190"), + MTK_FUNCTION(1, "MSDC0_DAT2"), + MTK_FUNCTION(2, "DMIC1_CLK"), + MTK_FUNCTION(3, "ANT_SEL19"), + MTK_FUNCTION(5, "I2SIN4_BCK") + ), + MTK_PIN( + 191, "GPIO191", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO191"), + MTK_FUNCTION(1, "MSDC0_DAT3"), + MTK_FUNCTION(2, "DMIC1_DAT"), + MTK_FUNCTION(3, "ANT_SEL20"), + MTK_FUNCTION(5, "I2SIN4_DATA0") + ), + MTK_PIN( + 192, "GPIO192", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO192"), + MTK_FUNCTION(1, "MSDC0_DAT4"), + MTK_FUNCTION(2, "IDDIG"), + MTK_FUNCTION(3, "ANT_SEL21"), + MTK_FUNCTION(4, "UFS_MPHY_SCL"), + MTK_FUNCTION(5, "I2SIN4_DATA1") + ), + MTK_PIN( + 193, "GPIO193", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO193"), + MTK_FUNCTION(1, "MSDC0_DAT5"), + MTK_FUNCTION(2, "USB_DRVVBUS"), + MTK_FUNCTION(4, "UFS_MPHY_SDA"), + MTK_FUNCTION(5, "I2SIN4_DATA2") + ), + MTK_PIN( + 194, "GPIO194", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO194"), + MTK_FUNCTION(1, "MSDC0_DAT6"), + MTK_FUNCTION(2, "VBUSVALID"), + MTK_FUNCTION(5, "I2SIN4_DATA3") + ), + MTK_PIN( + 195, "GPIO195", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO195"), + MTK_FUNCTION(1, "MSDC0_DAT7"), + MTK_FUNCTION(5, "I2SIN4_LRCK") + ), + MTK_PIN( + 196, "GPIO196", + MTK_EINT_FUNCTION(0, 196), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 197, "GPIO197", + MTK_EINT_FUNCTION(0, 197), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 198, "GPIO198", + MTK_EINT_FUNCTION(0, 198), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 199, "GPIO199", + MTK_EINT_FUNCTION(0, 199), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 200, "GPIO200", + MTK_EINT_FUNCTION(0, 200), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 201, "GPIO201", + MTK_EINT_FUNCTION(0, 201), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 202, "GPIO202", + MTK_EINT_FUNCTION(0, 202), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 203, "GPIO203", + MTK_EINT_FUNCTION(0, 203), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 204, "GPIO204", + MTK_EINT_FUNCTION(0, 204), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 205, "GPIO205", + MTK_EINT_FUNCTION(0, 205), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 206, "GPIO206", + MTK_EINT_FUNCTION(0, 206), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 207, "GPIO207", + MTK_EINT_FUNCTION(0, 207), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 208, "GPIO208", + MTK_EINT_FUNCTION(0, 208), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 209, "GPIO209", + MTK_EINT_FUNCTION(0, 209), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 210, "GPIO210", + MTK_EINT_FUNCTION(0, 210), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 211, "GPIO211", + MTK_EINT_FUNCTION(0, 211), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 212, "GPIO212", + MTK_EINT_FUNCTION(0, 212), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 213, "GPIO213", + MTK_EINT_FUNCTION(0, 213), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 214, "GPIO214", + MTK_EINT_FUNCTION(0, 214), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 215, "GPIO215", + MTK_EINT_FUNCTION(0, 215), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), +}; + +static struct mtk_eint_pin eint_pins_mt6878[] = { + MTK_EINT_PIN(0, 0, 0, 1), + MTK_EINT_PIN(1, 0, 1, 1), + MTK_EINT_PIN(2, 0, 2, 1), + MTK_EINT_PIN(3, 0, 3, 1), + MTK_EINT_PIN(4, 0, 4, 1), + MTK_EINT_PIN(5, 0, 5, 1), + MTK_EINT_PIN(6, 1, 0, 1), + MTK_EINT_PIN(7, 1, 1, 1), + MTK_EINT_PIN(8, 1, 2, 1), + MTK_EINT_PIN(9, 1, 3, 1), + MTK_EINT_PIN(10, 1, 4, 1), + MTK_EINT_PIN(11, 1, 5, 1), + MTK_EINT_PIN(12, 1, 6, 1), + MTK_EINT_PIN(13, 2, 0, 1), + MTK_EINT_PIN(14, 2, 1, 1), + MTK_EINT_PIN(15, 2, 2, 1), + MTK_EINT_PIN(16, 2, 3, 1), + MTK_EINT_PIN(17, 2, 4, 1), + MTK_EINT_PIN(18, 2, 5, 1), + MTK_EINT_PIN(19, 0, 6, 1), + MTK_EINT_PIN(20, 0, 7, 1), + MTK_EINT_PIN(21, 0, 8, 1), + MTK_EINT_PIN(22, 0, 9, 1), + MTK_EINT_PIN(23, 0, 10, 1), + MTK_EINT_PIN(24, 0, 11, 1), + MTK_EINT_PIN(25, 0, 12, 1), + MTK_EINT_PIN(26, 0, 13, 1), + MTK_EINT_PIN(27, 0, 14, 1), + MTK_EINT_PIN(28, 0, 15, 1), + MTK_EINT_PIN(29, 2, 6, 1), + MTK_EINT_PIN(30, 2, 7, 1), + MTK_EINT_PIN(31, 2, 8, 1), + MTK_EINT_PIN(32, 2, 9, 1), + MTK_EINT_PIN(33, 0, 16, 1), + MTK_EINT_PIN(34, 0, 17, 1), + MTK_EINT_PIN(35, 0, 18, 1), + MTK_EINT_PIN(36, 0, 19, 0), + MTK_EINT_PIN(37, 0, 20, 0), + MTK_EINT_PIN(38, 0, 21, 0), + MTK_EINT_PIN(39, 0, 22, 0), + MTK_EINT_PIN(40, 0, 23, 0), + MTK_EINT_PIN(41, 1, 7, 0), + MTK_EINT_PIN(42, 1, 8, 0), + MTK_EINT_PIN(43, 1, 9, 0), + MTK_EINT_PIN(44, 1, 10, 0), + MTK_EINT_PIN(45, 1, 11, 0), + MTK_EINT_PIN(46, 1, 12, 0), + MTK_EINT_PIN(47, 1, 13, 0), + MTK_EINT_PIN(48, 0, 24, 0), + MTK_EINT_PIN(49, 0, 25, 0), + MTK_EINT_PIN(50, 0, 26, 0), + MTK_EINT_PIN(51, 0, 27, 0), + MTK_EINT_PIN(52, 0, 28, 0), + MTK_EINT_PIN(53, 0, 29, 0), + MTK_EINT_PIN(54, 0, 30, 0), + MTK_EINT_PIN(55, 0, 31, 0), + MTK_EINT_PIN(56, 0, 32, 0), + MTK_EINT_PIN(57, 0, 33, 0), + MTK_EINT_PIN(58, 0, 34, 0), + MTK_EINT_PIN(59, 0, 35, 0), + MTK_EINT_PIN(60, 0, 36, 0), + MTK_EINT_PIN(61, 0, 37, 0), + MTK_EINT_PIN(62, 0, 38, 0), + MTK_EINT_PIN(63, 0, 39, 0), + MTK_EINT_PIN(64, 0, 40, 0), + MTK_EINT_PIN(65, 0, 41, 0), + MTK_EINT_PIN(66, 0, 42, 0), + MTK_EINT_PIN(67, 0, 43, 0), + MTK_EINT_PIN(68, 0, 44, 0), + MTK_EINT_PIN(69, 0, 45, 0), + MTK_EINT_PIN(70, 0, 46, 0), + MTK_EINT_PIN(71, 0, 47, 0), + MTK_EINT_PIN(72, 0, 48, 0), + MTK_EINT_PIN(73, 0, 49, 0), + MTK_EINT_PIN(74, 0, 50, 0), + MTK_EINT_PIN(75, 0, 51, 0), + MTK_EINT_PIN(76, 0, 52, 0), + MTK_EINT_PIN(77, 1, 14, 0), + MTK_EINT_PIN(78, 1, 15, 0), + MTK_EINT_PIN(79, 1, 16, 0), + MTK_EINT_PIN(80, 1, 17, 0), + MTK_EINT_PIN(81, 1, 18, 0), + MTK_EINT_PIN(82, 1, 19, 0), + MTK_EINT_PIN(83, 1, 20, 0), + MTK_EINT_PIN(84, 1, 21, 0), + MTK_EINT_PIN(85, 1, 22, 0), + MTK_EINT_PIN(86, 1, 23, 0), + MTK_EINT_PIN(87, 1, 24, 0), + MTK_EINT_PIN(88, 1, 25, 0), + MTK_EINT_PIN(89, 1, 26, 0), + MTK_EINT_PIN(90, 1, 27, 0), + MTK_EINT_PIN(91, 1, 28, 0), + MTK_EINT_PIN(92, 0, 53, 0), + MTK_EINT_PIN(93, 0, 54, 0), + MTK_EINT_PIN(94, 0, 55, 0), + MTK_EINT_PIN(95, 0, 56, 0), + MTK_EINT_PIN(96, 0, 57, 0), + MTK_EINT_PIN(97, 2, 10, 0), + MTK_EINT_PIN(98, 2, 11, 0), + MTK_EINT_PIN(99, 1, 29, 0), + MTK_EINT_PIN(100, 1, 30, 0), + MTK_EINT_PIN(101, 1, 31, 0), + MTK_EINT_PIN(102, 1, 32, 0), + MTK_EINT_PIN(103, 1, 33, 0), + MTK_EINT_PIN(104, 1, 34, 0), + MTK_EINT_PIN(105, 1, 35, 0), + MTK_EINT_PIN(106, 1, 36, 0), + MTK_EINT_PIN(107, 1, 37, 0), + MTK_EINT_PIN(108, 1, 38, 0), + MTK_EINT_PIN(109, 1, 39, 0), + MTK_EINT_PIN(110, 1, 40, 0), + MTK_EINT_PIN(111, 1, 41, 0), + MTK_EINT_PIN(112, 1, 42, 0), + MTK_EINT_PIN(113, 1, 43, 0), + MTK_EINT_PIN(114, 1, 44, 0), + MTK_EINT_PIN(115, 1, 45, 0), + MTK_EINT_PIN(116, 1, 46, 0), + MTK_EINT_PIN(196, 3, 0, 0), + MTK_EINT_PIN(197, 3, 1, 0), + MTK_EINT_PIN(198, 3, 2, 0), + MTK_EINT_PIN(199, 3, 3, 0), + MTK_EINT_PIN(200, 3, 4, 0), + MTK_EINT_PIN(201, 3, 5, 0), + MTK_EINT_PIN(202, 3, 6, 0), + MTK_EINT_PIN(203, 3, 7, 0), + MTK_EINT_PIN(204, 3, 8, 0), + MTK_EINT_PIN(205, 3, 9, 0), + MTK_EINT_PIN(206, 3, 10, 0), + MTK_EINT_PIN(207, 3, 11, 0), + MTK_EINT_PIN(208, 3, 12, 0), + MTK_EINT_PIN(209, 3, 13, 0), + MTK_EINT_PIN(210, 3, 14, 0), + MTK_EINT_PIN(211, 3, 15, 0), + MTK_EINT_PIN(212, 3, 16, 0), + MTK_EINT_PIN(213, 3, 17, 0), + MTK_EINT_PIN(214, 3, 18, 0), + MTK_EINT_PIN(215, 3, 19, 0), +}; + +#endif /* __PINCTRL_MTK_MT6878_H */ From a7b4825cb1346bf404fdb10cb00caf45a9900683 Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Fri, 12 Sep 2025 10:40:41 -0500 Subject: [PATCH 009/107] dt-bindings: pinctrl: pinctrl-single: add ti,am62l-padconf compatible Add the "ti,am62l-padconf" compatible to allow for some changes in the driver in the future when needed. Signed-off-by: Bryan Brattlof Acked-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml index f83dbf32ad18..9135788cf62e 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml @@ -24,6 +24,7 @@ properties: - items: - enum: - ti,am437-padconf + - ti,am62l-padconf - ti,am654-padconf - ti,dra7-padconf - ti,omap2420-padconf From 543e3b4a54d779446d0e7aaf4adee1b7d59292fe Mon Sep 17 00:00:00 2001 From: Antony Kurniawan Soemardi Date: Sun, 14 Sep 2025 18:34:59 +0000 Subject: [PATCH 010/107] dt-bindings: pinctrl: qcom: msm8960: rename msmgpio node to tlmm Rename the GPIO controller node from "msmgpio" to "tlmm" to match the convention used by other Qualcomm SoCs. Suggested-by: Shinjo Park Signed-off-by: Antony Kurniawan Soemardi Reviewed-by: Bjorn Andersson Acked-by: Rob Herring (Arm) Reviewed-by: Dmitry Baryshkov Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.yaml index 46618740bd31..03a369277014 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.yaml @@ -107,12 +107,12 @@ examples: - | #include - msmgpio: pinctrl@800000 { + tlmm: pinctrl@800000 { compatible = "qcom,msm8960-pinctrl"; reg = <0x800000 0x4000>; #gpio-cells = <2>; gpio-controller; - gpio-ranges = <&msmgpio 0 0 152>; + gpio-ranges = <&tlmm 0 0 152>; interrupts = ; interrupt-controller; #interrupt-cells = <2>; From 37e7b536061a33c8f27030e3ffc5a717a6c319e3 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 19 Sep 2025 15:17:11 +0300 Subject: [PATCH 011/107] pinctrl: qcom: glymur: Drop unnecessary platform data from match table The platform specific configuration is already passed on to the generic msm probe. So it's useless to exist in the match table next to the compatible. So drop it from match table. Fixes: 87ebcd8baebf ("pinctrl: qcom: Add glymur pinctrl driver") Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-glymur.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/qcom/pinctrl-glymur.c b/drivers/pinctrl/qcom/pinctrl-glymur.c index 9913f98e9531..9781e7fcb3a1 100644 --- a/drivers/pinctrl/qcom/pinctrl-glymur.c +++ b/drivers/pinctrl/qcom/pinctrl-glymur.c @@ -1743,7 +1743,7 @@ static const struct msm_pinctrl_soc_data glymur_tlmm = { }; static const struct of_device_id glymur_tlmm_of_match[] = { - { .compatible = "qcom,glymur-tlmm", .data = &glymur_tlmm }, + { .compatible = "qcom,glymur-tlmm", }, { } }; From e73fda2dcb0bad6650e654556c5242b773707257 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 19 Sep 2025 15:17:12 +0300 Subject: [PATCH 012/107] pinctrl: qcom: glymur: Fix the gpio and egpio pin functions Mark the gpio/egpio as GPIO specific pin functions, othewise the pin muxing generic framework will complain about the gpio being already requested by a different owner. Fixes: 87ebcd8baebf ("pinctrl: qcom: Add glymur pinctrl driver") Signed-off-by: Abel Vesa Reviewed-by: Bartosz Golaszewski Reviewed-by: Dmitry Baryshkov Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-glymur.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-glymur.c b/drivers/pinctrl/qcom/pinctrl-glymur.c index 9781e7fcb3a1..335005084b6b 100644 --- a/drivers/pinctrl/qcom/pinctrl-glymur.c +++ b/drivers/pinctrl/qcom/pinctrl-glymur.c @@ -1316,7 +1316,7 @@ static const char *const wcn_sw_ctrl_groups[] = { }; static const struct pinfunction glymur_functions[] = { - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(resout_gpio_n), MSM_PIN_FUNCTION(aoss_cti), MSM_PIN_FUNCTION(asc_cci), @@ -1342,7 +1342,7 @@ static const struct pinfunction glymur_functions[] = { MSM_PIN_FUNCTION(edp0_hot), MSM_PIN_FUNCTION(edp0_lcd), MSM_PIN_FUNCTION(edp1_lcd), - MSM_PIN_FUNCTION(egpio), + MSM_GPIO_PIN_FUNCTION(egpio), MSM_PIN_FUNCTION(eusb_ac_en), MSM_PIN_FUNCTION(gcc_gp1), MSM_PIN_FUNCTION(gcc_gp2), From 5f345e61a50d33eaba88e89d7867826aafb8b114 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Wed, 24 Sep 2025 22:31:02 +0530 Subject: [PATCH 013/107] dt-bindings: pinctrl: qcom,pmic-gpio: Add GPIO bindings for Glymur PMICs Update the Qualcomm Technologies, Inc. PMIC GPIO binding documentation to include compatible strings for PMK8850, PMH0101, PMH0104, PMH0110 and PMCX0102 PMICs. Signed-off-by: Anjelique Melendez Signed-off-by: Jishnu Prakash Signed-off-by: Pankaj Patil Signed-off-by: Kamal Wadhwa Reviewed-by: Bartosz Golaszewski Acked-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,pmic-gpio.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml index 5e6dfcc3fe9b..8ae4489637f3 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml @@ -59,7 +59,11 @@ properties: - qcom,pmc8180-gpio - qcom,pmc8180c-gpio - qcom,pmc8380-gpio + - qcom,pmcx0102-gpio - qcom,pmd8028-gpio + - qcom,pmh0101-gpio + - qcom,pmh0104-gpio + - qcom,pmh0110-gpio - qcom,pmi632-gpio - qcom,pmi8950-gpio - qcom,pmi8994-gpio @@ -68,6 +72,7 @@ properties: - qcom,pmiv0104-gpio - qcom,pmk8350-gpio - qcom,pmk8550-gpio + - qcom,pmk8850-gpio - qcom,pmm8155au-gpio - qcom,pmm8654au-gpio - qcom,pmp8074-gpio @@ -191,6 +196,8 @@ allOf: - qcom,pm8950-gpio - qcom,pm8953-gpio - qcom,pmi632-gpio + - qcom,pmh0104-gpio + - qcom,pmk8850-gpio then: properties: gpio-line-names: @@ -303,6 +310,8 @@ allOf: compatible: contains: enum: + - qcom,pmcx0102-gpio + - qcom,pmh0110-gpio - qcom,pmi8998-gpio then: properties: @@ -318,6 +327,7 @@ allOf: compatible: contains: enum: + - qcom,pmh0101-gpio - qcom,pmih0108-gpio then: properties: @@ -481,13 +491,18 @@ $defs: - gpio1-gpio22 for pm8994 - gpio1-gpio26 for pm8998 - gpio1-gpio22 for pma8084 + - gpio1-gpio14 for pmcx0102 - gpio1-gpio4 for pmd8028 + - gpio1-gpio18 for pmh0101 + - gpio1-gpio8 for pmh0104 + - gpio1-gpio14 for pmh0110 - gpio1-gpio8 for pmi632 - gpio1-gpio2 for pmi8950 - gpio1-gpio10 for pmi8994 - gpio1-gpio18 for pmih0108 - gpio1-gpio4 for pmk8350 - gpio1-gpio6 for pmk8550 + - gpio1-gpio8 for pmk8850 - gpio1-gpio10 for pmm8155au - gpio1-gpio12 for pmm8654au - gpio1-gpio12 for pmp8074 (holes on gpio1 and gpio12) From 120b6d1a22ee46dcf35e21949ddce6fe736550f0 Mon Sep 17 00:00:00 2001 From: Anjelique Melendez Date: Wed, 24 Sep 2025 22:31:03 +0530 Subject: [PATCH 014/107] pinctrl: qcom: spmi-gpio: Add PMCX0102, PMK8850 & PMH01XX PMICs support Add support for PMCX0102, PMH0101, PMH0104, PMH0110 and PMK8850 PMIC GPIOs with adding appropriate compatible strings. Signed-off-by: Anjelique Melendez Signed-off-by: Jishnu Prakash Signed-off-by: Kamal Wadhwa Reviewed-by: Dmitry Baryshkov Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index 485b68cc93f8..c4f7d2d7a017 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -1239,7 +1239,11 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pm8998-gpio", .data = (void *) 26 }, { .compatible = "qcom,pma8084-gpio", .data = (void *) 22 }, { .compatible = "qcom,pmc8380-gpio", .data = (void *) 10 }, + { .compatible = "qcom,pmcx0102-gpio", .data = (void *)14 }, { .compatible = "qcom,pmd8028-gpio", .data = (void *) 4 }, + { .compatible = "qcom,pmh0101-gpio", .data = (void *)18 }, + { .compatible = "qcom,pmh0104-gpio", .data = (void *)8 }, + { .compatible = "qcom,pmh0110-gpio", .data = (void *)14 }, { .compatible = "qcom,pmi632-gpio", .data = (void *) 8 }, { .compatible = "qcom,pmi8950-gpio", .data = (void *) 2 }, { .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 }, @@ -1248,6 +1252,7 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pmiv0104-gpio", .data = (void *) 10 }, { .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 }, { .compatible = "qcom,pmk8550-gpio", .data = (void *) 6 }, + { .compatible = "qcom,pmk8850-gpio", .data = (void *)8 }, { .compatible = "qcom,pmm8155au-gpio", .data = (void *) 10 }, { .compatible = "qcom,pmm8654au-gpio", .data = (void *) 12 }, /* pmp8074 has 12 GPIOs with holes on 1 and 12 */ From bfdccbe92e6de5a4b468343cbca3143b89df99af Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Wed, 24 Sep 2025 22:31:04 +0530 Subject: [PATCH 015/107] pinctrl: qcom: spmi-gpio: add support for {LV_VIN2, MV_VIN3}_CLK subtypes Add support for SPMI PMIC GPIO subtypes GPIO_LV_VIN2_CLK and GPIO_MV_VIN3_CLK. Signed-off-by: Subbaraman Narayanamurthy Signed-off-by: Jishnu Prakash Signed-off-by: Kamal Wadhwa Reviewed-by: Dmitry Baryshkov Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index c4f7d2d7a017..83f940fe30b2 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -42,6 +42,8 @@ #define PMIC_GPIO_SUBTYPE_GPIO_MV 0x11 #define PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2 0x12 #define PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3 0x13 +#define PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2_CLK 0x14 +#define PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3_CLK 0x15 #define PMIC_MPP_REG_RT_STS 0x10 #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1 @@ -852,11 +854,13 @@ static int pmic_gpio_populate(struct pmic_gpio_state *state, pad->lv_mv_type = true; break; case PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2: + case PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2_CLK: pad->num_sources = 2; pad->have_buffer = true; pad->lv_mv_type = true; break; case PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3: + case PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3_CLK: pad->num_sources = 3; pad->have_buffer = true; pad->lv_mv_type = true; From d51093cf011cab7235f64beb92a344806db393a6 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Wed, 24 Sep 2025 17:31:59 -0500 Subject: [PATCH 016/107] dt-bindings: pinctrl: Convert Marvell Berlin pinctrl to DT schema Convert the Marvell/Synaptics Berlin pinctrl binding to DT schema format. The "reg" property was not documented for the newer SoCs. Otherwise, it's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- .../bindings/pinctrl/berlin,pinctrl.txt | 47 ---------- .../pinctrl/marvell,berlin2-soc-pinctrl.yaml | 86 +++++++++++++++++++ 2 files changed, 86 insertions(+), 47 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/berlin,pinctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,berlin2-soc-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/berlin,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/berlin,pinctrl.txt deleted file mode 100644 index 0a2d5516e1f3..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/berlin,pinctrl.txt +++ /dev/null @@ -1,47 +0,0 @@ -* Pin-controller driver for the Marvell Berlin SoCs - -Pin control registers are part of both chip controller and system -controller register sets. Pin controller nodes should be a sub-node of -either the chip controller or system controller node. The pins -controlled are organized in groups, so no actual pin information is -needed. - -A pin-controller node should contain subnodes representing the pin group -configurations, one per function. Each subnode has the group name and -the muxing function used. - -Be aware the Marvell Berlin datasheets use the keyword 'mode' for what -is called a 'function' in the pin-controller subsystem. - -Required properties: -- compatible: should be one of: - "marvell,berlin2-soc-pinctrl", - "marvell,berlin2-system-pinctrl", - "marvell,berlin2cd-soc-pinctrl", - "marvell,berlin2cd-system-pinctrl", - "marvell,berlin2q-soc-pinctrl", - "marvell,berlin2q-system-pinctrl", - "marvell,berlin4ct-avio-pinctrl", - "marvell,berlin4ct-soc-pinctrl", - "marvell,berlin4ct-system-pinctrl", - "syna,as370-soc-pinctrl" - -Required subnode-properties: -- groups: a list of strings describing the group names. -- function: a string describing the function used to mux the groups. - -Example: - -sys_pinctrl: pin-controller { - compatible = "marvell,berlin2q-system-pinctrl"; - - uart0_pmux: uart0-pmux { - groups = "GSM12"; - function = "uart0"; - }; -}; - -&uart0 { - pinctrl-0 = <&uart0_pmux>; - pinctrl-names = "default"; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,berlin2-soc-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/marvell,berlin2-soc-pinctrl.yaml new file mode 100644 index 000000000000..6ace3bf5433b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/marvell,berlin2-soc-pinctrl.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/marvell,berlin2-soc-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Berlin pin-controller driver + +maintainers: + - Antoine Tenart + - Jisheng Zhang + +description: > + Pin control registers are part of both chip controller and system controller + register sets. Pin controller nodes should be a sub-node of either the chip + controller or system controller node. The pins controlled are organized in + groups, so no actual pin information is needed. + + A pin-controller node should contain subnodes representing the pin group + configurations, one per function. Each subnode has the group name and the + muxing function used. + + Be aware the Marvell Berlin datasheets use the keyword 'mode' for what is + called a 'function' in the pin-controller subsystem. + +properties: + compatible: + items: + - enum: + - marvell,berlin2-soc-pinctrl + - marvell,berlin2-system-pinctrl + - marvell,berlin2cd-soc-pinctrl + - marvell,berlin2cd-system-pinctrl + - marvell,berlin2q-soc-pinctrl + - marvell,berlin2q-system-pinctrl + - marvell,berlin4ct-avio-pinctrl + - marvell,berlin4ct-soc-pinctrl + - marvell,berlin4ct-system-pinctrl + - syna,as370-soc-pinctrl + + reg: + maxItems: 1 + +additionalProperties: + description: Pin group configuration subnodes. + type: object + $ref: /schemas/pinctrl/pinmux-node.yaml# + additionalProperties: false + + properties: + groups: + description: List of pin group names. + $ref: /schemas/types.yaml#/definitions/string-array + + function: + description: Function used to mux the group. + $ref: /schemas/types.yaml#/definitions/string + + required: + - groups + - function + +allOf: + - if: + properties: + compatible: + contains: + enum: + - marvell,berlin4ct-avio-pinctrl + - marvell,berlin4ct-soc-pinctrl + - marvell,berlin4ct-system-pinctrl + - syna,as370-soc-pinctrl + then: + required: + - reg + +examples: + - | + pinctrl { + compatible = "marvell,berlin2q-system-pinctrl"; + + uart0-pmux { + groups = "GSM12"; + function = "uart0"; + }; + }; From c1c9641a04e839604612eac99c827f8f3e0c4f06 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 25 Sep 2025 17:18:50 -0500 Subject: [PATCH 017/107] dt-bindings: pinctrl: Convert marvell,armada-3710-(sb|nb)-pinctrl to DT schema Convert the marvell,armada3710-(sb|nb)-pinctrl binding to DT schema format. The binding includes the "marvell,armada-3700-xtal-clock" subnode which is simple enough to include here. Mark interrupt-controller/#interrupt-cells as required as the users have them and the h/w is either capable of interrupts or not. As this syscon has 2 register ranges, syscon-common.yaml needs to be updated to drop the restriction of 1 register entry. Signed-off-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- .../bindings/clock/armada3700-xtal-clock.txt | 29 --- .../bindings/mfd/syscon-common.yaml | 3 - .../pinctrl/marvell,armada-37xx-pinctrl.txt | 195 ------------------ .../marvell,armada3710-xb-pinctrl.yaml | 124 +++++++++++ 4 files changed, 124 insertions(+), 227 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt delete mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada3710-xb-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt b/Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt deleted file mode 100644 index 4c0807f28cfa..000000000000 --- a/Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt +++ /dev/null @@ -1,29 +0,0 @@ -* Xtal Clock bindings for Marvell Armada 37xx SoCs - -Marvell Armada 37xx SoCs allow to determine the xtal clock frequencies by -reading the gpio latch register. - -This node must be a subnode of the node exposing the register address -of the GPIO block where the gpio latch is located. -See Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt - -Required properties: -- compatible : shall be one of the following: - "marvell,armada-3700-xtal-clock" -- #clock-cells : from common clock binding; shall be set to 0 - -Optional properties: -- clock-output-names : from common clock binding; allows overwrite default clock - output names ("xtal") - -Example: -pinctrl_nb: pinctrl-nb@13800 { - compatible = "armada3710-nb-pinctrl", "syscon", "simple-mfd"; - reg = <0x13800 0x100>, <0x13C00 0x20>; - - xtalclk: xtal-clk { - compatible = "marvell,armada-3700-xtal-clock"; - clock-output-names = "xtal"; - #clock-cells = <0>; - }; -}; diff --git a/Documentation/devicetree/bindings/mfd/syscon-common.yaml b/Documentation/devicetree/bindings/mfd/syscon-common.yaml index 451cbad467a3..14a08e7bc8bd 100644 --- a/Documentation/devicetree/bindings/mfd/syscon-common.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon-common.yaml @@ -35,9 +35,6 @@ properties: minItems: 2 maxItems: 5 # Should be enough - reg: - maxItems: 1 - reg-io-width: description: The size (in bytes) of the IO accesses that should be performed diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt deleted file mode 100644 index ecec514b3155..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt +++ /dev/null @@ -1,195 +0,0 @@ -* Marvell Armada 37xx SoC pin and gpio controller - -Each Armada 37xx SoC come with two pin and gpio controller one for the -south bridge and the other for the north bridge. - -Inside this set of register the gpio latch allows exposing some -configuration of the SoC and especially the clock frequency of the -xtal. Hence, this node is a represent as syscon allowing sharing the -register between multiple hardware block. - -GPIO and pin controller: ------------------------- - -Main node: - -Refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning -of the phrase "pin configuration node". - -Required properties for pinctrl driver: - -- compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd" - for the south bridge - "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd" - for the north bridge -- reg: The first set of register are for pinctrl/gpio and the second - set for the interrupt controller -- interrupts: list of the interrupt use by the gpio - -Available groups and functions for the North bridge: - -group: jtag - - pins 20-24 - - functions jtag, gpio - -group sdio0 - - pins 8-10 - - functions sdio, gpio - -group emmc_nb - - pins 27-35 - - functions emmc, gpio - -group pwm0 - - pin 11 (GPIO1-11) - - functions pwm, led, gpio - -group pwm1 - - pin 12 - - functions pwm, led, gpio - -group pwm2 - - pin 13 - - functions pwm, led, gpio - -group pwm3 - - pin 14 - - functions pwm, led, gpio - -group pmic1 - - pin 7 - - functions pmic, gpio - -group pmic0 - - pin 6 - - functions pmic, gpio - -group i2c2 - - pins 2-3 - - functions i2c, gpio - -group i2c1 - - pins 0-1 - - functions i2c, gpio - -group spi_cs1 - - pin 17 - - functions spi, gpio - -group spi_cs2 - - pin 18 - - functions spi, gpio - -group spi_cs3 - - pin 19 - - functions spi, gpio - -group onewire - - pin 4 - - functions onewire, gpio - -group uart1 - - pins 25-26 - - functions uart, gpio - -group spi_quad - - pins 15-16 - - functions spi, gpio - -group uart2 - - pins 9-10 and 18-19 - - functions uart, gpio - -Available groups and functions for the South bridge: - -group usb32_drvvbus0 - - pin 36 - - functions drvbus, gpio - -group usb2_drvvbus1 - - pin 37 - - functions drvbus, gpio - -group sdio_sb - - pins 60-65 - - functions sdio, gpio - -group rgmii - - pins 42-53 - - functions mii, gpio - -group pcie1 - - pins 39 - - functions pcie, gpio - -group pcie1_clkreq - - pins 40 - - functions pcie, gpio - -group pcie1_wakeup - - pins 41 - - functions pcie, gpio - -group smi - - pins 54-55 - - functions smi, gpio - -group ptp - - pins 56 - - functions ptp, gpio - -group ptp_clk - - pin 57 - - functions ptp, mii - -group ptp_trig - - pin 58 - - functions ptp, mii - -group mii_col - - pin 59 - - functions mii, mii_err - -GPIO subnode: - -Please refer to gpio.txt in this directory for details of gpio-ranges property -and the common GPIO bindings used by client devices. - -Required properties for gpio driver under the gpio subnode: -- interrupts: List of interrupt specifier for the controllers interrupt. -- gpio-controller: Marks the device node as a gpio controller. -- #gpio-cells: Should be 2. The first cell is the GPIO number and the - second cell specifies GPIO flags, as defined in - . Only the GPIO_ACTIVE_HIGH and - GPIO_ACTIVE_LOW flags are supported. -- gpio-ranges: Range of pins managed by the GPIO controller. - -Xtal Clock bindings for Marvell Armada 37xx SoCs ------------------------------------------------- - -see Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt - - -Example: -pinctrl_sb: pinctrl-sb@18800 { - compatible = "marvell,armada3710-sb-pinctrl", "syscon", "simple-mfd"; - reg = <0x18800 0x100>, <0x18C00 0x20>; - gpio { - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_sb 0 0 29>; - gpio-controller; - interrupts = - , - , - , - , - ; - }; - - rgmii_pins: mii-pins { - groups = "rgmii"; - function = "mii"; - }; - -}; diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada3710-xb-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/marvell,armada3710-xb-pinctrl.yaml new file mode 100644 index 000000000000..51bad2e8d6f1 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada3710-xb-pinctrl.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/marvell,armada3710-xb-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 37xx SoC pin and gpio controller + +maintainers: + - Gregory CLEMENT + - Marek Behún + - Miquel Raynal + +description: > + Each Armada 37xx SoC come with two pin and gpio controller one for the south + bridge and the other for the north bridge. + + Inside this set of register the gpio latch allows exposing some configuration + of the SoC and especially the clock frequency of the xtal. Hence, this node is + a represent as syscon allowing sharing the register between multiple hardware + block. + +properties: + compatible: + items: + - enum: + - marvell,armada3710-sb-pinctrl + - marvell,armada3710-nb-pinctrl + - const: syscon + - const: simple-mfd + + reg: + items: + - description: pinctrl and GPIO controller registers + - description: interrupt controller registers + + gpio: + description: GPIO controller subnode + type: object + additionalProperties: false + + properties: + '#gpio-cells': + const: 2 + + gpio-controller: true + + gpio-ranges: + description: Range of pins managed by the GPIO controller + + '#interrupt-cells': + const: 2 + + interrupt-controller: true + + interrupts: + description: List of interrupt specifiers for the GPIO controller + + required: + - '#gpio-cells' + - gpio-ranges + - gpio-controller + - '#interrupt-cells' + - interrupt-controller + - interrupts + + xtal-clk: + type: object + additionalProperties: false + + properties: + compatible: + const: marvell,armada-3700-xtal-clock + + '#clock-cells': + const: 0 + + clock-output-names: true + +patternProperties: + '-pins$': + $ref: pinmux-node.yaml# + additionalProperties: false + + properties: + groups: + enum: [ emmc_nb, i2c1, i2c2, jtag, mii_col, onewire, pcie1, + pcie1_clkreq, pcie1_wakeup, pmic0, pmic1, ptp, ptp_clk, + ptp_trig, pwm0, pwm1, pwm2, pwm3, rgmii, sdio0, sdio_sb, smi, + spi_cs1, spi_cs2, spi_cs3, spi_quad, uart1, uart2, + usb2_drvvbus1, usb32_drvvbus ] + + function: + enum: [ drvbus, emmc, gpio, i2c, jtag, led, mii, mii_err, onewire, + pcie, pmic, ptp, pwm, sdio, smi, spi, uart ] + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + pinctrl_sb: pinctrl@18800 { + compatible = "marvell,armada3710-sb-pinctrl", "syscon", "simple-mfd"; + reg = <0x18800 0x100>, <0x18C00 0x20>; + + gpio { + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_sb 0 0 29>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts = + , + , + , + , + ; + }; + }; From e7db6f1528fd036cfade3222dac979dfbc24ddfb Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Wed, 24 Sep 2025 16:16:03 -0700 Subject: [PATCH 018/107] dt-bindings: pinctrl: describe Kaanapali TLMM The Top Level Mode Multiplexer (TLMM) in the Kaanapali SoC provide GPIO and pinctrl functionality for UFS, SDC and 217 GPIO pins. Add a DeviceTree binding to describe the Kaanapali TLMM block. Signed-off-by: Jingyi Wang Reviewed-by: Krzysztof Kozlowski Reviewed-by: Bjorn Andersson Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,kaanapali-tlmm.yaml | 127 ++++++++++++++++++ 1 file changed, 127 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,kaanapali-tlmm.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,kaanapali-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,kaanapali-tlmm.yaml new file mode 100644 index 000000000000..53534a07a1f0 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,kaanapali-tlmm.yaml @@ -0,0 +1,127 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,kaanapali-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Kaanapali TLMM block + +maintainers: + - Jingyi Wang + +description: + Top Level Mode Multiplexer pin controller in Qualcomm Kaanapali SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,kaanapali-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 109 + + gpio-line-names: + maxItems: 217 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-kaanapali-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-kaanapali-tlmm-state" + additionalProperties: false + +$defs: + qcom-kaanapali-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-6])$" + - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk0, + audio_ext_mclk1, audio_ref_clk, cam_asc_mclk2, cam_asc_mclk4, + cam_mclk, cci_async_in, cci_i2c_scl, cci_i2c_sda, cci_timer, + cmu_rng, coex_uart1_rx, coex_uart1_tx, coex_uart2_rx, + coex_uart2_tx, dbg_out_clk, ddr_bist_complete, ddr_bist_fail, + ddr_bist_start, ddr_bist_stop, ddr_pxi0, ddr_pxi1, ddr_pxi2, + ddr_pxi3, dp_hot, egpio, gcc_gp1, gcc_gp2, gcc_gp3, gnss_adc0, + gnss_adc1, i2chub0_se0, i2chub0_se1, i2chub0_se2, i2chub0_se3, + i2chub0_se4, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws, + i2s1_data0, i2s1_data1, i2s1_sck, i2s1_ws, ibi_i3c, jitter_bist, + mdp_esync0_out, mdp_esync1_out, mdp_vsync, mdp_vsync0_out, + mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out, + mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, nav_gpio3, + pcie0_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux, + prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti, + qdss_gpio_traceclk, qdss_gpio_tracectl, qdss_gpio_tracedata, + qlink_big_enable, qlink_big_request, qlink_little_enable, + qlink_little_request, qlink_wmss, qspi0, qspi1, qspi2, qspi3, + qspi_clk, qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se3, + qup1_se4, qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1, + qup2_se2, qup2_se3, qup2_se4, qup3_se0, qup3_se1, qup3_se2, + qup3_se3, qup3_se4, qup3_se5, qup4_se0, qup4_se1, qup4_se2, + qup4_se3, qup4_se4, sd_write_protect, sdc40, sdc41, sdc42, sdc43, + sdc4_clk, sdc4_cmd, sys_throttle, tb_trig_sdc2, tb_trig_sdc4, + tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3, tsense_pwm1, + tsense_pwm2, tsense_pwm3, tsense_pwm4, tsense_pwm5, tsense_pwm6, + tsense_pwm7, uim0_clk, uim0_data, uim0_present, uim0_reset, uim1_clk, + uim1_data, uim1_present, uim1_reset, usb0_hs, usb_phy, vfr_0, vfr_1, + vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + tlmm: pinctrl@f100000 { + compatible = "qcom,kaanapali-tlmm"; + reg = <0x0f100000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 218>; + interrupt-controller; + #interrupt-cells = <2>; + + qup-uart7-state { + pins = "gpio62", "gpio63"; + function = "qup1_se7"; + }; + }; +... From 35ff9c6b318af715f54dc2053b328ca7bfb2c00f Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Wed, 24 Sep 2025 16:16:04 -0700 Subject: [PATCH 019/107] pinctrl: qcom: add the tlmm driver for Kaanapali platforms Add support for Kaanapali TLMM configuration and control via the pinctrl framework. Signed-off-by: Jingyi Wang Reviewed-by: Bartosz Golaszewski Reviewed-by: Bjorn Andersson Reviewed-by: Konrad Dybcio Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/Kconfig.msm | 8 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-kaanapali.c | 1803 ++++++++++++++++++++++ 3 files changed, 1812 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-kaanapali.c diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfig.msm index 69a5b47adedc..3e9e02774001 100644 --- a/drivers/pinctrl/qcom/Kconfig.msm +++ b/drivers/pinctrl/qcom/Kconfig.msm @@ -92,6 +92,14 @@ config PINCTRL_IPQ9574 Qualcomm Technologies Inc. IPQ9574 platform. Select this for IPQ9574. +config PINCTRL_KAANAPALI + tristate "Qualcomm Technologies Inc Kaanapali pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc Kaanapali platform. + config PINCTRL_MSM8226 tristate "Qualcomm 8226 pin controller driver" depends on ARM || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 567d3051e760..748b17a77b2c 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_IPQ5424) += pinctrl-ipq5424.o obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o obj-$(CONFIG_PINCTRL_IPQ6018) += pinctrl-ipq6018.o obj-$(CONFIG_PINCTRL_IPQ9574) += pinctrl-ipq9574.o +obj-$(CONFIG_PINCTRL_KAANAPALI) += pinctrl-kaanapali.o obj-$(CONFIG_PINCTRL_MSM8226) += pinctrl-msm8226.o obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o diff --git a/drivers/pinctrl/qcom/pinctrl-kaanapali.c b/drivers/pinctrl/qcom/pinctrl-kaanapali.c new file mode 100644 index 000000000000..364e6d997337 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-kaanapali.c @@ -0,0 +1,1803 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + msm_mux_##f10, \ + msm_mux_##f11 /* egpio mode */ \ + }, \ + .nfuncs = 12, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_wakeup_present_bit = 6, \ + .intr_wakeup_enable_bit = 7, \ + .intr_target_bit = 8, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, ctl, io) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = io, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc kaanapali_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + PINCTRL_PIN(173, "GPIO_173"), + PINCTRL_PIN(174, "GPIO_174"), + PINCTRL_PIN(175, "GPIO_175"), + PINCTRL_PIN(176, "GPIO_176"), + PINCTRL_PIN(177, "GPIO_177"), + PINCTRL_PIN(178, "GPIO_178"), + PINCTRL_PIN(179, "GPIO_179"), + PINCTRL_PIN(180, "GPIO_180"), + PINCTRL_PIN(181, "GPIO_181"), + PINCTRL_PIN(182, "GPIO_182"), + PINCTRL_PIN(183, "GPIO_183"), + PINCTRL_PIN(184, "GPIO_184"), + PINCTRL_PIN(185, "GPIO_185"), + PINCTRL_PIN(186, "GPIO_186"), + PINCTRL_PIN(187, "GPIO_187"), + PINCTRL_PIN(188, "GPIO_188"), + PINCTRL_PIN(189, "GPIO_189"), + PINCTRL_PIN(190, "GPIO_190"), + PINCTRL_PIN(191, "GPIO_191"), + PINCTRL_PIN(192, "GPIO_192"), + PINCTRL_PIN(193, "GPIO_193"), + PINCTRL_PIN(194, "GPIO_194"), + PINCTRL_PIN(195, "GPIO_195"), + PINCTRL_PIN(196, "GPIO_196"), + PINCTRL_PIN(197, "GPIO_197"), + PINCTRL_PIN(198, "GPIO_198"), + PINCTRL_PIN(199, "GPIO_199"), + PINCTRL_PIN(200, "GPIO_200"), + PINCTRL_PIN(201, "GPIO_201"), + PINCTRL_PIN(202, "GPIO_202"), + PINCTRL_PIN(203, "GPIO_203"), + PINCTRL_PIN(204, "GPIO_204"), + PINCTRL_PIN(205, "GPIO_205"), + PINCTRL_PIN(206, "GPIO_206"), + PINCTRL_PIN(207, "GPIO_207"), + PINCTRL_PIN(208, "GPIO_208"), + PINCTRL_PIN(209, "GPIO_209"), + PINCTRL_PIN(210, "GPIO_210"), + PINCTRL_PIN(211, "GPIO_211"), + PINCTRL_PIN(212, "GPIO_212"), + PINCTRL_PIN(213, "GPIO_213"), + PINCTRL_PIN(214, "GPIO_214"), + PINCTRL_PIN(215, "GPIO_215"), + PINCTRL_PIN(216, "GPIO_216"), + PINCTRL_PIN(217, "UFS_RESET"), + PINCTRL_PIN(218, "SDC2_CLK"), + PINCTRL_PIN(219, "SDC2_CMD"), + PINCTRL_PIN(220, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); +DECLARE_MSM_GPIO_PINS(166); +DECLARE_MSM_GPIO_PINS(167); +DECLARE_MSM_GPIO_PINS(168); +DECLARE_MSM_GPIO_PINS(169); +DECLARE_MSM_GPIO_PINS(170); +DECLARE_MSM_GPIO_PINS(171); +DECLARE_MSM_GPIO_PINS(172); +DECLARE_MSM_GPIO_PINS(173); +DECLARE_MSM_GPIO_PINS(174); +DECLARE_MSM_GPIO_PINS(175); +DECLARE_MSM_GPIO_PINS(176); +DECLARE_MSM_GPIO_PINS(177); +DECLARE_MSM_GPIO_PINS(178); +DECLARE_MSM_GPIO_PINS(179); +DECLARE_MSM_GPIO_PINS(180); +DECLARE_MSM_GPIO_PINS(181); +DECLARE_MSM_GPIO_PINS(182); +DECLARE_MSM_GPIO_PINS(183); +DECLARE_MSM_GPIO_PINS(184); +DECLARE_MSM_GPIO_PINS(185); +DECLARE_MSM_GPIO_PINS(186); +DECLARE_MSM_GPIO_PINS(187); +DECLARE_MSM_GPIO_PINS(188); +DECLARE_MSM_GPIO_PINS(189); +DECLARE_MSM_GPIO_PINS(190); +DECLARE_MSM_GPIO_PINS(191); +DECLARE_MSM_GPIO_PINS(192); +DECLARE_MSM_GPIO_PINS(193); +DECLARE_MSM_GPIO_PINS(194); +DECLARE_MSM_GPIO_PINS(195); +DECLARE_MSM_GPIO_PINS(196); +DECLARE_MSM_GPIO_PINS(197); +DECLARE_MSM_GPIO_PINS(198); +DECLARE_MSM_GPIO_PINS(199); +DECLARE_MSM_GPIO_PINS(200); +DECLARE_MSM_GPIO_PINS(201); +DECLARE_MSM_GPIO_PINS(202); +DECLARE_MSM_GPIO_PINS(203); +DECLARE_MSM_GPIO_PINS(204); +DECLARE_MSM_GPIO_PINS(205); +DECLARE_MSM_GPIO_PINS(206); +DECLARE_MSM_GPIO_PINS(207); +DECLARE_MSM_GPIO_PINS(208); +DECLARE_MSM_GPIO_PINS(209); +DECLARE_MSM_GPIO_PINS(210); +DECLARE_MSM_GPIO_PINS(211); +DECLARE_MSM_GPIO_PINS(212); +DECLARE_MSM_GPIO_PINS(213); +DECLARE_MSM_GPIO_PINS(214); +DECLARE_MSM_GPIO_PINS(215); +DECLARE_MSM_GPIO_PINS(216); + +static const unsigned int ufs_reset_pins[] = { 217 }; +static const unsigned int sdc2_clk_pins[] = { 218 }; +static const unsigned int sdc2_cmd_pins[] = { 219 }; +static const unsigned int sdc2_data_pins[] = { 220 }; + +enum kaanapali_functions { + msm_mux_gpio, + msm_mux_aoss_cti, + msm_mux_atest_char, + msm_mux_atest_usb, + msm_mux_audio_ext_mclk0, + msm_mux_audio_ext_mclk1, + msm_mux_audio_ref_clk, + msm_mux_cam_asc_mclk2, + msm_mux_cam_asc_mclk4, + msm_mux_cam_mclk, + msm_mux_cci_async_in, + msm_mux_cci_i2c_scl, + msm_mux_cci_i2c_sda, + msm_mux_cci_timer, + msm_mux_cmu_rng, + msm_mux_coex_uart1_rx, + msm_mux_coex_uart1_tx, + msm_mux_coex_uart2_rx, + msm_mux_coex_uart2_tx, + msm_mux_dbg_out_clk, + msm_mux_ddr_bist_complete, + msm_mux_ddr_bist_fail, + msm_mux_ddr_bist_start, + msm_mux_ddr_bist_stop, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_dp_hot, + msm_mux_egpio, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gnss_adc0, + msm_mux_gnss_adc1, + msm_mux_i2chub0_se0, + msm_mux_i2chub0_se1, + msm_mux_i2chub0_se2, + msm_mux_i2chub0_se3, + msm_mux_i2chub0_se4, + msm_mux_i2s0_data0, + msm_mux_i2s0_data1, + msm_mux_i2s0_sck, + msm_mux_i2s0_ws, + msm_mux_i2s1_data0, + msm_mux_i2s1_data1, + msm_mux_i2s1_sck, + msm_mux_i2s1_ws, + msm_mux_ibi_i3c, + msm_mux_jitter_bist, + msm_mux_mdp_esync0_out, + msm_mux_mdp_esync1_out, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0_out, + msm_mux_mdp_vsync1_out, + msm_mux_mdp_vsync2_out, + msm_mux_mdp_vsync3_out, + msm_mux_mdp_vsync5_out, + msm_mux_mdp_vsync_e, + msm_mux_nav_gpio0, + msm_mux_nav_gpio1, + msm_mux_nav_gpio2, + msm_mux_nav_gpio3, + msm_mux_pcie0_clk_req_n, + msm_mux_phase_flag, + msm_mux_pll_bist_sync, + msm_mux_pll_clk_aux, + msm_mux_prng_rosc0, + msm_mux_prng_rosc1, + msm_mux_prng_rosc2, + msm_mux_prng_rosc3, + msm_mux_qdss_cti, + msm_mux_qdss_gpio_traceclk, + msm_mux_qdss_gpio_tracectl, + msm_mux_qdss_gpio_tracedata, + msm_mux_qlink_big_enable, + msm_mux_qlink_big_request, + msm_mux_qlink_little_enable, + msm_mux_qlink_little_request, + msm_mux_qlink_wmss, + msm_mux_qspi0, + msm_mux_qspi1, + msm_mux_qspi2, + msm_mux_qspi3, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qup1_se0, + msm_mux_qup1_se1, + msm_mux_qup1_se2, + msm_mux_qup1_se3, + msm_mux_qup1_se4, + msm_mux_qup1_se5, + msm_mux_qup1_se6, + msm_mux_qup1_se7, + msm_mux_qup2_se0, + msm_mux_qup2_se1, + msm_mux_qup2_se2, + msm_mux_qup2_se3, + msm_mux_qup2_se4, + msm_mux_qup3_se0, + msm_mux_qup3_se1, + msm_mux_qup3_se2, + msm_mux_qup3_se3, + msm_mux_qup3_se4, + msm_mux_qup3_se5, + msm_mux_qup4_se0, + msm_mux_qup4_se1, + msm_mux_qup4_se2, + msm_mux_qup4_se3, + msm_mux_qup4_se4, + msm_mux_sd_write_protect, + msm_mux_sdc40, + msm_mux_sdc41, + msm_mux_sdc42, + msm_mux_sdc43, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sys_throttle, + msm_mux_tb_trig_sdc2, + msm_mux_tb_trig_sdc4, + msm_mux_tmess_prng0, + msm_mux_tmess_prng1, + msm_mux_tmess_prng2, + msm_mux_tmess_prng3, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_tsense_pwm3, + msm_mux_tsense_pwm4, + msm_mux_tsense_pwm5, + msm_mux_tsense_pwm6, + msm_mux_tsense_pwm7, + msm_mux_uim0_clk, + msm_mux_uim0_data, + msm_mux_uim0_present, + msm_mux_uim0_reset, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_usb0_hs, + msm_mux_usb_phy, + msm_mux_vfr_0, + msm_mux_vfr_1, + msm_mux_vsense_trigger_mirnat, + msm_mux_wcn_sw, + msm_mux_wcn_sw_ctrl, + msm_mux__, +}; + +static const char *const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", + "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", + "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", + "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", + "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", + "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", + "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", + "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101", + "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", + "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", + "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", + "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", + "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", + "gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137", + "gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143", + "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149", + "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155", + "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161", + "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", "gpio167", + "gpio168", "gpio169", "gpio170", "gpio171", "gpio172", "gpio173", + "gpio174", "gpio175", "gpio176", "gpio177", "gpio178", "gpio179", + "gpio180", "gpio181", "gpio182", "gpio183", "gpio184", "gpio185", + "gpio186", "gpio187", "gpio188", "gpio189", "gpio190", "gpio191", + "gpio192", "gpio193", "gpio194", "gpio195", "gpio196", "gpio197", + "gpio198", "gpio199", "gpio200", "gpio201", "gpio202", "gpio203", + "gpio204", "gpio205", "gpio206", "gpio207", "gpio208", "gpio209", + "gpio210", "gpio211", "gpio212", "gpio213", "gpio214", "gpio215", + "gpio216", +}; + +static const char *const aoss_cti_groups[] = { + "gpio74", "gpio75", "gpio76", "gpio77", +}; + +static const char *const atest_char_groups[] = { + "gpio126", "gpio127", "gpio128", "gpio129", "gpio133", +}; + +static const char *const atest_usb_groups[] = { + "gpio70", "gpio71", "gpio72", "gpio73", "gpio129", +}; + +static const char *const audio_ext_mclk0_groups[] = { + "gpio121", +}; + +static const char *const audio_ext_mclk1_groups[] = { + "gpio120", +}; + +static const char *const audio_ref_clk_groups[] = { + "gpio120", +}; + +static const char *const cam_asc_mclk2_groups[] = { + "gpio91", +}; + +static const char *const cam_asc_mclk4_groups[] = { + "gpio93", +}; + +static const char *const cam_mclk_groups[] = { + "gpio89", "gpio90", "gpio92", "gpio94", "gpio95", "gpio96", +}; + +static const char *const cci_async_in_groups[] = { + "gpio10", "gpio11", "gpio15", +}; + +static const char *const cci_i2c_scl_groups[] = { + "gpio110", "gpio112", "gpio114", "gpio116", "gpio149", "gpio160", +}; + +static const char *const cci_i2c_sda_groups[] = { + "gpio107", "gpio108", "gpio109", "gpio111", "gpio113", "gpio115", +}; + +static const char *const cci_timer_groups[] = { + "gpio105", "gpio106", "gpio107", "gpio159", "gpio160", +}; + +static const char *const cmu_rng_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", "gpio144", "gpio145", + "gpio146", "gpio147", +}; + +static const char *const coex_uart1_rx_groups[] = { + "gpio144", +}; + +static const char *const coex_uart1_tx_groups[] = { + "gpio145", +}; + +static const char *const coex_uart2_rx_groups[] = { + "gpio146", +}; + +static const char *const coex_uart2_tx_groups[] = { + "gpio147", +}; + +static const char *const dbg_out_clk_groups[] = { + "gpio42", +}; + +static const char *const ddr_bist_complete_groups[] = { + "gpio44", +}; + +static const char *const ddr_bist_fail_groups[] = { + "gpio40", +}; + +static const char *const ddr_bist_start_groups[] = { + "gpio41", +}; + +static const char *const ddr_bist_stop_groups[] = { + "gpio45", +}; + +static const char *const ddr_pxi0_groups[] = { + "gpio54", "gpio55", +}; + +static const char *const ddr_pxi1_groups[] = { + "gpio44", "gpio45", +}; + +static const char *const ddr_pxi2_groups[] = { + "gpio43", "gpio52", +}; + +static const char *const ddr_pxi3_groups[] = { + "gpio46", "gpio53", +}; + +static const char *const dp_hot_groups[] = { + "gpio47", +}; + +static const char *const egpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio28", "gpio29", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio163", "gpio164", "gpio165", "gpio166", + "gpio167", "gpio168", "gpio169", "gpio170", "gpio171", "gpio172", + "gpio173", "gpio174", "gpio175", "gpio176", "gpio177", "gpio178", + "gpio179", "gpio180", "gpio181", "gpio182", "gpio183", "gpio184", + "gpio185", "gpio186", "gpio187", "gpio188", "gpio189", "gpio190", + "gpio191", "gpio192", "gpio193", "gpio194", "gpio195", "gpio196", + "gpio197", "gpio198", "gpio199", "gpio200", "gpio201", "gpio202", + "gpio203", "gpio204", "gpio205", "gpio206", "gpio207", "gpio208", + "gpio209", "gpio210", "gpio211", "gpio212", "gpio213", "gpio214", + "gpio215", "gpio216", +}; + +static const char *const gcc_gp1_groups[] = { + "gpio130", "gpio158", +}; + +static const char *const gcc_gp2_groups[] = { + "gpio86", "gpio131", +}; + +static const char *const gcc_gp3_groups[] = { + "gpio87", "gpio132", +}; + +static const char *const gnss_adc0_groups[] = { + "gpio40", "gpio41", +}; + +static const char *const gnss_adc1_groups[] = { + "gpio42", "gpio77", +}; + +static const char *const i2chub0_se0_groups[] = { + "gpio66", "gpio67", +}; + +static const char *const i2chub0_se1_groups[] = { + "gpio78", "gpio79", +}; + +static const char *const i2chub0_se2_groups[] = { + "gpio68", "gpio69", +}; + +static const char *const i2chub0_se3_groups[] = { + "gpio70", "gpio71", +}; + +static const char *const i2chub0_se4_groups[] = { + "gpio72", "gpio73", +}; + +static const char *const i2s0_data0_groups[] = { + "gpio123", +}; + +static const char *const i2s0_data1_groups[] = { + "gpio124", +}; + +static const char *const i2s0_sck_groups[] = { + "gpio122", +}; + +static const char *const i2s0_ws_groups[] = { + "gpio125", +}; + +static const char *const i2s1_data0_groups[] = { + "gpio118", +}; + +static const char *const i2s1_data1_groups[] = { + "gpio120", +}; + +static const char *const i2s1_sck_groups[] = { + "gpio117", +}; + +static const char *const i2s1_ws_groups[] = { + "gpio119", +}; + +static const char *const ibi_i3c_groups[] = { + "gpio0", "gpio1", "gpio4", "gpio5", "gpio8", "gpio9", + "gpio12", "gpio13", "gpio28", "gpio29", "gpio32", "gpio33", + "gpio36", "gpio37", "gpio48", "gpio49", "gpio60", "gpio61", +}; + +static const char *const jitter_bist_groups[] = { + "gpio73", +}; + +static const char *const mdp_esync0_out_groups[] = { + "gpio88", +}; + +static const char *const mdp_esync1_out_groups[] = { + "gpio100", +}; + +static const char *const mdp_vsync_groups[] = { + "gpio86", "gpio87", "gpio97", "gpio98", +}; + +static const char *const mdp_vsync0_out_groups[] = { + "gpio86", +}; + +static const char *const mdp_vsync1_out_groups[] = { + "gpio86", +}; + +static const char *const mdp_vsync2_out_groups[] = { + "gpio87", +}; + +static const char *const mdp_vsync3_out_groups[] = { + "gpio87", +}; + +static const char *const mdp_vsync5_out_groups[] = { + "gpio87", +}; + +static const char *const mdp_vsync_e_groups[] = { + "gpio88", +}; + +static const char *const nav_gpio0_groups[] = { + "gpio150", +}; + +static const char *const nav_gpio1_groups[] = { + "gpio151", +}; + +static const char *const nav_gpio2_groups[] = { + "gpio148", +}; + +static const char *const nav_gpio3_groups[] = { + "gpio150", +}; + +static const char *const pcie0_clk_req_n_groups[] = { + "gpio103", +}; + +static const char *const phase_flag_groups[] = { + "gpio117", "gpio118", "gpio119", "gpio123", "gpio124", "gpio125", + "gpio169", "gpio170", "gpio171", "gpio172", "gpio173", "gpio175", + "gpio176", "gpio179", "gpio180", "gpio181", "gpio184", "gpio185", + "gpio192", "gpio196", "gpio197", "gpio198", "gpio199", "gpio204", + "gpio206", "gpio207", "gpio208", "gpio210", "gpio211", "gpio214", + "gpio215", "gpio216", +}; + +static const char *const pll_bist_sync_groups[] = { + "gpio104", +}; + +static const char *const pll_clk_aux_groups[] = { + "gpio94", +}; + +static const char *const prng_rosc0_groups[] = { + "gpio85", +}; + +static const char *const prng_rosc1_groups[] = { + "gpio64", +}; + +static const char *const prng_rosc2_groups[] = { + "gpio65", +}; + +static const char *const prng_rosc3_groups[] = { + "gpio66", +}; + +static const char *const qdss_cti_groups[] = { + "gpio27", "gpio31", "gpio72", "gpio73", "gpio82", "gpio83", + "gpio155", "gpio158", +}; + +static const char *const qdss_gpio_traceclk_groups[] = { + "gpio128", +}; + +static const char *const qdss_gpio_tracectl_groups[] = { + "gpio127", +}; + +static const char *const qdss_gpio_tracedata_groups[] = { + "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", + "gpio62", "gpio63", "gpio68", "gpio69", "gpio126", "gpio129", + "gpio130", "gpio131", "gpio132", "gpio133", +}; + +static const char *const qlink_big_enable_groups[] = { + "gpio156", +}; + +static const char *const qlink_big_request_groups[] = { + "gpio155", +}; + +static const char *const qlink_little_enable_groups[] = { + "gpio153", +}; + +static const char *const qlink_little_request_groups[] = { + "gpio152", +}; + +static const char *const qlink_wmss_groups[] = { + "gpio154", +}; + +static const char *const qspi0_groups[] = { + "gpio80", +}; + +static const char *const qspi1_groups[] = { + "gpio147", +}; + +static const char *const qspi2_groups[] = { + "gpio81", +}; + +static const char *const qspi3_groups[] = { + "gpio82", +}; + +static const char *const qspi_clk_groups[] = { + "gpio83", +}; + +static const char *const qspi_cs_groups[] = { + "gpio146", "gpio148", +}; + +static const char *const qup1_se0_groups[] = { + "gpio80", "gpio81", "gpio82", "gpio83", +}; + +static const char *const qup1_se1_groups[] = { + "gpio74", "gpio75", "gpio76", "gpio77", +}; + +static const char *const qup1_se2_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", "gpio130", "gpio131", "gpio132", +}; + +static const char *const qup1_se3_groups[] = { + "gpio44", "gpio45", "gpio46", "gpio47", +}; + +static const char *const qup1_se4_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; + +static const char *const qup1_se5_groups[] = { + "gpio52", "gpio53", "gpio54", "gpio55", +}; + +static const char *const qup1_se6_groups[] = { + "gpio56", "gpio57", "gpio58", "gpio59", +}; + +static const char *const qup1_se7_groups[] = { + "gpio60", "gpio61", "gpio62", "gpio63", +}; + +static const char *const qup2_se0_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char *const qup2_se1_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const char *const qup2_se2_groups[] = { + "gpio117", "gpio118", "gpio119", "gpio120", +}; + +static const char *const qup2_se3_groups[] = { + "gpio122", "gpio123", "gpio124", "gpio125", +}; + +static const char *const qup2_se4_groups[] = { + "gpio208", "gpio209", +}; + +static const char *const qup3_se0_groups[] = { + "gpio64", "gpio65", +}; + +static const char *const qup3_se1_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio15", +}; + +static const char *const qup3_se2_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; + +static const char *const qup3_se3_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; + +static const char *const qup3_se4_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; + +static const char *const qup3_se5_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", +}; + +static const char *const qup4_se0_groups[] = { + "gpio48", "gpio49", "gpio50", "gpio51", +}; + +static const char *const qup4_se1_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", +}; + +static const char *const qup4_se2_groups[] = { + "gpio32", "gpio33", "gpio34", "gpio35", +}; + +static const char *const qup4_se3_groups[] = { + "gpio84", "gpio121", +}; + +static const char *const qup4_se4_groups[] = { + "gpio161", "gpio162", +}; + +static const char *const sd_write_protect_groups[] = { + "gpio85", +}; + +static const char *const sdc40_groups[] = { + "gpio80", +}; + +static const char *const sdc41_groups[] = { + "gpio147", +}; + +static const char *const sdc42_groups[] = { + "gpio81", +}; + +static const char *const sdc43_groups[] = { + "gpio82", +}; + +static const char *const sdc4_clk_groups[] = { + "gpio83", +}; + +static const char *const sdc4_cmd_groups[] = { + "gpio148", +}; + +static const char *const sys_throttle_groups[] = { + "gpio99", +}; + +static const char *const tb_trig_sdc2_groups[] = { + "gpio88", +}; + +static const char *const tb_trig_sdc4_groups[] = { + "gpio146", +}; + +static const char *const tmess_prng0_groups[] = { + "gpio85", +}; + +static const char *const tmess_prng1_groups[] = { + "gpio64", +}; + +static const char *const tmess_prng2_groups[] = { + "gpio65", +}; + +static const char *const tmess_prng3_groups[] = { + "gpio66", +}; + +static const char *const tsense_pwm1_groups[] = { + "gpio87", +}; + +static const char *const tsense_pwm2_groups[] = { + "gpio10", +}; + +static const char *const tsense_pwm3_groups[] = { + "gpio97", +}; + +static const char *const tsense_pwm4_groups[] = { + "gpio99", +}; + +static const char *const tsense_pwm5_groups[] = { + "gpio105", +}; + +static const char *const tsense_pwm6_groups[] = { + "gpio106", +}; + +static const char *const tsense_pwm7_groups[] = { + "gpio159", +}; + +static const char *const uim0_clk_groups[] = { + "gpio127", +}; + +static const char *const uim0_data_groups[] = { + "gpio126", +}; + +static const char *const uim0_present_groups[] = { + "gpio129", +}; + +static const char *const uim0_reset_groups[] = { + "gpio128", +}; + +static const char *const uim1_clk_groups[] = { + "gpio37", "gpio55", "gpio71", "gpio131", +}; + +static const char *const uim1_data_groups[] = { + "gpio36", "gpio54", "gpio70", "gpio130", +}; + +static const char *const uim1_present_groups[] = { + "gpio133", +}; + +static const char *const uim1_reset_groups[] = { + "gpio39", "gpio56", "gpio72", "gpio132", +}; + +static const char *const usb0_hs_groups[] = { + "gpio79", +}; + +static const char *const usb_phy_groups[] = { + "gpio59", "gpio60", +}; + +static const char *const vfr_0_groups[] = { + "gpio146", +}; + +static const char *const vfr_1_groups[] = { + "gpio151", +}; + +static const char *const vsense_trigger_mirnat_groups[] = { + "gpio59", +}; + +static const char *const wcn_sw_groups[] = { + "gpio19", +}; + +static const char *const wcn_sw_ctrl_groups[] = { + "gpio18", +}; + +static const struct pinfunction kaanapali_functions[] = { + MSM_GPIO_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(aoss_cti), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_usb), + MSM_PIN_FUNCTION(audio_ext_mclk0), + MSM_PIN_FUNCTION(audio_ext_mclk1), + MSM_PIN_FUNCTION(audio_ref_clk), + MSM_PIN_FUNCTION(cam_asc_mclk2), + MSM_PIN_FUNCTION(cam_asc_mclk4), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async_in), + MSM_PIN_FUNCTION(cci_i2c_scl), + MSM_PIN_FUNCTION(cci_i2c_sda), + MSM_PIN_FUNCTION(cci_timer), + MSM_PIN_FUNCTION(cmu_rng), + MSM_PIN_FUNCTION(coex_uart1_rx), + MSM_PIN_FUNCTION(coex_uart1_tx), + MSM_PIN_FUNCTION(coex_uart2_rx), + MSM_PIN_FUNCTION(coex_uart2_tx), + MSM_PIN_FUNCTION(dbg_out_clk), + MSM_PIN_FUNCTION(ddr_bist_complete), + MSM_PIN_FUNCTION(ddr_bist_fail), + MSM_PIN_FUNCTION(ddr_bist_start), + MSM_PIN_FUNCTION(ddr_bist_stop), + MSM_PIN_FUNCTION(ddr_pxi0), + MSM_PIN_FUNCTION(ddr_pxi1), + MSM_PIN_FUNCTION(ddr_pxi2), + MSM_PIN_FUNCTION(ddr_pxi3), + MSM_PIN_FUNCTION(dp_hot), + MSM_PIN_FUNCTION(egpio), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(gnss_adc0), + MSM_PIN_FUNCTION(gnss_adc1), + MSM_PIN_FUNCTION(i2chub0_se0), + MSM_PIN_FUNCTION(i2chub0_se1), + MSM_PIN_FUNCTION(i2chub0_se2), + MSM_PIN_FUNCTION(i2chub0_se3), + MSM_PIN_FUNCTION(i2chub0_se4), + MSM_PIN_FUNCTION(i2s0_data0), + MSM_PIN_FUNCTION(i2s0_data1), + MSM_PIN_FUNCTION(i2s0_sck), + MSM_PIN_FUNCTION(i2s0_ws), + MSM_PIN_FUNCTION(i2s1_data0), + MSM_PIN_FUNCTION(i2s1_data1), + MSM_PIN_FUNCTION(i2s1_sck), + MSM_PIN_FUNCTION(i2s1_ws), + MSM_PIN_FUNCTION(ibi_i3c), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(mdp_esync0_out), + MSM_PIN_FUNCTION(mdp_esync1_out), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mdp_vsync0_out), + MSM_PIN_FUNCTION(mdp_vsync1_out), + MSM_PIN_FUNCTION(mdp_vsync2_out), + MSM_PIN_FUNCTION(mdp_vsync3_out), + MSM_PIN_FUNCTION(mdp_vsync5_out), + MSM_PIN_FUNCTION(mdp_vsync_e), + MSM_PIN_FUNCTION(nav_gpio0), + MSM_PIN_FUNCTION(nav_gpio1), + MSM_PIN_FUNCTION(nav_gpio2), + MSM_PIN_FUNCTION(nav_gpio3), + MSM_PIN_FUNCTION(pcie0_clk_req_n), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist_sync), + MSM_PIN_FUNCTION(pll_clk_aux), + MSM_PIN_FUNCTION(prng_rosc0), + MSM_PIN_FUNCTION(prng_rosc1), + MSM_PIN_FUNCTION(prng_rosc2), + MSM_PIN_FUNCTION(prng_rosc3), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qdss_gpio_traceclk), + MSM_PIN_FUNCTION(qdss_gpio_tracectl), + MSM_PIN_FUNCTION(qdss_gpio_tracedata), + MSM_PIN_FUNCTION(qlink_big_enable), + MSM_PIN_FUNCTION(qlink_big_request), + MSM_PIN_FUNCTION(qlink_little_enable), + MSM_PIN_FUNCTION(qlink_little_request), + MSM_PIN_FUNCTION(qlink_wmss), + MSM_PIN_FUNCTION(qspi0), + MSM_PIN_FUNCTION(qspi1), + MSM_PIN_FUNCTION(qspi2), + MSM_PIN_FUNCTION(qspi3), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs), + MSM_PIN_FUNCTION(qup1_se0), + MSM_PIN_FUNCTION(qup1_se1), + MSM_PIN_FUNCTION(qup1_se2), + MSM_PIN_FUNCTION(qup1_se3), + MSM_PIN_FUNCTION(qup1_se4), + MSM_PIN_FUNCTION(qup1_se5), + MSM_PIN_FUNCTION(qup1_se6), + MSM_PIN_FUNCTION(qup1_se7), + MSM_PIN_FUNCTION(qup2_se0), + MSM_PIN_FUNCTION(qup2_se1), + MSM_PIN_FUNCTION(qup2_se2), + MSM_PIN_FUNCTION(qup2_se3), + MSM_PIN_FUNCTION(qup2_se4), + MSM_PIN_FUNCTION(qup3_se0), + MSM_PIN_FUNCTION(qup3_se1), + MSM_PIN_FUNCTION(qup3_se2), + MSM_PIN_FUNCTION(qup3_se3), + MSM_PIN_FUNCTION(qup3_se4), + MSM_PIN_FUNCTION(qup3_se5), + MSM_PIN_FUNCTION(qup4_se0), + MSM_PIN_FUNCTION(qup4_se1), + MSM_PIN_FUNCTION(qup4_se2), + MSM_PIN_FUNCTION(qup4_se3), + MSM_PIN_FUNCTION(qup4_se4), + MSM_PIN_FUNCTION(sd_write_protect), + MSM_PIN_FUNCTION(sdc40), + MSM_PIN_FUNCTION(sdc41), + MSM_PIN_FUNCTION(sdc42), + MSM_PIN_FUNCTION(sdc43), + MSM_PIN_FUNCTION(sdc4_clk), + MSM_PIN_FUNCTION(sdc4_cmd), + MSM_PIN_FUNCTION(sys_throttle), + MSM_PIN_FUNCTION(tb_trig_sdc2), + MSM_PIN_FUNCTION(tb_trig_sdc4), + MSM_PIN_FUNCTION(tmess_prng0), + MSM_PIN_FUNCTION(tmess_prng1), + MSM_PIN_FUNCTION(tmess_prng2), + MSM_PIN_FUNCTION(tmess_prng3), + MSM_PIN_FUNCTION(tsense_pwm1), + MSM_PIN_FUNCTION(tsense_pwm2), + MSM_PIN_FUNCTION(tsense_pwm3), + MSM_PIN_FUNCTION(tsense_pwm4), + MSM_PIN_FUNCTION(tsense_pwm5), + MSM_PIN_FUNCTION(tsense_pwm6), + MSM_PIN_FUNCTION(tsense_pwm7), + MSM_PIN_FUNCTION(uim0_clk), + MSM_PIN_FUNCTION(uim0_data), + MSM_PIN_FUNCTION(uim0_present), + MSM_PIN_FUNCTION(uim0_reset), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(usb0_hs), + MSM_PIN_FUNCTION(usb_phy), + MSM_PIN_FUNCTION(vfr_0), + MSM_PIN_FUNCTION(vfr_1), + MSM_PIN_FUNCTION(vsense_trigger_mirnat), + MSM_PIN_FUNCTION(wcn_sw), + MSM_PIN_FUNCTION(wcn_sw_ctrl), +}; + +/* Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup kaanapali_groups[] = { + [0] = PINGROUP(0, qup2_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [1] = PINGROUP(1, qup2_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [2] = PINGROUP(2, qup2_se0, _, _, _, _, _, _, _, _, _, egpio), + [3] = PINGROUP(3, qup2_se0, _, _, _, _, _, _, _, _, _, egpio), + [4] = PINGROUP(4, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [5] = PINGROUP(5, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [6] = PINGROUP(6, qup2_se1, _, _, _, _, _, _, _, _, _, egpio), + [7] = PINGROUP(7, qup2_se1, _, _, _, _, _, _, _, _, _, egpio), + [8] = PINGROUP(8, qup3_se1, ibi_i3c, _, _, _, _, _, _, _, _, _), + [9] = PINGROUP(9, qup3_se1, ibi_i3c, _, _, _, _, _, _, _, _, _), + [10] = PINGROUP(10, qup3_se1, cci_async_in, _, tsense_pwm2, _, _, _, _, _, _, _), + [11] = PINGROUP(11, qup3_se1, cci_async_in, _, _, _, _, _, _, _, _, _), + [12] = PINGROUP(12, qup3_se2, ibi_i3c, qup3_se1, _, _, _, _, _, _, _, _), + [13] = PINGROUP(13, qup3_se2, ibi_i3c, qup3_se1, _, _, _, _, _, _, _, _), + [14] = PINGROUP(14, qup3_se2, _, _, _, _, _, _, _, _, _, _), + [15] = PINGROUP(15, qup3_se2, cci_async_in, qup3_se1, _, _, _, _, _, _, _, _), + [16] = PINGROUP(16, qup3_se3, _, _, _, _, _, _, _, _, _, _), + [17] = PINGROUP(17, qup3_se3, _, _, _, _, _, _, _, _, _, _), + [18] = PINGROUP(18, wcn_sw_ctrl, qup3_se3, _, _, _, _, _, _, _, _, _), + [19] = PINGROUP(19, wcn_sw, qup3_se3, _, _, _, _, _, _, _, _, _), + [20] = PINGROUP(20, qup3_se4, _, _, _, _, _, _, _, _, _, _), + [21] = PINGROUP(21, qup3_se4, _, _, _, _, _, _, _, _, _, _), + [22] = PINGROUP(22, qup3_se4, _, _, _, _, _, _, _, _, _, _), + [23] = PINGROUP(23, qup3_se4, _, _, _, _, _, _, _, _, _, _), + [24] = PINGROUP(24, qup3_se5, _, _, _, _, _, _, _, _, _, _), + [25] = PINGROUP(25, qup3_se5, _, _, _, _, _, _, _, _, _, _), + [26] = PINGROUP(26, qup3_se5, _, _, _, _, _, _, _, _, _, _), + [27] = PINGROUP(27, qup3_se5, qdss_cti, _, _, _, _, _, _, _, _, _), + [28] = PINGROUP(28, qup4_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [29] = PINGROUP(29, qup4_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [30] = PINGROUP(30, qup4_se1, _, _, _, _, _, _, _, _, _, _), + [31] = PINGROUP(31, qup4_se1, qdss_cti, _, _, _, _, _, _, _, _, _), + [32] = PINGROUP(32, qup4_se2, ibi_i3c, _, _, _, _, _, _, _, _, _), + [33] = PINGROUP(33, qup4_se2, ibi_i3c, _, _, _, _, _, _, _, _, _), + [34] = PINGROUP(34, qup4_se2, _, _, _, _, _, _, _, _, _, _), + [35] = PINGROUP(35, qup4_se2, _, _, _, _, _, _, _, _, _, _), + [36] = PINGROUP(36, qup1_se4, uim1_data, ibi_i3c, _, _, _, _, _, _, _, _), + [37] = PINGROUP(37, qup1_se4, uim1_clk, ibi_i3c, _, _, _, _, _, _, _, _), + [38] = PINGROUP(38, qup1_se4, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, _), + [39] = PINGROUP(39, qup1_se4, uim1_reset, qdss_gpio_tracedata, _, _, _, _, _, _, _, _), + [40] = PINGROUP(40, qup1_se2, cmu_rng, ddr_bist_fail, _, qdss_gpio_tracedata, gnss_adc0, + _, _, _, _, _), + [41] = PINGROUP(41, qup1_se2, cmu_rng, ddr_bist_start, _, qdss_gpio_tracedata, gnss_adc0, + _, _, _, _, _), + [42] = PINGROUP(42, qup1_se2, cmu_rng, dbg_out_clk, qdss_gpio_tracedata, gnss_adc1, _, _, + _, _, _, _), + [43] = PINGROUP(43, qup1_se2, cmu_rng, _, qdss_gpio_tracedata, ddr_pxi2, _, _, _, _, _, _), + [44] = PINGROUP(44, qup1_se3, ddr_bist_complete, ddr_pxi1, _, _, _, _, _, _, _, _), + [45] = PINGROUP(45, qup1_se3, ddr_bist_stop, ddr_pxi1, _, _, _, _, _, _, _, _), + [46] = PINGROUP(46, qup1_se3, ddr_pxi3, _, _, _, _, _, _, _, _, _), + [47] = PINGROUP(47, qup1_se3, dp_hot, _, _, _, _, _, _, _, _, _), + [48] = PINGROUP(48, qup4_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [49] = PINGROUP(49, qup4_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [50] = PINGROUP(50, qup4_se0, _, _, _, _, _, _, _, _, _, egpio), + [51] = PINGROUP(51, qup4_se0, _, _, _, _, _, _, _, _, _, egpio), + [52] = PINGROUP(52, qup1_se5, ddr_pxi2, _, _, _, _, _, _, _, _, _), + [53] = PINGROUP(53, qup1_se5, _, ddr_pxi3, _, _, _, _, _, _, _, _), + [54] = PINGROUP(54, qup1_se5, uim1_data, ddr_pxi0, _, _, _, _, _, _, _, _), + [55] = PINGROUP(55, qup1_se5, uim1_clk, ddr_pxi0, _, _, _, _, _, _, _, _), + [56] = PINGROUP(56, qup1_se6, uim1_reset, _, _, _, _, _, _, _, _, _), + [57] = PINGROUP(57, qup1_se6, _, _, _, _, _, _, _, _, _, _), + [58] = PINGROUP(58, qup1_se6, _, _, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, qup1_se6, usb_phy, vsense_trigger_mirnat, _, _, _, _, _, _, _, _), + [60] = PINGROUP(60, qup1_se7, usb_phy, ibi_i3c, _, _, _, _, _, _, _, _), + [61] = PINGROUP(61, qup1_se7, ibi_i3c, _, _, _, _, _, _, _, _, _), + [62] = PINGROUP(62, qup1_se7, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, _), + [63] = PINGROUP(63, qup1_se7, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, _), + [64] = PINGROUP(64, qup3_se0, _, prng_rosc1, tmess_prng1, _, _, _, _, _, _, _), + [65] = PINGROUP(65, qup3_se0, _, prng_rosc2, tmess_prng2, _, _, _, _, _, _, _), + [66] = PINGROUP(66, i2chub0_se0, prng_rosc3, tmess_prng3, _, _, _, _, _, _, _, _), + [67] = PINGROUP(67, i2chub0_se0, _, _, _, _, _, _, _, _, _, _), + [68] = PINGROUP(68, i2chub0_se2, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, _), + [69] = PINGROUP(69, i2chub0_se2, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, _), + [70] = PINGROUP(70, i2chub0_se3, uim1_data, _, atest_usb, _, _, _, _, _, _, _), + [71] = PINGROUP(71, i2chub0_se3, uim1_clk, _, atest_usb, _, _, _, _, _, _, _), + [72] = PINGROUP(72, i2chub0_se4, uim1_reset, qdss_cti, _, atest_usb, _, _, _, _, _, _), + [73] = PINGROUP(73, i2chub0_se4, qdss_cti, jitter_bist, atest_usb, _, _, _, _, _, _, _), + [74] = PINGROUP(74, qup1_se1, aoss_cti, _, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, qup1_se1, aoss_cti, _, _, _, _, _, _, _, _, _), + [76] = PINGROUP(76, qup1_se1, aoss_cti, _, _, _, _, _, _, _, _, _), + [77] = PINGROUP(77, qup1_se1, aoss_cti, gnss_adc1, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, i2chub0_se1, _, _, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, i2chub0_se1, usb0_hs, _, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, qup1_se0, sdc40, qspi0, _, _, _, _, _, _, _, _), + [81] = PINGROUP(81, qup1_se0, sdc42, qspi2, _, _, _, _, _, _, _, _), + [82] = PINGROUP(82, qup1_se0, sdc43, qdss_cti, qspi3, _, _, _, _, _, _, _), + [83] = PINGROUP(83, qup1_se0, sdc4_clk, qdss_cti, qspi_clk, _, _, _, _, _, _, _), + [84] = PINGROUP(84, qup4_se3, _, _, _, _, _, _, _, _, _, _), + [85] = PINGROUP(85, sd_write_protect, prng_rosc0, tmess_prng0, _, _, _, _, _, _, _, _), + [86] = PINGROUP(86, mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, gcc_gp2, _, _, _, _, _, _, + _), + [87] = PINGROUP(87, mdp_vsync, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out, gcc_gp3, _, + tsense_pwm1, _, _, _, _), + [88] = PINGROUP(88, mdp_vsync_e, mdp_esync0_out, tb_trig_sdc2, _, _, _, _, _, _, _, _), + [89] = PINGROUP(89, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [90] = PINGROUP(90, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [91] = PINGROUP(91, cam_asc_mclk2, _, _, _, _, _, _, _, _, _, _), + [92] = PINGROUP(92, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [93] = PINGROUP(93, cam_asc_mclk4, _, _, _, _, _, _, _, _, _, _), + [94] = PINGROUP(94, cam_mclk, pll_clk_aux, _, _, _, _, _, _, _, _, _), + [95] = PINGROUP(95, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [96] = PINGROUP(96, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [97] = PINGROUP(97, mdp_vsync, tsense_pwm3, _, _, _, _, _, _, _, _, _), + [98] = PINGROUP(98, mdp_vsync, _, _, _, _, _, _, _, _, _, _), + [99] = PINGROUP(99, sys_throttle, tsense_pwm4, _, _, _, _, _, _, _, _, _), + [100] = PINGROUP(100, mdp_esync1_out, _, _, _, _, _, _, _, _, _, _), + [101] = PINGROUP(101, _, _, _, _, _, _, _, _, _, _, _), + [102] = PINGROUP(102, _, _, _, _, _, _, _, _, _, _, _), + [103] = PINGROUP(103, pcie0_clk_req_n, _, _, _, _, _, _, _, _, _, _), + [104] = PINGROUP(104, pll_bist_sync, _, _, _, _, _, _, _, _, _, _), + [105] = PINGROUP(105, cci_timer, tsense_pwm5, _, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, cci_timer, tsense_pwm6, _, _, _, _, _, _, _, _, _), + [107] = PINGROUP(107, cci_timer, cci_i2c_sda, _, _, _, _, _, _, _, _, _), + [108] = PINGROUP(108, cci_i2c_sda, _, _, _, _, _, _, _, _, _, _), + [109] = PINGROUP(109, cci_i2c_sda, _, _, _, _, _, _, _, _, _, _), + [110] = PINGROUP(110, cci_i2c_scl, _, _, _, _, _, _, _, _, _, _), + [111] = PINGROUP(111, cci_i2c_sda, _, _, _, _, _, _, _, _, _, _), + [112] = PINGROUP(112, cci_i2c_scl, _, _, _, _, _, _, _, _, _, _), + [113] = PINGROUP(113, cci_i2c_sda, _, _, _, _, _, _, _, _, _, _), + [114] = PINGROUP(114, cci_i2c_scl, _, _, _, _, _, _, _, _, _, _), + [115] = PINGROUP(115, cci_i2c_sda, _, _, _, _, _, _, _, _, _, _), + [116] = PINGROUP(116, cci_i2c_scl, _, _, _, _, _, _, _, _, _, _), + [117] = PINGROUP(117, i2s1_sck, qup2_se2, phase_flag, _, _, _, _, _, _, _, _), + [118] = PINGROUP(118, i2s1_data0, qup2_se2, phase_flag, _, _, _, _, _, _, _, _), + [119] = PINGROUP(119, i2s1_ws, qup2_se2, phase_flag, _, _, _, _, _, _, _, _), + [120] = PINGROUP(120, i2s1_data1, qup2_se2, audio_ext_mclk1, audio_ref_clk, _, _, _, _, _, + _, _), + [121] = PINGROUP(121, audio_ext_mclk0, qup4_se3, _, _, _, _, _, _, _, _, _), + [122] = PINGROUP(122, i2s0_sck, qup2_se3, _, _, _, _, _, _, _, _, _), + [123] = PINGROUP(123, i2s0_data0, qup2_se3, _, phase_flag, _, _, _, _, _, _, _), + [124] = PINGROUP(124, i2s0_data1, qup2_se3, _, phase_flag, _, _, _, _, _, _, _), + [125] = PINGROUP(125, i2s0_ws, qup2_se3, phase_flag, _, _, _, _, _, _, _, _), + [126] = PINGROUP(126, uim0_data, qdss_gpio_tracedata, atest_char, _, _, _, _, _, _, _, _), + [127] = PINGROUP(127, uim0_clk, qdss_gpio_tracectl, atest_char, _, _, _, _, _, _, _, _), + [128] = PINGROUP(128, uim0_reset, qdss_gpio_traceclk, atest_char, _, _, _, _, _, _, _, _), + [129] = PINGROUP(129, uim0_present, qdss_gpio_tracedata, atest_usb, atest_char, _, _, _, _, + _, _, _), + [130] = PINGROUP(130, uim1_data, qup1_se2, gcc_gp1, qdss_gpio_tracedata, _, _, _, _, _, _, + _), + [131] = PINGROUP(131, uim1_clk, qup1_se2, gcc_gp2, qdss_gpio_tracedata, _, _, _, _, _, _, + _), + [132] = PINGROUP(132, uim1_reset, qup1_se2, gcc_gp3, qdss_gpio_tracedata, _, _, _, _, _, _, + _), + [133] = PINGROUP(133, uim1_present, qdss_gpio_tracedata, atest_char, _, _, _, _, _, _, _, + _), + [134] = PINGROUP(134, _, _, _, _, _, _, _, _, _, _, _), + [135] = PINGROUP(135, _, _, _, _, _, _, _, _, _, _, _), + [136] = PINGROUP(136, _, _, _, _, _, _, _, _, _, _, _), + [137] = PINGROUP(137, _, _, _, _, _, _, _, _, _, _, _), + [138] = PINGROUP(138, _, _, _, _, _, _, _, _, _, _, _), + [139] = PINGROUP(139, _, _, _, _, _, _, _, _, _, _, _), + [140] = PINGROUP(140, _, _, _, _, _, _, _, _, _, _, _), + [141] = PINGROUP(141, _, _, _, _, _, _, _, _, _, _, _), + [142] = PINGROUP(142, _, _, _, _, _, _, _, _, _, _, _), + [143] = PINGROUP(143, _, _, _, _, _, _, _, _, _, _, _), + [144] = PINGROUP(144, coex_uart1_rx, cmu_rng, _, _, _, _, _, _, _, _, _), + [145] = PINGROUP(145, coex_uart1_tx, cmu_rng, _, _, _, _, _, _, _, _, _), + [146] = PINGROUP(146, _, vfr_0, coex_uart2_rx, cmu_rng, tb_trig_sdc4, qspi_cs, _, _, _, _, + _), + [147] = PINGROUP(147, _, coex_uart2_tx, cmu_rng, sdc41, qspi1, _, _, _, _, _, _), + [148] = PINGROUP(148, nav_gpio2, _, sdc4_cmd, qspi_cs, _, _, _, _, _, _, _), + [149] = PINGROUP(149, cci_i2c_scl, _, _, _, _, _, _, _, _, _, _), + [150] = PINGROUP(150, nav_gpio0, nav_gpio3, _, _, _, _, _, _, _, _, _), + [151] = PINGROUP(151, nav_gpio1, vfr_1, _, _, _, _, _, _, _, _, _), + [152] = PINGROUP(152, qlink_little_request, _, _, _, _, _, _, _, _, _, _), + [153] = PINGROUP(153, qlink_little_enable, _, _, _, _, _, _, _, _, _, _), + [154] = PINGROUP(154, qlink_wmss, _, _, _, _, _, _, _, _, _, _), + [155] = PINGROUP(155, qlink_big_request, qdss_cti, _, _, _, _, _, _, _, _, _), + [156] = PINGROUP(156, qlink_big_enable, _, _, _, _, _, _, _, _, _, _), + [157] = PINGROUP(157, _, _, _, _, _, _, _, _, _, _, _), + [158] = PINGROUP(158, qdss_cti, gcc_gp1, _, _, _, _, _, _, _, _, _), + [159] = PINGROUP(159, cci_timer, tsense_pwm7, _, _, _, _, _, _, _, _, _), + [160] = PINGROUP(160, cci_timer, cci_i2c_scl, _, _, _, _, _, _, _, _, _), + [161] = PINGROUP(161, qup4_se4, _, _, _, _, _, _, _, _, _, _), + [162] = PINGROUP(162, qup4_se4, _, _, _, _, _, _, _, _, _, _), + [163] = PINGROUP(163, _, _, _, _, _, _, _, _, _, _, egpio), + [164] = PINGROUP(164, _, _, _, _, _, _, _, _, _, _, egpio), + [165] = PINGROUP(165, _, _, _, _, _, _, _, _, _, _, egpio), + [166] = PINGROUP(166, _, _, _, _, _, _, _, _, _, _, egpio), + [167] = PINGROUP(167, _, _, _, _, _, _, _, _, _, _, egpio), + [168] = PINGROUP(168, _, _, _, _, _, _, _, _, _, _, egpio), + [169] = PINGROUP(169, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [170] = PINGROUP(170, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [171] = PINGROUP(171, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [172] = PINGROUP(172, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [173] = PINGROUP(173, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [174] = PINGROUP(174, _, _, _, _, _, _, _, _, _, _, egpio), + [175] = PINGROUP(175, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [176] = PINGROUP(176, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [177] = PINGROUP(177, _, _, _, _, _, _, _, _, _, _, egpio), + [178] = PINGROUP(178, _, _, _, _, _, _, _, _, _, _, egpio), + [179] = PINGROUP(179, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [180] = PINGROUP(180, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [181] = PINGROUP(181, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [182] = PINGROUP(182, _, _, _, _, _, _, _, _, _, _, egpio), + [183] = PINGROUP(183, _, _, _, _, _, _, _, _, _, _, egpio), + [184] = PINGROUP(184, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [185] = PINGROUP(185, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [186] = PINGROUP(186, _, _, _, _, _, _, _, _, _, _, egpio), + [187] = PINGROUP(187, _, _, _, _, _, _, _, _, _, _, egpio), + [188] = PINGROUP(188, _, _, _, _, _, _, _, _, _, _, egpio), + [189] = PINGROUP(189, _, _, _, _, _, _, _, _, _, _, egpio), + [190] = PINGROUP(190, _, _, _, _, _, _, _, _, _, _, egpio), + [191] = PINGROUP(191, _, _, _, _, _, _, _, _, _, _, egpio), + [192] = PINGROUP(192, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [193] = PINGROUP(193, _, _, _, _, _, _, _, _, _, _, egpio), + [194] = PINGROUP(194, _, _, _, _, _, _, _, _, _, _, egpio), + [195] = PINGROUP(195, _, _, _, _, _, _, _, _, _, _, egpio), + [196] = PINGROUP(196, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [197] = PINGROUP(197, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [198] = PINGROUP(198, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [199] = PINGROUP(199, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [200] = PINGROUP(200, _, _, _, _, _, _, _, _, _, _, egpio), + [201] = PINGROUP(201, _, _, _, _, _, _, _, _, _, _, egpio), + [202] = PINGROUP(202, _, _, _, _, _, _, _, _, _, _, egpio), + [203] = PINGROUP(203, _, _, _, _, _, _, _, _, _, _, egpio), + [204] = PINGROUP(204, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [205] = PINGROUP(205, _, _, _, _, _, _, _, _, _, _, egpio), + [206] = PINGROUP(206, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [207] = PINGROUP(207, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [208] = PINGROUP(208, qup2_se4, _, phase_flag, _, _, _, _, _, _, _, egpio), + [209] = PINGROUP(209, qup2_se4, _, _, _, _, _, _, _, _, _, egpio), + [210] = PINGROUP(210, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [211] = PINGROUP(211, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [212] = PINGROUP(212, _, _, _, _, _, _, _, _, _, _, egpio), + [213] = PINGROUP(213, _, _, _, _, _, _, _, _, _, _, egpio), + [214] = PINGROUP(214, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [215] = PINGROUP(215, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [216] = PINGROUP(216, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [217] = UFS_RESET(ufs_reset, 0xe8004, 0xe9000), + [218] = SDC_QDSD_PINGROUP(sdc2_clk, 0xdd000, 14, 6), + [219] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xdd000, 11, 3), + [220] = SDC_QDSD_PINGROUP(sdc2_data, 0xdd000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map kaanapali_pdc_map[] = { + { 0, 89 }, { 3, 97 }, { 4, 90 }, { 7, 91 }, { 8, 92 }, { 11, 93 }, + { 12, 101 }, { 15, 115 }, { 17, 125 }, { 18, 127 }, { 19, 96 }, { 23, 99 }, + { 24, 100 }, { 27, 102 }, { 28, 103 }, { 31, 111 }, { 32, 109 }, { 35, 85 }, + { 36, 110 }, { 39, 112 }, { 43, 113 }, { 47, 138 }, { 48, 114 }, { 51, 98 }, + { 55, 88 }, { 57, 120 }, { 59, 121 }, { 60, 122 }, { 63, 108 }, { 64, 94 }, + { 65, 107 }, { 67, 116 }, { 68, 129 }, { 69, 130 }, { 75, 135 }, { 77, 123 }, + { 78, 119 }, { 79, 131 }, { 80, 139 }, { 81, 132 }, { 84, 118 }, { 85, 133 }, + { 86, 140 }, { 87, 141 }, { 88, 142 }, { 95, 143 }, { 96, 144 }, { 97, 117 }, + { 98, 134 }, { 99, 95 }, { 101, 145 }, { 102, 146 }, { 103, 147 }, { 104, 148 }, + { 120, 149 }, { 125, 150 }, { 129, 137 }, { 133, 84 }, { 144, 151 }, { 146, 152 }, + { 151, 153 }, { 152, 154 }, { 155, 106 }, { 158, 104 }, { 162, 126 }, { 164, 155 }, + { 167, 156 }, { 169, 157 }, { 170, 158 }, { 172, 159 }, { 174, 160 }, { 175, 161 }, + { 179, 162 }, { 180, 163 }, { 183, 164 }, { 186, 165 }, { 188, 128 }, { 189, 166 }, + { 190, 105 }, { 191, 167 }, { 194, 168 }, { 195, 169 }, { 196, 170 }, { 197, 171 }, + { 199, 136 }, { 200, 86 }, { 201, 172 }, { 202, 173 }, { 203, 174 }, { 205, 124 }, + { 209, 175 }, { 213, 87 }, { 216, 176 }, +}; + +static const struct msm_pinctrl_soc_data kaanapali_tlmm = { + .pins = kaanapali_pins, + .npins = ARRAY_SIZE(kaanapali_pins), + .functions = kaanapali_functions, + .nfunctions = ARRAY_SIZE(kaanapali_functions), + .groups = kaanapali_groups, + .ngroups = ARRAY_SIZE(kaanapali_groups), + .ngpios = 218, + .wakeirq_map = kaanapali_pdc_map, + .nwakeirq_map = ARRAY_SIZE(kaanapali_pdc_map), + .egpio_func = 11, +}; + +static int kaanapali_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &kaanapali_tlmm); +} + +static const struct of_device_id kaanapali_tlmm_of_match[] = { + { .compatible = "qcom,kaanapali-tlmm",}, + {}, +}; + +static struct platform_driver kaanapali_tlmm_driver = { + .driver = { + .name = "kaanapali-tlmm", + .of_match_table = kaanapali_tlmm_of_match, + }, + .probe = kaanapali_tlmm_probe, +}; + +static int __init kaanapali_tlmm_init(void) +{ + return platform_driver_register(&kaanapali_tlmm_driver); +} +arch_initcall(kaanapali_tlmm_init); + +static void __exit kaanapali_tlmm_exit(void) +{ + platform_driver_unregister(&kaanapali_tlmm_driver); +} +module_exit(kaanapali_tlmm_exit); + +MODULE_DESCRIPTION("QTI Kaanapali TLMM driver"); +MODULE_LICENSE("GPL"); +MODULE_DEVICE_TABLE(of, kaanapali_tlmm_of_match); From f919466878611065afb0b79feb28969af766ef3f Mon Sep 17 00:00:00 2001 From: Alexey Klimov Date: Tue, 7 Oct 2025 03:03:29 +0100 Subject: [PATCH 020/107] dt-bindings: pinctrl: qcom,sm6115-lpass-lpi: add QCM2290 compatible Add a compatible for the LPASS LPI pin controller on QCM2290. It seems to be compatible with sm6115 LPASS pinctrl. Cc: Konrad Dybcio Cc: Srinivas Kandagatla Acked-by: Rob Herring (Arm) Signed-off-by: Alexey Klimov Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml index f4cf2ce86fcd..ec1cd684753a 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml @@ -16,7 +16,13 @@ description: properties: compatible: - const: qcom,sm6115-lpass-lpi-pinctrl + oneOf: + - enum: + - qcom,sm6115-lpass-lpi-pinctrl + - items: + - enum: + - qcom,qcm2290-lpass-lpi-pinctrl + - const: qcom,sm6115-lpass-lpi-pinctrl reg: items: From 005a325480f418447949f43ace24a09a1fad5f09 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 7 Oct 2025 15:18:50 +0200 Subject: [PATCH 021/107] pinctrl: Demote subsystem banner message There is no reason to print any "hello world" from pin control unless (maybe) if we are debugging. Drop the banner. Reviewed-by: Bartosz Golaszewski Signed-off-by: Linus Walleij --- drivers/pinctrl/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index c5dbf4e9db84..157510157d47 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -2416,7 +2416,7 @@ EXPORT_SYMBOL_GPL(devm_pinctrl_unregister); static int __init pinctrl_init(void) { - pr_info("initialized pinctrl subsystem\n"); + pr_debug("initialized pinctrl subsystem\n"); pinctrl_init_debugfs(); return 0; } From 44bf66122c12ef6d3382a9b84b9be1802e5f0e95 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Fri, 12 Sep 2025 12:53:08 +0300 Subject: [PATCH 022/107] pinctrl: renesas: rzg2l: Fix ISEL restore on resume Commit 1d2da79708cb ("pinctrl: renesas: rzg2l: Avoid configuring ISEL in gpio_irq_{en,dis}able*()") dropped the configuration of ISEL from struct irq_chip::{irq_enable, irq_disable} APIs and moved it to struct gpio_chip::irq::{child_to_parent_hwirq, child_irq_domain_ops::free} APIs to fix spurious IRQs. After commit 1d2da79708cb ("pinctrl: renesas: rzg2l: Avoid configuring ISEL in gpio_irq_{en,dis}able*()"), ISEL was no longer configured properly on resume. This is because the pinctrl resume code used struct irq_chip::irq_enable (called from rzg2l_gpio_irq_restore()) to reconfigure the wakeup interrupts. Some drivers (e.g. Ethernet) may also reconfigure non-wakeup interrupts on resume through their own code, eventually calling struct irq_chip::irq_enable. Fix this by adding ISEL configuration back into the struct irq_chip::irq_enable API and on resume path for wakeup interrupts. As struct irq_chip::irq_enable needs now to lock to update the ISEL, convert the struct rzg2l_pinctrl::lock to a raw spinlock and replace the locking API calls with the raw variants. Otherwise the lockdep reports invalid wait context when probing the adv7511 module on RZ/G2L: [ BUG: Invalid wait context ] 6.17.0-rc5-next-20250911-00001-gfcfac22533c9 #18 Not tainted ----------------------------- (udev-worker)/165 is trying to lock: ffff00000e3664a8 (&pctrl->lock){....}-{3:3}, at: rzg2l_gpio_irq_enable+0x38/0x78 other info that might help us debug this: context-{5:5} 3 locks held by (udev-worker)/165: #0: ffff00000e890108 (&dev->mutex){....}-{4:4}, at: __driver_attach+0x90/0x1ac #1: ffff000011c07240 (request_class){+.+.}-{4:4}, at: __setup_irq+0xb4/0x6dc #2: ffff000011c070c8 (lock_class){....}-{2:2}, at: __setup_irq+0xdc/0x6dc stack backtrace: CPU: 1 UID: 0 PID: 165 Comm: (udev-worker) Not tainted 6.17.0-rc5-next-20250911-00001-gfcfac22533c9 #18 PREEMPT Hardware name: Renesas SMARC EVK based on r9a07g044l2 (DT) Call trace: show_stack+0x18/0x24 (C) dump_stack_lvl+0x90/0xd0 dump_stack+0x18/0x24 __lock_acquire+0xa14/0x20b4 lock_acquire+0x1c8/0x354 _raw_spin_lock_irqsave+0x60/0x88 rzg2l_gpio_irq_enable+0x38/0x78 irq_enable+0x40/0x8c __irq_startup+0x78/0xa4 irq_startup+0x108/0x16c __setup_irq+0x3c0/0x6dc request_threaded_irq+0xec/0x1ac devm_request_threaded_irq+0x80/0x134 adv7511_probe+0x928/0x9a4 [adv7511] i2c_device_probe+0x22c/0x3dc really_probe+0xbc/0x2a0 __driver_probe_device+0x78/0x12c driver_probe_device+0x40/0x164 __driver_attach+0x9c/0x1ac bus_for_each_dev+0x74/0xd0 driver_attach+0x24/0x30 bus_add_driver+0xe4/0x208 driver_register+0x60/0x128 i2c_register_driver+0x48/0xd0 adv7511_init+0x5c/0x1000 [adv7511] do_one_initcall+0x64/0x30c do_init_module+0x58/0x23c load_module+0x1bcc/0x1d40 init_module_from_file+0x88/0xc4 idempotent_init_module+0x188/0x27c __arm64_sys_finit_module+0x68/0xac invoke_syscall+0x48/0x110 el0_svc_common.constprop.0+0xc0/0xe0 do_el0_svc+0x1c/0x28 el0_svc+0x4c/0x160 el0t_64_sync_handler+0xa0/0xe4 el0t_64_sync+0x198/0x19c Having ISEL configuration back into the struct irq_chip::irq_enable API should be safe with respect to spurious IRQs, as in the probe case IRQs are enabled anyway in struct gpio_chip::irq::child_to_parent_hwirq. No spurious IRQs were detected on suspend/resume, boot, ethernet link insert/remove tests (executed on RZ/G3S). Boot, ethernet link insert/remove tests were also executed successfully on RZ/G2L. Fixes: 1d2da79708cb ("pinctrl: renesas: rzg2l: Avoid configuring ISEL in gpio_irq_{en,dis}able*(") Cc: stable@vger.kernel.org Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20250912095308.3603704-1-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 71 +++++++++++++++---------- 1 file changed, 44 insertions(+), 27 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index f524af6f586f..c360e473488c 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -359,7 +359,7 @@ struct rzg2l_pinctrl { spinlock_t bitmap_lock; /* protect tint_slot bitmap */ unsigned int hwirq[RZG2L_TINT_MAX_INTERRUPT]; - spinlock_t lock; /* lock read/write registers */ + raw_spinlock_t lock; /* lock read/write registers */ struct mutex mutex; /* serialize adding groups and functions */ struct rzg2l_pinctrl_pin_settings *settings; @@ -543,7 +543,7 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, unsigned long flags; u32 reg; - spin_lock_irqsave(&pctrl->lock, flags); + raw_spin_lock_irqsave(&pctrl->lock, flags); /* Set pin to 'Non-use (Hi-Z input protection)' */ reg = readw(pctrl->base + PM(off)); @@ -567,7 +567,7 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, pctrl->data->pwpr_pfc_lock_unlock(pctrl, true); - spin_unlock_irqrestore(&pctrl->lock, flags); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); }; static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, @@ -882,10 +882,10 @@ static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, addr += 4; } - spin_lock_irqsave(&pctrl->lock, flags); + raw_spin_lock_irqsave(&pctrl->lock, flags); reg = readl(addr) & ~(mask << (bit * 8)); writel(reg | (val << (bit * 8)), addr); - spin_unlock_irqrestore(&pctrl->lock, flags); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); } static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, u32 caps) @@ -1121,7 +1121,7 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oe if (bit < 0) return -EINVAL; - spin_lock_irqsave(&pctrl->lock, flags); + raw_spin_lock_irqsave(&pctrl->lock, flags); val = readb(pctrl->base + oen_offset); if (oen) val &= ~BIT(bit); @@ -1134,7 +1134,7 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oe writeb(val, pctrl->base + oen_offset); if (pctrl->data->hwcfg->oen_pwpr_lock) writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr); - spin_unlock_irqrestore(&pctrl->lock, flags); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); return 0; } @@ -1687,14 +1687,14 @@ static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset) if (ret) return ret; - spin_lock_irqsave(&pctrl->lock, flags); + raw_spin_lock_irqsave(&pctrl->lock, flags); /* Select GPIO mode in PMC Register */ reg8 = readb(pctrl->base + PMC(off)); reg8 &= ~BIT(bit); pctrl->data->pmc_writeb(pctrl, reg8, PMC(off)); - spin_unlock_irqrestore(&pctrl->lock, flags); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); return 0; } @@ -1709,7 +1709,7 @@ static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 offset, unsigned long flags; u16 reg16; - spin_lock_irqsave(&pctrl->lock, flags); + raw_spin_lock_irqsave(&pctrl->lock, flags); reg16 = readw(pctrl->base + PM(off)); reg16 &= ~(PM_MASK << (bit * 2)); @@ -1717,7 +1717,7 @@ static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 offset, reg16 |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2); writew(reg16, pctrl->base + PM(off)); - spin_unlock_irqrestore(&pctrl->lock, flags); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); } static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) @@ -1761,7 +1761,7 @@ static int rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset, unsigned long flags; u8 reg8; - spin_lock_irqsave(&pctrl->lock, flags); + raw_spin_lock_irqsave(&pctrl->lock, flags); reg8 = readb(pctrl->base + P(off)); @@ -1770,7 +1770,7 @@ static int rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset, else writeb(reg8 & ~BIT(bit), pctrl->base + P(off)); - spin_unlock_irqrestore(&pctrl->lock, flags); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); return 0; } @@ -2429,14 +2429,13 @@ static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl return gpioint; } -static void rzg2l_gpio_irq_endisable(struct rzg2l_pinctrl *pctrl, - unsigned int hwirq, bool enable) +static void __rzg2l_gpio_irq_endisable(struct rzg2l_pinctrl *pctrl, + unsigned int hwirq, bool enable) { const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; u64 *pin_data = pin_desc->drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq); - unsigned long flags; void __iomem *addr; addr = pctrl->base + ISEL(off); @@ -2445,12 +2444,20 @@ static void rzg2l_gpio_irq_endisable(struct rzg2l_pinctrl *pctrl, addr += 4; } - spin_lock_irqsave(&pctrl->lock, flags); if (enable) writel(readl(addr) | BIT(bit * 8), addr); else writel(readl(addr) & ~BIT(bit * 8), addr); - spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static void rzg2l_gpio_irq_endisable(struct rzg2l_pinctrl *pctrl, + unsigned int hwirq, bool enable) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&pctrl->lock, flags); + __rzg2l_gpio_irq_endisable(pctrl, hwirq, enable); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); } static void rzg2l_gpio_irq_disable(struct irq_data *d) @@ -2462,15 +2469,25 @@ static void rzg2l_gpio_irq_disable(struct irq_data *d) gpiochip_disable_irq(gc, hwirq); } -static void rzg2l_gpio_irq_enable(struct irq_data *d) +static void __rzg2l_gpio_irq_enable(struct irq_data *d, bool lock) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); unsigned int hwirq = irqd_to_hwirq(d); gpiochip_enable_irq(gc, hwirq); + if (lock) + rzg2l_gpio_irq_endisable(pctrl, hwirq, true); + else + __rzg2l_gpio_irq_endisable(pctrl, hwirq, true); irq_chip_enable_parent(d); } +static void rzg2l_gpio_irq_enable(struct irq_data *d) +{ + __rzg2l_gpio_irq_enable(d, true); +} + static int rzg2l_gpio_irq_set_type(struct irq_data *d, unsigned int type) { return irq_chip_set_type_parent(d, type); @@ -2616,11 +2633,11 @@ static void rzg2l_gpio_irq_restore(struct rzg2l_pinctrl *pctrl) * This has to be atomically executed to protect against a concurrent * interrupt. */ - spin_lock_irqsave(&pctrl->lock, flags); + raw_spin_lock_irqsave(&pctrl->lock, flags); ret = rzg2l_gpio_irq_set_type(data, irqd_get_trigger_type(data)); if (!ret && !irqd_irq_disabled(data)) - rzg2l_gpio_irq_enable(data); - spin_unlock_irqrestore(&pctrl->lock, flags); + __rzg2l_gpio_irq_enable(data, false); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); if (ret) dev_crit(pctrl->dev, "Failed to set IRQ type for virq=%u\n", virq); @@ -2950,7 +2967,7 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) "failed to enable GPIO clk\n"); } - spin_lock_init(&pctrl->lock); + raw_spin_lock_init(&pctrl->lock); spin_lock_init(&pctrl->bitmap_lock); mutex_init(&pctrl->mutex); atomic_set(&pctrl->wakeup_path, 0); @@ -3093,7 +3110,7 @@ static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl) u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; unsigned long flags; - spin_lock_irqsave(&pctrl->lock, flags); + raw_spin_lock_irqsave(&pctrl->lock, flags); pctrl->data->pwpr_pfc_lock_unlock(pctrl, false); /* Restore port registers. */ @@ -3138,7 +3155,7 @@ static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl) } pctrl->data->pwpr_pfc_lock_unlock(pctrl, true); - spin_unlock_irqrestore(&pctrl->lock, flags); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); } static int rzg2l_pinctrl_suspend_noirq(struct device *dev) @@ -3187,14 +3204,14 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev) writeb(cache->qspi, pctrl->base + QSPI); if (pctrl->data->hwcfg->oen_pwpr_lock) { - spin_lock_irqsave(&pctrl->lock, flags); + raw_spin_lock_irqsave(&pctrl->lock, flags); pwpr = readb(pctrl->base + regs->pwpr); writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr); } writeb(cache->oen, pctrl->base + pctrl->data->hwcfg->regs.oen); if (pctrl->data->hwcfg->oen_pwpr_lock) { writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr); - spin_unlock_irqrestore(&pctrl->lock, flags); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); } for (u8 i = 0; i < 2; i++) { if (regs->sd_ch) From fb8a7900dcba3764902ff9f0b3824f8818b3f4df Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 9 Sep 2025 11:42:44 +0100 Subject: [PATCH 023/107] pinctrl: renesas: rzg2l: Drop unnecessary pin configurations There is no need to reconfigure a pin if the pin's configuration values are the same as the reset values. E.g. the PS0 pin configuration for the NMI function is PMC = 1 and PFC = 0, which is the same as the reset values. Currently the code is first setting it to GPIO HI-Z state and then again reconfiguring to the NMI function, leading to spurious IRQs. Fix this by dropping unnecessary pin configuration from the driver. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20250909104247.3309-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index c360e473488c..efb406046f1a 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -541,9 +541,16 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, u8 pin, u8 off, u8 func) { unsigned long flags; - u32 reg; + u32 reg, pfc; + /* Switching to GPIO is not required if reset value is same as func */ raw_spin_lock_irqsave(&pctrl->lock, flags); + reg = readb(pctrl->base + PMC(off)); + pfc = readl(pctrl->base + PFC(off)); + if ((reg & BIT(pin)) && (((pfc >> (pin * 4)) & PFC_MASK) == func)) { + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + return; + } /* Set pin to 'Non-use (Hi-Z input protection)' */ reg = readw(pctrl->base + PM(off)); @@ -557,9 +564,8 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, writeb(reg & ~BIT(pin), pctrl->base + PMC(off)); /* Select Pin function mode with PFC register */ - reg = readl(pctrl->base + PFC(off)); - reg &= ~(PFC_MASK << (pin * 4)); - writel(reg | (func << (pin * 4)), pctrl->base + PFC(off)); + pfc &= ~(PFC_MASK << (pin * 4)); + writel(pfc | (func << (pin * 4)), pctrl->base + PFC(off)); /* Switch to Peripheral pin function with PMC register */ reg = readb(pctrl->base + PMC(off)); @@ -3130,11 +3136,18 @@ static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl) pm = readw(pctrl->base + PM(off)); for_each_set_bit(pin, &pinmap, max_pin) { struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; + u32 pfc_val, pfc_mask; /* Nothing to do if PFC was not configured before. */ if (!(cache->pmc[port] & BIT(pin))) continue; + pfc_val = readl(pctrl->base + PFC(off)); + pfc_mask = PFC_MASK << (pin * 4); + /* Nothing to do if reset value of the pin is same as cached value */ + if ((cache->pfc[port] & pfc_mask) == (pfc_val & pfc_mask)) + continue; + /* Set pin to 'Non-use (Hi-Z input protection)' */ pm &= ~(PM_MASK << (pin * 2)); writew(pm, pctrl->base + PM(off)); @@ -3144,8 +3157,8 @@ static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl) writeb(pmc, pctrl->base + PMC(off)); /* Select Pin function mode. */ - pfc &= ~(PFC_MASK << (pin * 4)); - pfc |= (cache->pfc[port] & (PFC_MASK << (pin * 4))); + pfc &= ~pfc_mask; + pfc |= (cache->pfc[port] & pfc_mask); writel(pfc, pctrl->base + PFC(off)); /* Switch to Peripheral pin function. */ From fea997df95fc43521a42851721a62e7c74dcacee Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 18 Sep 2025 22:04:01 +0200 Subject: [PATCH 024/107] pinctrl: renesas: Drop duplicate newlines Remove duplicate newlines. No functional change. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20250918200409.37284-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pfc-emev2.c | 1 - drivers/pinctrl/renesas/pfc-r8a73a4.c | 2 -- drivers/pinctrl/renesas/pfc-r8a7778.c | 1 - drivers/pinctrl/renesas/pfc-r8a77951.c | 1 - drivers/pinctrl/renesas/pfc-r8a7796.c | 1 - drivers/pinctrl/renesas/pfc-r8a77965.c | 1 - drivers/pinctrl/renesas/pfc-r8a77970.c | 1 - drivers/pinctrl/renesas/pfc-r8a77980.c | 1 - drivers/pinctrl/renesas/pfc-r8a77995.c | 2 -- drivers/pinctrl/renesas/pfc-r8a779f0.c | 1 - drivers/pinctrl/renesas/pfc-r8a779h0.c | 1 - drivers/pinctrl/renesas/pfc-sh7723.c | 1 - drivers/pinctrl/renesas/pfc-sh7724.c | 1 - drivers/pinctrl/renesas/pfc-sh7734.c | 1 - drivers/pinctrl/renesas/pinctrl-rza1.c | 1 - 15 files changed, 17 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-emev2.c b/drivers/pinctrl/renesas/pfc-emev2.c index 86d18b03668e..eee23ac87076 100644 --- a/drivers/pinctrl/renesas/pfc-emev2.c +++ b/drivers/pinctrl/renesas/pfc-emev2.c @@ -666,7 +666,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_NOFN(UART_1_0_PORT158, UART2_TX, SEL_UART_1_0_01), }; - #define EMEV_MUX_PIN(name, pin, mark) \ static const unsigned int name##_pins[] = { pin }; \ static const unsigned int name##_mux[] = { mark##_MARK } diff --git a/drivers/pinctrl/renesas/pfc-r8a73a4.c b/drivers/pinctrl/renesas/pfc-r8a73a4.c index be0a4914eab3..1b00765192f5 100644 --- a/drivers/pinctrl/renesas/pfc-r8a73a4.c +++ b/drivers/pinctrl/renesas/pfc-r8a73a4.c @@ -85,7 +85,6 @@ /* Port320 - Port329 */ \ PORT_10(320, fn, pfx##32, sfx) - enum { PINMUX_RESERVED = 0, @@ -227,7 +226,6 @@ enum { PINMUX_MARK_BEGIN, - #define F1(a) a##_MARK #define F2(a) a##_MARK #define F3(a) a##_MARK diff --git a/drivers/pinctrl/renesas/pfc-r8a7778.c b/drivers/pinctrl/renesas/pfc-r8a7778.c index db92d6d91d8e..4611e864ba69 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7778.c +++ b/drivers/pinctrl/renesas/pfc-r8a7778.c @@ -1994,7 +1994,6 @@ static const char * const scif5_groups[] = { "scif5_data_b", }; - static const char * const sdhi0_groups[] = { "sdhi0_cd", "sdhi0_ctrl", diff --git a/drivers/pinctrl/renesas/pfc-r8a77951.c b/drivers/pinctrl/renesas/pfc-r8a77951.c index a1d74f61fd8c..4b04cb9134b6 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77951.c +++ b/drivers/pinctrl/renesas/pfc-r8a77951.c @@ -249,7 +249,6 @@ #define GPSR7_1 FM(AVS2) #define GPSR7_0 FM(AVS1) - /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c index 807834f319f0..aead3b1173c9 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7796.c +++ b/drivers/pinctrl/renesas/pfc-r8a7796.c @@ -254,7 +254,6 @@ #define GPSR7_1 FM(AVS2) #define GPSR7_0 FM(AVS1) - /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c index e7c88a5d983f..22640cfe9e32 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77965.c +++ b/drivers/pinctrl/renesas/pfc-r8a77965.c @@ -254,7 +254,6 @@ #define GPSR7_1 FM(AVS2) #define GPSR7_0 FM(AVS1) - /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) diff --git a/drivers/pinctrl/renesas/pfc-r8a77970.c b/drivers/pinctrl/renesas/pfc-r8a77970.c index e1b3e3b38ec3..972b14ab2359 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77970.c +++ b/drivers/pinctrl/renesas/pfc-r8a77970.c @@ -159,7 +159,6 @@ #define GPSR5_1 FM(QSPI0_MOSI_IO0) #define GPSR5_0 FM(QSPI0_SPCLK) - /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ #define IP0_3_0 FM(DU_DR2) FM(HSCK0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_7_4 FM(DU_DR3) FM(HRTS0_N) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) diff --git a/drivers/pinctrl/renesas/pfc-r8a77980.c b/drivers/pinctrl/renesas/pfc-r8a77980.c index 877134d78c7e..53b44b24bfc6 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77980.c +++ b/drivers/pinctrl/renesas/pfc-r8a77980.c @@ -193,7 +193,6 @@ #define GPSR5_1 FM(QSPI0_MOSI_IO0) #define GPSR5_0 FM(QSPI0_SPCLK) - /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ #define IP0_3_0 FM(DU_DR2) FM(SCK4) FM(GETHER_RMII_CRS_DV) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_7_4 FM(DU_DR3) FM(RX4) FM(GETHER_RMII_RX_ER) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) diff --git a/drivers/pinctrl/renesas/pfc-r8a77995.c b/drivers/pinctrl/renesas/pfc-r8a77995.c index 298e7a07e493..b35c62f9a061 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77995.c +++ b/drivers/pinctrl/renesas/pfc-r8a77995.c @@ -427,7 +427,6 @@ FM(IP12_31_28) IP12_31_28 \ #define MOD_SEL1_27 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1) #define MOD_SEL1_26 FM(SEL_SSIF4_0) FM(SEL_SSIF4_1) - #define PINMUX_MOD_SELS \ \ MOD_SEL1_31 \ @@ -2869,7 +2868,6 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ } }; - static int r8a77995_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { switch (pin) { diff --git a/drivers/pinctrl/renesas/pfc-r8a779f0.c b/drivers/pinctrl/renesas/pfc-r8a779f0.c index 16e722a4d18f..46ca28fb2d51 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779f0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779f0.c @@ -652,7 +652,6 @@ static const unsigned int i2c5_mux[] = { SDA5_MARK, SCL5_MARK, }; - /* - INTC-EX ---------------------------------------------------------------- */ static const unsigned int intc_ex_irq0_pins[] = { /* IRQ0 */ diff --git a/drivers/pinctrl/renesas/pfc-r8a779h0.c b/drivers/pinctrl/renesas/pfc-r8a779h0.c index 48b1eef250d9..63b3725a0cf6 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779h0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779h0.c @@ -259,7 +259,6 @@ #define GPSR7_1 F_(AVB0_AVTP_CAPTURE, IP0SR7_7_4) #define GPSR7_0 F_(AVB0_AVTP_PPS, IP0SR7_3_0) - /* SR0 */ /* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ #define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC_N_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) diff --git a/drivers/pinctrl/renesas/pfc-sh7723.c b/drivers/pinctrl/renesas/pfc-sh7723.c index c1abdec9bf1d..bdf555e63c2e 100644 --- a/drivers/pinctrl/renesas/pfc-sh7723.c +++ b/drivers/pinctrl/renesas/pfc-sh7723.c @@ -182,7 +182,6 @@ enum { PTZ7_FN, PTZ6_FN, PTZ5_FN, PTZ4_FN, PTZ3_FN, PTZ2_FN, PTZ1_FN, PTZ0_FN, - PSA15_PSA14_FN1, PSA15_PSA14_FN2, PSA13_PSA12_FN1, PSA13_PSA12_FN2, PSA11_PSA10_FN1, PSA11_PSA10_FN2, diff --git a/drivers/pinctrl/renesas/pfc-sh7724.c b/drivers/pinctrl/renesas/pfc-sh7724.c index 5148a3460cc6..4e8c1fae7be6 100644 --- a/drivers/pinctrl/renesas/pfc-sh7724.c +++ b/drivers/pinctrl/renesas/pfc-sh7724.c @@ -210,7 +210,6 @@ enum { PTZ7_FN, PTZ6_FN, PTZ5_FN, PTZ4_FN, PTZ3_FN, PTZ2_FN, PTZ1_FN, PTZ0_FN, - PSA15_0, PSA15_1, PSA14_0, PSA14_1, PSA13_0, PSA13_1, diff --git a/drivers/pinctrl/renesas/pfc-sh7734.c b/drivers/pinctrl/renesas/pfc-sh7734.c index a0a5d8b94086..df2de853df93 100644 --- a/drivers/pinctrl/renesas/pfc-sh7734.c +++ b/drivers/pinctrl/renesas/pfc-sh7734.c @@ -664,7 +664,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP0_31_30, LCD_DATA15_A, SEL_LCDC_0), PINMUX_IPSR_MSEL(IP0_31_30, TIOC3D_C, SEL_MTU2_CH3_1), - /* IPSR1 */ PINMUX_IPSR_GPSR(IP1_1_0, A16), PINMUX_IPSR_GPSR(IP1_1_0, ST0_PWM), diff --git a/drivers/pinctrl/renesas/pinctrl-rza1.c b/drivers/pinctrl/renesas/pinctrl-rza1.c index f24e5915cbe4..4c7326e3de07 100644 --- a/drivers/pinctrl/renesas/pinctrl-rza1.c +++ b/drivers/pinctrl/renesas/pinctrl-rza1.c @@ -526,7 +526,6 @@ static inline int rza1_pinmux_get_swio(unsigned int port, const struct rza1_swio_pin *swio_pin; unsigned int i; - for (i = 0; i < table->npins; ++i) { swio_pin = &table->pins[i]; if (swio_pin->port == port && swio_pin->pin == pin && From cea950101108b7bfffe26ec4007b8e263a4b56a8 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sun, 21 Sep 2025 12:15:52 +0100 Subject: [PATCH 025/107] pinctrl: renesas: rzg2l: Fix PMC restore PMC restore needs unlocking the register using the PWPR register. Fixes: ede014cd1ea6422d ("pinctrl: renesas: rzg2l: Add function pointer for PMC register write") Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20250921111557.103069-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index efb406046f1a..6c97df26bff4 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -3016,7 +3016,11 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen * Now cache the registers or set them in the order suggested by * HW manual (section "Operation for GPIO Function"). */ - RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + PMC(off), cache->pmc[port]); + if (suspend) + RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + PMC(off), cache->pmc[port]); + else + pctrl->data->pmc_writeb(pctrl, cache->pmc[port], PMC(off)); + if (has_iolh) { RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off), cache->iolh[0][port]); From 647a6b1808dbec19acaba29d512767b3d4d9cd71 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Tue, 23 Sep 2025 20:49:50 +0300 Subject: [PATCH 026/107] pinctrl: renesas: rzg2l: Remove extra semicolons Semicolons after end of function braces are unnecessary, remove them. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20250923174951.1136259-1-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 6c97df26bff4..947bce7bfc0e 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -574,7 +574,7 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, pctrl->data->pwpr_pfc_lock_unlock(pctrl, true); raw_spin_unlock_irqrestore(&pctrl->lock, flags); -}; +} static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, @@ -614,7 +614,7 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, } return 0; -}; +} static int rzg2l_map_add_config(struct pinctrl_map *map, const char *group_or_pin, @@ -1419,7 +1419,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, *config = pinconf_to_config_packed(param, arg); return 0; -}; +} static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, unsigned int _pin, @@ -1619,7 +1619,7 @@ static int rzg2l_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev, } return 0; -}; +} static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, unsigned int group, @@ -1646,7 +1646,7 @@ static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, } return 0; -}; +} static const struct pinctrl_ops rzg2l_pinctrl_pctlops = { .get_groups_count = pinctrl_generic_get_group_count, From bf48f99d95dfd664ddb7c4d69b182606f5ed8605 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 24 Sep 2025 14:47:52 +0200 Subject: [PATCH 027/107] pinctrl: renesas: Remove unneeded semicolons Semicolons after end of function braces are not needed, remove them. Signed-off-by: Geert Uytterhoeven Link: https://patch.msgid.link/99db8c1bfb64980b54a4b5c4988c7935609133e1.1758718027.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pinctrl-rzt2h.c | 4 ++-- drivers/pinctrl/renesas/pinctrl-rzv2m.c | 10 +++++----- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzt2h.c b/drivers/pinctrl/renesas/pinctrl-rzt2h.c index 3872638f5ebb..4826ff91cd90 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzt2h.c +++ b/drivers/pinctrl/renesas/pinctrl-rzt2h.c @@ -144,7 +144,7 @@ static void rzt2h_pinctrl_set_pfc_mode(struct rzt2h_pinctrl *pctrl, /* Switch to Peripheral pin function with PMC register */ reg16 = rzt2h_pinctrl_readb(pctrl, port, PMC(port)); rzt2h_pinctrl_writeb(pctrl, port, reg16 | BIT(pin), PMC(port)); -}; +} static int rzt2h_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, @@ -182,7 +182,7 @@ static int rzt2h_pinctrl_set_mux(struct pinctrl_dev *pctldev, } return 0; -}; +} static int rzt2h_map_add_config(struct pinctrl_map *map, const char *group_or_pin, diff --git a/drivers/pinctrl/renesas/pinctrl-rzv2m.c b/drivers/pinctrl/renesas/pinctrl-rzv2m.c index dce68f93d2d5..495e7f5d4128 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzv2m.c +++ b/drivers/pinctrl/renesas/pinctrl-rzv2m.c @@ -155,7 +155,7 @@ static void rzv2m_pinctrl_set_pfc_mode(struct rzv2m_pinctrl *pctrl, /* Unmask input/output */ rzv2m_writel_we(pctrl->base + EN_MSK(port), pin, 0); rzv2m_writel_we(pctrl->base + DI_MSK(port), pin, 0); -}; +} static int rzv2m_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, @@ -186,7 +186,7 @@ static int rzv2m_pinctrl_set_mux(struct pinctrl_dev *pctldev, } return 0; -}; +} static int rzv2m_map_add_config(struct pinctrl_map *map, const char *group_or_pin, @@ -551,7 +551,7 @@ static int rzv2m_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, *config = pinconf_to_config_packed(param, arg); return 0; -}; +} static int rzv2m_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, unsigned int _pin, @@ -689,7 +689,7 @@ static int rzv2m_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev, } return 0; -}; +} static int rzv2m_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, unsigned int group, @@ -716,7 +716,7 @@ static int rzv2m_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, } return 0; -}; +} static const struct pinctrl_ops rzv2m_pinctrl_pctlops = { .get_groups_count = pinctrl_generic_get_group_count, From e1106d624cd72d7b526b2181ec9d30d431e6c559 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Wed, 8 Oct 2025 10:30:23 +0300 Subject: [PATCH 028/107] pinctrl: tegra20: register csus_mux clock Add csus_mux for further use as the csus clock parent, similar to how the cdev1 and cdev2 muxes are utilized. Additionally, constify the cdev parent name lists to resolve checkpatch warnings. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen Signed-off-by: Linus Walleij --- drivers/pinctrl/tegra/pinctrl-tegra20.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/tegra/pinctrl-tegra20.c b/drivers/pinctrl/tegra/pinctrl-tegra20.c index 737fc2000f66..1a1758fd7def 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra20.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra20.c @@ -2222,14 +2222,18 @@ static const struct tegra_pinctrl_soc_data tegra20_pinctrl = { .drvtype_in_mux = false, }; -static const char *cdev1_parents[] = { +static const char * const cdev1_parents[] = { "dev1_osc_div", "pll_a_out0", "pll_m_out1", "audio", }; -static const char *cdev2_parents[] = { +static const char * const cdev2_parents[] = { "dev2_osc_div", "hclk", "pclk", "pll_p_out4", }; +static const char * const csus_parents[] = { + "pll_c_out1", "pll_p_out2", "pll_p_out3", "vi_sensor", +}; + static void tegra20_pinctrl_register_clock_muxes(struct platform_device *pdev) { struct tegra_pmx *pmx = platform_get_drvdata(pdev); @@ -2239,6 +2243,9 @@ static void tegra20_pinctrl_register_clock_muxes(struct platform_device *pdev) clk_register_mux(NULL, "cdev2_mux", cdev2_parents, 4, 0, pmx->regs[1] + 0x8, 4, 2, CLK_MUX_READ_ONLY, NULL); + + clk_register_mux(NULL, "csus_mux", csus_parents, 4, 0, + pmx->regs[1] + 0x8, 6, 2, CLK_MUX_READ_ONLY, NULL); } static int tegra20_pinctrl_probe(struct platform_device *pdev) From 8c10adaf337fb24a9f43dd08c37476da26d0be5d Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Mon, 13 Oct 2025 14:12:05 -0500 Subject: [PATCH 029/107] dt-bindings: pinctrl: Convert actions,s700-pinctrl to DT schema Convert the actions,s700-pinctrl binding to DT schema format. It's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) Acked-by: Manivannan Sadhasivam Signed-off-by: Linus Walleij --- .../bindings/pinctrl/actions,s700-pinctrl.txt | 170 --------------- .../pinctrl/actions,s700-pinctrl.yaml | 204 ++++++++++++++++++ 2 files changed, 204 insertions(+), 170 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/actions,s700-pinctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/actions,s700-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/actions,s700-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/actions,s700-pinctrl.txt deleted file mode 100644 index d13ff82f8518..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/actions,s700-pinctrl.txt +++ /dev/null @@ -1,170 +0,0 @@ -Actions Semi S700 Pin Controller - -This binding describes the pin controller found in the S700 SoC. - -Required Properties: - -- compatible: Should be "actions,s700-pinctrl" -- reg: Should contain the register base address and size of - the pin controller. -- clocks: phandle of the clock feeding the pin controller -- gpio-controller: Marks the device node as a GPIO controller. -- gpio-ranges: Specifies the mapping between gpio controller and - pin-controller pins. -- #gpio-cells: Should be two. The first cell is the gpio pin number - and the second cell is used for optional parameters. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells: Specifies the number of cells needed to encode an - interrupt. Shall be set to 2. The first cell - defines the interrupt number, the second encodes - the trigger flags described in - bindings/interrupt-controller/interrupts.txt -- interrupts: The interrupt outputs from the controller. There is one GPIO - interrupt per GPIO bank. The number of interrupts listed depends - on the number of GPIO banks on the SoC. The interrupts must be - ordered by bank, starting with bank 0. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - -PIN CONFIGURATION NODES: - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - -Pinmux functions are available only for the pin groups while pinconf -parameters are available for both pin groups and individual pins. - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - -Required Properties: - -- pins: An array of strings, each string containing the name of a pin. - These pins are used for selecting the pull control and schmitt - trigger parameters. The following are the list of pins - available: - - eth_txd0, eth_txd1, eth_txd2, eth_txd3, eth_txen, eth_rxer, - eth_crs_dv, eth_rxd1, eth_rxd0, eth_rxd2, eth_rxd3, eth_ref_clk, - eth_mdc, eth_mdio, sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0, - i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1, - pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, ks_in0, ks_in1, ks_in2, - ks_in3, ks_out0, ks_out1, ks_out2, lvds_oep, lvds_oen, lvds_odp, - lvds_odn, lvds_ocp, lvds_ocn, lvds_obp, lvds_obn, lvds_oap, - lvds_oan, lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp, - lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean, lcd0_d18, - lcd0_d2, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, dsi_cn, - dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sd0_d0, sd0_d1, sd0_d2, - sd0_d3, sd1_d0, sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk, - sd1_cmd, sd1_clk, spi0_ss, spi0_miso, uart0_rx, uart0_tx, - uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb, uart3_rx, uart3_tx, - uart3_rtsb, uart3_ctsb, i2c0_sclk, i2c0_sdata, i2c1_sclk, - i2c1_sdata, i2c2_sdata, csi_dn0, csi_dp0, csi_dn1, csi_dp1, - csi_cn, csi_cp, csi_dn2, csi_dp2, csi_dn3, csi_dp3, - sensor0_pclk, sensor0_ckout, dnand_d0, dnand_d1, dnand_d2, - dnand_d3, dnand_d4, dnand_d5, dnand_d6, dnand_d7, dnand_wrb, - dnand_rdb, dnand_rdbn, dnand_dqs, dnand_dqsn, dnand_rb0, - dnand_ale, dnand_cle, dnand_ceb0, dnand_ceb1, dnand_ceb2, - dnand_ceb3, porb, clko_25m, bsel, pkg0, pkg1, pkg2, pkg3 - -- groups: An array of strings, each string containing the name of a pin - group. These pin groups are used for selecting the pinmux - functions. - rgmii_txd23_mfp, rgmii_rxd2_mfp, rgmii_rxd3_mfp, lcd0_d18_mfp, - rgmii_txd01_mfp, rgmii_txd0_mfp, rgmii_txd1_mfp, rgmii_txen_mfp, - rgmii_rxen_mfp, rgmii_rxd1_mfp, rgmii_rxd0_mfp, rgmii_ref_clk_mfp, - i2s_d0_mfp, i2s_pcm1_mfp, i2s0_pcm0_mfp, i2s1_pcm0_mfp, - i2s_d1_mfp, ks_in2_mfp, ks_in1_mfp, ks_in0_mfp, ks_in3_mfp, - ks_out0_mfp, ks_out1_mfp, ks_out2_mfp, lvds_o_pn_mfp, dsi_dn0_mfp, - dsi_dp2_mfp, lcd0_d2_mfp, dsi_dp3_mfp, dsi_dn3_mfp, dsi_dp0_mfp, - lvds_ee_pn_mfp, uart2_rx_tx_mfp, spi0_i2c_pcm_mfp, dsi_dnp1_cp_d2_mfp, - dsi_dnp1_cp_d17_mfp, lvds_e_pn_mfp, dsi_dn2_mfp, uart2_rtsb_mfp, - uart2_ctsb_mfp, uart3_rtsb_mfp, uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, - sd0_d2_d3_mfp, sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_mfp, - uart0_rx_mfp, clko_25m_mfp, csi_cn_cp_mfp, sens0_ckout_mfp, uart0_tx_mfp, - i2c0_mfp, csi_dn_dp_mfp, sen0_pclk_mfp, pcm1_in_mfp, pcm1_clk_mfp, - pcm1_sync_mfp, pcm1_out_mfp, dnand_data_wr_mfp, dnand_acle_ce0_mfp, - nand_ceb2_mfp, nand_ceb3_mfp - - These pin groups are used for selecting the drive strength - parameters. - - sirq_drv, rgmii_txd23_drv, rgmii_rxd23_drv, rgmii_txd01_txen_drv, - rgmii_rxer_drv, rgmii_crs_drv, rgmii_rxd10_drv, rgmii_ref_clk_drv, - smi_mdc_mdio_drv, i2s_d0_drv, i2s_bclk0_drv, i2s3_drv, i2s13_drv, - pcm1_drv, ks_in_drv, ks_out_drv, lvds_all_drv, lcd_d18_d2_drv, - dsi_all_drv, sd0_d0_d3_drv, sd0_cmd_drv, sd0_clk_drv, spi0_all_drv, - uart0_rx_drv, uart0_tx_drv, uart2_all_drv, i2c0_all_drv, i2c12_all_drv, - sens0_pclk_drv, sens0_ckout_drv, uart3_all_drv - -- function: An array of strings, each string containing the name of the - pinmux functions. These functions can only be selected by - the corresponding pin groups. The following are the list of - pinmux functions available: - - nor, eth_rgmii, eth_sgmii, spi0, spi1, spi2, spi3, seNs0, sens1, - uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1, - pcm1, pcm0, ks, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, p0, - sd0, sd1, sd2, i2c0, i2c1, i2c2, i2c3, dsi, lvds, usb30, - clko_25m, mipi_csi, nand, spdif, sirq0, sirq1, sirq2, bt, lcd0 - -Optional Properties: - -- bias-pull-down: No arguments. The specified pins should be configured as - pull down. -- bias-pull-up: No arguments. The specified pins should be configured as - pull up. -- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified - pins -- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified - pins -- drive-strength: Integer. Selects the drive strength for the specified - pins in mA. - Valid values are: - <2> - <4> - <8> - <12> - -Example: - - pinctrl: pinctrl@e01b0000 { - compatible = "actions,s700-pinctrl"; - reg = <0x0 0xe01b0000 0x0 0x1000>; - clocks = <&cmu CLK_GPIO>; - gpio-controller; - gpio-ranges = <&pinctrl 0 0 136>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - , - , - ; - - uart3-default: uart3-default { - pinmux { - groups = "uart3_rtsb_mfp", "uart3_ctsb_mfp"; - function = "uart3"; - }; - pinconf { - groups = "uart3_all_drv"; - drive-strength = <2>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/actions,s700-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/actions,s700-pinctrl.yaml new file mode 100644 index 000000000000..9597b983c332 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/actions,s700-pinctrl.yaml @@ -0,0 +1,204 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/actions,s700-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Actions Semi S700 Pin Controller + +maintainers: + - Manivannan Sadhasivam + +properties: + compatible: + const: actions,s700-pinctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + gpio-controller: true + + gpio-line-names: + maxItems: 136 + + gpio-ranges: true + + '#gpio-cells': + const: 2 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + maxItems: 5 + description: + The interrupt outputs from the controller. There is one GPIO interrupt per + GPIO bank. The interrupts must be ordered by bank, starting with + bank 0. + +additionalProperties: + type: object + description: Pin configuration subnode + additionalProperties: false + + properties: + pinmux: + description: Configure pin multiplexing. + type: object + $ref: /schemas/pinctrl/pinmux-node.yaml# + additionalProperties: false + + properties: + groups: + items: + enum: [ + rgmii_txd23_mfp, rgmii_rxd2_mfp, rgmii_rxd3_mfp, lcd0_d18_mfp, + rgmii_txd01_mfp, rgmii_txd0_mfp, rgmii_txd1_mfp, rgmii_txen_mfp, + rgmii_rxen_mfp, rgmii_rxd1_mfp, rgmii_rxd0_mfp, rgmii_ref_clk_mfp, + i2c1_dummy, i2c2_dummy, i2s_d0_mfp, i2s_pcm1_mfp, i2s0_pcm0_mfp, i2s1_pcm0_mfp, + i2s_d1_mfp, ks_in2_mfp, ks_in1_mfp, ks_in0_mfp, ks_in3_mfp, + ks_out0_mfp, ks_out1_mfp, ks_out2_mfp, lvds_o_pn_mfp, dsi_dn0_mfp, + dsi_dp2_mfp, lcd0_d2_mfp, dsi_dp3_mfp, dsi_dn3_mfp, dsi_dp0_mfp, + lvds_ee_pn_mfp, uart2_rx_tx_mfp, spi0_i2c_pcm_mfp, + dsi_dnp1_cp_d2_mfp, dsi_dnp1_cp_d17_mfp, lvds_e_pn_mfp, + dsi_dn2_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp, + uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp, + sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_mfp, + uart0_rx_mfp, clko_25m_mfp, csi_cn_cp_mfp, sens0_ckout_mfp, + uart0_tx_mfp, i2c0_mfp, csi_dn_dp_mfp, sen0_pclk_mfp, pcm1_in_mfp, + pcm1_clk_mfp, pcm1_sync_mfp, pcm1_out_mfp, dnand_data_wr_mfp, + dnand_acle_ce0_mfp, nand_ceb2_mfp, nand_ceb3_mfp + ] + + function: + items: + enum: [ + nor, eth_rgmii, eth_sgmii, spi0, spi1, spi2, spi3, seNs0, sens1, + uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1, pcm1, + pcm0, ks, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, p0, sd0, sd1, + sd2, i2c0, i2c1, i2c2, i2c3, dsi, lvds, usb30, clko_25m, mipi_csi, + nand, spdif, sirq0, sirq1, sirq2, bt, lcd0 + ] + + required: + - groups + - function + + pinconf: + description: Configure pin-specific parameters. + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml# + - $ref: /schemas/pinctrl/pinmux-node.yaml# + additionalProperties: false + + properties: + groups: + items: + enum: [ + sirq_drv, rgmii_txd23_drv, rgmii_rxd23_drv, rgmii_txd01_txen_drv, + rgmii_rxer_drv, rgmii_crs_drv, rgmii_rxd10_drv, rgmii_ref_clk_drv, + smi_mdc_mdio_drv, i2s_d0_drv, i2s_bclk0_drv, i2s3_drv, i2s13_drv, + pcm1_drv, ks_in_drv, ks_out_drv, lvds_all_drv, lcd_d18_d2_drv, + dsi_all_drv, sd0_d0_d3_drv, sd0_cmd_drv, sd0_clk_drv, + spi0_all_drv, uart0_rx_drv, uart0_tx_drv, uart2_all_drv, + i2c0_all_drv, i2c12_all_drv, sens0_pclk_drv, sens0_ckout_drv, + uart3_all_drv + ] + + pins: + items: + enum: [ + eth_txd0, eth_txd1, eth_txd2, eth_txd3, eth_txen, eth_rxer, + eth_crs_dv, eth_rxd1, eth_rxd0, eth_rxd2, eth_rxd3, eth_ref_clk, + eth_mdc, eth_mdio, sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0, + i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1, + pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, ks_in0, ks_in1, ks_in2, + ks_in3, ks_out0, ks_out1, ks_out2, lvds_oep, lvds_oen, lvds_odp, + lvds_odn, lvds_ocp, lvds_ocn, lvds_obp, lvds_obn, lvds_oap, + lvds_oan, lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp, + lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean, lcd0_d18, + lcd0_d2, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, dsi_cn, + dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sd0_d0, sd0_d1, sd0_d2, + sd0_d3, sd1_d0, sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, + sd1_clk, spi0_ss, spi0_miso, uart0_rx, uart0_tx, uart2_rx, + uart2_tx, uart2_rtsb, uart2_ctsb, uart3_rx, uart3_tx, uart3_rtsb, + uart3_ctsb, i2c0_sclk, i2c0_sdata, i2c1_sclk, i2c1_sdata, + i2c2_sclk, i2c2_sdata, csi_dn0, csi_dp0, csi_dn1, csi_dp1, csi_cn, csi_cp, + csi_dn2, csi_dp2, csi_dn3, csi_dp3, sensor0_pclk, sensor0_ckout, + dnand_d0, dnand_d1, dnand_d2, dnand_d3, dnand_d4, dnand_d5, + dnand_d6, dnand_d7, dnand_wrb, dnand_rdb, dnand_rdbn, dnand_dqs, + dnand_dqsn, dnand_rb0, dnand_ale, dnand_cle, dnand_ceb0, + dnand_ceb1, dnand_ceb2, dnand_ceb3, porb, clko_25m, bsel, pkg0, + pkg1, pkg2, pkg3 + ] + + bias-pull-down: + type: boolean + + bias-pull-up: + type: boolean + + drive-strength: + description: Selects the drive strength for the specified pins in mA. + enum: [2, 4, 8, 12] + + input-schmitt-enable: true + input-schmitt-disable: true + + oneOf: + - required: + - groups + - required: + - pins + + anyOf: + - required: [ pinmux ] + - required: [ pinconf ] + +required: + - compatible + - reg + - clocks + - gpio-controller + - gpio-ranges + - '#gpio-cells' + - interrupt-controller + - '#interrupt-cells' + - interrupts + +examples: + - | + #include + + pinctrl: pinctrl@e01b0000 { + compatible = "actions,s700-pinctrl"; + reg = <0xe01b0000 0x1000>; + clocks = <&cmu 1>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 136>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + , + , + ; + + uart3-default { + pinmux { + groups = "uart3_rtsb_mfp", "uart3_ctsb_mfp"; + function = "uart3"; + }; + pinconf { + groups = "uart3_all_drv"; + drive-strength = <2>; + }; + }; + }; From af1825d7668d98c6bb8dfd1abeb503ac6e0b449b Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Mon, 13 Oct 2025 14:12:16 -0500 Subject: [PATCH 030/107] dt-bindings: pinctrl: Convert actions,s900-pinctrl to DT schema Convert the actions,s900-pinctrl binding to DT schema format. It's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) Acked-by: Manivannan Sadhasivam Signed-off-by: Linus Walleij --- .../bindings/pinctrl/actions,s900-pinctrl.txt | 204 ---------------- .../pinctrl/actions,s900-pinctrl.yaml | 219 ++++++++++++++++++ 2 files changed, 219 insertions(+), 204 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt deleted file mode 100644 index 81b58dddd3ed..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt +++ /dev/null @@ -1,204 +0,0 @@ -Actions Semi S900 Pin Controller - -This binding describes the pin controller found in the S900 SoC. - -Required Properties: - -- compatible: Should be "actions,s900-pinctrl" -- reg: Should contain the register base address and size of - the pin controller. -- clocks: phandle of the clock feeding the pin controller -- gpio-controller: Marks the device node as a GPIO controller. -- gpio-ranges: Specifies the mapping between gpio controller and - pin-controller pins. -- #gpio-cells: Should be two. The first cell is the gpio pin number - and the second cell is used for optional parameters. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells: Specifies the number of cells needed to encode an - interrupt. Shall be set to 2. The first cell - defines the interrupt number, the second encodes - the trigger flags described in - bindings/interrupt-controller/interrupts.txt -- interrupts: The interrupt outputs from the controller. There is one GPIO - interrupt per GPIO bank. The number of interrupts listed depends - on the number of GPIO banks on the SoC. The interrupts must be - ordered by bank, starting with bank 0. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - -PIN CONFIGURATION NODES: - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - -Pinmux functions are available only for the pin groups while pinconf -parameters are available for both pin groups and individual pins. - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - -Required Properties: - -- pins: An array of strings, each string containing the name of a pin. - These pins are used for selecting the pull control and schmitt - trigger parameters. The following are the list of pins - available: - - eth_txd0, eth_txd1, eth_txen, eth_rxer, eth_crs_dv, - eth_rxd1, eth_rxd0, eth_ref_clk, eth_mdc, eth_mdio, - sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0, i2s_lrclk0, - i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1, - pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, eram_a5, - eram_a6, eram_a7, eram_a8, eram_a9, eram_a10, eram_a11, - lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp, - lvds_ocn, lvds_obp, lvds_obn, lvds_oap, lvds_oan, - lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp, - lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean, - sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0, sd1_d1, - sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk, - spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx, - uart0_tx, uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb, - uart3_rx, uart3_tx, uart3_rtsb, uart3_ctsb, uart4_rx, - uart4_tx, i2c0_sclk, i2c0_sdata, i2c1_sclk, i2c1_sdata, - i2c2_sclk, i2c2_sdata, csi0_dn0, csi0_dp0, csi0_dn1, - csi0_dp1, csi0_cn, csi0_cp, csi0_dn2, csi0_dp2, csi0_dn3, - csi0_dp3, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, - dsi_cn, dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sensor0_pclk, - csi1_dn0,csi1_dp0,csi1_dn1, csi1_dp1, csi1_cn, csi1_cp, - sensor0_ckout, nand0_d0, nand0_d1, nand0_d2, nand0_d3, - nand0_d4, nand0_d5, nand0_d6, nand0_d7, nand0_dqs, - nand0_dqsn, nand0_ale, nand0_cle, nand0_ceb0, nand0_ceb1, - nand0_ceb2, nand0_ceb3, nand1_d0, nand1_d1, nand1_d2, - nand1_d3, nand1_d4, nand1_d5, nand1_d6, nand1_d7, nand1_dqs, - nand1_dqsn, nand1_ale, nand1_cle, nand1_ceb0, nand1_ceb1, - nand1_ceb2, nand1_ceb3, sgpio0, sgpio1, sgpio2, sgpio3 - -- groups: An array of strings, each string containing the name of a pin - group. These pin groups are used for selecting the pinmux - functions. - - lvds_oxx_uart4_mfp, rmii_mdc_mfp, rmii_mdio_mfp, sirq0_mfp, - sirq1_mfp, rmii_txd0_mfp, rmii_txd1_mfp, rmii_txen_mfp, - rmii_rxer_mfp, rmii_crs_dv_mfp, rmii_rxd1_mfp, rmii_rxd0_mfp, - rmii_ref_clk_mfp, i2s_d0_mfp, i2s_d1_mfp, i2s_lr_m_clk0_mfp, - i2s_bclk0_mfp, i2s_bclk1_mclk1_mfp, pcm1_in_out_mfp, - pcm1_clk_mfp, pcm1_sync_mfp, eram_a5_mfp, eram_a6_mfp, - eram_a7_mfp, eram_a8_mfp, eram_a9_mfp, eram_a10_mfp, - eram_a11_mfp, lvds_oep_odn_mfp, lvds_ocp_obn_mfp, - lvds_oap_oan_mfp, lvds_e_mfp, spi0_sclk_mosi_mfp, spi0_ss_mfp, - spi0_miso_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp, - uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp, - sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_clk_mfp, - uart0_rx_mfp, nand0_d0_ceb3_mfp, uart0_tx_mfp, i2c0_mfp, - csi0_cn_cp_mfp, csi0_dn0_dp3_mfp, csi1_dn0_cp_mfp, - dsi_dp3_dn1_mfp, dsi_cp_dn0_mfp, dsi_dp2_dn2_mfp, - nand1_d0_ceb1_mfp, nand1_ceb3_mfp, nand1_ceb0_mfp, - csi1_dn0_dp0_mfp, uart4_rx_tx_mfp - - - These pin groups are used for selecting the drive strength - parameters. - - sgpio3_drv, sgpio2_drv, sgpio1_drv, sgpio0_drv, - rmii_tx_d0_d1_drv, rmii_txen_rxer_drv, rmii_crs_dv_drv, - rmii_rx_d1_d0_drv, rmii_ref_clk_drv, rmii_mdc_mdio_drv, - sirq_0_1_drv, sirq2_drv, i2s_d0_d1_drv, i2s_lr_m_clk0_drv, - i2s_blk1_mclk1_drv, pcm1_in_out_drv, lvds_oap_oan_drv, - lvds_oep_odn_drv, lvds_ocp_obn_drv, lvds_e_drv, sd0_d3_d0_drv, - sd1_d3_d0_drv, sd0_sd1_cmd_clk_drv, spi0_sclk_mosi_drv, - spi0_ss_miso_drv, uart0_rx_tx_drv, uart4_rx_tx_drv, uart2_drv, - uart3_drv, i2c0_drv, i2c1_drv, i2c2_drv, sensor0_drv - - These pin groups are used for selecting the slew rate - parameters. - - sgpio3_sr, sgpio2_sr, sgpio1_sr, sgpio0_sr, rmii_tx_d0_d1_sr, - rmii_txen_rxer_sr, rmii_crs_dv_sr, rmii_rx_d1_d0_sr, - rmii_ref_clk_sr, rmii_mdc_mdio_sr, sirq_0_1_sr, sirq2_sr, - i2s_do_d1_sr, i2s_lr_m_clk0_sr, i2s_bclk0_mclk1_sr, - pcm1_in_out_sr, sd1_d3_d0_sr, sd0_sd1_clk_cmd_sr, - spi0_sclk_mosi_sr, spi0_ss_miso_sr, uart0_rx_tx_sr, - uart4_rx_tx_sr, uart2_sr, uart3_sr, i2c0_sr, i2c1_sr, i2c2_sr, - sensor0_sr - -- function: An array of strings, each string containing the name of the - pinmux functions. These functions can only be selected by - the corresponding pin groups. The following are the list of - pinmux functions available: - - eram, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0, - uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1, - pcm0, pcm1, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, sd0, - sd1, sd2, sd3, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, lvds, - usb30, usb20, gpu, mipi_csi0, mipi_csi1, mipi_dsi, nand0, - nand1, spdif, sirq0, sirq1, sirq2 - -Optional Properties: - -- bias-bus-hold: No arguments. The specified pins should retain the previous - state value. -- bias-high-impedance: No arguments. The specified pins should be configured - as high impedance. -- bias-pull-down: No arguments. The specified pins should be configured as - pull down. -- bias-pull-up: No arguments. The specified pins should be configured as - pull up. -- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified - pins -- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified - pins -- slew-rate: Integer. Sets slew rate for the specified pins. - Valid values are: - <0> - Slow - <1> - Fast -- drive-strength: Integer. Selects the drive strength for the specified - pins in mA. - Valid values are: - <2> - <4> - <8> - <12> - -Example: - - pinctrl: pinctrl@e01b0000 { - compatible = "actions,s900-pinctrl"; - reg = <0x0 0xe01b0000 0x0 0x1000>; - clocks = <&cmu CLK_GPIO>; - gpio-controller; - gpio-ranges = <&pinctrl 0 0 146>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - , - , - , - ; - - uart2-default: uart2-default { - pinmux { - groups = "lvds_oep_odn_mfp"; - function = "uart2"; - }; - pinconf { - groups = "lvds_oep_odn_drv"; - drive-strength = <12>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.yaml new file mode 100644 index 000000000000..5c7b9f13226d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.yaml @@ -0,0 +1,219 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/actions,s900-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Actions Semi S900 Pin Controller + +maintainers: + - Manivannan Sadhasivam + +properties: + compatible: + const: actions,s900-pinctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 6 + description: The interrupt outputs from the controller. There is one GPIO + interrupt per GPIO bank. The number of interrupts listed depends on the + number of GPIO banks on the SoC. The interrupts must be ordered by bank, + starting with bank 0. + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + clocks: + maxItems: 1 + + gpio-controller: true + + gpio-line-names: + maxItems: 146 + + gpio-ranges: true + + "#gpio-cells": + const: 2 + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - "#interrupt-cells" + - clocks + - gpio-controller + - gpio-ranges + - "#gpio-cells" + +additionalProperties: + type: object + description: Pin configuration subnode + additionalProperties: false + + properties: + pinmux: + type: object + description: Pin mux configuration + $ref: /schemas/pinctrl/pinmux-node.yaml# + additionalProperties: false + + properties: + groups: + items: + enum: [ + lvds_oxx_uart4_mfp, rmii_mdc_mfp, rmii_mdio_mfp, sirq0_mfp, + sirq1_mfp, rmii_txd0_mfp, rmii_txd1_mfp, rmii_txen_mfp, + rmii_rxer_mfp, rmii_crs_dv_mfp, rmii_rxd1_mfp, rmii_rxd0_mfp, + rmii_ref_clk_mfp, i2s_d0_mfp, i2s_d1_mfp, i2s_lr_m_clk0_mfp, + i2s_bclk0_mfp, i2s_bclk1_mclk1_mfp, pcm1_in_out_mfp, pcm1_clk_mfp, + pcm1_sync_mfp, eram_a5_mfp, eram_a6_mfp, eram_a7_mfp, eram_a8_mfp, + eram_a9_mfp, eram_a10_mfp, eram_a11_mfp, lvds_oep_odn_mfp, + lvds_ocp_obn_mfp, lvds_oap_oan_mfp, lvds_e_mfp, + spi0_sclk_mosi_mfp, spi0_ss_mfp, spi0_miso_mfp, uart2_rtsb_mfp, + uart2_ctsb_mfp, uart3_rtsb_mfp, uart3_ctsb_mfp, sd0_d0_mfp, + sd0_d1_mfp, sd0_d2_d3_mfp, sd1_d0_d3_mfp, sd0_cmd_mfp, + sd0_clk_mfp, sd1_cmd_clk_mfp, uart0_rx_mfp, nand0_d0_ceb3_mfp, + uart0_tx_mfp, i2c0_mfp, csi0_cn_cp_mfp, csi0_dn0_dp3_mfp, + csi1_dn0_cp_mfp, dsi_dp3_dn1_mfp, dsi_cp_dn0_mfp, dsi_dp2_dn2_mfp, + nand1_d0_ceb1_mfp, nand1_ceb3_mfp, nand1_ceb0_mfp, + csi1_dn0_dp0_mfp, uart4_rx_tx_mfp + ] + + function: + items: + enum: [ + eram, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0, + uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1, + pcm0, pcm1, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, sd0, + sd1, sd2, sd3, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, lvds, + usb30, usb20, gpu, mipi_csi0, mipi_csi1, mipi_dsi, nand0, + nand1, spdif, sirq0, sirq1, sirq2 + ] + + required: + - groups + - function + + pinconf: + type: object + description: Pin configuration parameters + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml# + - $ref: /schemas/pinctrl/pinmux-node.yaml# + + additionalProperties: false + + properties: + groups: + items: + enum: [ + # pin groups for drive strength + sgpio3_drv, sgpio2_drv, sgpio1_drv, sgpio0_drv, rmii_tx_d0_d1_drv, + rmii_txen_rxer_drv, rmii_crs_dv_drv, rmii_rx_d1_d0_drv, + rmii_ref_clk_drv, rmii_mdc_mdio_drv, sirq_0_1_drv, sirq2_drv, + i2s_d0_d1_drv, i2s_lr_m_clk0_drv, i2s_blk1_mclk1_drv, + pcm1_in_out_drv, lvds_oap_oan_drv, lvds_oep_odn_drv, + lvds_ocp_obn_drv, lvds_e_drv, sd0_d3_d0_drv, sd1_d3_d0_drv, + sd0_sd1_cmd_clk_drv, spi0_sclk_mosi_drv, spi0_ss_miso_drv, + uart0_rx_tx_drv, uart4_rx_tx_drv, uart2_drv, uart3_drv, i2c0_drv, + i2c1_drv, i2c2_drv, sensor0_drv, + # pin groups for slew rate + sgpio3_sr, sgpio2_sr, sgpio1_sr, sgpio0_sr, rmii_tx_d0_d1_sr, + rmii_txen_rxer_sr, rmii_crs_dv_sr, rmii_rx_d1_d0_sr, + rmii_ref_clk_sr, rmii_mdc_mdio_sr, sirq_0_1_sr, sirq2_sr, + i2s_do_d1_sr, i2s_lr_m_clk0_sr, i2s_bclk0_mclk1_sr, + pcm1_in_out_sr, sd1_d3_d0_sr, sd0_sd1_clk_cmd_sr, + spi0_sclk_mosi_sr, spi0_ss_miso_sr, uart0_rx_tx_sr, + uart4_rx_tx_sr, uart2_sr, uart3_sr, i2c0_sr, i2c1_sr, i2c2_sr, + sensor0_sr + ] + + pins: + items: + enum: [ + eth_txd0, eth_txd1, eth_txen, eth_rxer, eth_crs_dv, eth_rxd1, + eth_rxd0, eth_ref_clk, eth_mdc, eth_mdio, sirq0, sirq1, sirq2, + i2s_d0, i2s_bclk0, i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, + i2s_lrclk1, i2s_mclk1, pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, + eram_a5, eram_a6, eram_a7, eram_a8, eram_a9, eram_a10, eram_a11, + lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp, lvds_ocn, + lvds_obp, lvds_obn, lvds_oap, lvds_oan, lvds_eep, lvds_een, + lvds_edp, lvds_edn, lvds_ecp, lvds_ecn, lvds_ebp, lvds_ebn, + lvds_eap, lvds_ean, sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0, + sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk, + spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx, uart0_tx, + uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb, uart3_rx, uart3_tx, + uart3_rtsb, uart3_ctsb, uart4_rx, uart4_tx, i2c0_sclk, i2c0_sdata, + i2c1_sclk, i2c1_sdata, i2c2_sclk, i2c2_sdata, csi0_dn0, csi0_dp0, + csi0_dn1, csi0_dp1, csi0_cn, csi0_cp, csi0_dn2, csi0_dp2, + csi0_dn3, csi0_dp3, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, + dsi_cn, dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sensor0_pclk, + csi1_dn0, csi1_dp0, csi1_dn1, csi1_dp1, csi1_cn, csi1_cp, + sensor0_ckout, nand0_d0, nand0_d1, nand0_d2, nand0_d3, nand0_d4, + nand0_d5, nand0_d6, nand0_d7, nand0_dqs, nand0_dqsn, nand0_ale, + nand0_cle, nand0_ceb0, nand0_ceb1, nand0_ceb2, nand0_ceb3, + nand1_d0, nand1_d1, nand1_d2, nand1_d3, nand1_d4, nand1_d5, + nand1_d6, nand1_d7, nand1_dqs, nand1_dqsn, nand1_ale, nand1_cle, + nand1_ceb0, nand1_ceb1, nand1_ceb2, nand1_ceb3, sgpio0, sgpio1, + sgpio2, sgpio3 + ] + + bias-bus-hold: true + bias-high-impedance: true + + bias-pull-down: + type: boolean + + bias-pull-up: + type: boolean + + input-schmitt-enable: true + input-schmitt-disable: true + slew-rate: true + drive-strength: true + + oneOf: + - required: + - groups + - required: + - pins + +examples: + - | + #include + + pinctrl: pinctrl@e01b0000 { + compatible = "actions,s900-pinctrl"; + reg = <0xe01b0000 0x1000>; + clocks = <&cmu 1>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 146>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + , + , + , + ; + + uart2-default { + pinmux { + groups = "lvds_oep_odn_mfp"; + function = "uart2"; + }; + + pinconf { + groups = "lvds_oep_odn_drv"; + drive-strength = <12>; + }; + }; + }; From f84f54841dd091a909027e6eaf5ea3dc29937592 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Mon, 13 Oct 2025 14:12:25 -0500 Subject: [PATCH 031/107] dt-bindings: pinctrl: Convert brcm,ns2-pinmux to DT schema Convert the brcm,ns2-pinmux binding to DT schema format. It's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- .../bindings/pinctrl/brcm,ns2-pinmux.txt | 102 ---------------- .../bindings/pinctrl/brcm,ns2-pinmux.yaml | 111 ++++++++++++++++++ 2 files changed, 111 insertions(+), 102 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,ns2-pinmux.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,ns2-pinmux.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,ns2-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/brcm,ns2-pinmux.txt deleted file mode 100644 index 40e0a9a19525..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/brcm,ns2-pinmux.txt +++ /dev/null @@ -1,102 +0,0 @@ -Broadcom Northstar2 IOMUX Controller - -The Northstar2 IOMUX controller supports group based mux configuration. There -are some individual pins that support modifying the pinconf parameters. - -Required properties: - -- compatible: - Must be "brcm,ns2-pinmux" - -- reg: - Define the base and range of the I/O address space that contains the - Northstar2 IOMUX and pin configuration registers. - -Properties in sub nodes: - -- function: - The mux function to select - -- groups: - The list of groups to select with a given function - -- pins: - List of pin names to change configuration - -The generic properties bias-disable, bias-pull-down, bias-pull-up, -drive-strength, slew-rate, input-enable, input-disable are supported -for some individual pins listed at the end. - -For more details, refer to -Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - -For example: - - pinctrl: pinctrl@6501d130 { - compatible = "brcm,ns2-pinmux"; - reg = <0x6501d130 0x08>, - <0x660a0028 0x04>, - <0x660009b0 0x40>; - - pinctrl-names = "default"; - pinctrl-0 = <&nand_sel>, <&uart3_rx>, <&sdio0_d4>; - - /* Select nand function */ - nand_sel: nand_sel { - function = "nand"; - groups = "nand_grp"; - }; - - /* Pull up the uart3 rx pin */ - uart3_rx: uart3_rx { - pins = "uart3_sin"; - bias-pull-up; - }; - - /* Set the drive strength of sdio d4 pin */ - sdio0_d4: sdio0_d4 { - pins = "sdio0_data4"; - drive-strength = <8>; - }; - }; - -List of supported functions and groups in Northstar2: - -"nand": "nand_grp" - -"nor": "nor_data_grp", "nor_adv_grp", "nor_addr_0_3_grp", "nor_addr_4_5_grp", - "nor_addr_6_7_grp", "nor_addr_8_9_grp", "nor_addr_10_11_grp", - "nor_addr_12_15_grp" - -"gpio": "gpio_0_1_grp", "gpio_2_5_grp", "gpio_6_7_grp", "gpio_8_9_grp", - "gpio_10_11_grp", "gpio_12_13_grp", "gpio_14_17_grp", "gpio_18_19_grp", - "gpio_20_21_grp", "gpio_22_23_grp", "gpio_24_25_grp", "gpio_26_27_grp", - "gpio_28_29_grp", "gpio_30_31_grp" - -"pcie": "pcie_ab1_clk_wak_grp", "pcie_a3_clk_wak_grp", "pcie_b3_clk_wak_grp", - "pcie_b2_clk_wak_grp", "pcie_a2_clk_wak_grp" - -"uart0": "uart0_modem_grp", "uart0_rts_cts_grp", "uart0_in_out_grp" - -"uart1": "uart1_ext_clk_grp", "uart1_dcd_dsr_grp", "uart1_ri_dtr_grp", - "uart1_rts_cts_grp", "uart1_in_out_grp" - -"uart2": "uart2_rts_cts_grp" - -"pwm": "pwm_0_grp", "pwm_1_grp", "pwm_2_grp", "pwm_3_grp" - - -List of pins that support pinconf parameters: - -"qspi_wp", "qspi_hold", "qspi_cs", "qspi_sck", "uart3_sin", "uart3_sout", -"qspi_mosi", "qspi_miso", "spi0_fss", "spi0_rxd", "spi0_txd", "spi0_sck", -"spi1_fss", "spi1_rxd", "spi1_txd", "spi1_sck", "sdio0_data7", -"sdio0_emmc_rst", "sdio0_led_on", "sdio0_wp", "sdio0_data3", "sdio0_data4", -"sdio0_data5", "sdio0_data6", "sdio0_cmd", "sdio0_data0", "sdio0_data1", -"sdio0_data2", "sdio1_led_on", "sdio1_wp", "sdio0_cd_l", "sdio0_clk", -"sdio1_data5", "sdio1_data6", "sdio1_data7", "sdio1_emmc_rst", "sdio1_data1", -"sdio1_data2", "sdio1_data3", "sdio1_data4", "sdio1_cd_l", "sdio1_clk", -"sdio1_cmd", "sdio1_data0", "ext_mdio_0", "ext_mdc_0", "usb3_p1_vbus_ppc", -"usb3_p1_overcurrent", "usb3_p0_vbus_ppc", "usb3_p0_overcurrent", -"usb2_presence_indication", "usb2_vbus_present", "usb2_vbus_ppc", -"usb2_overcurrent", "sata_led1", "sata_led0" diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,ns2-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,ns2-pinmux.yaml new file mode 100644 index 000000000000..1de23c06fa49 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,ns2-pinmux.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,ns2-pinmux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Northstar2 IOMUX Controller + +maintainers: + - Ray Jui + - Scott Branden + +properties: + compatible: + const: brcm,ns2-pinmux + + reg: + maxItems: 3 + +additionalProperties: + description: Pin group node properties + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml# + - $ref: /schemas/pinctrl/pinmux-node.yaml# + additionalProperties: false + + properties: + function: + description: The mux function to select + $ref: /schemas/types.yaml#/definitions/string + + groups: + items: + enum: [ + nand_grp, nor_data_grp, nor_adv_grp, nor_addr_0_3_grp, + nor_addr_4_5_grp, nor_addr_6_7_grp, nor_addr_8_9_grp, + nor_addr_10_11_grp, nor_addr_12_15_grp, gpio_0_1_grp, gpio_2_5_grp, + gpio_6_7_grp, gpio_8_9_grp, gpio_10_11_grp, gpio_12_13_grp, + gpio_14_17_grp, gpio_18_19_grp, gpio_20_21_grp, gpio_22_23_grp, + gpio_24_25_grp, gpio_26_27_grp, gpio_28_29_grp, gpio_30_31_grp, + pcie_ab1_clk_wak_grp, pcie_a3_clk_wak_grp, pcie_b3_clk_wak_grp, + pcie_b2_clk_wak_grp, pcie_a2_clk_wak_grp, uart0_modem_grp, + uart0_rts_cts_grp, uart0_in_out_grp, uart1_ext_clk_grp, + uart1_dcd_dsr_grp, uart1_ri_dtr_grp, uart1_rts_cts_grp, + uart1_in_out_grp, uart2_rts_cts_grp, pwm_0_grp, pwm_1_grp, pwm_2_grp, + pwm_3_grp + ] + + pins: + items: + enum: [ + qspi_wp, qspi_hold, qspi_cs, qspi_sck, uart3_sin, uart3_sout, + qspi_mosi, qspi_miso, spi0_fss, spi0_rxd, spi0_txd, spi0_sck, + spi1_fss, spi1_rxd, spi1_txd, spi1_sck, sdio0_data7, sdio0_emmc_rst, + sdio0_led_on, sdio0_wp, sdio0_data3, sdio0_data4, sdio0_data5, + sdio0_data6, sdio0_cmd, sdio0_data0, sdio0_data1, sdio0_data2, + sdio1_led_on, sdio1_wp, sdio0_cd_l, sdio0_clk, sdio1_data5, + sdio1_data6, sdio1_data7, sdio1_emmc_rst, sdio1_data1, sdio1_data2, + sdio1_data3, sdio1_data4, sdio1_cd_l, sdio1_clk, sdio1_cmd, + sdio1_data0, ext_mdio_0, ext_mdc_0, usb3_p1_vbus_ppc, + usb3_p1_overcurrent, usb3_p0_vbus_ppc, usb3_p0_overcurrent, + usb2_presence_indication, usb2_vbus_present, usb2_vbus_ppc, + usb2_overcurrent, sata_led1, sata_led0 + ] + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + slew-rate: true + input-enable: true + input-disable: true + + oneOf: + - required: + - groups + - function + - required: + - pins + +required: + - compatible + - reg + +examples: + - | + pinctrl@6501d130 { + compatible = "brcm,ns2-pinmux"; + reg = <0x6501d130 0x08>, + <0x660a0028 0x04>, + <0x660009b0 0x40>; + + /* Select nand function */ + nand-sel { + function = "nand"; + groups = "nand_grp"; + }; + + /* Pull up the uart3 rx pin */ + uart3-rx { + pins = "uart3_sin"; + bias-pull-up; + }; + + /* Set the drive strength of sdio d4 pin */ + sdio0-d4 { + pins = "sdio0_data4"; + drive-strength = <8>; + }; + }; From a419bc0f13f3d13c3947d99accf6df9c690d4f25 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Mon, 13 Oct 2025 14:12:33 -0500 Subject: [PATCH 032/107] dt-bindings: pinctrl: Convert bitmain,bm1880-pinctrl to DT schema Convert the bitmain,bm1880-pinctrl binding to DT schema format. It's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) Acked-by: Manivannan Sadhasivam Signed-off-by: Linus Walleij --- .../pinctrl/bitmain,bm1880-pinctrl.txt | 126 ----------------- .../pinctrl/bitmain,bm1880-pinctrl.yaml | 132 ++++++++++++++++++ MAINTAINERS | 2 +- 3 files changed, 133 insertions(+), 127 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt deleted file mode 100644 index 4980776122cc..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt +++ /dev/null @@ -1,126 +0,0 @@ -Bitmain BM1880 Pin Controller - -This binding describes the pin controller found in the BM1880 SoC. - -Required Properties: - -- compatible: Should be "bitmain,bm1880-pinctrl" -- reg: Offset and length of pinctrl space in SCTRL. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration for BM1880 SoC -includes pinmux and various pin configuration parameters, such as pull-up, -slew rate etc... - -Each configuration node can consist of multiple nodes describing the pinmux -options. The name of each subnode is not important; all subnodes should be -enumerated and processed purely based on their content. - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pinmux subnode: - -Required Properties: - -- pins: An array of strings, each string containing the name of a pin. - Valid values for pins are: - - MIO0 - MIO111 - -- groups: An array of strings, each string containing the name of a pin - group. Valid values for groups are: - - nand_grp, spi_grp, emmc_grp, sdio_grp, eth0_grp, pwm0_grp, - pwm1_grp, pwm2_grp, pwm3_grp, pwm4_grp, pwm5_grp, pwm6_grp, - pwm7_grp, pwm8_grp, pwm9_grp, pwm10_grp, pwm11_grp, pwm12_grp, - pwm13_grp, pwm14_grp, pwm15_grp, pwm16_grp, pwm17_grp, - pwm18_grp, pwm19_grp, pwm20_grp, pwm21_grp, pwm22_grp, - pwm23_grp, pwm24_grp, pwm25_grp, pwm26_grp, pwm27_grp, - pwm28_grp, pwm29_grp, pwm30_grp, pwm31_grp, pwm32_grp, - pwm33_grp, pwm34_grp, pwm35_grp, pwm36_grp, i2c0_grp, - i2c1_grp, i2c2_grp, i2c3_grp, i2c4_grp, uart0_grp, uart1_grp, - uart2_grp, uart3_grp, uart4_grp, uart5_grp, uart6_grp, - uart7_grp, uart8_grp, uart9_grp, uart10_grp, uart11_grp, - uart12_grp, uart13_grp, uart14_grp, uart15_grp, gpio0_grp, - gpio1_grp, gpio2_grp, gpio3_grp, gpio4_grp, gpio5_grp, - gpio6_grp, gpio7_grp, gpio8_grp, gpio9_grp, gpio10_grp, - gpio11_grp, gpio12_grp, gpio13_grp, gpio14_grp, gpio15_grp, - gpio16_grp, gpio17_grp, gpio18_grp, gpio19_grp, gpio20_grp, - gpio21_grp, gpio22_grp, gpio23_grp, gpio24_grp, gpio25_grp, - gpio26_grp, gpio27_grp, gpio28_grp, gpio29_grp, gpio30_grp, - gpio31_grp, gpio32_grp, gpio33_grp, gpio34_grp, gpio35_grp, - gpio36_grp, gpio37_grp, gpio38_grp, gpio39_grp, gpio40_grp, - gpio41_grp, gpio42_grp, gpio43_grp, gpio44_grp, gpio45_grp, - gpio46_grp, gpio47_grp, gpio48_grp, gpio49_grp, gpio50_grp, - gpio51_grp, gpio52_grp, gpio53_grp, gpio54_grp, gpio55_grp, - gpio56_grp, gpio57_grp, gpio58_grp, gpio59_grp, gpio60_grp, - gpio61_grp, gpio62_grp, gpio63_grp, gpio64_grp, gpio65_grp, - gpio66_grp, gpio67_grp, eth1_grp, i2s0_grp, i2s0_mclkin_grp, - i2s1_grp, i2s1_mclkin_grp, spi0_grp - -- function: An array of strings, each string containing the name of the - pinmux functions. The following are the list of pinmux - functions available: - - nand, spi, emmc, sdio, eth0, pwm0, pwm1, pwm2, pwm3, pwm4, - pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, pwm12, pwm13, - pwm14, pwm15, pwm16, pwm17, pwm18, pwm19, pwm20, pwm21, pwm22, - pwm23, pwm24, pwm25, pwm26, pwm27, pwm28, pwm29, pwm30, pwm31, - pwm32, pwm33, pwm34, pwm35, pwm36, i2c0, i2c1, i2c2, i2c3, - i2c4, uart0, uart1, uart2, uart3, uart4, uart5, uart6, uart7, - uart8, uart9, uart10, uart11, uart12, uart13, uart14, uart15, - gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, gpio8, - gpio9, gpio10, gpio11, gpio12, gpio13, gpio14, gpio15, gpio16, - gpio17, gpio18, gpio19, gpio20, gpio21, gpio22, gpio23, - gpio24, gpio25, gpio26, gpio27, gpio28, gpio29, gpio30, - gpio31, gpio32, gpio33, gpio34, gpio35, gpio36, gpio37, - gpio38, gpio39, gpio40, gpio41, gpio42, gpio43, gpio44, - gpio45, gpio46, gpio47, gpio48, gpio49, gpio50, gpio51, - gpio52, gpio53, gpio54, gpio55, gpio56, gpio57, gpio58, - gpio59, gpio60, gpio61, gpio62, gpio63, gpio64, gpio65, - gpio66, gpio67, eth1, i2s0, i2s0_mclkin, i2s1, i2s1_mclkin, - spi0 - -Optional Properties: - -- bias-disable: No arguments. Disable pin bias. -- bias-pull-down: No arguments. The specified pins should be configured as - pull down. -- bias-pull-up: No arguments. The specified pins should be configured as - pull up. -- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified - pins -- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified - pins -- slew-rate: Integer. Sets slew rate for the specified pins. - Valid values are: - <0> - Slow - <1> - Fast -- drive-strength: Integer. Selects the drive strength for the specified - pins in mA. - Valid values are: - <4> - <8> - <12> - <16> - <20> - <24> - <28> - <32> - -Example: - pinctrl: pinctrl@400 { - compatible = "bitmain,bm1880-pinctrl"; - reg = <0x400 0x120>; - - pinctrl_uart0_default: uart0-default { - pinmux { - groups = "uart0_grp"; - function = "uart0"; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.yaml new file mode 100644 index 000000000000..542be9870838 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.yaml @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/bitmain,bm1880-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bitmain BM1880 Pin Controller + +maintainers: + - Manivannan Sadhasivam + +properties: + compatible: + const: bitmain,bm1880-pinctrl + + reg: + maxItems: 1 + +additionalProperties: + description: A pin configuration node. + type: object + additionalProperties: false + + properties: + pinmux: + type: object + description: Pin multiplexing parameters. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml# + - $ref: /schemas/pinctrl/pinmux-node.yaml# + additionalProperties: false + + properties: + pins: + items: + pattern: '^MIO[0-9]+$' + + groups: + items: + enum: [ + nand_grp, spi_grp, emmc_grp, sdio_grp, eth0_grp, pwm0_grp, + pwm1_grp, pwm2_grp, pwm3_grp, pwm4_grp, pwm5_grp, pwm6_grp, + pwm7_grp, pwm8_grp, pwm9_grp, pwm10_grp, pwm11_grp, pwm12_grp, + pwm13_grp, pwm14_grp, pwm15_grp, pwm16_grp, pwm17_grp, + pwm18_grp, pwm19_grp, pwm20_grp, pwm21_grp, pwm22_grp, + pwm23_grp, pwm24_grp, pwm25_grp, pwm26_grp, pwm27_grp, + pwm28_grp, pwm29_grp, pwm30_grp, pwm31_grp, pwm32_grp, + pwm33_grp, pwm34_grp, pwm35_grp, pwm36_grp, i2c0_grp, + i2c1_grp, i2c2_grp, i2c3_grp, i2c4_grp, uart0_grp, uart1_grp, + uart2_grp, uart3_grp, uart4_grp, uart5_grp, uart6_grp, + uart7_grp, uart8_grp, uart9_grp, uart10_grp, uart11_grp, + uart12_grp, uart13_grp, uart14_grp, uart15_grp, gpio0_grp, + gpio1_grp, gpio2_grp, gpio3_grp, gpio4_grp, gpio5_grp, + gpio6_grp, gpio7_grp, gpio8_grp, gpio9_grp, gpio10_grp, + gpio11_grp, gpio12_grp, gpio13_grp, gpio14_grp, gpio15_grp, + gpio16_grp, gpio17_grp, gpio18_grp, gpio19_grp, gpio20_grp, + gpio21_grp, gpio22_grp, gpio23_grp, gpio24_grp, gpio25_grp, + gpio26_grp, gpio27_grp, gpio28_grp, gpio29_grp, gpio30_grp, + gpio31_grp, gpio32_grp, gpio33_grp, gpio34_grp, gpio35_grp, + gpio36_grp, gpio37_grp, gpio38_grp, gpio39_grp, gpio40_grp, + gpio41_grp, gpio42_grp, gpio43_grp, gpio44_grp, gpio45_grp, + gpio46_grp, gpio47_grp, gpio48_grp, gpio49_grp, gpio50_grp, + gpio51_grp, gpio52_grp, gpio53_grp, gpio54_grp, gpio55_grp, + gpio56_grp, gpio57_grp, gpio58_grp, gpio59_grp, gpio60_grp, + gpio61_grp, gpio62_grp, gpio63_grp, gpio64_grp, gpio65_grp, + gpio66_grp, gpio67_grp, eth1_grp, i2s0_grp, i2s0_mclkin_grp, + i2s1_grp, i2s1_mclkin_grp, spi0_grp + ] + + function: + items: + enum: [ + nand, spi, emmc, sdio, eth0, pwm0, pwm1, pwm2, pwm3, pwm4, + pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, pwm12, pwm13, + pwm14, pwm15, pwm16, pwm17, pwm18, pwm19, pwm20, pwm21, pwm22, + pwm23, pwm24, pwm25, pwm26, pwm27, pwm28, pwm29, pwm30, pwm31, + pwm32, pwm33, pwm34, pwm35, pwm36, i2c0, i2c1, i2c2, i2c3, + i2c4, uart0, uart1, uart2, uart3, uart4, uart5, uart6, uart7, + uart8, uart9, uart10, uart11, uart12, uart13, uart14, uart15, + gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, gpio8, + gpio9, gpio10, gpio11, gpio12, gpio13, gpio14, gpio15, gpio16, + gpio17, gpio18, gpio19, gpio20, gpio21, gpio22, gpio23, + gpio24, gpio25, gpio26, gpio27, gpio28, gpio29, gpio30, + gpio31, gpio32, gpio33, gpio34, gpio35, gpio36, gpio37, + gpio38, gpio39, gpio40, gpio41, gpio42, gpio43, gpio44, + gpio45, gpio46, gpio47, gpio48, gpio49, gpio50, gpio51, + gpio52, gpio53, gpio54, gpio55, gpio56, gpio57, gpio58, + gpio59, gpio60, gpio61, gpio62, gpio63, gpio64, gpio65, + gpio66, gpio67, eth1, i2s0, i2s0_mclkin, i2s1, i2s1_mclkin, + spi0 + ] + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + input-schmitt-enable: true + input-schmitt-disable: true + + slew-rate: + description: > + Sets slew rate. Valid values: 0 = Slow, 1 = Fast. + enum: [0, 1] + + drive-strength: + enum: [4, 8, 12, 16, 20, 24, 28, 32] + + oneOf: + - required: + - pins + - required: + - groups + + required: + - function + +required: + - compatible + - reg + +examples: + - | + pinctrl@400 { + compatible = "bitmain,bm1880-pinctrl"; + reg = <0x400 0x120>; + + uart0-default { + pinmux { + groups = "uart0_grp"; + function = "uart0"; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 46126ce2f968..bdbcd05095b1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2529,7 +2529,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/arm/bitmain.yaml F: Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml -F: Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt +F: Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.yaml F: arch/arm64/boot/dts/bitmain/ F: drivers/clk/clk-bm1880.c F: drivers/pinctrl/pinctrl-bm1880.c From 7958b4bb806c1af800ca23c8333a98231b3ab0b1 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 22 Oct 2025 15:23:42 +0200 Subject: [PATCH 033/107] pinctrl: pinmux: Add missing .function_is_gpio kerneldoc This callback was undocumented, add the docs. Reviewed-by: Bartosz Golaszewski Signed-off-by: Linus Walleij --- include/linux/pinctrl/pinmux.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/linux/pinctrl/pinmux.h b/include/linux/pinctrl/pinmux.h index 6db6c3e1ccc2..094bbe2fd6fd 100644 --- a/include/linux/pinctrl/pinmux.h +++ b/include/linux/pinctrl/pinmux.h @@ -35,6 +35,16 @@ struct pinctrl_gpio_range; * name can be used with the generic @pinctrl_ops to retrieve the * actual pins affected. The applicable groups will be returned in * @groups and the number of groups in @num_groups + * @function_is_gpio: determine if the indicated function selector passed + * corresponds to the GPIO function which is used by the accelerated GPIO + * functions @gpio_request_enable, @gpio_disable_free and + * @gpio_set_direction. When the pin control core can properly determine + * if a function is a GPIO function, it is easier to use the @strict mode + * on the pin controller. Since a single function is passed, this is + * only useful on pin controllers that use a specific function for GPIO, + * and that usually presupposes that a one-group-per-pin approach is + * used, so that a single function can be set on a single pin to turn + * it to GPIO mode. * @set_mux: enable a certain muxing function with a certain pin group. The * driver does not need to figure out whether enabling this function * conflicts some other use of the pins in that group, such collisions From 2b195e2bab1d7b4983c3348d8a2e457bb767ce36 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 22 Oct 2025 15:34:27 +0200 Subject: [PATCH 034/107] dt-bindings: pinctrl: toshiba,visconti: Drop redundant functions type Referenced pinmux-node.yaml schema already defines type for "functions" so $ref is redundant. Signed-off-by: Krzysztof Kozlowski Acked-by: Conor Dooley Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml index 19d47fd414bc..a811a643bb88 100644 --- a/Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml @@ -42,7 +42,6 @@ patternProperties: function: description: Function to mux. - $ref: /schemas/types.yaml#/definitions/string enum: [i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c8, spi0, spi1, spi2, spi3, spi4, spi5, spi6, uart0, uart1, uart2, uart3, pwm, pcmif_out, pcmif_in] From aa09d5a147702814ee8cf8faf0aea8f001cee1bc Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 21 Oct 2025 10:06:05 +0200 Subject: [PATCH 035/107] pinctrl: renesas: rza1: Make mux_conf const in rza1_pin_mux_single() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The rza1_mux_conf object pointed to by the mux_conf parameter of rza1_pin_mux_single() is never modified. Make it const. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://patch.msgid.link/168e06bc57081aa3c42ff9aa2740a0a108df7d34.1761033950.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pinctrl-rza1.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rza1.c b/drivers/pinctrl/renesas/pinctrl-rza1.c index 4c7326e3de07..3cfa4c8be80e 100644 --- a/drivers/pinctrl/renesas/pinctrl-rza1.c +++ b/drivers/pinctrl/renesas/pinctrl-rza1.c @@ -668,7 +668,7 @@ static inline int rza1_pin_get(struct rza1_port *port, unsigned int pin) * @mux_conf: pin multiplexing descriptor */ static int rza1_pin_mux_single(struct rza1_pinctrl *rza1_pctl, - struct rza1_mux_conf *mux_conf) + const struct rza1_mux_conf *mux_conf) { struct rza1_port *port = &rza1_pctl->ports[mux_conf->port]; unsigned int pin = mux_conf->pin; @@ -1118,7 +1118,7 @@ static int rza1_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, unsigned int group) { struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev); - struct rza1_mux_conf *mux_confs; + const struct rza1_mux_conf *mux_confs; const struct function_desc *func; struct group_desc *grp; int i; @@ -1131,7 +1131,7 @@ static int rza1_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, if (!func) return -EINVAL; - mux_confs = (struct rza1_mux_conf *)func->data; + mux_confs = (const struct rza1_mux_conf *)func->data; for (i = 0; i < grp->grp.npins; ++i) { int ret; From 645f1095d317854816bcfa13201f4bcf121465fe Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Thu, 23 Oct 2025 18:14:57 +0100 Subject: [PATCH 036/107] dt-bindings: pinctrl: document pic64gx "gpio2" pinmux The pic64gx has a second pinmux "downstream" of the iomux0 pinmux. The documentation for the SoC provides no name for this device, but it is used to swap pins between either GPIO controller #2 or select other functions, hence the "gpio2" name. Currently there is no documentation about what each bit actually does that is publicly available, nor (I believe) what pins are affected. That info is as follows: pin role (1/0) --- ---------- E14 MAC_0_MDC/GPIO_2_0 E15 MAC_0_MDIO/GPIO_2_1 F16 MAC_1_MDC/GPIO_2_2 F17 MAC_1_MDIO/GPIO_2_3 D19 SPI_0_CLK/GPIO_2_4 B18 SPI_0_SS0/GPIO_2_5 B10 CAN_0_RXBUS/GPIO_2_6 C14 PCIE_PERST_2#/GPIO_2_7 E18 PCIE_WAKE#/GPIO_2_8 D18 PCIE_PERST_1#/GPIO_2_9 E19 SPI_0_DO/GPIO_2_10 C7 SPI_0_DI/GPIO_2_11 D6 QSPI_SS0/GPIO_2_12 D7 QSPI_CLK (B)/GPIO_2_13 C9 QSPI_DATA0/GPIO_2_14 C10 QSPI_DATA1/GPIO_2_15 A5 QSPI_DATA2/GPIO_2_16 A6 QSPI_DATA3/GPIO_2_17 D8 MMUART_3_RXD/GPIO_2_18 D9 MMUART_3_TXD/GPIO_2_19 B8 MMUART_4_RXD/GPIO_2_20 A8 MMUART_4_TXD/GPIO_2_21 C12 CAN_1_TXBUS/GPIO_2_22 B12 CAN_1_RXBUS/GPIO_2_23 A11 CAN_0_TX_EBL_N/GPIO_2_24 A10 CAN_1_TX_EBL_N/GPIO_2_25 D11 MMUART_2_RXD/GPIO_2_26 C11 MMUART_2_TXD/GPIO_2_27 B9 CAN_0_TXBUS/GPIO_2_28 Reviewed-by: Rob Herring (Arm) Signed-off-by: Conor Dooley Signed-off-by: Linus Walleij --- .../microchip,pic64gx-pinctrl-gpio2.yaml | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,pic64gx-pinctrl-gpio2.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,pic64gx-pinctrl-gpio2.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,pic64gx-pinctrl-gpio2.yaml new file mode 100644 index 000000000000..e3792679de58 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/microchip,pic64gx-pinctrl-gpio2.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/microchip,pic64gx-pinctrl-gpio2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PIC64GX GPIO2 Mux + +maintainers: + - Conor Dooley + +description: + The "GPIO2 Mux" determines whether GPIO2 or select other functions are + available on package pins on PIC64GX. Some of these functions must be + mapped to this mux via iomux0 for settings here to have any impact. + +properties: + compatible: + const: microchip,pic64gx-pinctrl-gpio2 + + reg: + maxItems: 1 + + pinctrl-use-default: true + +patternProperties: + '^mux-': + type: object + $ref: pinmux-node.yaml + additionalProperties: false + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [ mdio0, mdio1, spi0, can0, pcie, qspi, uart3, uart4, can1, uart2, gpio ] + + groups: + description: + An array of strings. Each string contains the name of a group. + items: + enum: [ mdio0, mdio1, spi0, can0, pcie, qspi, uart3, uart4, can1, uart2, + gpio_mdio0, gpio_mdio1, gpio_spi0, gpio_can0, gpio_pcie, + gpio_qspi, gpio_uart3, gpio_uart4, gpio_can1, gpio_uart2 ] + + required: + - function + - groups + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@41000000 { + compatible = "microchip,pic64gx-pinctrl-gpio2"; + reg = <0x41000000 0x4>; + pinctrl-use-default; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_gpio2>, <&mdio1_gpio2>, <&spi0_gpio2>, <&qspi_gpio2>, + <&uart3_gpio2>, <&uart4_gpio2>, <&can1_gpio2>, <&can0_gpio2>, + <&uart2_gpio2>; + + mux-gpio2 { + function = "gpio"; + groups = "gpio_mdio1", "gpio_spi0", "gpio_can0", "gpio_pcie", + "gpio_qspi", "gpio_uart3", "gpio_uart4", "gpio_can1"; + }; + }; + +... From 38cf9d6413142290316776c80f19eb92a4e19a9f Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Thu, 23 Oct 2025 18:14:58 +0100 Subject: [PATCH 037/107] pinctrl: add pic64gx "gpio2" pinmux driver The pic64gx has a second pinmux "downstream" of the iomux0 pinmux. The documentation for the SoC provides no name for this device, but it is used to swap pins between either GPIO controller #2 or select other functions, hence the "gpio2" name. Add a driver for it. Signed-off-by: Conor Dooley Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 8 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-pic64gx-gpio2.c | 356 ++++++++++++++++++++++++ 3 files changed, 365 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-pic64gx-gpio2.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 4f8507ebbdac..e83fda9bf308 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -486,6 +486,14 @@ config PINCTRL_PIC32MZDA def_bool y if PIC32MZDA select PINCTRL_PIC32 +config PINCTRL_PIC64GX + bool "pic64gx gpio2 pinctrl driver" + depends on ARCH_MICROCHIP || COMPILE_TEST + select GENERIC_PINCONF + default y + help + This selects the pinctrl driver for gpio2 on pic64gx. + config PINCTRL_PISTACHIO bool "IMG Pistachio SoC pinctrl driver" depends on OF && (MIPS || COMPILE_TEST) diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index e0cfb9b7c99b..f33976a6c91b 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -48,6 +48,7 @@ obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o obj-$(CONFIG_PINCTRL_PEF2256) += pinctrl-pef2256.o obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o +obj-$(CONFIG_PINCTRL_PIC64GX) += pinctrl-pic64gx-gpio2.o obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o diff --git a/drivers/pinctrl/pinctrl-pic64gx-gpio2.c b/drivers/pinctrl/pinctrl-pic64gx-gpio2.c new file mode 100644 index 000000000000..f322bb5e6181 --- /dev/null +++ b/drivers/pinctrl/pinctrl-pic64gx-gpio2.c @@ -0,0 +1,356 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "pinctrl-utils.h" + +#define PIC64GX_PINMUX_REG 0x0 + +static const struct regmap_config pic64gx_gpio2_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .val_format_endian = REGMAP_ENDIAN_LITTLE, + .max_register = 0x0, +}; + +struct pic64gx_gpio2_pinctrl { + struct pinctrl_dev *pctrl; + struct device *dev; + struct regmap *regmap; + struct pinctrl_desc desc; +}; + +struct pic64gx_gpio2_pin_group { + const char *name; + const unsigned int *pins; + const unsigned int num_pins; + u32 mask; + u32 setting; +}; + +struct pic64gx_gpio2_function { + const char *name; + const char * const *groups; + const unsigned int num_groups; +}; + +static const struct pinctrl_pin_desc pic64gx_gpio2_pins[] = { + PINCTRL_PIN(0, "E14"), + PINCTRL_PIN(1, "E15"), + PINCTRL_PIN(2, "F16"), + PINCTRL_PIN(3, "F17"), + PINCTRL_PIN(4, "D19"), + PINCTRL_PIN(5, "B18"), + PINCTRL_PIN(6, "B10"), + PINCTRL_PIN(7, "C14"), + PINCTRL_PIN(8, "E18"), + PINCTRL_PIN(9, "D18"), + PINCTRL_PIN(10, "E19"), + PINCTRL_PIN(11, "C7"), + PINCTRL_PIN(12, "D6"), + PINCTRL_PIN(13, "D7"), + PINCTRL_PIN(14, "C9"), + PINCTRL_PIN(15, "C10"), + PINCTRL_PIN(16, "A5"), + PINCTRL_PIN(17, "A6"), + PINCTRL_PIN(18, "D8"), + PINCTRL_PIN(19, "D9"), + PINCTRL_PIN(20, "B8"), + PINCTRL_PIN(21, "A8"), + PINCTRL_PIN(22, "C12"), + PINCTRL_PIN(23, "B12"), + PINCTRL_PIN(24, "A11"), + PINCTRL_PIN(25, "A10"), + PINCTRL_PIN(26, "D11"), + PINCTRL_PIN(27, "C11"), + PINCTRL_PIN(28, "B9"), +}; + +static const unsigned int pic64gx_gpio2_mdio0_pins[] = { + 0, 1 +}; + +static const unsigned int pic64gx_gpio2_mdio1_pins[] = { + 2, 3 +}; + +static const unsigned int pic64gx_gpio2_spi0_pins[] = { + 4, 5, 10, 11 +}; + +static const unsigned int pic64gx_gpio2_can0_pins[] = { + 6, 24, 28 +}; + +static const unsigned int pic64gx_gpio2_pcie_pins[] = { + 7, 8, 9 +}; + +static const unsigned int pic64gx_gpio2_qspi_pins[] = { + 12, 13, 14, 15, 16, 17 +}; + +static const unsigned int pic64gx_gpio2_uart3_pins[] = { + 18, 19 +}; + +static const unsigned int pic64gx_gpio2_uart4_pins[] = { + 20, 21 +}; + +static const unsigned int pic64gx_gpio2_can1_pins[] = { + 22, 23, 25 +}; + +static const unsigned int pic64gx_gpio2_uart2_pins[] = { + 26, 27 +}; + +#define PIC64GX_PINCTRL_GROUP(_name, _mask) { \ + .name = "gpio_" #_name, \ + .pins = pic64gx_gpio2_##_name##_pins, \ + .num_pins = ARRAY_SIZE(pic64gx_gpio2_##_name##_pins), \ + .mask = _mask, \ + .setting = 0x0, \ +}, { \ + .name = #_name, \ + .pins = pic64gx_gpio2_##_name##_pins, \ + .num_pins = ARRAY_SIZE(pic64gx_gpio2_##_name##_pins), \ + .mask = _mask, \ + .setting = _mask, \ +} + +static const struct pic64gx_gpio2_pin_group pic64gx_gpio2_pin_groups[] = { + PIC64GX_PINCTRL_GROUP(mdio0, BIT(0) | BIT(1)), + PIC64GX_PINCTRL_GROUP(mdio1, BIT(2) | BIT(3)), + PIC64GX_PINCTRL_GROUP(spi0, BIT(4) | BIT(5) | BIT(10) | BIT(11)), + PIC64GX_PINCTRL_GROUP(can0, BIT(6) | BIT(24) | BIT(28)), + PIC64GX_PINCTRL_GROUP(pcie, BIT(7) | BIT(8) | BIT(9)), + PIC64GX_PINCTRL_GROUP(qspi, GENMASK(17, 12)), + PIC64GX_PINCTRL_GROUP(uart3, BIT(18) | BIT(19)), + PIC64GX_PINCTRL_GROUP(uart4, BIT(20) | BIT(21)), + PIC64GX_PINCTRL_GROUP(can1, BIT(22) | BIT(23) | BIT(25)), + PIC64GX_PINCTRL_GROUP(uart2, BIT(26) | BIT(27)), +}; + +static const char * const pic64gx_gpio2_gpio_groups[] = { + "gpio_mdio0", "gpio_mdio1", "gpio_spi0", "gpio_can0", "gpio_pcie", + "gpio_qspi", "gpio_uart3", "gpio_uart4", "gpio_can1", "gpio_uart2" +}; + +static const char * const pic64gx_gpio2_mdio0_groups[] = { + "mdio0" +}; + +static const char * const pic64gx_gpio2_mdio1_groups[] = { + "mdio1" +}; + +static const char * const pic64gx_gpio2_spi0_groups[] = { + "spi0" +}; + +static const char * const pic64gx_gpio2_can0_groups[] = { + "can0" +}; + +static const char * const pic64gx_gpio2_pcie_groups[] = { + "pcie" +}; + +static const char * const pic64gx_gpio2_qspi_groups[] = { + "qspi" +}; + +static const char * const pic64gx_gpio2_uart3_groups[] = { + "uart3" +}; + +static const char * const pic64gx_gpio2_uart4_groups[] = { + "uart4" +}; + +static const char * const pic64gx_gpio2_can1_groups[] = { + "can1" +}; + +static const char * const pic64gx_gpio2_uart2_groups[] = { + "uart2" +}; + +#define PIC64GX_PINCTRL_FUNCTION(_name) { \ + .name = #_name, \ + .groups = pic64gx_gpio2_##_name##_groups, \ + .num_groups = ARRAY_SIZE(pic64gx_gpio2_##_name##_groups), \ +} + +static const struct pic64gx_gpio2_function pic64gx_gpio2_functions[] = { + PIC64GX_PINCTRL_FUNCTION(gpio), + PIC64GX_PINCTRL_FUNCTION(mdio0), + PIC64GX_PINCTRL_FUNCTION(mdio1), + PIC64GX_PINCTRL_FUNCTION(spi0), + PIC64GX_PINCTRL_FUNCTION(can0), + PIC64GX_PINCTRL_FUNCTION(pcie), + PIC64GX_PINCTRL_FUNCTION(qspi), + PIC64GX_PINCTRL_FUNCTION(uart3), + PIC64GX_PINCTRL_FUNCTION(uart4), + PIC64GX_PINCTRL_FUNCTION(can1), + PIC64GX_PINCTRL_FUNCTION(uart2), +}; + +static void pic64gx_gpio2_pin_dbg_show(struct pinctrl_dev *pctrl_dev, struct seq_file *seq, + unsigned int pin) +{ + struct pic64gx_gpio2_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev); + u32 val; + + regmap_read(pctrl->regmap, PIC64GX_PINMUX_REG, &val); + val = (val & BIT(pin)) >> pin; + seq_printf(seq, "pin: %u val: %x\n", pin, val); +} + +static int pic64gx_gpio2_groups_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(pic64gx_gpio2_pin_groups); +} + +static const char *pic64gx_gpio2_group_name(struct pinctrl_dev *pctldev, unsigned int selector) +{ + return pic64gx_gpio2_pin_groups[selector].name; +} + +static int pic64gx_gpio2_group_pins(struct pinctrl_dev *pctldev, unsigned int selector, + const unsigned int **pins, unsigned int *num_pins) +{ + *pins = pic64gx_gpio2_pin_groups[selector].pins; + *num_pins = pic64gx_gpio2_pin_groups[selector].num_pins; + + return 0; +} + +static const struct pinctrl_ops pic64gx_gpio2_pinctrl_ops = { + .get_groups_count = pic64gx_gpio2_groups_count, + .get_group_name = pic64gx_gpio2_group_name, + .get_group_pins = pic64gx_gpio2_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, + .dt_free_map = pinctrl_utils_free_map, + .pin_dbg_show = pic64gx_gpio2_pin_dbg_show, +}; + +static int pic64gx_gpio2_pinmux_get_funcs_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(pic64gx_gpio2_functions); +} + +static const char *pic64gx_gpio2_pinmux_get_func_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return pic64gx_gpio2_functions[selector].name; +} + +static int pic64gx_gpio2_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned int selector, + const char * const **groups, + unsigned int * const num_groups) +{ + *groups = pic64gx_gpio2_functions[selector].groups; + *num_groups = pic64gx_gpio2_functions[selector].num_groups; + + return 0; +} + +static int pic64gx_gpio2_pinmux_set_mux(struct pinctrl_dev *pctrl_dev, unsigned int fsel, + unsigned int gsel) +{ + struct pic64gx_gpio2_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev); + struct device *dev = pctrl->dev; + const struct pic64gx_gpio2_pin_group *group; + const struct pic64gx_gpio2_function *function; + + group = &pic64gx_gpio2_pin_groups[gsel]; + function = &pic64gx_gpio2_functions[fsel]; + + dev_dbg(dev, "Setting func %s mask %x setting %x\n", + function->name, group->mask, group->setting); + regmap_assign_bits(pctrl->regmap, PIC64GX_PINMUX_REG, group->mask, group->setting); + + return 0; +} + +static const struct pinmux_ops pic64gx_gpio2_pinmux_ops = { + .get_functions_count = pic64gx_gpio2_pinmux_get_funcs_count, + .get_function_name = pic64gx_gpio2_pinmux_get_func_name, + .get_function_groups = pic64gx_gpio2_pinmux_get_groups, + .set_mux = pic64gx_gpio2_pinmux_set_mux, +}; + +static int pic64gx_gpio2_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct pic64gx_gpio2_pinctrl *pctrl; + void __iomem *base; + + pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) { + dev_err(dev, "Failed get resource\n"); + return PTR_ERR(base); + } + + pctrl->regmap = devm_regmap_init_mmio(dev, base, &pic64gx_gpio2_regmap_config); + if (IS_ERR(pctrl->regmap)) { + dev_err(dev, "Failed to map regmap\n"); + return PTR_ERR(pctrl->regmap); + } + + pctrl->desc.name = dev_name(dev); + pctrl->desc.pins = pic64gx_gpio2_pins; + pctrl->desc.npins = ARRAY_SIZE(pic64gx_gpio2_pins); + pctrl->desc.pctlops = &pic64gx_gpio2_pinctrl_ops; + pctrl->desc.pmxops = &pic64gx_gpio2_pinmux_ops; + pctrl->desc.owner = THIS_MODULE; + + pctrl->dev = dev; + + platform_set_drvdata(pdev, pctrl); + + pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); + if (IS_ERR(pctrl->pctrl)) + return PTR_ERR(pctrl->pctrl); + + return 0; +} + +static const struct of_device_id pic64gx_gpio2_of_match[] = { + { .compatible = "microchip,pic64gx-pinctrl-gpio2" }, + { } +}; +MODULE_DEVICE_TABLE(of, pic64gx_gpio2_of_match); + +static struct platform_driver pic64gx_gpio2_driver = { + .driver = { + .name = "pic64gx-pinctrl-gpio2", + .of_match_table = pic64gx_gpio2_of_match, + }, + .probe = pic64gx_gpio2_probe, +}; +module_platform_driver(pic64gx_gpio2_driver); + +MODULE_AUTHOR("Conor Dooley "); +MODULE_DESCRIPTION("pic64gx gpio2 pinctrl driver"); +MODULE_LICENSE("GPL"); From 2f0073afd9bf88263c3d5136680a0e33a413383f Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Thu, 23 Oct 2025 18:14:59 +0100 Subject: [PATCH 038/107] dt-bindings: pinctrl: document polarfire soc iomux0 pinmux On Polarfire SoC, iomux0 is responsible for routing functions to either Multiprocessor Subsystem (MSS) IOs or to the FPGA fabric, where they can either interface with custom RTL or be routed to the FPGA fabric's IOs. Document it. Reviewed-by: Rob Herring (Arm) Signed-off-by: Conor Dooley Signed-off-by: Linus Walleij --- .../microchip,mpfs-pinctrl-iomux0.yaml | 89 +++++++++++++++++++ .../microchip,mpfs-mss-top-sysreg.yaml | 13 ++- 2 files changed, 101 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml new file mode 100644 index 000000000000..3c98eb35fb82 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire SoC iomux0 + +maintainers: + - Conor Dooley + +description: + iomux0 is responsible for routing some functions to either the FPGA fabric, + or to MSSIOs. It only performs muxing, and has no IO configuration role, as + fabric IOs are configured separately and just routing a function to MSSIOs is + not sufficient for it to actually get mapped to an MSSIO, just makes it + possible. + +properties: + compatible: + oneOf: + - const: microchip,mpfs-pinctrl-iomux0 + - items: + - const: microchip,pic64gx-pinctrl-iomux0 + - const: microchip,mpfs-pinctrl-iomux0 + + reg: + maxItems: 1 + + pinctrl-use-default: true + +patternProperties: + '^mux-': + type: object + $ref: pinmux-node.yaml + additionalProperties: false + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [ spi0, spi1, i2c0, i2c1, can0, can1, qspi, uart0, uart1, uart2, + uart3, uart4, mdio0, mdio1 ] + + groups: + description: + An array of strings. Each string contains the name of a group. + items: + enum: [ spi0_fabric, spi0_mssio, spi1_fabric, spi1_mssio, i2c0_fabric, + i2c0_mssio, i2c1_fabric, i2c1_mssio, can0_fabric, can0_mssio, + can1_fabric, can1_mssio, qspi_fabric, qspi_mssio, + uart0_fabric, uart0_mssio, uart1_fabric, uart1_mssio, + uart2_fabric, uart2_mssio, uart3_fabric, uart3_mssio, + uart4_fabric, uart4_mssio, mdio0_fabric, mdio0_mssio, + mdio1_fabric, mdio1_mssio ] + + required: + - function + - groups + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #size-cells = <1>; + #address-cells = <1>; + + pinctrl@200 { + compatible = "microchip,mpfs-pinctrl-iomux0"; + reg = <0x200 0x4>; + + mux-spi0-fabric { + function = "spi0"; + groups = "spi0_fabric"; + }; + + mux-spi1-mssio { + function = "spi1"; + groups = "spi1_mssio"; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml index 1ab691db8795..39987f722411 100644 --- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml @@ -18,10 +18,17 @@ properties: items: - const: microchip,mpfs-mss-top-sysreg - const: syscon + - const: simple-mfd reg: maxItems: 1 + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + '#reset-cells': description: The AHB/AXI peripherals on the PolarFire SoC have reset support, so @@ -31,6 +38,10 @@ properties: of PolarFire clock/reset IDs. const: 1 + pinctrl@200: + type: object + $ref: /schemas/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml + required: - compatible - reg @@ -40,7 +51,7 @@ additionalProperties: false examples: - | syscon@20002000 { - compatible = "microchip,mpfs-mss-top-sysreg", "syscon"; + compatible = "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd"; reg = <0x20002000 0x1000>; #reset-cells = <1>; }; From 46397274da2284f46e550dc795de5ceeef8f89bf Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Thu, 23 Oct 2025 18:15:00 +0100 Subject: [PATCH 039/107] pinctrl: add polarfire soc iomux0 pinmux driver On Polarfire SoC, iomux0 is responsible for routing functions to either Multiprocessor Subsystem (MSS) IOs or to the FPGA fabric, where they can either interface with custom RTL or be routed to the FPGA fabric's IOs. Add a driver for it. Signed-off-by: Conor Dooley Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 8 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-mpfs-iomux0.c | 278 ++++++++++++++++++++++++++ 3 files changed, 287 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-mpfs-iomux0.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index e83fda9bf308..4ec2bb7f67cf 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -505,6 +505,14 @@ config PINCTRL_PISTACHIO help This support pinctrl and GPIO driver for IMG Pistachio SoC. +config PINCTRL_POLARFIRE_SOC + bool "Polarfire SoC pinctrl driver" + depends on ARCH_MICROCHIP || COMPILE_TEST + select GENERIC_PINCONF + default y + help + This selects the pinctrl driver for Microchip Polarfire SoC. + config PINCTRL_RK805 tristate "Pinctrl and GPIO driver for RK805 PMIC" depends on MFD_RK8XX diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index f33976a6c91b..ea4e890766e1 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -50,6 +50,7 @@ obj-$(CONFIG_PINCTRL_PEF2256) += pinctrl-pef2256.o obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o obj-$(CONFIG_PINCTRL_PIC64GX) += pinctrl-pic64gx-gpio2.o obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o +obj-$(CONFIG_PINCTRL_POLARFIRE_SOC) += pinctrl-mpfs-iomux0.o obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o obj-$(CONFIG_PINCTRL_RP1) += pinctrl-rp1.o diff --git a/drivers/pinctrl/pinctrl-mpfs-iomux0.c b/drivers/pinctrl/pinctrl-mpfs-iomux0.c new file mode 100644 index 000000000000..49d9fcec0a16 --- /dev/null +++ b/drivers/pinctrl/pinctrl-mpfs-iomux0.c @@ -0,0 +1,278 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "core.h" +#include "pinctrl-utils.h" +#include "pinconf.h" +#include "pinmux.h" + +#define MPFS_IOMUX0_REG 0x200 + +struct mpfs_iomux0_pinctrl { + struct pinctrl_dev *pctrl; + struct device *dev; + struct regmap *regmap; + struct pinctrl_desc desc; +}; + +struct mpfs_iomux0_pin_group { + const char *name; + const unsigned int *pins; + u32 mask; + u32 setting; +}; + +struct mpfs_iomux0_function { + const char *name; + const char * const *groups; +}; + +static const struct pinctrl_pin_desc mpfs_iomux0_pins[] = { + PINCTRL_PIN(0, "spi0"), + PINCTRL_PIN(1, "spi1"), + PINCTRL_PIN(2, "i2c0"), + PINCTRL_PIN(3, "i2c1"), + PINCTRL_PIN(4, "can0"), + PINCTRL_PIN(5, "can1"), + PINCTRL_PIN(6, "qspi"), + PINCTRL_PIN(7, "uart0"), + PINCTRL_PIN(8, "uart1"), + PINCTRL_PIN(9, "uart2"), + PINCTRL_PIN(10, "uart3"), + PINCTRL_PIN(11, "uart4"), + PINCTRL_PIN(12, "mdio0"), + PINCTRL_PIN(13, "mdio1"), +}; + +static const unsigned int mpfs_iomux0_spi0_pins[] = { 0 }; +static const unsigned int mpfs_iomux0_spi1_pins[] = { 1 }; +static const unsigned int mpfs_iomux0_i2c0_pins[] = { 2 }; +static const unsigned int mpfs_iomux0_i2c1_pins[] = { 3 }; +static const unsigned int mpfs_iomux0_can0_pins[] = { 4 }; +static const unsigned int mpfs_iomux0_can1_pins[] = { 5 }; +static const unsigned int mpfs_iomux0_qspi_pins[] = { 6 }; +static const unsigned int mpfs_iomux0_uart0_pins[] = { 7 }; +static const unsigned int mpfs_iomux0_uart1_pins[] = { 8 }; +static const unsigned int mpfs_iomux0_uart2_pins[] = { 9 }; +static const unsigned int mpfs_iomux0_uart3_pins[] = { 10 }; +static const unsigned int mpfs_iomux0_uart4_pins[] = { 11 }; +static const unsigned int mpfs_iomux0_mdio0_pins[] = { 12 }; +static const unsigned int mpfs_iomux0_mdio1_pins[] = { 13 }; + +#define MPFS_IOMUX0_GROUP(_name) { \ + .name = #_name "_mssio", \ + .pins = mpfs_iomux0_##_name##_pins, \ + .mask = BIT(mpfs_iomux0_##_name##_pins[0]), \ + .setting = 0x0, \ +}, { \ + .name = #_name "_fabric", \ + .pins = mpfs_iomux0_##_name##_pins, \ + .mask = BIT(mpfs_iomux0_##_name##_pins[0]), \ + .setting = BIT(mpfs_iomux0_##_name##_pins[0]), \ +} + +static const struct mpfs_iomux0_pin_group mpfs_iomux0_pin_groups[] = { + MPFS_IOMUX0_GROUP(spi0), + MPFS_IOMUX0_GROUP(spi1), + MPFS_IOMUX0_GROUP(i2c0), + MPFS_IOMUX0_GROUP(i2c1), + MPFS_IOMUX0_GROUP(can0), + MPFS_IOMUX0_GROUP(can1), + MPFS_IOMUX0_GROUP(qspi), + MPFS_IOMUX0_GROUP(uart0), + MPFS_IOMUX0_GROUP(uart1), + MPFS_IOMUX0_GROUP(uart2), + MPFS_IOMUX0_GROUP(uart3), + MPFS_IOMUX0_GROUP(uart4), + MPFS_IOMUX0_GROUP(mdio0), + MPFS_IOMUX0_GROUP(mdio1), +}; + +static const char * const mpfs_iomux0_spi0_groups[] = { "spi0_mssio", "spi0_fabric" }; +static const char * const mpfs_iomux0_spi1_groups[] = { "spi1_mssio", "spi1_fabric" }; +static const char * const mpfs_iomux0_i2c0_groups[] = { "i2c0_mssio", "i2c0_fabric" }; +static const char * const mpfs_iomux0_i2c1_groups[] = { "i2c1_mssio", "i2c1_fabric" }; +static const char * const mpfs_iomux0_can0_groups[] = { "can0_mssio", "can0_fabric" }; +static const char * const mpfs_iomux0_can1_groups[] = { "can1_mssio", "can1_fabric" }; +static const char * const mpfs_iomux0_qspi_groups[] = { "qspi_mssio", "qspi_fabric" }; +static const char * const mpfs_iomux0_uart0_groups[] = { "uart0_mssio", "uart0_fabric" }; +static const char * const mpfs_iomux0_uart1_groups[] = { "uart1_mssio", "uart1_fabric" }; +static const char * const mpfs_iomux0_uart2_groups[] = { "uart2_mssio", "uart2_fabric" }; +static const char * const mpfs_iomux0_uart3_groups[] = { "uart3_mssio", "uart3_fabric" }; +static const char * const mpfs_iomux0_uart4_groups[] = { "uart4_mssio", "uart4_fabric" }; +static const char * const mpfs_iomux0_mdio0_groups[] = { "mdio0_mssio", "mdio0_fabric" }; +static const char * const mpfs_iomux0_mdio1_groups[] = { "mdio1_mssio", "mdio1_fabric" }; + +#define MPFS_IOMUX0_FUNCTION(_name) { \ + .name = #_name, \ + .groups = mpfs_iomux0_##_name##_groups, \ +} + +static const struct mpfs_iomux0_function mpfs_iomux0_functions[] = { + MPFS_IOMUX0_FUNCTION(spi0), + MPFS_IOMUX0_FUNCTION(spi1), + MPFS_IOMUX0_FUNCTION(i2c0), + MPFS_IOMUX0_FUNCTION(i2c1), + MPFS_IOMUX0_FUNCTION(can0), + MPFS_IOMUX0_FUNCTION(can1), + MPFS_IOMUX0_FUNCTION(qspi), + MPFS_IOMUX0_FUNCTION(uart0), + MPFS_IOMUX0_FUNCTION(uart1), + MPFS_IOMUX0_FUNCTION(uart2), + MPFS_IOMUX0_FUNCTION(uart3), + MPFS_IOMUX0_FUNCTION(uart4), + MPFS_IOMUX0_FUNCTION(mdio0), + MPFS_IOMUX0_FUNCTION(mdio1), +}; + +static void mpfs_iomux0_pin_dbg_show(struct pinctrl_dev *pctrl_dev, struct seq_file *seq, + unsigned int pin) +{ + struct mpfs_iomux0_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev); + u32 val; + + seq_printf(seq, "reg: %x, pin: %u ", MPFS_IOMUX0_REG, pin); + + regmap_read(pctrl->regmap, MPFS_IOMUX0_REG, &val); + val = (val & BIT(pin)) >> pin; + + seq_printf(seq, "val: %x\n", val); +} + +static int mpfs_iomux0_groups_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(mpfs_iomux0_pin_groups); +} + +static const char *mpfs_iomux0_group_name(struct pinctrl_dev *pctldev, unsigned int selector) +{ + return mpfs_iomux0_pin_groups[selector].name; +} + +static int mpfs_iomux0_group_pins(struct pinctrl_dev *pctldev, unsigned int selector, + const unsigned int **pins, unsigned int *num_pins) +{ + *pins = mpfs_iomux0_pin_groups[selector].pins; + *num_pins = 1; + + return 0; +} + +static const struct pinctrl_ops mpfs_iomux0_pinctrl_ops = { + .get_groups_count = mpfs_iomux0_groups_count, + .get_group_name = mpfs_iomux0_group_name, + .get_group_pins = mpfs_iomux0_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, + .dt_free_map = pinctrl_utils_free_map, + .pin_dbg_show = mpfs_iomux0_pin_dbg_show, +}; + +static int mpfs_iomux0_pinmux_set_mux(struct pinctrl_dev *pctrl_dev, unsigned int fsel, + unsigned int gsel) +{ + struct mpfs_iomux0_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev); + struct device *dev = pctrl->dev; + const struct mpfs_iomux0_pin_group *group; + const struct mpfs_iomux0_function *function; + + group = &mpfs_iomux0_pin_groups[gsel]; + function = &mpfs_iomux0_functions[fsel]; + + dev_dbg(dev, "Setting func %s mask %x setting %x\n", + function->name, group->mask, group->setting); + regmap_assign_bits(pctrl->regmap, MPFS_IOMUX0_REG, group->mask, group->setting); + + return 0; +} + +static int mpfs_iomux0_pinmux_get_funcs_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(mpfs_iomux0_functions); +} + +static const char *mpfs_iomux0_pinmux_get_func_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return mpfs_iomux0_functions[selector].name; +} + +static int mpfs_iomux0_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned int selector, + const char * const **groups, + unsigned int * const num_groups) +{ + *groups = mpfs_iomux0_functions[selector].groups; + *num_groups = 2; + + return 0; +} + +static const struct pinmux_ops mpfs_iomux0_pinmux_ops = { + .get_functions_count = mpfs_iomux0_pinmux_get_funcs_count, + .get_function_name = mpfs_iomux0_pinmux_get_func_name, + .get_function_groups = mpfs_iomux0_pinmux_get_groups, + .set_mux = mpfs_iomux0_pinmux_set_mux, +}; + +static int mpfs_iomux0_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mpfs_iomux0_pinctrl *pctrl; + + pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + pctrl->regmap = device_node_to_regmap(pdev->dev.parent->of_node); + if (IS_ERR(pctrl->regmap)) + dev_err_probe(dev, PTR_ERR(pctrl->regmap), "Failed to find syscon regmap\n"); + + pctrl->desc.name = dev_name(dev); + pctrl->desc.pins = mpfs_iomux0_pins; + pctrl->desc.npins = ARRAY_SIZE(mpfs_iomux0_pins); + pctrl->desc.pctlops = &mpfs_iomux0_pinctrl_ops; + pctrl->desc.pmxops = &mpfs_iomux0_pinmux_ops; + pctrl->desc.owner = THIS_MODULE; + + pctrl->dev = dev; + + platform_set_drvdata(pdev, pctrl); + + pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); + if (IS_ERR(pctrl->pctrl)) + return PTR_ERR(pctrl->pctrl); + + return 0; +} + +static const struct of_device_id mpfs_iomux0_of_match[] = { + { .compatible = "microchip,mpfs-pinctrl-iomux0" }, + { } +}; +MODULE_DEVICE_TABLE(of, mpfs_iomux0_of_match); + +static struct platform_driver mpfs_iomux0_driver = { + .driver = { + .name = "mpfs-pinctrl-iomux0", + .of_match_table = mpfs_iomux0_of_match, + }, + .probe = mpfs_iomux0_probe, +}; +module_platform_driver(mpfs_iomux0_driver); + +MODULE_AUTHOR("Conor Dooley "); +MODULE_DESCRIPTION("Polarfire SoC iomux0 pinctrl driver"); +MODULE_LICENSE("GPL"); From e5cea3c87c3f92c1d7193e0b8eb9ef139ce8d4d6 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Thu, 23 Oct 2025 18:15:01 +0100 Subject: [PATCH 040/107] MAINTAINERS: add Microchip RISC-V pinctrl drivers/bindings to entry Add the new gpio2 and iomux0 drivers and bindings to the existing entry for Microchip RISC-V devices. Signed-off-by: Conor Dooley Signed-off-by: Linus Walleij --- MAINTAINERS | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index bdbcd05095b1..181a58ec4a8d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22089,6 +22089,8 @@ F: Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml F: Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml F: Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml F: Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml +F: Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml +F: Documentation/devicetree/bindings/pinctrl/microchip,pic64gx-pinctrl-gpio2.yaml F: Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml F: Documentation/devicetree/bindings/riscv/microchip.yaml F: Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml @@ -22102,6 +22104,8 @@ F: drivers/gpio/gpio-mpfs.c F: drivers/i2c/busses/i2c-microchip-corei2c.c F: drivers/mailbox/mailbox-mpfs.c F: drivers/pci/controller/plda/pcie-microchip-host.c +F: drivers/pinctrl/pinctrl-mpfs-iomux0.c +F: drivers/pinctrl/pinctrl-pic64gx-gpio2.c F: drivers/pwm/pwm-microchip-core.c F: drivers/reset/reset-mpfs.c F: drivers/rtc/rtc-mpfs.c From a5fad3aeff41f89ac94230d66ee5f9c1526cb3ce Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Wed, 22 Oct 2025 10:40:58 +0300 Subject: [PATCH 041/107] pinctrl: renesas: rzg2l: Remove useless wrappers rzg2l_gpio_irq_set_type() and rzg2l_gpio_irqc_eoi() only call the equivalent parent functions, replace their usage with the parent functions and remove them. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251022074100.1994447-1-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 947bce7bfc0e..f25ecada5c69 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -2494,16 +2494,6 @@ static void rzg2l_gpio_irq_enable(struct irq_data *d) __rzg2l_gpio_irq_enable(d, true); } -static int rzg2l_gpio_irq_set_type(struct irq_data *d, unsigned int type) -{ - return irq_chip_set_type_parent(d, type); -} - -static void rzg2l_gpio_irqc_eoi(struct irq_data *d) -{ - irq_chip_eoi_parent(d); -} - static void rzg2l_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p) { struct gpio_chip *gc = irq_data_get_irq_chip_data(data); @@ -2539,8 +2529,8 @@ static const struct irq_chip rzg2l_gpio_irqchip = { .irq_enable = rzg2l_gpio_irq_enable, .irq_mask = irq_chip_mask_parent, .irq_unmask = irq_chip_unmask_parent, - .irq_set_type = rzg2l_gpio_irq_set_type, - .irq_eoi = rzg2l_gpio_irqc_eoi, + .irq_set_type = irq_chip_set_type_parent, + .irq_eoi = irq_chip_eoi_parent, .irq_print_chip = rzg2l_gpio_irq_print_chip, .irq_set_affinity = irq_chip_set_affinity_parent, .irq_set_wake = rzg2l_gpio_irq_set_wake, @@ -2640,7 +2630,7 @@ static void rzg2l_gpio_irq_restore(struct rzg2l_pinctrl *pctrl) * interrupt. */ raw_spin_lock_irqsave(&pctrl->lock, flags); - ret = rzg2l_gpio_irq_set_type(data, irqd_get_trigger_type(data)); + ret = irq_chip_set_type_parent(data, irqd_get_trigger_type(data)); if (!ret && !irqd_irq_disabled(data)) __rzg2l_gpio_irq_enable(data, false); raw_spin_unlock_irqrestore(&pctrl->lock, flags); From 329b71cd1e9e975583d772e1741c676bb2ddad2c Mon Sep 17 00:00:00 2001 From: Gary Yang Date: Tue, 21 Oct 2025 15:04:08 +0800 Subject: [PATCH 042/107] dt-bindings: pinctrl: Add cix,sky1-pinctrl The pin-controller is used to control the Soc pins. There are two pin-controllers on Cix Sky1 platform. One is used under S0 state, the other is used under S0 and S5 state. Signed-off-by: Gary Yang Reviewed-by: Conor Dooley Signed-off-by: Linus Walleij --- .../bindings/pinctrl/cix,sky1-pinctrl.yaml | 92 +++++++++++++++++++ 1 file changed, 92 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml new file mode 100644 index 000000000000..36977b0d745b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/cix,sky1-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cix Sky1 Soc Pin Controller + +maintainers: + - Gary Yang + +description: + The pin-controller is used to control Soc pins. There are two pin-controllers + on Cix Sky1 platform. one is used under S0 state, the other one is used under + S0 and S5 state. + +properties: + compatible: + enum: + - cix,sky1-pinctrl + - cix,sky1-pinctrl-s5 + + reg: + items: + - description: gpio base + +patternProperties: + '-cfg$': + type: object + additionalProperties: false + + description: + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. + + patternProperties: + 'pins$': + type: object + additionalProperties: false + + description: + Each subnode will list the pins it needs, and how they should + be configured, with regard to muxer configuration, bias pull, + and drive strength. + + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + pinmux: + description: + Values are constructed from pin number and mux setting, pin + number is left shifted by 8 bits, then ORed with mux setting + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + drive-strength: + description: + typical current when output high level. + enum: [ 2, 3, 5, 6, 8, 9, 11, 12, 13, 14, 17, 18, 20, 21, 23, + 24 ] + + + required: + - pinmux + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #define CIX_PAD_GPIO012_FUNC_GPIO012 (11 << 8 | 0x0) + pinctrl@4170000 { + compatible = "cix,sky1-pinctrl"; + reg = <0x4170000 0x1000>; + + wifi_vbat_gpio: wifi-vbat-gpio-cfg { + pins { + pinmux = ; + bias-pull-up; + drive-strength = <8>; + }; + }; + }; From 920500c5fe66168f138be7f66089e8c8547694f1 Mon Sep 17 00:00:00 2001 From: Gary Yang Date: Tue, 21 Oct 2025 15:04:09 +0800 Subject: [PATCH 043/107] pinctrl: cix: Add pin-controller support for sky1 There are two pin-controllers on Cix Sky1 platform. one is used under S0 state, the other is used under S0 and S5 state. Signed-off-by: Gary Yang [Dropped pinctrl_provide_dummies()] Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/cix/Kconfig | 14 + drivers/pinctrl/cix/Makefile | 4 + drivers/pinctrl/cix/pinctrl-sky1-base.c | 572 ++++++++++++++++++++++++ drivers/pinctrl/cix/pinctrl-sky1.c | 559 +++++++++++++++++++++++ drivers/pinctrl/cix/pinctrl-sky1.h | 48 ++ 7 files changed, 1199 insertions(+) create mode 100644 drivers/pinctrl/cix/Kconfig create mode 100644 drivers/pinctrl/cix/Makefile create mode 100644 drivers/pinctrl/cix/pinctrl-sky1-base.c create mode 100644 drivers/pinctrl/cix/pinctrl-sky1.c create mode 100644 drivers/pinctrl/cix/pinctrl-sky1.h diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 4ec2bb7f67cf..2e590913fa44 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -702,6 +702,7 @@ source "drivers/pinctrl/aspeed/Kconfig" source "drivers/pinctrl/bcm/Kconfig" source "drivers/pinctrl/berlin/Kconfig" source "drivers/pinctrl/cirrus/Kconfig" +source "drivers/pinctrl/cix/Kconfig" source "drivers/pinctrl/freescale/Kconfig" source "drivers/pinctrl/intel/Kconfig" source "drivers/pinctrl/mediatek/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index ea4e890766e1..be5200c23e60 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -71,6 +71,7 @@ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-y += bcm/ obj-$(CONFIG_PINCTRL_BERLIN) += berlin/ obj-y += cirrus/ +obj-y += cix/ obj-y += freescale/ obj-$(CONFIG_X86) += intel/ obj-y += mediatek/ diff --git a/drivers/pinctrl/cix/Kconfig b/drivers/pinctrl/cix/Kconfig new file mode 100644 index 000000000000..455120dd7318 --- /dev/null +++ b/drivers/pinctrl/cix/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only +config PINCTRL_SKY1_BASE + tristate + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + select REGMAP + +config PINCTRL_SKY1 + tristate "Cix Sky1 pinctrl driver" + depends on ARCH_CIX || COMPILE_TEST + select PINCTRL_SKY1_BASE + help + Say Y here to enable the sky1 pinctrl driver diff --git a/drivers/pinctrl/cix/Makefile b/drivers/pinctrl/cix/Makefile new file mode 100644 index 000000000000..22685d6a107b --- /dev/null +++ b/drivers/pinctrl/cix/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 +# Cix Sky1 pin control drivers +obj-$(CONFIG_PINCTRL_SKY1_BASE) += pinctrl-sky1-base.o +obj-$(CONFIG_PINCTRL_SKY1) += pinctrl-sky1.o diff --git a/drivers/pinctrl/cix/pinctrl-sky1-base.c b/drivers/pinctrl/cix/pinctrl-sky1-base.c new file mode 100644 index 000000000000..b03e10147b09 --- /dev/null +++ b/drivers/pinctrl/cix/pinctrl-sky1-base.c @@ -0,0 +1,572 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Author: Jerry Zhu +// Author: Gary Yang + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../core.h" +#include "../pinconf.h" +#include "../pinctrl-utils.h" +#include "../pinmux.h" +#include "pinctrl-sky1.h" + +#define SKY1_PIN_SIZE (4) +#define SKY1_MUX_MASK GENMASK(8, 7) +#define SKY1_MUX_SHIFT (7) +#define SKY1_PULLCONF_MASK GENMASK(6, 5) +#define SKY1_PULLUP_BIT (6) +#define SKY1_PULLDN_BIT (5) +#define SKY1_DS_MASK GENMASK(3, 0) + +#define CIX_PIN_NO_SHIFT (8) +#define CIX_PIN_FUN_MASK GENMASK(1, 0) +#define CIX_GET_PIN_NO(x) ((x) >> CIX_PIN_NO_SHIFT) +#define CIX_GET_PIN_FUNC(x) ((x) & CIX_PIN_FUN_MASK) +#define SKY1_DEFAULT_DS_VAL (4) + +static const char * const sky1_gpio_functions[] = { + "func0", "func1", "func2", "func3", +}; + +static unsigned char sky1_ds_table[] = { + 2, 3, 5, 6, 8, 9, 11, 12, 13, 14, 17, 18, 20, 21, 23, 24, +}; + +static bool sky1_pctrl_is_function_valid(struct sky1_pinctrl *spctl, + u32 pin_num, u32 fnum) +{ + int i; + + for (i = 0; i < spctl->info->npins; i++) { + const struct sky1_pin_desc *pin = spctl->info->pins + i; + + if (pin->pin.number == pin_num) { + if (fnum < pin->nfunc) + return true; + + break; + } + } + + return false; +} + +static int sky1_pctrl_dt_node_to_map_func(struct sky1_pinctrl *spctl, + u32 pin, u32 fnum, struct sky1_pinctrl_group *grp, + struct pinctrl_map **map, unsigned int *reserved_maps, + unsigned int *num_maps) +{ + bool ret; + + if (*num_maps == *reserved_maps) + return -ENOSPC; + + (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[*num_maps].data.mux.group = grp->name; + + ret = sky1_pctrl_is_function_valid(spctl, pin, fnum); + if (!ret) { + dev_err(spctl->dev, "invalid function %d on pin %d .\n", + fnum, pin); + return -EINVAL; + } + + (*map)[*num_maps].data.mux.function = sky1_gpio_functions[fnum]; + (*num_maps)++; + + return 0; +} + +static struct sky1_pinctrl_group * +sky1_pctrl_find_group_by_pin(struct sky1_pinctrl *spctl, u32 pin) +{ + int i; + + for (i = 0; i < spctl->info->npins; i++) { + struct sky1_pinctrl_group *grp = + (struct sky1_pinctrl_group *)spctl->groups + i; + + if (grp->pin == pin) + return grp; + } + + return NULL; +} + +static int sky1_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, + struct device_node *node, + struct pinctrl_map **map, + unsigned int *reserved_maps, + unsigned int *num_maps) +{ + struct property *pins; + u32 pinfunc, pin, func; + int num_pins, num_funcs, maps_per_pin; + unsigned long *configs; + unsigned int num_configs; + bool has_config = false; + int i, err; + unsigned int reserve = 0; + struct sky1_pinctrl_group *grp; + struct sky1_pinctrl *spctl = pinctrl_dev_get_drvdata(pctldev); + + pins = of_find_property(node, "pinmux", NULL); + if (!pins) { + dev_err(spctl->dev, "missing pins property in node %pOFn .\n", + node); + return -EINVAL; + } + + err = pinconf_generic_parse_dt_config(node, pctldev, &configs, + &num_configs); + if (err) + return err; + + if (num_configs) + has_config = true; + + num_pins = pins->length / sizeof(u32); + num_funcs = num_pins; + maps_per_pin = 0; + if (num_funcs) + maps_per_pin++; + if (has_config && num_pins >= 1) + maps_per_pin++; + + if (!num_pins || !maps_per_pin) { + err = -EINVAL; + goto exit; + } + + reserve = num_pins * maps_per_pin; + + err = pinctrl_utils_reserve_map(pctldev, map, + reserved_maps, num_maps, reserve); + if (err < 0) + goto exit; + + for (i = 0; i < num_pins; i++) { + err = of_property_read_u32_index(node, "pinmux", + i, &pinfunc); + if (err) + goto exit; + + pin = CIX_GET_PIN_NO(pinfunc); + func = CIX_GET_PIN_FUNC(pinfunc); + pctldev->num_functions = ARRAY_SIZE(sky1_gpio_functions); + + if (pin >= pctldev->desc->npins || + func >= pctldev->num_functions) { + dev_err(spctl->dev, "invalid pins value.\n"); + err = -EINVAL; + goto exit; + } + + grp = sky1_pctrl_find_group_by_pin(spctl, pin); + if (!grp) { + dev_err(spctl->dev, "unable to match pin %d to group\n", + pin); + err = -EINVAL; + goto exit; + } + + err = sky1_pctrl_dt_node_to_map_func(spctl, pin, func, grp, + map, reserved_maps, num_maps); + if (err < 0) + goto exit; + + if (has_config) { + err = pinctrl_utils_add_map_configs(pctldev, map, + reserved_maps, num_maps, grp->name, + configs, num_configs, + PIN_MAP_TYPE_CONFIGS_GROUP); + if (err < 0) + goto exit; + } + } + + err = 0; + +exit: + kfree(configs); + return err; +} + +static int sky1_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, unsigned int *num_maps) +{ + unsigned int reserved_maps; + int ret; + + *map = NULL; + *num_maps = 0; + reserved_maps = 0; + + for_each_child_of_node_scoped(np_config, np) { + ret = sky1_pctrl_dt_subnode_to_map(pctldev, np, map, + &reserved_maps, num_maps); + if (ret < 0) { + pinctrl_utils_free_map(pctldev, *map, *num_maps); + return ret; + } + } + + return 0; +} + +static void sky1_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, + unsigned int num_maps) +{ + kfree(map); +} + +static int sky1_pctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct sky1_pinctrl *spctl = pinctrl_dev_get_drvdata(pctldev); + + return spctl->info->npins; +} + +static const char *sky1_pctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned int group) +{ + struct sky1_pinctrl *spctl = pinctrl_dev_get_drvdata(pctldev); + + return spctl->groups[group].name; +} + +static int sky1_pctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int group, + const unsigned int **pins, + unsigned int *num_pins) +{ + struct sky1_pinctrl *spctl = pinctrl_dev_get_drvdata(pctldev); + + *pins = (unsigned int *)&spctl->groups[group].pin; + *num_pins = 1; + + return 0; +} + +static void sky1_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, + unsigned int offset) +{ + seq_printf(s, "%s", dev_name(pctldev->dev)); +} + +static const struct pinctrl_ops sky1_pctrl_ops = { + .dt_node_to_map = sky1_pctrl_dt_node_to_map, + .dt_free_map = sky1_dt_free_map, + .get_groups_count = sky1_pctrl_get_groups_count, + .get_group_name = sky1_pctrl_get_group_name, + .get_group_pins = sky1_pctrl_get_group_pins, + .pin_dbg_show = sky1_pin_dbg_show, +}; + +static int sky1_pmx_set_one_pin(struct sky1_pinctrl *spctl, + unsigned int pin, unsigned char muxval) +{ + u32 reg_val; + void __iomem *pin_reg; + + pin_reg = spctl->base + pin * SKY1_PIN_SIZE; + reg_val = readl(pin_reg); + reg_val &= ~SKY1_MUX_MASK; + reg_val |= muxval << SKY1_MUX_SHIFT; + writel(reg_val, pin_reg); + + dev_dbg(spctl->dev, "write: offset 0x%x val 0x%x\n", + pin * SKY1_PIN_SIZE, reg_val); + return 0; +} + +static int sky1_pmx_set_mux(struct pinctrl_dev *pctldev, + unsigned int function, + unsigned int group) +{ + bool ret; + struct sky1_pinctrl *spctl = pinctrl_dev_get_drvdata(pctldev); + struct sky1_pinctrl_group *g = + (struct sky1_pinctrl_group *)spctl->groups + group; + + ret = sky1_pctrl_is_function_valid(spctl, g->pin, function); + if (!ret) { + dev_err(spctl->dev, "invalid function %d on group %d .\n", + function, group); + return -EINVAL; + } + + sky1_pmx_set_one_pin(spctl, g->pin, function); + return 0; +} + +static int sky1_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(sky1_gpio_functions); +} + +static const char *sky1_pmx_get_func_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return sky1_gpio_functions[selector]; +} + +static int sky1_pmx_get_func_groups(struct pinctrl_dev *pctldev, + unsigned int function, + const char * const **groups, + unsigned int * const num_groups) +{ + struct sky1_pinctrl *spctl = pinctrl_dev_get_drvdata(pctldev); + const struct sky1_pinctrl_soc_info *info = spctl->info; + + *groups = spctl->grp_names; + *num_groups = info->npins; + + return 0; +} + +static const struct pinmux_ops sky1_pmx_ops = { + .get_functions_count = sky1_pmx_get_funcs_cnt, + .get_function_groups = sky1_pmx_get_func_groups, + .get_function_name = sky1_pmx_get_func_name, + .set_mux = sky1_pmx_set_mux, +}; + +static int sky1_pconf_set_pull_select(struct sky1_pinctrl *spctl, + unsigned int pin, bool enable, bool isup) +{ + u32 reg_val, reg_pullsel = 0; + void __iomem *pin_reg; + + pin_reg = spctl->base + pin * SKY1_PIN_SIZE; + reg_val = readl(pin_reg); + reg_val &= ~SKY1_PULLCONF_MASK; + + if (!enable) + goto update; + + if (isup) + reg_pullsel = BIT(SKY1_PULLUP_BIT); + else + reg_pullsel = BIT(SKY1_PULLDN_BIT); + +update: + reg_val |= reg_pullsel; + writel(reg_val, pin_reg); + + dev_dbg(spctl->dev, "write: offset 0x%x val 0x%x\n", + pin * SKY1_PIN_SIZE, reg_val); + return 0; +} + +static int sky1_ds_to_index(unsigned char driving) +{ + int i; + + for (i = 0; i < sizeof(sky1_ds_table); i++) + if (driving == sky1_ds_table[i]) + return i; + return SKY1_DEFAULT_DS_VAL; +} + +static int sky1_pconf_set_driving(struct sky1_pinctrl *spctl, + unsigned int pin, unsigned char driving) +{ + unsigned int reg_val, val; + void __iomem *pin_reg; + + if (pin >= spctl->info->npins) + return -EINVAL; + + pin_reg = spctl->base + pin * SKY1_PIN_SIZE; + reg_val = readl(pin_reg); + reg_val &= ~SKY1_DS_MASK; + val = sky1_ds_to_index(driving); + reg_val |= (val & SKY1_DS_MASK); + writel(reg_val, pin_reg); + + dev_dbg(spctl->dev, "write: offset 0x%x val 0x%x\n", + pin * SKY1_PIN_SIZE, reg_val); + + return 0; +} + +static int sky1_pconf_parse_conf(struct pinctrl_dev *pctldev, + unsigned int pin, enum pin_config_param param, + enum pin_config_param arg) +{ + int ret = 0; + struct sky1_pinctrl *spctl = pinctrl_dev_get_drvdata(pctldev); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + ret = sky1_pconf_set_pull_select(spctl, pin, false, false); + break; + case PIN_CONFIG_BIAS_PULL_UP: + ret = sky1_pconf_set_pull_select(spctl, pin, true, true); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + ret = sky1_pconf_set_pull_select(spctl, pin, true, false); + break; + case PIN_CONFIG_DRIVE_STRENGTH: + ret = sky1_pconf_set_driving(spctl, pin, arg); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static int sky1_pconf_group_get(struct pinctrl_dev *pctldev, + unsigned int group, + unsigned long *config) +{ + struct sky1_pinctrl *spctl = pinctrl_dev_get_drvdata(pctldev); + struct sky1_pinctrl_group *g = &spctl->groups[group]; + + *config = g->config; + + return 0; +} + +static int sky1_pconf_group_set(struct pinctrl_dev *pctldev, unsigned int group, + unsigned long *configs, unsigned int num_configs) +{ + struct sky1_pinctrl *spctl = pinctrl_dev_get_drvdata(pctldev); + struct sky1_pinctrl_group *g = &spctl->groups[group]; + int i, ret; + + for (i = 0; i < num_configs; i++) { + ret = sky1_pconf_parse_conf(pctldev, g->pin, + pinconf_to_config_param(configs[i]), + pinconf_to_config_argument(configs[i])); + if (ret < 0) + return ret; + + g->config = configs[i]; + } + + return 0; +} + +static const struct pinconf_ops sky1_pinconf_ops = { + .pin_config_group_get = sky1_pconf_group_get, + .pin_config_group_set = sky1_pconf_group_set, +}; + +static int sky1_pctrl_build_state(struct platform_device *pdev) +{ + struct sky1_pinctrl *spctl = platform_get_drvdata(pdev); + const struct sky1_pinctrl_soc_info *info = spctl->info; + int i; + + /* Allocate groups */ + spctl->groups = devm_kcalloc(&pdev->dev, info->npins, + sizeof(*spctl->groups), GFP_KERNEL); + if (!spctl->groups) + return -ENOMEM; + + /* We assume that one pin is one group, use pin name as group name. */ + spctl->grp_names = devm_kcalloc(&pdev->dev, info->npins, + sizeof(*spctl->grp_names), GFP_KERNEL); + if (!spctl->grp_names) + return -ENOMEM; + + for (i = 0; i < info->npins; i++) { + const struct sky1_pin_desc *pin = spctl->info->pins + i; + struct sky1_pinctrl_group *group = + (struct sky1_pinctrl_group *)spctl->groups + i; + + group->name = pin->pin.name; + group->pin = pin->pin.number; + spctl->grp_names[i] = pin->pin.name; + } + + return 0; +} + +int sky1_base_pinctrl_probe(struct platform_device *pdev, + const struct sky1_pinctrl_soc_info *info) +{ + struct pinctrl_desc *sky1_pinctrl_desc; + struct sky1_pinctrl *spctl; + struct pinctrl_pin_desc *pins; + int ret, i; + + if (!info || !info->pins || !info->npins) { + dev_err(&pdev->dev, "wrong pinctrl info\n"); + return -EINVAL; + } + + /* Create state holders etc for this driver */ + spctl = devm_kzalloc(&pdev->dev, sizeof(*spctl), GFP_KERNEL); + if (!spctl) + return -ENOMEM; + + spctl->info = info; + platform_set_drvdata(pdev, spctl); + + spctl->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(spctl->base)) + return PTR_ERR(spctl->base); + + sky1_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*sky1_pinctrl_desc), + GFP_KERNEL); + if (!sky1_pinctrl_desc) + return -ENOMEM; + + pins = devm_kcalloc(&pdev->dev, info->npins, sizeof(*pins), + GFP_KERNEL); + if (!pins) + return -ENOMEM; + for (i = 0; i < info->npins; i++) + pins[i] = info->pins[i].pin; + + ret = sky1_pctrl_build_state(pdev); + if (ret) + return ret; + + sky1_pinctrl_desc->name = dev_name(&pdev->dev); + sky1_pinctrl_desc->pins = pins; + sky1_pinctrl_desc->npins = info->npins; + sky1_pinctrl_desc->pctlops = &sky1_pctrl_ops; + sky1_pinctrl_desc->pmxops = &sky1_pmx_ops; + sky1_pinctrl_desc->confops = &sky1_pinconf_ops; + sky1_pinctrl_desc->owner = THIS_MODULE; + spctl->dev = &pdev->dev; + ret = devm_pinctrl_register_and_init(&pdev->dev, + sky1_pinctrl_desc, spctl, + &spctl->pctl); + if (ret) { + dev_err(&pdev->dev, "could not register SKY1 pinctrl driver\n"); + return ret; + } + + dev_dbg(&pdev->dev, "initialized SKY1 pinctrl driver\n"); + + return pinctrl_enable(spctl->pctl); +} +EXPORT_SYMBOL_GPL(sky1_base_pinctrl_probe); + + +MODULE_AUTHOR("Jerry Zhu "); +MODULE_DESCRIPTION("Cix SKy1 pinctrl base driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/cix/pinctrl-sky1.c b/drivers/pinctrl/cix/pinctrl-sky1.c new file mode 100644 index 000000000000..5d0d8be815b2 --- /dev/null +++ b/drivers/pinctrl/cix/pinctrl-sky1.c @@ -0,0 +1,559 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Author: Jerry Zhu +// Author: Gary Yang + +#include +#include +#include +#include +#include +#include +#include +#include "linux/stddef.h" + +#include "../core.h" +#include "pinctrl-sky1.h" + +/* Pad names for the s5 domain pinmux subsystem */ +static const char * const gpio1_group[] = {"GPIO1"}; +static const char * const gpio2_group[] = {"GPIO2"}; +static const char * const gpio3_group[] = {"GPIO3"}; +static const char * const gpio4_group[] = {"GPIO4"}; +static const char * const gpio5_group[] = {"GPIO5"}; +static const char * const gpio6_group[] = {"GPIO6"}; +static const char * const gpio7_group[] = {"GPIO7"}; +static const char * const gpio8_group[] = {"GPIO8"}; +static const char * const gpio9_group[] = {"GPIO9"}; +static const char * const gpio10_group[] = {"GPIO10"}; +static const char * const gpio11_group[] = {"GPIO11"}; +static const char * const gpio12_group[] = {"GPIO12"}; +static const char * const gpio13_group[] = {"GPIO13"}; +static const char * const gpio14_group[] = {"GPIO14"}; +static const char * const rsmrst_group[] = { }; +static const char * const srst_group[] = { }; +static const char * const slp_s3_group[] = { }; +static const char * const slp_s5_group[] = { }; +static const char * const pwrgd_group[] = { }; +static const char * const pwrok_group[] = { }; +static const char * const pwrbtn_group[] = { }; +static const char * const ddrio_gate_group[] = { }; +static const char * const jtag_gpio_group[] = { }; +static const char * const jtag_tck_group[] = { }; +static const char * const jtag_tdi_group[] = { }; +static const char * const jtag_tdo_group[] = { }; +static const char * const tms_group[] = { }; +static const char * const trsl_group[] = { }; +static const char * const sfi_i2c0_scl_group[] = {"SFI_I2C0_SCL", + "SFI_I3C0_SCL"}; +static const char * const sfi_i2c0_sda_group[] = {"SFI_I2C0_SDA", + "SFI_I3C0_SDA"}; +static const char * const sfi_i2c1_scl_group[] = {"SFI_I2C1_SCL", + "SFI_I3C1_SCL", "SFI_SPI_CS0"}; +static const char * const sfi_i2c1_sda_group[] = {"SFI_I2C1_SDA", + "SFI_I3C1_SDA", "SFI_SPI_CS1"}; +static const char * const sfi_gpio0_group[] = {"GPIO15", "SFI_SPI_SCK", + "SFI_GPIO0"}; +static const char * const sfi_gpio1_group[] = {"GPIO16", "SFI_SPI_MOSI", + "SFI_GPIO1"}; +static const char * const sfi_gpio2_group[] = {"GPIO17", "SFI_SPI_MISO", + "SFI_GPIO2"}; +static const char * const gpio18_group[] = {"SFI_GPIO3", "GPIO18"}; +static const char * const gpio19_group[] = {"SFI_GPIO4", "GPIO19"}; +static const char * const gpio20_group[] = {"SFI_GPIO5", "GPIO20"}; +static const char * const gpio21_group[] = {"SFI_GPIO6", "GPIO21"}; +static const char * const gpio22_group[] = {"SFI_GPIO7", "GPIO22"}; +static const char * const gpio23_group[] = {"SFI_GPIO8", "GPIO23", + "SFI_I3C0_PUR_EN_L"}; +static const char * const gpio24_group[] = {"SFI_GPIO9", "GPIO24", + "SFI_I3C1_PUR_EN_L"}; +static const char * const spi1_miso_group[] = {"SPI1_MISO", "GPIO25"}; +static const char * const spi1_cs0_group[] = {"SPI1_CS0", "GPIO26"}; +static const char * const spi1_cs1_group[] = {"SPI1_CS1", "GPIO27"}; +static const char * const spi1_mosi_group[] = {"SPI1_MOSI", "GPIO28"}; +static const char * const spi1_clk_group[] = {"SPI1_CLK", "GPIO29"}; +static const char * const gpio30_group[] = {"GPIO30", "USB_0C0_L"}; +static const char * const gpio31_group[] = {"GPIO31", "USB_0C1_L"}; +static const char * const gpio32_group[] = {"GPIO32", "USB_0C2_L"}; +static const char * const gpio33_group[] = {"GPIO33", "USB_0C3_L"}; +static const char * const gpio34_group[] = {"GPIO34", "USB_0C4_L"}; +static const char * const gpio35_group[] = {"GPIO35", "USB_0C5_L"}; +static const char * const gpio36_group[] = {"GPIO36", "USB_0C6_L"}; +static const char * const gpio37_group[] = {"GPIO37", "USB_0C7_L"}; +static const char * const gpio38_group[] = {"GPIO38", "USB_0C8_L"}; +static const char * const gpio39_group[] = {"GPIO39", "USB_0C9_L"}; +static const char * const gpio40_group[] = {"GPIO40", "USB_DRIVE_VBUS0"}; +static const char * const gpio41_group[] = {"GPIO41", "USB_DRIVE_VBUS4"}; +static const char * const gpio42_group[] = {"GPIO42", "USB_DRIVE_VBUS5"}; +static const char * const se_qspi_clk_group[] = {"SE_QSPI_CLK", "QSPI_CLK"}; +static const char * const se_qspi_cs_group[] = {"SE_QSPI_CS_L", "QSPI_CS_L"}; +static const char * const se_qspi_data0_group[] = {"SE_QSPI_DATA0", + "QSPI_DATA0"}; +static const char * const se_qspi_data1_group[] = {"SE_QSPI_DATA1", + "QSPI_DATA1"}; +static const char * const se_qspi_data2_group[] = {"SE_QSPI_DATA2", + "QSPI_DATA2"}; +static const char * const se_qspi_data3_group[] = {"SE_QSPI_DATA3", + "QSPI_DATA3"}; +static const struct sky1_pin_desc sky1_pinctrl_s5_pads[] = { + SKY_PINFUNCTION(PINCTRL_PIN(0, "GPIO1"), gpio1), + SKY_PINFUNCTION(PINCTRL_PIN(1, "GPIO2"), gpio2), + SKY_PINFUNCTION(PINCTRL_PIN(2, "GPIO3"), gpio3), + SKY_PINFUNCTION(PINCTRL_PIN(3, "GPIO4"), gpio4), + SKY_PINFUNCTION(PINCTRL_PIN(4, "GPIO5"), gpio5), + SKY_PINFUNCTION(PINCTRL_PIN(5, "GPIO6"), gpio6), + SKY_PINFUNCTION(PINCTRL_PIN(6, "GPIO7"), gpio7), + SKY_PINFUNCTION(PINCTRL_PIN(7, "GPIO8"), gpio8), + SKY_PINFUNCTION(PINCTRL_PIN(8, "GPIO9"), gpio9), + SKY_PINFUNCTION(PINCTRL_PIN(9, "GPIO10"), gpio10), + SKY_PINFUNCTION(PINCTRL_PIN(10, "GPIO11"), gpio11), + SKY_PINFUNCTION(PINCTRL_PIN(11, "GPIO12"), gpio12), + SKY_PINFUNCTION(PINCTRL_PIN(12, "GPIO13"), gpio13), + SKY_PINFUNCTION(PINCTRL_PIN(13, "GPIO14"), gpio14), + SKY_PINFUNCTION(PINCTRL_PIN(14, "RSMRST_L"), rsmrst), + SKY_PINFUNCTION(PINCTRL_PIN(15, "SRST_L"), srst), + SKY_PINFUNCTION(PINCTRL_PIN(16, "SLP_S3_L"), slp_s3), + SKY_PINFUNCTION(PINCTRL_PIN(17, "SLP_S5_L"), slp_s5), + SKY_PINFUNCTION(PINCTRL_PIN(18, "PWRGD"), pwrgd), + SKY_PINFUNCTION(PINCTRL_PIN(19, "PWROK"), pwrok), + SKY_PINFUNCTION(PINCTRL_PIN(20, "PWRBTN_L"), pwrbtn), + SKY_PINFUNCTION(PINCTRL_PIN(21, "VDD_DDRIO_GATE"), ddrio_gate), + SKY_PINFUNCTION(PINCTRL_PIN(22, "JTAG_GPIO_L"), jtag_gpio), + SKY_PINFUNCTION(PINCTRL_PIN(23, "JTAG_TCK"), jtag_tck), + SKY_PINFUNCTION(PINCTRL_PIN(24, "JTAG_TDI"), jtag_tdi), + SKY_PINFUNCTION(PINCTRL_PIN(25, "JTAG_TDO"), jtag_tdo), + SKY_PINFUNCTION(PINCTRL_PIN(26, "TMS"), tms), + SKY_PINFUNCTION(PINCTRL_PIN(27, "TRSL_L"), trsl), + SKY_PINFUNCTION(PINCTRL_PIN(28, "SFI_I2C0_SCL"), sfi_i2c0_scl), + SKY_PINFUNCTION(PINCTRL_PIN(29, "SFI_I2C0_SDA"), sfi_i2c0_sda), + SKY_PINFUNCTION(PINCTRL_PIN(30, "SFI_I2C1_SCL"), sfi_i2c1_scl), + SKY_PINFUNCTION(PINCTRL_PIN(31, "SFI_I2C1_SDA"), sfi_i2c1_sda), + SKY_PINFUNCTION(PINCTRL_PIN(32, "SFI_GPIO0"), sfi_gpio0), + SKY_PINFUNCTION(PINCTRL_PIN(33, "SFI_GPIO1"), sfi_gpio1), + SKY_PINFUNCTION(PINCTRL_PIN(34, "SFI_GPIO2"), sfi_gpio2), + SKY_PINFUNCTION(PINCTRL_PIN(35, "GPIO18"), gpio18), + SKY_PINFUNCTION(PINCTRL_PIN(36, "GPIO19"), gpio19), + SKY_PINFUNCTION(PINCTRL_PIN(37, "GPIO20"), gpio20), + SKY_PINFUNCTION(PINCTRL_PIN(38, "GPIO21"), gpio21), + SKY_PINFUNCTION(PINCTRL_PIN(39, "GPIO22"), gpio22), + SKY_PINFUNCTION(PINCTRL_PIN(40, "GPIO23"), gpio23), + SKY_PINFUNCTION(PINCTRL_PIN(41, "GPIO24"), gpio24), + SKY_PINFUNCTION(PINCTRL_PIN(42, "SPI1_MISO"), spi1_miso), + SKY_PINFUNCTION(PINCTRL_PIN(43, "SPI1_CS0"), spi1_cs0), + SKY_PINFUNCTION(PINCTRL_PIN(44, "SPI1_CS1"), spi1_cs1), + SKY_PINFUNCTION(PINCTRL_PIN(45, "SPI1_MOSI"), spi1_mosi), + SKY_PINFUNCTION(PINCTRL_PIN(46, "SPI1_CLK"), spi1_clk), + SKY_PINFUNCTION(PINCTRL_PIN(47, "GPIO30"), gpio30), + SKY_PINFUNCTION(PINCTRL_PIN(48, "GPIO31"), gpio31), + SKY_PINFUNCTION(PINCTRL_PIN(49, "GPIO32"), gpio32), + SKY_PINFUNCTION(PINCTRL_PIN(50, "GPIO33"), gpio33), + SKY_PINFUNCTION(PINCTRL_PIN(51, "GPIO34"), gpio34), + SKY_PINFUNCTION(PINCTRL_PIN(52, "GPIO35"), gpio35), + SKY_PINFUNCTION(PINCTRL_PIN(53, "GPIO36"), gpio36), + SKY_PINFUNCTION(PINCTRL_PIN(54, "GPIO37"), gpio37), + SKY_PINFUNCTION(PINCTRL_PIN(55, "GPIO38"), gpio38), + SKY_PINFUNCTION(PINCTRL_PIN(56, "GPIO39"), gpio39), + SKY_PINFUNCTION(PINCTRL_PIN(57, "GPIO40"), gpio40), + SKY_PINFUNCTION(PINCTRL_PIN(58, "GPIO41"), gpio41), + SKY_PINFUNCTION(PINCTRL_PIN(59, "GPIO42"), gpio42), + SKY_PINFUNCTION(PINCTRL_PIN(60, "SE_QSPI_CLK"), se_qspi_clk), + SKY_PINFUNCTION(PINCTRL_PIN(61, "SE_QSPI_CS_L"), se_qspi_cs), + SKY_PINFUNCTION(PINCTRL_PIN(62, "SE_QSPI_DATA0"), se_qspi_data0), + SKY_PINFUNCTION(PINCTRL_PIN(63, "SE_QSPI_DATA1"), se_qspi_data1), + SKY_PINFUNCTION(PINCTRL_PIN(64, "SE_QSPI_DATA2"), se_qspi_data2), + SKY_PINFUNCTION(PINCTRL_PIN(65, "SE_QSPI_DATA3"), se_qspi_data3), +}; + +/* Pad names for the s0 domain pinmux subsystem */ +static const char * const gpio43_group[] = {"GPIO43"}; +static const char * const gpio44_group[] = {"GPIO44"}; +static const char * const gpio45_group[] = {"GPIO45"}; +static const char * const gpio46_group[] = {"GPIO46"}; +static const char * const reset_in_group[] = { }; +static const char * const plt_reset_group[] = { }; +static const char * const thermtrip_group[] = { }; +static const char * const prochot_group[] = { }; +static const char * const pm_i2c0_clk_group[] = { }; +static const char * const pm_i2c0_data_group[] = { }; +static const char * const pm_i2c1_clk_group[] = { }; +static const char * const pm_i2c1_data_group[] = { }; +static const char * const pm_i2c2_clk_group[] = { }; +static const char * const pm_i2c2_data_group[] = { }; +static const char * const pm_i2c3_clk_group[] = { }; +static const char * const pm_i2c3_data_group[] = { }; +static const char * const strap0_group[] = { }; +static const char * const strap1_group[] = { }; +static const char * const dp2_digon_group[] = {"DP2_DIGON"}; +static const char * const dp2_blon_group[] = {"DP2_BLON"}; +static const char * const dp2_vary_bl_group[] = {"DP2_VARY_BL"}; +static const char * const i2c7_scl_group[] = {"I2C7_SCL"}; +static const char * const i2c7_sda_group[] = {"I2C7_SDA"}; +static const char * const uart6_csu_se_txd_group[] = { }; +static const char * const clk_req1_group[] = { }; +static const char * const clk_req3_group[] = { }; +static const char * const i2c5_scl_group[] = {"I2C5_SCL", "GPIO47"}; +static const char * const i2c5_sda_group[] = {"I2C5_SDA", "GPIO48"}; +static const char * const i2c6_scl_group[] = {"I2C6_SCL", "GPIO49"}; +static const char * const i2c6_sda_group[] = {"I2C6_SDA", "GPIO50"}; +static const char * const i2c0_scl_group[] = {"I2C0_SCL", "GPIO51"}; +static const char * const i2c0_sda_group[] = {"I2C0_SDA", "GPIO52"}; +static const char * const i2c1_scl_group[] = {"I2C1_SCL", "GPIO53"}; +static const char * const i2c1_sda_group[] = {"I2C1_SDA", "GPIO54"}; +static const char * const i2c2_scl_group[] = {"I2C2_SCL", "I3C0_SCL", + "GPIO55"}; +static const char * const i2c2_sda_group[] = {"I2C2_SDA", "I3C0_SDA", + "GPIO56"}; +static const char * const gpio57_group[] = {"GPIO57", "I3C0_PUR_EN_L"}; +static const char * const i2c3_scl_group[] = {"I2C3_SCL", "I3C1_SCL", + "GPIO58"}; +static const char * const i2c3_sda_group[] = {"I2C3_SDA", "I3C1_SDA", + "GPIO59"}; +static const char * const gpio60_group[] = {"GPIO60", "I3C1_PUR_EN_L"}; +static const char * const i2c4_scl_group[] = {"I2C4_SCL", "GPIO61"}; +static const char * const i2c4_sda_group[] = {"I2C4_SDA", "GPIO62"}; +static const char * const hda_bitclk_group[] = {"HDA_BITCLK", "I2S0_SCK", + "I2S9_RSCK_DBG"}; +static const char * const hda_rst_group[] = {"HDA_RST_L", "I2S0_DATA_IN", + "I2S9_DATA_IN_DBG"}; +static const char * const hda_sdin0_group[] = {"HDA_SDIN0", "I2S0_MCLK", + "I2S9_TSCK_DBG"}; +static const char * const hda_sdout0_group[] = {"HDA_SDOUT0", "I2S0_DATA_OUT", + "I2S9_TWS_DBG"}; +static const char * const hda_sync_group[] = {"HDA_SYNC", "I2S0_WS", + "I2S9_RWS_DBG"}; +static const char * const hda_sdin1_group[] = {"HDA_SDIN1", "GPIO63", + "I2S9_DATA_IN1_DBG"}; +static const char * const hda_sdout1_group[] = {"HDA_SDOUT1", "GPIO64", + "I2S9_DATA_OUT0_DBG"}; +static const char * const i2s1_mclk_group[] = {"I2S1_MCLK", "GPIO65"}; +static const char * const i2s1_sck_group[] = {"I2S1_SCK", "GPIO66"}; +static const char * const i2s1_ws_group[] = {"I2S1_WS", "GPIO67"}; +static const char * const i2s1_data_in_group[] = {"I2S1_DATA_IN", "GPIO68"}; +static const char * const i2s1_data_out_group[] = {"I2S1_DATA_OUT", "GPIO69"}; +static const char * const i2s2_mck_group[] = {"I2S2_MCLK", "GPIO70"}; +static const char * const i2s2_rsck_group[] = {"I2S2_RSCK", "GPIO71", + "I2S5_RSCK_DBG", "I2S6_RSCK_DBG"}; +static const char * const i2s2_rws_group[] = {"I2S2_RWS", "GPIO72", + "I2S5_RWS_DBG", "I2S6_RWS_DBG"}; +static const char * const i2s2_tsck_group[] = {"I2S2_TSCK", "GPIO73", + "I2S5_TSCK_DBG", "I2S6_TSCK_DBG"}; +static const char * const i2s2_tws_group[] = {"I2S2_TWS", "GPIO74", + "I2S5_TWS_DBG", "I2S6_TWS_DBG"}; +static const char * const i2s2_data_in0_group[] = {"I2S2_DATA_IN0", "GPIO75", + "I2S5_DATA_IN0_DBG", "I2S6_DATA_IN0_DBG"}; +static const char * const i2s2_data_in1_group[] = {"I2S2_DATA_IN1", "GPIO76", + "I2S5_DATA_IN1_DBG", "I2S6_DATA_IN1_DBG"}; +static const char * const i2s2_data_out0_group[] = {"I2S2_DATA_OUT0", "GPIO77", + "I2S5_DATA_OUT0_DBG", "I2S6_DATA_OUT0_DBG"}; +static const char * const i2s2_data_out1_group[] = {"I2S2_DATA_OUT1", "GPIO78", + "I2S5_DATA_OUT1_DBG", "I2S6_DATA_OUT1_DBG"}; +static const char * const i2s2_data_out2_group[] = {"I2S2_DATA_OUT2", + "GPIO79"}; +static const char * const i2s2_data_out3_group[] = {"I2S2_DATA_OUT3", "GPIO80", + "I2S9_DATA_OUT1_DBG"}; +static const char * const i2s3_mclk_group[] = {"I2S3_MCLK", "GPIO81"}; +static const char * const i2s3_rsck_group[] = {"I2S3_RSCK", "GPIO82", + "I2S7_RSCK_DBG", "I2S8_RSCK_DBG"}; +static const char * const i2s3_rws_group[] = {"I2S3_RWS", "GPIO83", + "I2S7_RWS_DBG", "I2S8_RWS_DBG"}; +static const char * const i2s3_tsck_group[] = {"I2S3_TSCK", "GPIO84", + "I2S7_TSCK_DBG", "I2S8_TSCK_DBG"}; +static const char * const i2s3_tws_group[] = {"I2S3_TWS", "GPIO85", + "I2S7_TWS_DBG", "I2S8_TWS_DBG"}; +static const char * const i2s3_data_in0_group[] = {"I2S3_DATA_IN0", "GPIO86", + "I2S7_DATA_IN0_DBG", "I2S8_DATA_IN0_DBG"}; +static const char * const i2s3_data_in1_group[] = {"I2S3_DATA_IN1", "GPIO87", + "I2S7_DATA_IN1_DBG", "I2S8_DATA_IN1_DBG"}; +static const char * const i2s3_data_out0_group[] = {"I2S3_DATA_OUT0", "GPIO88", + "I2S7_DATA_OUT0_DBG", "I2S8_DATA_OUT0_DBG"}; +static const char * const i2s3_data_out1_group[] = {"I2S3_DATA_OUT1", "GPIO89", + "I2S7_DATA_OUT1_DBG", "I2S8_DATA_OUT1_DBG"}; +static const char * const gpio90_group[] = {"GPIO90", "I2S4_MCLK_LB"}; +static const char * const gpio91_group[] = {"GPIO91", "I2S4_SCK_LB"}; +static const char * const gpio92_group[] = {"GPIO92", "I2S4_WS_LB"}; +static const char * const gpio93_group[] = {"GPIO93", "I2S4_DATA_IN_LB"}; +static const char * const gpio94_group[] = {"GPIO94", "I2S4_DATA_OUT_LB"}; +static const char * const uart0_txd_group[] = {"UART0_TXD", "PWM0", "GPIO95"}; +static const char * const uart0_rxd_group[] = {"UART0_RXD", "PWM1", "GPIO96"}; +static const char * const uart0_cts_group[] = {"UART0_CTS", "FAN_OUT2", + "GPIO97"}; +static const char * const uart0_rts_group[] = {"UART0_RTS", "FAN_TACH2", + "GPIO98"}; +static const char * const uart1_txd_group[] = {"UART1_TXD", "FAN_OUT0", + "GPIO99"}; +static const char * const uart1_rxd_group[] = {"UART1_RXD", "FAN_TACH0", + "GPIO100"}; +static const char * const uart1_cts_group[] = {"UART1_CTS", "FAN_OUT1", + "GPIO101"}; +static const char * const uart1_rts_group[] = {"UART1_RTS", "FAN_TACH1", + "GPIO102"}; +static const char * const uart2_txd_group[] = {"UART2_TXD", "GPIO103"}; +static const char * const uart2_rxd_group[] = {"UART2_RXD", "GPIO104"}; +static const char * const uart3_txd_group[] = {"UART3_TXD", "GPIO105"}; +static const char * const uart3_rxd_group[] = {"UART3_RXD", "GPIO106"}; +static const char * const uart3_cts_group[] = {"UART3_CTS", "GPIO107", + "TRIGIN0"}; +static const char * const uart3_rts_group[] = {"UART3_RTS", "GPIO108", + "TRIGIN1"}; +static const char * const uart4_csu_pm_txd_group[] = {"UART4_CSU_PM_TXD", + "GPIO109"}; +static const char * const uart4_csu_pm_rxd_group[] = {"UART4_CSU_PM_RXD", + "GPIO110"}; +static const char * const uart5_csu_se_txd_group[] = {"UART5_CSU_SE_TXD", + "GPIO111"}; +static const char * const uart5_csu_se_rxd_group[] = {"UART5_CSU_SE_RXD", + "GPIO112"}; +static const char * const uart6_csu_se_rxd_group[] = {"UART6_CSU_SE_RXD", + "GPIO113"}; +static const char * const clk_req0_group[] = {"CLK_REQ0_L", "GPIO114"}; +static const char * const clk_req2_group[] = {"CLK_REQ2_L", "GPIO115"}; +static const char * const clk_req4_group[] = {"CLK_REQ4_L", "GPIO116"}; +static const char * const csi0_mclk0_group[] = {"CSI0_MCLK0", "GPIO117"}; +static const char * const csi0_mclk1_group[] = {"CSI0_MCLK1", "GPIO118"}; +static const char * const csi1_mclk0_group[] = {"CSI1_MCLK0", "GPIO119"}; +static const char * const csi1_mclk1_group[] = {"CSI1_MCLK1", "GPIO120"}; +static const char * const gpio121_group[] = {"GPIO121", "GMAC0_REFCLK_25M"}; +static const char * const gpio122_group[] = {"GPIO122", "GMAC0_TX_CTL"}; +static const char * const gpio123_group[] = {"GPIO123", "GMAC0_TXD0"}; +static const char * const gpio124_group[] = {"GPIO124", "GMAC0_TXD1"}; +static const char * const gpio125_group[] = {"GPIO125", "GMAC0_TXD2"}; +static const char * const gpio126_group[] = {"GPIO126", "GMAC0_TXD3"}; +static const char * const gpio127_group[] = {"GPIO127", "GMAC0_TX_CLK"}; +static const char * const gpio128_group[] = {"GPIO128", "GMAC0_RX_CTL"}; +static const char * const gpio129_group[] = {"GPIO129", "GMAC0_RXD0"}; +static const char * const gpio130_group[] = {"GPIO130", "GMAC0_RXD1"}; +static const char * const gpio131_group[] = {"GPIO131", "GMAC0_RXD2"}; +static const char * const gpio132_group[] = {"GPIO132", "GMAC0_RXD3"}; +static const char * const gpio133_group[] = {"GPIO133", "GMAC0_RX_CLK"}; +static const char * const gpio134_group[] = {"GPIO134", "GMAC0_MDC"}; +static const char * const gpio135_group[] = {"GPIO135", "GMAC0_MDIO"}; +static const char * const gpio136_group[] = {"GPIO136", "GMAC1_REFCLK_25M"}; +static const char * const gpio137_group[] = {"GPIO137", "GMAC1_TX_CTL"}; +static const char * const gpio138_group[] = {"GPIO138", "GMAC1_TXD0", + "SPI2_MISO"}; +static const char * const gpio139_group[] = {"GPIO139", "GMAC1_TXD1", + "SPI2_CS0"}; +static const char * const gpio140_group[] = {"GPIO140", "GMAC1_TXD2", + "SPI2_CS1"}; +static const char * const gpio141_group[] = {"GPIO141", "GMAC1_TXD3", + "SPI2_MOSI"}; +static const char * const gpio142_group[] = {"GPIO142", "GMAC1_TX_CLK", + "SPI2_CLK"}; +static const char * const gpio143_group[] = {"GPIO143", "GMAC1_RX_CTL"}; +static const char * const gpio144_group[] = {"GPIO144", "GMAC1_RXD0"}; +static const char * const gpio145_group[] = {"GPIO145", "GMAC1_RXD1"}; +static const char * const gpio146_group[] = {"GPIO146", "GMAC1_RXD2"}; +static const char * const gpio147_group[] = {"GPIO147", "GMAC1_RXD3"}; +static const char * const gpio148_group[] = {"GPIO148", "GMAC1_RX_CLK"}; +static const char * const gpio149_group[] = {"GPIO149", "GMAC1_MDC"}; +static const char * const gpio150_group[] = {"GPIO150", "GMAC1_MDIO"}; +static const char * const gpio151_group[] = {"GPIO151", "PM_GPIO0"}; +static const char * const gpio152_group[] = {"GPIO152", "PM_GPIO1"}; +static const char * const gpio153_group[] = {"GPIO153", "PM_GPIO2"}; +static const struct sky1_pin_desc sky1_pinctrl_pads[] = { + SKY_PINFUNCTION(PINCTRL_PIN(0, "GPIO43"), gpio43), + SKY_PINFUNCTION(PINCTRL_PIN(1, "GPIO44"), gpio44), + SKY_PINFUNCTION(PINCTRL_PIN(2, "GPIO45"), gpio45), + SKY_PINFUNCTION(PINCTRL_PIN(3, "GPIO46"), gpio46), + SKY_PINFUNCTION(PINCTRL_PIN(4, "RESET_IN_L"), reset_in), + SKY_PINFUNCTION(PINCTRL_PIN(5, "PLT_RESET_L"), plt_reset), + SKY_PINFUNCTION(PINCTRL_PIN(6, "THERMTRIP_L"), thermtrip), + SKY_PINFUNCTION(PINCTRL_PIN(7, "PROCHOT_L"), prochot), + SKY_PINFUNCTION(PINCTRL_PIN(8, "PM_I2C0_CLK"), pm_i2c0_clk), + SKY_PINFUNCTION(PINCTRL_PIN(9, "PM_I2C0_DATA"), pm_i2c0_data), + SKY_PINFUNCTION(PINCTRL_PIN(10, "PM_I2C1_CLK"), pm_i2c1_clk), + SKY_PINFUNCTION(PINCTRL_PIN(11, "PM_I2C1_DATA"), pm_i2c1_data), + SKY_PINFUNCTION(PINCTRL_PIN(12, "PM_I2C2_CLK"), pm_i2c2_clk), + SKY_PINFUNCTION(PINCTRL_PIN(13, "PM_I2C2_DATA"), pm_i2c2_data), + SKY_PINFUNCTION(PINCTRL_PIN(14, "PM_I2C3_CLK"), pm_i2c3_clk), + SKY_PINFUNCTION(PINCTRL_PIN(15, "PM_I2C3_DATA"), pm_i2c3_data), + SKY_PINFUNCTION(PINCTRL_PIN(16, "STRAP0"), strap0), + SKY_PINFUNCTION(PINCTRL_PIN(17, "STRAP1"), strap1), + SKY_PINFUNCTION(PINCTRL_PIN(18, "DP2_DIGON"), dp2_digon), + SKY_PINFUNCTION(PINCTRL_PIN(19, "DP2_BLON"), dp2_blon), + SKY_PINFUNCTION(PINCTRL_PIN(20, "DP2_VARY_BL"), dp2_vary_bl), + SKY_PINFUNCTION(PINCTRL_PIN(21, "I2C7_SCL"), i2c7_scl), + SKY_PINFUNCTION(PINCTRL_PIN(22, "I2C7_SDA"), i2c7_sda), + SKY_PINFUNCTION(PINCTRL_PIN(23, "UART6_CSU_SE_TXD"), uart6_csu_se_txd), + SKY_PINFUNCTION(PINCTRL_PIN(24, "CLK_REQ1_L"), clk_req1), + SKY_PINFUNCTION(PINCTRL_PIN(25, "CLK_REQ3_L"), clk_req3), + SKY_PINFUNCTION(PINCTRL_PIN(26, "I2C5_SCL"), i2c5_scl), + SKY_PINFUNCTION(PINCTRL_PIN(27, "I2C5_SDA"), i2c5_sda), + SKY_PINFUNCTION(PINCTRL_PIN(28, "I2C6_SCL"), i2c6_scl), + SKY_PINFUNCTION(PINCTRL_PIN(29, "I2C6_SDA"), i2c6_sda), + SKY_PINFUNCTION(PINCTRL_PIN(30, "I2C0_CLK"), i2c0_scl), + SKY_PINFUNCTION(PINCTRL_PIN(31, "I2C0_SDA"), i2c0_sda), + SKY_PINFUNCTION(PINCTRL_PIN(32, "I2C1_CLK"), i2c1_scl), + SKY_PINFUNCTION(PINCTRL_PIN(33, "I2C1_SDA"), i2c1_sda), + SKY_PINFUNCTION(PINCTRL_PIN(34, "I2C2_SCL"), i2c2_scl), + SKY_PINFUNCTION(PINCTRL_PIN(35, "I2C2_SDA"), i2c2_sda), + SKY_PINFUNCTION(PINCTRL_PIN(36, "GPIO57"), gpio57), + SKY_PINFUNCTION(PINCTRL_PIN(37, "I2C3_SCL"), i2c3_scl), + SKY_PINFUNCTION(PINCTRL_PIN(38, "I2C3_SDA"), i2c3_sda), + SKY_PINFUNCTION(PINCTRL_PIN(39, "GPIO60"), gpio60), + SKY_PINFUNCTION(PINCTRL_PIN(40, "I2C4_SCL"), i2c4_scl), + SKY_PINFUNCTION(PINCTRL_PIN(41, "I2C4_SDA"), i2c4_sda), + SKY_PINFUNCTION(PINCTRL_PIN(42, "HDA_BITCLK"), hda_bitclk), + SKY_PINFUNCTION(PINCTRL_PIN(43, "HDA_RST_L"), hda_rst), + SKY_PINFUNCTION(PINCTRL_PIN(44, "HDA_SDIN0"), hda_sdin0), + SKY_PINFUNCTION(PINCTRL_PIN(45, "HDA_SDOUT0"), hda_sdout0), + SKY_PINFUNCTION(PINCTRL_PIN(46, "HDA_SYNC"), hda_sync), + SKY_PINFUNCTION(PINCTRL_PIN(47, "HDA_SDIN1"), hda_sdin1), + SKY_PINFUNCTION(PINCTRL_PIN(48, "HDA_SDOUT1"), hda_sdout1), + SKY_PINFUNCTION(PINCTRL_PIN(49, "I2S1_MCLK"), i2s1_mclk), + SKY_PINFUNCTION(PINCTRL_PIN(50, "I2S1_SCK"), i2s1_sck), + SKY_PINFUNCTION(PINCTRL_PIN(51, "I2S1_WS"), i2s1_ws), + SKY_PINFUNCTION(PINCTRL_PIN(52, "I2S1_DATA_IN"), i2s1_data_in), + SKY_PINFUNCTION(PINCTRL_PIN(53, "I2S1_DATA_OUT"), i2s1_data_out), + SKY_PINFUNCTION(PINCTRL_PIN(54, "I2S2_MCLK"), i2s2_mck), + SKY_PINFUNCTION(PINCTRL_PIN(55, "I2S2_RSCK"), i2s2_rsck), + SKY_PINFUNCTION(PINCTRL_PIN(56, "I2S2_RWS"), i2s2_rws), + SKY_PINFUNCTION(PINCTRL_PIN(57, "I2S2_TSCK"), i2s2_tsck), + SKY_PINFUNCTION(PINCTRL_PIN(58, "I2S2_TWS"), i2s2_tws), + SKY_PINFUNCTION(PINCTRL_PIN(59, "I2S2_DATA_IN0"), i2s2_data_in0), + SKY_PINFUNCTION(PINCTRL_PIN(60, "I2S2_DATA_IN1"), i2s2_data_in1), + SKY_PINFUNCTION(PINCTRL_PIN(61, "I2S2_DATA_OUT0"), i2s2_data_out0), + SKY_PINFUNCTION(PINCTRL_PIN(62, "I2S2_DATA_OUT1"), i2s2_data_out1), + SKY_PINFUNCTION(PINCTRL_PIN(63, "I2S2_DATA_OUT2"), i2s2_data_out2), + SKY_PINFUNCTION(PINCTRL_PIN(64, "I2S2_DATA_OUT3"), i2s2_data_out3), + SKY_PINFUNCTION(PINCTRL_PIN(65, "I2S3_MCLK"), i2s3_mclk), + SKY_PINFUNCTION(PINCTRL_PIN(66, "I2S3_RSCK"), i2s3_rsck), + SKY_PINFUNCTION(PINCTRL_PIN(67, "I2S3_RWS"), i2s3_rws), + SKY_PINFUNCTION(PINCTRL_PIN(68, "I2S3_TSCK"), i2s3_tsck), + SKY_PINFUNCTION(PINCTRL_PIN(69, "I2S3_TWS"), i2s3_tws), + SKY_PINFUNCTION(PINCTRL_PIN(70, "I2S3_DATA_IN0"), i2s3_data_in0), + SKY_PINFUNCTION(PINCTRL_PIN(71, "I2S3_DATA_IN1"), i2s3_data_in1), + SKY_PINFUNCTION(PINCTRL_PIN(72, "I2S3_DATA_OUT0"), i2s3_data_out0), + SKY_PINFUNCTION(PINCTRL_PIN(73, "I2S3_DATA_OUT1"), i2s3_data_out1), + SKY_PINFUNCTION(PINCTRL_PIN(74, "GPIO90"), gpio90), + SKY_PINFUNCTION(PINCTRL_PIN(75, "GPIO91"), gpio91), + SKY_PINFUNCTION(PINCTRL_PIN(76, "GPIO92"), gpio92), + SKY_PINFUNCTION(PINCTRL_PIN(77, "GPIO93"), gpio93), + SKY_PINFUNCTION(PINCTRL_PIN(78, "GPIO94"), gpio94), + SKY_PINFUNCTION(PINCTRL_PIN(79, "UART0_TXD"), uart0_txd), + SKY_PINFUNCTION(PINCTRL_PIN(80, "UART0_RXD"), uart0_rxd), + SKY_PINFUNCTION(PINCTRL_PIN(81, "UART0_CTS"), uart0_cts), + SKY_PINFUNCTION(PINCTRL_PIN(82, "UART0_RTS"), uart0_rts), + SKY_PINFUNCTION(PINCTRL_PIN(83, "UART1_TXD"), uart1_txd), + SKY_PINFUNCTION(PINCTRL_PIN(84, "UART1_RXD"), uart1_rxd), + SKY_PINFUNCTION(PINCTRL_PIN(85, "UART1_CTS"), uart1_cts), + SKY_PINFUNCTION(PINCTRL_PIN(86, "UART1_RTS"), uart1_rts), + SKY_PINFUNCTION(PINCTRL_PIN(87, "UART2_TXD"), uart2_txd), + SKY_PINFUNCTION(PINCTRL_PIN(88, "UART2_RXD"), uart2_rxd), + SKY_PINFUNCTION(PINCTRL_PIN(89, "UART3_TXD"), uart3_txd), + SKY_PINFUNCTION(PINCTRL_PIN(90, "UART3_RXD"), uart3_rxd), + SKY_PINFUNCTION(PINCTRL_PIN(91, "UART3_CTS"), uart3_cts), + SKY_PINFUNCTION(PINCTRL_PIN(92, "UART3_RTS"), uart3_rts), + SKY_PINFUNCTION(PINCTRL_PIN(93, "UART4_CSU_PM_TXD"), uart4_csu_pm_txd), + SKY_PINFUNCTION(PINCTRL_PIN(94, "UART4_CSU_PM_RXD"), uart4_csu_pm_rxd), + SKY_PINFUNCTION(PINCTRL_PIN(95, "UART5_CSU_SE_TXD"), uart5_csu_se_txd), + SKY_PINFUNCTION(PINCTRL_PIN(96, "UART5_CSU_SE_RXD"), uart5_csu_se_rxd), + SKY_PINFUNCTION(PINCTRL_PIN(97, "UART6_CSU_SE_RXD"), uart6_csu_se_rxd), + SKY_PINFUNCTION(PINCTRL_PIN(98, "CLK_REQ0_L"), clk_req0), + SKY_PINFUNCTION(PINCTRL_PIN(99, "CLK_REQ2_L"), clk_req2), + SKY_PINFUNCTION(PINCTRL_PIN(100, "CLK_REQ4_L"), clk_req4), + SKY_PINFUNCTION(PINCTRL_PIN(101, "CSI0_MCLK0"), csi0_mclk0), + SKY_PINFUNCTION(PINCTRL_PIN(102, "CSI0_MCLK1"), csi0_mclk1), + SKY_PINFUNCTION(PINCTRL_PIN(103, "CSI1_MCLK0"), csi1_mclk0), + SKY_PINFUNCTION(PINCTRL_PIN(104, "CSI1_MCLK1"), csi1_mclk1), + SKY_PINFUNCTION(PINCTRL_PIN(105, "GPIO121"), gpio121), + SKY_PINFUNCTION(PINCTRL_PIN(106, "GPIO122"), gpio122), + SKY_PINFUNCTION(PINCTRL_PIN(107, "GPIO123"), gpio123), + SKY_PINFUNCTION(PINCTRL_PIN(108, "GPIO124"), gpio124), + SKY_PINFUNCTION(PINCTRL_PIN(109, "GPIO125"), gpio125), + SKY_PINFUNCTION(PINCTRL_PIN(110, "GPIO126"), gpio126), + SKY_PINFUNCTION(PINCTRL_PIN(111, "GPIO127"), gpio127), + SKY_PINFUNCTION(PINCTRL_PIN(112, "GPIO128"), gpio128), + SKY_PINFUNCTION(PINCTRL_PIN(113, "GPIO129"), gpio129), + SKY_PINFUNCTION(PINCTRL_PIN(114, "GPIO130"), gpio130), + SKY_PINFUNCTION(PINCTRL_PIN(115, "GPIO131"), gpio131), + SKY_PINFUNCTION(PINCTRL_PIN(116, "GPIO132"), gpio132), + SKY_PINFUNCTION(PINCTRL_PIN(117, "GPIO133"), gpio133), + SKY_PINFUNCTION(PINCTRL_PIN(118, "GPIO134"), gpio134), + SKY_PINFUNCTION(PINCTRL_PIN(119, "GPIO135"), gpio135), + SKY_PINFUNCTION(PINCTRL_PIN(120, "GPIO136"), gpio136), + SKY_PINFUNCTION(PINCTRL_PIN(121, "GPIO137"), gpio137), + SKY_PINFUNCTION(PINCTRL_PIN(122, "GPIO138"), gpio138), + SKY_PINFUNCTION(PINCTRL_PIN(123, "GPIO139"), gpio139), + SKY_PINFUNCTION(PINCTRL_PIN(124, "GPIO140"), gpio140), + SKY_PINFUNCTION(PINCTRL_PIN(125, "GPIO141"), gpio141), + SKY_PINFUNCTION(PINCTRL_PIN(126, "GPIO142"), gpio142), + SKY_PINFUNCTION(PINCTRL_PIN(127, "GPIO143"), gpio143), + SKY_PINFUNCTION(PINCTRL_PIN(128, "GPIO144"), gpio144), + SKY_PINFUNCTION(PINCTRL_PIN(129, "GPIO145"), gpio145), + SKY_PINFUNCTION(PINCTRL_PIN(130, "GPIO146"), gpio146), + SKY_PINFUNCTION(PINCTRL_PIN(131, "GPIO147"), gpio147), + SKY_PINFUNCTION(PINCTRL_PIN(132, "GPIO148"), gpio148), + SKY_PINFUNCTION(PINCTRL_PIN(133, "GPIO149"), gpio149), + SKY_PINFUNCTION(PINCTRL_PIN(134, "GPIO150"), gpio150), + SKY_PINFUNCTION(PINCTRL_PIN(135, "GPIO151"), gpio151), + SKY_PINFUNCTION(PINCTRL_PIN(136, "GPIO152"), gpio152), + SKY_PINFUNCTION(PINCTRL_PIN(137, "GPIO153"), gpio153), +}; + +static const struct sky1_pinctrl_soc_info sky1_pinctrl_s5_info = { + .pins = sky1_pinctrl_s5_pads, + .npins = ARRAY_SIZE(sky1_pinctrl_s5_pads), +}; + +static const struct sky1_pinctrl_soc_info sky1_pinctrl_info = { + .pins = sky1_pinctrl_pads, + .npins = ARRAY_SIZE(sky1_pinctrl_pads), +}; + +static const struct of_device_id sky1_pinctrl_of_match[] = { + { .compatible = "cix,sky1-pinctrl-s5", .data = &sky1_pinctrl_s5_info, }, + { .compatible = "cix,sky1-pinctrl", .data = &sky1_pinctrl_info, }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, sky1_pinctrl_of_match); + +static int __maybe_unused sky1_pinctrl_suspend(struct device *dev) +{ + struct sky1_pinctrl *spctl = dev_get_drvdata(dev); + + return pinctrl_force_sleep(spctl->pctl); +} + +static int __maybe_unused sky1_pinctrl_resume(struct device *dev) +{ + struct sky1_pinctrl *spctl = dev_get_drvdata(dev); + + return pinctrl_force_default(spctl->pctl); +} + +const struct dev_pm_ops sky1_pinctrl_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(sky1_pinctrl_suspend, + sky1_pinctrl_resume) +}; +EXPORT_SYMBOL_GPL(sky1_pinctrl_pm_ops); + +static int sky1_pinctrl_probe(struct platform_device *pdev) +{ + const struct sky1_pinctrl_soc_info *pinctrl_info; + + pinctrl_info = device_get_match_data(&pdev->dev); + if (!pinctrl_info) + return -ENODEV; + + return sky1_base_pinctrl_probe(pdev, pinctrl_info); +} + +static struct platform_driver sky1_pinctrl_driver = { + .driver = { + .name = "sky1-pinctrl", + .of_match_table = sky1_pinctrl_of_match, + .pm = &sky1_pinctrl_pm_ops, + }, + .probe = sky1_pinctrl_probe, +}; + +static int __init sky1_pinctrl_init(void) +{ + return platform_driver_register(&sky1_pinctrl_driver); +} +arch_initcall(sky1_pinctrl_init); + +MODULE_AUTHOR("Jerry Zhu "); +MODULE_DESCRIPTION("Cix Sky1 pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/cix/pinctrl-sky1.h b/drivers/pinctrl/cix/pinctrl-sky1.h new file mode 100644 index 000000000000..a8b099852965 --- /dev/null +++ b/drivers/pinctrl/cix/pinctrl-sky1.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Author: Jerry Zhu + */ + +#ifndef __DRIVERS_PINCTRL_SKY1_H +#define __DRIVERS_PINCTRL_SKY1_H + +struct sky1_pinctrl_group { + const char *name; + unsigned long config; + unsigned int pin; +}; + +struct sky1_pin_desc { + const struct pinctrl_pin_desc pin; + const char * const *func_group; + unsigned int nfunc; +}; + +struct sky1_pinctrl_soc_info { + const struct sky1_pin_desc *pins; + unsigned int npins; +}; + +#define SKY_PINFUNCTION(_pin, _func) \ +((struct sky1_pin_desc) { \ + .pin = _pin, \ + .func_group = _func##_group, \ + .nfunc = ARRAY_SIZE(_func##_group), \ + }) +/** + * @dev: a pointer back to containing device + * @base: the offset to the controller in virtual memory + */ +struct sky1_pinctrl { + struct device *dev; + struct pinctrl_dev *pctl; + void __iomem *base; + const struct sky1_pinctrl_soc_info *info; + struct sky1_pinctrl_group *groups; + const char **grp_names; +}; + +int sky1_base_pinctrl_probe(struct platform_device *pdev, + const struct sky1_pinctrl_soc_info *info); + +#endif /* __DRIVERS_PINCTRL_SKY1_H */ From 4a6cc9655fcc46690de5c517c9a6dbbed1a7932e Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Thu, 23 Oct 2025 15:26:49 +0200 Subject: [PATCH 044/107] pinctrl: pinconf-generic: Fix minor typos in comments s/specyfying/specifying/ s/propertity/property/ Signed-off-by: Antonio Borneo Signed-off-by: Linus Walleij --- drivers/pinctrl/pinconf-generic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index 5de6ff62c69b..e3d10bbcdaeb 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -104,7 +104,7 @@ static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev, * @pctldev: Pincontrol device * @s: File to print to * @gname: Group name specifying pins - * @pin: Pin number specyfying pin + * @pin: Pin number specifying pin * * Print the pinconf configuration for the requested pin(s) to @s. Pins can be * specified either by pin using @pin or by group using @gname. Only one needs @@ -242,7 +242,7 @@ static void parse_dt_cfg(struct device_node *np, * @pmux: array with pin mux value entries * @npins: number of pins * - * pinmux propertity: mux value [0,7]bits and pin identity [8,31]bits. + * pinmux property: mux value [0,7]bits and pin identity [8,31]bits. */ int pinconf_generic_parse_dt_pinmux(struct device_node *np, struct device *dev, unsigned int **pid, unsigned int **pmux, From 90a18c512884adb49ddc2fb30e94594169aae808 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Thu, 23 Oct 2025 15:26:50 +0200 Subject: [PATCH 045/107] pinctrl: pinconf-generic: Handle string values for generic properties Allow a generic pinconf property to specify its argument as one of the strings in a match list. Convert the matching string to an integer value using the index in the list, then keep using this value in the generic pinconf code. Signed-off-by: Antonio Borneo Signed-off-by: Linus Walleij --- drivers/pinctrl/pinconf-generic.c | 57 ++++++++++++++++++------- include/linux/pinctrl/pinconf-generic.h | 11 ++++- 2 files changed, 50 insertions(+), 18 deletions(-) diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index e3d10bbcdaeb..72906d71ae1a 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -65,11 +65,12 @@ static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev, int i; for (i = 0; i < nitems; i++) { + const struct pin_config_item *item = &items[i]; unsigned long config; int ret; /* We want to check out this parameter */ - config = pinconf_to_config_packed(items[i].param, 0); + config = pinconf_to_config_packed(item->param, 0); if (gname) ret = pin_config_group_get(dev_name(pctldev->dev), gname, &config); @@ -86,15 +87,22 @@ static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev, if (*print_sep) seq_puts(s, ", "); *print_sep = 1; - seq_puts(s, items[i].display); + seq_puts(s, item->display); /* Print unit if available */ - if (items[i].has_arg) { + if (item->has_arg) { u32 val = pinconf_to_config_argument(config); - if (items[i].format) - seq_printf(s, " (%u %s)", val, items[i].format); + if (item->format) + seq_printf(s, " (%u %s)", val, item->format); else seq_printf(s, " (0x%x)", val); + + if (item->values && item->num_values) { + if (val < item->num_values) + seq_printf(s, " \"%s\"", item->values[val]); + else + seq_puts(s, " \"(unknown)\""); + } } } } @@ -205,10 +213,10 @@ static const struct pinconf_generic_params dt_params[] = { * @ncfg. @ncfg is updated to reflect the number of entries after parsing. @cfg * needs to have enough memory allocated to hold all possible entries. */ -static void parse_dt_cfg(struct device_node *np, - const struct pinconf_generic_params *params, - unsigned int count, unsigned long *cfg, - unsigned int *ncfg) +static int parse_dt_cfg(struct device_node *np, + const struct pinconf_generic_params *params, + unsigned int count, unsigned long *cfg, + unsigned int *ncfg) { int i; @@ -217,7 +225,19 @@ static void parse_dt_cfg(struct device_node *np, int ret; const struct pinconf_generic_params *par = ¶ms[i]; - ret = of_property_read_u32(np, par->property, &val); + if (par->values && par->num_values) { + ret = fwnode_property_match_property_string(of_fwnode_handle(np), + par->property, + par->values, par->num_values); + if (ret == -ENOENT) + return ret; + if (ret >= 0) { + val = ret; + ret = 0; + } + } else { + ret = of_property_read_u32(np, par->property, &val); + } /* property not found */ if (ret == -EINVAL) @@ -231,6 +251,8 @@ static void parse_dt_cfg(struct device_node *np, cfg[*ncfg] = pinconf_to_config_packed(par->param, val); (*ncfg)++; } + + return 0; } /** @@ -323,13 +345,16 @@ int pinconf_generic_parse_dt_config(struct device_node *np, if (!cfg) return -ENOMEM; - parse_dt_cfg(np, dt_params, ARRAY_SIZE(dt_params), cfg, &ncfg); + ret = parse_dt_cfg(np, dt_params, ARRAY_SIZE(dt_params), cfg, &ncfg); + if (ret) + return ret; if (pctldev && pctldev->desc->num_custom_params && - pctldev->desc->custom_params) - parse_dt_cfg(np, pctldev->desc->custom_params, - pctldev->desc->num_custom_params, cfg, &ncfg); - - ret = 0; + pctldev->desc->custom_params) { + ret = parse_dt_cfg(np, pctldev->desc->custom_params, + pctldev->desc->num_custom_params, cfg, &ncfg); + if (ret) + return ret; + } /* no configs found at all */ if (ncfg == 0) { diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h index d9245ecec71d..f82add5d3302 100644 --- a/include/linux/pinctrl/pinconf-generic.h +++ b/include/linux/pinctrl/pinconf-generic.h @@ -181,21 +181,28 @@ static inline unsigned long pinconf_to_config_packed(enum pin_config_param param return PIN_CONF_PACKED(param, argument); } -#define PCONFDUMP(a, b, c, d) { \ - .param = a, .display = b, .format = c, .has_arg = d \ +#define PCONFDUMP_WITH_VALUES(a, b, c, d, e, f) { \ + .param = a, .display = b, .format = c, .has_arg = d, \ + .values = e, .num_values = f \ } +#define PCONFDUMP(a, b, c, d) PCONFDUMP_WITH_VALUES(a, b, c, d, NULL, 0) + struct pin_config_item { const enum pin_config_param param; const char * const display; const char * const format; bool has_arg; + const char * const *values; + size_t num_values; }; struct pinconf_generic_params { const char * const property; enum pin_config_param param; u32 default_value; + const char * const *values; + size_t num_values; }; int pinconf_generic_dt_subnode_to_map(struct pinctrl_dev *pctldev, From 55c7f5ef904fc2dcc7ef5945c5efb0cd60b46d32 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Thu, 23 Oct 2025 15:26:51 +0200 Subject: [PATCH 046/107] pinctrl: pinconf-generic: Add properties 'skew-delay-{in,out}put-ps' Add the properties 'skew-delay-input-ps' and 'skew-delay-output-ps' to the generic parameters used for parsing DT files. This allows to specify the independent skew delay value for the two directions. This enables drivers that use the generic pin configuration to get the value passed through these new properties. Signed-off-by: Antonio Borneo Signed-off-by: Linus Walleij --- drivers/pinctrl/pinconf-generic.c | 4 ++++ include/linux/pinctrl/pinconf-generic.h | 8 ++++++++ 2 files changed, 12 insertions(+) diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index 72906d71ae1a..366775841c63 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -54,6 +54,8 @@ static const struct pin_config_item conf_items[] = { PCONFDUMP(PIN_CONFIG_SLEEP_HARDWARE_STATE, "sleep hardware state", NULL, false), PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL, true), PCONFDUMP(PIN_CONFIG_SKEW_DELAY, "skew delay", NULL, true), + PCONFDUMP(PIN_CONFIG_SKEW_DELAY_INPUT_PS, "input skew delay", "ps", true), + PCONFDUMP(PIN_CONFIG_SKEW_DELAY_OUTPUT_PS, "output skew delay", "ps", true), }; static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev, @@ -198,6 +200,8 @@ static const struct pinconf_generic_params dt_params[] = { { "sleep-hardware-state", PIN_CONFIG_SLEEP_HARDWARE_STATE, 0 }, { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 }, { "skew-delay", PIN_CONFIG_SKEW_DELAY, 0 }, + { "skew-delay-input-ps", PIN_CONFIG_SKEW_DELAY_INPUT_PS, 0 }, + { "skew-delay-output-ps", PIN_CONFIG_SKEW_DELAY_OUTPUT_PS, 0 }, }; /** diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h index f82add5d3302..1be4032071c2 100644 --- a/include/linux/pinctrl/pinconf-generic.h +++ b/include/linux/pinctrl/pinconf-generic.h @@ -112,6 +112,12 @@ struct pinctrl_map; * or latch delay (on outputs) this parameter (in a custom format) * specifies the clock skew or latch delay. It typically controls how * many double inverters are put in front of the line. + * @PIN_CONFIG_SKEW_DELAY_INPUT_PS: if the pin has independent values for the + * programmable skew rate (on inputs) and latch delay (on outputs), then + * this parameter specifies the clock skew only. The argument is in ps. + * @PIN_CONFIG_SKEW_DELAY_OUPUT_PS: if the pin has independent values for the + * programmable skew rate (on inputs) and latch delay (on outputs), then + * this parameter specifies the latch delay only. The argument is in ps. * @PIN_CONFIG_SLEEP_HARDWARE_STATE: indicate this is sleep related state. * @PIN_CONFIG_SLEW_RATE: if the pin can select slew rate, the argument to * this parameter (on a custom format) tells the driver which alternative @@ -147,6 +153,8 @@ enum pin_config_param { PIN_CONFIG_PERSIST_STATE, PIN_CONFIG_POWER_SOURCE, PIN_CONFIG_SKEW_DELAY, + PIN_CONFIG_SKEW_DELAY_INPUT_PS, + PIN_CONFIG_SKEW_DELAY_OUTPUT_PS, PIN_CONFIG_SLEEP_HARDWARE_STATE, PIN_CONFIG_SLEW_RATE, PIN_CONFIG_END = 0x7F, From 5c284d086bcf3bcfe54debb44a18fb218f91c010 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Thu, 23 Oct 2025 15:26:52 +0200 Subject: [PATCH 047/107] dt-bindings: pincfg-node: Add properties 'skew-delay-{in,out}put-ps' Add the properties 'skew-delay-input-ps' and 'skew-delay-output-ps' to specify independent skew delay value for the two pin's directions. Make the new properties unavailable when the existing property 'skew-delay' is selected. Signed-off-by: Antonio Borneo Acked-by: Conor Dooley Signed-off-by: Linus Walleij --- .../bindings/pinctrl/pincfg-node.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml b/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml index cbfcf215e571..d1bc389e0a6d 100644 --- a/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml @@ -153,4 +153,21 @@ properties: pin. Typically indicates how many double-inverters are used to delay the signal. + skew-delay-input-ps: + description: + this affects the expected clock skew in ps on an input pin. + + skew-delay-output-ps: + description: + this affects the expected delay in ps before latching a value to + an output pin. + +if: + required: + - skew-delay +then: + properties: + skew-delay-input-ps: false + skew-delay-output-ps: false + additionalProperties: true From 5a0398cc2a364e8c314a9c6361680a95d7d9b5d7 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Thu, 23 Oct 2025 15:26:53 +0200 Subject: [PATCH 048/107] pinctrl: stm32: Rework stm32_pconf_parse_conf() Reduce the number of parameters of the function by moving inside the function the decoding of the field 'config'. While there: - change the type of 'param' to 'unsigned int' to handle the extra values not in 'enum pin_config_param'; - change the type of 'arg' to 'u32' to avoid additional conversions and align to 'u32' the corresponding param of __stm32_gpio_set(). Signed-off-by: Antonio Borneo Signed-off-by: Linus Walleij --- drivers/pinctrl/stm32/pinctrl-stm32.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index 3ebb468de830..6c5f9e015e8e 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -287,7 +287,7 @@ static void stm32_gpio_rif_release_semaphore(struct stm32_gpio_bank *bank, unsig /* GPIO functions */ static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, - unsigned offset, int value) + unsigned int offset, u32 value) { stm32_gpio_backup_value(bank, offset, value); @@ -1195,10 +1195,11 @@ static bool stm32_pconf_get(struct stm32_gpio_bank *bank, } static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev, - unsigned int pin, enum pin_config_param param, - enum pin_config_param arg) + unsigned int pin, unsigned long config) { struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + unsigned int param = pinconf_to_config_param(config); + u32 arg = pinconf_to_config_argument(config); struct pinctrl_gpio_range *range; struct stm32_gpio_bank *bank; int offset, ret = 0; @@ -1267,9 +1268,7 @@ static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, for (i = 0; i < num_configs; i++) { mutex_lock(&pctldev->mutex); - ret = stm32_pconf_parse_conf(pctldev, g->pin, - pinconf_to_config_param(configs[i]), - pinconf_to_config_argument(configs[i])); + ret = stm32_pconf_parse_conf(pctldev, g->pin, configs[i]); mutex_unlock(&pctldev->mutex); if (ret < 0) return ret; @@ -1286,9 +1285,7 @@ static int stm32_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin, int i, ret; for (i = 0; i < num_configs; i++) { - ret = stm32_pconf_parse_conf(pctldev, pin, - pinconf_to_config_param(configs[i]), - pinconf_to_config_argument(configs[i])); + ret = stm32_pconf_parse_conf(pctldev, pin, configs[i]); if (ret < 0) return ret; } From bbd3fc34122431f5b004777c97164bc95f71228d Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Thu, 23 Oct 2025 15:26:54 +0200 Subject: [PATCH 049/107] pinctrl: stm32: Simplify handling of backup pin status Use C bit-field to keep the backup of the pin status, instead of explicitly handling the bit-field through shift and mask of a u32 container. Signed-off-by: Antonio Borneo Signed-off-by: Linus Walleij --- drivers/pinctrl/stm32/pinctrl-stm32.c | 70 +++++++++------------------ 1 file changed, 24 insertions(+), 46 deletions(-) diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index 6c5f9e015e8e..66f9783fce86 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -54,18 +54,6 @@ #define STM32_GPIO_CIDCFGR(x) (0x50 + (0x8 * (x))) #define STM32_GPIO_SEMCR(x) (0x54 + (0x8 * (x))) -/* custom bitfield to backup pin status */ -#define STM32_GPIO_BKP_MODE_SHIFT 0 -#define STM32_GPIO_BKP_MODE_MASK GENMASK(1, 0) -#define STM32_GPIO_BKP_ALT_SHIFT 2 -#define STM32_GPIO_BKP_ALT_MASK GENMASK(5, 2) -#define STM32_GPIO_BKP_SPEED_SHIFT 6 -#define STM32_GPIO_BKP_SPEED_MASK GENMASK(7, 6) -#define STM32_GPIO_BKP_PUPD_SHIFT 8 -#define STM32_GPIO_BKP_PUPD_MASK GENMASK(9, 8) -#define STM32_GPIO_BKP_TYPE 10 -#define STM32_GPIO_BKP_VAL 11 - #define STM32_GPIO_CIDCFGR_CFEN BIT(0) #define STM32_GPIO_CIDCFGR_SEMEN BIT(1) #define STM32_GPIO_CIDCFGR_SCID_MASK GENMASK(5, 4) @@ -100,6 +88,15 @@ struct stm32_pinctrl_group { unsigned pin; }; +struct stm32_pin_backup { + unsigned int alt:4; + unsigned int mode:2; + unsigned int bias:2; + unsigned int speed:2; + unsigned int drive:1; + unsigned int value:1; +}; + struct stm32_gpio_bank { void __iomem *base; struct reset_control *rstc; @@ -110,7 +107,7 @@ struct stm32_gpio_bank { struct irq_domain *domain; u32 bank_nr; u32 bank_ioport_nr; - u32 pin_backup[STM32_GPIO_PINS_PER_BANK]; + struct stm32_pin_backup pin_backup[STM32_GPIO_PINS_PER_BANK]; u8 irq_type[STM32_GPIO_PINS_PER_BANK]; bool secure_control; bool rif_control; @@ -176,38 +173,32 @@ static inline u32 stm32_gpio_get_alt(u32 function) static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank, u32 offset, u32 value) { - bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); - bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; + bank->pin_backup[offset].value = value; } static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset, u32 mode, u32 alt) { - bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | - STM32_GPIO_BKP_ALT_MASK); - bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT; - bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT; + bank->pin_backup[offset].mode = mode; + bank->pin_backup[offset].alt = alt; } static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset, u32 drive) { - bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE); - bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE; + bank->pin_backup[offset].drive = drive; } static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset, u32 speed) { - bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK; - bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT; + bank->pin_backup[offset].speed = speed; } static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset, u32 bias) { - bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK; - bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT; + bank->pin_backup[offset].bias = bias; } /* RIF functions */ @@ -1798,7 +1789,7 @@ static int __maybe_unused stm32_pinctrl_restore_gpio_regs( struct stm32_pinctrl *pctl, u32 pin) { const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin); - u32 val, alt, mode, offset = stm32_gpio_pin(pin); + u32 mode, offset = stm32_gpio_pin(pin); struct pinctrl_gpio_range *range; struct stm32_gpio_bank *bank; bool pin_is_irq; @@ -1818,36 +1809,23 @@ static int __maybe_unused stm32_pinctrl_restore_gpio_regs( bank = gpiochip_get_data(range->gc); - alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK; - alt >>= STM32_GPIO_BKP_ALT_SHIFT; - mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK; - mode >>= STM32_GPIO_BKP_MODE_SHIFT; - - ret = stm32_pmx_set_mode(bank, offset, mode, alt); + mode = bank->pin_backup[offset].mode; + ret = stm32_pmx_set_mode(bank, offset, mode, bank->pin_backup[offset].alt); if (ret) return ret; - if (mode == 1) { - val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL); - val = val >> STM32_GPIO_BKP_VAL; - __stm32_gpio_set(bank, offset, val); - } + if (mode == 1) + __stm32_gpio_set(bank, offset, bank->pin_backup[offset].value); - val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE); - val >>= STM32_GPIO_BKP_TYPE; - ret = stm32_pconf_set_driving(bank, offset, val); + ret = stm32_pconf_set_driving(bank, offset, bank->pin_backup[offset].drive); if (ret) return ret; - val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK; - val >>= STM32_GPIO_BKP_SPEED_SHIFT; - ret = stm32_pconf_set_speed(bank, offset, val); + ret = stm32_pconf_set_speed(bank, offset, bank->pin_backup[offset].speed); if (ret) return ret; - val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK; - val >>= STM32_GPIO_BKP_PUPD_SHIFT; - ret = stm32_pconf_set_bias(bank, offset, val); + ret = stm32_pconf_set_bias(bank, offset, bank->pin_backup[offset].bias); if (ret) return ret; From 701a6aa4a3b1ce7228523f696c9a1212abdd317f Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Thu, 23 Oct 2025 15:26:55 +0200 Subject: [PATCH 050/107] pinctrl: stm32: Drop useless spinlock save and restore There is no need to acquire a spinlock to only read a register for debugfs reporting. Drop such useless spinlock save and restore. Signed-off-by: Antonio Borneo Signed-off-by: Linus Walleij --- drivers/pinctrl/stm32/pinctrl-stm32.c | 25 ------------------------- 1 file changed, 25 deletions(-) diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index 66f9783fce86..7175328d0df0 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -920,9 +920,6 @@ static void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, u32 val; int alt_shift = (pin % 8) * 4; int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; - unsigned long flags; - - spin_lock_irqsave(&bank->lock, flags); val = readl_relaxed(bank->base + alt_offset); val &= GENMASK(alt_shift + 3, alt_shift); @@ -931,8 +928,6 @@ static void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, val = readl_relaxed(bank->base + STM32_GPIO_MODER); val &= GENMASK(pin * 2 + 1, pin * 2); *mode = val >> (pin * 2); - - spin_unlock_irqrestore(&bank->lock, flags); } static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev, @@ -1050,16 +1045,11 @@ static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank, static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank, unsigned int offset) { - unsigned long flags; u32 val; - spin_lock_irqsave(&bank->lock, flags); - val = readl_relaxed(bank->base + STM32_GPIO_TYPER); val &= BIT(offset); - spin_unlock_irqrestore(&bank->lock, flags); - return (val >> offset); } @@ -1101,16 +1091,11 @@ static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank, static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank, unsigned int offset) { - unsigned long flags; u32 val; - spin_lock_irqsave(&bank->lock, flags); - val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); val &= GENMASK(offset * 2 + 1, offset * 2); - spin_unlock_irqrestore(&bank->lock, flags); - return (val >> (offset * 2)); } @@ -1152,27 +1137,19 @@ static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank, static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank, unsigned int offset) { - unsigned long flags; u32 val; - spin_lock_irqsave(&bank->lock, flags); - val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); val &= GENMASK(offset * 2 + 1, offset * 2); - spin_unlock_irqrestore(&bank->lock, flags); - return (val >> (offset * 2)); } static bool stm32_pconf_get(struct stm32_gpio_bank *bank, unsigned int offset, bool dir) { - unsigned long flags; u32 val; - spin_lock_irqsave(&bank->lock, flags); - if (dir) val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); @@ -1180,8 +1157,6 @@ static bool stm32_pconf_get(struct stm32_gpio_bank *bank, val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & BIT(offset)); - spin_unlock_irqrestore(&bank->lock, flags); - return val; } From 78a3ce945e66966832d2a8c07494163bd3c2f3ac Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Thu, 23 Oct 2025 15:26:56 +0200 Subject: [PATCH 051/107] pinctrl: stm32: Avoid keeping a bool value in a u32 variable Change type of variable to avoid keeping the bool return value in a variable of u32 type. Signed-off-by: Antonio Borneo Signed-off-by: Linus Walleij --- drivers/pinctrl/stm32/pinctrl-stm32.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index 7175328d0df0..ac64cb7f86d7 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -1148,7 +1148,7 @@ static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank, static bool stm32_pconf_get(struct stm32_gpio_bank *bank, unsigned int offset, bool dir) { - u32 val; + bool val; if (dir) val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & From c0cfa3a9fbb9965c2ecc6e1f9d6087b676b3d348 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Thu, 23 Oct 2025 15:26:57 +0200 Subject: [PATCH 052/107] pinctrl: stm32: Support I/O synchronization parameters Devices in the stm32mp2xx family include an I/O synchronization block on each pin that is used to fine tune and improve the I/O timing margins of high speed synchronous interfaces. It can be configured to provide independently for each pin: - skew rate on input direction or latch delay on output direction; - inversion of clock signals or re-sampling of data signals. Add support for the generic properties: - skew-delay-input-ps; - skew-delay-output-ps. Add support for the property 'st,io-sync' to configure clock inversion or data re-sampling mode. Show the new parameters on debugfs pinconf-pins. Enable it for the stm32mp257 pinctrl driver. Co-developed-by: Valentin Caron Signed-off-by: Valentin Caron Co-developed-by: Fabien Dessenne Signed-off-by: Fabien Dessenne Signed-off-by: Antonio Borneo Signed-off-by: Linus Walleij --- drivers/pinctrl/stm32/pinctrl-stm32.c | 255 +++++++++++++++++++++ drivers/pinctrl/stm32/pinctrl-stm32.h | 1 + drivers/pinctrl/stm32/pinctrl-stm32mp257.c | 2 + 3 files changed, 258 insertions(+) diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index ac64cb7f86d7..5f8829fdd985 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -51,9 +51,23 @@ #define STM32_GPIO_AFRL 0x20 #define STM32_GPIO_AFRH 0x24 #define STM32_GPIO_SECCFGR 0x30 +#define STM32_GPIO_DELAYRL 0x40 +#define STM32_GPIO_ADVCFGRL 0x48 #define STM32_GPIO_CIDCFGR(x) (0x50 + (0x8 * (x))) #define STM32_GPIO_SEMCR(x) (0x54 + (0x8 * (x))) +/* Unitary delay for STM32_GPIO_DELAYRL */ +#define STM32_GPIO_DELAYRL_PS 250 + +#define STM32_GPIO_ADVCFGR_DLYPATH_MASK BIT(0) +#define STM32_GPIO_ADVCFGR_DE_MASK BIT(1) +#define STM32_GPIO_ADVCFGR_INVCLK_MASK BIT(2) +#define STM32_GPIO_ADVCFGR_RET_MASK BIT(3) +#define STM32_GPIO_ADVCFGR_IO_SYNC_MASK \ + (STM32_GPIO_ADVCFGR_DE_MASK \ + | STM32_GPIO_ADVCFGR_INVCLK_MASK \ + | STM32_GPIO_ADVCFGR_RET_MASK) + #define STM32_GPIO_CIDCFGR_CFEN BIT(0) #define STM32_GPIO_CIDCFGR_SEMEN BIT(1) #define STM32_GPIO_CIDCFGR_SCID_MASK GENMASK(5, 4) @@ -67,6 +81,9 @@ #define SYSCFG_IRQMUX_MASK GENMASK(3, 0) +/* Vendor specific pin configuration */ +#define STM32_GPIO_PIN_CONFIG_IO_SYNC (PIN_CONFIG_END + 1) + #define gpio_range_to_bank(chip) \ container_of(chip, struct stm32_gpio_bank, range) @@ -82,6 +99,32 @@ static const char * const stm32_gpio_functions[] = { "reserved", }; +static const char * const stm32_gpio_io_sync[] = { + "pass-through", + "clock inverted", + "data on rising edge", + "data on falling edge", + "data on both edges", +}; + +static u8 io_sync_2_advcfgr[] = { + /* data or clock GPIO pass-through */ + [0] = 0, + /* clock GPIO inverted */ + [1] = STM32_GPIO_ADVCFGR_INVCLK_MASK, + /* data GPIO re-sampled on clock rising edge */ + [2] = STM32_GPIO_ADVCFGR_RET_MASK, + /* data GPIO re-sampled on clock falling edge */ + [3] = STM32_GPIO_ADVCFGR_RET_MASK | STM32_GPIO_ADVCFGR_INVCLK_MASK, + /* data GPIO re-sampled on both clock edges */ + [4] = STM32_GPIO_ADVCFGR_RET_MASK | STM32_GPIO_ADVCFGR_DE_MASK, +}; + +static const struct pinconf_generic_params stm32_gpio_bindings[] = { + {"st,io-sync", STM32_GPIO_PIN_CONFIG_IO_SYNC, 0, + stm32_gpio_io_sync, ARRAY_SIZE(stm32_gpio_io_sync)}, +}; + struct stm32_pinctrl_group { const char *name; unsigned long config; @@ -95,6 +138,8 @@ struct stm32_pin_backup { unsigned int speed:2; unsigned int drive:1; unsigned int value:1; + unsigned int advcfg:4; + unsigned int skew_delay:4; }; struct stm32_gpio_bank { @@ -110,6 +155,7 @@ struct stm32_gpio_bank { struct stm32_pin_backup pin_backup[STM32_GPIO_PINS_PER_BANK]; u8 irq_type[STM32_GPIO_PINS_PER_BANK]; bool secure_control; + bool io_sync_control; bool rif_control; }; @@ -201,6 +247,21 @@ static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset, bank->pin_backup[offset].bias = bias; } +static void stm32_gpio_backup_advcfg(struct stm32_gpio_bank *bank, u32 offset, u32 mask, u32 value) +{ + u32 val; + + val = bank->pin_backup[offset].advcfg; + val &= ~mask; + val |= value & mask; + bank->pin_backup[offset].advcfg = val; +} + +static void stm32_gpio_backup_skew_delay(struct stm32_gpio_bank *bank, u32 offset, u32 delay) +{ + bank->pin_backup[offset].skew_delay = delay; +} + /* RIF functions */ static bool stm32_gpio_rif_valid(struct stm32_gpio_bank *bank, unsigned int gpio_nr) @@ -1145,6 +1206,155 @@ static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank, return (val >> (offset * 2)); } +static void +stm32_pconf_set_advcfgr_nolock(struct stm32_gpio_bank *bank, int offset, u32 mask, u32 value) +{ + int advcfgr_offset = STM32_GPIO_ADVCFGRL + (offset / 8) * 4; + int advcfgr_shift = (offset % 8) * 4; + u32 val; + + val = readl_relaxed(bank->base + advcfgr_offset); + val &= ~(mask << advcfgr_shift); + val |= (value & mask) << advcfgr_shift; + writel_relaxed(val, bank->base + advcfgr_offset); + + stm32_gpio_backup_advcfg(bank, offset, mask, value); +} + +static int stm32_pconf_set_advcfgr(struct stm32_gpio_bank *bank, int offset, u32 mask, u32 value) +{ + struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); + unsigned long flags; + int err = 0; + + if (!bank->io_sync_control) + return -ENOTSUPP; + + spin_lock_irqsave(&bank->lock, flags); + + if (pctl->hwlock) { + err = hwspin_lock_timeout_in_atomic(pctl->hwlock, HWSPNLCK_TIMEOUT); + if (err) { + dev_err(pctl->dev, "Can't get hwspinlock\n"); + goto unlock; + } + } + + stm32_pconf_set_advcfgr_nolock(bank, offset, mask, value); + + if (pctl->hwlock) + hwspin_unlock_in_atomic(pctl->hwlock); + +unlock: + spin_unlock_irqrestore(&bank->lock, flags); + + return err; +} + +static u32 stm32_pconf_get_advcfgr(struct stm32_gpio_bank *bank, int offset, u32 mask) +{ + int advcfgr_offset = STM32_GPIO_ADVCFGRL + (offset / 8) * 4; + int advcfgr_shift = (offset % 8) * 4; + u32 val; + + if (!bank->io_sync_control) + return 0; + + val = readl_relaxed(bank->base + advcfgr_offset); + val >>= advcfgr_shift; + + return val & mask; +} + +static int stm32_pconf_set_io_sync(struct stm32_gpio_bank *bank, int offset, u32 io_sync) +{ + if (io_sync >= ARRAY_SIZE(io_sync_2_advcfgr)) + return -EINVAL; + + return stm32_pconf_set_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_IO_SYNC_MASK, + io_sync_2_advcfgr[io_sync]); +} + +static const char *stm32_pconf_get_io_sync_str(struct stm32_gpio_bank *bank, int offset) +{ + u32 io_sync = stm32_pconf_get_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_IO_SYNC_MASK); + + if (io_sync & STM32_GPIO_ADVCFGR_RET_MASK) { + if (io_sync & STM32_GPIO_ADVCFGR_DE_MASK) + return "data GPIO re-sampled on both clock edges"; + + if (io_sync & STM32_GPIO_ADVCFGR_INVCLK_MASK) + return "data GPIO re-sampled on clock falling edge"; + + return "data GPIO re-sampled on clock rising edge"; + } + + if (io_sync & STM32_GPIO_ADVCFGR_INVCLK_MASK) + return "clock GPIO inverted"; + + return NULL; +} + +static int +stm32_pconf_set_skew_delay(struct stm32_gpio_bank *bank, int offset, u32 delay, bool is_dir_input) +{ + struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); + int delay_offset = STM32_GPIO_DELAYRL + (offset / 8) * 4; + int delay_shift = (offset % 8) * 4; + unsigned long flags; + int err = 0; + u32 val; + + if (!bank->io_sync_control) + return -ENOTSUPP; + + spin_lock_irqsave(&bank->lock, flags); + + if (pctl->hwlock) { + err = hwspin_lock_timeout_in_atomic(pctl->hwlock, HWSPNLCK_TIMEOUT); + if (err) { + dev_err(pctl->dev, "Can't get hwspinlock\n"); + goto unlock; + } + } + + val = readl_relaxed(bank->base + delay_offset); + val &= ~GENMASK(delay_shift + 3, delay_shift); + val |= (delay << delay_shift); + writel_relaxed(val, bank->base + delay_offset); + + stm32_gpio_backup_skew_delay(bank, offset, delay); + + stm32_pconf_set_advcfgr_nolock(bank, offset, STM32_GPIO_ADVCFGR_DLYPATH_MASK, + is_dir_input ? STM32_GPIO_ADVCFGR_DLYPATH_MASK : 0); + + if (pctl->hwlock) + hwspin_unlock_in_atomic(pctl->hwlock); + +unlock: + spin_unlock_irqrestore(&bank->lock, flags); + + return err; +} + +static u32 stm32_pconf_get_skew_delay_val(struct stm32_gpio_bank *bank, int offset) +{ + int delay_offset = STM32_GPIO_DELAYRL + (offset / 8) * 4; + int delay_shift = (offset % 8) * 4; + u32 val; + + val = readl_relaxed(bank->base + delay_offset); + val &= GENMASK(delay_shift + 3, delay_shift); + + return val >> delay_shift; +} + +static const char *stm32_pconf_get_skew_dir_str(struct stm32_gpio_bank *bank, int offset) +{ + return stm32_pconf_get_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_DLYPATH_MASK) ? + "input" : "output"; +} + static bool stm32_pconf_get(struct stm32_gpio_bank *bank, unsigned int offset, bool dir) { @@ -1207,6 +1417,17 @@ static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev, __stm32_gpio_set(bank, offset, arg); ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false); break; + case PIN_CONFIG_SKEW_DELAY_INPUT_PS: + arg /= STM32_GPIO_DELAYRL_PS; + ret = stm32_pconf_set_skew_delay(bank, offset, arg, true); + break; + case PIN_CONFIG_SKEW_DELAY_OUTPUT_PS: + arg /= STM32_GPIO_DELAYRL_PS; + ret = stm32_pconf_set_skew_delay(bank, offset, arg, false); + break; + case STM32_GPIO_PIN_CONFIG_IO_SYNC: + ret = stm32_pconf_set_io_sync(bank, offset, arg); + break; default: ret = -ENOTSUPP; } @@ -1349,6 +1570,22 @@ static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev, case 3: break; } + + if (bank->io_sync_control) { + const char *io_sync_str, *skew_dir_str; + u32 skew_delay; + + io_sync_str = stm32_pconf_get_io_sync_str(bank, offset); + skew_dir_str = stm32_pconf_get_skew_dir_str(bank, offset); + skew_delay = stm32_pconf_get_skew_delay_val(bank, offset); + + if (io_sync_str) + seq_printf(s, " - IO-sync: %s", io_sync_str); + + if (skew_delay) + seq_printf(s, " - Skew-delay: %u (%u ps) %s", skew_delay, + skew_delay * STM32_GPIO_DELAYRL_PS, skew_dir_str); + } } static const struct pinconf_ops stm32_pconf_ops = { @@ -1441,6 +1678,7 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode bank->bank_nr = bank_nr; bank->bank_ioport_nr = bank_ioport_nr; bank->secure_control = pctl->match_data->secure_control; + bank->io_sync_control = pctl->match_data->io_sync_control; bank->rif_control = pctl->match_data->rif_control; spin_lock_init(&bank->lock); @@ -1683,6 +1921,8 @@ int stm32_pctl_probe(struct platform_device *pdev) pctl->pctl_desc.confops = &stm32_pconf_ops; pctl->pctl_desc.pctlops = &stm32_pctrl_ops; pctl->pctl_desc.pmxops = &stm32_pmx_ops; + pctl->pctl_desc.num_custom_params = ARRAY_SIZE(stm32_gpio_bindings); + pctl->pctl_desc.custom_params = stm32_gpio_bindings; pctl->dev = &pdev->dev; pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, @@ -1804,6 +2044,21 @@ static int __maybe_unused stm32_pinctrl_restore_gpio_regs( if (ret) return ret; + if (bank->io_sync_control) { + bool is_input = bank->pin_backup[offset].advcfg & STM32_GPIO_ADVCFGR_DLYPATH_MASK; + + ret = stm32_pconf_set_skew_delay(bank, offset, + bank->pin_backup[offset].skew_delay, + is_input); + if (ret) + return ret; + + ret = stm32_pconf_set_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_IO_SYNC_MASK, + bank->pin_backup[offset].advcfg); + if (ret) + return ret; + } + if (pin_is_irq) regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr); diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.h b/drivers/pinctrl/stm32/pinctrl-stm32.h index b98a4141bf2c..d17cbdbba448 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.h +++ b/drivers/pinctrl/stm32/pinctrl-stm32.h @@ -64,6 +64,7 @@ struct stm32_pinctrl_match_data { const struct stm32_desc_pin *pins; const unsigned int npins; bool secure_control; + bool io_sync_control; bool rif_control; }; diff --git a/drivers/pinctrl/stm32/pinctrl-stm32mp257.c b/drivers/pinctrl/stm32/pinctrl-stm32mp257.c index d226de524bfc..6709bddd9718 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32mp257.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32mp257.c @@ -2543,6 +2543,7 @@ static const struct stm32_desc_pin stm32mp257_z_pins[] = { static struct stm32_pinctrl_match_data stm32mp257_match_data = { .pins = stm32mp257_pins, .npins = ARRAY_SIZE(stm32mp257_pins), + .io_sync_control = true, .secure_control = true, .rif_control = true, }; @@ -2550,6 +2551,7 @@ static struct stm32_pinctrl_match_data stm32mp257_match_data = { static struct stm32_pinctrl_match_data stm32mp257_z_match_data = { .pins = stm32mp257_z_pins, .npins = ARRAY_SIZE(stm32mp257_z_pins), + .io_sync_control = true, .secure_control = true, .rif_control = true, }; From cf7a3d4d3f31ec10f595f90e23f7961d8bc57cee Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Thu, 23 Oct 2025 15:26:58 +0200 Subject: [PATCH 053/107] dt-bindings: pinctrl: stm32: Use properties from pincfg-node.yaml Don't re-declare the standard pincfg properties; take them from the default schema. Signed-off-by: Antonio Borneo Acked-by: Conor Dooley Signed-off-by: Linus Walleij --- .../bindings/pinctrl/st,stm32-pinctrl.yaml | 27 ++++++++----------- 1 file changed, 11 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml index 961161c2ab62..27c0dd7a8df0 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml @@ -151,6 +151,8 @@ patternProperties: pinctrl group available on the machine. Each subnode will list the pins it needs, and how they should be configured, with regard to muxer configuration, pullups, drive, output high/low and output speed. + $ref: /schemas/pinctrl/pincfg-node.yaml + properties: pinmux: $ref: /schemas/types.yaml#/definitions/uint32-array @@ -195,26 +197,19 @@ patternProperties: pinmux = ; }; - bias-disable: - type: boolean + bias-disable: true - bias-pull-down: - type: boolean + bias-pull-down: true - bias-pull-up: - type: boolean + bias-pull-up: true - drive-push-pull: - type: boolean + drive-push-pull: true - drive-open-drain: - type: boolean + drive-open-drain: true - output-low: - type: boolean + output-low: true - output-high: - type: boolean + output-high: true slew-rate: description: | @@ -222,8 +217,8 @@ patternProperties: 1: Medium speed 2: Fast speed 3: High speed - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1, 2, 3] + minimum: 0 + maximum: 3 required: - pinmux From a730bf753eae64c6e7dcaf5d4a5c5d0ac0f76f95 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Thu, 23 Oct 2025 15:26:59 +0200 Subject: [PATCH 054/107] dt-bindings: pinctrl: stm32: Support I/O synchronization parameters Document the support of the I/O synchronization parameters: - skew-delay-input-ps; - skew-delay-output-ps; - st,io-sync. Forbid 'skew-delay-input-ps' and 'skew-delay-output-ps' to be both present on the same pin. Allow the new properties only with compatibles that support them. Add an example that uses the new properties. Co-developed-by: Fabien Dessenne Signed-off-by: Fabien Dessenne Signed-off-by: Antonio Borneo Reviewed-by: Conor Dooley Signed-off-by: Linus Walleij --- .../bindings/pinctrl/st,stm32-pinctrl.yaml | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml index 27c0dd7a8df0..76d956b4a537 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml @@ -220,12 +220,65 @@ patternProperties: minimum: 0 maximum: 3 + skew-delay-input-ps: + description: | + IO synchronization skew rate applied to the input path + enum: [0, 300, 500, 750, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250] + + skew-delay-output-ps: + description: | + IO synchronization latch delay applied to the output path + enum: [0, 300, 500, 750, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250] + + st,io-sync: + $ref: /schemas/types.yaml#/definitions/string + enum: + - pass-through + - clock inverted + - data on rising edge + - data on falling edge + - data on both edges + description: | + IO synchronization through re-sampling or inversion + "pass-through" - data or clock GPIO pass-through + "clock inverted" - clock GPIO inverted + "data on rising edge" - data GPIO re-sampled on clock rising edge + "data on falling edge" - data GPIO re-sampled on clock falling edge + "data on both edges" - data GPIO re-sampled on both clock edges + default: pass-through + required: - pinmux + # Not allowed both skew-delay-input-ps and skew-delay-output-ps + if: + required: + - skew-delay-input-ps + then: + properties: + skew-delay-output-ps: false + allOf: - $ref: pinctrl.yaml# + - if: + not: + properties: + compatible: + contains: + enum: + - st,stm32mp257-pinctrl + - st,stm32mp257-z-pinctrl + then: + patternProperties: + '-[0-9]*$': + patternProperties: + '^pins': + properties: + skew-delay-input-ps: false + skew-delay-output-ps: false + st,io-sync: false + required: - compatible - '#address-cells' @@ -306,4 +359,25 @@ examples: pinctrl-names = "default"; }; + - | + #include + //Example 4 skew-delay and st,io-sync + pinctrl: pinctrl@44240000 { + compatible = "st,stm32mp257-pinctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x44240000 0xa0400>; + + eth3_rgmii_pins_a: eth3-rgmii-0 { + pins1 { + pinmux = ; + st,io-sync = "data on both edges"; + }; + pins2 { + pinmux = ; + skew-delay-output-ps = <500>; + }; + }; + }; + ... From b45928845cc3997c074ee12960fdca8173c70da2 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Mon, 27 Oct 2025 18:18:20 +0300 Subject: [PATCH 055/107] pinctrl-scmi: remove unused struct members The ->pins and ->nr_pins members are not used so delete them. Signed-off-by: Dan Carpenter Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-scmi.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-scmi.c b/drivers/pinctrl/pinctrl-scmi.c index d14528b9aa31..af3ac031e362 100644 --- a/drivers/pinctrl/pinctrl-scmi.c +++ b/drivers/pinctrl/pinctrl-scmi.c @@ -40,8 +40,6 @@ struct scmi_pinctrl { struct pinctrl_desc pctl_desc; struct pinfunction *functions; unsigned int nr_functions; - struct pinctrl_pin_desc *pins; - unsigned int nr_pins; }; static int pinctrl_scmi_get_groups_count(struct pinctrl_dev *pctldev) From f9f4fda15e720686f1b2b436591ab11255e4e85e Mon Sep 17 00:00:00 2001 From: Maksim Kiselev Date: Mon, 27 Oct 2025 13:46:26 +0300 Subject: [PATCH 056/107] pinctrl: mcp23s08: init reg_defaults from HW at probe and switch cache type The probe function does not guarantee that chip registers are in their default state. Thus using reg_defaults for regmap is incorrect. For example, the chip may have already been configured by the bootloader before the Linux driver loads, or the mcp might not have a reset at all and not reset a state between reboots. In such cases, using reg_defaults leads to the cache values diverging from the actual registers values in the chip. Previous attempts to fix consequences of this issue were made in 'commit 3ede3f8b4b4b ("pinctrl: mcp23s08: Reset all pins to input at probe")', but this is insufficient. The OLAT register reset is also required. And there's still potential for new issues arising due to cache desynchronization of other registers. Therefore, remove reg_defaults and provide num_reg_defaults_raw. In that case the cache defaults being initialized from hardware. Also switch cache type to REGCACHE_MAPLE, which is aware of (in)valid cache entries. And remove the force reset all pins to input at probe as it is no longer required. Link: https://lore.kernel.org/all/20251009132651.649099-2-bigunclemax@gmail.com/ Suggested-by: Mike Looijmans Suggested-by: Andy Shevchenko Suggested-by: Sander Vanheule Signed-off-by: Maksim Kiselev Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-mcp23s08.c | 40 +++--------------------------- 1 file changed, 4 insertions(+), 36 deletions(-) diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c index a17fcaddf490..586f2f67c617 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08.c +++ b/drivers/pinctrl/pinctrl-mcp23s08.c @@ -44,17 +44,6 @@ #define MCP_GPIO 0x09 #define MCP_OLAT 0x0a -static const struct reg_default mcp23x08_defaults[] = { - {.reg = MCP_IODIR, .def = 0xff}, - {.reg = MCP_IPOL, .def = 0x00}, - {.reg = MCP_GPINTEN, .def = 0x00}, - {.reg = MCP_DEFVAL, .def = 0x00}, - {.reg = MCP_INTCON, .def = 0x00}, - {.reg = MCP_IOCON, .def = 0x00}, - {.reg = MCP_GPPU, .def = 0x00}, - {.reg = MCP_OLAT, .def = 0x00}, -}; - static const struct regmap_range mcp23x08_volatile_range = { .range_min = MCP_INTF, .range_max = MCP_GPIO, @@ -82,25 +71,13 @@ const struct regmap_config mcp23x08_regmap = { .reg_stride = 1, .volatile_table = &mcp23x08_volatile_table, .precious_table = &mcp23x08_precious_table, - .reg_defaults = mcp23x08_defaults, - .num_reg_defaults = ARRAY_SIZE(mcp23x08_defaults), - .cache_type = REGCACHE_FLAT, + .num_reg_defaults_raw = MCP_OLAT + 1, + .cache_type = REGCACHE_MAPLE, .max_register = MCP_OLAT, .disable_locking = true, /* mcp->lock protects the regmap */ }; EXPORT_SYMBOL_GPL(mcp23x08_regmap); -static const struct reg_default mcp23x17_defaults[] = { - {.reg = MCP_IODIR << 1, .def = 0xffff}, - {.reg = MCP_IPOL << 1, .def = 0x0000}, - {.reg = MCP_GPINTEN << 1, .def = 0x0000}, - {.reg = MCP_DEFVAL << 1, .def = 0x0000}, - {.reg = MCP_INTCON << 1, .def = 0x0000}, - {.reg = MCP_IOCON << 1, .def = 0x0000}, - {.reg = MCP_GPPU << 1, .def = 0x0000}, - {.reg = MCP_OLAT << 1, .def = 0x0000}, -}; - static const struct regmap_range mcp23x17_volatile_range = { .range_min = MCP_INTF << 1, .range_max = MCP_GPIO << 1, @@ -129,9 +106,8 @@ const struct regmap_config mcp23x17_regmap = { .max_register = MCP_OLAT << 1, .volatile_table = &mcp23x17_volatile_table, .precious_table = &mcp23x17_precious_table, - .reg_defaults = mcp23x17_defaults, - .num_reg_defaults = ARRAY_SIZE(mcp23x17_defaults), - .cache_type = REGCACHE_FLAT, + .num_reg_defaults_raw = MCP_OLAT + 1, + .cache_type = REGCACHE_MAPLE, .val_format_endian = REGMAP_ENDIAN_LITTLE, .disable_locking = true, /* mcp->lock protects the regmap */ }; @@ -642,14 +618,6 @@ int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, mcp->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); - /* - * Reset the chip - we don't really know what state it's in, so reset - * all pins to input first to prevent surprises. - */ - ret = mcp_write(mcp, MCP_IODIR, mcp->chip.ngpio == 16 ? 0xFFFF : 0xFF); - if (ret < 0) - return ret; - /* verify MCP_IOCON.SEQOP = 0, so sequential reads work, * and MCP_IOCON.HAEN = 1, so we work with all chips. */ From 002679f79ed605e543fbace465557317cd307c9a Mon Sep 17 00:00:00 2001 From: Haotian Zhang Date: Wed, 29 Oct 2025 09:42:52 +0800 Subject: [PATCH 057/107] pinctrl: stm32: fix hwspinlock resource leak in probe function In stm32_pctl_probe(), hwspin_lock_request_specific() is called to request a hwspinlock, but the acquired lock is not freed on multiple error paths after this call. This causes resource leakage when the function fails to initialize properly. Use devm_hwspin_lock_request_specific() instead of hwspin_lock_request_specific() to automatically manage the hwspinlock resource lifecycle. Fixes: 97cfb6cd34f2 ("pinctrl: stm32: protect configuration registers with a hwspinlock") Signed-off-by: Haotian Zhang Reviewed-by: Antonio Borneo Signed-off-by: Linus Walleij --- drivers/pinctrl/stm32/pinctrl-stm32.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index 5f8829fdd985..ceb9e19f2290 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -1872,7 +1872,7 @@ int stm32_pctl_probe(struct platform_device *pdev) if (hwlock_id == -EPROBE_DEFER) return hwlock_id; } else { - pctl->hwlock = hwspin_lock_request_specific(hwlock_id); + pctl->hwlock = devm_hwspin_lock_request_specific(dev, hwlock_id); } spin_lock_init(&pctl->irqmux_lock); From 99224c151c19b74e1930d236dd348b6b22a607a5 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Wed, 29 Oct 2025 15:29:35 +0000 Subject: [PATCH 058/107] pinctrl: mpfs-iomux0: fix compile-time constant warning for LLVM prior to 17 With LLVM prior to 17.0.0: drivers/pinctrl/pinctrl-mpfs-iomux0.c:89:2: error: initializer element is not a compile-time constant MPFS_IOMUX0_GROUP(spi0), ^~~~~~~~~~~~~~~~~~~~~~~ drivers/pinctrl/pinctrl-mpfs-iomux0.c:79:10: note: expanded from macro 'MPFS_IOMUX0_GROUP' .mask = BIT(mpfs_iomux0_##_name##_pins[0]), \ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ include/vdso/bits.h:7:19: note: expanded from macro 'BIT' \#define BIT(nr) (UL(1) << (nr)) ^~~~~~~~~~~~~~~ This is a constant, but LLVM prior to a change from Nick to match the gcc behaviour did not allow this. The macro isn't really all that much of an idiot-proofing, just change it to the same sort that's in the gpio2 driver, where a second argument provides the mask/setting. Reported-by: Nathan Chancellor Link: https://github.com/ClangBuiltLinux/linux/issues/2140 Fixes: 46397274da22 ("pinctrl: add polarfire soc iomux0 pinmux driver") Signed-off-by: Conor Dooley Reviewed-by: Nathan Chancellor Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-mpfs-iomux0.c | 36 +++++++++++++-------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/pinctrl/pinctrl-mpfs-iomux0.c b/drivers/pinctrl/pinctrl-mpfs-iomux0.c index 49d9fcec0a16..cf5b2e4e8f5b 100644 --- a/drivers/pinctrl/pinctrl-mpfs-iomux0.c +++ b/drivers/pinctrl/pinctrl-mpfs-iomux0.c @@ -73,33 +73,33 @@ static const unsigned int mpfs_iomux0_uart4_pins[] = { 11 }; static const unsigned int mpfs_iomux0_mdio0_pins[] = { 12 }; static const unsigned int mpfs_iomux0_mdio1_pins[] = { 13 }; -#define MPFS_IOMUX0_GROUP(_name) { \ +#define MPFS_IOMUX0_GROUP(_name, _mask) { \ .name = #_name "_mssio", \ .pins = mpfs_iomux0_##_name##_pins, \ - .mask = BIT(mpfs_iomux0_##_name##_pins[0]), \ + .mask = _mask, \ .setting = 0x0, \ }, { \ .name = #_name "_fabric", \ .pins = mpfs_iomux0_##_name##_pins, \ - .mask = BIT(mpfs_iomux0_##_name##_pins[0]), \ - .setting = BIT(mpfs_iomux0_##_name##_pins[0]), \ + .mask = _mask, \ + .setting = _mask, \ } static const struct mpfs_iomux0_pin_group mpfs_iomux0_pin_groups[] = { - MPFS_IOMUX0_GROUP(spi0), - MPFS_IOMUX0_GROUP(spi1), - MPFS_IOMUX0_GROUP(i2c0), - MPFS_IOMUX0_GROUP(i2c1), - MPFS_IOMUX0_GROUP(can0), - MPFS_IOMUX0_GROUP(can1), - MPFS_IOMUX0_GROUP(qspi), - MPFS_IOMUX0_GROUP(uart0), - MPFS_IOMUX0_GROUP(uart1), - MPFS_IOMUX0_GROUP(uart2), - MPFS_IOMUX0_GROUP(uart3), - MPFS_IOMUX0_GROUP(uart4), - MPFS_IOMUX0_GROUP(mdio0), - MPFS_IOMUX0_GROUP(mdio1), + MPFS_IOMUX0_GROUP(spi0, BIT(0)), + MPFS_IOMUX0_GROUP(spi1, BIT(1)), + MPFS_IOMUX0_GROUP(i2c0, BIT(2)), + MPFS_IOMUX0_GROUP(i2c1, BIT(3)), + MPFS_IOMUX0_GROUP(can0, BIT(4)), + MPFS_IOMUX0_GROUP(can1, BIT(5)), + MPFS_IOMUX0_GROUP(qspi, BIT(6)), + MPFS_IOMUX0_GROUP(uart0, BIT(7)), + MPFS_IOMUX0_GROUP(uart1, BIT(8)), + MPFS_IOMUX0_GROUP(uart2, BIT(9)), + MPFS_IOMUX0_GROUP(uart3, BIT(10)), + MPFS_IOMUX0_GROUP(uart4, BIT(11)), + MPFS_IOMUX0_GROUP(mdio0, BIT(12)), + MPFS_IOMUX0_GROUP(mdio1, BIT(13)), }; static const char * const mpfs_iomux0_spi0_groups[] = { "spi0_mssio", "spi0_fabric" }; From cf6dd6cafdfc3844648ba52efdaec0bd4e631129 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 3 Nov 2025 20:58:28 +0100 Subject: [PATCH 059/107] pinctrl: baytrail: Unify messages with help of dev_err_probe() Unify error messages that might appear during probe phase by switching to use dev_err_probe(). Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-baytrail.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index 5fd107a00ef8..b3a5222a175f 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -1498,9 +1498,9 @@ static int byt_gpio_add_pin_ranges(struct gpio_chip *chip) ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins); if (ret) - dev_err(dev, "failed to add GPIO pin range\n"); + return dev_err_probe(dev, ret, "failed to add GPIO pin range\n"); - return ret; + return 0; } static int byt_gpio_probe(struct intel_pinctrl *vg) @@ -1548,9 +1548,9 @@ static int byt_gpio_probe(struct intel_pinctrl *vg) ret = devm_gpiochip_add_data(vg->dev, gc, vg); if (ret) - dev_err(vg->dev, "failed adding byt-gpio chip\n"); + return dev_err_probe(vg->dev, ret, "failed to register gpiochip\n"); - return ret; + return 0; } static int byt_set_soc_data(struct intel_pinctrl *vg, @@ -1601,10 +1601,8 @@ static int byt_pinctrl_probe(struct platform_device *pdev) vg->dev = dev; ret = byt_set_soc_data(vg, soc_data); - if (ret) { - dev_err(dev, "failed to set soc data\n"); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, "failed to set soc data\n"); vg->pctldesc = byt_pinctrl_desc; vg->pctldesc.name = dev_name(dev); @@ -1612,10 +1610,8 @@ static int byt_pinctrl_probe(struct platform_device *pdev) vg->pctldesc.npins = vg->soc->npins; vg->pctldev = devm_pinctrl_register(dev, &vg->pctldesc, vg); - if (IS_ERR(vg->pctldev)) { - dev_err(dev, "failed to register pinctrl driver\n"); - return PTR_ERR(vg->pctldev); - } + if (IS_ERR(vg->pctldev)) + return dev_err_probe(dev, PTR_ERR(vg->pctldev), "failed to register pinctrl\n"); ret = byt_gpio_probe(vg); if (ret) From 6afe489df6b3af0851fb98f522ecdb41c75e4632 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 3 Nov 2025 20:58:29 +0100 Subject: [PATCH 060/107] pinctrl: cherryview: Unify messages with help of dev_err_probe() Unify error messages that might appear during probe phase by switching to use dev_err_probe(). Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-cherryview.c | 24 ++++++++-------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index f81f7929cd3b..077fa1318aaf 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -1528,10 +1528,8 @@ static int chv_gpio_add_pin_ranges(struct gpio_chip *chip) for (i = 0; i < community->ngpps; i++) { gpp = &community->gpps[i]; ret = gpiochip_add_pin_range(chip, dev_name(dev), gpp->base, gpp->base, gpp->size); - if (ret) { - dev_err(dev, "failed to add GPIO pin range\n"); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, "failed to add GPIO pin range\n"); } return 0; @@ -1567,17 +1565,13 @@ static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq) chip->irq.init_valid_mask = chv_init_irq_valid_mask; } else { irq_base = devm_irq_alloc_descs(dev, -1, 0, pctrl->soc->npins, NUMA_NO_NODE); - if (irq_base < 0) { - dev_err(dev, "Failed to allocate IRQ numbers\n"); - return irq_base; - } + if (irq_base < 0) + return dev_err_probe(dev, irq_base, "failed to allocate IRQ numbers\n"); } ret = devm_gpiochip_add_data(dev, chip, pctrl); - if (ret) { - dev_err(dev, "Failed to register gpiochip\n"); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, "failed to register gpiochip\n"); if (!need_valid_mask) { for (i = 0; i < community->ngpps; i++) { @@ -1673,10 +1667,8 @@ static int chv_pinctrl_probe(struct platform_device *pdev) pctrl->pctldesc.npins = pctrl->soc->npins; pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl); - if (IS_ERR(pctrl->pctldev)) { - dev_err(dev, "failed to register pinctrl driver\n"); - return PTR_ERR(pctrl->pctldev); - } + if (IS_ERR(pctrl->pctldev)) + return dev_err_probe(dev, PTR_ERR(pctrl->pctldev), "failed to register pinctrl\n"); ret = chv_gpio_probe(pctrl, irq); if (ret) From e2620a2c44dcb00af8216afb74040bfe4dc4a211 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 3 Nov 2025 20:58:30 +0100 Subject: [PATCH 061/107] pinctrl: intel: Unify messages with help of dev_err_probe() Unify error messages that might appear during probe phase by switching to use dev_err_probe(). Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-intel.c | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index d68cef4ec52a..1e2f77d200f9 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1356,10 +1356,8 @@ static int intel_gpio_add_pin_ranges(struct gpio_chip *gc) ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), grp->gpio_base, grp->base, grp->size); - if (ret) { - dev_err(pctrl->dev, "failed to add GPIO pin range\n"); - return ret; - } + if (ret) + return dev_err_probe(pctrl->dev, ret, "failed to add GPIO pin range\n"); } return 0; @@ -1401,10 +1399,8 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, IRQF_SHARED | IRQF_NO_THREAD, dev_name(pctrl->dev), pctrl); - if (ret) { - dev_err(pctrl->dev, "failed to request interrupt\n"); - return ret; - } + if (ret) + return dev_err_probe(pctrl->dev, ret, "failed to request interrupt\n"); /* Setup IRQ chip */ girq = &pctrl->chip.irq; @@ -1417,10 +1413,8 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) girq->init_hw = intel_gpio_irq_init_hw; ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl); - if (ret) { - dev_err(pctrl->dev, "failed to register gpiochip\n"); - return ret; - } + if (ret) + return dev_err_probe(pctrl->dev, ret, "failed to register gpiochip\n"); return 0; } @@ -1668,10 +1662,8 @@ int intel_pinctrl_probe(struct platform_device *pdev, pctrl->pctldesc.npins = pctrl->soc->npins; pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl); - if (IS_ERR(pctrl->pctldev)) { - dev_err(dev, "failed to register pinctrl driver\n"); - return PTR_ERR(pctrl->pctldev); - } + if (IS_ERR(pctrl->pctldev)) + return dev_err_probe(dev, PTR_ERR(pctrl->pctldev), "failed to register pinctrl\n"); ret = intel_gpio_probe(pctrl, irq); if (ret) From a13735785c27c0df5b51919b63fa98c1a03118f7 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 3 Nov 2025 20:19:15 +0100 Subject: [PATCH 062/107] pinctrl: lynxpoint: Unify messages with help of dev_err_probe() Unify error messages that might appear during probe phase by switching to use dev_err_probe(). Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 28 ++++++++--------------- 1 file changed, 10 insertions(+), 18 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index 3fb628309fb2..1565eefdd4bf 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -700,9 +700,9 @@ static int lp_gpio_add_pin_ranges(struct gpio_chip *chip) ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, lg->soc->npins); if (ret) - dev_err(dev, "failed to add GPIO pin range\n"); + return dev_err_probe(dev, ret, "failed to add GPIO pin range\n"); - return ret; + return 0; } static int lp_gpio_probe(struct platform_device *pdev) @@ -739,24 +739,18 @@ static int lp_gpio_probe(struct platform_device *pdev) lg->pctldesc.npins = lg->soc->npins; lg->pctldev = devm_pinctrl_register(dev, &lg->pctldesc, lg); - if (IS_ERR(lg->pctldev)) { - dev_err(dev, "failed to register pinctrl driver\n"); - return PTR_ERR(lg->pctldev); - } + if (IS_ERR(lg->pctldev)) + return dev_err_probe(dev, PTR_ERR(lg->pctldev), "failed to register pinctrl\n"); platform_set_drvdata(pdev, lg); io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0); - if (!io_rc) { - dev_err(dev, "missing IO resources\n"); - return -EINVAL; - } + if (!io_rc) + return dev_err_probe(dev, -EINVAL, "missing IO resources\n"); regs = devm_ioport_map(dev, io_rc->start, resource_size(io_rc)); - if (!regs) { - dev_err(dev, "failed mapping IO region %pR\n", &io_rc); - return -EBUSY; - } + if (!regs) + return dev_err_probe(dev, -EBUSY, "failed mapping IO region %pR\n", &io_rc); for (i = 0; i < lg->soc->ncommunities; i++) { struct intel_community *comm = &lg->communities[i]; @@ -807,10 +801,8 @@ static int lp_gpio_probe(struct platform_device *pdev) } ret = devm_gpiochip_add_data(dev, gc, lg); - if (ret) { - dev_err(dev, "failed adding lp-gpio chip\n"); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, "failed to register gpiochip\n"); return 0; } From 534ea60bc4809b8ec4f13d6b252c4bb8d5f243d2 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 3 Nov 2025 20:58:31 +0100 Subject: [PATCH 063/107] pinctrl: tangier: Unify messages with help of dev_err_probe() Unify error messages that might appear during probe phase by switching to use dev_err_probe(). Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-tangier.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-tangier.c b/drivers/pinctrl/intel/pinctrl-tangier.c index ac61e632b487..5f0b7334a489 100644 --- a/drivers/pinctrl/intel/pinctrl-tangier.c +++ b/drivers/pinctrl/intel/pinctrl-tangier.c @@ -562,8 +562,7 @@ static int tng_pinctrl_probe(struct platform_device *pdev, tp->pctldev = devm_pinctrl_register(dev, &tp->pctldesc, tp); if (IS_ERR(tp->pctldev)) - return dev_err_probe(dev, PTR_ERR(tp->pctldev), - "failed to register pinctrl driver\n"); + return dev_err_probe(dev, PTR_ERR(tp->pctldev), "failed to register pinctrl\n"); return 0; } From 59d2d28f2269dfb89d64828fd330bc32113fd036 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 4 Nov 2025 14:01:03 +0100 Subject: [PATCH 064/107] pinctrl: cix: sky1: Provide pin control dummy states This exports and calls the pinctrl_provide_dummies() function from the CIX SKY1 driver. The reasons are explained in a comment in the commit, in essence the two pin controllers need to go through explicit state transitions default->sleep->default despite they only handle one single state each. Reviewed-by: Hans Zhang Reviewed-by: Fugang Duan Signed-off-by: Linus Walleij --- drivers/pinctrl/cix/pinctrl-sky1-base.c | 15 +++++++++++++++ drivers/pinctrl/core.c | 1 + 2 files changed, 16 insertions(+) diff --git a/drivers/pinctrl/cix/pinctrl-sky1-base.c b/drivers/pinctrl/cix/pinctrl-sky1-base.c index b03e10147b09..a5b583f10441 100644 --- a/drivers/pinctrl/cix/pinctrl-sky1-base.c +++ b/drivers/pinctrl/cix/pinctrl-sky1-base.c @@ -560,6 +560,21 @@ int sky1_base_pinctrl_probe(struct platform_device *pdev, return ret; } + /* + * The SKY1 SoC has two pin controllers: one for normal working state + * and one for sleep state. Since one controller only has working + * states and the other only sleep states, it will seem to the + * controller is always in the first configured state, so no + * transitions between default->sleep->default are detected and no + * new pin states are applied when we go in and out of sleep state. + * + * To counter this, provide dummies, so that the sleep-only pin + * controller still get some default states, and the working state pin + * controller get some sleep states, so that state transitions occur + * and we re-configure pins for default and sleep states. + */ + pinctrl_provide_dummies(); + dev_dbg(&pdev->dev, "initialized SKY1 pinctrl driver\n"); return pinctrl_enable(spctl->pctl); diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index 157510157d47..83254a95ef17 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -70,6 +70,7 @@ void pinctrl_provide_dummies(void) { pinctrl_dummy_state = true; } +EXPORT_SYMBOL_GPL(pinctrl_provide_dummies); const char *pinctrl_dev_get_name(struct pinctrl_dev *pctldev) { From e1a57abb3be5ca5a33b84861d4ff7ece923419b9 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 4 Nov 2025 15:56:35 +0100 Subject: [PATCH 065/107] pinctrl: intel: Introduce INTEL_GPP() macro A new macro will be used for the further refactoring of the drivers. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-intel.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h index 4d4e1257afdf..654af5977603 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.h +++ b/drivers/pinctrl/intel/pinctrl-intel.h @@ -76,6 +76,15 @@ enum { INTEL_GPIO_BASE_MATCH = 0, }; +/* Initialise struct intel_padgroup */ +#define INTEL_GPP(r, s, e, g) \ + { \ + .reg_num = (r), \ + .base = (s), \ + .size = ((e) - (s) + 1), \ + .gpio_base = (g), \ + } + /** * struct intel_community - Intel pin community description * @barno: MMIO BAR number where registers for this community reside From 16b37ed0f373638c85bf9ed68d070073bd2921a5 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 4 Nov 2025 15:56:36 +0100 Subject: [PATCH 066/107] pinctrl: alderlake: Switch to INTEL_GPP() macro Replace custom macro with the recently defined INTEL_GPP(). Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-alderlake.c | 68 ++++++++++------------- 1 file changed, 30 insertions(+), 38 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-alderlake.c b/drivers/pinctrl/intel/pinctrl-alderlake.c index 108eac205aa9..7bf1d5c285a0 100644 --- a/drivers/pinctrl/intel/pinctrl-alderlake.c +++ b/drivers/pinctrl/intel/pinctrl-alderlake.c @@ -27,14 +27,6 @@ #define ADL_S_GPI_IS 0x200 #define ADL_S_GPI_IE 0x220 -#define ADL_GPP(r, s, e, g) \ - { \ - .reg_num = (r), \ - .base = (s), \ - .size = ((e) - (s) + 1), \ - .gpio_base = (g), \ - } - #define ADL_N_COMMUNITY(b, s, e, g) \ INTEL_COMMUNITY_GPPS(b, s, e, g, ADL_N) @@ -316,28 +308,28 @@ static const struct pinctrl_pin_desc adln_pins[] = { }; static const struct intel_padgroup adln_community0_gpps[] = { - ADL_GPP(0, 0, 25, 0), /* GPP_B */ - ADL_GPP(1, 26, 41, 32), /* GPP_T */ - ADL_GPP(2, 42, 66, 64), /* GPP_A */ + INTEL_GPP(0, 0, 25, 0), /* GPP_B */ + INTEL_GPP(1, 26, 41, 32), /* GPP_T */ + INTEL_GPP(2, 42, 66, 64), /* GPP_A */ }; static const struct intel_padgroup adln_community1_gpps[] = { - ADL_GPP(0, 67, 74, 96), /* GPP_S */ - ADL_GPP(1, 75, 94, 128), /* GPP_I */ - ADL_GPP(2, 95, 118, 160), /* GPP_H */ - ADL_GPP(3, 119, 139, 192), /* GPP_D */ - ADL_GPP(4, 140, 168, 224), /* vGPIO */ + INTEL_GPP(0, 67, 74, 96), /* GPP_S */ + INTEL_GPP(1, 75, 94, 128), /* GPP_I */ + INTEL_GPP(2, 95, 118, 160), /* GPP_H */ + INTEL_GPP(3, 119, 139, 192), /* GPP_D */ + INTEL_GPP(4, 140, 168, 224), /* vGPIO */ }; static const struct intel_padgroup adln_community4_gpps[] = { - ADL_GPP(0, 169, 192, 256), /* GPP_C */ - ADL_GPP(1, 193, 217, 288), /* GPP_F */ - ADL_GPP(2, 218, 223, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ - ADL_GPP(3, 224, 248, 320), /* GPP_E */ + INTEL_GPP(0, 169, 192, 256), /* GPP_C */ + INTEL_GPP(1, 193, 217, 288), /* GPP_F */ + INTEL_GPP(2, 218, 223, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ + INTEL_GPP(3, 224, 248, 320), /* GPP_E */ }; static const struct intel_padgroup adln_community5_gpps[] = { - ADL_GPP(0, 249, 256, 352), /* GPP_R */ + INTEL_GPP(0, 249, 256, 352), /* GPP_R */ }; static const struct intel_community adln_communities[] = { @@ -680,35 +672,35 @@ static const struct pinctrl_pin_desc adls_pins[] = { }; static const struct intel_padgroup adls_community0_gpps[] = { - ADL_GPP(0, 0, 24, 0), /* GPP_I */ - ADL_GPP(1, 25, 47, 32), /* GPP_R */ - ADL_GPP(2, 48, 59, 64), /* GPP_J */ - ADL_GPP(3, 60, 86, 96), /* vGPIO */ - ADL_GPP(4, 87, 94, 128), /* vGPIO_0 */ + INTEL_GPP(0, 0, 24, 0), /* GPP_I */ + INTEL_GPP(1, 25, 47, 32), /* GPP_R */ + INTEL_GPP(2, 48, 59, 64), /* GPP_J */ + INTEL_GPP(3, 60, 86, 96), /* vGPIO */ + INTEL_GPP(4, 87, 94, 128), /* vGPIO_0 */ }; static const struct intel_padgroup adls_community1_gpps[] = { - ADL_GPP(0, 95, 118, 160), /* GPP_B */ - ADL_GPP(1, 119, 126, 192), /* GPP_G */ - ADL_GPP(2, 127, 150, 224), /* GPP_H */ + INTEL_GPP(0, 95, 118, 160), /* GPP_B */ + INTEL_GPP(1, 119, 126, 192), /* GPP_G */ + INTEL_GPP(2, 127, 150, 224), /* GPP_H */ }; static const struct intel_padgroup adls_community3_gpps[] = { - ADL_GPP(0, 151, 159, INTEL_GPIO_BASE_NOMAP), /* SPI0 */ - ADL_GPP(1, 160, 175, 256), /* GPP_A */ - ADL_GPP(2, 176, 199, 288), /* GPP_C */ + INTEL_GPP(0, 151, 159, INTEL_GPIO_BASE_NOMAP), /* SPI0 */ + INTEL_GPP(1, 160, 175, 256), /* GPP_A */ + INTEL_GPP(2, 176, 199, 288), /* GPP_C */ }; static const struct intel_padgroup adls_community4_gpps[] = { - ADL_GPP(0, 200, 207, 320), /* GPP_S */ - ADL_GPP(1, 208, 230, 352), /* GPP_E */ - ADL_GPP(2, 231, 245, 384), /* GPP_K */ - ADL_GPP(3, 246, 269, 416), /* GPP_F */ + INTEL_GPP(0, 200, 207, 320), /* GPP_S */ + INTEL_GPP(1, 208, 230, 352), /* GPP_E */ + INTEL_GPP(2, 231, 245, 384), /* GPP_K */ + INTEL_GPP(3, 246, 269, 416), /* GPP_F */ }; static const struct intel_padgroup adls_community5_gpps[] = { - ADL_GPP(0, 270, 294, 448), /* GPP_D */ - ADL_GPP(1, 295, 303, INTEL_GPIO_BASE_NOMAP), /* JTAG */ + INTEL_GPP(0, 270, 294, 448), /* GPP_D */ + INTEL_GPP(1, 295, 303, INTEL_GPIO_BASE_NOMAP), /* JTAG */ }; static const struct intel_community adls_communities[] = { From 9db14f71029d9d2b23f831203d893c30b8e2a079 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 4 Nov 2025 15:56:37 +0100 Subject: [PATCH 067/107] pinctrl: cannonlake: Switch to INTEL_GPP() macro Replace custom macro with the recently defined INTEL_GPP(). Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-cannonlake.c | 68 ++++++++++------------ 1 file changed, 30 insertions(+), 38 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-cannonlake.c b/drivers/pinctrl/intel/pinctrl-cannonlake.c index 14a5d339385d..a3ffd19fd5be 100644 --- a/drivers/pinctrl/intel/pinctrl-cannonlake.c +++ b/drivers/pinctrl/intel/pinctrl-cannonlake.c @@ -28,14 +28,6 @@ #define CNL_H_GPI_IS 0x100 #define CNL_H_GPI_IE 0x120 -#define CNL_GPP(r, s, e, g) \ - { \ - .reg_num = (r), \ - .base = (s), \ - .size = ((e) - (s) + 1), \ - .gpio_base = (g), \ - } - #define CNL_LP_COMMUNITY(b, s, e, g) \ INTEL_COMMUNITY_GPPS(b, s, e, g, CNL_LP) @@ -362,32 +354,32 @@ static const struct pinctrl_pin_desc cnlh_pins[] = { }; static const struct intel_padgroup cnlh_community0_gpps[] = { - CNL_GPP(0, 0, 24, 0), /* GPP_A */ - CNL_GPP(1, 25, 50, 32), /* GPP_B */ + INTEL_GPP(0, 0, 24, 0), /* GPP_A */ + INTEL_GPP(1, 25, 50, 32), /* GPP_B */ }; static const struct intel_padgroup cnlh_community1_gpps[] = { - CNL_GPP(0, 51, 74, 64), /* GPP_C */ - CNL_GPP(1, 75, 98, 96), /* GPP_D */ - CNL_GPP(2, 99, 106, 128), /* GPP_G */ - CNL_GPP(3, 107, 114, INTEL_GPIO_BASE_NOMAP), /* AZA */ - CNL_GPP(4, 115, 146, 160), /* vGPIO_0 */ - CNL_GPP(5, 147, 154, INTEL_GPIO_BASE_NOMAP), /* vGPIO_1 */ + INTEL_GPP(0, 51, 74, 64), /* GPP_C */ + INTEL_GPP(1, 75, 98, 96), /* GPP_D */ + INTEL_GPP(2, 99, 106, 128), /* GPP_G */ + INTEL_GPP(3, 107, 114, INTEL_GPIO_BASE_NOMAP), /* AZA */ + INTEL_GPP(4, 115, 146, 160), /* vGPIO_0 */ + INTEL_GPP(5, 147, 154, INTEL_GPIO_BASE_NOMAP), /* vGPIO_1 */ }; static const struct intel_padgroup cnlh_community3_gpps[] = { - CNL_GPP(0, 155, 178, 192), /* GPP_K */ - CNL_GPP(1, 179, 202, 224), /* GPP_H */ - CNL_GPP(2, 203, 215, 256), /* GPP_E */ - CNL_GPP(3, 216, 239, 288), /* GPP_F */ - CNL_GPP(4, 240, 248, INTEL_GPIO_BASE_NOMAP), /* SPI */ + INTEL_GPP(0, 155, 178, 192), /* GPP_K */ + INTEL_GPP(1, 179, 202, 224), /* GPP_H */ + INTEL_GPP(2, 203, 215, 256), /* GPP_E */ + INTEL_GPP(3, 216, 239, 288), /* GPP_F */ + INTEL_GPP(4, 240, 248, INTEL_GPIO_BASE_NOMAP), /* SPI */ }; static const struct intel_padgroup cnlh_community4_gpps[] = { - CNL_GPP(0, 249, 259, INTEL_GPIO_BASE_NOMAP), /* CPU */ - CNL_GPP(1, 260, 268, INTEL_GPIO_BASE_NOMAP), /* JTAG */ - CNL_GPP(2, 269, 286, 320), /* GPP_I */ - CNL_GPP(3, 287, 298, 352), /* GPP_J */ + INTEL_GPP(0, 249, 259, INTEL_GPIO_BASE_NOMAP), /* CPU */ + INTEL_GPP(1, 260, 268, INTEL_GPIO_BASE_NOMAP), /* JTAG */ + INTEL_GPP(2, 269, 286, 320), /* GPP_I */ + INTEL_GPP(3, 287, 298, 352), /* GPP_J */ }; static const unsigned int cnlh_spi0_pins[] = { 40, 41, 42, 43 }; @@ -780,25 +772,25 @@ static const struct intel_function cnllp_functions[] = { }; static const struct intel_padgroup cnllp_community0_gpps[] = { - CNL_GPP(0, 0, 24, 0), /* GPP_A */ - CNL_GPP(1, 25, 50, 32), /* GPP_B */ - CNL_GPP(2, 51, 58, 64), /* GPP_G */ - CNL_GPP(3, 59, 67, INTEL_GPIO_BASE_NOMAP), /* SPI */ + INTEL_GPP(0, 0, 24, 0), /* GPP_A */ + INTEL_GPP(1, 25, 50, 32), /* GPP_B */ + INTEL_GPP(2, 51, 58, 64), /* GPP_G */ + INTEL_GPP(3, 59, 67, INTEL_GPIO_BASE_NOMAP), /* SPI */ }; static const struct intel_padgroup cnllp_community1_gpps[] = { - CNL_GPP(0, 68, 92, 96), /* GPP_D */ - CNL_GPP(1, 93, 116, 128), /* GPP_F */ - CNL_GPP(2, 117, 140, 160), /* GPP_H */ - CNL_GPP(3, 141, 172, 192), /* vGPIO */ - CNL_GPP(4, 173, 180, 224), /* vGPIO */ + INTEL_GPP(0, 68, 92, 96), /* GPP_D */ + INTEL_GPP(1, 93, 116, 128), /* GPP_F */ + INTEL_GPP(2, 117, 140, 160), /* GPP_H */ + INTEL_GPP(3, 141, 172, 192), /* vGPIO */ + INTEL_GPP(4, 173, 180, 224), /* vGPIO */ }; static const struct intel_padgroup cnllp_community4_gpps[] = { - CNL_GPP(0, 181, 204, 256), /* GPP_C */ - CNL_GPP(1, 205, 228, 288), /* GPP_E */ - CNL_GPP(2, 229, 237, INTEL_GPIO_BASE_NOMAP), /* JTAG */ - CNL_GPP(3, 238, 243, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ + INTEL_GPP(0, 181, 204, 256), /* GPP_C */ + INTEL_GPP(1, 205, 228, 288), /* GPP_E */ + INTEL_GPP(2, 229, 237, INTEL_GPIO_BASE_NOMAP), /* JTAG */ + INTEL_GPP(3, 238, 243, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ }; static const struct intel_community cnllp_communities[] = { From 51327d683963cf2f4f4210f8275e9a522ba27dd4 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 4 Nov 2025 15:56:38 +0100 Subject: [PATCH 068/107] pinctrl: icelake: Switch to INTEL_GPP() macro Replace custom macro with the recently defined INTEL_GPP(). Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-icelake.c | 60 +++++++++++-------------- 1 file changed, 26 insertions(+), 34 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-icelake.c b/drivers/pinctrl/intel/pinctrl-icelake.c index 7e028c61ed0f..1516fe7b4e4a 100644 --- a/drivers/pinctrl/intel/pinctrl-icelake.c +++ b/drivers/pinctrl/intel/pinctrl-icelake.c @@ -28,14 +28,6 @@ #define ICL_N_GPI_IS 0x100 #define ICL_N_GPI_IE 0x120 -#define ICL_GPP(r, s, e, g) \ - { \ - .reg_num = (r), \ - .base = (s), \ - .size = ((e) - (s) + 1), \ - .gpio_base = (g), \ - } - #define ICL_LP_COMMUNITY(b, s, e, g) \ INTEL_COMMUNITY_GPPS(b, s, e, g, ICL_LP) @@ -302,29 +294,29 @@ static const struct pinctrl_pin_desc icllp_pins[] = { }; static const struct intel_padgroup icllp_community0_gpps[] = { - ICL_GPP(0, 0, 7, 0), /* GPP_G */ - ICL_GPP(1, 8, 33, 32), /* GPP_B */ - ICL_GPP(2, 34, 58, 64), /* GPP_A */ + INTEL_GPP(0, 0, 7, 0), /* GPP_G */ + INTEL_GPP(1, 8, 33, 32), /* GPP_B */ + INTEL_GPP(2, 34, 58, 64), /* GPP_A */ }; static const struct intel_padgroup icllp_community1_gpps[] = { - ICL_GPP(0, 59, 82, 96), /* GPP_H */ - ICL_GPP(1, 83, 103, 128), /* GPP_D */ - ICL_GPP(2, 104, 123, 160), /* GPP_F */ - ICL_GPP(3, 124, 152, 192), /* vGPIO */ + INTEL_GPP(0, 59, 82, 96), /* GPP_H */ + INTEL_GPP(1, 83, 103, 128), /* GPP_D */ + INTEL_GPP(2, 104, 123, 160), /* GPP_F */ + INTEL_GPP(3, 124, 152, 192), /* vGPIO */ }; static const struct intel_padgroup icllp_community4_gpps[] = { - ICL_GPP(0, 153, 176, 224), /* GPP_C */ - ICL_GPP(1, 177, 182, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ - ICL_GPP(2, 183, 206, 256), /* GPP_E */ - ICL_GPP(3, 207, 215, INTEL_GPIO_BASE_NOMAP), /* JTAG */ + INTEL_GPP(0, 153, 176, 224), /* GPP_C */ + INTEL_GPP(1, 177, 182, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ + INTEL_GPP(2, 183, 206, 256), /* GPP_E */ + INTEL_GPP(3, 207, 215, INTEL_GPIO_BASE_NOMAP), /* JTAG */ }; static const struct intel_padgroup icllp_community5_gpps[] = { - ICL_GPP(0, 216, 223, 288), /* GPP_R */ - ICL_GPP(1, 224, 231, 320), /* GPP_S */ - ICL_GPP(2, 232, 240, INTEL_GPIO_BASE_NOMAP), /* SPI */ + INTEL_GPP(0, 216, 223, 288), /* GPP_R */ + INTEL_GPP(1, 224, 231, 320), /* GPP_S */ + INTEL_GPP(2, 232, 240, INTEL_GPIO_BASE_NOMAP), /* SPI */ }; static const struct intel_community icllp_communities[] = { @@ -632,27 +624,27 @@ static const struct pinctrl_pin_desc icln_pins[] = { }; static const struct intel_padgroup icln_community0_gpps[] = { - ICL_GPP(0, 0, 8, INTEL_GPIO_BASE_NOMAP), /* SPI */ - ICL_GPP(1, 9, 34, 32), /* GPP_B */ - ICL_GPP(2, 35, 55, 64), /* GPP_A */ - ICL_GPP(3, 56, 63, 96), /* GPP_S */ - ICL_GPP(4, 64, 71, 128), /* GPP_R */ + INTEL_GPP(0, 0, 8, INTEL_GPIO_BASE_NOMAP), /* SPI */ + INTEL_GPP(1, 9, 34, 32), /* GPP_B */ + INTEL_GPP(2, 35, 55, 64), /* GPP_A */ + INTEL_GPP(3, 56, 63, 96), /* GPP_S */ + INTEL_GPP(4, 64, 71, 128), /* GPP_R */ }; static const struct intel_padgroup icln_community1_gpps[] = { - ICL_GPP(0, 72, 95, 160), /* GPP_H */ - ICL_GPP(1, 96, 121, 192), /* GPP_D */ - ICL_GPP(2, 122, 150, 224), /* vGPIO */ - ICL_GPP(3, 151, 174, 256), /* GPP_C */ + INTEL_GPP(0, 72, 95, 160), /* GPP_H */ + INTEL_GPP(1, 96, 121, 192), /* GPP_D */ + INTEL_GPP(2, 122, 150, 224), /* vGPIO */ + INTEL_GPP(3, 151, 174, 256), /* GPP_C */ }; static const struct intel_padgroup icln_community4_gpps[] = { - ICL_GPP(0, 175, 180, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ - ICL_GPP(1, 181, 204, 288), /* GPP_E */ + INTEL_GPP(0, 175, 180, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ + INTEL_GPP(1, 181, 204, 288), /* GPP_E */ }; static const struct intel_padgroup icln_community5_gpps[] = { - ICL_GPP(0, 205, 212, INTEL_GPIO_BASE_ZERO), /* GPP_G */ + INTEL_GPP(0, 205, 212, INTEL_GPIO_BASE_ZERO), /* GPP_G */ }; static const struct intel_community icln_communities[] = { From 29d06c2d39d054eb72f62adac1ba1b63f2d0b365 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 4 Nov 2025 15:56:39 +0100 Subject: [PATCH 069/107] pinctrl: jasperlake: Switch to INTEL_GPP() macro Replace custom macro with the recently defined INTEL_GPP(). Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-jasperlake.c | 34 +++++++++------------- 1 file changed, 13 insertions(+), 21 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-jasperlake.c b/drivers/pinctrl/intel/pinctrl-jasperlake.c index aef0e7f92154..c6e1836c69a7 100644 --- a/drivers/pinctrl/intel/pinctrl-jasperlake.c +++ b/drivers/pinctrl/intel/pinctrl-jasperlake.c @@ -21,14 +21,6 @@ #define JSL_GPI_IS 0x100 #define JSL_GPI_IE 0x120 -#define JSL_GPP(r, s, e, g) \ - { \ - .reg_num = (r), \ - .base = (s), \ - .size = ((e) - (s) + 1), \ - .gpio_base = (g), \ - } - #define JSL_COMMUNITY(b, s, e, g) \ INTEL_COMMUNITY_GPPS(b, s, e, g, JSL) @@ -283,28 +275,28 @@ static const struct pinctrl_pin_desc jsl_pins[] = { }; static const struct intel_padgroup jsl_community0_gpps[] = { - JSL_GPP(0, 0, 19, 320), /* GPP_F */ - JSL_GPP(1, 20, 28, INTEL_GPIO_BASE_NOMAP), /* SPI */ - JSL_GPP(2, 29, 54, 32), /* GPP_B */ - JSL_GPP(3, 55, 75, 64), /* GPP_A */ - JSL_GPP(4, 76, 83, 96), /* GPP_S */ - JSL_GPP(5, 84, 91, 128), /* GPP_R */ + INTEL_GPP(0, 0, 19, 320), /* GPP_F */ + INTEL_GPP(1, 20, 28, INTEL_GPIO_BASE_NOMAP), /* SPI */ + INTEL_GPP(2, 29, 54, 32), /* GPP_B */ + INTEL_GPP(3, 55, 75, 64), /* GPP_A */ + INTEL_GPP(4, 76, 83, 96), /* GPP_S */ + INTEL_GPP(5, 84, 91, 128), /* GPP_R */ }; static const struct intel_padgroup jsl_community1_gpps[] = { - JSL_GPP(0, 92, 115, 160), /* GPP_H */ - JSL_GPP(1, 116, 141, 192), /* GPP_D */ - JSL_GPP(2, 142, 170, 224), /* vGPIO */ - JSL_GPP(3, 171, 194, 256), /* GPP_C */ + INTEL_GPP(0, 92, 115, 160), /* GPP_H */ + INTEL_GPP(1, 116, 141, 192), /* GPP_D */ + INTEL_GPP(2, 142, 170, 224), /* vGPIO */ + INTEL_GPP(3, 171, 194, 256), /* GPP_C */ }; static const struct intel_padgroup jsl_community4_gpps[] = { - JSL_GPP(0, 195, 200, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ - JSL_GPP(1, 201, 224, 288), /* GPP_E */ + INTEL_GPP(0, 195, 200, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ + INTEL_GPP(1, 201, 224, 288), /* GPP_E */ }; static const struct intel_padgroup jsl_community5_gpps[] = { - JSL_GPP(0, 225, 232, INTEL_GPIO_BASE_ZERO), /* GPP_G */ + INTEL_GPP(0, 225, 232, INTEL_GPIO_BASE_ZERO), /* GPP_G */ }; static const struct intel_community jsl_communities[] = { From c11e90dc9ab324cc14f90b9b26ec95710f52b846 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 4 Nov 2025 15:56:40 +0100 Subject: [PATCH 070/107] pinctrl: lakefield: Switch to INTEL_GPP() macro Replace custom macro with the recently defined INTEL_GPP(). Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-lakefield.c | 26 ++++++++--------------- 1 file changed, 9 insertions(+), 17 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-lakefield.c b/drivers/pinctrl/intel/pinctrl-lakefield.c index 60281f421608..bfb8b565d15c 100644 --- a/drivers/pinctrl/intel/pinctrl-lakefield.c +++ b/drivers/pinctrl/intel/pinctrl-lakefield.c @@ -21,14 +21,6 @@ #define LKF_GPI_IS 0x100 #define LKF_GPI_IE 0x110 -#define LKF_GPP(r, s, e, g) \ - { \ - .reg_num = (r), \ - .base = (s), \ - .size = ((e) - (s) + 1), \ - .gpio_base = (g), \ - } - #define LKF_COMMUNITY(b, s, e, g) \ INTEL_COMMUNITY_GPPS(b, s, e, g, LKF) @@ -308,24 +300,24 @@ static const struct pinctrl_pin_desc lkf_pins[] = { }; static const struct intel_padgroup lkf_community0_gpps[] = { - LKF_GPP(0, 0, 31, 0), /* EAST_0 */ - LKF_GPP(1, 32, 59, 32), /* EAST_1 */ + INTEL_GPP(0, 0, 31, 0), /* EAST_0 */ + INTEL_GPP(1, 32, 59, 32), /* EAST_1 */ }; static const struct intel_padgroup lkf_community1_gpps[] = { - LKF_GPP(0, 60, 91, 64), /* NORTHWEST_0 */ - LKF_GPP(1, 92, 123, 96), /* NORTHWEST_1 */ - LKF_GPP(2, 124, 148, 128), /* NORTHWEST_2 */ + INTEL_GPP(0, 60, 91, 64), /* NORTHWEST_0 */ + INTEL_GPP(1, 92, 123, 96), /* NORTHWEST_1 */ + INTEL_GPP(2, 124, 148, 128), /* NORTHWEST_2 */ }; static const struct intel_padgroup lkf_community2_gpps[] = { - LKF_GPP(0, 149, 180, 160), /* WEST_0 */ - LKF_GPP(1, 181, 212, 192), /* WEST_1 */ - LKF_GPP(2, 213, 237, 224), /* WEST_2 */ + INTEL_GPP(0, 149, 180, 160), /* WEST_0 */ + INTEL_GPP(1, 181, 212, 192), /* WEST_1 */ + INTEL_GPP(2, 213, 237, 224), /* WEST_2 */ }; static const struct intel_padgroup lkf_community3_gpps[] = { - LKF_GPP(0, 238, 266, 256), /* SOUTHEAST */ + INTEL_GPP(0, 238, 266, 256), /* SOUTHEAST */ }; static const struct intel_community lkf_communities[] = { From cac89a3dca3a6dbc420bf5253c2d212cb9b4b339 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 4 Nov 2025 15:56:41 +0100 Subject: [PATCH 071/107] pinctrl: meteorlake: Switch to INTEL_GPP() macro Replace custom macro with the recently defined INTEL_GPP(). Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-meteorlake.c | 54 +++++++++------------- 1 file changed, 23 insertions(+), 31 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-meteorlake.c b/drivers/pinctrl/intel/pinctrl-meteorlake.c index f564376ce437..b7395947569a 100644 --- a/drivers/pinctrl/intel/pinctrl-meteorlake.c +++ b/drivers/pinctrl/intel/pinctrl-meteorlake.c @@ -27,14 +27,6 @@ #define MTL_S_GPI_IS 0x200 #define MTL_S_GPI_IE 0x210 -#define MTL_GPP(r, s, e, g) \ - { \ - .reg_num = (r), \ - .base = (s), \ - .size = ((e) - (s) + 1), \ - .gpio_base = (g), \ - } - #define MTL_P_COMMUNITY(b, s, e, g) \ INTEL_COMMUNITY_GPPS(b, s, e, g, MTL_P) @@ -349,33 +341,33 @@ static const struct pinctrl_pin_desc mtlp_pins[] = { }; static const struct intel_padgroup mtlp_community0_gpps[] = { - MTL_GPP(0, 0, 4, 0), /* CPU */ - MTL_GPP(1, 5, 28, 32), /* GPP_V */ - MTL_GPP(2, 29, 52, 64), /* GPP_C */ + INTEL_GPP(0, 0, 4, 0), /* CPU */ + INTEL_GPP(1, 5, 28, 32), /* GPP_V */ + INTEL_GPP(2, 29, 52, 64), /* GPP_C */ }; static const struct intel_padgroup mtlp_community1_gpps[] = { - MTL_GPP(0, 53, 77, 96), /* GPP_A */ - MTL_GPP(1, 78, 102, 128), /* GPP_E */ + INTEL_GPP(0, 53, 77, 96), /* GPP_A */ + INTEL_GPP(1, 78, 102, 128), /* GPP_E */ }; static const struct intel_padgroup mtlp_community3_gpps[] = { - MTL_GPP(0, 103, 128, 160), /* GPP_H */ - MTL_GPP(1, 129, 154, 192), /* GPP_F */ - MTL_GPP(2, 155, 169, 224), /* SPI0 */ - MTL_GPP(3, 170, 183, 256), /* vGPIO_3 */ + INTEL_GPP(0, 103, 128, 160), /* GPP_H */ + INTEL_GPP(1, 129, 154, 192), /* GPP_F */ + INTEL_GPP(2, 155, 169, 224), /* SPI0 */ + INTEL_GPP(3, 170, 183, 256), /* vGPIO_3 */ }; static const struct intel_padgroup mtlp_community4_gpps[] = { - MTL_GPP(0, 184, 191, 288), /* GPP_S */ - MTL_GPP(1, 192, 203, 320), /* JTAG */ + INTEL_GPP(0, 184, 191, 288), /* GPP_S */ + INTEL_GPP(1, 192, 203, 320), /* JTAG */ }; static const struct intel_padgroup mtlp_community5_gpps[] = { - MTL_GPP(0, 204, 228, 352), /* GPP_B */ - MTL_GPP(1, 229, 253, 384), /* GPP_D */ - MTL_GPP(2, 254, 285, 416), /* vGPIO_0 */ - MTL_GPP(3, 286, 288, 448), /* vGPIO_1 */ + INTEL_GPP(0, 204, 228, 352), /* GPP_B */ + INTEL_GPP(1, 229, 253, 384), /* GPP_D */ + INTEL_GPP(2, 254, 285, 416), /* vGPIO_0 */ + INTEL_GPP(3, 286, 288, 448), /* vGPIO_1 */ }; static const struct intel_community mtlp_communities[] = { @@ -554,20 +546,20 @@ static const struct pinctrl_pin_desc mtls_pins[] = { }; static const struct intel_padgroup mtls_community0_gpps[] = { - MTL_GPP(0, 0, 27, 0), /* GPP_A */ - MTL_GPP(1, 28, 46, 32), /* vGPIO_0 */ - MTL_GPP(2, 47, 73, 64), /* GPP_C */ + INTEL_GPP(0, 0, 27, 0), /* GPP_A */ + INTEL_GPP(1, 28, 46, 32), /* vGPIO_0 */ + INTEL_GPP(2, 47, 73, 64), /* GPP_C */ }; static const struct intel_padgroup mtls_community1_gpps[] = { - MTL_GPP(0, 74, 93, 96), /* GPP_B */ - MTL_GPP(1, 94, 95, 128), /* vGPIO_3 */ - MTL_GPP(2, 96, 119, 160), /* GPP_D */ + INTEL_GPP(0, 74, 93, 96), /* GPP_B */ + INTEL_GPP(1, 94, 95, 128), /* vGPIO_3 */ + INTEL_GPP(2, 96, 119, 160), /* GPP_D */ }; static const struct intel_padgroup mtls_community3_gpps[] = { - MTL_GPP(0, 120, 135, 192), /* JTAG_CPU */ - MTL_GPP(1, 136, 147, 224), /* vGPIO_4 */ + INTEL_GPP(0, 120, 135, 192), /* JTAG_CPU */ + INTEL_GPP(1, 136, 147, 224), /* vGPIO_4 */ }; static const struct intel_community mtls_communities[] = { From 9151857eefbb8528690e37b07260301a58e9127d Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 4 Nov 2025 15:56:42 +0100 Subject: [PATCH 072/107] pinctrl: meteorpoint: Switch to INTEL_GPP() macro Replace custom macro with the recently defined INTEL_GPP(). Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-meteorpoint.c | 46 +++++++++------------ 1 file changed, 19 insertions(+), 27 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-meteorpoint.c b/drivers/pinctrl/intel/pinctrl-meteorpoint.c index ab46ac5f3b15..b7858c2b2c5c 100644 --- a/drivers/pinctrl/intel/pinctrl-meteorpoint.c +++ b/drivers/pinctrl/intel/pinctrl-meteorpoint.c @@ -21,14 +21,6 @@ #define MTP_GPI_IS 0x200 #define MTP_GPI_IE 0x220 -#define MTP_GPP(r, s, e, g) \ - { \ - .reg_num = (r), \ - .base = (s), \ - .size = ((e) - (s) + 1), \ - .gpio_base = (g), \ - } - #define MTP_COMMUNITY(b, s, e, g) \ INTEL_COMMUNITY_GPPS(b, s, e, g, MTP) @@ -395,37 +387,37 @@ static const struct pinctrl_pin_desc mtps_pins[] = { }; static const struct intel_padgroup mtps_community0_gpps[] = { - MTP_GPP(0, 0, 24, 0), /* GPP_D */ - MTP_GPP(1, 25, 38, 32), /* GPP_R */ - MTP_GPP(2, 39, 56, 64), /* GPP_J */ - MTP_GPP(3, 57, 87, 96), /* vGPIO */ + INTEL_GPP(0, 0, 24, 0), /* GPP_D */ + INTEL_GPP(1, 25, 38, 32), /* GPP_R */ + INTEL_GPP(2, 39, 56, 64), /* GPP_J */ + INTEL_GPP(3, 57, 87, 96), /* vGPIO */ }; static const struct intel_padgroup mtps_community1_gpps[] = { - MTP_GPP(0, 88, 102, 128), /* GPP_A */ - MTP_GPP(1, 103, 114, 160), /* DIR_ESPI */ - MTP_GPP(2, 115, 136, 192), /* GPP_B */ + INTEL_GPP(0, 88, 102, 128), /* GPP_A */ + INTEL_GPP(1, 103, 114, 160), /* DIR_ESPI */ + INTEL_GPP(2, 115, 136, 192), /* GPP_B */ }; static const struct intel_padgroup mtps_community3_gpps[] = { - MTP_GPP(0, 137, 145, 224), /* SPI0 */ - MTP_GPP(1, 146, 169, 256), /* GPP_C */ - MTP_GPP(2, 170, 189, 288), /* GPP_H */ - MTP_GPP(3, 190, 193, 320), /* vGPIO_3 */ - MTP_GPP(4, 194, 201, 352), /* vGPIO_0 */ - MTP_GPP(5, 202, 232, 384), /* vGPIO_4 */ + INTEL_GPP(0, 137, 145, 224), /* SPI0 */ + INTEL_GPP(1, 146, 169, 256), /* GPP_C */ + INTEL_GPP(2, 170, 189, 288), /* GPP_H */ + INTEL_GPP(3, 190, 193, 320), /* vGPIO_3 */ + INTEL_GPP(4, 194, 201, 352), /* vGPIO_0 */ + INTEL_GPP(5, 202, 232, 384), /* vGPIO_4 */ }; static const struct intel_padgroup mtps_community4_gpps[] = { - MTP_GPP(0, 233, 240, 416), /* GPP_S */ - MTP_GPP(1, 241, 263, 448), /* GPP_E */ - MTP_GPP(2, 264, 277, 480), /* GPP_K */ - MTP_GPP(3, 278, 301, 512), /* GPP_F */ + INTEL_GPP(0, 233, 240, 416), /* GPP_S */ + INTEL_GPP(1, 241, 263, 448), /* GPP_E */ + INTEL_GPP(2, 264, 277, 480), /* GPP_K */ + INTEL_GPP(3, 278, 301, 512), /* GPP_F */ }; static const struct intel_padgroup mtps_community5_gpps[] = { - MTP_GPP(0, 302, 322, 544), /* GPP_I */ - MTP_GPP(1, 323, 338, 576), /* JTAG_CPU */ + INTEL_GPP(0, 302, 322, 544), /* GPP_I */ + INTEL_GPP(1, 323, 338, 576), /* JTAG_CPU */ }; static const struct intel_community mtps_communities[] = { From ba6467787b6843dec08d16944f9d2a7757b5acfb Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 4 Nov 2025 15:56:43 +0100 Subject: [PATCH 073/107] pinctrl: tigerlake: Switch to INTEL_GPP() macro Replace custom macro with the recently defined INTEL_GPP(). Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-tigerlake.c | 70 ++++++++++------------- 1 file changed, 31 insertions(+), 39 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-tigerlake.c b/drivers/pinctrl/intel/pinctrl-tigerlake.c index c43576e10273..c0887596d113 100644 --- a/drivers/pinctrl/intel/pinctrl-tigerlake.c +++ b/drivers/pinctrl/intel/pinctrl-tigerlake.c @@ -28,14 +28,6 @@ #define TGL_H_GPI_IS 0x100 #define TGL_H_GPI_IE 0x120 -#define TGL_GPP(r, s, e, g) \ - { \ - .reg_num = (r), \ - .base = (s), \ - .size = ((e) - (s) + 1), \ - .gpio_base = (g), \ - } - #define TGL_LP_COMMUNITY(b, s, e, g) \ INTEL_COMMUNITY_GPPS(b, s, e, g, TGL_LP) @@ -339,30 +331,30 @@ static const struct pinctrl_pin_desc tgllp_pins[] = { }; static const struct intel_padgroup tgllp_community0_gpps[] = { - TGL_GPP(0, 0, 25, 0), /* GPP_B */ - TGL_GPP(1, 26, 41, 32), /* GPP_T */ - TGL_GPP(2, 42, 66, 64), /* GPP_A */ + INTEL_GPP(0, 0, 25, 0), /* GPP_B */ + INTEL_GPP(1, 26, 41, 32), /* GPP_T */ + INTEL_GPP(2, 42, 66, 64), /* GPP_A */ }; static const struct intel_padgroup tgllp_community1_gpps[] = { - TGL_GPP(0, 67, 74, 96), /* GPP_S */ - TGL_GPP(1, 75, 98, 128), /* GPP_H */ - TGL_GPP(2, 99, 119, 160), /* GPP_D */ - TGL_GPP(3, 120, 143, 192), /* GPP_U */ - TGL_GPP(4, 144, 170, 224), /* vGPIO */ + INTEL_GPP(0, 67, 74, 96), /* GPP_S */ + INTEL_GPP(1, 75, 98, 128), /* GPP_H */ + INTEL_GPP(2, 99, 119, 160), /* GPP_D */ + INTEL_GPP(3, 120, 143, 192), /* GPP_U */ + INTEL_GPP(4, 144, 170, 224), /* vGPIO */ }; static const struct intel_padgroup tgllp_community4_gpps[] = { - TGL_GPP(0, 171, 194, 256), /* GPP_C */ - TGL_GPP(1, 195, 219, 288), /* GPP_F */ - TGL_GPP(2, 220, 225, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ - TGL_GPP(3, 226, 250, 320), /* GPP_E */ - TGL_GPP(4, 251, 259, INTEL_GPIO_BASE_NOMAP), /* JTAG */ + INTEL_GPP(0, 171, 194, 256), /* GPP_C */ + INTEL_GPP(1, 195, 219, 288), /* GPP_F */ + INTEL_GPP(2, 220, 225, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ + INTEL_GPP(3, 226, 250, 320), /* GPP_E */ + INTEL_GPP(4, 251, 259, INTEL_GPIO_BASE_NOMAP), /* JTAG */ }; static const struct intel_padgroup tgllp_community5_gpps[] = { - TGL_GPP(0, 260, 267, 352), /* GPP_R */ - TGL_GPP(1, 268, 276, INTEL_GPIO_BASE_NOMAP), /* SPI */ + INTEL_GPP(0, 260, 267, 352), /* GPP_R */ + INTEL_GPP(1, 268, 276, INTEL_GPIO_BASE_NOMAP), /* SPI */ }; static const struct intel_community tgllp_communities[] = { @@ -691,34 +683,34 @@ static const struct pinctrl_pin_desc tglh_pins[] = { }; static const struct intel_padgroup tglh_community0_gpps[] = { - TGL_GPP(0, 0, 24, 0), /* GPP_A */ - TGL_GPP(1, 25, 44, 32), /* GPP_R */ - TGL_GPP(2, 45, 70, 64), /* GPP_B */ - TGL_GPP(3, 71, 78, 96), /* vGPIO_0 */ + INTEL_GPP(0, 0, 24, 0), /* GPP_A */ + INTEL_GPP(1, 25, 44, 32), /* GPP_R */ + INTEL_GPP(2, 45, 70, 64), /* GPP_B */ + INTEL_GPP(3, 71, 78, 96), /* vGPIO_0 */ }; static const struct intel_padgroup tglh_community1_gpps[] = { - TGL_GPP(0, 79, 104, 128), /* GPP_D */ - TGL_GPP(1, 105, 128, 160), /* GPP_C */ - TGL_GPP(2, 129, 136, 192), /* GPP_S */ - TGL_GPP(3, 137, 153, 224), /* GPP_G */ - TGL_GPP(4, 154, 180, 256), /* vGPIO */ + INTEL_GPP(0, 79, 104, 128), /* GPP_D */ + INTEL_GPP(1, 105, 128, 160), /* GPP_C */ + INTEL_GPP(2, 129, 136, 192), /* GPP_S */ + INTEL_GPP(3, 137, 153, 224), /* GPP_G */ + INTEL_GPP(4, 154, 180, 256), /* vGPIO */ }; static const struct intel_padgroup tglh_community3_gpps[] = { - TGL_GPP(0, 181, 193, 288), /* GPP_E */ - TGL_GPP(1, 194, 217, 320), /* GPP_F */ + INTEL_GPP(0, 181, 193, 288), /* GPP_E */ + INTEL_GPP(1, 194, 217, 320), /* GPP_F */ }; static const struct intel_padgroup tglh_community4_gpps[] = { - TGL_GPP(0, 218, 241, 352), /* GPP_H */ - TGL_GPP(1, 242, 251, 384), /* GPP_J */ - TGL_GPP(2, 252, 266, 416), /* GPP_K */ + INTEL_GPP(0, 218, 241, 352), /* GPP_H */ + INTEL_GPP(1, 242, 251, 384), /* GPP_J */ + INTEL_GPP(2, 252, 266, 416), /* GPP_K */ }; static const struct intel_padgroup tglh_community5_gpps[] = { - TGL_GPP(0, 267, 281, 448), /* GPP_I */ - TGL_GPP(1, 282, 290, INTEL_GPIO_BASE_NOMAP), /* JTAG */ + INTEL_GPP(0, 267, 281, 448), /* GPP_I */ + INTEL_GPP(1, 282, 290, INTEL_GPIO_BASE_NOMAP), /* JTAG */ }; static const struct intel_community tglh_communities[] = { From d99b7a9d51ad9585c20427f99b83ea756bd84b4b Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 4 Nov 2025 15:56:44 +0100 Subject: [PATCH 074/107] pinctrl: sunrisepoint: Switch to INTEL_GPP() macro Replace custom macro with the recently defined INTEL_GPP(). Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-sunrisepoint.c | 26 +++++++------------- 1 file changed, 9 insertions(+), 17 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c index a7a5fa65fd9d..b51befde9e8b 100644 --- a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c +++ b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c @@ -28,14 +28,6 @@ #define SPT_LP_GPI_IS 0x100 #define SPT_LP_GPI_IE 0x120 -#define SPT_H_GPP(r, s, e, g) \ - { \ - .reg_num = (r), \ - .base = (s), \ - .size = ((e) - (s) + 1), \ - .gpio_base = (g), \ - } - #define SPT_H_COMMUNITY(b, s, e, g) \ INTEL_COMMUNITY_GPPS(b, s, e, g, SPT_H) @@ -538,21 +530,21 @@ static const struct intel_function spth_functions[] = { }; static const struct intel_padgroup spth_community0_gpps[] = { - SPT_H_GPP(0, 0, 23, 0), /* GPP_A */ - SPT_H_GPP(1, 24, 47, 24), /* GPP_B */ + INTEL_GPP(0, 0, 23, 0), /* GPP_A */ + INTEL_GPP(1, 24, 47, 24), /* GPP_B */ }; static const struct intel_padgroup spth_community1_gpps[] = { - SPT_H_GPP(0, 48, 71, 48), /* GPP_C */ - SPT_H_GPP(1, 72, 95, 72), /* GPP_D */ - SPT_H_GPP(2, 96, 108, 96), /* GPP_E */ - SPT_H_GPP(3, 109, 132, 120), /* GPP_F */ - SPT_H_GPP(4, 133, 156, 144), /* GPP_G */ - SPT_H_GPP(5, 157, 180, 168), /* GPP_H */ + INTEL_GPP(0, 48, 71, 48), /* GPP_C */ + INTEL_GPP(1, 72, 95, 72), /* GPP_D */ + INTEL_GPP(2, 96, 108, 96), /* GPP_E */ + INTEL_GPP(3, 109, 132, 120), /* GPP_F */ + INTEL_GPP(4, 133, 156, 144), /* GPP_G */ + INTEL_GPP(5, 157, 180, 168), /* GPP_H */ }; static const struct intel_padgroup spth_community3_gpps[] = { - SPT_H_GPP(0, 181, 191, 192), /* GPP_I */ + INTEL_GPP(0, 181, 191, 192), /* GPP_I */ }; static const struct intel_community spth_communities[] = { From b737322278ffabd2766ac681c28553609a48694e Mon Sep 17 00:00:00 2001 From: Thanh Quan Date: Tue, 4 Nov 2025 17:59:43 +0100 Subject: [PATCH 075/107] pinctrl: renesas: r8a779g0: Remove AVB[01]_MII MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rev.1.30 of the R-Car V4H Series Hardware User’s Manual removed the "AVB[01]_MII_*" signals from the pin control register tables. As these are further unused in the pin control driver, they can be removed safely. Signed-off-by: Thanh Quan Signed-off-by: Geert Uytterhoeven Reviewed-by: Marek Vasut Link: https://patch.msgid.link/58662f50136280532bcc8bbe94741d82425bd118.1762274384.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pfc-r8a779g0.c | 96 +++++++++----------------- 1 file changed, 32 insertions(+), 64 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c index 218c5eff9b67..bf34e206f6f6 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c @@ -471,55 +471,55 @@ #define IP0SR6_7_4 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR6_11_8 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR6_15_12 FM(AVB1_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR6_19_16 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR6_23_20 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR6_27_24 FM(AVB1_TXC) FM(AVB1_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR6_31_28 FM(AVB1_TX_CTL) FM(AVB1_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR6_19_16 FM(AVB1_LINK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR6_23_20 FM(AVB1_AVTP_MATCH) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR6_27_24 FM(AVB1_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR6_31_28 FM(AVB1_TX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* IP1SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP1SR6_3_0 FM(AVB1_RXC) FM(AVB1_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR6_7_4 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR6_11_8 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR6_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR6_19_16 FM(AVB1_TD1) FM(AVB1_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR6_23_20 FM(AVB1_TD0) FM(AVB1_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR6_27_24 FM(AVB1_RD1) FM(AVB1_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR6_31_28 FM(AVB1_RD0) FM(AVB1_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR6_3_0 FM(AVB1_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR6_7_4 FM(AVB1_RX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR6_11_8 FM(AVB1_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR6_15_12 FM(AVB1_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR6_19_16 FM(AVB1_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR6_23_20 FM(AVB1_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR6_27_24 FM(AVB1_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR6_31_28 FM(AVB1_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* IP2SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP2SR6_3_0 FM(AVB1_TD2) FM(AVB1_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR6_7_4 FM(AVB1_RD2) FM(AVB1_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR6_11_8 FM(AVB1_TD3) FM(AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR6_15_12 FM(AVB1_RD3) FM(AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR6_3_0 FM(AVB1_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR6_7_4 FM(AVB1_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR6_11_8 FM(AVB1_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR6_15_12 FM(AVB1_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2SR6_19_16 FM(AVB1_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* SR7 */ /* IP0SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP0SR7_3_0 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR7_7_4 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR7_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR7_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR7_19_16 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR7_3_0 FM(AVB0_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR7_7_4 FM(AVB0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR7_11_8 FM(AVB0_AVTP_MATCH) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR7_15_12 FM(AVB0_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR7_19_16 FM(AVB0_LINK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR7_23_20 FM(AVB0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR7_27_24 FM(AVB0_TD2) FM(AVB0_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR7_31_28 FM(AVB0_TD1) FM(AVB0_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR7_27_24 FM(AVB0_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR7_31_28 FM(AVB0_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* IP1SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP1SR7_3_0 FM(AVB0_RD3) FM(AVB0_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR7_3_0 FM(AVB0_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1SR7_7_4 FM(AVB0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1SR7_11_8 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR7_15_12 FM(AVB0_TD0) FM(AVB0_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR7_19_16 FM(AVB0_RD2) FM(AVB0_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR7_15_12 FM(AVB0_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR7_19_16 FM(AVB0_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1SR7_23_20 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1SR7_27_24 FM(AVB0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR7_31_28 FM(AVB0_TXC) FM(AVB0_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR7_31_28 FM(AVB0_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* IP2SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP2SR7_3_0 FM(AVB0_TX_CTL) FM(AVB0_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR7_7_4 FM(AVB0_RD1) FM(AVB0_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR7_11_8 FM(AVB0_RD0) FM(AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR7_15_12 FM(AVB0_RXC) FM(AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR7_19_16 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR7_3_0 FM(AVB0_TX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR7_7_4 FM(AVB0_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR7_11_8 FM(AVB0_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR7_15_12 FM(AVB0_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR7_19_16 FM(AVB0_RX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* SR8 */ /* IP0SR8 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ @@ -1076,118 +1076,86 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP0SR6_15_12, AVB1_PHY_INT), PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_LINK), - PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_MII_TX_ER), PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_AVTP_MATCH), - PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_MII_RX_ER), PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_TXC), - PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_MII_TXC), PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_TX_CTL), - PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_MII_TX_EN), /* IP1SR6 */ PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_RXC), - PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_MII_RXC), PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_RX_CTL), - PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_MII_RX_DV), PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_AVTP_PPS), - PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_MII_COL), PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_AVTP_CAPTURE), - PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_MII_CRS), PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_TD1), - PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_MII_TD1), PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_TD0), - PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_MII_TD0), PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_RD1), - PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_MII_RD1), PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_RD0), - PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_MII_RD0), /* IP2SR6 */ PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_TD2), - PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_MII_TD2), PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_RD2), - PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_MII_RD2), PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_TD3), - PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_MII_TD3), PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_RD3), - PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_MII_RD3), PINMUX_IPSR_GPSR(IP2SR6_19_16, AVB1_TXCREFCLK), /* IP0SR7 */ PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_AVTP_PPS), - PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_MII_COL), PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_AVTP_CAPTURE), - PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_MII_CRS), PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_AVTP_MATCH), - PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_MII_RX_ER), PINMUX_IPSR_GPSR(IP0SR7_11_8, CC5_OSCOUT), PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_TD3), - PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_MII_TD3), PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_LINK), - PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_MII_TX_ER), PINMUX_IPSR_GPSR(IP0SR7_23_20, AVB0_PHY_INT), PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_TD2), - PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_MII_TD2), PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_TD1), - PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_MII_TD1), /* IP1SR7 */ PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_RD3), - PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_MII_RD3), PINMUX_IPSR_GPSR(IP1SR7_7_4, AVB0_TXCREFCLK), PINMUX_IPSR_GPSR(IP1SR7_11_8, AVB0_MAGIC), PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_TD0), - PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_MII_TD0), PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_RD2), - PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_MII_RD2), PINMUX_IPSR_GPSR(IP1SR7_23_20, AVB0_MDC), PINMUX_IPSR_GPSR(IP1SR7_27_24, AVB0_MDIO), PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_TXC), - PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_MII_TXC), /* IP2SR7 */ PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_TX_CTL), - PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_MII_TX_EN), PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_RD1), - PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_MII_RD1), PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_RD0), - PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_MII_RD0), PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_RXC), - PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_MII_RXC), PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_RX_CTL), - PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_MII_RX_DV), /* IP0SR8 */ PINMUX_IPSR_MSEL(IP0SR8_3_0, SCL0, SEL_SCL0_0), From ac4e5f4ab6f367be3d5acfe2d3cfc519d149d7ac Mon Sep 17 00:00:00 2001 From: Huy Bui Date: Tue, 4 Nov 2025 17:59:44 +0100 Subject: [PATCH 076/107] pinctrl: renesas: r8a779g0: Remove CC5_OSCOUT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rev.1.30 of the R-Car V4H Series Hardware User’s Manual removed the "CC5_OSCOUT" signal from the pin control register tables. As this is further unused in the pin control driver, it can be removed safely. Signed-off-by: Huy Bui Signed-off-by: Geert Uytterhoeven Reviewed-by: Marek Vasut Link: https://patch.msgid.link/77f9efe5388f2801ace945b7793d4823618eeec8.1762274384.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pfc-r8a779g0.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c index bf34e206f6f6..945e4f87806d 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c @@ -497,7 +497,7 @@ /* IP0SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ #define IP0SR7_3_0 FM(AVB0_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR7_7_4 FM(AVB0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR7_11_8 FM(AVB0_AVTP_MATCH) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR7_11_8 FM(AVB0_AVTP_MATCH) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR7_15_12 FM(AVB0_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR7_19_16 FM(AVB0_LINK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR7_23_20 FM(AVB0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -1117,7 +1117,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_AVTP_CAPTURE), PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_AVTP_MATCH), - PINMUX_IPSR_GPSR(IP0SR7_11_8, CC5_OSCOUT), PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_TD3), From 87f8ed0518bd7d792948809f3bf8f789522fad74 Mon Sep 17 00:00:00 2001 From: Huy Bui Date: Tue, 4 Nov 2025 17:59:45 +0100 Subject: [PATCH 077/107] pinctrl: renesas: r8a779g0: Remove STPWT_EXTFXR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rev.1.30 of the R-Car V4H Series Hardware User’s Manual removed the "STPWT_EXTFXR" signal from the pin control register tables. As this is further unused in the pin control driver, it can be removed safely. Signed-off-by: Huy Bui Signed-off-by: Geert Uytterhoeven Reviewed-by: Marek Vasut Link: https://patch.msgid.link/f6cfdbbc024d85e87583a1d57ea01582632f1216.1762274384.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pfc-r8a779g0.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c index 945e4f87806d..1c8abd68583a 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c @@ -352,7 +352,7 @@ #define IP1SR2_3_0 FM(TPU0TO0_A) FM(CANFD6_RX) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_15_12 FM(CANFD0_RX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2_A) F_(0, 0) FM(TCLK3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3_A) FM(PWM1_B) FM(TCLK4_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -925,7 +925,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP1SR2_11_8, FXR_TXENB_N_B), PINMUX_IPSR_GPSR(IP1SR2_15_12, CANFD0_RX), - PINMUX_IPSR_GPSR(IP1SR2_15_12, STPWT_EXTFXR), PINMUX_IPSR_GPSR(IP1SR2_19_16, CANFD2_TX), PINMUX_IPSR_GPSR(IP1SR2_19_16, TPU0TO2_A), From 3a430f50b8ceaae345ee507abfa5e7360819db71 Mon Sep 17 00:00:00 2001 From: Huy Bui Date: Tue, 4 Nov 2025 17:59:46 +0100 Subject: [PATCH 078/107] pinctrl: renesas: r8a779h0: Remove CC5_OSCOUT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rev.0.71 of the R-Car V4M Series Hardware User’s Manual removed the "CC5_OSCOUT" signal from the pin control register tables. As this is further unused in the pin control driver, it can be removed safely. Signed-off-by: Huy Bui Signed-off-by: Geert Uytterhoeven Reviewed-by: Marek Vasut Link: https://patch.msgid.link/895bb560467309706931d14aeea0e063ad0e86eb.1762274384.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pfc-r8a779h0.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a779h0.c b/drivers/pinctrl/renesas/pfc-r8a779h0.c index 63b3725a0cf6..cee7690ea19d 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779h0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779h0.c @@ -478,7 +478,7 @@ /* IP0SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ #define IP0SR7_3_0 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR7_7_4 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR7_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR7_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR7_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR7_19_16 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR7_23_20 FM(AVB0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -1123,7 +1123,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_AVTP_MATCH), PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_MII_RX_ER), - PINMUX_IPSR_GPSR(IP0SR7_11_8, CC5_OSCOUT), PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_TD3), PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_MII_TD3), From 8903597df7b6d511f81abb47708a33e9a1e6a530 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 4 Nov 2025 17:59:47 +0100 Subject: [PATCH 079/107] pinctrl: renesas: r8a779h0: Remove STPWT_EXTFXR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rev.0.81 of the R-Car V4M Series Hardware User’s Manual removed the "STPWT_EXTFXR" signal from the pin control register tables. As this is further unused in the pin control driver, it can be removed safely. Signed-off-by: Geert Uytterhoeven Reviewed-by: Marek Vasut Link: https://patch.msgid.link/f849fa3b9b516e9dd04b45462b69f52225259480.1762274384.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pfc-r8a779h0.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a779h0.c b/drivers/pinctrl/renesas/pfc-r8a779h0.c index cee7690ea19d..ec0fc1bf7a90 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779h0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779h0.c @@ -339,7 +339,7 @@ #define IP1SR2_3_0 FM(TPU0TO0_A) F_(0, 0) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_15_12 FM(CANFD0_RX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2_A) F_(0, 0) FM(TCLK3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3_A) FM(PWM1_B) FM(TCLK4_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -865,7 +865,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP1SR2_11_8, FXR_TXENB_N_B), PINMUX_IPSR_GPSR(IP1SR2_15_12, CANFD0_RX), - PINMUX_IPSR_GPSR(IP1SR2_15_12, STPWT_EXTFXR), PINMUX_IPSR_GPSR(IP1SR2_19_16, CANFD2_TX), PINMUX_IPSR_GPSR(IP1SR2_19_16, TPU0TO2_A), From ea2bfb853b15f01b6a24e3fb020feb1c0568873b Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Mon, 27 Oct 2025 16:26:41 -0500 Subject: [PATCH 080/107] dt-bindings: pinctrl: Convert sprd,sc9860-pinctrl to DT schema Convert the sprd,sc9860-pinctrl binding to DT schema format. What's valid for the the sleep mode child nodes wasn't well defined. The schema is based on the example (as there's no .dts with pin states) and the driver's register definitions. Signed-off-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- .../bindings/pinctrl/sprd,pinctrl.txt | 83 -------- .../bindings/pinctrl/sprd,sc9860-pinctrl.txt | 70 ------ .../bindings/pinctrl/sprd,sc9860-pinctrl.yaml | 199 ++++++++++++++++++ 3 files changed, 199 insertions(+), 153 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/sprd,pinctrl.txt delete mode 100644 Documentation/devicetree/bindings/pinctrl/sprd,sc9860-pinctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/sprd,sc9860-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/sprd,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/sprd,pinctrl.txt deleted file mode 100644 index 779b8ef0f6e6..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/sprd,pinctrl.txt +++ /dev/null @@ -1,83 +0,0 @@ -* Spreadtrum Pin Controller - -The Spreadtrum pin controller are organized in 3 blocks (types). - -The first block comprises some global control registers, and each -register contains several bit fields with one bit or several bits -to configure for some global common configuration, such as domain -pad driving level, system control select and so on ("domain pad -driving level": One pin can output 3.0v or 1.8v, depending on the -related domain pad driving selection, if the related domain pad -select 3.0v, then the pin can output 3.0v. "system control" is used -to choose one function (like: UART0) for which system, since we -have several systems (AP/CP/CM4) on one SoC.). - -There are too much various configuration that we can not list all -of them, so we can not make every Spreadtrum-special configuration -as one generic configuration, and maybe it will add more strange -global configuration in future. Then we add one "sprd,control" to -set these various global control configuration, and we need use -magic number for this property. - -Moreover we recognise every fields comprising one bit or several -bits in one global control register as one pin, thus we should -record every pin's bit offset, bit width and register offset to -configure this field (pin). - -The second block comprises some common registers which have unified -register definition, and each register described one pin is used -to configure the pin sleep mode, function select and sleep related -configuration. - -Now we have 4 systems for sleep mode on SC9860 SoC: AP system, -PUBCP system, TGLDSP system and AGDSP system. And the pin sleep -related configuration are: -- input-enable -- input-disable -- output-high -- output-low -- bias-pull-up -- bias-pull-down - -In some situation we need set the pin sleep mode and pin sleep related -configuration, to set the pin sleep related configuration automatically -by hardware when the system specified by sleep mode goes into deep -sleep mode. For example, if we set the pin sleep mode as PUBCP_SLEEP -and set the pin sleep related configuration as "input-enable", which -means when PUBCP system goes into deep sleep mode, this pin will be set -input enable automatically. - -Moreover we can not use the "sleep" state, since some systems (like: -PUBCP system) do not run linux kernel OS (only AP system run linux -kernel on SC9860 platform), then we can not select "sleep" state -when the PUBCP system goes into deep sleep mode. Thus we introduce -"sprd,sleep-mode" property to set pin sleep mode. - -The last block comprises some misc registers which also have unified -register definition, and each register described one pin is used to -configure drive strength, pull up/down and so on. Especially for pull -up, we have two kind pull up resistor: 20K and 4.7K. - -Required properties for Spreadtrum pin controller: -- compatible: "sprd,-pinctrl" - Please refer to each sprd,-pinctrl.txt binding doc for supported SoCs. -- reg: The register address of pin controller device. -- pins : An array of pin names. - -Optional properties: -- function: Specified the function name. -- drive-strength: Drive strength in mA. -- input-schmitt-disable: Enable schmitt-trigger mode. -- input-schmitt-enable: Disable schmitt-trigger mode. -- bias-disable: Disable pin bias. -- bias-pull-down: Pull down on pin. -- bias-pull-up: Pull up on pin. -- input-enable: Enable pin input. -- input-disable: Enable pin output. -- output-high: Set the pin as an output level high. -- output-low: Set the pin as an output level low. -- sleep-hardware-state: Indicate these configs in this state are sleep related. -- sprd,control: Control values referring to databook for global control pins. -- sprd,sleep-mode: Sleep mode selection. - -Please refer to each sprd,-pinctrl.txt binding doc for supported values. diff --git a/Documentation/devicetree/bindings/pinctrl/sprd,sc9860-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/sprd,sc9860-pinctrl.txt deleted file mode 100644 index 5a628333d52f..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/sprd,sc9860-pinctrl.txt +++ /dev/null @@ -1,70 +0,0 @@ -* Spreadtrum SC9860 Pin Controller - -Please refer to sprd,pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: Must be "sprd,sc9860-pinctrl". -- reg: The register address of pin controller device. -- pins : An array of strings, each string containing the name of a pin. - -Optional properties: -- function: A string containing the name of the function, values must be - one of: "func1", "func2", "func3" and "func4". -- drive-strength: Drive strength in mA. Supported values: 2, 4, 6, 8, 10, - 12, 14, 16, 20, 21, 24, 25, 27, 29, 31 and 33. -- input-schmitt-disable: Enable schmitt-trigger mode. -- input-schmitt-enable: Disable schmitt-trigger mode. -- bias-disable: Disable pin bias. -- bias-pull-down: Pull down on pin. -- bias-pull-up: Pull up on pin. Supported values: 20000 for pull-up resistor - is 20K and 4700 for pull-up resistor is 4.7K. -- input-enable: Enable pin input. -- input-disable: Enable pin output. -- output-high: Set the pin as an output level high. -- output-low: Set the pin as an output level low. -- sleep-hardware-state: Indicate these configs in this state are sleep related. -- sprd,control: Control values referring to databook for global control pins. -- sprd,sleep-mode: Choose the pin sleep mode, and supported values are: - AP_SLEEP, PUBCP_SLEEP, TGLDSP_SLEEP and AGDSP_SLEEP. - -Pin sleep mode definition: -enum pin_sleep_mode { - AP_SLEEP = BIT(0), - PUBCP_SLEEP = BIT(1), - TGLDSP_SLEEP = BIT(2), - AGDSP_SLEEP = BIT(3), -}; - -Example: -pin_controller: pinctrl@402a0000 { - compatible = "sprd,sc9860-pinctrl"; - reg = <0x402a0000 0x10000>; - - grp1: sd0 { - pins = "SC9860_VIO_SD2_IRTE", "SC9860_VIO_SD0_IRTE"; - sprd,control = <0x1>; - }; - - grp2: rfctl_33 { - pins = "SC9860_RFCTL33"; - function = "func2"; - sprd,sleep-mode = ; - grp2_sleep_mode: rfctl_33_sleep { - pins = "SC9860_RFCTL33"; - sleep-hardware-state; - output-low; - } - }; - - grp3: rfctl_misc_20 { - pins = "SC9860_RFCTL20_MISC"; - drive-strength = <10>; - bias-pull-up = <4700>; - grp3_sleep_mode: rfctl_misc_sleep { - pins = "SC9860_RFCTL20_MISC"; - sleep-hardware-state; - bias-pull-up; - } - }; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/sprd,sc9860-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/sprd,sc9860-pinctrl.yaml new file mode 100644 index 000000000000..59d23eb8aa97 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/sprd,sc9860-pinctrl.yaml @@ -0,0 +1,199 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/sprd,sc9860-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Spreadtrum SC9860 Pin Controller + +maintainers: + - Baolin Wang + +description: > + The Spreadtrum pin controller are organized in 3 blocks (types). + + The first block comprises some global control registers, and each + register contains several bit fields with one bit or several bits + to configure for some global common configuration, such as domain + pad driving level, system control select and so on ("domain pad + driving level": One pin can output 3.0v or 1.8v, depending on the + related domain pad driving selection, if the related domain pad + select 3.0v, then the pin can output 3.0v. "system control" is used + to choose one function (like: UART0) for which system, since we + have several systems (AP/CP/CM4) on one SoC.). + + There are too much various configuration that we can not list all + of them, so we can not make every Spreadtrum-special configuration + as one generic configuration, and maybe it will add more strange + global configuration in future. Then we add one "sprd,control" to + set these various global control configuration, and we need use + magic number for this property. + + Moreover we recognize every fields comprising one bit or several + bits in one global control register as one pin, thus we should + record every pin's bit offset, bit width and register offset to + configure this field (pin). + + The second block comprises some common registers which have unified + register definition, and each register described one pin is used + to configure the pin sleep mode, function select and sleep related + configuration. + + Now we have 4 systems for sleep mode on SC9860 SoC: AP system, + PUBCP system, TGLDSP system and AGDSP system. And the pin sleep + related configuration are: + - input-enable + - input-disable + - output-high + - output-low + - bias-pull-up + - bias-pull-down + + In some situation we need set the pin sleep mode and pin sleep related + configuration, to set the pin sleep related configuration automatically + by hardware when the system specified by sleep mode goes into deep + sleep mode. For example, if we set the pin sleep mode as PUBCP_SLEEP + and set the pin sleep related configuration as "input-enable", which + means when PUBCP system goes into deep sleep mode, this pin will be set + input enable automatically. + + Moreover we can not use the "sleep" state, since some systems (like: + PUBCP system) do not run linux kernel OS (only AP system run linux + kernel on SC9860 platform), then we can not select "sleep" state + when the PUBCP system goes into deep sleep mode. Thus we introduce + "sprd,sleep-mode" property to set pin sleep mode. + + The last block comprises some misc registers which also have unified + register definition, and each register described one pin is used to + configure drive strength, pull up/down and so on. Especially for pull + up, we have two kind pull up resistor: 20K and 4.7K. + +properties: + compatible: + const: sprd,sc9860-pinctrl + + reg: + maxItems: 1 + +additionalProperties: + $ref: '#/$defs/pin-node' + unevaluatedProperties: false + + properties: + function: + description: Function to assign to the pins. + enum: + - func1 + - func2 + - func3 + - func4 + + drive-strength: + description: Drive strength in mA. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [2, 4, 6, 8, 10, 12, 14, 16, 20, 21, 24, 25, 27, 29, 31, 33] + + input-schmitt-disable: true + + input-schmitt-enable: true + + bias-pull-up: + enum: [20000, 4700] + + sprd,sleep-mode: + description: Pin sleep mode selection. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 0x1f + + sprd,control: + description: Control values referring to databook for global control pins. + $ref: /schemas/types.yaml#/definitions/uint32 + + patternProperties: + 'sleep$': + $ref: '#/$defs/pin-node' + unevaluatedProperties: false + + properties: + bias-pull-up: + type: boolean + + sleep-hardware-state: + description: Indicate these configs in sleep related state. + type: boolean + +$defs: + pin-node: + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml# + - $ref: /schemas/pinctrl/pinmux-node.yaml# + + properties: + pins: + description: Names of pins to configure. + $ref: /schemas/types.yaml#/definitions/string-array + + bias-disable: + description: Disable pin bias. + type: boolean + + bias-pull-down: + description: Pull down on pin. + type: boolean + + bias-pull-up: true + + input-enable: + description: Enable pin input. + type: boolean + + input-disable: + description: Enable pin output. + type: boolean + + output-high: + description: Set the pin as an output level high. + type: boolean + + output-low: + description: Set the pin as an output level low. + type: boolean + +required: + - compatible + - reg + +examples: + - | + pin_controller: pinctrl@402a0000 { + compatible = "sprd,sc9860-pinctrl"; + reg = <0x402a0000 0x10000>; + + grp1: sd0 { + pins = "SC9860_VIO_SD2_IRTE", "SC9860_VIO_SD0_IRTE"; + sprd,control = <0x1>; + }; + + grp2: rfctl_33 { + pins = "SC9860_RFCTL33"; + function = "func2"; + sprd,sleep-mode = <3>; + grp2_sleep_mode: rfctl_33_sleep { + pins = "SC9860_RFCTL33"; + sleep-hardware-state; + output-low; + }; + }; + + grp3: rfctl_misc_20 { + pins = "SC9860_RFCTL20_MISC"; + drive-strength = <10>; + bias-pull-up = <4700>; + grp3_sleep_mode: rfctl_misc_sleep { + pins = "SC9860_RFCTL20_MISC"; + sleep-hardware-state; + bias-pull-up; + }; + }; + }; From 13064950339ffc73a0e55e9b4898df861b04848e Mon Sep 17 00:00:00 2001 From: Ye Zhang Date: Tue, 4 Nov 2025 10:12:21 +0800 Subject: [PATCH 081/107] dt-bindings: pinctrl: Add rk3506 pinctrl support Add the compatible string for the rk3506 SoC. Signed-off-by: Ye Zhang Acked-by: Krzysztof Kozlowski Reviewed-by: Heiko Stuebner Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml index 125af766b992..76e607281716 100644 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml @@ -44,6 +44,7 @@ properties: - rockchip,rk3328-pinctrl - rockchip,rk3368-pinctrl - rockchip,rk3399-pinctrl + - rockchip,rk3506-pinctrl - rockchip,rk3528-pinctrl - rockchip,rk3562-pinctrl - rockchip,rk3568-pinctrl From dbd2317d7b9f88b7b4b7de0d48173ee178f2ac97 Mon Sep 17 00:00:00 2001 From: Ye Zhang Date: Tue, 4 Nov 2025 10:12:22 +0800 Subject: [PATCH 082/107] pinctrl: rockchip: Add rk3506 pinctrl support Add support for the 5 rk3506 GPIO banks. Signed-off-by: Ye Zhang Reviewed-by: Heiko Stuebner Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-rockchip.c | 442 ++++++++++++++++++++++++++++- drivers/pinctrl/pinctrl-rockchip.h | 4 + 2 files changed, 438 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 7a68a6237649..e44ef262beec 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -105,6 +105,29 @@ .pull_type[3] = pull3, \ } +#define PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(id, pins, label, iom0, \ + iom1, iom2, iom3, \ + offset0, offset1, \ + offset2, offset3, drv0, \ + drv1, drv2, drv3) \ + { \ + .bank_num = id, \ + .nr_pins = pins, \ + .name = label, \ + .iomux = { \ + { .type = iom0, .offset = offset0 }, \ + { .type = iom1, .offset = offset1 }, \ + { .type = iom2, .offset = offset2 }, \ + { .type = iom3, .offset = offset3 }, \ + }, \ + .drv = { \ + { .drv_type = drv0, .offset = -1 }, \ + { .drv_type = drv1, .offset = -1 }, \ + { .drv_type = drv2, .offset = -1 }, \ + { .drv_type = drv3, .offset = -1 }, \ + }, \ + } + #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ { \ .bank_num = id, \ @@ -233,6 +256,35 @@ .pull_type[3] = pull3, \ } +#define PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS_PULL_FLAGS(id, pins, \ + label, iom0, iom1, \ + iom2, iom3, offset0, \ + offset1, offset2, \ + offset3, drv0, drv1, \ + drv2, drv3, pull0, \ + pull1, pull2, pull3) \ + { \ + .bank_num = id, \ + .nr_pins = pins, \ + .name = label, \ + .iomux = { \ + { .type = iom0, .offset = offset0 }, \ + { .type = iom1, .offset = offset1 }, \ + { .type = iom2, .offset = offset2 }, \ + { .type = iom3, .offset = offset3 }, \ + }, \ + .drv = { \ + { .drv_type = drv0, .offset = -1 }, \ + { .drv_type = drv1, .offset = -1 }, \ + { .drv_type = drv2, .offset = -1 }, \ + { .drv_type = drv3, .offset = -1 }, \ + }, \ + .pull_type[0] = pull0, \ + .pull_type[1] = pull1, \ + .pull_type[2] = pull2, \ + .pull_type[3] = pull3, \ + } + #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \ { \ .bank_num = ID, \ @@ -1120,6 +1172,13 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) else regmap = info->regmap_base; + if (ctrl->type == RK3506) { + if (bank->bank_num == 1) + regmap = info->regmap_ioc1; + else if (bank->bank_num == 4) + return 0; + } + /* get basic quadrupel of mux registers and the correct reg inside */ mux_type = bank->iomux[iomux_num].type; reg = bank->iomux[iomux_num].offset; @@ -1239,6 +1298,13 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) else regmap = info->regmap_base; + if (ctrl->type == RK3506) { + if (bank->bank_num == 1) + regmap = info->regmap_ioc1; + else if (bank->bank_num == 4) + return 0; + } + /* get basic quadrupel of mux registers and the correct reg inside */ mux_type = bank->iomux[iomux_num].type; reg = bank->iomux[iomux_num].offset; @@ -2003,6 +2069,262 @@ static int rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, return 0; } +#define RK3506_DRV_BITS_PER_PIN 8 +#define RK3506_DRV_PINS_PER_REG 2 +#define RK3506_DRV_GPIO0_A_OFFSET 0x100 +#define RK3506_DRV_GPIO0_D_OFFSET 0x830 +#define RK3506_DRV_GPIO1_OFFSET 0x140 +#define RK3506_DRV_GPIO2_OFFSET 0x180 +#define RK3506_DRV_GPIO3_OFFSET 0x1c0 +#define RK3506_DRV_GPIO4_OFFSET 0x840 + +static int rk3506_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + int ret = 0; + + switch (bank->bank_num) { + case 0: + *regmap = info->regmap_pmu; + if (pin_num > 24) { + ret = -EINVAL; + } else if (pin_num < 24) { + *reg = RK3506_DRV_GPIO0_A_OFFSET; + } else { + *reg = RK3506_DRV_GPIO0_D_OFFSET; + *bit = 3; + + return 0; + } + break; + + case 1: + *regmap = info->regmap_ioc1; + if (pin_num < 28) + *reg = RK3506_DRV_GPIO1_OFFSET; + else + ret = -EINVAL; + break; + + case 2: + *regmap = info->regmap_base; + if (pin_num < 17) + *reg = RK3506_DRV_GPIO2_OFFSET; + else + ret = -EINVAL; + break; + + case 3: + *regmap = info->regmap_base; + if (pin_num < 15) + *reg = RK3506_DRV_GPIO3_OFFSET; + else + ret = -EINVAL; + break; + + case 4: + *regmap = info->regmap_base; + if (pin_num < 8 || pin_num > 11) { + ret = -EINVAL; + } else { + *reg = RK3506_DRV_GPIO4_OFFSET; + *bit = 10; + + return 0; + } + break; + + default: + ret = -EINVAL; + break; + } + + if (ret) { + dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num); + + return ret; + } + + *reg += ((pin_num / RK3506_DRV_PINS_PER_REG) * 4); + *bit = pin_num % RK3506_DRV_PINS_PER_REG; + *bit *= RK3506_DRV_BITS_PER_PIN; + + return 0; +} + +#define RK3506_PULL_BITS_PER_PIN 2 +#define RK3506_PULL_PINS_PER_REG 8 +#define RK3506_PULL_GPIO0_A_OFFSET 0x200 +#define RK3506_PULL_GPIO0_D_OFFSET 0x830 +#define RK3506_PULL_GPIO1_OFFSET 0x210 +#define RK3506_PULL_GPIO2_OFFSET 0x220 +#define RK3506_PULL_GPIO3_OFFSET 0x230 +#define RK3506_PULL_GPIO4_OFFSET 0x840 + +static int rk3506_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + int ret = 0; + + switch (bank->bank_num) { + case 0: + *regmap = info->regmap_pmu; + if (pin_num > 24) { + ret = -EINVAL; + } else if (pin_num < 24) { + *reg = RK3506_PULL_GPIO0_A_OFFSET; + } else { + *reg = RK3506_PULL_GPIO0_D_OFFSET; + *bit = 5; + + return 0; + } + break; + + case 1: + *regmap = info->regmap_ioc1; + if (pin_num < 28) + *reg = RK3506_PULL_GPIO1_OFFSET; + else + ret = -EINVAL; + break; + + case 2: + *regmap = info->regmap_base; + if (pin_num < 17) + *reg = RK3506_PULL_GPIO2_OFFSET; + else + ret = -EINVAL; + break; + + case 3: + *regmap = info->regmap_base; + if (pin_num < 15) + *reg = RK3506_PULL_GPIO3_OFFSET; + else + ret = -EINVAL; + break; + + case 4: + *regmap = info->regmap_base; + if (pin_num < 8 || pin_num > 11) { + ret = -EINVAL; + } else { + *reg = RK3506_PULL_GPIO4_OFFSET; + *bit = 13; + + return 0; + } + break; + + default: + ret = -EINVAL; + break; + } + + if (ret) { + dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num); + + return ret; + } + + *reg += ((pin_num / RK3506_PULL_PINS_PER_REG) * 4); + *bit = pin_num % RK3506_PULL_PINS_PER_REG; + *bit *= RK3506_PULL_BITS_PER_PIN; + + return 0; +} + +#define RK3506_SMT_BITS_PER_PIN 1 +#define RK3506_SMT_PINS_PER_REG 8 +#define RK3506_SMT_GPIO0_A_OFFSET 0x400 +#define RK3506_SMT_GPIO0_D_OFFSET 0x830 +#define RK3506_SMT_GPIO1_OFFSET 0x410 +#define RK3506_SMT_GPIO2_OFFSET 0x420 +#define RK3506_SMT_GPIO3_OFFSET 0x430 +#define RK3506_SMT_GPIO4_OFFSET 0x840 + +static int rk3506_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, + struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + int ret = 0; + + switch (bank->bank_num) { + case 0: + *regmap = info->regmap_pmu; + if (pin_num > 24) { + ret = -EINVAL; + } else if (pin_num < 24) { + *reg = RK3506_SMT_GPIO0_A_OFFSET; + } else { + *reg = RK3506_SMT_GPIO0_D_OFFSET; + *bit = 9; + + return 0; + } + break; + + case 1: + *regmap = info->regmap_ioc1; + if (pin_num < 28) + *reg = RK3506_SMT_GPIO1_OFFSET; + else + ret = -EINVAL; + break; + + case 2: + *regmap = info->regmap_base; + if (pin_num < 17) + *reg = RK3506_SMT_GPIO2_OFFSET; + else + ret = -EINVAL; + break; + + case 3: + *regmap = info->regmap_base; + if (pin_num < 15) + *reg = RK3506_SMT_GPIO3_OFFSET; + else + ret = -EINVAL; + break; + + case 4: + *regmap = info->regmap_base; + if (pin_num < 8 || pin_num > 11) { + ret = -EINVAL; + } else { + *reg = RK3506_SMT_GPIO4_OFFSET; + *bit = 8; + + return 0; + } + break; + + default: + ret = -EINVAL; + break; + } + + if (ret) { + dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num); + + return ret; + } + + *reg += ((pin_num / RK3506_SMT_PINS_PER_REG) * 4); + *bit = pin_num % RK3506_SMT_PINS_PER_REG; + *bit *= RK3506_SMT_BITS_PER_PIN; + + return 0; +} + #define RK3528_DRV_BITS_PER_PIN 8 #define RK3528_DRV_PINS_PER_REG 2 #define RK3528_DRV_GPIO0_OFFSET 0x100 @@ -2749,7 +3071,8 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, rmask_bits = RK3588_DRV_BITS_PER_PIN; ret = strength; goto config; - } else if (ctrl->type == RK3528 || + } else if (ctrl->type == RK3506 || + ctrl->type == RK3528 || ctrl->type == RK3562 || ctrl->type == RK3568) { rmask_bits = RK3568_DRV_BITS_PER_PIN; @@ -2828,12 +3151,37 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, case DRV_TYPE_IO_1V8_ONLY: rmask_bits = RK3288_DRV_BITS_PER_PIN; break; + case DRV_TYPE_IO_LEVEL_2_BIT: + ret = regmap_read(regmap, reg, &data); + if (ret) + return ret; + data >>= bit; + + return data & 0x3; + case DRV_TYPE_IO_LEVEL_8_BIT: + ret = regmap_read(regmap, reg, &data); + if (ret) + return ret; + data >>= bit; + data &= (1 << 8) - 1; + + ret = hweight8(data); + if (ret > 0) + return ret - 1; + else + return -EINVAL; default: dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type); return -EINVAL; } config: + if (ctrl->type == RK3506) { + if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) { + rmask_bits = 2; + ret = strength; + } + } /* enable the write to the equivalent lower bits */ data = ((1 << rmask_bits) - 1) << (bit + 16); rmask = data | (data >> 16); @@ -2957,6 +3305,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, case RK3328: case RK3368: case RK3399: + case RK3506: case RK3528: case RK3562: case RK3568: @@ -3077,6 +3426,10 @@ static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num) break; } + if (ctrl->type == RK3506) + if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) + return data & 0x3; + return data & 0x1; } @@ -3112,6 +3465,14 @@ static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, break; } + if (ctrl->type == RK3506) { + if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) { + data = 0x3 << (bit + 16); + rmask = data | (data >> 16); + data |= ((enable ? 0x3 : 0) << bit); + } + } + return regmap_update_bits(regmap, reg, rmask, data); } @@ -3227,6 +3588,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, case RK3328: case RK3368: case RK3399: + case RK3506: case RK3528: case RK3562: case RK3568: @@ -3880,13 +4242,10 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) } /* try to find the optional reference to the pmu syscon */ - node = of_parse_phandle(np, "rockchip,pmu", 0); - if (node) { - info->regmap_pmu = syscon_node_to_regmap(node); - of_node_put(node); - if (IS_ERR(info->regmap_pmu)) - return PTR_ERR(info->regmap_pmu); - } + info->regmap_pmu = syscon_regmap_lookup_by_phandle_optional(np, "rockchip,pmu"); + + /* try to find the optional reference to the ioc1 syscon */ + info->regmap_ioc1 = syscon_regmap_lookup_by_phandle_optional(np, "rockchip,ioc1"); ret = rockchip_pinctrl_register(pdev, info); if (ret) @@ -4350,6 +4709,71 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = { .drv_calc_reg = rk3399_calc_drv_reg_and_bit, }; +static struct rockchip_pin_bank rk3506_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS_PULL_FLAGS(0, 32, "gpio0", + IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, + IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, + IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, + IOMUX_WIDTH_2BIT | IOMUX_SOURCE_PMU, + 0x0, 0x8, 0x10, 0x830, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_2_BIT, + 0, 0, 0, 1), + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(1, 32, "gpio1", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x20, 0x28, 0x30, 0x38, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT), + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(2, 32, "gpio2", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x40, 0x48, 0x50, 0x58, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT), + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(3, 32, "gpio3", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x60, 0x68, 0x70, 0x78, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT), + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS_PULL_FLAGS(4, 32, "gpio4", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x80, 0x88, 0x90, 0x98, + DRV_TYPE_IO_LEVEL_2_BIT, + DRV_TYPE_IO_LEVEL_2_BIT, + DRV_TYPE_IO_LEVEL_2_BIT, + DRV_TYPE_IO_LEVEL_2_BIT, + 1, 1, 1, 1), +}; + +static struct rockchip_pin_ctrl rk3506_pin_ctrl __maybe_unused = { + .pin_banks = rk3506_pin_banks, + .nr_banks = ARRAY_SIZE(rk3506_pin_banks), + .label = "RK3506-GPIO", + .type = RK3506, + .pull_calc_reg = rk3506_calc_pull_reg_and_bit, + .drv_calc_reg = rk3506_calc_drv_reg_and_bit, + .schmitt_calc_reg = rk3506_calc_schmitt_reg_and_bit, +}; + static struct rockchip_pin_bank rk3528_pin_banks[] = { PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0", IOMUX_WIDTH_4BIT, @@ -4560,6 +4984,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = { .data = &rk3368_pin_ctrl }, { .compatible = "rockchip,rk3399-pinctrl", .data = &rk3399_pin_ctrl }, + { .compatible = "rockchip,rk3506-pinctrl", + .data = &rk3506_pin_ctrl }, { .compatible = "rockchip,rk3528-pinctrl", .data = &rk3528_pin_ctrl }, { .compatible = "rockchip,rk3562-pinctrl", diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h index 35cd38079d1e..4f4aff42a80a 100644 --- a/drivers/pinctrl/pinctrl-rockchip.h +++ b/drivers/pinctrl/pinctrl-rockchip.h @@ -196,6 +196,7 @@ enum rockchip_pinctrl_type { RK3328, RK3368, RK3399, + RK3506, RK3528, RK3562, RK3568, @@ -260,6 +261,8 @@ enum rockchip_pin_drv_type { DRV_TYPE_IO_1V8_ONLY, DRV_TYPE_IO_1V8_3V0_AUTO, DRV_TYPE_IO_3V3_ONLY, + DRV_TYPE_IO_LEVEL_2_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, DRV_TYPE_MAX }; @@ -458,6 +461,7 @@ struct rockchip_pinctrl { int reg_size; struct regmap *regmap_pull; struct regmap *regmap_pmu; + struct regmap *regmap_ioc1; struct device *dev; struct rockchip_pin_ctrl *ctrl; struct pinctrl_desc pctl; From 7959deaabea8380a318fefe9f3fffc37e5b0fc15 Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Wed, 5 Nov 2025 11:50:22 +0100 Subject: [PATCH 083/107] pinctrl: stm32: handle semaphore acquisition when handling pinctrl/pinmux When a GPIO RIF configuration is in semaphore mode, and the semaphore hasn't been taken before configuring the GPIO, the write operations silently fail. To avoid a silent fail when applying a pinctrl, if the pins that are being configured are in semaphore mode, take the semaphore. Note that there is no proper release of the RIF semaphore yet for pinctrl. Signed-off-by: Gatien Chevallier Signed-off-by: Linus Walleij --- drivers/pinctrl/stm32/pinctrl-stm32.c | 35 +++++++++++++++++++++------ 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index ceb9e19f2290..6a99708a5a23 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -362,11 +362,9 @@ static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset) return -EINVAL; } - if (bank->rif_control) { - if (!stm32_gpio_rif_acquire_semaphore(bank, offset)) { - dev_err(pctl->dev, "pin %d not available.\n", pin); - return -EINVAL; - } + if (bank->rif_control && !stm32_gpio_rif_acquire_semaphore(bank, offset)) { + dev_err(pctl->dev, "pin %d not available.\n", offset); + return -EACCES; } return pinctrl_gpio_request(chip, offset); @@ -1040,7 +1038,9 @@ static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, static int stm32_pmx_request(struct pinctrl_dev *pctldev, unsigned int gpio) { struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + unsigned int offset = stm32_gpio_pin(gpio); struct pinctrl_gpio_range *range; + struct stm32_gpio_bank *bank; range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, gpio); if (!range) { @@ -1048,11 +1048,20 @@ static int stm32_pmx_request(struct pinctrl_dev *pctldev, unsigned int gpio) return -EINVAL; } - if (!gpiochip_line_is_valid(range->gc, stm32_gpio_pin(gpio))) { + if (!gpiochip_line_is_valid(range->gc, offset)) { dev_warn(pctl->dev, "Can't access gpio %d\n", gpio); return -EACCES; } + bank = gpiochip_get_data(range->gc); + if (!bank) + return -ENODEV; + + if (bank->rif_control && !stm32_gpio_rif_acquire_semaphore(bank, offset)) { + dev_err(pctl->dev, "pin %d not available.\n", offset); + return -EACCES; + } + return 0; } @@ -1394,6 +1403,11 @@ static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev, return -EACCES; } + if (bank->rif_control && !stm32_gpio_rif_acquire_semaphore(bank, offset)) { + dev_err(pctl->dev, "pin %d not available.\n", offset); + return -EACCES; + } + switch (param) { case PIN_CONFIG_DRIVE_PUSH_PULL: ret = stm32_pconf_set_driving(bank, offset, 0); @@ -2014,16 +2028,21 @@ static int __maybe_unused stm32_pinctrl_restore_gpio_regs( if (!range) return 0; + bank = gpiochip_get_data(range->gc); + if (!gpiochip_line_is_valid(range->gc, offset)) return 0; + if (bank->rif_control && !stm32_gpio_rif_acquire_semaphore(bank, offset)) { + dev_err(pctl->dev, "pin %d not available.\n", offset); + return -EACCES; + } + pin_is_irq = gpiochip_line_is_irq(range->gc, offset); if (!desc || (!pin_is_irq && !desc->gpio_owner)) return 0; - bank = gpiochip_get_data(range->gc); - mode = bank->pin_backup[offset].mode; ret = stm32_pmx_set_mode(bank, offset, mode, bank->pin_backup[offset].alt); if (ret) From 9322da935c9a2db2b81a9660f650e48423ebf34d Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Mon, 27 Oct 2025 14:28:11 +0100 Subject: [PATCH 084/107] dt-bindings: pinctrl: mt7988: allow gpio-hogs Allow gpio-hogs in pinctrl node for switching pcie on Bananapi R4 Pro. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/mediatek,mt7988-pinctrl.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7988-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7988-pinctrl.yaml index 26dfe7e7735a..1f31b520cb43 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7988-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7988-pinctrl.yaml @@ -61,6 +61,11 @@ required: - "#gpio-cells" patternProperties: + "-hog(-[0-9]+)?$": + type: object + required: + - gpio-hog + '-pins$': type: object additionalProperties: false From 4043b0c45f8555a079bdac69a19ed08695a47a7b Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Fri, 7 Nov 2025 00:57:04 +0100 Subject: [PATCH 085/107] pinctrl: airoha: generalize pins/group/function/confs handling In preparation for support of Airoha AN7583, generalize pins/group/function/confs handling and move them in match_data. Inner function will base the values on the pinctrl priv struct instead of relying on hardcoded struct. This permits to use different PIN data while keeping the same logic. Signed-off-by: Christian Marangi Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-airoha.c | 565 ++++++++++++---------- 1 file changed, 317 insertions(+), 248 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c index f1cf2578fe42..32e5c1b32d50 100644 --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c @@ -30,15 +30,15 @@ #include "../pinconf.h" #include "../pinmux.h" -#define PINCTRL_PIN_GROUP(id) \ - PINCTRL_PINGROUP(#id, id##_pins, ARRAY_SIZE(id##_pins)) +#define PINCTRL_PIN_GROUP(id, table) \ + PINCTRL_PINGROUP(id, table##_pins, ARRAY_SIZE(table##_pins)) -#define PINCTRL_FUNC_DESC(id) \ +#define PINCTRL_FUNC_DESC(id, table) \ { \ - .desc = PINCTRL_PINFUNCTION(#id, id##_groups, \ - ARRAY_SIZE(id##_groups)), \ - .groups = id##_func_group, \ - .group_size = ARRAY_SIZE(id##_func_group), \ + .desc = PINCTRL_PINFUNCTION(#id, table##_groups, \ + ARRAY_SIZE(table##_groups)),\ + .groups = table##_func_group, \ + .group_size = ARRAY_SIZE(table##_func_group), \ } #define PINCTRL_CONF_DESC(p, offset, mask) \ @@ -357,16 +357,46 @@ struct airoha_pinctrl_gpiochip { u32 irq_type[AIROHA_NUM_PINS]; }; +struct airoha_pinctrl_confs_info { + const struct airoha_pinctrl_conf *confs; + unsigned int num_confs; +}; + +enum airoha_pinctrl_confs_type { + AIROHA_PINCTRL_CONFS_PULLUP, + AIROHA_PINCTRL_CONFS_PULLDOWN, + AIROHA_PINCTRL_CONFS_DRIVE_E2, + AIROHA_PINCTRL_CONFS_DRIVE_E4, + AIROHA_PINCTRL_CONFS_PCIE_RST_OD, + + AIROHA_PINCTRL_CONFS_MAX, +}; + struct airoha_pinctrl { struct pinctrl_dev *ctrl; + struct pinctrl_desc desc; + const struct pingroup *grps; + const struct airoha_pinctrl_func *funcs; + const struct airoha_pinctrl_confs_info *confs_info; + struct regmap *chip_scu; struct regmap *regmap; struct airoha_pinctrl_gpiochip gpiochip; }; -static struct pinctrl_pin_desc airoha_pinctrl_pins[] = { +struct airoha_pinctrl_match_data { + const struct pinctrl_pin_desc *pins; + const unsigned int num_pins; + const struct pingroup *grps; + const unsigned int num_grps; + const struct airoha_pinctrl_func *funcs; + const unsigned int num_funcs; + const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX]; +}; + +static struct pinctrl_pin_desc en7581_pinctrl_pins[] = { PINCTRL_PIN(0, "uart1_txd"), PINCTRL_PIN(1, "uart1_rxd"), PINCTRL_PIN(2, "i2c_scl"), @@ -427,172 +457,172 @@ static struct pinctrl_pin_desc airoha_pinctrl_pins[] = { PINCTRL_PIN(63, "pcie_reset2"), }; -static const int pon_pins[] = { 49, 50, 51, 52, 53, 54 }; -static const int pon_tod_1pps_pins[] = { 46 }; -static const int gsw_tod_1pps_pins[] = { 46 }; -static const int sipo_pins[] = { 16, 17 }; -static const int sipo_rclk_pins[] = { 16, 17, 43 }; -static const int mdio_pins[] = { 14, 15 }; -static const int uart2_pins[] = { 48, 55 }; -static const int uart2_cts_rts_pins[] = { 46, 47 }; -static const int hsuart_pins[] = { 28, 29 }; -static const int hsuart_cts_rts_pins[] = { 26, 27 }; -static const int uart4_pins[] = { 38, 39 }; -static const int uart5_pins[] = { 18, 19 }; -static const int i2c0_pins[] = { 2, 3 }; -static const int i2c1_pins[] = { 14, 15 }; -static const int jtag_udi_pins[] = { 16, 17, 18, 19, 20 }; -static const int jtag_dfd_pins[] = { 16, 17, 18, 19, 20 }; -static const int i2s_pins[] = { 26, 27, 28, 29 }; -static const int pcm1_pins[] = { 22, 23, 24, 25 }; -static const int pcm2_pins[] = { 18, 19, 20, 21 }; -static const int spi_quad_pins[] = { 32, 33 }; -static const int spi_pins[] = { 4, 5, 6, 7 }; -static const int spi_cs1_pins[] = { 34 }; -static const int pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 }; -static const int pcm_spi_int_pins[] = { 14 }; -static const int pcm_spi_rst_pins[] = { 15 }; -static const int pcm_spi_cs1_pins[] = { 43 }; -static const int pcm_spi_cs2_pins[] = { 40 }; -static const int pcm_spi_cs2_p128_pins[] = { 40 }; -static const int pcm_spi_cs2_p156_pins[] = { 40 }; -static const int pcm_spi_cs3_pins[] = { 41 }; -static const int pcm_spi_cs4_pins[] = { 42 }; -static const int emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 }; -static const int pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 }; -static const int gpio0_pins[] = { 13 }; -static const int gpio1_pins[] = { 14 }; -static const int gpio2_pins[] = { 15 }; -static const int gpio3_pins[] = { 16 }; -static const int gpio4_pins[] = { 17 }; -static const int gpio5_pins[] = { 18 }; -static const int gpio6_pins[] = { 19 }; -static const int gpio7_pins[] = { 20 }; -static const int gpio8_pins[] = { 21 }; -static const int gpio9_pins[] = { 22 }; -static const int gpio10_pins[] = { 23 }; -static const int gpio11_pins[] = { 24 }; -static const int gpio12_pins[] = { 25 }; -static const int gpio13_pins[] = { 26 }; -static const int gpio14_pins[] = { 27 }; -static const int gpio15_pins[] = { 28 }; -static const int gpio16_pins[] = { 29 }; -static const int gpio17_pins[] = { 30 }; -static const int gpio18_pins[] = { 31 }; -static const int gpio19_pins[] = { 32 }; -static const int gpio20_pins[] = { 33 }; -static const int gpio21_pins[] = { 34 }; -static const int gpio22_pins[] = { 35 }; -static const int gpio23_pins[] = { 36 }; -static const int gpio24_pins[] = { 37 }; -static const int gpio25_pins[] = { 38 }; -static const int gpio26_pins[] = { 39 }; -static const int gpio27_pins[] = { 40 }; -static const int gpio28_pins[] = { 41 }; -static const int gpio29_pins[] = { 42 }; -static const int gpio30_pins[] = { 43 }; -static const int gpio31_pins[] = { 44 }; -static const int gpio33_pins[] = { 46 }; -static const int gpio34_pins[] = { 47 }; -static const int gpio35_pins[] = { 48 }; -static const int gpio36_pins[] = { 49 }; -static const int gpio37_pins[] = { 50 }; -static const int gpio38_pins[] = { 51 }; -static const int gpio39_pins[] = { 52 }; -static const int gpio40_pins[] = { 53 }; -static const int gpio41_pins[] = { 54 }; -static const int gpio42_pins[] = { 55 }; -static const int gpio43_pins[] = { 56 }; -static const int gpio44_pins[] = { 57 }; -static const int gpio45_pins[] = { 58 }; -static const int gpio46_pins[] = { 59 }; -static const int pcie_reset0_pins[] = { 61 }; -static const int pcie_reset1_pins[] = { 62 }; -static const int pcie_reset2_pins[] = { 63 }; +static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 }; +static const int en7581_pon_tod_1pps_pins[] = { 46 }; +static const int en7581_gsw_tod_1pps_pins[] = { 46 }; +static const int en7581_sipo_pins[] = { 16, 17 }; +static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 }; +static const int en7581_mdio_pins[] = { 14, 15 }; +static const int en7581_uart2_pins[] = { 48, 55 }; +static const int en7581_uart2_cts_rts_pins[] = { 46, 47 }; +static const int en7581_hsuart_pins[] = { 28, 29 }; +static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 }; +static const int en7581_uart4_pins[] = { 38, 39 }; +static const int en7581_uart5_pins[] = { 18, 19 }; +static const int en7581_i2c0_pins[] = { 2, 3 }; +static const int en7581_i2c1_pins[] = { 14, 15 }; +static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 }; +static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 }; +static const int en7581_i2s_pins[] = { 26, 27, 28, 29 }; +static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 }; +static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 }; +static const int en7581_spi_quad_pins[] = { 32, 33 }; +static const int en7581_spi_pins[] = { 4, 5, 6, 7 }; +static const int en7581_spi_cs1_pins[] = { 34 }; +static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 }; +static const int en7581_pcm_spi_int_pins[] = { 14 }; +static const int en7581_pcm_spi_rst_pins[] = { 15 }; +static const int en7581_pcm_spi_cs1_pins[] = { 43 }; +static const int en7581_pcm_spi_cs2_pins[] = { 40 }; +static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 }; +static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 }; +static const int en7581_pcm_spi_cs3_pins[] = { 41 }; +static const int en7581_pcm_spi_cs4_pins[] = { 42 }; +static const int en7581_emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 }; +static const int en7581_pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 }; +static const int en7581_gpio0_pins[] = { 13 }; +static const int en7581_gpio1_pins[] = { 14 }; +static const int en7581_gpio2_pins[] = { 15 }; +static const int en7581_gpio3_pins[] = { 16 }; +static const int en7581_gpio4_pins[] = { 17 }; +static const int en7581_gpio5_pins[] = { 18 }; +static const int en7581_gpio6_pins[] = { 19 }; +static const int en7581_gpio7_pins[] = { 20 }; +static const int en7581_gpio8_pins[] = { 21 }; +static const int en7581_gpio9_pins[] = { 22 }; +static const int en7581_gpio10_pins[] = { 23 }; +static const int en7581_gpio11_pins[] = { 24 }; +static const int en7581_gpio12_pins[] = { 25 }; +static const int en7581_gpio13_pins[] = { 26 }; +static const int en7581_gpio14_pins[] = { 27 }; +static const int en7581_gpio15_pins[] = { 28 }; +static const int en7581_gpio16_pins[] = { 29 }; +static const int en7581_gpio17_pins[] = { 30 }; +static const int en7581_gpio18_pins[] = { 31 }; +static const int en7581_gpio19_pins[] = { 32 }; +static const int en7581_gpio20_pins[] = { 33 }; +static const int en7581_gpio21_pins[] = { 34 }; +static const int en7581_gpio22_pins[] = { 35 }; +static const int en7581_gpio23_pins[] = { 36 }; +static const int en7581_gpio24_pins[] = { 37 }; +static const int en7581_gpio25_pins[] = { 38 }; +static const int en7581_gpio26_pins[] = { 39 }; +static const int en7581_gpio27_pins[] = { 40 }; +static const int en7581_gpio28_pins[] = { 41 }; +static const int en7581_gpio29_pins[] = { 42 }; +static const int en7581_gpio30_pins[] = { 43 }; +static const int en7581_gpio31_pins[] = { 44 }; +static const int en7581_gpio33_pins[] = { 46 }; +static const int en7581_gpio34_pins[] = { 47 }; +static const int en7581_gpio35_pins[] = { 48 }; +static const int en7581_gpio36_pins[] = { 49 }; +static const int en7581_gpio37_pins[] = { 50 }; +static const int en7581_gpio38_pins[] = { 51 }; +static const int en7581_gpio39_pins[] = { 52 }; +static const int en7581_gpio40_pins[] = { 53 }; +static const int en7581_gpio41_pins[] = { 54 }; +static const int en7581_gpio42_pins[] = { 55 }; +static const int en7581_gpio43_pins[] = { 56 }; +static const int en7581_gpio44_pins[] = { 57 }; +static const int en7581_gpio45_pins[] = { 58 }; +static const int en7581_gpio46_pins[] = { 59 }; +static const int en7581_pcie_reset0_pins[] = { 61 }; +static const int en7581_pcie_reset1_pins[] = { 62 }; +static const int en7581_pcie_reset2_pins[] = { 63 }; -static const struct pingroup airoha_pinctrl_groups[] = { - PINCTRL_PIN_GROUP(pon), - PINCTRL_PIN_GROUP(pon_tod_1pps), - PINCTRL_PIN_GROUP(gsw_tod_1pps), - PINCTRL_PIN_GROUP(sipo), - PINCTRL_PIN_GROUP(sipo_rclk), - PINCTRL_PIN_GROUP(mdio), - PINCTRL_PIN_GROUP(uart2), - PINCTRL_PIN_GROUP(uart2_cts_rts), - PINCTRL_PIN_GROUP(hsuart), - PINCTRL_PIN_GROUP(hsuart_cts_rts), - PINCTRL_PIN_GROUP(uart4), - PINCTRL_PIN_GROUP(uart5), - PINCTRL_PIN_GROUP(i2c0), - PINCTRL_PIN_GROUP(i2c1), - PINCTRL_PIN_GROUP(jtag_udi), - PINCTRL_PIN_GROUP(jtag_dfd), - PINCTRL_PIN_GROUP(i2s), - PINCTRL_PIN_GROUP(pcm1), - PINCTRL_PIN_GROUP(pcm2), - PINCTRL_PIN_GROUP(spi), - PINCTRL_PIN_GROUP(spi_quad), - PINCTRL_PIN_GROUP(spi_cs1), - PINCTRL_PIN_GROUP(pcm_spi), - PINCTRL_PIN_GROUP(pcm_spi_int), - PINCTRL_PIN_GROUP(pcm_spi_rst), - PINCTRL_PIN_GROUP(pcm_spi_cs1), - PINCTRL_PIN_GROUP(pcm_spi_cs2_p128), - PINCTRL_PIN_GROUP(pcm_spi_cs2_p156), - PINCTRL_PIN_GROUP(pcm_spi_cs2), - PINCTRL_PIN_GROUP(pcm_spi_cs3), - PINCTRL_PIN_GROUP(pcm_spi_cs4), - PINCTRL_PIN_GROUP(emmc), - PINCTRL_PIN_GROUP(pnand), - PINCTRL_PIN_GROUP(gpio0), - PINCTRL_PIN_GROUP(gpio1), - PINCTRL_PIN_GROUP(gpio2), - PINCTRL_PIN_GROUP(gpio3), - PINCTRL_PIN_GROUP(gpio4), - PINCTRL_PIN_GROUP(gpio5), - PINCTRL_PIN_GROUP(gpio6), - PINCTRL_PIN_GROUP(gpio7), - PINCTRL_PIN_GROUP(gpio8), - PINCTRL_PIN_GROUP(gpio9), - PINCTRL_PIN_GROUP(gpio10), - PINCTRL_PIN_GROUP(gpio11), - PINCTRL_PIN_GROUP(gpio12), - PINCTRL_PIN_GROUP(gpio13), - PINCTRL_PIN_GROUP(gpio14), - PINCTRL_PIN_GROUP(gpio15), - PINCTRL_PIN_GROUP(gpio16), - PINCTRL_PIN_GROUP(gpio17), - PINCTRL_PIN_GROUP(gpio18), - PINCTRL_PIN_GROUP(gpio19), - PINCTRL_PIN_GROUP(gpio20), - PINCTRL_PIN_GROUP(gpio21), - PINCTRL_PIN_GROUP(gpio22), - PINCTRL_PIN_GROUP(gpio23), - PINCTRL_PIN_GROUP(gpio24), - PINCTRL_PIN_GROUP(gpio25), - PINCTRL_PIN_GROUP(gpio26), - PINCTRL_PIN_GROUP(gpio27), - PINCTRL_PIN_GROUP(gpio28), - PINCTRL_PIN_GROUP(gpio29), - PINCTRL_PIN_GROUP(gpio30), - PINCTRL_PIN_GROUP(gpio31), - PINCTRL_PIN_GROUP(gpio33), - PINCTRL_PIN_GROUP(gpio34), - PINCTRL_PIN_GROUP(gpio35), - PINCTRL_PIN_GROUP(gpio36), - PINCTRL_PIN_GROUP(gpio37), - PINCTRL_PIN_GROUP(gpio38), - PINCTRL_PIN_GROUP(gpio39), - PINCTRL_PIN_GROUP(gpio40), - PINCTRL_PIN_GROUP(gpio41), - PINCTRL_PIN_GROUP(gpio42), - PINCTRL_PIN_GROUP(gpio43), - PINCTRL_PIN_GROUP(gpio44), - PINCTRL_PIN_GROUP(gpio45), - PINCTRL_PIN_GROUP(gpio46), - PINCTRL_PIN_GROUP(pcie_reset0), - PINCTRL_PIN_GROUP(pcie_reset1), - PINCTRL_PIN_GROUP(pcie_reset2), +static const struct pingroup en7581_pinctrl_groups[] = { + PINCTRL_PIN_GROUP("pon", en7581_pon), + PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps), + PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps), + PINCTRL_PIN_GROUP("sipo", en7581_sipo), + PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk), + PINCTRL_PIN_GROUP("mdio", en7581_mdio), + PINCTRL_PIN_GROUP("uart2", en7581_uart2), + PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts), + PINCTRL_PIN_GROUP("hsuart", en7581_hsuart), + PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts), + PINCTRL_PIN_GROUP("uart4", en7581_uart4), + PINCTRL_PIN_GROUP("uart5", en7581_uart5), + PINCTRL_PIN_GROUP("i2c0", en7581_i2c0), + PINCTRL_PIN_GROUP("i2c1", en7581_i2c1), + PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi), + PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd), + PINCTRL_PIN_GROUP("i2s", en7581_i2s), + PINCTRL_PIN_GROUP("pcm1", en7581_pcm1), + PINCTRL_PIN_GROUP("pcm2", en7581_pcm2), + PINCTRL_PIN_GROUP("spi", en7581_spi), + PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad), + PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1), + PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi), + PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int), + PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst), + PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1), + PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128), + PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156), + PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2), + PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3), + PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4), + PINCTRL_PIN_GROUP("emmc", en7581_emmc), + PINCTRL_PIN_GROUP("pnand", en7581_pnand), + PINCTRL_PIN_GROUP("gpio0", en7581_gpio0), + PINCTRL_PIN_GROUP("gpio1", en7581_gpio1), + PINCTRL_PIN_GROUP("gpio2", en7581_gpio2), + PINCTRL_PIN_GROUP("gpio3", en7581_gpio3), + PINCTRL_PIN_GROUP("gpio4", en7581_gpio4), + PINCTRL_PIN_GROUP("gpio5", en7581_gpio5), + PINCTRL_PIN_GROUP("gpio6", en7581_gpio6), + PINCTRL_PIN_GROUP("gpio7", en7581_gpio7), + PINCTRL_PIN_GROUP("gpio8", en7581_gpio8), + PINCTRL_PIN_GROUP("gpio9", en7581_gpio9), + PINCTRL_PIN_GROUP("gpio10", en7581_gpio10), + PINCTRL_PIN_GROUP("gpio11", en7581_gpio11), + PINCTRL_PIN_GROUP("gpio12", en7581_gpio12), + PINCTRL_PIN_GROUP("gpio13", en7581_gpio13), + PINCTRL_PIN_GROUP("gpio14", en7581_gpio14), + PINCTRL_PIN_GROUP("gpio15", en7581_gpio15), + PINCTRL_PIN_GROUP("gpio16", en7581_gpio16), + PINCTRL_PIN_GROUP("gpio17", en7581_gpio17), + PINCTRL_PIN_GROUP("gpio18", en7581_gpio18), + PINCTRL_PIN_GROUP("gpio19", en7581_gpio19), + PINCTRL_PIN_GROUP("gpio20", en7581_gpio20), + PINCTRL_PIN_GROUP("gpio21", en7581_gpio21), + PINCTRL_PIN_GROUP("gpio22", en7581_gpio22), + PINCTRL_PIN_GROUP("gpio23", en7581_gpio23), + PINCTRL_PIN_GROUP("gpio24", en7581_gpio24), + PINCTRL_PIN_GROUP("gpio25", en7581_gpio25), + PINCTRL_PIN_GROUP("gpio26", en7581_gpio26), + PINCTRL_PIN_GROUP("gpio27", en7581_gpio27), + PINCTRL_PIN_GROUP("gpio28", en7581_gpio28), + PINCTRL_PIN_GROUP("gpio29", en7581_gpio29), + PINCTRL_PIN_GROUP("gpio30", en7581_gpio30), + PINCTRL_PIN_GROUP("gpio31", en7581_gpio31), + PINCTRL_PIN_GROUP("gpio33", en7581_gpio33), + PINCTRL_PIN_GROUP("gpio34", en7581_gpio34), + PINCTRL_PIN_GROUP("gpio35", en7581_gpio35), + PINCTRL_PIN_GROUP("gpio36", en7581_gpio36), + PINCTRL_PIN_GROUP("gpio37", en7581_gpio37), + PINCTRL_PIN_GROUP("gpio38", en7581_gpio38), + PINCTRL_PIN_GROUP("gpio39", en7581_gpio39), + PINCTRL_PIN_GROUP("gpio40", en7581_gpio40), + PINCTRL_PIN_GROUP("gpio41", en7581_gpio41), + PINCTRL_PIN_GROUP("gpio42", en7581_gpio42), + PINCTRL_PIN_GROUP("gpio43", en7581_gpio43), + PINCTRL_PIN_GROUP("gpio44", en7581_gpio44), + PINCTRL_PIN_GROUP("gpio45", en7581_gpio45), + PINCTRL_PIN_GROUP("gpio46", en7581_gpio46), + PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0), + PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1), + PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2), }; static const char *const pon_groups[] = { "pon" }; @@ -1955,33 +1985,33 @@ static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = { }, }; -static const struct airoha_pinctrl_func airoha_pinctrl_funcs[] = { - PINCTRL_FUNC_DESC(pon), - PINCTRL_FUNC_DESC(tod_1pps), - PINCTRL_FUNC_DESC(sipo), - PINCTRL_FUNC_DESC(mdio), - PINCTRL_FUNC_DESC(uart), - PINCTRL_FUNC_DESC(i2c), - PINCTRL_FUNC_DESC(jtag), - PINCTRL_FUNC_DESC(pcm), - PINCTRL_FUNC_DESC(spi), - PINCTRL_FUNC_DESC(pcm_spi), - PINCTRL_FUNC_DESC(i2s), - PINCTRL_FUNC_DESC(emmc), - PINCTRL_FUNC_DESC(pnand), - PINCTRL_FUNC_DESC(pcie_reset), - PINCTRL_FUNC_DESC(pwm), - PINCTRL_FUNC_DESC(phy1_led0), - PINCTRL_FUNC_DESC(phy2_led0), - PINCTRL_FUNC_DESC(phy3_led0), - PINCTRL_FUNC_DESC(phy4_led0), - PINCTRL_FUNC_DESC(phy1_led1), - PINCTRL_FUNC_DESC(phy2_led1), - PINCTRL_FUNC_DESC(phy3_led1), - PINCTRL_FUNC_DESC(phy4_led1), +static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = { + PINCTRL_FUNC_DESC("pon", pon), + PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), + PINCTRL_FUNC_DESC("sipo", sipo), + PINCTRL_FUNC_DESC("mdio", mdio), + PINCTRL_FUNC_DESC("uart", uart), + PINCTRL_FUNC_DESC("i2c", i2c), + PINCTRL_FUNC_DESC("jtag", jtag), + PINCTRL_FUNC_DESC("pcm", pcm), + PINCTRL_FUNC_DESC("spi", spi), + PINCTRL_FUNC_DESC("pcm_spi", pcm_spi), + PINCTRL_FUNC_DESC("i2s", i2s), + PINCTRL_FUNC_DESC("emmc", emmc), + PINCTRL_FUNC_DESC("pnand", pnand), + PINCTRL_FUNC_DESC("pcie_reset", pcie_reset), + PINCTRL_FUNC_DESC("pwm", pwm), + PINCTRL_FUNC_DESC("phy1_led0", phy1_led0), + PINCTRL_FUNC_DESC("phy2_led0", phy2_led0), + PINCTRL_FUNC_DESC("phy3_led0", phy3_led0), + PINCTRL_FUNC_DESC("phy4_led0", phy4_led0), + PINCTRL_FUNC_DESC("phy1_led1", phy1_led1), + PINCTRL_FUNC_DESC("phy2_led1", phy2_led1), + PINCTRL_FUNC_DESC("phy3_led1", phy3_led1), + PINCTRL_FUNC_DESC("phy4_led1", phy4_led1), }; -static const struct airoha_pinctrl_conf airoha_pinctrl_pullup_conf[] = { +static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = { PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), @@ -2042,7 +2072,7 @@ static const struct airoha_pinctrl_conf airoha_pinctrl_pullup_conf[] = { PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK), }; -static const struct airoha_pinctrl_conf airoha_pinctrl_pulldown_conf[] = { +static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = { PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), @@ -2103,7 +2133,7 @@ static const struct airoha_pinctrl_conf airoha_pinctrl_pulldown_conf[] = { PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK), }; -static const struct airoha_pinctrl_conf airoha_pinctrl_drive_e2_conf[] = { +static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = { PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), @@ -2164,7 +2194,7 @@ static const struct airoha_pinctrl_conf airoha_pinctrl_drive_e2_conf[] = { PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK), }; -static const struct airoha_pinctrl_conf airoha_pinctrl_drive_e4_conf[] = { +static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = { PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), @@ -2225,7 +2255,7 @@ static const struct airoha_pinctrl_conf airoha_pinctrl_drive_e4_conf[] = { PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK), }; -static const struct airoha_pinctrl_conf airoha_pinctrl_pcie_rst_od_conf[] = { +static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = { PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), PINCTRL_CONF_DESC(63, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK), @@ -2546,12 +2576,17 @@ airoha_pinctrl_get_conf_reg(const struct airoha_pinctrl_conf *conf, } static int airoha_pinctrl_get_conf(struct airoha_pinctrl *pinctrl, - const struct airoha_pinctrl_conf *conf, - int conf_size, int pin, u32 *val) + enum airoha_pinctrl_confs_type conf_type, + int pin, u32 *val) { + const struct airoha_pinctrl_confs_info *confs_info; const struct airoha_pinctrl_reg *reg; - reg = airoha_pinctrl_get_conf_reg(conf, conf_size, pin); + confs_info = &pinctrl->confs_info[conf_type]; + + reg = airoha_pinctrl_get_conf_reg(confs_info->confs, + confs_info->num_confs, + pin); if (!reg) return -EINVAL; @@ -2564,12 +2599,17 @@ static int airoha_pinctrl_get_conf(struct airoha_pinctrl *pinctrl, } static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl, - const struct airoha_pinctrl_conf *conf, - int conf_size, int pin, u32 val) + enum airoha_pinctrl_confs_type conf_type, + int pin, u32 val) { + const struct airoha_pinctrl_confs_info *confs_info; const struct airoha_pinctrl_reg *reg = NULL; - reg = airoha_pinctrl_get_conf_reg(conf, conf_size, pin); + confs_info = &pinctrl->confs_info[conf_type]; + + reg = airoha_pinctrl_get_conf_reg(confs_info->confs, + confs_info->num_confs, + pin); if (!reg) return -EINVAL; @@ -2582,44 +2622,34 @@ static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl, } #define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val) \ - airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pullup_conf, \ - ARRAY_SIZE(airoha_pinctrl_pullup_conf), \ + airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \ (pin), (val)) #define airoha_pinctrl_get_pulldown_conf(pinctrl, pin, val) \ - airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pulldown_conf, \ - ARRAY_SIZE(airoha_pinctrl_pulldown_conf), \ + airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \ (pin), (val)) #define airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, val) \ - airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_drive_e2_conf, \ - ARRAY_SIZE(airoha_pinctrl_drive_e2_conf), \ + airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \ (pin), (val)) #define airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, val) \ - airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_drive_e4_conf, \ - ARRAY_SIZE(airoha_pinctrl_drive_e4_conf), \ + airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \ (pin), (val)) #define airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, val) \ - airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pcie_rst_od_conf, \ - ARRAY_SIZE(airoha_pinctrl_pcie_rst_od_conf), \ + airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \ (pin), (val)) #define airoha_pinctrl_set_pullup_conf(pinctrl, pin, val) \ - airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pullup_conf, \ - ARRAY_SIZE(airoha_pinctrl_pullup_conf), \ + airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \ (pin), (val)) #define airoha_pinctrl_set_pulldown_conf(pinctrl, pin, val) \ - airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pulldown_conf, \ - ARRAY_SIZE(airoha_pinctrl_pulldown_conf), \ + airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \ (pin), (val)) #define airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, val) \ - airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_drive_e2_conf, \ - ARRAY_SIZE(airoha_pinctrl_drive_e2_conf), \ + airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \ (pin), (val)) #define airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, val) \ - airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_drive_e4_conf, \ - ARRAY_SIZE(airoha_pinctrl_drive_e4_conf), \ + airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \ (pin), (val)) #define airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, val) \ - airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pcie_rst_od_conf, \ - ARRAY_SIZE(airoha_pinctrl_pcie_rst_od_conf), \ + airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \ (pin), (val)) static int airoha_pinconf_get_direction(struct pinctrl_dev *pctrl_dev, u32 p) @@ -2796,12 +2826,13 @@ static int airoha_pinconf_set(struct pinctrl_dev *pctrl_dev, static int airoha_pinconf_group_get(struct pinctrl_dev *pctrl_dev, unsigned int group, unsigned long *config) { + struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); u32 cur_config = 0; int i; - for (i = 0; i < airoha_pinctrl_groups[group].npins; i++) { + for (i = 0; i < pinctrl->grps[group].npins; i++) { if (airoha_pinconf_get(pctrl_dev, - airoha_pinctrl_groups[group].pins[i], + pinctrl->grps[group].pins[i], config)) return -ENOTSUPP; @@ -2818,13 +2849,14 @@ static int airoha_pinconf_group_set(struct pinctrl_dev *pctrl_dev, unsigned int group, unsigned long *configs, unsigned int num_configs) { + struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); int i; - for (i = 0; i < airoha_pinctrl_groups[group].npins; i++) { + for (i = 0; i < pinctrl->grps[group].npins; i++) { int err; err = airoha_pinconf_set(pctrl_dev, - airoha_pinctrl_groups[group].pins[i], + pinctrl->grps[group].pins[i], configs, num_configs); if (err) return err; @@ -2850,23 +2882,16 @@ static const struct pinctrl_ops airoha_pctlops = { .dt_free_map = pinconf_generic_dt_free_map, }; -static const struct pinctrl_desc airoha_pinctrl_desc = { - .name = KBUILD_MODNAME, - .owner = THIS_MODULE, - .pctlops = &airoha_pctlops, - .pmxops = &airoha_pmxops, - .confops = &airoha_confops, - .pins = airoha_pinctrl_pins, - .npins = ARRAY_SIZE(airoha_pinctrl_pins), -}; - static int airoha_pinctrl_probe(struct platform_device *pdev) { + const struct airoha_pinctrl_match_data *data; struct device *dev = &pdev->dev; struct airoha_pinctrl *pinctrl; struct regmap *map; int err, i; + data = device_get_match_data(dev); + pinctrl = devm_kzalloc(dev, sizeof(*pinctrl), GFP_KERNEL); if (!pinctrl) return -ENOMEM; @@ -2881,14 +2906,23 @@ static int airoha_pinctrl_probe(struct platform_device *pdev) pinctrl->chip_scu = map; - err = devm_pinctrl_register_and_init(dev, &airoha_pinctrl_desc, + /* Init pinctrl desc struct */ + pinctrl->desc.name = KBUILD_MODNAME; + pinctrl->desc.owner = THIS_MODULE, + pinctrl->desc.pctlops = &airoha_pctlops, + pinctrl->desc.pmxops = &airoha_pmxops, + pinctrl->desc.confops = &airoha_confops, + pinctrl->desc.pins = data->pins, + pinctrl->desc.npins = data->num_pins, + + err = devm_pinctrl_register_and_init(dev, &pinctrl->desc, pinctrl, &pinctrl->ctrl); if (err) return err; /* build pin groups */ - for (i = 0; i < ARRAY_SIZE(airoha_pinctrl_groups); i++) { - const struct pingroup *grp = &airoha_pinctrl_groups[i]; + for (i = 0; i < data->num_grps; i++) { + const struct pingroup *grp = &data->grps[i]; err = pinctrl_generic_add_group(pinctrl->ctrl, grp->name, grp->pins, grp->npins, @@ -2901,10 +2935,10 @@ static int airoha_pinctrl_probe(struct platform_device *pdev) } /* build functions */ - for (i = 0; i < ARRAY_SIZE(airoha_pinctrl_funcs); i++) { + for (i = 0; i < data->num_funcs; i++) { const struct airoha_pinctrl_func *func; - func = &airoha_pinctrl_funcs[i]; + func = &data->funcs[i]; err = pinmux_generic_add_pinfunction(pinctrl->ctrl, &func->desc, (void *)func); @@ -2915,6 +2949,10 @@ static int airoha_pinctrl_probe(struct platform_device *pdev) } } + pinctrl->grps = data->grps; + pinctrl->funcs = data->funcs; + pinctrl->confs_info = data->confs_info; + err = pinctrl_enable(pinctrl->ctrl); if (err) return err; @@ -2923,8 +2961,39 @@ static int airoha_pinctrl_probe(struct platform_device *pdev) return airoha_pinctrl_add_gpiochip(pinctrl, pdev); } +static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = { + .pins = en7581_pinctrl_pins, + .num_pins = ARRAY_SIZE(en7581_pinctrl_pins), + .grps = en7581_pinctrl_groups, + .num_grps = ARRAY_SIZE(en7581_pinctrl_groups), + .funcs = en7581_pinctrl_funcs, + .num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs), + .confs_info = { + [AIROHA_PINCTRL_CONFS_PULLUP] = { + .confs = en7581_pinctrl_pullup_conf, + .num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf), + }, + [AIROHA_PINCTRL_CONFS_PULLDOWN] = { + .confs = en7581_pinctrl_pulldown_conf, + .num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E2] = { + .confs = en7581_pinctrl_drive_e2_conf, + .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E4] = { + .confs = en7581_pinctrl_drive_e4_conf, + .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf), + }, + [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = { + .confs = en7581_pinctrl_pcie_rst_od_conf, + .num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf), + }, + }, +}; + static const struct of_device_id airoha_pinctrl_of_match[] = { - { .compatible = "airoha,en7581-pinctrl" }, + { .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match); From 579839c9548cf2a85e873ad787bc2fa6610bf8ab Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Fri, 7 Nov 2025 00:57:05 +0100 Subject: [PATCH 086/107] pinctrl: airoha: convert PHY LED GPIO to macro PHY LED GPIO pinctrl struct definition is very similar across the different 4 PHY and 2 LED and it can be generelized to a macro. To reduce code size, convert them to a common macro. Signed-off-by: Christian Marangi Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-airoha.c | 588 ++++------------------ 1 file changed, 100 insertions(+), 488 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c index 32e5c1b32d50..cb0edc2a66a1 100644 --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c @@ -1473,516 +1473,128 @@ static const struct airoha_pinctrl_func_group pwm_func_group[] = { }, }; +#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_2ND_I2C_MODE, \ + (mux_val), \ + (mux_val), \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_LAN_LED0_MAPPING, \ + (map_mask), \ + (map_val), \ + }, \ + .regmap_size = 2, \ + } + +#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_2ND_I2C_MODE, \ + (mux_val), \ + (mux_val), \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_LAN_LED1_MAPPING, \ + (map_mask), \ + (map_val), \ + }, \ + .regmap_size = 2, \ + } + static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = { - { - .name = "gpio33", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN0_LED0_MODE_MASK, - GPIO_LAN0_LED0_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED0_MAPPING, - LAN0_LED_MAPPING_MASK, - LAN0_PHY_LED_MAP(0) - }, - .regmap_size = 2, - }, { - .name = "gpio34", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN1_LED0_MODE_MASK, - GPIO_LAN1_LED0_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED0_MAPPING, - LAN1_LED_MAPPING_MASK, - LAN1_PHY_LED_MAP(0) - }, - .regmap_size = 2, - }, { - .name = "gpio35", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN2_LED0_MODE_MASK, - GPIO_LAN2_LED0_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED0_MAPPING, - LAN2_LED_MAPPING_MASK, - LAN2_PHY_LED_MAP(0) - }, - .regmap_size = 2, - }, { - .name = "gpio42", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN3_LED0_MODE_MASK, - GPIO_LAN3_LED0_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED0_MAPPING, - LAN3_LED_MAPPING_MASK, - LAN3_PHY_LED_MAP(0) - }, - .regmap_size = 2, - }, + AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), }; static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = { - { - .name = "gpio33", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN0_LED0_MODE_MASK, - GPIO_LAN0_LED0_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED0_MAPPING, - LAN0_LED_MAPPING_MASK, - LAN0_PHY_LED_MAP(1) - }, - .regmap_size = 2, - }, { - .name = "gpio34", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN1_LED0_MODE_MASK, - GPIO_LAN1_LED0_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED0_MAPPING, - LAN1_LED_MAPPING_MASK, - LAN1_PHY_LED_MAP(1) - }, - .regmap_size = 2, - }, { - .name = "gpio35", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN2_LED0_MODE_MASK, - GPIO_LAN2_LED0_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED0_MAPPING, - LAN2_LED_MAPPING_MASK, - LAN2_PHY_LED_MAP(1) - }, - .regmap_size = 2, - }, { - .name = "gpio42", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN3_LED0_MODE_MASK, - GPIO_LAN3_LED0_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED0_MAPPING, - LAN3_LED_MAPPING_MASK, - LAN3_PHY_LED_MAP(1) - }, - .regmap_size = 2, - }, + AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), }; static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = { - { - .name = "gpio33", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN0_LED0_MODE_MASK, - GPIO_LAN0_LED0_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED0_MAPPING, - LAN0_LED_MAPPING_MASK, - LAN0_PHY_LED_MAP(2) - }, - .regmap_size = 2, - }, { - .name = "gpio34", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN1_LED0_MODE_MASK, - GPIO_LAN1_LED0_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED0_MAPPING, - LAN1_LED_MAPPING_MASK, - LAN1_PHY_LED_MAP(2) - }, - .regmap_size = 2, - }, { - .name = "gpio35", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN2_LED0_MODE_MASK, - GPIO_LAN2_LED0_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED0_MAPPING, - LAN2_LED_MAPPING_MASK, - LAN2_PHY_LED_MAP(2) - }, - .regmap_size = 2, - }, { - .name = "gpio42", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN3_LED0_MODE_MASK, - GPIO_LAN3_LED0_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED0_MAPPING, - LAN3_LED_MAPPING_MASK, - LAN3_PHY_LED_MAP(2) - }, - .regmap_size = 2, - }, + AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), }; static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = { - { - .name = "gpio33", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN0_LED0_MODE_MASK, - GPIO_LAN0_LED0_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED0_MAPPING, - LAN0_LED_MAPPING_MASK, - LAN0_PHY_LED_MAP(3) - }, - .regmap_size = 2, - }, { - .name = "gpio34", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN1_LED0_MODE_MASK, - GPIO_LAN1_LED0_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED0_MAPPING, - LAN1_LED_MAPPING_MASK, - LAN1_PHY_LED_MAP(3) - }, - .regmap_size = 2, - }, { - .name = "gpio35", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN2_LED0_MODE_MASK, - GPIO_LAN2_LED0_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED0_MAPPING, - LAN2_LED_MAPPING_MASK, - LAN2_PHY_LED_MAP(3) - }, - .regmap_size = 2, - }, { - .name = "gpio42", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN3_LED0_MODE_MASK, - GPIO_LAN3_LED0_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED0_MAPPING, - LAN3_LED_MAPPING_MASK, - LAN3_PHY_LED_MAP(3) - }, - .regmap_size = 2, - }, + AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), }; static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = { - { - .name = "gpio43", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN0_LED1_MODE_MASK, - GPIO_LAN0_LED1_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED1_MAPPING, - LAN0_LED_MAPPING_MASK, - LAN0_PHY_LED_MAP(0) - }, - .regmap_size = 2, - }, { - .name = "gpio44", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN1_LED1_MODE_MASK, - GPIO_LAN1_LED1_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED1_MAPPING, - LAN1_LED_MAPPING_MASK, - LAN1_PHY_LED_MAP(0) - }, - .regmap_size = 2, - }, { - .name = "gpio45", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN2_LED1_MODE_MASK, - GPIO_LAN2_LED1_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED1_MAPPING, - LAN2_LED_MAPPING_MASK, - LAN2_PHY_LED_MAP(0) - }, - .regmap_size = 2, - }, { - .name = "gpio46", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN3_LED1_MODE_MASK, - GPIO_LAN3_LED1_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED1_MAPPING, - LAN3_LED_MAPPING_MASK, - LAN3_PHY_LED_MAP(0) - }, - .regmap_size = 2, - }, + AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), }; static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = { - { - .name = "gpio43", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN0_LED1_MODE_MASK, - GPIO_LAN0_LED1_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED1_MAPPING, - LAN0_LED_MAPPING_MASK, - LAN0_PHY_LED_MAP(1) - }, - .regmap_size = 2, - }, { - .name = "gpio44", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN1_LED1_MODE_MASK, - GPIO_LAN1_LED1_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED1_MAPPING, - LAN1_LED_MAPPING_MASK, - LAN1_PHY_LED_MAP(1) - }, - .regmap_size = 2, - }, { - .name = "gpio45", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN2_LED1_MODE_MASK, - GPIO_LAN2_LED1_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED1_MAPPING, - LAN2_LED_MAPPING_MASK, - LAN2_PHY_LED_MAP(1) - }, - .regmap_size = 2, - }, { - .name = "gpio46", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN3_LED1_MODE_MASK, - GPIO_LAN3_LED1_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED1_MAPPING, - LAN3_LED_MAPPING_MASK, - LAN3_PHY_LED_MAP(1) - }, - .regmap_size = 2, - }, + AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), }; static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = { - { - .name = "gpio43", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN0_LED1_MODE_MASK, - GPIO_LAN0_LED1_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED1_MAPPING, - LAN0_LED_MAPPING_MASK, - LAN0_PHY_LED_MAP(2) - }, - .regmap_size = 2, - }, { - .name = "gpio44", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN1_LED1_MODE_MASK, - GPIO_LAN1_LED1_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED1_MAPPING, - LAN1_LED_MAPPING_MASK, - LAN1_PHY_LED_MAP(2) - }, - .regmap_size = 2, - }, { - .name = "gpio45", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN2_LED1_MODE_MASK, - GPIO_LAN2_LED1_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED1_MAPPING, - LAN2_LED_MAPPING_MASK, - LAN2_PHY_LED_MAP(2) - }, - .regmap_size = 2, - }, { - .name = "gpio46", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN3_LED1_MODE_MASK, - GPIO_LAN3_LED1_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED1_MAPPING, - LAN3_LED_MAPPING_MASK, - LAN3_PHY_LED_MAP(2) - }, - .regmap_size = 2, - }, + AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), }; static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = { - { - .name = "gpio43", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN0_LED1_MODE_MASK, - GPIO_LAN0_LED1_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED1_MAPPING, - LAN0_LED_MAPPING_MASK, - LAN0_PHY_LED_MAP(3) - }, - .regmap_size = 2, - }, { - .name = "gpio44", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN1_LED1_MODE_MASK, - GPIO_LAN1_LED1_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED1_MAPPING, - LAN1_LED_MAPPING_MASK, - LAN1_PHY_LED_MAP(3) - }, - .regmap_size = 2, - }, { - .name = "gpio45", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN2_LED1_MODE_MASK, - GPIO_LAN2_LED1_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED1_MAPPING, - LAN2_LED_MAPPING_MASK, - LAN2_PHY_LED_MAP(3) - }, - .regmap_size = 2, - }, { - .name = "gpio46", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_LAN3_LED1_MODE_MASK, - GPIO_LAN3_LED1_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_LAN_LED1_MAPPING, - LAN3_LED_MAPPING_MASK, - LAN3_PHY_LED_MAP(3) - }, - .regmap_size = 2, - }, + AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), }; static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = { From 1552ad5d649cff9d170e5bc1d13ab1487333b4b7 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Fri, 7 Nov 2025 00:57:06 +0100 Subject: [PATCH 087/107] pinctrl: airoha: convert PWM GPIO to macro The PWM GPIO struct definition follow the same pattern for every GPIO pin hence it can be converted to a macro. Create 2 macro one for normal mux and one for ext mux and convert all the entry to these new macro to reduce code size. Signed-off-by: Christian Marangi Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-airoha.c | 465 ++++------------------ 1 file changed, 68 insertions(+), 397 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c index cb0edc2a66a1..f3cf48bdd1f8 100644 --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c @@ -1073,404 +1073,75 @@ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = { }; /* PWM */ +#define AIROHA_PINCTRL_PWM(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_MUX, \ + REG_GPIO_FLASH_MODE_CFG, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } \ + +#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } \ + static const struct airoha_pinctrl_func_group pwm_func_group[] = { - { - .name = "gpio0", - .regmap[0] = { - AIROHA_FUNC_PWM_MUX, - REG_GPIO_FLASH_MODE_CFG, - GPIO0_FLASH_MODE_CFG, - GPIO0_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio1", - .regmap[0] = { - AIROHA_FUNC_PWM_MUX, - REG_GPIO_FLASH_MODE_CFG, - GPIO1_FLASH_MODE_CFG, - GPIO1_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio2", - .regmap[0] = { - AIROHA_FUNC_PWM_MUX, - REG_GPIO_FLASH_MODE_CFG, - GPIO2_FLASH_MODE_CFG, - GPIO2_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio3", - .regmap[0] = { - AIROHA_FUNC_PWM_MUX, - REG_GPIO_FLASH_MODE_CFG, - GPIO3_FLASH_MODE_CFG, - GPIO3_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio4", - .regmap[0] = { - AIROHA_FUNC_PWM_MUX, - REG_GPIO_FLASH_MODE_CFG, - GPIO4_FLASH_MODE_CFG, - GPIO4_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio5", - .regmap[0] = { - AIROHA_FUNC_PWM_MUX, - REG_GPIO_FLASH_MODE_CFG, - GPIO5_FLASH_MODE_CFG, - GPIO5_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio6", - .regmap[0] = { - AIROHA_FUNC_PWM_MUX, - REG_GPIO_FLASH_MODE_CFG, - GPIO6_FLASH_MODE_CFG, - GPIO6_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio7", - .regmap[0] = { - AIROHA_FUNC_PWM_MUX, - REG_GPIO_FLASH_MODE_CFG, - GPIO7_FLASH_MODE_CFG, - GPIO7_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio8", - .regmap[0] = { - AIROHA_FUNC_PWM_MUX, - REG_GPIO_FLASH_MODE_CFG, - GPIO8_FLASH_MODE_CFG, - GPIO8_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio9", - .regmap[0] = { - AIROHA_FUNC_PWM_MUX, - REG_GPIO_FLASH_MODE_CFG, - GPIO9_FLASH_MODE_CFG, - GPIO9_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio10", - .regmap[0] = { - AIROHA_FUNC_PWM_MUX, - REG_GPIO_FLASH_MODE_CFG, - GPIO10_FLASH_MODE_CFG, - GPIO10_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio11", - .regmap[0] = { - AIROHA_FUNC_PWM_MUX, - REG_GPIO_FLASH_MODE_CFG, - GPIO11_FLASH_MODE_CFG, - GPIO11_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio12", - .regmap[0] = { - AIROHA_FUNC_PWM_MUX, - REG_GPIO_FLASH_MODE_CFG, - GPIO12_FLASH_MODE_CFG, - GPIO12_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio13", - .regmap[0] = { - AIROHA_FUNC_PWM_MUX, - REG_GPIO_FLASH_MODE_CFG, - GPIO13_FLASH_MODE_CFG, - GPIO13_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio14", - .regmap[0] = { - AIROHA_FUNC_PWM_MUX, - REG_GPIO_FLASH_MODE_CFG, - GPIO14_FLASH_MODE_CFG, - GPIO14_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio15", - .regmap[0] = { - AIROHA_FUNC_PWM_MUX, - REG_GPIO_FLASH_MODE_CFG, - GPIO15_FLASH_MODE_CFG, - GPIO15_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio16", - .regmap[0] = { - AIROHA_FUNC_PWM_EXT_MUX, - REG_GPIO_FLASH_MODE_CFG_EXT, - GPIO16_FLASH_MODE_CFG, - GPIO16_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio17", - .regmap[0] = { - AIROHA_FUNC_PWM_EXT_MUX, - REG_GPIO_FLASH_MODE_CFG_EXT, - GPIO17_FLASH_MODE_CFG, - GPIO17_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio18", - .regmap[0] = { - AIROHA_FUNC_PWM_EXT_MUX, - REG_GPIO_FLASH_MODE_CFG_EXT, - GPIO18_FLASH_MODE_CFG, - GPIO18_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio19", - .regmap[0] = { - AIROHA_FUNC_PWM_EXT_MUX, - REG_GPIO_FLASH_MODE_CFG_EXT, - GPIO19_FLASH_MODE_CFG, - GPIO19_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio20", - .regmap[0] = { - AIROHA_FUNC_PWM_EXT_MUX, - REG_GPIO_FLASH_MODE_CFG_EXT, - GPIO20_FLASH_MODE_CFG, - GPIO20_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio21", - .regmap[0] = { - AIROHA_FUNC_PWM_EXT_MUX, - REG_GPIO_FLASH_MODE_CFG_EXT, - GPIO21_FLASH_MODE_CFG, - GPIO21_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio22", - .regmap[0] = { - AIROHA_FUNC_PWM_EXT_MUX, - REG_GPIO_FLASH_MODE_CFG_EXT, - GPIO22_FLASH_MODE_CFG, - GPIO22_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio23", - .regmap[0] = { - AIROHA_FUNC_PWM_EXT_MUX, - REG_GPIO_FLASH_MODE_CFG_EXT, - GPIO23_FLASH_MODE_CFG, - GPIO23_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio24", - .regmap[0] = { - AIROHA_FUNC_PWM_EXT_MUX, - REG_GPIO_FLASH_MODE_CFG_EXT, - GPIO24_FLASH_MODE_CFG, - GPIO24_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio25", - .regmap[0] = { - AIROHA_FUNC_PWM_EXT_MUX, - REG_GPIO_FLASH_MODE_CFG_EXT, - GPIO25_FLASH_MODE_CFG, - GPIO25_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio26", - .regmap[0] = { - AIROHA_FUNC_PWM_EXT_MUX, - REG_GPIO_FLASH_MODE_CFG_EXT, - GPIO26_FLASH_MODE_CFG, - GPIO26_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio27", - .regmap[0] = { - AIROHA_FUNC_PWM_EXT_MUX, - REG_GPIO_FLASH_MODE_CFG_EXT, - GPIO27_FLASH_MODE_CFG, - GPIO27_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio28", - .regmap[0] = { - AIROHA_FUNC_PWM_EXT_MUX, - REG_GPIO_FLASH_MODE_CFG_EXT, - GPIO28_FLASH_MODE_CFG, - GPIO28_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio29", - .regmap[0] = { - AIROHA_FUNC_PWM_EXT_MUX, - REG_GPIO_FLASH_MODE_CFG_EXT, - GPIO29_FLASH_MODE_CFG, - GPIO29_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio30", - .regmap[0] = { - AIROHA_FUNC_PWM_EXT_MUX, - REG_GPIO_FLASH_MODE_CFG_EXT, - GPIO30_FLASH_MODE_CFG, - GPIO30_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio31", - .regmap[0] = { - AIROHA_FUNC_PWM_EXT_MUX, - REG_GPIO_FLASH_MODE_CFG_EXT, - GPIO31_FLASH_MODE_CFG, - GPIO31_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio36", - .regmap[0] = { - AIROHA_FUNC_PWM_EXT_MUX, - REG_GPIO_FLASH_MODE_CFG_EXT, - GPIO36_FLASH_MODE_CFG, - GPIO36_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio37", - .regmap[0] = { - AIROHA_FUNC_PWM_EXT_MUX, - REG_GPIO_FLASH_MODE_CFG_EXT, - GPIO37_FLASH_MODE_CFG, - GPIO37_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio38", - .regmap[0] = { - AIROHA_FUNC_PWM_EXT_MUX, - REG_GPIO_FLASH_MODE_CFG_EXT, - GPIO38_FLASH_MODE_CFG, - GPIO38_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio39", - .regmap[0] = { - AIROHA_FUNC_PWM_EXT_MUX, - REG_GPIO_FLASH_MODE_CFG_EXT, - GPIO39_FLASH_MODE_CFG, - GPIO39_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio40", - .regmap[0] = { - AIROHA_FUNC_PWM_EXT_MUX, - REG_GPIO_FLASH_MODE_CFG_EXT, - GPIO40_FLASH_MODE_CFG, - GPIO40_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio41", - .regmap[0] = { - AIROHA_FUNC_PWM_EXT_MUX, - REG_GPIO_FLASH_MODE_CFG_EXT, - GPIO41_FLASH_MODE_CFG, - GPIO41_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio42", - .regmap[0] = { - AIROHA_FUNC_PWM_EXT_MUX, - REG_GPIO_FLASH_MODE_CFG_EXT, - GPIO42_FLASH_MODE_CFG, - GPIO42_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio43", - .regmap[0] = { - AIROHA_FUNC_PWM_EXT_MUX, - REG_GPIO_FLASH_MODE_CFG_EXT, - GPIO43_FLASH_MODE_CFG, - GPIO43_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio44", - .regmap[0] = { - AIROHA_FUNC_PWM_EXT_MUX, - REG_GPIO_FLASH_MODE_CFG_EXT, - GPIO44_FLASH_MODE_CFG, - GPIO44_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio45", - .regmap[0] = { - AIROHA_FUNC_PWM_EXT_MUX, - REG_GPIO_FLASH_MODE_CFG_EXT, - GPIO45_FLASH_MODE_CFG, - GPIO45_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio46", - .regmap[0] = { - AIROHA_FUNC_PWM_EXT_MUX, - REG_GPIO_FLASH_MODE_CFG_EXT, - GPIO46_FLASH_MODE_CFG, - GPIO46_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, { - .name = "gpio47", - .regmap[0] = { - AIROHA_FUNC_PWM_EXT_MUX, - REG_GPIO_FLASH_MODE_CFG_EXT, - GPIO47_FLASH_MODE_CFG, - GPIO47_FLASH_MODE_CFG - }, - .regmap_size = 1, - }, + AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio47", GPIO47_FLASH_MODE_CFG), }; #define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ From e6e47d31d3f80d1e9eee863f1f24d8597f3c9deb Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Fri, 7 Nov 2025 00:57:07 +0100 Subject: [PATCH 088/107] dt-bindings: pinctrl: airoha: Document AN7583 Pin Controller Document Airoha AN7583 Pin Controller based on Airoha EN7581 with some minor difference on some function group (PCM and LED gpio). To not bloat the EN7581 schema with massive if condition, use a dedicated YAML schema for Airoha AN7583. Signed-off-by: Christian Marangi Reviewed-by: Conor Dooley Signed-off-by: Linus Walleij --- .../pinctrl/airoha,an7583-pinctrl.yaml | 402 ++++++++++++++++++ 1 file changed, 402 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml new file mode 100644 index 000000000000..79910214d9b5 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml @@ -0,0 +1,402 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/airoha,an7583-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha AN7583 Pin Controller + +maintainers: + - Lorenzo Bianconi + +description: + The Airoha's AN7583 Pin controller is used to control SoC pins. + +properties: + compatible: + const: airoha,an7583-pinctrl + + interrupts: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - interrupts + - gpio-controller + - "#gpio-cells" + - interrupt-controller + - "#interrupt-cells" + +patternProperties: + '-pins$': + type: object + + patternProperties: + '^mux(-|$)': + type: object + + description: + pinmux configuration nodes. + + $ref: /schemas/pinctrl/pinmux-node.yaml + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [pon, tod_1pps, sipo, mdio, uart, i2c, jtag, pcm, spi, + pcm_spi, i2s, emmc, pnand, pcie_reset, pwm, phy1_led0, + phy2_led0, phy3_led0, phy4_led0, phy1_led1, phy2_led1, + phy3_led1, phy4_led1] + + groups: + description: + An array of strings. Each string contains the name of a group. + + required: + - function + - groups + + allOf: + - if: + properties: + function: + const: pon + then: + properties: + groups: + enum: [pon] + - if: + properties: + function: + const: tod_1pps + then: + properties: + groups: + enum: [pon_tod_1pps, gsw_tod_1pps] + - if: + properties: + function: + const: sipo + then: + properties: + groups: + enum: [sipo, sipo_rclk] + - if: + properties: + function: + const: mdio + then: + properties: + groups: + enum: [mdio] + - if: + properties: + function: + const: uart + then: + properties: + groups: + items: + enum: [uart2, uart2_cts_rts, hsuart, hsuart_cts_rts, + uart4, uart5] + maxItems: 2 + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c1] + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag_udi, jtag_dfd] + - if: + properties: + function: + const: pcm + then: + properties: + groups: + enum: [pcm1, pcm2] + - if: + properties: + function: + const: spi + then: + properties: + groups: + items: + enum: [spi_quad, spi_cs1] + maxItems: 2 + - if: + properties: + function: + const: pcm_spi + then: + properties: + groups: + items: + enum: [pcm_spi, pcm_spi_int, pcm_spi_rst, pcm_spi_cs1, + pcm_spi_cs2, pcm_spi_cs3, pcm_spi_cs4] + maxItems: 7 + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2s] + - if: + properties: + function: + const: emmc + then: + properties: + groups: + enum: [emmc] + - if: + properties: + function: + const: pnand + then: + properties: + groups: + enum: [pnand] + - if: + properties: + function: + const: pcie_reset + then: + properties: + groups: + enum: [pcie_reset0, pcie_reset1] + - if: + properties: + function: + const: pwm + then: + properties: + groups: + enum: [gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, + gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, + gpio14, gpio15, gpio16, gpio17, gpio18, gpio19, + gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, + gpio26, gpio27, gpio28, gpio29, gpio30, gpio31, + gpio36, gpio37, gpio38, gpio39, gpio40, gpio41, + gpio42, gpio43, gpio44, gpio45, gpio46, gpio47] + - if: + properties: + function: + const: phy1_led0 + then: + properties: + groups: + enum: [gpio1, gpio2, gpio3, gpio4] + - if: + properties: + function: + const: phy2_led0 + then: + properties: + groups: + enum: [gpio1, gpio2, gpio3, gpio4] + - if: + properties: + function: + const: phy3_led0 + then: + properties: + groups: + enum: [gpio1, gpio2, gpio3, gpio4] + - if: + properties: + function: + const: phy4_led0 + then: + properties: + groups: + enum: [gpio1, gpio2, gpio3, gpio4] + - if: + properties: + function: + const: phy1_led1 + then: + properties: + groups: + enum: [gpio8, gpio9, gpio10, gpio11] + - if: + properties: + function: + const: phy2_led1 + then: + properties: + groups: + enum: [gpio8, gpio9, gpio10, gpio11] + - if: + properties: + function: + const: phy3_led1 + then: + properties: + groups: + enum: [gpio8, gpio9, gpio10, gpio11] + - if: + properties: + function: + const: phy4_led1 + then: + properties: + groups: + enum: [gpio8, gpio9, gpio10, gpio11] + + additionalProperties: false + + '^conf(-|$)': + type: object + + description: + pinconf configuration nodes. + + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pins: + description: + An array of strings. Each string contains the name of a pin. + items: + enum: [uart1_txd, uart1_rxd, i2c_scl, i2c_sda, spi_cs0, spi_clk, + spi_mosi, spi_miso, gpio0, gpio1, gpio2, gpio3, gpio4, + gpio5, gpio6, gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, + gpio13, gpio14, gpio15, gpio16, gpio17, gpio18, gpio19, + gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, gpio26, + gpio27, gpio28, gpio29, gpio30, gpio31, gpio32, gpio33, + gpio34, gpio35, gpio36, gpio37, gpio38, gpio39, gpio40, + gpio41, gpio42, gpio43, gpio44, gpio45, gpio46, + pcie_reset0, pcie_reset1, pcie_reset2] + minItems: 1 + maxItems: 58 + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + input-enable: true + + output-enable: true + + output-low: true + + output-high: true + + drive-open-drain: true + + drive-strength: + description: + Selects the drive strength for MIO pins, in mA. + enum: [2, 4, 6, 8] + + required: + - pins + + additionalProperties: false + + additionalProperties: false + +additionalProperties: false + +examples: + - | + #include + + pinctrl { + compatible = "airoha,an7583-pinctrl"; + + interrupt-parent = <&gic>; + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + pcie1-rst-pins { + conf { + pins = "pcie_reset1"; + drive-open-drain = <1>; + }; + }; + + pwm-pins { + mux { + function = "pwm"; + groups = "gpio18"; + }; + }; + + spi-pins { + mux { + function = "spi"; + groups = "spi_quad", "spi_cs1"; + }; + }; + + uart2-pins { + mux { + function = "uart"; + groups = "uart2", "uart2_cts_rts"; + }; + }; + + uar5-pins { + mux { + function = "uart"; + groups = "uart5"; + }; + }; + + mmc-pins { + mux { + function = "emmc"; + groups = "emmc"; + }; + }; + + mdio-pins { + mux { + function = "mdio"; + groups = "mdio"; + }; + + conf { + pins = "gpio2"; + output-enable; + }; + }; + }; From 3ffeb17a9a27a668efb6fbd074835e187910a9bb Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Fri, 7 Nov 2025 00:57:08 +0100 Subject: [PATCH 089/107] pinctrl: airoha: add support for Airoha AN7583 PINs Add all the required entry to add suppot for Airoha AN7583 PINs. Where possible the same function group are used from Airoha EN7581 to reduce code duplication. Signed-off-by: Christian Marangi Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-airoha.c | 747 +++++++++++++++++++++- 1 file changed, 740 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c index f3cf48bdd1f8..bfcedc7f920b 100644 --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c @@ -70,6 +70,7 @@ #define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20) #define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19) #define GPIO_PCM_SPI_CS2_MODE_P128_MASK BIT(18) +#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK BIT(18) #define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17) #define GPIO_PCM_SPI_MODE_MASK BIT(16) #define GPIO_PCM2_MODE_MASK BIT(13) @@ -127,6 +128,8 @@ /* CONF */ #define REG_I2C_SDA_E2 0x001c +#define AN7583_I2C1_SCL_E2_MASK BIT(16) +#define AN7583_I2C1_SDA_E2_MASK BIT(15) #define SPI_MISO_E2_MASK BIT(14) #define SPI_MOSI_E2_MASK BIT(13) #define SPI_CLK_E2_MASK BIT(12) @@ -134,12 +137,16 @@ #define PCIE2_RESET_E2_MASK BIT(10) #define PCIE1_RESET_E2_MASK BIT(9) #define PCIE0_RESET_E2_MASK BIT(8) +#define AN7583_MDIO_0_E2_MASK BIT(5) +#define AN7583_MDC_0_E2_MASK BIT(4) #define UART1_RXD_E2_MASK BIT(3) #define UART1_TXD_E2_MASK BIT(2) #define I2C_SCL_E2_MASK BIT(1) #define I2C_SDA_E2_MASK BIT(0) #define REG_I2C_SDA_E4 0x0020 +#define AN7583_I2C1_SCL_E4_MASK BIT(16) +#define AN7583_I2C1_SDA_E4_MASK BIT(15) #define SPI_MISO_E4_MASK BIT(14) #define SPI_MOSI_E4_MASK BIT(13) #define SPI_CLK_E4_MASK BIT(12) @@ -147,6 +154,8 @@ #define PCIE2_RESET_E4_MASK BIT(10) #define PCIE1_RESET_E4_MASK BIT(9) #define PCIE0_RESET_E4_MASK BIT(8) +#define AN7583_MDIO_0_E4_MASK BIT(5) +#define AN7583_MDC_0_E4_MASK BIT(4) #define UART1_RXD_E4_MASK BIT(3) #define UART1_TXD_E4_MASK BIT(2) #define I2C_SCL_E4_MASK BIT(1) @@ -158,6 +167,8 @@ #define REG_GPIO_H_E4 0x0030 #define REG_I2C_SDA_PU 0x0044 +#define AN7583_I2C1_SCL_PU_MASK BIT(16) +#define AN7583_I2C1_SDA_PU_MASK BIT(15) #define SPI_MISO_PU_MASK BIT(14) #define SPI_MOSI_PU_MASK BIT(13) #define SPI_CLK_PU_MASK BIT(12) @@ -165,12 +176,16 @@ #define PCIE2_RESET_PU_MASK BIT(10) #define PCIE1_RESET_PU_MASK BIT(9) #define PCIE0_RESET_PU_MASK BIT(8) +#define AN7583_MDIO_0_PU_MASK BIT(5) +#define AN7583_MDC_0_PU_MASK BIT(4) #define UART1_RXD_PU_MASK BIT(3) #define UART1_TXD_PU_MASK BIT(2) #define I2C_SCL_PU_MASK BIT(1) #define I2C_SDA_PU_MASK BIT(0) #define REG_I2C_SDA_PD 0x0048 +#define AN7583_I2C1_SDA_PD_MASK BIT(16) +#define AN7583_I2C1_SCL_PD_MASK BIT(15) #define SPI_MISO_PD_MASK BIT(14) #define SPI_MOSI_PD_MASK BIT(13) #define SPI_CLK_PD_MASK BIT(12) @@ -178,6 +193,8 @@ #define PCIE2_RESET_PD_MASK BIT(10) #define PCIE1_RESET_PD_MASK BIT(9) #define PCIE0_RESET_PD_MASK BIT(8) +#define AN7583_MDIO_0_PD_MASK BIT(5) +#define AN7583_MDC_0_PD_MASK BIT(4) #define UART1_RXD_PD_MASK BIT(3) #define UART1_TXD_PD_MASK BIT(2) #define I2C_SCL_PD_MASK BIT(1) @@ -625,10 +642,223 @@ static const struct pingroup en7581_pinctrl_groups[] = { PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2), }; +static struct pinctrl_pin_desc an7583_pinctrl_pins[] = { + PINCTRL_PIN(2, "gpio0"), + PINCTRL_PIN(3, "gpio1"), + PINCTRL_PIN(4, "gpio2"), + PINCTRL_PIN(5, "gpio3"), + PINCTRL_PIN(6, "gpio4"), + PINCTRL_PIN(7, "gpio5"), + PINCTRL_PIN(8, "gpio6"), + PINCTRL_PIN(9, "gpio7"), + PINCTRL_PIN(10, "gpio8"), + PINCTRL_PIN(11, "gpio9"), + PINCTRL_PIN(12, "gpio10"), + PINCTRL_PIN(13, "gpio11"), + PINCTRL_PIN(14, "gpio12"), + PINCTRL_PIN(15, "gpio13"), + PINCTRL_PIN(16, "gpio14"), + PINCTRL_PIN(17, "gpio15"), + PINCTRL_PIN(18, "gpio16"), + PINCTRL_PIN(19, "gpio17"), + PINCTRL_PIN(20, "gpio18"), + PINCTRL_PIN(21, "gpio19"), + PINCTRL_PIN(22, "gpio20"), + PINCTRL_PIN(23, "gpio21"), + PINCTRL_PIN(24, "gpio22"), + PINCTRL_PIN(25, "gpio23"), + PINCTRL_PIN(26, "gpio24"), + PINCTRL_PIN(27, "gpio25"), + PINCTRL_PIN(28, "gpio26"), + PINCTRL_PIN(29, "gpio27"), + PINCTRL_PIN(30, "gpio28"), + PINCTRL_PIN(31, "gpio29"), + PINCTRL_PIN(32, "gpio30"), + PINCTRL_PIN(33, "gpio31"), + PINCTRL_PIN(34, "gpio32"), + PINCTRL_PIN(35, "gpio33"), + PINCTRL_PIN(36, "gpio34"), + PINCTRL_PIN(37, "gpio35"), + PINCTRL_PIN(38, "gpio36"), + PINCTRL_PIN(39, "gpio37"), + PINCTRL_PIN(40, "gpio38"), + PINCTRL_PIN(41, "i2c0_scl"), + PINCTRL_PIN(42, "i2c0_sda"), + PINCTRL_PIN(43, "i2c1_scl"), + PINCTRL_PIN(44, "i2c1_sda"), + PINCTRL_PIN(45, "spi_clk"), + PINCTRL_PIN(46, "spi_cs"), + PINCTRL_PIN(47, "spi_mosi"), + PINCTRL_PIN(48, "spi_miso"), + PINCTRL_PIN(49, "uart_txd"), + PINCTRL_PIN(50, "uart_rxd"), + PINCTRL_PIN(51, "pcie_reset0"), + PINCTRL_PIN(52, "pcie_reset1"), + PINCTRL_PIN(53, "mdc_0"), + PINCTRL_PIN(54, "mdio_0"), +}; + +static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 }; +static const int an7583_pon_tod_1pps_pins[] = { 32 }; +static const int an7583_gsw_tod_1pps_pins[] = { 32 }; +static const int an7583_sipo_pins[] = { 34, 35 }; +static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 }; +static const int an7583_mdio_pins[] = { 43, 44 }; +static const int an7583_uart2_pins[] = { 34, 35 }; +static const int an7583_uart2_cts_rts_pins[] = { 32, 33 }; +static const int an7583_hsuart_pins[] = { 30, 31 }; +static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 }; +static const int an7583_npu_uart_pins[] = { 7, 8 }; +static const int an7583_uart4_pins[] = { 7, 8 }; +static const int an7583_uart5_pins[] = { 23, 24 }; +static const int an7583_i2c0_pins[] = { 41, 42 }; +static const int an7583_i2c1_pins[] = { 43, 44 }; +static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 }; +static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 }; +static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 }; +static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 }; +static const int an7583_spi_pins[] = { 28, 29, 30, 31 }; +static const int an7583_spi_quad_pins[] = { 25, 26 }; +static const int an7583_spi_cs1_pins[] = { 27 }; +static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 }; +static const int an7583_pcm_spi_rst_pins[] = { 14 }; +static const int an7583_pcm_spi_cs1_pins[] = { 24 }; +static const int an7583_emmc_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47 }; +static const int an7583_pnand_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48 }; +static const int an7583_gpio0_pins[] = { 2 }; +static const int an7583_gpio1_pins[] = { 3 }; +static const int an7583_gpio2_pins[] = { 4 }; +static const int an7583_gpio3_pins[] = { 5 }; +static const int an7583_gpio4_pins[] = { 6 }; +static const int an7583_gpio5_pins[] = { 7 }; +static const int an7583_gpio6_pins[] = { 8 }; +static const int an7583_gpio7_pins[] = { 9 }; +static const int an7583_gpio8_pins[] = { 10 }; +static const int an7583_gpio9_pins[] = { 11 }; +static const int an7583_gpio10_pins[] = { 12 }; +static const int an7583_gpio11_pins[] = { 13 }; +static const int an7583_gpio12_pins[] = { 14 }; +static const int an7583_gpio13_pins[] = { 15 }; +static const int an7583_gpio14_pins[] = { 16 }; +static const int an7583_gpio15_pins[] = { 17 }; +static const int an7583_gpio16_pins[] = { 18 }; +static const int an7583_gpio17_pins[] = { 19 }; +static const int an7583_gpio18_pins[] = { 20 }; +static const int an7583_gpio19_pins[] = { 21 }; +static const int an7583_gpio20_pins[] = { 22 }; +static const int an7583_gpio21_pins[] = { 24 }; +static const int an7583_gpio23_pins[] = { 25 }; +static const int an7583_gpio24_pins[] = { 26 }; +static const int an7583_gpio25_pins[] = { 27 }; +static const int an7583_gpio26_pins[] = { 28 }; +static const int an7583_gpio27_pins[] = { 29 }; +static const int an7583_gpio28_pins[] = { 30 }; +static const int an7583_gpio29_pins[] = { 31 }; +static const int an7583_gpio30_pins[] = { 32 }; +static const int an7583_gpio31_pins[] = { 33 }; +static const int an7583_gpio33_pins[] = { 35 }; +static const int an7583_gpio34_pins[] = { 36 }; +static const int an7583_gpio35_pins[] = { 37 }; +static const int an7583_gpio36_pins[] = { 38 }; +static const int an7583_gpio37_pins[] = { 39 }; +static const int an7583_gpio38_pins[] = { 40 }; +static const int an7583_gpio39_pins[] = { 41 }; +static const int an7583_gpio40_pins[] = { 42 }; +static const int an7583_gpio41_pins[] = { 43 }; +static const int an7583_gpio42_pins[] = { 44 }; +static const int an7583_gpio43_pins[] = { 45 }; +static const int an7583_gpio44_pins[] = { 46 }; +static const int an7583_gpio45_pins[] = { 47 }; +static const int an7583_gpio46_pins[] = { 48 }; +static const int an7583_gpio47_pins[] = { 49 }; +static const int an7583_gpio48_pins[] = { 50 }; +static const int an7583_pcie_reset0_pins[] = { 51 }; +static const int an7583_pcie_reset1_pins[] = { 52 }; + +static const struct pingroup an7583_pinctrl_groups[] = { + PINCTRL_PIN_GROUP("pon", an7583_pon), + PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps), + PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps), + PINCTRL_PIN_GROUP("sipo", an7583_sipo), + PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk), + PINCTRL_PIN_GROUP("mdio", an7583_mdio), + PINCTRL_PIN_GROUP("uart2", an7583_uart2), + PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts), + PINCTRL_PIN_GROUP("hsuart", an7583_hsuart), + PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts), + PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart), + PINCTRL_PIN_GROUP("uart4", an7583_uart4), + PINCTRL_PIN_GROUP("uart5", an7583_uart5), + PINCTRL_PIN_GROUP("i2c0", an7583_i2c0), + PINCTRL_PIN_GROUP("i2c1", an7583_i2c1), + PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi), + PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd), + PINCTRL_PIN_GROUP("pcm1", an7583_pcm1), + PINCTRL_PIN_GROUP("pcm2", an7583_pcm2), + PINCTRL_PIN_GROUP("spi", an7583_spi), + PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad), + PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1), + PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi), + PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst), + PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1), + PINCTRL_PIN_GROUP("emmc", an7583_emmc), + PINCTRL_PIN_GROUP("pnand", an7583_pnand), + PINCTRL_PIN_GROUP("gpio0", an7583_gpio0), + PINCTRL_PIN_GROUP("gpio1", an7583_gpio1), + PINCTRL_PIN_GROUP("gpio2", an7583_gpio2), + PINCTRL_PIN_GROUP("gpio3", an7583_gpio3), + PINCTRL_PIN_GROUP("gpio4", an7583_gpio4), + PINCTRL_PIN_GROUP("gpio5", an7583_gpio5), + PINCTRL_PIN_GROUP("gpio6", an7583_gpio6), + PINCTRL_PIN_GROUP("gpio7", an7583_gpio7), + PINCTRL_PIN_GROUP("gpio8", an7583_gpio8), + PINCTRL_PIN_GROUP("gpio9", an7583_gpio9), + PINCTRL_PIN_GROUP("gpio10", an7583_gpio10), + PINCTRL_PIN_GROUP("gpio11", an7583_gpio11), + PINCTRL_PIN_GROUP("gpio12", an7583_gpio12), + PINCTRL_PIN_GROUP("gpio13", an7583_gpio13), + PINCTRL_PIN_GROUP("gpio14", an7583_gpio14), + PINCTRL_PIN_GROUP("gpio15", an7583_gpio15), + PINCTRL_PIN_GROUP("gpio16", an7583_gpio16), + PINCTRL_PIN_GROUP("gpio17", an7583_gpio17), + PINCTRL_PIN_GROUP("gpio18", an7583_gpio18), + PINCTRL_PIN_GROUP("gpio19", an7583_gpio19), + PINCTRL_PIN_GROUP("gpio20", an7583_gpio20), + PINCTRL_PIN_GROUP("gpio21", an7583_gpio21), + PINCTRL_PIN_GROUP("gpio23", an7583_gpio23), + PINCTRL_PIN_GROUP("gpio24", an7583_gpio24), + PINCTRL_PIN_GROUP("gpio25", an7583_gpio25), + PINCTRL_PIN_GROUP("gpio26", an7583_gpio26), + PINCTRL_PIN_GROUP("gpio27", an7583_gpio27), + PINCTRL_PIN_GROUP("gpio28", an7583_gpio28), + PINCTRL_PIN_GROUP("gpio29", an7583_gpio29), + PINCTRL_PIN_GROUP("gpio30", an7583_gpio30), + PINCTRL_PIN_GROUP("gpio31", an7583_gpio31), + PINCTRL_PIN_GROUP("gpio33", an7583_gpio33), + PINCTRL_PIN_GROUP("gpio34", an7583_gpio34), + PINCTRL_PIN_GROUP("gpio35", an7583_gpio35), + PINCTRL_PIN_GROUP("gpio36", an7583_gpio36), + PINCTRL_PIN_GROUP("gpio37", an7583_gpio37), + PINCTRL_PIN_GROUP("gpio38", an7583_gpio38), + PINCTRL_PIN_GROUP("gpio39", an7583_gpio39), + PINCTRL_PIN_GROUP("gpio40", an7583_gpio40), + PINCTRL_PIN_GROUP("gpio41", an7583_gpio41), + PINCTRL_PIN_GROUP("gpio42", an7583_gpio42), + PINCTRL_PIN_GROUP("gpio43", an7583_gpio43), + PINCTRL_PIN_GROUP("gpio44", an7583_gpio44), + PINCTRL_PIN_GROUP("gpio45", an7583_gpio45), + PINCTRL_PIN_GROUP("gpio46", an7583_gpio46), + PINCTRL_PIN_GROUP("gpio47", an7583_gpio47), + PINCTRL_PIN_GROUP("gpio48", an7583_gpio48), + PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0), + PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1), +}; + static const char *const pon_groups[] = { "pon" }; static const char *const tod_1pps_groups[] = { "pon_tod_1pps", "gsw_tod_1pps" }; static const char *const sipo_groups[] = { "sipo", "sipo_rclk" }; static const char *const mdio_groups[] = { "mdio" }; +static const char *const an7583_mdio_groups[] = { "mdio" }; static const char *const uart_groups[] = { "uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts", "uart4", "uart5" }; @@ -641,11 +871,16 @@ static const char *const pcm_spi_groups[] = { "pcm_spi", "pcm_spi_int", "pcm_spi_cs2_p156", "pcm_spi_cs2_p128", "pcm_spi_cs3", "pcm_spi_cs4" }; +static const char *const an7583_pcm_spi_groups[] = { "pcm_spi", "pcm_spi_int", + "pcm_spi_rst", "pcm_spi_cs1", + "pcm_spi_cs2", "pcm_spi_cs3", + "pcm_spi_cs4" }; static const char *const i2s_groups[] = { "i2s" }; static const char *const emmc_groups[] = { "emmc" }; static const char *const pnand_groups[] = { "pnand" }; static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1", "pcie_reset2" }; +static const char *const an7583_pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1" }; static const char *const pwm_groups[] = { "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", @@ -684,6 +919,22 @@ static const char *const phy3_led1_groups[] = { "gpio43", "gpio44", "gpio45", "gpio46" }; static const char *const phy4_led1_groups[] = { "gpio43", "gpio44", "gpio45", "gpio46" }; +static const char *const an7583_phy1_led0_groups[] = { "gpio1", "gpio2", + "gpio3", "gpio4" }; +static const char *const an7583_phy2_led0_groups[] = { "gpio1", "gpio2", + "gpio3", "gpio4" }; +static const char *const an7583_phy3_led0_groups[] = { "gpio1", "gpio2", + "gpio3", "gpio4" }; +static const char *const an7583_phy4_led0_groups[] = { "gpio1", "gpio2", + "gpio3", "gpio4" }; +static const char *const an7583_phy1_led1_groups[] = { "gpio8", "gpio9", + "gpio10", "gpio11" }; +static const char *const an7583_phy2_led1_groups[] = { "gpio8", "gpio9", + "gpio10", "gpio11" }; +static const char *const an7583_phy3_led1_groups[] = { "gpio8", "gpio9", + "gpio10", "gpio11" }; +static const char *const an7583_phy4_led1_groups[] = { "gpio8", "gpio9", + "gpio10", "gpio11" }; static const struct airoha_pinctrl_func_group pon_func_group[] = { { @@ -761,6 +1012,25 @@ static const struct airoha_pinctrl_func_group mdio_func_group[] = { }, }; +static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = { + { + .name = "mdio", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SGMII_MDIO_MODE_MASK, + GPIO_SGMII_MDIO_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_MDC_IO_MASTER_MODE_MODE, + GPIO_MDC_IO_MASTER_MODE_MODE + }, + .regmap_size = 2, + }, +}; + static const struct airoha_pinctrl_func_group uart_func_group[] = { { .name = "uart2", @@ -1002,6 +1272,73 @@ static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = { }, }; +static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = { + { + .name = "pcm_spi", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_MODE_MASK, + GPIO_PCM_SPI_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_int", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_INT_MODE_MASK, + GPIO_PCM_INT_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_rst", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_RESET_MODE_MASK, + GPIO_PCM_RESET_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS1_MODE_MASK, + GPIO_PCM_SPI_CS1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + AN7583_GPIO_PCM_SPI_CS2_MODE_MASK, + AN7583_GPIO_PCM_SPI_CS2_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs3", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS3_MODE_MASK, + GPIO_PCM_SPI_CS3_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs4", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS4_MODE_MASK, + GPIO_PCM_SPI_CS4_MODE_MASK + }, + .regmap_size = 1, + }, +}; + static const struct airoha_pinctrl_func_group i2s_func_group[] = { { .name = "i2s", @@ -1072,6 +1409,28 @@ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = { }, }; +static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = { + { + .name = "pcie_reset0", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET0_MASK, + GPIO_PCIE_RESET0_MASK + }, + .regmap_size = 1, + }, { + .name = "pcie_reset1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET1_MASK, + GPIO_PCIE_RESET1_MASK + }, + .regmap_size = 1, + }, +}; + /* PWM */ #define AIROHA_PINCTRL_PWM(gpio, mux_val) \ { \ @@ -1268,6 +1627,94 @@ static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = { LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), }; +static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), +}; + +static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio1", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), +}; + static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = { PINCTRL_FUNC_DESC("pon", pon), PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), @@ -1294,6 +1741,31 @@ static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = { PINCTRL_FUNC_DESC("phy4_led1", phy4_led1), }; +static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = { + PINCTRL_FUNC_DESC("pon", pon), + PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), + PINCTRL_FUNC_DESC("sipo", sipo), + PINCTRL_FUNC_DESC("mdio", an7583_mdio), + PINCTRL_FUNC_DESC("uart", uart), + PINCTRL_FUNC_DESC("i2c", i2c), + PINCTRL_FUNC_DESC("jtag", jtag), + PINCTRL_FUNC_DESC("pcm", pcm), + PINCTRL_FUNC_DESC("spi", spi), + PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi), + PINCTRL_FUNC_DESC("emmc", emmc), + PINCTRL_FUNC_DESC("pnand", pnand), + PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset), + PINCTRL_FUNC_DESC("pwm", pwm), + PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0), + PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0), + PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0), + PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0), + PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1), + PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1), + PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1), + PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1), +}; + static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = { PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), @@ -1355,6 +1827,62 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = { PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK), }; +static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = { + PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(18)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)), + PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)), + PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)), + PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)), + PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)), + PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)), + PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)), + PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), + PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), + PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK), + PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK), + PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), + PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), + PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), + PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK), + PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), + PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), + PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), + PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), + PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK), + PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK), +}; + static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = { PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), @@ -1416,6 +1944,62 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = { PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK), }; +static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = { + PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(18)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)), + PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)), + PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)), + PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)), + PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)), + PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)), + PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)), + PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), + PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), + PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK), + PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK), + PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), + PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), + PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), + PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK), + PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), + PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), + PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), + PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), + PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK), + PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK), +}; + static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = { PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), @@ -1477,6 +2061,62 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = { PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK), }; +static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = { + PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(18)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)), + PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)), + PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)), + PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)), + PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)), + PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)), + PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)), + PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), + PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), + PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK), + PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK), + PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), + PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), + PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), + PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK), + PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), + PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), + PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), + PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), + PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK), + PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK), +}; + static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = { PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), @@ -1538,12 +2178,73 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = { PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK), }; +static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = { + PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(18)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)), + PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)), + PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)), + PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)), + PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)), + PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)), + PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)), + PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), + PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), + PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK), + PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK), + PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), + PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), + PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), + PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK), + PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), + PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), + PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), + PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), + PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK), + PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK), +}; + static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = { PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), PINCTRL_CONF_DESC(63, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK), }; +static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = { + PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), + PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), +}; + static int airoha_convert_pin_to_reg_offset(struct pinctrl_dev *pctrl_dev, struct pinctrl_gpio_range *range, int pin) @@ -1708,7 +2409,7 @@ static const struct irq_chip airoha_gpio_irq_chip = { }; static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl, - struct platform_device *pdev) + struct platform_device *pdev) { struct airoha_pinctrl_gpiochip *chip = &pinctrl->gpiochip; struct gpio_chip *gc = &chip->chip; @@ -1743,7 +2444,7 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl, return irq; err = devm_request_irq(dev, irq, airoha_irq_handler, IRQF_SHARED, - dev_name(dev), pinctrl); + dev_name(dev), pinctrl); if (err) { dev_err(dev, "error requesting irq %d: %d\n", irq, err); return err; @@ -1807,8 +2508,8 @@ static int airoha_pinmux_set_mux(struct pinctrl_dev *pctrl_dev, } static int airoha_pinmux_set_direction(struct pinctrl_dev *pctrl_dev, - struct pinctrl_gpio_range *range, - unsigned int p, bool input) + struct pinctrl_gpio_range *range, + unsigned int p, bool input) { struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); u32 mask, index; @@ -1898,7 +2599,7 @@ static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl, if (regmap_update_bits(pinctrl->chip_scu, reg->offset, reg->mask, - val << __ffs(reg->mask))) + val << __ffs(reg->mask))) return -EINVAL; return 0; @@ -2115,8 +2816,8 @@ static int airoha_pinconf_group_get(struct pinctrl_dev *pctrl_dev, for (i = 0; i < pinctrl->grps[group].npins; i++) { if (airoha_pinconf_get(pctrl_dev, - pinctrl->grps[group].pins[i], - config)) + pinctrl->grps[group].pins[i], + config)) return -ENOTSUPP; if (i && cur_config != *config) @@ -2275,8 +2976,40 @@ static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = { }, }; +static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = { + .pins = an7583_pinctrl_pins, + .num_pins = ARRAY_SIZE(an7583_pinctrl_pins), + .grps = an7583_pinctrl_groups, + .num_grps = ARRAY_SIZE(an7583_pinctrl_groups), + .funcs = an7583_pinctrl_funcs, + .num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs), + .confs_info = { + [AIROHA_PINCTRL_CONFS_PULLUP] = { + .confs = an7583_pinctrl_pullup_conf, + .num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf), + }, + [AIROHA_PINCTRL_CONFS_PULLDOWN] = { + .confs = an7583_pinctrl_pulldown_conf, + .num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E2] = { + .confs = en7581_pinctrl_drive_e2_conf, + .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E4] = { + .confs = an7583_pinctrl_drive_e4_conf, + .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf), + }, + [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = { + .confs = an7583_pinctrl_pcie_rst_od_conf, + .num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf), + }, + }, +}; + static const struct of_device_id airoha_pinctrl_of_match[] = { { .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data }, + { .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match); From ce884de219de43deac6c482590d677872bf358ff Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 11 Nov 2025 20:10:25 +0100 Subject: [PATCH 090/107] pinctrl: cedarfork: Switch to INTEL_GPP() macro Replace custom macro with the recently defined INTEL_GPP(). Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-cedarfork.c | 37 +++++++++-------------- 1 file changed, 15 insertions(+), 22 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-cedarfork.c b/drivers/pinctrl/intel/pinctrl-cedarfork.c index 2ce97abeb0e4..2916f7d90090 100644 --- a/drivers/pinctrl/intel/pinctrl-cedarfork.c +++ b/drivers/pinctrl/intel/pinctrl-cedarfork.c @@ -21,13 +21,6 @@ #define CDF_GPI_IS 0x200 #define CDF_GPI_IE 0x230 -#define CDF_GPP(r, s, e) \ - { \ - .reg_num = (r), \ - .base = (s), \ - .size = ((e) - (s) + 1), \ - } - #define CDF_COMMUNITY(b, s, e, g) \ INTEL_COMMUNITY_GPPS(b, s, e, g, CDF) @@ -288,24 +281,24 @@ static const struct pinctrl_pin_desc cdf_pins[] = { }; static const struct intel_padgroup cdf_community0_gpps[] = { - CDF_GPP(0, 0, 23), /* WEST2 */ - CDF_GPP(1, 24, 47), /* WEST3 */ - CDF_GPP(2, 48, 70), /* WEST01 */ - CDF_GPP(3, 71, 90), /* WEST5 */ - CDF_GPP(4, 91, 96), /* WESTC */ - CDF_GPP(5, 97, 101), /* WESTC_DFX */ - CDF_GPP(6, 102, 111), /* WESTA */ - CDF_GPP(7, 112, 123), /* WESTB */ - CDF_GPP(8, 124, 143), /* WESTD */ - CDF_GPP(9, 144, 144), /* WESTD_PECI */ - CDF_GPP(10, 145, 167), /* WESTF */ + INTEL_GPP(0, 0, 23, 0), /* WEST2 */ + INTEL_GPP(1, 24, 47, 24), /* WEST3 */ + INTEL_GPP(2, 48, 70, 48), /* WEST01 */ + INTEL_GPP(3, 71, 90, 71), /* WEST5 */ + INTEL_GPP(4, 91, 96, 91), /* WESTC */ + INTEL_GPP(5, 97, 101, 97), /* WESTC_DFX */ + INTEL_GPP(6, 102, 111, 102), /* WESTA */ + INTEL_GPP(7, 112, 123, 112), /* WESTB */ + INTEL_GPP(8, 124, 143, 124), /* WESTD */ + INTEL_GPP(9, 144, 144, 144), /* WESTD_PECI */ + INTEL_GPP(10, 145, 167, 145), /* WESTF */ }; static const struct intel_padgroup cdf_community1_gpps[] = { - CDF_GPP(0, 168, 191), /* EAST2 */ - CDF_GPP(1, 192, 202), /* EAST3 */ - CDF_GPP(2, 203, 225), /* EAST0 */ - CDF_GPP(3, 226, 236), /* EMMC */ + INTEL_GPP(0, 168, 191, 168), /* EAST2 */ + INTEL_GPP(1, 192, 202, 192), /* EAST3 */ + INTEL_GPP(2, 203, 225, 203), /* EAST0 */ + INTEL_GPP(3, 226, 236, 226), /* EMMC */ }; static const struct intel_community cdf_communities[] = { From d772897c7cfd8b158c3997b00ddbd9b5671b4fa4 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 11 Nov 2025 20:10:26 +0100 Subject: [PATCH 091/107] pinctrl: denverton: Switch to INTEL_GPP() macro Replace custom macro with the recently defined INTEL_GPP(). Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-denverton.c | 21 +++++++-------------- 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-denverton.c b/drivers/pinctrl/intel/pinctrl-denverton.c index fef44c663be6..f492f73ba246 100644 --- a/drivers/pinctrl/intel/pinctrl-denverton.c +++ b/drivers/pinctrl/intel/pinctrl-denverton.c @@ -21,13 +21,6 @@ #define DNV_GPI_IS 0x100 #define DNV_GPI_IE 0x120 -#define DNV_GPP(n, s, e) \ - { \ - .reg_num = (n), \ - .base = (s), \ - .size = ((e) - (s) + 1), \ - } - #define DNV_COMMUNITY(b, s, e, g) \ INTEL_COMMUNITY_GPPS(b, s, e, g, DNV) @@ -222,16 +215,16 @@ static const struct intel_function dnv_functions[] = { }; static const struct intel_padgroup dnv_north_gpps[] = { - DNV_GPP(0, 0, 31), /* North ALL_0 */ - DNV_GPP(1, 32, 40), /* North ALL_1 */ + INTEL_GPP(0, 0, 31, 0), /* North ALL_0 */ + INTEL_GPP(1, 32, 40, 32), /* North ALL_1 */ }; static const struct intel_padgroup dnv_south_gpps[] = { - DNV_GPP(0, 41, 58), /* South DFX */ - DNV_GPP(1, 59, 90), /* South GPP0_0 */ - DNV_GPP(2, 91, 111), /* South GPP0_1 */ - DNV_GPP(3, 112, 143), /* South GPP1_0 */ - DNV_GPP(4, 144, 153), /* South GPP1_1 */ + INTEL_GPP(0, 41, 58, 41), /* South DFX */ + INTEL_GPP(1, 59, 90, 59), /* South GPP0_0 */ + INTEL_GPP(2, 91, 111, 91), /* South GPP0_1 */ + INTEL_GPP(3, 112, 143, 112), /* South GPP1_0 */ + INTEL_GPP(4, 144, 153, 144), /* South GPP1_1 */ }; static const struct intel_community dnv_communities[] = { From 6c7a9976998d97f9ec9eb84e490f5a65fa2bd479 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 11 Nov 2025 20:10:27 +0100 Subject: [PATCH 092/107] pinctrl: emmitsburg: Switch to INTEL_GPP() macro Replace custom macro with the recently defined INTEL_GPP(). Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-emmitsburg.c | 33 +++++++++------------- 1 file changed, 13 insertions(+), 20 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-emmitsburg.c b/drivers/pinctrl/intel/pinctrl-emmitsburg.c index 9d8a32aca177..ba06a9ec239a 100644 --- a/drivers/pinctrl/intel/pinctrl-emmitsburg.c +++ b/drivers/pinctrl/intel/pinctrl-emmitsburg.c @@ -21,13 +21,6 @@ #define EBG_GPI_IS 0x200 #define EBG_GPI_IE 0x210 -#define EBG_GPP(r, s, e) \ - { \ - .reg_num = (r), \ - .base = (s), \ - .size = ((e) - (s) + 1), \ - } - #define EBG_COMMUNITY(b, s, e, g) \ INTEL_COMMUNITY_GPPS(b, s, e, g, EBG) @@ -311,31 +304,31 @@ static const struct pinctrl_pin_desc ebg_pins[] = { }; static const struct intel_padgroup ebg_community0_gpps[] = { - EBG_GPP(0, 0, 20), /* GPP_A */ - EBG_GPP(1, 21, 44), /* GPP_B */ - EBG_GPP(2, 45, 65), /* SPI */ + INTEL_GPP(0, 0, 20, 0), /* GPP_A */ + INTEL_GPP(1, 21, 44, 21), /* GPP_B */ + INTEL_GPP(2, 45, 65, 45), /* SPI */ }; static const struct intel_padgroup ebg_community1_gpps[] = { - EBG_GPP(0, 66, 87), /* GPP_C */ - EBG_GPP(1, 88, 111), /* GPP_D */ + INTEL_GPP(0, 66, 87, 66), /* GPP_C */ + INTEL_GPP(1, 88, 111, 88), /* GPP_D */ }; static const struct intel_padgroup ebg_community3_gpps[] = { - EBG_GPP(0, 112, 135), /* GPP_E */ - EBG_GPP(1, 136, 145), /* JTAG */ + INTEL_GPP(0, 112, 135, 112), /* GPP_E */ + INTEL_GPP(1, 136, 145, 136), /* JTAG */ }; static const struct intel_padgroup ebg_community4_gpps[] = { - EBG_GPP(0, 146, 165), /* GPP_H */ - EBG_GPP(1, 166, 183), /* GPP_J */ + INTEL_GPP(0, 146, 165, 146), /* GPP_H */ + INTEL_GPP(1, 166, 183, 166), /* GPP_J */ }; static const struct intel_padgroup ebg_community5_gpps[] = { - EBG_GPP(0, 184, 207), /* GPP_I */ - EBG_GPP(1, 208, 225), /* GPP_L */ - EBG_GPP(2, 226, 243), /* GPP_M */ - EBG_GPP(3, 244, 261), /* GPP_N */ + INTEL_GPP(0, 184, 207, 184), /* GPP_I */ + INTEL_GPP(1, 208, 225, 208), /* GPP_L */ + INTEL_GPP(2, 226, 243, 226), /* GPP_M */ + INTEL_GPP(3, 244, 261, 244), /* GPP_N */ }; static const struct intel_community ebg_communities[] = { From dd0c7bffe3d1c03b5e191d648f0ccc17bffe37e3 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 11 Nov 2025 20:10:28 +0100 Subject: [PATCH 093/107] pinctrl: cherryview: Switch to INTEL_GPP() macro Replace custom macro with the recently defined INTEL_GPP(). Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-cherryview.c | 46 ++++++++++------------ 1 file changed, 20 insertions(+), 26 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 077fa1318aaf..f6c29bdc3103 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -92,12 +92,6 @@ struct intel_community_context { #define PINMODE(m, i) ((m) | ((i) * PINMODE_INVERT_OE)) -#define CHV_GPP(start, end) \ - { \ - .base = (start), \ - .size = (end) - (start) + 1, \ - } - #define CHV_COMMUNITY(g, i, a) \ { \ .gpps = (g), \ @@ -258,13 +252,13 @@ static const struct intel_function southwest_functions[] = { }; static const struct intel_padgroup southwest_gpps[] = { - CHV_GPP(0, 7), - CHV_GPP(15, 22), - CHV_GPP(30, 37), - CHV_GPP(45, 52), - CHV_GPP(60, 67), - CHV_GPP(75, 82), - CHV_GPP(90, 97), + INTEL_GPP(0, 0, 7, 0), + INTEL_GPP(1, 15, 22, 15), + INTEL_GPP(2, 30, 37, 30), + INTEL_GPP(3, 45, 52, 45), + INTEL_GPP(4, 60, 67, 60), + INTEL_GPP(5, 75, 82, 75), + INTEL_GPP(6, 90, 97, 90), }; /* @@ -354,11 +348,11 @@ static const struct pinctrl_pin_desc north_pins[] = { }; static const struct intel_padgroup north_gpps[] = { - CHV_GPP(0, 8), - CHV_GPP(15, 27), - CHV_GPP(30, 41), - CHV_GPP(45, 56), - CHV_GPP(60, 72), + INTEL_GPP(0, 0, 8, 0), + INTEL_GPP(1, 15, 27, 15), + INTEL_GPP(2, 30, 41, 30), + INTEL_GPP(3, 45, 56, 45), + INTEL_GPP(4, 60, 72, 60), }; /* @@ -406,8 +400,8 @@ static const struct pinctrl_pin_desc east_pins[] = { }; static const struct intel_padgroup east_gpps[] = { - CHV_GPP(0, 11), - CHV_GPP(15, 26), + INTEL_GPP(0, 0, 11, 0), + INTEL_GPP(1, 15, 26, 15), }; static const struct intel_community east_communities[] = { @@ -526,12 +520,12 @@ static const struct intel_function southeast_functions[] = { }; static const struct intel_padgroup southeast_gpps[] = { - CHV_GPP(0, 7), - CHV_GPP(15, 26), - CHV_GPP(30, 35), - CHV_GPP(45, 52), - CHV_GPP(60, 69), - CHV_GPP(75, 85), + INTEL_GPP(0, 0, 7, 0), + INTEL_GPP(1, 15, 26, 15), + INTEL_GPP(2, 30, 35, 30), + INTEL_GPP(3, 45, 52, 45), + INTEL_GPP(4, 60, 69, 60), + INTEL_GPP(5, 75, 85, 75), }; static const struct intel_community southeast_communities[] = { From cc4e46fa76afcb4fc56b801c9577dc60a64a00d6 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 11 Nov 2025 20:10:29 +0100 Subject: [PATCH 094/107] pinctrl: elkhartlake: Switch to INTEL_GPP() macro Replace custom macro with the recently defined INTEL_GPP(). Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-elkhartlake.c | 43 +++++++++------------ 1 file changed, 18 insertions(+), 25 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-elkhartlake.c b/drivers/pinctrl/intel/pinctrl-elkhartlake.c index ab414e07555a..0e8742f31cd4 100644 --- a/drivers/pinctrl/intel/pinctrl-elkhartlake.c +++ b/drivers/pinctrl/intel/pinctrl-elkhartlake.c @@ -21,13 +21,6 @@ #define EHL_GPI_IS 0x100 #define EHL_GPI_IE 0x120 -#define EHL_GPP(r, s, e) \ - { \ - .reg_num = (r), \ - .base = (s), \ - .size = ((e) - (s) + 1), \ - } - #define EHL_COMMUNITY(b, s, e, g) \ INTEL_COMMUNITY_GPPS(b, s, e, g, EHL) @@ -106,9 +99,9 @@ static const struct pinctrl_pin_desc ehl_community0_pins[] = { }; static const struct intel_padgroup ehl_community0_gpps[] = { - EHL_GPP(0, 0, 25), /* GPP_B */ - EHL_GPP(1, 26, 41), /* GPP_T */ - EHL_GPP(2, 42, 66), /* GPP_G */ + INTEL_GPP(0, 0, 25, 0), /* GPP_B */ + INTEL_GPP(1, 26, 41, 26), /* GPP_T */ + INTEL_GPP(2, 42, 66, 42), /* GPP_G */ }; static const struct intel_community ehl_community0[] = { @@ -245,11 +238,11 @@ static const struct pinctrl_pin_desc ehl_community1_pins[] = { }; static const struct intel_padgroup ehl_community1_gpps[] = { - EHL_GPP(0, 0, 15), /* GPP_V */ - EHL_GPP(1, 16, 39), /* GPP_H */ - EHL_GPP(2, 40, 60), /* GPP_D */ - EHL_GPP(3, 61, 84), /* GPP_U */ - EHL_GPP(4, 85, 112), /* vGPIO */ + INTEL_GPP(0, 0, 15, 0), /* GPP_V */ + INTEL_GPP(1, 16, 39, 16), /* GPP_H */ + INTEL_GPP(2, 40, 60, 40), /* GPP_D */ + INTEL_GPP(3, 61, 84, 61), /* GPP_U */ + INTEL_GPP(4, 85, 112, 85), /* vGPIO */ }; static const struct intel_community ehl_community1[] = { @@ -286,7 +279,7 @@ static const struct pinctrl_pin_desc ehl_community2_pins[] = { }; static const struct intel_padgroup ehl_community2_gpps[] = { - EHL_GPP(0, 0, 16), /* DSW */ + INTEL_GPP(0, 0, 16, 0), /* DSW */ }; static const struct intel_community ehl_community2[] = { @@ -356,10 +349,10 @@ static const struct pinctrl_pin_desc ehl_community3_pins[] = { }; static const struct intel_padgroup ehl_community3_gpps[] = { - EHL_GPP(0, 0, 16), /* CPU */ - EHL_GPP(1, 17, 18), /* GPP_S */ - EHL_GPP(2, 19, 42), /* GPP_A */ - EHL_GPP(3, 43, 46), /* vGPIO_3 */ + INTEL_GPP(0, 0, 16, 0), /* CPU */ + INTEL_GPP(1, 17, 18, 17), /* GPP_S */ + INTEL_GPP(2, 19, 42, 19), /* GPP_A */ + INTEL_GPP(3, 43, 46, 43), /* vGPIO_3 */ }; static const struct intel_community ehl_community3[] = { @@ -462,10 +455,10 @@ static const struct pinctrl_pin_desc ehl_community4_pins[] = { }; static const struct intel_padgroup ehl_community4_gpps[] = { - EHL_GPP(0, 0, 23), /* GPP_C */ - EHL_GPP(1, 24, 48), /* GPP_F */ - EHL_GPP(2, 49, 54), /* HVCMOS */ - EHL_GPP(3, 55, 79), /* GPP_E */ + INTEL_GPP(0, 0, 23, 0), /* GPP_C */ + INTEL_GPP(1, 24, 48, 24), /* GPP_F */ + INTEL_GPP(2, 49, 54, 49), /* HVCMOS */ + INTEL_GPP(3, 55, 79, 55), /* GPP_E */ }; static const struct intel_community ehl_community4[] = { @@ -493,7 +486,7 @@ static const struct pinctrl_pin_desc ehl_community5_pins[] = { }; static const struct intel_padgroup ehl_community5_gpps[] = { - EHL_GPP(0, 0, 7), /* GPP_R */ + INTEL_GPP(0, 0, 7, 0), /* GPP_R */ }; static const struct intel_community ehl_community5[] = { From f2596d9fa19c0910319fe8eb1ccdf6348f0e02db Mon Sep 17 00:00:00 2001 From: Chen Ni Date: Tue, 11 Nov 2025 14:29:44 +0800 Subject: [PATCH 095/107] pinctrl: airoha: convert comma to semicolon Replace comma between expressions with semicolons. Using a ',' in place of a ';' can have unintended side effects. Although that is not the case here, it is seems best to use ';' unless ',' is intended. Found by inspection. No functional change intended. Compile tested only. Signed-off-by: Chen Ni Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-airoha.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c index bfcedc7f920b..983d96fd399a 100644 --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c @@ -2892,12 +2892,12 @@ static int airoha_pinctrl_probe(struct platform_device *pdev) /* Init pinctrl desc struct */ pinctrl->desc.name = KBUILD_MODNAME; - pinctrl->desc.owner = THIS_MODULE, - pinctrl->desc.pctlops = &airoha_pctlops, - pinctrl->desc.pmxops = &airoha_pmxops, - pinctrl->desc.confops = &airoha_confops, - pinctrl->desc.pins = data->pins, - pinctrl->desc.npins = data->num_pins, + pinctrl->desc.owner = THIS_MODULE; + pinctrl->desc.pctlops = &airoha_pctlops; + pinctrl->desc.pmxops = &airoha_pmxops; + pinctrl->desc.confops = &airoha_confops; + pinctrl->desc.pins = data->pins; + pinctrl->desc.npins = data->num_pins; err = devm_pinctrl_register_and_init(dev, &pinctrl->desc, pinctrl, &pinctrl->ctrl); From 3b0cf6ab35909d7ac8d561e18159c62d42d914c2 Mon Sep 17 00:00:00 2001 From: John Madieu Date: Thu, 6 Nov 2025 09:07:58 +0100 Subject: [PATCH 096/107] pinctrl: renesas: rzg2l: Refactor OEN register PWPR handling Extract the OEN register write with PWPR protection logic into a helper function to eliminate code duplication between rzg2l_write_oen() and rzg2l_pinctrl_resume_noirq(). Introduce rzg2l_oen_write_with_pwpr() helper that encapsulates the PWPR unlock, OEN register write, and PWPR lock sequence. This helper must be called with pctrl->lock already held by the caller. Reported-by: Pavel Machek Closes: https://lore.kernel.org/cip-dev/OS9PR01MB16368C765305362F5F4132759FFC4A@OS9PR01MB16368.jpnprd01.prod.outlook.com/T/#u Signed-off-by: John Madieu Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251106080758.36645-1-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 53 +++++++++++++++---------- 1 file changed, 33 insertions(+), 20 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index f25ecada5c69..863e779dda02 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1112,13 +1112,37 @@ static int rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin) return !(readb(pctrl->base + pctrl->data->hwcfg->regs.oen) & BIT(bit)); } -static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) +/** + * rzg2l_oen_write_with_pwpr - Write to OEN register with PWPR protection + * @pctrl: pinctrl driver data + * @val: value to write to OEN register + * + * Writes to the OEN register, handling PWPR write protection if required + * by the hardware configuration. Must be called with pctrl->lock held. + */ +static void rzg2l_oen_write_with_pwpr(struct rzg2l_pinctrl *pctrl, u8 val) { const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; + u16 oen_offset = pctrl->data->hwcfg->regs.oen; + u8 pwpr; + + if (pctrl->data->hwcfg->oen_pwpr_lock) { + pwpr = readb(pctrl->base + regs->pwpr); + writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr); + } + + writeb(val, pctrl->base + oen_offset); + + if (pctrl->data->hwcfg->oen_pwpr_lock) + writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr); +} + +static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) +{ u16 oen_offset = pctrl->data->hwcfg->regs.oen; unsigned long flags; - u8 val, pwpr; int bit; + u8 val; if (!pctrl->data->pin_to_oen_bit) return -EOPNOTSUPP; @@ -1133,13 +1157,8 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oe val &= ~BIT(bit); else val |= BIT(bit); - if (pctrl->data->hwcfg->oen_pwpr_lock) { - pwpr = readb(pctrl->base + regs->pwpr); - writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr); - } - writeb(val, pctrl->base + oen_offset); - if (pctrl->data->hwcfg->oen_pwpr_lock) - writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr); + + rzg2l_oen_write_with_pwpr(pctrl, val); raw_spin_unlock_irqrestore(&pctrl->lock, flags); return 0; @@ -3200,7 +3219,6 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev) const struct rzg2l_register_offsets *regs = &hwcfg->regs; struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; unsigned long flags; - u8 pwpr; int ret; if (!atomic_read(&pctrl->wakeup_path)) { @@ -3210,16 +3228,11 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev) } writeb(cache->qspi, pctrl->base + QSPI); - if (pctrl->data->hwcfg->oen_pwpr_lock) { - raw_spin_lock_irqsave(&pctrl->lock, flags); - pwpr = readb(pctrl->base + regs->pwpr); - writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr); - } - writeb(cache->oen, pctrl->base + pctrl->data->hwcfg->regs.oen); - if (pctrl->data->hwcfg->oen_pwpr_lock) { - writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr); - raw_spin_unlock_irqrestore(&pctrl->lock, flags); - } + + raw_spin_lock_irqsave(&pctrl->lock, flags); + rzg2l_oen_write_with_pwpr(pctrl, cache->oen); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + for (u8 i = 0; i < 2; i++) { if (regs->sd_ch) writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); From 2f61c00972193d014185655e533a809d824cef47 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 18 Nov 2025 13:34:01 +0100 Subject: [PATCH 097/107] pinctrl: intel: Export intel_gpio_add_pin_ranges() Export intel_gpio_add_pin_ranges() for reuse in other drivers. Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-intel.c | 12 +++++++++++- drivers/pinctrl/intel/pinctrl-intel.h | 2 ++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 1e2f77d200f9..cf9db8ac0f42 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1345,7 +1345,16 @@ static int intel_gpio_irq_init_hw(struct gpio_chip *gc) return 0; } -static int intel_gpio_add_pin_ranges(struct gpio_chip *gc) +/** + * intel_gpio_add_pin_ranges - add GPIO pin ranges for all groups in all communities + * @gc: GPIO chip structure + * + * This function iterates over all communities and all groups and adds the respective + * GPIO pin ranges, so the GPIO library will correctly map a GPIO offset to a pin number. + * + * Return: 0, or negative error code if range can't be added. + */ +int intel_gpio_add_pin_ranges(struct gpio_chip *gc) { struct intel_pinctrl *pctrl = gpiochip_get_data(gc); const struct intel_community *community; @@ -1362,6 +1371,7 @@ static int intel_gpio_add_pin_ranges(struct gpio_chip *gc) return 0; } +EXPORT_SYMBOL_NS_GPL(intel_gpio_add_pin_ranges, "PINCTRL_INTEL"); static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl) { diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h index 654af5977603..c1520797f895 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.h +++ b/drivers/pinctrl/intel/pinctrl-intel.h @@ -276,6 +276,8 @@ extern const struct dev_pm_ops intel_pinctrl_pm_ops; const struct intel_community *intel_get_community(const struct intel_pinctrl *pctrl, unsigned int pin); +int intel_gpio_add_pin_ranges(struct gpio_chip *gc); + int intel_get_groups_count(struct pinctrl_dev *pctldev); const char *intel_get_group_name(struct pinctrl_dev *pctldev, unsigned int group); int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, From 3bcfd55bedfc62e73cc36395e77a67827116cfcd Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 18 Nov 2025 13:34:02 +0100 Subject: [PATCH 098/107] pinctrl: cherryview: Convert to use intel_gpio_add_pin_ranges() Driver is ready to use intel_gpio_add_pin_ranges() directly instead of custom approach. Convert it now. Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-cherryview.c | 20 +------------------- 1 file changed, 1 insertion(+), 19 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index f6c29bdc3103..8bd0c8512f78 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -1511,24 +1511,6 @@ static int chv_gpio_irq_init_hw(struct gpio_chip *chip) return 0; } -static int chv_gpio_add_pin_ranges(struct gpio_chip *chip) -{ - struct intel_pinctrl *pctrl = gpiochip_get_data(chip); - struct device *dev = pctrl->dev; - const struct intel_community *community = &pctrl->communities[0]; - const struct intel_padgroup *gpp; - int ret, i; - - for (i = 0; i < community->ngpps; i++) { - gpp = &community->gpps[i]; - ret = gpiochip_add_pin_range(chip, dev_name(dev), gpp->base, gpp->base, gpp->size); - if (ret) - return dev_err_probe(dev, ret, "failed to add GPIO pin range\n"); - } - - return 0; -} - static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq) { const struct intel_community *community = &pctrl->communities[0]; @@ -1542,7 +1524,7 @@ static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq) chip->ngpio = pctrl->soc->pins[pctrl->soc->npins - 1].number + 1; chip->label = dev_name(dev); - chip->add_pin_ranges = chv_gpio_add_pin_ranges; + chip->add_pin_ranges = intel_gpio_add_pin_ranges; chip->parent = dev; chip->base = -1; From f2bd5a0f59d052d16749bccf637690e51947a5d6 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sat, 15 Nov 2025 18:00:00 +0800 Subject: [PATCH 099/107] pinctrl: airoha: fix pinctrl function mismatch issue The blamed commit made the following changes: -#define PINCTRL_FUNC_DESC(id)... - .desc = PINCTRL_PINFUNCTION(#id, ... +#define PINCTRL_FUNC_DESC(id, table)... + .desc = PINCTRL_PINFUNCTION(#id, ... - PINCTRL_FUNC_DESC(pon)... + PINCTRL_FUNC_DESC("pon", pon)... It's clear that the id of funcs doesn't match the definition. Remove redundant #string from the definition to fix this issue: pinctrl-airoha ...: invalid function mdio in map table Fixes: 4043b0c45f85 ("pinctrl: airoha: generalize pins/group/function/confs handling") Signed-off-by: Chukun Pan Acked-by: Christian Marangi Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-airoha.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c index 983d96fd399a..2a5b9b6f08d9 100644 --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c @@ -35,7 +35,7 @@ #define PINCTRL_FUNC_DESC(id, table) \ { \ - .desc = PINCTRL_PINFUNCTION(#id, table##_groups, \ + .desc = PINCTRL_PINFUNCTION(id, table##_groups, \ ARRAY_SIZE(table##_groups)),\ .groups = table##_func_group, \ .group_size = ARRAY_SIZE(table##_func_group), \ From 0341d1b1ebf10bcbb9f35e174e83dbb21068387d Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Wed, 12 Nov 2025 11:44:30 -0700 Subject: [PATCH 100/107] pinctrl: airoha: Fix AIROHA_PINCTRL_CONFS_DRIVE_E2 in an7583_pinctrl_match_data Clang warns (or errors with CONFIG_WERROR=y / W=e): pinctrl/mediatek/pinctrl-airoha.c:2064:41: error: variable 'an7583_pinctrl_drive_e2_conf' is not needed and will not be emitted [-Werror,-Wunneeded-internal-declaration] 2064 | static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = { | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ Due to a typo, an7583_pinctrl_drive_e2_conf is only used within ARRAY_SIZE() (hence no instance of -Wunused-variable), which is evaluated at compile time, so it will not be needed in the final object file. Fix the .confs assignment for AIROHA_PINCTRL_CONFS_DRIVE_E2 in an7583_pinctrl_match_data to clear up the warning. Closes: https://github.com/ClangBuiltLinux/linux/issues/2142 Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs") Signed-off-by: Nathan Chancellor Acked-by: Christian Marangi Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-airoha.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c index 2a5b9b6f08d9..995ba6175c95 100644 --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c @@ -2993,7 +2993,7 @@ static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = { .num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf), }, [AIROHA_PINCTRL_CONFS_DRIVE_E2] = { - .confs = en7581_pinctrl_drive_e2_conf, + .confs = an7583_pinctrl_drive_e2_conf, .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf), }, [AIROHA_PINCTRL_CONFS_DRIVE_E4] = { From a7840365d179af3002912af76b46d1a3f450ba57 Mon Sep 17 00:00:00 2001 From: Jacky Chou Date: Mon, 17 Nov 2025 20:37:50 +0800 Subject: [PATCH 101/107] dt-bindings: pinctrl: aspeed,ast2600-pinctrl: Add PCIe RC PERST# group Add PCIe PERST# group to support for PCIe RC. Signed-off-by: Jacky Chou Acked-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml index 80974c46f3ef..af8979af9b45 100644 --- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml @@ -141,6 +141,7 @@ additionalProperties: - NRTS3 - NRTS4 - OSCCLK + - PCIERC1 - PEWAKE - PWM0 - PWM1 @@ -369,6 +370,7 @@ additionalProperties: - NRTS3 - NRTS4 - OSCCLK + - PCIERC1 - PEWAKE - PWM0 - PWM1 From da53dcd54cc35efa7a8236846bb39d40deeee034 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 18 Nov 2025 13:11:24 +0100 Subject: [PATCH 102/107] dt-bindings: pinctrl: cix,sky1-pinctrl: Drop duplicate newline Fix the following DT schema check warning: ./Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml:68:1: [warning] too many blank lines (2 > 1) (empty-lines) One newline is enough. No functional change. Signed-off-by: Marek Vasut Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml index 36977b0d745b..8ed53496c386 100644 --- a/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml @@ -65,7 +65,6 @@ patternProperties: enum: [ 2, 3, 5, 6, 8, 9, 11, 12, 13, 14, 17, 18, 20, 21, 23, 24 ] - required: - pinmux From ebd61482ffab499208f06b8d3fa183cbe2dd5fa7 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 24 Nov 2025 15:35:16 +0100 Subject: [PATCH 103/107] pinctrl: cix: Fix obscure dependency When compile-testing for UM-Linux the build fails because we don't have IOMEM. Add an explicit dependency. Fixes: 920500c5fe66 ("pinctrl: cix: Add pin-controller support for sky1") Reviewed-by: Peter Chen Signed-off-by: Linus Walleij --- drivers/pinctrl/cix/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/cix/Kconfig b/drivers/pinctrl/cix/Kconfig index 455120dd7318..1529b1af6388 100644 --- a/drivers/pinctrl/cix/Kconfig +++ b/drivers/pinctrl/cix/Kconfig @@ -9,6 +9,7 @@ config PINCTRL_SKY1_BASE config PINCTRL_SKY1 tristate "Cix Sky1 pinctrl driver" depends on ARCH_CIX || COMPILE_TEST + depends on HAS_IOMEM select PINCTRL_SKY1_BASE help Say Y here to enable the sky1 pinctrl driver From ac52b4a98509de3760919fa33e03384a5e770d7a Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 30 Nov 2025 17:14:45 +0100 Subject: [PATCH 104/107] MAINTAINERS: Change Linus Walleij mail address I will be using my kernel.org mail address going forward. There is no point in splitting this MAINTAINERS patch up per subsystem, I will just include it with the rest of my patches to pin control in the next merge window. Signed-off-by: Linus Walleij --- MAINTAINERS | 58 ++++++++++++++++++++++++++--------------------------- 1 file changed, 29 insertions(+), 29 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 181a58ec4a8d..13f61acdc8f7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -195,7 +195,7 @@ F: drivers/pinctrl/pinctrl-upboard.c F: include/linux/mfd/upboard-fpga.h AB8500 BATTERY AND CHARGER DRIVERS -M: Linus Walleij +M: Linus Walleij F: Documentation/devicetree/bindings/power/supply/*ab8500* F: drivers/power/supply/*ab8500* @@ -2045,7 +2045,7 @@ F: Documentation/devicetree/bindings/display/arm,hdlcd.yaml F: drivers/gpu/drm/arm/hdlcd_* ARM INTEGRATOR, VERSATILE AND REALVIEW SUPPORT -M: Linus Walleij +M: Linus Walleij L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/arm/arm,integrator.yaml @@ -2203,7 +2203,7 @@ F: Documentation/devicetree/bindings/memory-controllers/arm,pl35x-smc.yaml F: drivers/memory/pl353-smc.c ARM PRIMECELL SSP PL022 SPI DRIVER -M: Linus Walleij +M: Linus Walleij L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/spi/spi-pl022.yaml @@ -2216,7 +2216,7 @@ F: drivers/tty/serial/amba-pl01*.c F: include/linux/amba/serial.h ARM PRIMECELL VIC PL190/PL192 DRIVER -M: Linus Walleij +M: Linus Walleij L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/interrupt-controller/arm,vic.yaml @@ -2633,7 +2633,7 @@ F: tools/perf/util/cs-etm.* ARM/CORTINA SYSTEMS GEMINI ARM ARCHITECTURE M: Hans Ulli Kroll -M: Linus Walleij +M: Linus Walleij L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git https://github.com/ulli-kroll/linux.git @@ -3035,7 +3035,7 @@ F: include/dt-bindings/clock/mstar-* F: include/dt-bindings/gpio/msc313-gpio.h ARM/NOMADIK/Ux500 ARCHITECTURES -M: Linus Walleij +M: Linus Walleij L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik.git @@ -3732,7 +3732,7 @@ F: Documentation/devicetree/bindings/media/i2c/asahi-kasei,ak7375.yaml F: drivers/media/i2c/ak7375.c ASAHI KASEI AK8974 DRIVER -M: Linus Walleij +M: Linus Walleij L: linux-iio@vger.kernel.org S: Supported W: http://www.akm.com/ @@ -6758,7 +6758,7 @@ S: Maintained F: drivers/pinctrl/pinctrl-cy8c95x0.c CYPRESS CY8CTMA140 TOUCHSCREEN DRIVER -M: Linus Walleij +M: Linus Walleij L: linux-input@vger.kernel.org S: Maintained F: drivers/input/touchscreen/cy8ctma140.c @@ -6778,13 +6778,13 @@ Q: http://patchwork.linuxtv.org/project/linux-media/list/ F: drivers/media/common/cypress_firmware* CYTTSP TOUCHSCREEN DRIVER -M: Linus Walleij +M: Linus Walleij L: linux-input@vger.kernel.org S: Maintained F: drivers/input/touchscreen/cyttsp* D-LINK DIR-685 TOUCHKEYS DRIVER -M: Linus Walleij +M: Linus Walleij L: linux-input@vger.kernel.org S: Supported F: drivers/input/keyboard/dlink-dir685-touchkeys.c @@ -7653,13 +7653,13 @@ T: git https://gitlab.freedesktop.org/drm/misc/kernel.git F: drivers/gpu/drm/tiny/appletbdrm.c DRM DRIVER FOR ARM PL111 CLCD -M: Linus Walleij +M: Linus Walleij S: Maintained T: git https://gitlab.freedesktop.org/drm/misc/kernel.git F: drivers/gpu/drm/pl111/ DRM DRIVER FOR ARM VERSATILE TFT PANELS -M: Linus Walleij +M: Linus Walleij S: Maintained T: git https://gitlab.freedesktop.org/drm/misc/kernel.git F: Documentation/devicetree/bindings/display/panel/arm,versatile-tft-panel.yaml @@ -7709,7 +7709,7 @@ F: Documentation/devicetree/bindings/display/panel/ebbg,ft8719.yaml F: drivers/gpu/drm/panel/panel-ebbg-ft8719.c DRM DRIVER FOR FARADAY TVE200 TV ENCODER -M: Linus Walleij +M: Linus Walleij S: Maintained T: git https://gitlab.freedesktop.org/drm/misc/kernel.git F: drivers/gpu/drm/tve200/ @@ -7903,14 +7903,14 @@ F: include/dt-bindings/clock/qcom,dsi-phy-28nm.h F: include/uapi/drm/msm_drm.h DRM DRIVER FOR NOVATEK NT35510 PANELS -M: Linus Walleij +M: Linus Walleij S: Maintained T: git https://gitlab.freedesktop.org/drm/misc/kernel.git F: Documentation/devicetree/bindings/display/panel/novatek,nt35510.yaml F: drivers/gpu/drm/panel/panel-novatek-nt35510.c DRM DRIVER FOR NOVATEK NT35560 PANELS -M: Linus Walleij +M: Linus Walleij S: Maintained T: git https://gitlab.freedesktop.org/drm/misc/kernel.git F: Documentation/devicetree/bindings/display/panel/sony,acx424akp.yaml @@ -8028,7 +8028,7 @@ F: Documentation/devicetree/bindings/display/panel/raydium,rm67191.yaml F: drivers/gpu/drm/panel/panel-raydium-rm67191.c DRM DRIVER FOR SAMSUNG DB7430 PANELS -M: Linus Walleij +M: Linus Walleij S: Maintained T: git https://gitlab.freedesktop.org/drm/misc/kernel.git F: Documentation/devicetree/bindings/display/panel/samsung,lms397kf04.yaml @@ -8112,7 +8112,7 @@ F: Documentation/devicetree/bindings/display/solomon,ssd13*.yaml F: drivers/gpu/drm/solomon/ssd130x* DRM DRIVER FOR ST-ERICSSON MCDE -M: Linus Walleij +M: Linus Walleij S: Maintained T: git https://gitlab.freedesktop.org/drm/misc/kernel.git F: Documentation/devicetree/bindings/display/ste,mcde.yaml @@ -8144,7 +8144,7 @@ F: Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml F: drivers/gpu/drm/bridge/ti-sn65dsi86.c DRM DRIVER FOR TPO TPG110 PANELS -M: Linus Walleij +M: Linus Walleij S: Maintained T: git https://gitlab.freedesktop.org/drm/misc/kernel.git F: Documentation/devicetree/bindings/display/panel/tpo,tpg110.yaml @@ -8188,7 +8188,7 @@ F: drivers/gpu/drm/vmwgfx/ F: include/uapi/drm/vmwgfx_drm.h DRM DRIVER FOR WIDECHIPS WS2401 PANELS -M: Linus Walleij +M: Linus Walleij S: Maintained T: git https://gitlab.freedesktop.org/drm/misc/kernel.git F: Documentation/devicetree/bindings/display/panel/samsung,lms380kf01.yaml @@ -9482,7 +9482,7 @@ F: include/linux/fanotify.h F: include/uapi/linux/fanotify.h FARADAY FOTG210 USB2 DUAL-ROLE CONTROLLER -M: Linus Walleij +M: Linus Walleij L: linux-usb@vger.kernel.org S: Maintained F: drivers/usb/fotg210/ @@ -10669,7 +10669,7 @@ F: drivers/gpio/gpio-sloppy-logic-analyzer.c F: tools/gpio/gpio-sloppy-logic-analyzer.sh GPIO SUBSYSTEM -M: Linus Walleij +M: Linus Walleij M: Bartosz Golaszewski L: linux-gpio@vger.kernel.org S: Maintained @@ -13033,7 +13033,7 @@ F: Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml F: drivers/iio/imu/inv_icm42600/ INVENSENSE MPU-3050 GYROSCOPE DRIVER -M: Linus Walleij +M: Linus Walleij L: linux-iio@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/iio/gyroscope/invensense,mpu3050.yaml @@ -13948,7 +13948,7 @@ F: drivers/auxdisplay/ks0108.c F: include/linux/ks0108.h KTD253 BACKLIGHT DRIVER -M: Linus Walleij +M: Linus Walleij S: Maintained F: Documentation/devicetree/bindings/leds/backlight/kinetic,ktd253.yaml F: drivers/video/backlight/ktd253-backlight.c @@ -14159,7 +14159,7 @@ F: drivers/ata/pata_arasan_cf.c F: include/linux/pata_arasan_cf_data.h LIBATA PATA FARADAY FTIDE010 AND GEMINI SATA BRIDGE DRIVERS -M: Linus Walleij +M: Linus Walleij L: linux-ide@vger.kernel.org S: Maintained F: drivers/ata/pata_ftide010.c @@ -19663,7 +19663,7 @@ F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml F: drivers/pci/controller/dwc/*imx6* PCI DRIVER FOR INTEL IXP4XX -M: Linus Walleij +M: Linus Walleij S: Maintained F: Documentation/devicetree/bindings/pci/intel,ixp4xx-pci.yaml F: drivers/pci/controller/pci-ixp4xx.c @@ -19774,7 +19774,7 @@ F: drivers/pci/controller/cadence/pci-j721e.c F: drivers/pci/controller/dwc/pci-dra7xx.c PCI DRIVER FOR V3 SEMICONDUCTOR V360EPC -M: Linus Walleij +M: Linus Walleij L: linux-pci@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/pci/v3,v360epc-pci.yaml @@ -20219,7 +20219,7 @@ K: (?i)clone3 K: \b(clone_args|kernel_clone_args)\b PIN CONTROL SUBSYSTEM -M: Linus Walleij +M: Linus Walleij L: linux-gpio@vger.kernel.org S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git @@ -21631,7 +21631,7 @@ F: Documentation/devicetree/bindings/watchdog/realtek,otto-wdt.yaml F: drivers/watchdog/realtek_otto_wdt.c REALTEK RTL83xx SMI DSA ROUTER CHIPS -M: Linus Walleij +M: Linus Walleij M: Alvin Šipraga S: Maintained F: Documentation/devicetree/bindings/net/dsa/realtek.yaml @@ -23384,7 +23384,7 @@ S: Supported F: net/smc/ SHARP GP2AP002A00F/GP2AP002S00F SENSOR DRIVER -M: Linus Walleij +M: Linus Walleij L: linux-iio@vger.kernel.org S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio.git From 61d1bb53547d42c6bdaec9da4496beb3a1a05264 Mon Sep 17 00:00:00 2001 From: Haotian Zhang Date: Wed, 3 Dec 2025 14:13:47 +0800 Subject: [PATCH 105/107] pinctrl: single: Fix incorrect type for error return variable pcs_pinconf_get() and pcs_pinconf_set() declare ret as unsigned int, but assign it the return values of pcs_get_function() that may return negative error codes. This causes negative error codes to be converted to large positive values. Change ret from unsigned int to int in both functions. Fixes: 9dddb4df90d1 ("pinctrl: single: support generic pinconf") Signed-off-by: Haotian Zhang Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-single.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 6d580aa282ec..998f23d6c317 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -485,7 +485,8 @@ static int pcs_pinconf_get(struct pinctrl_dev *pctldev, struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); struct pcs_function *func; enum pin_config_param param; - unsigned offset = 0, data = 0, i, j, ret; + unsigned offset = 0, data = 0, i, j; + int ret; ret = pcs_get_function(pctldev, pin, &func); if (ret) @@ -549,9 +550,9 @@ static int pcs_pinconf_set(struct pinctrl_dev *pctldev, { struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); struct pcs_function *func; - unsigned offset = 0, shift = 0, i, data, ret; + unsigned offset = 0, shift = 0, i, data; u32 arg; - int j; + int j, ret; enum pin_config_param param; ret = pcs_get_function(pctldev, pin, &func); From 9dc966799ac9a2573d970080334a801fcc283a1b Mon Sep 17 00:00:00 2001 From: Ali Tariq Date: Sun, 26 Oct 2025 11:42:40 +0000 Subject: [PATCH 106/107] pinctrl: starfive: use dynamic GPIO base allocation The JH7110 pinctrl driver currently sets a static GPIO base number from platform data: sfp->gc.base = info->gc_base; Static base assignment is deprecated and results in the following warning: gpio gpiochip0: Static allocation of GPIO base is deprecated, use dynamic allocation. Set `sfp->gc.base = -1` to let the GPIO core dynamically allocate the base number. This removes the warning and aligns the driver with current GPIO guidelines. Since the GPIO base is now allocated dynamically, remove `gc_base` field in `struct jh7110_pinctrl_soc_info` and the associated `JH7110_SYS_GC_BASE` and `JH7110_AON_GC_BASE` constants as they are no longer used anywhere in the driver. Tested on VisionFive 2 (JH7110 SoC). Signed-off-by: Ali Tariq Reviewed-by: Emil Renner Berthing Reviewed-by: Bartosz Golaszewski Signed-off-by: Linus Walleij --- drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c | 2 -- drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c | 2 -- drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c | 2 +- drivers/pinctrl/starfive/pinctrl-starfive-jh7110.h | 1 - 4 files changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c index cf42e204cbf0..3433b3c91692 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c @@ -29,7 +29,6 @@ #include "pinctrl-starfive-jh7110.h" #define JH7110_AON_NGPIO 4 -#define JH7110_AON_GC_BASE 64 #define JH7110_AON_REGS_NUM 37 @@ -138,7 +137,6 @@ static const struct jh7110_pinctrl_soc_info jh7110_aon_pinctrl_info = { .pins = jh7110_aon_pins, .npins = ARRAY_SIZE(jh7110_aon_pins), .ngpios = JH7110_AON_NGPIO, - .gc_base = JH7110_AON_GC_BASE, .dout_reg_base = JH7110_AON_DOUT, .dout_mask = GENMASK(3, 0), .doen_reg_base = JH7110_AON_DOEN, diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c index 03c2ad808d61..9b67063a0b0b 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c @@ -29,7 +29,6 @@ #include "pinctrl-starfive-jh7110.h" #define JH7110_SYS_NGPIO 64 -#define JH7110_SYS_GC_BASE 0 #define JH7110_SYS_REGS_NUM 174 @@ -410,7 +409,6 @@ static const struct jh7110_pinctrl_soc_info jh7110_sys_pinctrl_info = { .pins = jh7110_sys_pins, .npins = ARRAY_SIZE(jh7110_sys_pins), .ngpios = JH7110_SYS_NGPIO, - .gc_base = JH7110_SYS_GC_BASE, .dout_reg_base = JH7110_SYS_DOUT, .dout_mask = GENMASK(6, 0), .doen_reg_base = JH7110_SYS_DOEN, diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c index 05e3af75b09f..eb5cf8c067d1 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c @@ -938,7 +938,7 @@ int jh7110_pinctrl_probe(struct platform_device *pdev) sfp->gc.set = jh7110_gpio_set; sfp->gc.set_config = jh7110_gpio_set_config; sfp->gc.add_pin_ranges = jh7110_gpio_add_pin_ranges; - sfp->gc.base = info->gc_base; + sfp->gc.base = -1; sfp->gc.ngpio = info->ngpios; jh7110_irq_chip.name = sfp->gc.label; diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.h b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.h index a33d0d4e1382..2da2d6858008 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.h +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.h @@ -38,7 +38,6 @@ struct jh7110_pinctrl_soc_info { const struct pinctrl_pin_desc *pins; unsigned int npins; unsigned int ngpios; - unsigned int gc_base; /* gpio dout/doen/din/gpioinput register */ unsigned int dout_reg_base; From 666065caa31aeb812978740bae21871067bb14b6 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 4 Dec 2025 10:50:14 +0100 Subject: [PATCH 107/107] pinctrl: add CONFIG_OF dependencies for microchip drivers The two newly added drivers fail to link on builds without CONFIG_OF: x86_64-linux-ld: drivers/pinctrl/pinctrl-pic64gx-gpio2.o: in function `pinconf_generic_dt_node_to_map_all': pinctrl-pic64gx-gpio2.c:(.text+0xc9): undefined reference to `pinconf_generic_dt_node_to_map' x86_64-linux-ld: drivers/pinctrl/pinctrl-mpfs-iomux0.o: in function `pinconf_generic_dt_node_to_map_all': pinctrl-mpfs-iomux0.c:(.text+0xc9): undefined reference to `pinconf_generic_dt_node_to_map' Add a Kconfig dependencies. Fixes: 38cf9d641314 ("pinctrl: add pic64gx "gpio2" pinmux driver") Fixes: 46397274da22 ("pinctrl: add polarfire soc iomux0 pinmux driver") Signed-off-by: Arnd Bergmann Acked-by: Conor Dooley Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 2e590913fa44..bc7f37afc48b 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -489,6 +489,7 @@ config PINCTRL_PIC32MZDA config PINCTRL_PIC64GX bool "pic64gx gpio2 pinctrl driver" depends on ARCH_MICROCHIP || COMPILE_TEST + depends on OF select GENERIC_PINCONF default y help @@ -508,6 +509,7 @@ config PINCTRL_PISTACHIO config PINCTRL_POLARFIRE_SOC bool "Polarfire SoC pinctrl driver" depends on ARCH_MICROCHIP || COMPILE_TEST + depends on OF select GENERIC_PINCONF default y help