From c6005d4dd216a5eb0837432511cc87c9a19c5c9e Mon Sep 17 00:00:00 2001 From: Joshua Yeong Date: Wed, 15 May 2024 13:02:53 +0800 Subject: [PATCH 1/4] dt-bindings: cache: Add docs for StarFive Starlink cache controller Add DT binding documentation used by StarFive's Starlink cache controller. Signed-off-by: Joshua Yeong Reviewed-by: Rob Herring (Arm) Signed-off-by: Conor Dooley --- .../cache/starfive,jh8100-starlink-cache.yaml | 66 +++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 Documentation/devicetree/bindings/cache/starfive,jh8100-starlink-cache.yaml diff --git a/Documentation/devicetree/bindings/cache/starfive,jh8100-starlink-cache.yaml b/Documentation/devicetree/bindings/cache/starfive,jh8100-starlink-cache.yaml new file mode 100644 index 000000000000..6d61098e388b --- /dev/null +++ b/Documentation/devicetree/bindings/cache/starfive,jh8100-starlink-cache.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/starfive,jh8100-starlink-cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive StarLink Cache Controller + +maintainers: + - Joshua Yeong + +description: + StarFive's StarLink Cache Controller manages the L3 cache shared between + clusters of CPU cores. The cache driver enables RISC-V non-standard cache + management as an alternative to instructions in the RISC-V Zicbom extension. + +allOf: + - $ref: /schemas/cache-controller.yaml# + +# We need a select here so we don't match all nodes with 'cache' +select: + properties: + compatible: + contains: + enum: + - starfive,jh8100-starlink-cache + + required: + - compatible + +properties: + compatible: + items: + - const: starfive,jh8100-starlink-cache + - const: cache + + reg: + maxItems: 1 + +unevaluatedProperties: false + +required: + - compatible + - reg + - cache-block-size + - cache-level + - cache-sets + - cache-size + - cache-unified + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + cache-controller@15000000 { + compatible = "starfive,jh8100-starlink-cache", "cache"; + reg = <0x0 0x15000000 0x0 0x278>; + cache-block-size = <64>; + cache-level = <3>; + cache-sets = <8192>; + cache-size = <0x400000>; + cache-unified; + }; + }; From cabff60ca77da6cb460988e2af40bde95776d92b Mon Sep 17 00:00:00 2001 From: Joshua Yeong Date: Wed, 15 May 2024 13:02:52 +0800 Subject: [PATCH 2/4] cache: Add StarFive StarLink cache management Add StarFive Starlink cache management driver. The driver enables RISC-V non-standard cache operation on SoC that does not support Zicbom extension instructions. Signed-off-by: Joshua Yeong Signed-off-by: Conor Dooley --- drivers/cache/Kconfig | 9 ++ drivers/cache/Makefile | 5 +- drivers/cache/starfive_starlink_cache.c | 130 ++++++++++++++++++++++++ 3 files changed, 142 insertions(+), 2 deletions(-) create mode 100644 drivers/cache/starfive_starlink_cache.c diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig index 9345ce4976d7..94abd8f632a7 100644 --- a/drivers/cache/Kconfig +++ b/drivers/cache/Kconfig @@ -14,4 +14,13 @@ config SIFIVE_CCACHE help Support for the composable cache controller on SiFive platforms. +config STARFIVE_STARLINK_CACHE + bool "StarFive StarLink Cache controller" + depends on RISCV + depends on ARCH_STARFIVE + select RISCV_DMA_NONCOHERENT + select RISCV_NONSTANDARD_CACHE_OPS + help + Support for the StarLink cache controller IP from StarFive. + endmenu diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile index 7657cff3bd6c..55c5e851034d 100644 --- a/drivers/cache/Makefile +++ b/drivers/cache/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_AX45MP_L2_CACHE) += ax45mp_cache.o -obj-$(CONFIG_SIFIVE_CCACHE) += sifive_ccache.o +obj-$(CONFIG_AX45MP_L2_CACHE) += ax45mp_cache.o +obj-$(CONFIG_SIFIVE_CCACHE) += sifive_ccache.o +obj-$(CONFIG_STARFIVE_STARLINK_CACHE) += starfive_starlink_cache.o diff --git a/drivers/cache/starfive_starlink_cache.c b/drivers/cache/starfive_starlink_cache.c new file mode 100644 index 000000000000..24c7d078ca22 --- /dev/null +++ b/drivers/cache/starfive_starlink_cache.c @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Cache Management Operations for StarFive's Starlink cache controller + * + * Copyright (C) 2024 Shanghai StarFive Technology Co., Ltd. + * + * Author: Joshua Yeong + */ + +#include +#include +#include +#include + +#include + +#define STARLINK_CACHE_FLUSH_START_ADDR 0x0 +#define STARLINK_CACHE_FLUSH_END_ADDR 0x8 +#define STARLINK_CACHE_FLUSH_CTL 0x10 +#define STARLINK_CACHE_ALIGN 0x40 + +#define STARLINK_CACHE_ADDRESS_RANGE_MASK GENMASK(39, 0) +#define STARLINK_CACHE_FLUSH_CTL_MODE_MASK GENMASK(2, 1) +#define STARLINK_CACHE_FLUSH_CTL_ENABLE_MASK BIT(0) + +#define STARLINK_CACHE_FLUSH_CTL_CLEAN_INVALIDATE 0 +#define STARLINK_CACHE_FLUSH_CTL_MAKE_INVALIDATE 1 +#define STARLINK_CACHE_FLUSH_CTL_CLEAN_SHARED 2 +#define STARLINK_CACHE_FLUSH_POLL_DELAY_US 1 +#define STARLINK_CACHE_FLUSH_TIMEOUT_US 5000000 + +static void __iomem *starlink_cache_base; + +static void starlink_cache_flush_complete(void) +{ + volatile void __iomem *ctl = starlink_cache_base + STARLINK_CACHE_FLUSH_CTL; + u64 v; + int ret; + + ret = readq_poll_timeout_atomic(ctl, v, !(v & STARLINK_CACHE_FLUSH_CTL_ENABLE_MASK), + STARLINK_CACHE_FLUSH_POLL_DELAY_US, + STARLINK_CACHE_FLUSH_TIMEOUT_US); + if (ret) + WARN(1, "StarFive Starlink cache flush operation timeout\n"); +} + +static void starlink_cache_dma_cache_wback(phys_addr_t paddr, unsigned long size) +{ + writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr), + starlink_cache_base + STARLINK_CACHE_FLUSH_START_ADDR); + writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr + size), + starlink_cache_base + STARLINK_CACHE_FLUSH_END_ADDR); + + mb(); + writeq(FIELD_PREP(STARLINK_CACHE_FLUSH_CTL_MODE_MASK, + STARLINK_CACHE_FLUSH_CTL_CLEAN_SHARED), + starlink_cache_base + STARLINK_CACHE_FLUSH_CTL); + + starlink_cache_flush_complete(); +} + +static void starlink_cache_dma_cache_invalidate(phys_addr_t paddr, unsigned long size) +{ + writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr), + starlink_cache_base + STARLINK_CACHE_FLUSH_START_ADDR); + writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr + size), + starlink_cache_base + STARLINK_CACHE_FLUSH_END_ADDR); + + mb(); + writeq(FIELD_PREP(STARLINK_CACHE_FLUSH_CTL_MODE_MASK, + STARLINK_CACHE_FLUSH_CTL_MAKE_INVALIDATE), + starlink_cache_base + STARLINK_CACHE_FLUSH_CTL); + + starlink_cache_flush_complete(); +} + +static void starlink_cache_dma_cache_wback_inv(phys_addr_t paddr, unsigned long size) +{ + writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr), + starlink_cache_base + STARLINK_CACHE_FLUSH_START_ADDR); + writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr + size), + starlink_cache_base + STARLINK_CACHE_FLUSH_END_ADDR); + + mb(); + writeq(FIELD_PREP(STARLINK_CACHE_FLUSH_CTL_MODE_MASK, + STARLINK_CACHE_FLUSH_CTL_CLEAN_INVALIDATE), + starlink_cache_base + STARLINK_CACHE_FLUSH_CTL); + + starlink_cache_flush_complete(); +} + +static const struct riscv_nonstd_cache_ops starlink_cache_ops = { + .wback = &starlink_cache_dma_cache_wback, + .inv = &starlink_cache_dma_cache_invalidate, + .wback_inv = &starlink_cache_dma_cache_wback_inv, +}; + +static const struct of_device_id starlink_cache_ids[] = { + { .compatible = "starfive,jh8100-starlink-cache" }, + { /* sentinel */ } +}; + +static int __init starlink_cache_init(void) +{ + struct device_node *np; + u32 block_size; + int ret; + + np = of_find_matching_node(NULL, starlink_cache_ids); + if (!of_device_is_available(np)) + return -ENODEV; + + ret = of_property_read_u32(np, "cache-block-size", &block_size); + if (ret) + return ret; + + if (block_size % STARLINK_CACHE_ALIGN) + return -EINVAL; + + starlink_cache_base = of_iomap(np, 0); + if (!starlink_cache_base) + return -ENOMEM; + + riscv_cbom_block_size = block_size; + riscv_noncoherent_supported(); + riscv_noncoherent_register_cache_ops(&starlink_cache_ops); + + return 0; +} +arch_initcall(starlink_cache_init); From 4ca47d8bcca09af570e7133dbdf550980c86ca7b Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Wed, 26 Jun 2024 16:54:17 +0100 Subject: [PATCH 3/4] MAINTAINERS: add cache binding directory to cache driver entry The directory covering cache controller bindings has no MAINTAINER other than the fallback to myself, Rob and Krzysztof. Add it to the entry for the corresponding drivers. Acked-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index d6c90161c7bf..ade3d3491c19 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21286,6 +21286,7 @@ M: Conor Dooley L: linux-riscv@lists.infradead.org S: Maintained T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ +F: Documentation/devicetree/bindings/cache/ F: drivers/cache STARFIRE/DURALAN NETWORK DRIVER From 3d41249c1dee0fa22ebd8d27aa0a280edf943a0e Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Wed, 26 Jun 2024 16:54:16 +0100 Subject: [PATCH 4/4] MAINTAINERS: add microchip soc binding directory to microchip soc driver entry I noticed that there's technically not an explicit maintainer for this directory, even if the files currently in it are covered by either the Mircochip FPGA or AT91 entries. Add it to the entry covering the corresponding driver directory. Acked-by: Nicolas Ferre Acked-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index ade3d3491c19..bb2addcf836a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14850,6 +14850,7 @@ MICROCHIP SOC DRIVERS M: Conor Dooley S: Supported T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ +F: Documentation/devicetree/bindings/soc/microchip/ F: drivers/soc/microchip/ MICROCHIP SPI DRIVER