From f973bfa075cc05a891cfb0ac44212aa2a27ac54f Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Fri, 23 Jun 2017 09:21:41 -0500 Subject: [PATCH 1/5] arm64: dts: stratix10: fix up the gic register for the Stratix10 platform The register entries for the ARM GIC-400 should have a 2nd set of address. Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index c2b9bcb0ef61..631e09aa1b48 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -75,10 +75,10 @@ intc: intc@fffc1000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; interrupt-controller; - reg = <0x0 0xfffc1000 0x1000>, - <0x0 0xfffc2000 0x2000>, - <0x0 0xfffc4000 0x2000>, - <0x0 0xfffc6000 0x2000>; + reg = <0x0 0xfffc1000 0x0 0x1000>, + <0x0 0xfffc2000 0x0 0x2000>, + <0x0 0xfffc4000 0x0 0x2000>, + <0x0 0xfffc6000 0x0 0x2000>; }; soc { From 701e3a48772bae0f1181a7bb3ea7e23f17c03a82 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Fri, 8 Sep 2017 10:14:18 -0500 Subject: [PATCH 2/5] arm64: dts: stratix10: add ethernet/sdmmc support to the S10 devkit Enable ethernet and sdmmc support on the Stratix10 devkit. Signed-off-by: Dinh Nguyen --- v2: Create a separate PHY node --- .../dts/altera/socfpga_stratix10_socdk.dts | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index 41ea2dba2fce..590758613677 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -34,6 +34,44 @@ memory { }; }; +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + + max-frame-size = <3800>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <4>; + + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <1860>; /* 960ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + }; + }; +}; + +&mmc { + status = "okay"; + num-slots = <1>; + cap-sd-highspeed; + broken-cd; + bus-width = <4>; +}; + &uart0 { status = "okay"; }; From e519922e30fb59f33766b49e3af67931be2858a6 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Wed, 20 Sep 2017 12:11:27 -0500 Subject: [PATCH 3/5] arm64: dts: stratix10: include the reset manager bindings Add the reset manager includes for Stratix10. Need to use the '#include' instead of '/include/' to avoid a DTC syntax error. Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 1 + arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 631e09aa1b48..f7fbc38d8fa6 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -15,6 +15,7 @@ */ /dts-v1/; +#include / { compatible = "altr,socfpga-stratix10"; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index 590758613677..46f27edaa08e 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -14,7 +14,7 @@ * this program. If not, see . */ -/include/ "socfpga_stratix10.dtsi" +#include "socfpga_stratix10.dtsi" / { model = "SoCFPGA Stratix 10 SoCDK"; From 7691d62689d3bee3db12251a51adc5a5acfef220 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Wed, 20 Sep 2017 12:31:55 -0500 Subject: [PATCH 4/5] arm64: dts: stratix10: add the 'altr,modrst-off' property Update the Stratix10 reset manager with the 'altr,modrst-offset' property. Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index f7fbc38d8fa6..99e2afec0329 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -224,6 +224,7 @@ rst: rstmgr@ffd11000 { #reset-cells = <1>; compatible = "altr,rst-mgr"; reg = <0xffd11000 0x1000>; + altr,modrst-offset = <0x20>; }; spi0: spi@ffda4000 { From 788251fa08118efa934ba2f54989997e7a5be679 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Wed, 20 Sep 2017 16:36:02 -0500 Subject: [PATCH 5/5] arm64: dts: stratix10: add reset property for various peripherals Add reset property for emac, gpio, i2c, sdmmc, timers, and watchdog. Signed-off-by: Dinh Nguyen --- .../boot/dts/altera/socfpga_stratix10.dtsi | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 99e2afec0329..6804936f2459 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -101,6 +101,8 @@ gmac0: ethernet@ff800000 { interrupts = <0 90 4>; interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; + resets = <&rst EMAC0_RESET>; + reset-names = "stmmaceth"; status = "disabled"; }; @@ -110,6 +112,8 @@ gmac1: ethernet@ff802000 { interrupts = <0 91 4>; interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; + resets = <&rst EMAC1_RESET>; + reset-names = "stmmaceth"; status = "disabled"; }; @@ -119,6 +123,8 @@ gmac2: ethernet@ff804000 { interrupts = <0 92 4>; interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; + resets = <&rst EMAC2_RESET>; + reset-names = "stmmaceth"; status = "disabled"; }; @@ -127,6 +133,7 @@ gpio0: gpio@ffc03200 { #size-cells = <0>; compatible = "snps,dw-apb-gpio"; reg = <0xffc03200 0x100>; + resets = <&rst GPIO0_RESET>; status = "disabled"; porta: gpio-controller@0 { @@ -146,6 +153,7 @@ gpio1: gpio@ffc03300 { #size-cells = <0>; compatible = "snps,dw-apb-gpio"; reg = <0xffc03300 0x100>; + resets = <&rst GPIO1_RESET>; status = "disabled"; portb: gpio-controller@0 { @@ -166,6 +174,7 @@ i2c0: i2c@ffc02800 { compatible = "snps,designware-i2c"; reg = <0xffc02800 0x100>; interrupts = <0 103 4>; + resets = <&rst I2C0_RESET>; status = "disabled"; }; @@ -175,6 +184,7 @@ i2c1: i2c@ffc02900 { compatible = "snps,designware-i2c"; reg = <0xffc02900 0x100>; interrupts = <0 104 4>; + resets = <&rst I2C1_RESET>; status = "disabled"; }; @@ -184,6 +194,7 @@ i2c2: i2c@ffc02a00 { compatible = "snps,designware-i2c"; reg = <0xffc02a00 0x100>; interrupts = <0 105 4>; + resets = <&rst I2C2_RESET>; status = "disabled"; }; @@ -193,6 +204,7 @@ i2c3: i2c@ffc02b00 { compatible = "snps,designware-i2c"; reg = <0xffc02b00 0x100>; interrupts = <0 106 4>; + resets = <&rst I2C3_RESET>; status = "disabled"; }; @@ -202,6 +214,7 @@ i2c4: i2c@ffc02c00 { compatible = "snps,designware-i2c"; reg = <0xffc02c00 0x100>; interrupts = <0 107 4>; + resets = <&rst I2C4_RESET>; status = "disabled"; }; @@ -212,6 +225,8 @@ mmc: dwmmc0@ff808000 { reg = <0xff808000 0x1000>; interrupts = <0 96 4>; fifo-depth = <0x400>; + resets = <&rst SDMMC_RESET>; + reset-names = "reset"; status = "disabled"; }; @@ -293,6 +308,7 @@ uart0: serial0@ffc02000 { interrupts = <0 108 4>; reg-shift = <2>; reg-io-width = <4>; + resets = <&rst UART0_RESET>; status = "disabled"; }; @@ -302,6 +318,7 @@ uart1: serial1@ffc02100 { interrupts = <0 109 4>; reg-shift = <2>; reg-io-width = <4>; + resets = <&rst UART1_RESET>; status = "disabled"; }; @@ -317,6 +334,8 @@ usb0: usb@ffb00000 { interrupts = <0 93 4>; phys = <&usbphy0>; phy-names = "usb2-phy"; + resets = <&rst USB0_RESET>; + reset-names = "dwc2"; status = "disabled"; }; @@ -326,6 +345,8 @@ usb1: usb@ffb40000 { interrupts = <0 94 4>; phys = <&usbphy0>; phy-names = "usb2-phy"; + resets = <&rst USB1_RESET>; + reset-names = "dwc2"; status = "disabled"; }; @@ -333,6 +354,7 @@ watchdog0: watchdog@ffd00200 { compatible = "snps,dw-wdt"; reg = <0xffd00200 0x100>; interrupts = <0 117 4>; + resets = <&rst WATCHDOG0_RESET>; status = "disabled"; }; @@ -340,6 +362,7 @@ watchdog1: watchdog@ffd00300 { compatible = "snps,dw-wdt"; reg = <0xffd00300 0x100>; interrupts = <0 118 4>; + resets = <&rst WATCHDOG1_RESET>; status = "disabled"; }; @@ -347,6 +370,7 @@ watchdog2: watchdog@ffd00400 { compatible = "snps,dw-wdt"; reg = <0xffd00400 0x100>; interrupts = <0 125 4>; + resets = <&rst WATCHDOG2_RESET>; status = "disabled"; }; @@ -354,6 +378,7 @@ watchdog3: watchdog@ffd00500 { compatible = "snps,dw-wdt"; reg = <0xffd00500 0x100>; interrupts = <0 126 4>; + resets = <&rst WATCHDOG3_RESET>; status = "disabled"; }; };