From c86ee66e14acb15d7d20b329ea49f751c9df8bc9 Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Tue, 21 Oct 2025 17:41:36 +0800 Subject: [PATCH 01/10] dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei Add vendor prefixes for "anlogic", "milianke" and "nuclei". These are required for describing the Milianke MLKPAI-FS01 board with DR1V90 SoC from Anlogic, which uses a processor core designed by Nuclei. Acked-by: Krzysztof Kozlowski Signed-off-by: Junhui Liu Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index f1d1882009ba..23e74b96bfb7 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -132,6 +132,8 @@ patternProperties: description: Anbernic "^andestech,.*": description: Andes Technology Corporation + "^anlogic,.*": + description: Shanghai Anlogic Infotech Co., Ltd. "^anvo,.*": description: Anvo-Systems Dresden GmbH "^aoly,.*": @@ -1023,6 +1025,8 @@ patternProperties: description: MikroElektronika d.o.o. "^mikrotik,.*": description: MikroTik + "^milianke,.*": + description: Changzhou Milianke Electronic Technology Co., Ltd "^milkv,.*": description: MilkV Technology Co., Ltd "^miniand,.*": @@ -1140,6 +1144,8 @@ patternProperties: description: Novatek "^novtech,.*": description: NovTech, Inc. + "^nuclei,.*": + description: Nuclei System Technology "^numonyx,.*": description: Numonyx (deprecated, use micron) deprecated: true From 66c2a3173cdaf7b776552203609f008c8709dd22 Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Tue, 21 Oct 2025 17:41:37 +0800 Subject: [PATCH 02/10] dt-bindings: riscv: Add Nuclei UX900 compatibles The UX900 is a RISC-V core from Nuclei, used in the Anlogic DR1V90 SoC. It features a 64-bit architecture and dual-issue, 9-stage pipeline, with lots of optional extensions including V, K, Zc, and more. Acked-by: Conor Dooley Signed-off-by: Junhui Liu Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 153d0dac57fb..20b7c834559c 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -48,6 +48,7 @@ properties: - amd,mbv64 - andestech,ax45mp - canaan,k210 + - nuclei,ux900 - sifive,bullet0 - sifive,e5 - sifive,e7 From 4689d4422ac47ffb0a4c06fdb0e165388f585d01 Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Tue, 21 Oct 2025 17:41:38 +0800 Subject: [PATCH 03/10] dt-bindings: riscv: Add Anlogic DR1V90 Add Anlogic DR1V90 FPSoC, featuring a UX900 RISC-V core as the processing system (PS) and 94,464 LUTs programmable logic (PL). It is used by the Milianke MLKPAI-FS01 board, a SBC equipped with 512MB DDR3 memory, USB-C UART, 1GbE RJ45 Ethernet, USB-A 2.0 port, TF card slot, and 256Mbit Quad-SPI flash. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Junhui Liu Signed-off-by: Conor Dooley --- .../devicetree/bindings/riscv/anlogic.yaml | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/anlogic.yaml diff --git a/Documentation/devicetree/bindings/riscv/anlogic.yaml b/Documentation/devicetree/bindings/riscv/anlogic.yaml new file mode 100644 index 000000000000..91b1526c99aa --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/anlogic.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/anlogic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Anlogic SoC-based boards + +maintainers: + - Junhui Liu + +description: + Anlogic SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - milianke,mlkpai-fs01 + - const: anlogic,dr1v90 + +additionalProperties: true + +... From ccc3fd3ebeef2686f005733858c0a1b2cb89aaeb Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Tue, 21 Oct 2025 17:41:42 +0800 Subject: [PATCH 04/10] dt-bindings: timer: Add Anlogic DR1V90 ACLINT MTIMER Add MTIMER support for Anlogic DR1V90 SoC, which uses Nuclei UX900 with a TIMER unit compliant with the ACLINT specification. Signed-off-by: Junhui Liu Acked-by: Rob Herring (Arm) Signed-off-by: Conor Dooley --- .../timer/thead,c900-aclint-mtimer.yaml | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml index 4ed30efe4052..cf7c82e980f6 100644 --- a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml +++ b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml @@ -4,18 +4,23 @@ $id: http://devicetree.org/schemas/timer/thead,c900-aclint-mtimer.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Sophgo CLINT Timer +title: ACLINT Machine-level Timer Device maintainers: - Inochi Amaoto properties: compatible: - items: - - enum: - - sophgo,sg2042-aclint-mtimer - - sophgo,sg2044-aclint-mtimer - - const: thead,c900-aclint-mtimer + oneOf: + - items: + - enum: + - sophgo,sg2042-aclint-mtimer + - sophgo,sg2044-aclint-mtimer + - const: thead,c900-aclint-mtimer + - items: + - enum: + - anlogic,dr1v90-aclint-mtimer + - const: nuclei,ux900-aclint-mtimer reg: items: From a94f9be29464f85e97683901162ca236dde40dc7 Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Tue, 21 Oct 2025 17:41:43 +0800 Subject: [PATCH 05/10] dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart The Anlogic DR1V90 SoC integrates a UART controller compatible with snps,dw-apb-uart, operating at a 50 MHz clock. Acked-by: Rob Herring (Arm) Signed-off-by: Junhui Liu Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml index cb9da6c97afc..691bd0bac6be 100644 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -51,6 +51,7 @@ properties: - const: renesas,rzn1-uart - items: - enum: + - anlogic,dr1v90-uart - brcm,bcm11351-dw-apb-uart - brcm,bcm21664-dw-apb-uart - rockchip,px30-uart From 9c96219602b1a29c1959c5799aa3e6c5e14e395c Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Tue, 21 Oct 2025 17:41:45 +0800 Subject: [PATCH 06/10] riscv: Add Anlogic SoC famly Kconfig support The first SoC in the Anlogic series is DR1V90, which contains a RISC-V core from Nuclei. Acked-by: Conor Dooley Signed-off-by: Junhui Liu Signed-off-by: Conor Dooley --- arch/riscv/Kconfig.socs | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 848e7149e443..25f7e58cbf74 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -7,6 +7,11 @@ config ARCH_ANDES help This enables support for Andes SoC platform hardware. +config ARCH_ANLOGIC + bool "Anlogic SoCs" + help + This enables support for Anlogic SoC platform hardware. + config ARCH_ESWIN bool "ESWIN SoCs" help From 77874ebd4032b1f407b01a7bbdfcad752da05592 Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Tue, 21 Oct 2025 17:41:46 +0800 Subject: [PATCH 07/10] riscv: dts: Add initial Anlogic DR1V90 SoC device tree DR1V90 is a FPSoC from Anlogic, which features a RISC-V core as the PS part and 94,464 LUTs for the PL part. The PS part integrates a Nuclei UX900 RISC-V core with 32KB L1 icache and 32KB L1 dcache. It also provides two "snps,dw-apb-uart" compatible UART controllers. Some basic information of the processor can be obtained by running a simple application from nuclei-sdk [1]: -----Nuclei RISC-V CPU Configuration Information----- MARCHID: 0xc900 MIMPID: 0x20300 ISA: RV64 A B C D F I M P S U MCFG: TEE ECC ECLIC PLIC PPI ILM DLM ICACHE DCACHE IREGION No-Safety-Mechanism DLEN=VLEN/2 ILM: 256 KB has-ecc DLM: 256 KB has-ecc ICACHE: 32 KB(set=256,way=2,lsize=64,ecc=1) DCACHE: 32 KB(set=256,way=2,lsize=64,ecc=1) TLB: MainTLB(set=32,way=2,entry=1,ecc=1) ITLB(entry=8) DTLB(entry=8) IREGION: 0x68000000 128 MB Unit Size Address INFO 64KB 0x68000000 DEBUG 64KB 0x68010000 ECLIC 64KB 0x68020000 TIMER 64KB 0x68030000 PLIC 64MB 0x6c000000 INFO-Detail: mpasize : 0 PPI: 0xf8000000 128 MB -----End of Nuclei CPU INFO----- Link: https://github.com/Nuclei-Software/nuclei-sdk/blob/master/application/baremetal/cpuinfo/main.c [1] Acked-by: Conor Dooley Signed-off-by: Junhui Liu Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/anlogic/dr1v90.dtsi | 100 ++++++++++++++++++++++++ 1 file changed, 100 insertions(+) create mode 100644 arch/riscv/boot/dts/anlogic/dr1v90.dtsi diff --git a/arch/riscv/boot/dts/anlogic/dr1v90.dtsi b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi new file mode 100644 index 000000000000..a5d0765ade32 --- /dev/null +++ b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2025 Junhui Liu + */ + +/dts-v1/; +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "Anlogic DR1V90"; + compatible = "anlogic,dr1v90"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <800000000>; + + cpu@0 { + compatible = "nuclei,ux900", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <32768>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <32768>; + mmu-type = "riscv,sv39"; + reg = <0>; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zbc", + "zbkc", "zbs", "zicntr", "zicsr", "zifencei", + "zihintpause", "zihpm"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + aclint_mswi: interrupt-controller@68031000 { + compatible = "anlogic,dr1v90-aclint-mswi", "nuclei,ux900-aclint-mswi"; + reg = <0x0 0x68031000 0x0 0x4000>; + interrupts-extended = <&cpu0_intc 3>; + }; + + aclint_mtimer: timer@68035000 { + compatible = "anlogic,dr1v90-aclint-mtimer", "nuclei,ux900-aclint-mtimer"; + reg = <0x0 0x68035000 0x0 0x8000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu0_intc 7>; + }; + + aclint_sswi: interrupt-controller@6803d000 { + compatible = "anlogic,dr1v90-aclint-sswi", "nuclei,ux900-aclint-sswi"; + reg = <0x0 0x6803d000 0x0 0x3000>; + #interrupt-cells = <0>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 1>; + }; + + plic: interrupt-controller@6c000000 { + compatible = "anlogic,dr1v90-plic", "sifive,plic-1.0.0"; + reg = <0x0 0x6c000000 0x0 0x4000000>; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; + riscv,ndev = <150>; + }; + + uart0: serial@f8400000 { + compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart"; + reg = <0x0 0xf8400000 0x0 0x1000>; + clock-frequency = <50000000>; + interrupts = <71>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart1: serial@f8401000 { + compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart"; + reg = <0x0 0xf8401000 0x0 0x1000>; + clock-frequency = <50000000>; + interrupts = <72>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + }; +}; From 7e6fd69c12f464c21e489aba763f0cef5cdd1373 Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Tue, 21 Oct 2025 17:41:47 +0800 Subject: [PATCH 08/10] riscv: dts: anlogic: Add Milianke MLKPAI FS01 board Add support for the Milianke MLKPAI FS01 board based on the Anlogic DR1V90 SoC. The board features 512MB of onboard memory, USB-C UART, 1GbE RJ45 Ethernet, USB-A 2.0 port, TF card slot, and 256Mbit Quad-SPI flash. Currently, the board can boot to a console via UART1, which is connected to the onboard serial chip and routed to the Type-C interface. Acked-by: Conor Dooley Signed-off-by: Junhui Liu Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/anlogic/Makefile | 2 ++ .../boot/dts/anlogic/dr1v90-mlkpai-fs01.dts | 28 +++++++++++++++++++ 3 files changed, 31 insertions(+) create mode 100644 arch/riscv/boot/dts/anlogic/Makefile create mode 100644 arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index 3763d199c70a..f99d38ee1aad 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 subdir-y += allwinner subdir-y += andes +subdir-y += anlogic subdir-y += canaan subdir-y += eswin subdir-y += microchip diff --git a/arch/riscv/boot/dts/anlogic/Makefile b/arch/riscv/boot/dts/anlogic/Makefile new file mode 100644 index 000000000000..87f3b2f418cf --- /dev/null +++ b/arch/riscv/boot/dts/anlogic/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ANLOGIC) += dr1v90-mlkpai-fs01.dtb diff --git a/arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts b/arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts new file mode 100644 index 000000000000..597407655efd --- /dev/null +++ b/arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2025 Junhui Liu + */ + +#include "dr1v90.dtsi" + +/ { + model = "Milianke MLKPAI-FS01"; + compatible = "milianke,mlkpai-fs01", "anlogic,dr1v90"; + + aliases { + serial0 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x20000000>; + }; +}; + +&uart1 { + status = "okay"; +}; From fa9311d9499fedf0f6d06c22e016b228f2f5d473 Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Tue, 21 Oct 2025 17:41:48 +0800 Subject: [PATCH 09/10] riscv: defconfig: Enable Anlogic SoC Enable Anlogic SoC config in defconfig to allow the default upstream kernel booting on Milianke MLKPAI-FS01 board. Acked-by: Conor Dooley Signed-off-by: Junhui Liu Signed-off-by: Conor Dooley --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index fc2725cbca18..14b82f770efe 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -23,6 +23,7 @@ CONFIG_CHECKPOINT_RESTORE=y CONFIG_BLK_DEV_INITRD=y CONFIG_PROFILING=y CONFIG_ARCH_ANDES=y +CONFIG_ARCH_ANLOGIC=y CONFIG_ARCH_MICROCHIP=y CONFIG_ARCH_SIFIVE=y CONFIG_ARCH_SOPHGO=y From d5c3f49b75832553ba0dafabc2d394a885106498 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Wed, 12 Nov 2025 17:09:25 +0000 Subject: [PATCH 10/10] MAINTAINERS: Setup support for Anlogic tree Add myself as the maintainer of the Anlogic DR1V90 SoC tree, including the corresponding DTS and DT bindings paths for Anlogic RISC-V-based SoCs. I don't really want to look after this platform, but am due to irritation of the vendor's behaviour towards the contributor of support. Hence, Odd Fixes as the status. Signed-off-by: Conor Dooley --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 46126ce2f968..8c153489d2fd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22055,6 +22055,14 @@ F: Documentation/devicetree/bindings/riscv/andes.yaml F: Documentation/devicetree/bindings/timer/andestech,plmt0.yaml F: arch/riscv/boot/dts/andes/ +RISC-V ANLOGIC SoC SUPPORT +M: Conor Dooley +T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ +L: linux-riscv@lists.infradead.org +S: Odd Fixes +F: Documentation/devicetree/bindings/riscv/anlogic.yaml +F: arch/riscv/boot/dts/anlogic/ + RISC-V ARCHITECTURE M: Paul Walmsley M: Palmer Dabbelt