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drm/amd/amdgpu: remove duplicated code in gfx_v11 and gfx_v12

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The functions gfx_v11_0_handle_priv_fault and
gfx_v12_0_handle_priv_fault share the same logic for searching and
triggering a scheduler fault on a ring. This patch moves the shared
ring-searching logic to a common function, amdgpu_gfx_handle_priv_fault,
in amdgpu_gfx.c. The hardware-specific decoding of ring IDs remains in
the version-specific files to maintain proper architectural separation.

Signed-off-by: Ulisses Paixao <ulissespaixao@usp.br>
Co-developed-by: Felipe Sousa <felipesousa@usp.br>
Signed-off-by: Felipe Sousa <felipesousa@usp.br>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Ulisses Paixao
2026-07-29 10:22:26 -04:00
committed by Alex Deucher
parent d8b517d374
commit 9243cf4777
4 changed files with 67 additions and 87 deletions
Download Patch File Download Diff File Expand all files Collapse all files

54
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
View File

@@ -34,6 +34,7 @@
#include "amdgpu_xcp.h"
#include "amdgpu_xgmi.h"
#include "amdgpu_mes.h"
#include "amdgpu_userq.h"
#include "mes_userqueue.h"
#include "nvd.h"
@@ -855,6 +856,59 @@ int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id)
return r;
}
/**
* amdgpu_gfx_handle_priv_fault - Handle privileged instruction fault
*
* @adev: amdgpu_device pointer
* @entry: interrupt vector entry containing fault information
* @me_id: micro-engine ID of the faulty ring
* @pipe_id: pipe ID of the faulty ring
* @queue_id: queue ID of the faulty ring
*
* This function handles privileged instruction faults by identifying
* the faulty ring (gfx or compute) and triggering a scheduler fault
*/
void amdgpu_gfx_handle_priv_fault(struct amdgpu_device *adev,
struct amdgpu_iv_entry *entry,
u8 me_id, u8 pipe_id, u8 queue_id)
{
struct amdgpu_ring *ring;
u32 doorbell_offset;
int i;
/*
* Try KQ first by ring_id (HW slot is authoritative). The
* KMD compute_hqd_mask contract guarantees KCQ and user queues
* never share a HW slot.
*/
if (!adev->gfx.disable_kq) {
for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
ring = &adev->gfx.gfx_ring[i];
if (ring->me == me_id && ring->pipe == pipe_id &&
ring->queue == queue_id) {
drm_sched_fault(&ring->sched);
return;
}
}
for (i = 0; i < adev->gfx.num_compute_rings; i++) {
ring = &adev->gfx.compute_ring[i];
if (ring->me == me_id && ring->pipe == pipe_id &&
ring->queue == queue_id) {
drm_sched_fault(&ring->sched);
return;
}
}
}
doorbell_offset = entry->src_data[0] & AMDGPU_CTXID0_DOORBELL_ID_MASK;
/* No KQ matched: HW slot is a MES-scheduled user queue. */
if (adev->enable_mes && doorbell_offset)
amdgpu_userq_process_reset_irq(adev, entry->pasid,
doorbell_offset);
}
static void amdgpu_gfx_do_off_ctrl(struct amdgpu_device *adev, bool enable,
bool no_delay)
{

3
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
View File

@@ -620,6 +620,9 @@ bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev,
struct amdgpu_ring *ring);
bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
int pipe, int queue);
void amdgpu_gfx_handle_priv_fault(struct amdgpu_device *adev,
struct amdgpu_iv_entry *entry,
u8 me_id, u8 pipe_id, u8 queue_id);
void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
void amdgpu_gfx_off_ctrl_immediate(struct amdgpu_device *adev, bool enable);
int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value);

48
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
View File

@@ -6714,51 +6714,13 @@ static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev,
struct amdgpu_iv_entry *entry)
{
u32 doorbell_offset = entry->src_data[0] & AMDGPU_CTXID0_DOORBELL_ID_MASK;
u8 me_id, pipe_id, queue_id;
/*
* Try KQ first by ring_id (HW slot is authoritative). The
* KMD compute_hqd_mask contract guarantees KCQ and user queues
* never share a HW slot.
*/
if (!adev->gfx.disable_kq) {
u8 me_id = (entry->ring_id & 0x0c) >> 2;
u8 pipe_id = (entry->ring_id & 0x03) >> 0;
u8 queue_id = (entry->ring_id & 0x70) >> 4;
struct amdgpu_ring *ring;
int i;
me_id = (entry->ring_id & 0x0c) >> 2;
pipe_id = (entry->ring_id & 0x03) >> 0;
queue_id = (entry->ring_id & 0x70) >> 4;
switch (me_id) {
case 0:
for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
ring = &adev->gfx.gfx_ring[i];
if (ring->me == me_id && ring->pipe == pipe_id &&
ring->queue == queue_id) {
drm_sched_fault(&ring->sched);
return;
}
}
break;
case 1:
case 2:
for (i = 0; i < adev->gfx.num_compute_rings; i++) {
ring = &adev->gfx.compute_ring[i];
if (ring->me == me_id && ring->pipe == pipe_id &&
ring->queue == queue_id) {
drm_sched_fault(&ring->sched);
return;
}
}
break;
default:
break;
}
}
/* No KQ matched: HW slot is a MES-scheduled user queue. */
if (adev->enable_mes && doorbell_offset)
amdgpu_userq_process_reset_irq(adev, entry->pasid,
doorbell_offset);
amdgpu_gfx_handle_priv_fault(adev, entry, me_id, pipe_id, queue_id);
}
static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev,

49
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
View File

@@ -5045,52 +5045,13 @@ static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev,
struct amdgpu_iv_entry *entry)
{
u32 doorbell_offset = entry->src_data[0] & AMDGPU_CTXID0_DOORBELL_ID_MASK;
u8 me_id, pipe_id, queue_id;
/*
* Try KQ first by ring_id; UQ as fallback. KCQ and UQ never share
* a HW slot (compute_hqd_mask contract).
*/
if (!adev->gfx.disable_kq) {
u8 me_id, pipe_id, queue_id;
struct amdgpu_ring *ring;
int i;
me_id = (entry->ring_id & 0x0c) >> 2;
pipe_id = (entry->ring_id & 0x03) >> 0;
queue_id = (entry->ring_id & 0x70) >> 4;
me_id = (entry->ring_id & 0x0c) >> 2;
pipe_id = (entry->ring_id & 0x03) >> 0;
queue_id = (entry->ring_id & 0x70) >> 4;
switch (me_id) {
case 0:
for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
ring = &adev->gfx.gfx_ring[i];
if (ring->me == me_id && ring->pipe == pipe_id &&
ring->queue == queue_id) {
drm_sched_fault(&ring->sched);
return;
}
}
break;
case 1:
case 2:
for (i = 0; i < adev->gfx.num_compute_rings; i++) {
ring = &adev->gfx.compute_ring[i];
if (ring->me == me_id && ring->pipe == pipe_id &&
ring->queue == queue_id) {
drm_sched_fault(&ring->sched);
return;
}
}
break;
default:
break;
}
}
/* No KQ matched: HW slot is a MES-scheduled user queue. */
if (adev->enable_mes && doorbell_offset)
amdgpu_userq_process_reset_irq(adev, entry->pasid,
doorbell_offset);
amdgpu_gfx_handle_priv_fault(adev, entry, me_id, pipe_id, queue_id);
}
static int gfx_v12_0_priv_reg_irq(struct amdgpu_device *adev,