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drm/msm/a6xx: Add a pwrup_list field to a6xx_info

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Add a field to contain the pwup_reglist needed for preemption.

Signed-off-by: Antonino Maniscalco <antomani103@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/618018/
Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Antonino Maniscalco
2024-10-03 18:12:54 +02:00
committed by Rob Clark
parent c7546e2c3c
commit 91389b4e32
3 changed files with 41 additions and 0 deletions
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26
drivers/gpu/drm/msm/adreno/a6xx_catalog.c
View File

@@ -1281,6 +1281,28 @@ static const u32 a730_protect_regs[] = {
};
DECLARE_ADRENO_PROTECT(a730_protect, 48);
static const uint32_t a7xx_pwrup_reglist_regs[] = {
REG_A6XX_UCHE_TRAP_BASE,
REG_A6XX_UCHE_TRAP_BASE + 1,
REG_A6XX_UCHE_WRITE_THRU_BASE,
REG_A6XX_UCHE_WRITE_THRU_BASE + 1,
REG_A6XX_UCHE_GMEM_RANGE_MIN,
REG_A6XX_UCHE_GMEM_RANGE_MIN + 1,
REG_A6XX_UCHE_GMEM_RANGE_MAX,
REG_A6XX_UCHE_GMEM_RANGE_MAX + 1,
REG_A6XX_UCHE_CACHE_WAYS,
REG_A6XX_UCHE_MODE_CNTL,
REG_A6XX_RB_NC_MODE_CNTL,
REG_A6XX_RB_CMP_DBG_ECO_CNTL,
REG_A7XX_GRAS_NC_MODE_CNTL,
REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE,
REG_A6XX_UCHE_GBIF_GX_CONFIG,
REG_A6XX_UCHE_CLIENT_PF,
REG_A6XX_TPL1_DBG_ECO_CNTL1,
};
DECLARE_ADRENO_REGLIST_LIST(a7xx_pwrup_reglist);
static const struct adreno_info a7xx_gpus[] = {
{
.chip_ids = ADRENO_CHIP_IDS(0x07000200),
@@ -1321,6 +1343,7 @@ static const struct adreno_info a7xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a730_hwcg,
.protect = &a730_protect,
.pwrup_reglist = &a7xx_pwrup_reglist,
.gmu_cgc_mode = 0x00020000,
},
.address_space_size = SZ_16G,
@@ -1341,6 +1364,7 @@ static const struct adreno_info a7xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a740_hwcg,
.protect = &a730_protect,
.pwrup_reglist = &a7xx_pwrup_reglist,
.gmu_chipid = 0x7020100,
.gmu_cgc_mode = 0x00020202,
},
@@ -1361,6 +1385,7 @@ static const struct adreno_info a7xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a740_hwcg,
.protect = &a730_protect,
.pwrup_reglist = &a7xx_pwrup_reglist,
.gmu_chipid = 0x7050001,
.gmu_cgc_mode = 0x00020202,
},
@@ -1381,6 +1406,7 @@ static const struct adreno_info a7xx_gpus[] = {
.zapfw = "gen70900_zap.mbn",
.a6xx = &(const struct a6xx_info) {
.protect = &a730_protect,
.pwrup_reglist = &a7xx_pwrup_reglist,
.gmu_chipid = 0x7090100,
.gmu_cgc_mode = 0x00020202,
},

2
drivers/gpu/drm/msm/adreno/a6xx_gpu.h
View File

@@ -17,10 +17,12 @@ extern bool hang_debug;
*
* @hwcg: hw clock gating register sequence
* @protect: CP_PROTECT settings
* @pwrup_reglist pwrup reglist for preemption
*/
struct a6xx_info {
const struct adreno_reglist *hwcg;
const struct adreno_protect *protect;
const struct adreno_reglist_list *pwrup_reglist;
u32 gmu_chipid;
u32 gmu_cgc_mode;
u32 prim_fifo_threshold;

13
drivers/gpu/drm/msm/adreno/adreno_gpu.h
View File

@@ -157,6 +157,19 @@ static const struct adreno_protect name = { \
.count_max = __count_max, \
};
struct adreno_reglist_list {
/** @reg: List of register **/
const u32 *regs;
/** @count: Number of registers in the list **/
u32 count;
};
#define DECLARE_ADRENO_REGLIST_LIST(name) \
static const struct adreno_reglist_list name = { \
.regs = name ## _regs, \
.count = ARRAY_SIZE(name ## _regs), \
};
struct adreno_gpu {
struct msm_gpu base;
const struct adreno_info *info;