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drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188
Add support for the newer HDMI-TX (Encoder) v2 and DDC v2 IPs found in MediaTek's MT8195, MT8188 SoC and their variants, and including support for display modes up to 4k60 and for HDMI Audio, as per the HDMI 2.0 spec. HDCP and CEC functionalities are also supported by this hardware, but are not included in this commit and that also poses a slight difference between the V2 and V1 controllers in how they handle Hotplug Detection (HPD). While the v1 controller was using the CEC controller to check HDMI cable connection and disconnection, in this driver the v2 one does not. This is due to the fact that on parts with v2 designs, like the MT8195 SoC, there is one CEC controller shared between the HDMI Transmitter (HDMI-TX) and Receiver (HDMI-RX): before eventually adding support to use the CEC HW to wake up the HDMI controllers it is necessary to have support for one TX, one RX *and* for both at the same time. Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20251023-mediatek-drm-hdmi-v2-v11-9-7873ec4a1edf@collabora.com/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> ddc_v2 ddc_v2
This commit is contained in:
AngeloGioacchino Del Regno
committed by
Chun-Kuang Hu
Chun-Kuang Hu
parent
3cbf91147a
commit
8d0f798862
@@ -45,3 +45,15 @@ config DRM_MEDIATEK_HDMI
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select DRM_MEDIATEK_HDMI_COMMON
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help
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DRM/KMS HDMI driver for Mediatek SoCs
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config DRM_MEDIATEK_HDMI_V2
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tristate "DRM HDMI v2 IP support for MediaTek SoCs"
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depends on DRM_MEDIATEK
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select DRM_MEDIATEK_HDMI_COMMON
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help
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Say yes here to enable support for the HDMIv2 IP and related
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DDCv2 as found in the MediaTek MT8195, MT8188 SoCs and other
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variants.
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This driver can also be built as a module. If so, the HDMIv2
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module will be called "mtk_hdmi_v2", and the DDCv2 module
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will be called "mtk_hdmi_ddc_v2".
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@@ -25,5 +25,7 @@ obj-$(CONFIG_DRM_MEDIATEK_HDMI_COMMON) += mtk_hdmi_common.o
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obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mtk_cec.o
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obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mtk_hdmi.o
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obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mtk_hdmi_ddc.o
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obj-$(CONFIG_DRM_MEDIATEK_HDMI_V2) += mtk_hdmi_v2.o
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obj-$(CONFIG_DRM_MEDIATEK_HDMI_V2) += mtk_hdmi_ddc_v2.o
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obj-$(CONFIG_DRM_MEDIATEK_DP) += mtk_dp.o
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@@ -302,6 +302,10 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, struct platform_device
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if (ret)
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return dev_err_probe(dev, ret, "Failed to get clocks\n");
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hdmi->irq = platform_get_irq(pdev, 0);
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if (!hdmi->irq)
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return hdmi->irq;
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hdmi->regs = device_node_to_regmap(dev->of_node);
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if (IS_ERR(hdmi->regs))
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return PTR_ERR(hdmi->regs);
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@@ -126,6 +126,12 @@ struct hdmi_audio_param {
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struct hdmi_codec_params codec_params;
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};
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enum hdmi_hpd_state {
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HDMI_PLUG_OUT = 0,
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HDMI_PLUG_IN_AND_SINK_POWER_ON,
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HDMI_PLUG_IN_ONLY,
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};
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struct mtk_hdmi_ver_conf {
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const struct drm_bridge_funcs *bridge_funcs;
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const struct hdmi_codec_ops *codec_ops;
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@@ -139,6 +145,7 @@ struct mtk_hdmi_conf {
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bool tz_disabled;
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bool cea_modes_only;
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unsigned long max_mode_clock;
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u32 reg_hdmi_tx_cfg;
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};
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struct mtk_hdmi {
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@@ -161,6 +168,8 @@ struct mtk_hdmi {
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bool audio_enable;
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bool powered;
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bool enabled;
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unsigned int irq;
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enum hdmi_hpd_state hpd;
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hdmi_codec_plugged_cb plugged_cb;
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struct device *codec_dev;
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struct mutex update_plugged_status_lock;
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396
drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c
Normal file
396
drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c
Normal file
@@ -0,0 +1,396 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* MediaTek HDMI v2 Display Data Channel Driver
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*
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* Copyright (c) 2021 MediaTek Inc.
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* Copyright (c) 2021 BayLibre, SAS
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* Copyright (c) 2024 Collabora Ltd.
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* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/i2c.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/types.h>
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#include <drm/drm_edid.h>
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#include "mtk_hdmi_common.h"
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#include "mtk_hdmi_regs_v2.h"
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#define DDC2_DLY_CNT 572 /* BIM=208M/(v*4) = 90Khz */
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#define DDC2_DLY_CNT_EDID 832 /* BIM=208M/(v*4) = 62.5Khz */
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#define SI2C_ADDR_READ 0xf4
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#define SCDC_I2C_SLAVE_ADDRESS 0x54
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struct mtk_hdmi_ddc {
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struct device *dev;
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struct regmap *regs;
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struct clk *clk;
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struct i2c_adapter adap;
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};
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static int mtk_ddc_check_and_rise_low_bus(struct mtk_hdmi_ddc *ddc)
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{
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u32 val;
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regmap_read(ddc->regs, HDCP2X_DDCM_STATUS, &val);
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if (val & DDC_I2C_BUS_LOW) {
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regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD,
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FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_CLOCK_SCL));
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usleep_range(250, 300);
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}
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if (val & DDC_I2C_NO_ACK) {
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u32 ddc_ctrl, hpd_ddc_ctrl, hpd_ddc_status;
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regmap_read(ddc->regs, DDC_CTRL, &ddc_ctrl);
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regmap_read(ddc->regs, HPD_DDC_CTRL, &hpd_ddc_ctrl);
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regmap_read(ddc->regs, HPD_DDC_STATUS, &hpd_ddc_status);
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}
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if (val & DDC_I2C_NO_ACK)
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return -EIO;
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return 0;
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}
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static int mtk_ddc_wr_one(struct mtk_hdmi_ddc *ddc, u16 addr_id,
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u16 offset_id, u8 *wr_data)
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{
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u32 val;
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int ret;
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/* If down, rise bus for write operation */
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mtk_ddc_check_and_rise_low_bus(ddc);
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regmap_update_bits(ddc->regs, HPD_DDC_CTRL, HPD_DDC_DELAY_CNT,
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FIELD_PREP(HPD_DDC_DELAY_CNT, DDC2_DLY_CNT));
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if (wr_data) {
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regmap_write(ddc->regs, SI2C_CTRL,
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FIELD_PREP(SI2C_ADDR, SI2C_ADDR_READ) |
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FIELD_PREP(SI2C_WDATA, *wr_data) |
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SI2C_WR);
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}
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regmap_write(ddc->regs, DDC_CTRL,
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FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_SEQ_WRITE) |
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FIELD_PREP(DDC_CTRL_DIN_CNT, wr_data == NULL ? 0 : 1) |
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FIELD_PREP(DDC_CTRL_OFFSET, offset_id) |
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FIELD_PREP(DDC_CTRL_ADDR, addr_id));
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usleep_range(1000, 1250);
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ret = regmap_read_poll_timeout(ddc->regs, HPD_DDC_STATUS, val,
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!(val & DDC_I2C_IN_PROG), 500, 1000);
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if (ret) {
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dev_err(ddc->dev, "DDC I2C write timeout\n");
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return ret;
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}
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/* The I2C bus might be down after WR operation: rise it again */
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ret = mtk_ddc_check_and_rise_low_bus(ddc);
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if (ret) {
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dev_err(ddc->dev, "Error during write operation: No ACK\n");
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return ret;
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}
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return 0;
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}
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static int mtk_ddcm_read_hdmi(struct mtk_hdmi_ddc *ddc, u16 uc_dev,
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u8 addr, u8 *puc_value, u16 data_cnt)
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{
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u16 dly_cnt, i, uc_idx;
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u32 rem, temp_length, uc_read_count, val;
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u64 loop_counter;
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int ret;
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mtk_ddc_check_and_rise_low_bus(ddc);
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regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD,
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FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_CLEAR_FIFO));
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if (data_cnt >= 16) {
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temp_length = 16;
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loop_counter = data_cnt;
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rem = do_div(loop_counter, temp_length);
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if (rem)
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loop_counter++;
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} else {
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temp_length = data_cnt;
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loop_counter = 1;
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}
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if (uc_dev >= DDC_ADDR)
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dly_cnt = DDC2_DLY_CNT_EDID;
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else
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dly_cnt = DDC2_DLY_CNT;
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regmap_update_bits(ddc->regs, HPD_DDC_CTRL, HPD_DDC_DELAY_CNT,
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FIELD_PREP(HPD_DDC_DELAY_CNT, dly_cnt));
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for (i = 0; i < loop_counter; i++) {
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rem = data_cnt % 16;
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if (i > 0 && i == (loop_counter - 1) && rem)
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temp_length = rem;
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/* 0x51 - 0x53: Flow control */
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if (uc_dev > DDC_ADDR && uc_dev <= 0x53) {
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regmap_update_bits(ddc->regs, SCDC_CTRL, SCDC_DDC_SEGMENT,
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FIELD_PREP(SCDC_DDC_SEGMENT, uc_dev - DDC_ADDR));
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regmap_write(ddc->regs, DDC_CTRL,
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FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_ENH_READ_NOACK) |
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FIELD_PREP(DDC_CTRL_DIN_CNT, temp_length) |
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FIELD_PREP(DDC_CTRL_OFFSET, addr + i * temp_length) |
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FIELD_PREP(DDC_CTRL_ADDR, DDC_ADDR));
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} else {
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u16 offset;
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if (addr != 0x43)
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offset = i * 16;
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else
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offset = 0;
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regmap_write(ddc->regs, DDC_CTRL,
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FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_SEQ_READ_NOACK) |
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FIELD_PREP(DDC_CTRL_DIN_CNT, temp_length) |
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FIELD_PREP(DDC_CTRL_OFFSET, addr + offset) |
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FIELD_PREP(DDC_CTRL_ADDR, uc_dev));
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}
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usleep_range(5000, 5500);
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ret = regmap_read_poll_timeout(ddc->regs, HPD_DDC_STATUS, val,
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!(val & DDC_I2C_IN_PROG), 1000,
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500 * (temp_length + 5));
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if (ret) {
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dev_err(ddc->dev, "Timeout waiting for DDC I2C\n");
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return ret;
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}
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ret = mtk_ddc_check_and_rise_low_bus(ddc);
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if (ret) {
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dev_err(ddc->dev, "Error during read operation: No ACK\n");
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return ret;
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}
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for (uc_idx = 0; uc_idx < temp_length; uc_idx++) {
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unsigned int read_idx = i * 16 + uc_idx;
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regmap_write(ddc->regs, SI2C_CTRL,
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FIELD_PREP(SI2C_ADDR, SI2C_ADDR_READ) |
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SI2C_RD);
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regmap_read(ddc->regs, HPD_DDC_STATUS, &val);
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puc_value[read_idx] = FIELD_GET(DDC_DATA_OUT, val);
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regmap_write(ddc->regs, SI2C_CTRL,
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FIELD_PREP(SI2C_ADDR, SI2C_ADDR_READ) |
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SI2C_CONFIRM_READ);
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/*
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* If HDMI IP gets reset during EDID read, DDC read
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* operation will fail and its delay counter will be
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* reset to 400.
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*/
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regmap_read(ddc->regs, HPD_DDC_CTRL, &val);
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if (FIELD_GET(HPD_DDC_DELAY_CNT, val) < DDC2_DLY_CNT)
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return 0;
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uc_read_count = read_idx + 1;
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}
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}
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if (uc_read_count > U8_MAX)
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dev_warn(ddc->dev, "Invalid read data count %u\n", uc_read_count);
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return uc_read_count;
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}
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static int mtk_hdmi_fg_ddc_data_read(struct mtk_hdmi_ddc *ddc, u16 b_dev,
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u8 data_addr, u16 data_cnt, u8 *pr_data)
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{
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int read_data_cnt;
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u16 req_data_cnt;
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if (!data_cnt) {
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dev_err(ddc->dev, "Invalid DDCM read request\n");
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return -EINVAL;
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}
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req_data_cnt = U8_MAX - data_addr + 1;
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if (req_data_cnt > data_cnt)
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req_data_cnt = data_cnt;
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regmap_set_bits(ddc->regs, HDCP2X_POL_CTRL, HDCP2X_DIS_POLL_EN);
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read_data_cnt = mtk_ddcm_read_hdmi(ddc, b_dev, data_addr, pr_data, req_data_cnt);
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if (read_data_cnt < 0)
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return read_data_cnt;
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else if (read_data_cnt != req_data_cnt)
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return -EINVAL;
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return 0;
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}
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static int mtk_hdmi_ddc_fg_data_write(struct mtk_hdmi_ddc *ddc, u16 b_dev,
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u8 data_addr, u16 data_cnt, u8 *pr_data)
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{
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int i, ret;
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regmap_set_bits(ddc->regs, HDCP2X_POL_CTRL, HDCP2X_DIS_POLL_EN);
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/*
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* In case there is no payload data, just do a single write for the
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* address only
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*/
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if (data_cnt == 0)
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return mtk_ddc_wr_one(ddc, b_dev, data_addr, NULL);
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i = 0;
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do {
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ret = mtk_ddc_wr_one(ddc, b_dev, data_addr + i, pr_data + i);
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if (ret)
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return ret;
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} while (++i < data_cnt);
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return 0;
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}
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static int mtk_hdmi_ddc_v2_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
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{
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struct mtk_hdmi_ddc *ddc;
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u8 offset = 0;
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int i, ret;
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ddc = adapter->algo_data;
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for (i = 0; i < num; i++) {
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struct i2c_msg *msg = &msgs[i];
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if (!msg->buf) {
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dev_err(ddc->dev, "No message buffer\n");
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return -EINVAL;
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}
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if (msg->flags & I2C_M_RD) {
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/*
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* The underlying DDC hardware always issues a write request
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* that assigns the read offset as part of the read operation,
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* therefore, use the `offset` value assigned in the previous
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* write request from drm_edid
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*/
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ret = mtk_hdmi_fg_ddc_data_read(ddc, msg->addr, offset,
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msg->len, &msg->buf[0]);
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if (ret)
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return ret;
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} else {
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/*
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* The HW needs the data offset, found in buf[0], in the
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* DDC_CTRL register, and each byte of data, starting at
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* buf[1], goes in the SI2C_WDATA register.
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*/
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ret = mtk_hdmi_ddc_fg_data_write(ddc, msg->addr, msg->buf[0],
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msg->len - 1, &msg->buf[1]);
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if (ret)
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return ret;
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/*
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* Store the offset value requested by drm_edid or by
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* scdc to use in subsequent read requests.
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*/
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if ((msg->addr == DDC_ADDR || msg->addr == SCDC_I2C_SLAVE_ADDRESS) &&
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msg->len == 1) {
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offset = msg->buf[0];
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}
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}
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}
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return i;
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}
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static u32 mtk_hdmi_ddc_v2_func(struct i2c_adapter *adapter)
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{
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
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}
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static const struct i2c_algorithm mtk_hdmi_ddc_v2_algorithm = {
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.master_xfer = mtk_hdmi_ddc_v2_xfer,
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.functionality = mtk_hdmi_ddc_v2_func,
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};
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static int mtk_hdmi_ddc_v2_probe(struct platform_device *pdev)
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{
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||||
struct device *dev = &pdev->dev;
|
||||
struct mtk_hdmi_ddc *ddc;
|
||||
int ret;
|
||||
|
||||
ddc = devm_kzalloc(dev, sizeof(*ddc), GFP_KERNEL);
|
||||
if (!ddc)
|
||||
return -ENOMEM;
|
||||
|
||||
ddc->dev = dev;
|
||||
ddc->regs = device_node_to_regmap(dev->parent->of_node);
|
||||
if (IS_ERR_OR_NULL(ddc->regs))
|
||||
return dev_err_probe(dev,
|
||||
IS_ERR(ddc->regs) ? PTR_ERR(ddc->regs) : -EINVAL,
|
||||
"Cannot get regmap\n");
|
||||
|
||||
ddc->clk = devm_clk_get_enabled(dev, NULL);
|
||||
if (IS_ERR(ddc->clk))
|
||||
return dev_err_probe(dev, PTR_ERR(ddc->clk), "Cannot get DDC clock\n");
|
||||
|
||||
strscpy(ddc->adap.name, "mediatek-hdmi-ddc-v2", sizeof(ddc->adap.name));
|
||||
ddc->adap.owner = THIS_MODULE;
|
||||
ddc->adap.algo = &mtk_hdmi_ddc_v2_algorithm;
|
||||
ddc->adap.retries = 3;
|
||||
ddc->adap.dev.of_node = dev->of_node;
|
||||
ddc->adap.algo_data = ddc;
|
||||
ddc->adap.dev.parent = &pdev->dev;
|
||||
|
||||
ret = devm_pm_runtime_enable(&pdev->dev);
|
||||
if (ret)
|
||||
return dev_err_probe(&pdev->dev, ret, "Cannot enable Runtime PM\n");
|
||||
|
||||
pm_runtime_get_sync(dev);
|
||||
|
||||
ret = devm_i2c_add_adapter(dev, &ddc->adap);
|
||||
if (ret < 0)
|
||||
return dev_err_probe(dev, ret, "Cannot add DDC I2C adapter\n");
|
||||
|
||||
platform_set_drvdata(pdev, ddc);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id mtk_hdmi_ddc_v2_match[] = {
|
||||
{ .compatible = "mediatek,mt8195-hdmi-ddc" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mtk_hdmi_ddc_v2_match);
|
||||
|
||||
struct platform_driver mtk_hdmi_ddc_v2_driver = {
|
||||
.probe = mtk_hdmi_ddc_v2_probe,
|
||||
.driver = {
|
||||
.name = "mediatek-hdmi-ddc-v2",
|
||||
.of_match_table = mtk_hdmi_ddc_v2_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(mtk_hdmi_ddc_v2_driver);
|
||||
|
||||
MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
|
||||
MODULE_AUTHOR("Can Zeng <can.zeng@mediatek.com>");
|
||||
MODULE_DESCRIPTION("MediaTek HDMIv2 DDC Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
263
drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h
Normal file
263
drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h
Normal file
@@ -0,0 +1,263 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2021 MediaTek Inc.
|
||||
* Copyright (c) 2021 BayLibre, SAS
|
||||
* Copyright (c) 2024 Collabora Ltd.
|
||||
* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
*/
|
||||
|
||||
#ifndef _MTK_HDMI_REGS_H
|
||||
#define _MTK_HDMI_REGS_H
|
||||
|
||||
/* HDMI_TOP Config */
|
||||
#define TOP_CFG00 0x000
|
||||
#define HDMI2_ON BIT(2)
|
||||
#define HDMI_MODE_HDMI BIT(3)
|
||||
#define SCR_ON BIT(4)
|
||||
#define TMDS_PACK_MODE GENMASK(9, 8)
|
||||
#define TMDS_PACK_MODE_8BPP 0
|
||||
#define TMDS_PACK_MODE_10BPP 1
|
||||
#define TMDS_PACK_MODE_12BPP 2
|
||||
#define TMDS_PACK_MODE_16BPP 3
|
||||
#define DEEPCOLOR_PKT_EN BIT(12)
|
||||
#define HDMI_ABIST_VIDEO_FORMAT GENMASK(21, 16)
|
||||
#define HDMI_ABIST_ENABLE BIT(31)
|
||||
#define TOP_CFG01 0x004
|
||||
#define CP_SET_MUTE_EN BIT(0)
|
||||
#define CP_CLR_MUTE_EN BIT(1)
|
||||
#define NULL_PKT_EN BIT(2)
|
||||
#define NULL_PKT_VSYNC_HIGH_EN BIT(3)
|
||||
|
||||
/* HDMI_TOP Audio: Channel Mapping */
|
||||
#define TOP_AUD_MAP 0x00c
|
||||
#define SD0_MAP GENMASK(2, 0)
|
||||
#define SD1_MAP GENMASK(6, 4)
|
||||
#define SD2_MAP GENMASK(10, 8)
|
||||
#define SD3_MAP GENMASK(14, 12)
|
||||
#define SD4_MAP GENMASK(18, 16)
|
||||
#define SD5_MAP GENMASK(22, 20)
|
||||
#define SD6_MAP GENMASK(26, 24)
|
||||
#define SD7_MAP GENMASK(30, 28)
|
||||
|
||||
/* Auxiliary Video Information (AVI) Infoframe */
|
||||
#define TOP_AVI_HEADER 0x024
|
||||
#define TOP_AVI_PKT00 0x028
|
||||
#define TOP_AVI_PKT01 0x02C
|
||||
#define TOP_AVI_PKT02 0x030
|
||||
#define TOP_AVI_PKT03 0x034
|
||||
#define TOP_AVI_PKT04 0x038
|
||||
#define TOP_AVI_PKT05 0x03C
|
||||
|
||||
/* Audio Interface Infoframe */
|
||||
#define TOP_AIF_HEADER 0x040
|
||||
#define TOP_AIF_PKT00 0x044
|
||||
#define TOP_AIF_PKT01 0x048
|
||||
#define TOP_AIF_PKT02 0x04c
|
||||
#define TOP_AIF_PKT03 0x050
|
||||
|
||||
/* Audio SPDIF Infoframe */
|
||||
#define TOP_SPDIF_HEADER 0x054
|
||||
#define TOP_SPDIF_PKT00 0x058
|
||||
#define TOP_SPDIF_PKT01 0x05c
|
||||
#define TOP_SPDIF_PKT02 0x060
|
||||
#define TOP_SPDIF_PKT03 0x064
|
||||
#define TOP_SPDIF_PKT04 0x068
|
||||
#define TOP_SPDIF_PKT05 0x06c
|
||||
#define TOP_SPDIF_PKT06 0x070
|
||||
#define TOP_SPDIF_PKT07 0x074
|
||||
|
||||
/* Infoframes Configuration */
|
||||
#define TOP_INFO_EN 0x01c
|
||||
#define AVI_EN BIT(0)
|
||||
#define SPD_EN BIT(1)
|
||||
#define AUD_EN BIT(2)
|
||||
#define CP_EN BIT(5)
|
||||
#define VSIF_EN BIT(11)
|
||||
#define AVI_EN_WR BIT(16)
|
||||
#define SPD_EN_WR BIT(17)
|
||||
#define AUD_EN_WR BIT(18)
|
||||
#define CP_EN_WR BIT(21)
|
||||
#define VSIF_EN_WR BIT(27)
|
||||
#define TOP_INFO_RPT 0x020
|
||||
#define AVI_RPT_EN BIT(0)
|
||||
#define SPD_RPT_EN BIT(1)
|
||||
#define AUD_RPT_EN BIT(2)
|
||||
#define CP_RPT_EN BIT(5)
|
||||
#define VSIF_RPT_EN BIT(11)
|
||||
|
||||
/* Vendor Specific Infoframe */
|
||||
#define TOP_VSIF_HEADER 0x174
|
||||
#define TOP_VSIF_PKT00 0x178
|
||||
#define TOP_VSIF_PKT01 0x17c
|
||||
#define TOP_VSIF_PKT02 0x180
|
||||
#define TOP_VSIF_PKT03 0x184
|
||||
#define TOP_VSIF_PKT04 0x188
|
||||
#define TOP_VSIF_PKT05 0x18c
|
||||
#define TOP_VSIF_PKT06 0x190
|
||||
#define TOP_VSIF_PKT07 0x194
|
||||
|
||||
/* HDMI_TOP Misc */
|
||||
#define TOP_MISC_CTLR 0x1a4
|
||||
#define DEEP_COLOR_ADD BIT(4)
|
||||
|
||||
/* Hardware interrupts */
|
||||
#define TOP_INT_STA00 0x1a8
|
||||
#define TOP_INT_ENABLE00 0x1b0
|
||||
#define HTPLG_R_INT BIT(0)
|
||||
#define HTPLG_F_INT BIT(1)
|
||||
#define PORD_R_INT BIT(2)
|
||||
#define PORD_F_INT BIT(3)
|
||||
#define HDMI_VSYNC_INT BIT(4)
|
||||
#define HDMI_AUDIO_INT BIT(5)
|
||||
#define HDCP2X_RX_REAUTH_REQ_DDCM_INT BIT(25)
|
||||
#define TOP_INT_ENABLE01 0x1b4
|
||||
#define TOP_INT_CLR00 0x1b8
|
||||
#define TOP_INT_CLR01 0x1bc
|
||||
|
||||
|
||||
/* Video Mute */
|
||||
#define TOP_VMUTE_CFG1 0x1c8
|
||||
#define REG_VMUTE_EN BIT(16)
|
||||
|
||||
/* HDMI Audio IP */
|
||||
#define AIP_CTRL 0x400
|
||||
#define CTS_SW_SEL BIT(0)
|
||||
#define CTS_REQ_EN BIT(1)
|
||||
#define MCLK_EN BIT(2)
|
||||
#define NO_MCLK_CTSGEN_SEL BIT(3)
|
||||
#define AUD_IN_EN BIT(8)
|
||||
#define AUD_SEL_OWRT BIT(9)
|
||||
#define SPDIF_EN BIT(13)
|
||||
#define HBRA_ON BIT(14)
|
||||
#define DSD_EN BIT(15)
|
||||
#define I2S_EN GENMASK(19, 16)
|
||||
#define HBR_FROM_SPDIF BIT(20)
|
||||
#define CTS_CAL_N4 BIT(23)
|
||||
#define SPDIF_INTERNAL_MODULE BIT(24)
|
||||
#define AIP_N_VAL 0x404
|
||||
#define AIP_CTS_SVAL 0x408
|
||||
#define AIP_SPDIF_CTRL 0x40c
|
||||
#define WR_1UI_LOCK BIT(0)
|
||||
#define FS_OVERRIDE_WRITE BIT(1)
|
||||
#define WR_2UI_LOCK BIT(2)
|
||||
#define MAX_1UI_WRITE GENMASK(15, 8)
|
||||
#define MAX_2UI_SPDIF_WRITE GENMASK(23, 16)
|
||||
#define MAX_2UI_I2S_HI_WRITE GENMASK(23, 20)
|
||||
#define MAX_2UI_I2S_LFE_CC_SWAP BIT(1)
|
||||
#define MAX_2UI_I2S_LO_WRITE GENMASK(19, 16)
|
||||
#define AUD_ERR_THRESH GENMASK(29, 24)
|
||||
#define I2S2DSD_EN BIT(30)
|
||||
#define AIP_I2S_CTRL 0x410
|
||||
#define FIFO0_MAP GENMASK(1, 0)
|
||||
#define FIFO1_MAP GENMASK(3, 2)
|
||||
#define FIFO2_MAP GENMASK(5, 4)
|
||||
#define FIFO3_MAP GENMASK(7, 6)
|
||||
#define I2S_1ST_BIT_NOSHIFT BIT(8)
|
||||
#define I2S_DATA_DIR_LSB BIT(9)
|
||||
#define JUSTIFY_RIGHT BIT(10)
|
||||
#define WS_HIGH BIT(11)
|
||||
#define VBIT_COMPRESSED BIT(12)
|
||||
#define CBIT_ORDER_SAME BIT(13)
|
||||
#define SCK_EDGE_RISE BIT(14)
|
||||
#define AIP_I2S_CHST0 0x414
|
||||
#define AIP_I2S_CHST1 0x418
|
||||
#define AIP_TXCTRL 0x424
|
||||
#define RST4AUDIO BIT(0)
|
||||
#define RST4AUDIO_FIFO BIT(1)
|
||||
#define RST4AUDIO_ACR BIT(2)
|
||||
#define AUD_LAYOUT_1 BIT(4)
|
||||
#define AUD_MUTE_FIFO_EN BIT(5)
|
||||
#define AUD_PACKET_DROP BIT(6)
|
||||
#define DSD_MUTE_EN BIT(7)
|
||||
#define AIP_TPI_CTRL 0x428
|
||||
#define TPI_AUDIO_LOOKUP_EN BIT(2)
|
||||
|
||||
/* Video downsampling configuration */
|
||||
#define VID_DOWNSAMPLE_CONFIG 0x8d0
|
||||
#define C444_C422_CONFIG_ENABLE BIT(0)
|
||||
#define C422_C420_CONFIG_ENABLE BIT(4)
|
||||
#define C422_C420_CONFIG_BYPASS BIT(5)
|
||||
#define C422_C420_CONFIG_OUT_CB_OR_CR BIT(6)
|
||||
#define VID_OUT_FORMAT 0x8fc
|
||||
#define OUTPUT_FORMAT_DEMUX_420_ENABLE BIT(10)
|
||||
|
||||
/* HDCP registers */
|
||||
#define HDCP_TOP_CTRL 0xc00
|
||||
#define HDCP2X_CTRL_0 0xc20
|
||||
#define HDCP2X_EN BIT(0)
|
||||
#define HDCP2X_ENCRYPT_EN BIT(7)
|
||||
#define HDCP2X_HPD_OVR BIT(10)
|
||||
#define HDCP2X_HPD_SW BIT(11)
|
||||
#define HDCP2X_POL_CTRL 0xc54
|
||||
#define HDCP2X_DIS_POLL_EN BIT(16)
|
||||
#define HDCP1X_CTRL 0xcd0
|
||||
#define HDCP1X_ENC_EN BIT(6)
|
||||
|
||||
/* HDMI DDC registers */
|
||||
#define HPD_DDC_CTRL 0xc08
|
||||
#define HPD_DDC_DELAY_CNT GENMASK(31, 16)
|
||||
#define HPD_DDC_HPD_DBNC_EN BIT(2)
|
||||
#define HPD_DDC_PORD_DBNC_EN BIT(3)
|
||||
#define DDC_CTRL 0xc10
|
||||
#define DDC_CTRL_ADDR GENMASK(7, 1)
|
||||
#define DDC_CTRL_OFFSET GENMASK(15, 8)
|
||||
#define DDC_CTRL_DIN_CNT GENMASK(25, 16)
|
||||
#define DDC_CTRL_CMD GENMASK(31, 28)
|
||||
#define SCDC_CTRL 0xc18
|
||||
#define SCDC_DDC_SEGMENT GENMASK(15, 8)
|
||||
#define HPD_DDC_STATUS 0xc60
|
||||
#define HPD_STATE GENMASK(1, 0)
|
||||
#define HPD_STATE_CONNECTED 2
|
||||
#define HPD_PIN_STA BIT(4)
|
||||
#define PORD_PIN_STA BIT(5)
|
||||
#define DDC_I2C_IN_PROG BIT(13)
|
||||
#define DDC_DATA_OUT GENMASK(23, 16)
|
||||
#define SI2C_CTRL 0xcac
|
||||
#define SI2C_WR BIT(0)
|
||||
#define SI2C_RD BIT(1)
|
||||
#define SI2C_CONFIRM_READ BIT(2)
|
||||
#define SI2C_WDATA GENMASK(15, 8)
|
||||
#define SI2C_ADDR GENMASK(23, 16)
|
||||
|
||||
/* HDCP DDC registers */
|
||||
#define HDCP2X_DDCM_STATUS 0xc68
|
||||
#define DDC_I2C_NO_ACK BIT(10)
|
||||
#define DDC_I2C_BUS_LOW BIT(11)
|
||||
|
||||
/* HDMI TX registers */
|
||||
#define HDMITX_CONFIG_MT8188 0xea0
|
||||
#define HDMITX_CONFIG_MT8195 0x900
|
||||
#define HDMI_YUV420_MODE BIT(10)
|
||||
#define HDMITX_SW_HPD BIT(29)
|
||||
#define HDMITX_SW_RSTB BIT(31)
|
||||
|
||||
/**
|
||||
* enum mtk_hdmi_ddc_v2_cmds - DDC_CMD register commands
|
||||
* @DDC_CMD_READ_NOACK: Current address read with no ACK on last byte
|
||||
* @DDC_CMD_READ: Current address read with ACK on last byte
|
||||
* @DDC_CMD_SEQ_READ_NOACK: Sequential read with no ACK on last byte
|
||||
* @DDC_CMD_SEQ_READ: Sequential read with ACK on last byte
|
||||
* @DDC_CMD_ENH_READ_NOACK: Enhanced read with no ACK on last byte
|
||||
* @DDC_CMD_ENH_READ: Enhanced read with ACK on last byte
|
||||
* @DDC_CMD_SEQ_WRITE_NOACK: Sequential write ignoring ACK on last byte
|
||||
* @DDC_CMD_SEQ_WRITE: Sequential write requiring ACK on last byte
|
||||
* @DDC_CMD_RSVD: Reserved for future use
|
||||
* @DDC_CMD_CLEAR_FIFO: Clear DDC I2C FIFO
|
||||
* @DDC_CMD_CLOCK_SCL: Start clocking DDC I2C SCL
|
||||
* @DDC_CMD_ABORT_XFER: Abort DDC I2C transaction
|
||||
*/
|
||||
enum mtk_hdmi_ddc_v2_cmds {
|
||||
DDC_CMD_READ_NOACK = 0x0,
|
||||
DDC_CMD_READ,
|
||||
DDC_CMD_SEQ_READ_NOACK,
|
||||
DDC_CMD_SEQ_READ,
|
||||
DDC_CMD_ENH_READ_NOACK,
|
||||
DDC_CMD_ENH_READ,
|
||||
DDC_CMD_SEQ_WRITE_NOACK,
|
||||
DDC_CMD_SEQ_WRITE = 0x07,
|
||||
DDC_CMD_CLEAR_FIFO = 0x09,
|
||||
DDC_CMD_CLOCK_SCL = 0x0a,
|
||||
DDC_CMD_ABORT_XFER = 0x0f
|
||||
};
|
||||
|
||||
#endif /* _MTK_HDMI_REGS_H */
|
||||
1398
drivers/gpu/drm/mediatek/mtk_hdmi_v2.c
Normal file
1398
drivers/gpu/drm/mediatek/mtk_hdmi_v2.c
Normal file
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user