From 1de8493069b8f510e586242c1b4329cd3c9b6fb9 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Mon, 10 Feb 2020 18:06:53 +0100 Subject: [PATCH 1/8] clk: sunxi-ng: a64: Export MBUS clock MBUS clock will be referenced in MBUS controller node. Export it. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- drivers/clk/sunxi-ng/ccu-sun50i-a64.h | 4 ---- include/dt-bindings/clock/sun50i-a64-ccu.h | 2 +- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.h b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h index 116e6f826d04..54d1f96f4b68 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.h +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h @@ -55,10 +55,6 @@ /* All the DRAM gates are exported */ -/* Some more module clocks are exported */ - -#define CLK_MBUS 112 - /* And the DSI and GPU module clock is exported */ #define CLK_NUMBER (CLK_GPU + 1) diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h index e512a1c9b0fc..318eb15c414c 100644 --- a/include/dt-bindings/clock/sun50i-a64-ccu.h +++ b/include/dt-bindings/clock/sun50i-a64-ccu.h @@ -131,7 +131,7 @@ #define CLK_AVS 109 #define CLK_HDMI 110 #define CLK_HDMI_DDC 111 - +#define CLK_MBUS 112 #define CLK_DSI_DPHY 113 #define CLK_GPU 114 From 2b48dcb7a821fc38e0be3e171bd02e058196ccf1 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Tue, 11 Feb 2020 19:59:30 +0100 Subject: [PATCH 2/8] clk: sunxi-ng: sun8i-de2: Split out H5 definitions H5 has less clocks and resets than A64. Currently that's not obvious because A64 is missing rotation core related clocks and reset. Split out H5 definition. A64 structures will be fixed in subsequent commit. Note that this patch depends on commit 19368d99746e ("clk: sunxi-ng: add support for Allwinner H3 DE2 CCU") for the H3 clock list. Fixes: 763c5bd045b1 ("clk: sunxi-ng: add support for DE2 CCU") Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c index d9668493c3f9..2478ae314d0f 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c @@ -192,6 +192,12 @@ static struct ccu_reset_map sun50i_a64_de2_resets[] = { [RST_WB] = { 0x08, BIT(2) }, }; +static struct ccu_reset_map sun50i_h5_de2_resets[] = { + [RST_MIXER0] = { 0x08, BIT(0) }, + [RST_MIXER1] = { 0x08, BIT(1) }, + [RST_WB] = { 0x08, BIT(2) }, +}; + static struct ccu_reset_map sun50i_h6_de3_resets[] = { [RST_MIXER0] = { 0x08, BIT(0) }, [RST_MIXER1] = { 0x08, BIT(1) }, @@ -229,6 +235,16 @@ static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = { .num_resets = ARRAY_SIZE(sun50i_a64_de2_resets), }; +static const struct sunxi_ccu_desc sun50i_h5_de2_clk_desc = { + .ccu_clks = sun8i_h3_de2_clks, + .num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks), + + .hw_clks = &sun8i_h3_de2_hw_clks, + + .resets = sun50i_h5_de2_resets, + .num_resets = ARRAY_SIZE(sun50i_h5_de2_resets), +}; + static const struct sunxi_ccu_desc sun50i_h6_de3_clk_desc = { .ccu_clks = sun50i_h6_de3_clks, .num_ccu_clks = ARRAY_SIZE(sun50i_h6_de3_clks), @@ -347,7 +363,7 @@ static const struct of_device_id sunxi_de2_clk_ids[] = { }, { .compatible = "allwinner,sun50i-h5-de2-clk", - .data = &sun50i_a64_de2_clk_desc, + .data = &sun50i_h5_de2_clk_desc, }, { .compatible = "allwinner,sun50i-h6-de3-clk", From b4bbce660a3694811b5500c40b9cd69513b50d38 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Tue, 11 Feb 2020 19:59:31 +0100 Subject: [PATCH 3/8] clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A64 A64 has rotation core which needs clocks and reset. Because there is no appropriate structures available, make a separate, A64 specific structures. Fixes: cf4881c12935 ("clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCU") Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 45 ++++++++++++++++++++++++++-- 1 file changed, 42 insertions(+), 3 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c index 2478ae314d0f..c6220be8e205 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c @@ -108,6 +108,24 @@ static struct ccu_common *sun8i_v3s_de2_clks[] = { &wb_div_clk.common, }; +static struct ccu_common *sun50i_a64_de2_clks[] = { + &mixer0_clk.common, + &mixer1_clk.common, + &wb_clk.common, + + &bus_mixer0_clk.common, + &bus_mixer1_clk.common, + &bus_wb_clk.common, + + &mixer0_div_clk.common, + &mixer1_div_clk.common, + &wb_div_clk.common, + + &bus_rot_clk.common, + &rot_clk.common, + &rot_div_clk.common, +}; + static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = { .hws = { [CLK_MIXER0] = &mixer0_clk.common.hw, @@ -156,6 +174,26 @@ static struct clk_hw_onecell_data sun8i_v3s_de2_hw_clks = { .num = CLK_NUMBER_WITHOUT_ROT, }; +static struct clk_hw_onecell_data sun50i_a64_de2_hw_clks = { + .hws = { + [CLK_MIXER0] = &mixer0_clk.common.hw, + [CLK_MIXER1] = &mixer1_clk.common.hw, + [CLK_WB] = &wb_clk.common.hw, + [CLK_ROT] = &rot_clk.common.hw, + + [CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw, + [CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw, + [CLK_BUS_WB] = &bus_wb_clk.common.hw, + [CLK_BUS_ROT] = &bus_rot_clk.common.hw, + + [CLK_MIXER0_DIV] = &mixer0_div_clk.common.hw, + [CLK_MIXER1_DIV] = &mixer1_div_clk.common.hw, + [CLK_WB_DIV] = &wb_div_clk.common.hw, + [CLK_ROT_DIV] = &rot_div_clk.common.hw, + }, + .num = CLK_NUMBER_WITH_ROT, +}; + static struct clk_hw_onecell_data sun50i_h6_de3_hw_clks = { .hws = { [CLK_MIXER0] = &mixer0_clk.common.hw, @@ -190,6 +228,7 @@ static struct ccu_reset_map sun50i_a64_de2_resets[] = { [RST_MIXER0] = { 0x08, BIT(0) }, [RST_MIXER1] = { 0x08, BIT(1) }, [RST_WB] = { 0x08, BIT(2) }, + [RST_ROT] = { 0x08, BIT(3) }, }; static struct ccu_reset_map sun50i_h5_de2_resets[] = { @@ -226,10 +265,10 @@ static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = { }; static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = { - .ccu_clks = sun8i_h3_de2_clks, - .num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks), + .ccu_clks = sun50i_a64_de2_clks, + .num_ccu_clks = ARRAY_SIZE(sun50i_a64_de2_clks), - .hw_clks = &sun8i_h3_de2_hw_clks, + .hw_clks = &sun50i_a64_de2_hw_clks, .resets = sun50i_a64_de2_resets, .num_resets = ARRAY_SIZE(sun50i_a64_de2_resets), From 75250eb75c828eebda77e23f44de0f037546ea9a Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Tue, 11 Feb 2020 19:59:32 +0100 Subject: [PATCH 4/8] clk: sunxi-ng: sun8i-de2: H6 doesn't have rotate core DE3 documentation regarding presence of rotate core in H6 is a bit confusing. Register descriptions mention bits for enabling rotate core clocks and reset, but general overview doesn't list it as feature of H6 display engine, BSP kernel doesn't support it and there is no interrupt listed for it. Manual poking registers also didn't reveal presence of rotate core. Let's assume there isn't any rotate core on H6 present and remove related clocks. With that done, structures are same as those for H5, so just reuse H5 structure. Fixes: 56808da9f97f ("clk: sunxi-ng: Add support for H6 DE3 clocks") Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 57 +--------------------------- 1 file changed, 1 insertion(+), 56 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c index c6220be8e205..87a30d072ae9 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c @@ -51,24 +51,6 @@ static SUNXI_CCU_M(mixer1_div_a83_clk, "mixer1-div", "pll-de", 0x0c, 4, 4, static SUNXI_CCU_M(wb_div_a83_clk, "wb-div", "pll-de", 0x0c, 8, 4, CLK_SET_RATE_PARENT); -static struct ccu_common *sun50i_h6_de3_clks[] = { - &mixer0_clk.common, - &mixer1_clk.common, - &wb_clk.common, - - &bus_mixer0_clk.common, - &bus_mixer1_clk.common, - &bus_wb_clk.common, - - &mixer0_div_clk.common, - &mixer1_div_clk.common, - &wb_div_clk.common, - - &bus_rot_clk.common, - &rot_clk.common, - &rot_div_clk.common, -}; - static struct ccu_common *sun8i_a83t_de2_clks[] = { &mixer0_clk.common, &mixer1_clk.common, @@ -194,26 +176,6 @@ static struct clk_hw_onecell_data sun50i_a64_de2_hw_clks = { .num = CLK_NUMBER_WITH_ROT, }; -static struct clk_hw_onecell_data sun50i_h6_de3_hw_clks = { - .hws = { - [CLK_MIXER0] = &mixer0_clk.common.hw, - [CLK_MIXER1] = &mixer1_clk.common.hw, - [CLK_WB] = &wb_clk.common.hw, - [CLK_ROT] = &rot_clk.common.hw, - - [CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw, - [CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw, - [CLK_BUS_WB] = &bus_wb_clk.common.hw, - [CLK_BUS_ROT] = &bus_rot_clk.common.hw, - - [CLK_MIXER0_DIV] = &mixer0_div_clk.common.hw, - [CLK_MIXER1_DIV] = &mixer1_div_clk.common.hw, - [CLK_WB_DIV] = &wb_div_clk.common.hw, - [CLK_ROT_DIV] = &rot_div_clk.common.hw, - }, - .num = CLK_NUMBER_WITH_ROT, -}; - static struct ccu_reset_map sun8i_a83t_de2_resets[] = { [RST_MIXER0] = { 0x08, BIT(0) }, /* @@ -237,13 +199,6 @@ static struct ccu_reset_map sun50i_h5_de2_resets[] = { [RST_WB] = { 0x08, BIT(2) }, }; -static struct ccu_reset_map sun50i_h6_de3_resets[] = { - [RST_MIXER0] = { 0x08, BIT(0) }, - [RST_MIXER1] = { 0x08, BIT(1) }, - [RST_WB] = { 0x08, BIT(2) }, - [RST_ROT] = { 0x08, BIT(3) }, -}; - static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = { .ccu_clks = sun8i_a83t_de2_clks, .num_ccu_clks = ARRAY_SIZE(sun8i_a83t_de2_clks), @@ -284,16 +239,6 @@ static const struct sunxi_ccu_desc sun50i_h5_de2_clk_desc = { .num_resets = ARRAY_SIZE(sun50i_h5_de2_resets), }; -static const struct sunxi_ccu_desc sun50i_h6_de3_clk_desc = { - .ccu_clks = sun50i_h6_de3_clks, - .num_ccu_clks = ARRAY_SIZE(sun50i_h6_de3_clks), - - .hw_clks = &sun50i_h6_de3_hw_clks, - - .resets = sun50i_h6_de3_resets, - .num_resets = ARRAY_SIZE(sun50i_h6_de3_resets), -}; - static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = { .ccu_clks = sun8i_v3s_de2_clks, .num_ccu_clks = ARRAY_SIZE(sun8i_v3s_de2_clks), @@ -406,7 +351,7 @@ static const struct of_device_id sunxi_de2_clk_ids[] = { }, { .compatible = "allwinner,sun50i-h6-de3-clk", - .data = &sun50i_h6_de3_clk_desc, + .data = &sun50i_h5_de2_clk_desc, }, { } }; From 8f9b11a33ad6976e17e7279a170864a1fc613803 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Tue, 11 Feb 2020 19:59:33 +0100 Subject: [PATCH 5/8] clk: sunxi-ng: sun8i-de2: Don't reuse A83T resets Currently, V3s and H3 reuse A83T reset structure. However, A83T contains additional core for rotation, which is not present in V3s and H3. Make new reset structure for H3 and let V3s reuse it. A83T reset structure will be amended in subsequent commit. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c index 87a30d072ae9..bbbe1ed7aba1 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c @@ -179,9 +179,18 @@ static struct clk_hw_onecell_data sun50i_a64_de2_hw_clks = { static struct ccu_reset_map sun8i_a83t_de2_resets[] = { [RST_MIXER0] = { 0x08, BIT(0) }, /* - * For A83T, H3 and R40, mixer1 reset line is shared with wb, so - * only RST_WB is exported here. - * For V3s there's just no mixer1, so it also shares this struct. + * Mixer1 reset line is shared with wb, so only RST_WB is + * exported here. + */ + [RST_WB] = { 0x08, BIT(2) }, +}; + +static struct ccu_reset_map sun8i_h3_de2_resets[] = { + [RST_MIXER0] = { 0x08, BIT(0) }, + /* + * Mixer1 reset line is shared with wb, so only RST_WB is + * exported here. + * V3s doesn't have mixer1, so it also shares this struct. */ [RST_WB] = { 0x08, BIT(2) }, }; @@ -215,8 +224,8 @@ static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = { .hw_clks = &sun8i_h3_de2_hw_clks, - .resets = sun8i_a83t_de2_resets, - .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets), + .resets = sun8i_h3_de2_resets, + .num_resets = ARRAY_SIZE(sun8i_h3_de2_resets), }; static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = { @@ -245,8 +254,8 @@ static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = { .hw_clks = &sun8i_v3s_de2_hw_clks, - .resets = sun8i_a83t_de2_resets, - .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets), + .resets = sun8i_h3_de2_resets, + .num_resets = ARRAY_SIZE(sun8i_h3_de2_resets), }; static int sunxi_de2_clk_probe(struct platform_device *pdev) From b0bfba905cf81d540acaac7a4b23459f7df1bb24 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Tue, 11 Feb 2020 19:59:34 +0100 Subject: [PATCH 6/8] clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A83T A83T structures don't have clocks and reset for rotation core. Add them. Fixes: 763c5bd045b1 ("clk: sunxi-ng: add support for DE2 CCU") Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c index bbbe1ed7aba1..9656553c01f3 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c @@ -50,6 +50,8 @@ static SUNXI_CCU_M(mixer1_div_a83_clk, "mixer1-div", "pll-de", 0x0c, 4, 4, CLK_SET_RATE_PARENT); static SUNXI_CCU_M(wb_div_a83_clk, "wb-div", "pll-de", 0x0c, 8, 4, CLK_SET_RATE_PARENT); +static SUNXI_CCU_M(rot_div_a83_clk, "rot-div", "pll-de", 0x0c, 0x0c, 4, + CLK_SET_RATE_PARENT); static struct ccu_common *sun8i_a83t_de2_clks[] = { &mixer0_clk.common, @@ -63,6 +65,10 @@ static struct ccu_common *sun8i_a83t_de2_clks[] = { &mixer0_div_a83_clk.common, &mixer1_div_a83_clk.common, &wb_div_a83_clk.common, + + &bus_rot_clk.common, + &rot_clk.common, + &rot_div_a83_clk.common, }; static struct ccu_common *sun8i_h3_de2_clks[] = { @@ -113,16 +119,19 @@ static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = { [CLK_MIXER0] = &mixer0_clk.common.hw, [CLK_MIXER1] = &mixer1_clk.common.hw, [CLK_WB] = &wb_clk.common.hw, + [CLK_ROT] = &rot_clk.common.hw, [CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw, [CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw, [CLK_BUS_WB] = &bus_wb_clk.common.hw, + [CLK_BUS_ROT] = &bus_rot_clk.common.hw, [CLK_MIXER0_DIV] = &mixer0_div_a83_clk.common.hw, [CLK_MIXER1_DIV] = &mixer1_div_a83_clk.common.hw, [CLK_WB_DIV] = &wb_div_a83_clk.common.hw, + [CLK_ROT_DIV] = &rot_div_a83_clk.common.hw, }, - .num = CLK_NUMBER_WITHOUT_ROT, + .num = CLK_NUMBER_WITH_ROT, }; static struct clk_hw_onecell_data sun8i_h3_de2_hw_clks = { @@ -183,6 +192,7 @@ static struct ccu_reset_map sun8i_a83t_de2_resets[] = { * exported here. */ [RST_WB] = { 0x08, BIT(2) }, + [RST_ROT] = { 0x08, BIT(3) }, }; static struct ccu_reset_map sun8i_h3_de2_resets[] = { From 11d0c436ffed1dba397e9adec9eaebfe7eef2d10 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Tue, 11 Feb 2020 19:59:35 +0100 Subject: [PATCH 7/8] clk: sunxi-ng: sun8i-de2: Add R40 specific quirks R40 is actually very similar to A64, but it doesn't have mixer1 reset. This means it's clocks and resets combination is unique and R40 specific quirks are needed. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c index 9656553c01f3..5a278c391f1d 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c @@ -238,6 +238,16 @@ static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = { .num_resets = ARRAY_SIZE(sun8i_h3_de2_resets), }; +static const struct sunxi_ccu_desc sun8i_r40_de2_clk_desc = { + .ccu_clks = sun50i_a64_de2_clks, + .num_ccu_clks = ARRAY_SIZE(sun50i_a64_de2_clks), + + .hw_clks = &sun50i_a64_de2_hw_clks, + + .resets = sun8i_a83t_de2_resets, + .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets), +}; + static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = { .ccu_clks = sun50i_a64_de2_clks, .num_ccu_clks = ARRAY_SIZE(sun50i_a64_de2_clks), @@ -356,6 +366,10 @@ static const struct of_device_id sunxi_de2_clk_ids[] = { .compatible = "allwinner,sun8i-h3-de2-clk", .data = &sun8i_h3_de2_clk_desc, }, + { + .compatible = "allwinner,sun8i-r40-de2-clk", + .data = &sun8i_r40_de2_clk_desc, + }, { .compatible = "allwinner,sun8i-v3s-de2-clk", .data = &sun8i_v3s_de2_clk_desc, From b998b75f8603c37c8a43a3d849cd2c4929adf402 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Tue, 11 Feb 2020 19:59:36 +0100 Subject: [PATCH 8/8] clk: sunxi-ng: sun8i-de2: Sort structures V3s quirks are not in right place. Move it. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c index 5a278c391f1d..524f33275bc7 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c @@ -248,6 +248,16 @@ static const struct sunxi_ccu_desc sun8i_r40_de2_clk_desc = { .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets), }; +static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = { + .ccu_clks = sun8i_v3s_de2_clks, + .num_ccu_clks = ARRAY_SIZE(sun8i_v3s_de2_clks), + + .hw_clks = &sun8i_v3s_de2_hw_clks, + + .resets = sun8i_a83t_de2_resets, + .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets), +}; + static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = { .ccu_clks = sun50i_a64_de2_clks, .num_ccu_clks = ARRAY_SIZE(sun50i_a64_de2_clks), @@ -268,16 +278,6 @@ static const struct sunxi_ccu_desc sun50i_h5_de2_clk_desc = { .num_resets = ARRAY_SIZE(sun50i_h5_de2_resets), }; -static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = { - .ccu_clks = sun8i_v3s_de2_clks, - .num_ccu_clks = ARRAY_SIZE(sun8i_v3s_de2_clks), - - .hw_clks = &sun8i_v3s_de2_hw_clks, - - .resets = sun8i_h3_de2_resets, - .num_resets = ARRAY_SIZE(sun8i_h3_de2_resets), -}; - static int sunxi_de2_clk_probe(struct platform_device *pdev) { struct resource *res;