mirrors/linux
2
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-05-24 01:31:46 -04:00
Code Issues Packages Projects Releases Wiki Activity

drm/i915: add vlv_clock_get_czclk()

Browse Source 
Add vlv_clock_get_czclk() helper to avoid looking at i915->czclk_freq
directly.

Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://lore.kernel.org/r/4885f6e486a31c773a3bfebd6936670234e57bd0.1757688216.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula
2025-09-12 17:48:43 +03:00
parent 01c46fcef5
commit 8c2833ff1d
5 changed files with 20 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/i915/display/intel_cdclk.c
View File

@@ -627,7 +627,6 @@ static void vlv_get_cdclk(struct intel_display *display,
static void vlv_program_pfi_credits(struct intel_display *display)
{
struct drm_i915_private *dev_priv = to_i915(display->drm);
unsigned int credits, default_credits;
if (display->platform.cherryview)
@@ -635,7 +634,7 @@ static void vlv_program_pfi_credits(struct intel_display *display)
else
default_credits = PFI_CREDIT(8);
if (display->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
if (display->cdclk.hw.cdclk >= vlv_clock_get_czclk(display->drm)) {
/* CHV suggested value is 31 or 63 */
if (display->platform.cherryview)
credits = PFI_CREDIT_63;

20
drivers/gpu/drm/i915/display/intel_display.c
View File

@@ -190,25 +190,33 @@ int vlv_get_cck_clock_hpll(struct drm_device *drm,
return hpll;
}
int vlv_clock_get_gpll(struct drm_device *drm)
int vlv_clock_get_czclk(struct drm_device *drm)
{
struct drm_i915_private *i915 = to_i915(drm);
if (!i915->czclk_freq)
i915->czclk_freq = vlv_get_cck_clock_hpll(drm, "czclk",
CCK_CZ_CLOCK_CONTROL);
return i915->czclk_freq;
}
int vlv_clock_get_gpll(struct drm_device *drm)
{
return vlv_get_cck_clock(drm, "GPLL ref", CCK_GPLL_CLOCK_CONTROL,
i915->czclk_freq);
vlv_clock_get_czclk(drm));
}
void intel_update_czclk(struct intel_display *display)
{
struct drm_i915_private *dev_priv = to_i915(display->drm);
int czclk_freq;
if (!display->platform.valleyview && !display->platform.cherryview)
return;
dev_priv->czclk_freq = vlv_get_cck_clock_hpll(display->drm, "czclk",
CCK_CZ_CLOCK_CONTROL);
czclk_freq = vlv_clock_get_czclk(display->drm);
drm_dbg_kms(display->drm, "CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
drm_dbg_kms(display->drm, "CZ clock rate: %d kHz\n", czclk_freq);
}
static bool is_hdr_mode(const struct intel_crtc_state *crtc_state)

1
drivers/gpu/drm/i915/display/intel_display.h
View File

@@ -440,6 +440,7 @@ int vlv_get_cck_clock(struct drm_device *drm,
const char *name, u32 reg, int ref_freq);
int vlv_get_cck_clock_hpll(struct drm_device *drm,
const char *name, u32 reg);
int vlv_clock_get_czclk(struct drm_device *drm);
int vlv_clock_get_gpll(struct drm_device *drm);
bool intel_has_pending_fb_unpin(struct intel_display *display);
void intel_encoder_destroy(struct drm_encoder *encoder);

3
drivers/gpu/drm/i915/gt/intel_rc6.c
View File

@@ -6,6 +6,7 @@
#include <linux/pm_runtime.h>
#include <linux/string_helpers.h>
#include "display/intel_display.h"
#include "gem/i915_gem_region.h"
#include "i915_drv.h"
#include "i915_reg.h"
@@ -802,7 +803,7 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, enum intel_rc6_res_type id)
/* On VLV and CHV, residency time is in CZ units rather than 1.28us */
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
mul = 1000000;
div = i915->czclk_freq;
div = vlv_clock_get_czclk(&i915->drm);
overflow_hw = BIT_ULL(40);
time_hw = vlv_residency_raw(uncore, reg);
} else {

3
drivers/gpu/drm/i915/gt/intel_rps.c
View File

@@ -1777,6 +1777,7 @@ static void vlv_c0_read(struct intel_uncore *uncore, struct intel_rps_ei *ei)
static u32 vlv_wa_c0_ei(struct intel_rps *rps, u32 pm_iir)
{
struct drm_i915_private *i915 = rps_to_i915(rps);
struct intel_uncore *uncore = rps_to_uncore(rps);
const struct intel_rps_ei *prev = &rps->ei;
struct intel_rps_ei now;
@@ -1793,7 +1794,7 @@ static u32 vlv_wa_c0_ei(struct intel_rps *rps, u32 pm_iir)
time = ktime_us_delta(now.ktime, prev->ktime);
time *= rps_to_i915(rps)->czclk_freq;
time *= vlv_clock_get_czclk(&i915->drm);
/* Workload can be split between render + media,
* e.g. SwapBuffers being blitted in X after being rendered in