From d9abae3ca5e8fa30fe5074aafd52a5bdfb8b2ed8 Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Tue, 2 Feb 2016 11:40:50 +0800 Subject: [PATCH 01/27] ARM: dts: rockchip: add vop device node for rk3036 The rk3036 support two overlay plane and one hwc plane, it supports IOMMU, and its IOMMU same as rk3288's. Signed-off-by: Caesar Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index d0f4bb7e1e50..4932abf2a784 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -119,6 +119,11 @@ arm-pmu { interrupt-affinity = <&cpu0>, <&cpu1>; }; + display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + timer { compatible = "arm,armv7-timer"; arm,cpu-registers-not-fw-configured; @@ -149,6 +154,32 @@ smp-sram@0 { }; }; + vop: vop@10118000 { + compatible = "rockchip,rk3036-vop"; + reg = <0x10118000 0x19c>; + interrupts = ; + clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>; + reset-names = "axi", "ahb", "dclk"; + iommus = <&vop_mmu>; + status = "disabled"; + + vop_out: port { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + vop_mmu: iommu@10118300 { + compatible = "rockchip,iommu"; + reg = <0x10118300 0x100>; + interrupts = ; + interrupt-names = "vop_mmu"; + #iommu-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@10139000 { compatible = "arm,gic-400"; interrupt-controller; From b7217cf19c633dc542ba4980f8fa34933ca1d343 Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Tue, 2 Feb 2016 11:40:50 +0800 Subject: [PATCH 02/27] ARM: dts: rockchip: add hdmi device node for rk3036 Add the Innosilicon hdmi node for HDMI display. Signed-off-by: Caesar Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036.dtsi | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index 4932abf2a784..8139fbf3de7f 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -168,6 +168,10 @@ vop: vop@10118000 { vop_out: port { #address-cells = <1>; #size-cells = <0>; + vop_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vop>; + }; }; }; @@ -328,6 +332,27 @@ acodec: acodec-ana@20030000 { status = "disabled"; }; + hdmi: hdmi@20034000 { + compatible = "rockchip,rk3036-inno-hdmi"; + reg = <0x20034000 0x4000>; + interrupts = ; + clocks = <&cru PCLK_HDMI>; + clock-names = "pclk"; + rockchip,grf = <&grf>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_ctl>; + status = "disabled"; + + hdmi_in: port { + #address-cells = <1>; + #size-cells = <0>; + hdmi_in_vop: endpoint@0 { + reg = <0>; + remote-endpoint = <&vop_out_hdmi>; + }; + }; + }; + timer: timer@20044000 { compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer"; reg = <0x20044000 0x20>; @@ -675,6 +700,15 @@ i2s_bus: i2s-bus { }; }; + hdmi { + hdmi_ctl: hdmi-ctl { + rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>, + <1 9 RK_FUNC_1 &pcfg_pull_none>, + <1 10 RK_FUNC_1 &pcfg_pull_none>, + <1 11 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + uart0 { uart0_xfer: uart0-xfer { rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>, From cef0abefa146877019e63c4e6ae439d40d01804f Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Tue, 2 Feb 2016 11:40:50 +0800 Subject: [PATCH 03/27] ARM: dts: rockchip: enable graphics support on rk3036-kylin Enable the recently added vop and hdmi nodes on the rk3036-kylin board. Signed-off-by: Caesar Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036-kylin.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts index 6251d109eff4..01dd4a805c81 100644 --- a/arch/arm/boot/dts/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rk3036-kylin.dts @@ -130,6 +130,10 @@ &emmc { status = "okay"; }; +&hdmi { + status = "okay"; +}; + &i2c1 { clock-frequency = <400000>; @@ -385,6 +389,14 @@ &usb_otg { status = "okay"; }; +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + &pinctrl { leds { led_ctl: led-ctl { From 5415ba40650900f7d663a4b79f346c45dddd4ce0 Mon Sep 17 00:00:00 2001 From: John Keeping Date: Tue, 23 Feb 2016 13:40:59 +0000 Subject: [PATCH 04/27] ARM: dts: rockchip: fix MIPI interrupt on rk3288 This isn't currently used by the driver but the correct value is 19 since DSIHOST0 is 51 in the TRM and the GIC offset requires 32 to be subtracted. Signed-off-by: John Keeping Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 31f7e20ef418..872ccf01d509 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -878,7 +878,7 @@ vopl_mmu: iommu@ff940300 { mipi_dsi: mipi@ff960000 { compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0xff960000 0x4000>; - interrupts = ; + interrupts = ; clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; clock-names = "ref", "pclk"; rockchip,grf = <&grf>; From 57dcfa56138c883905a265979cc84ef69675ae00 Mon Sep 17 00:00:00 2001 From: John Keeping Date: Tue, 23 Feb 2016 13:41:00 +0000 Subject: [PATCH 05/27] ARM: dts: rockchip: fix audio interrupts on rk3288 These must be translated from the values in the TRM by subtracting 32, which has not been done. The SPDIF interrupt is also off-by-one. Signed-off-by: John Keeping Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 872ccf01d509..e6e181387630 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -765,7 +765,7 @@ spdif: sound@ff88b0000 { clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>; dmas = <&dmac_bus_s 3>; dma-names = "tx"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&spdif_tx>; rockchip,grf = <&grf>; @@ -775,7 +775,7 @@ spdif: sound@ff88b0000 { i2s: i2s@ff890000 { compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; reg = <0xff890000 0x10000>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; From 1946a201b3963b78a9e2123aedbdd11c4c4849dd Mon Sep 17 00:00:00 2001 From: John Keeping Date: Tue, 23 Feb 2016 12:39:41 +0000 Subject: [PATCH 06/27] ARM: dts: rockchip: add mipi_dsi to VIO power domain on rk3288 The MIPI controllers are part of the VIO power domain so add the necessary property to indicate this for the controller we support. Signed-off-by: John Keeping Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index e6e181387630..74eae995c330 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -881,6 +881,7 @@ mipi_dsi: mipi@ff960000 { interrupts = ; clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; clock-names = "ref", "pclk"; + power-domains = <&power RK3288_PD_VIO>; rockchip,grf = <&grf>; #address-cells = <1>; #size-cells = <0>; From fe95effb4c381355e38f5bffced4917a2b6dc7d3 Mon Sep 17 00:00:00 2001 From: Jianqun Xu Date: Tue, 23 Feb 2016 15:01:01 +0800 Subject: [PATCH 07/27] dt-bindings: add bindings for Rockchip grf Add devicetree bindings for Rockchip grf which found on Rockchip SoCs. Signed-off-by: Jianqun Xu Acked-by: Rob Herring Signed-off-by: Heiko Stuebner --- .../devicetree/bindings/soc/rockchip/grf.txt | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/rockchip/grf.txt diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.txt b/Documentation/devicetree/bindings/soc/rockchip/grf.txt new file mode 100644 index 000000000000..013e71a2cdc7 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.txt @@ -0,0 +1,35 @@ +* Rockchip General Register Files (GRF) + +The general register file will be used to do static set by software, which +is composed of many registers for system control. + +From RK3368 SoCs, the GRF is divided into two sections, +- GRF, used for general non-secure system, +- PMUGRF, used for always on system + +Required Properties: + +- compatible: GRF should be one of the followings + - "rockchip,rk3066-grf", "syscon": for rk3066 + - "rockchip,rk3188-grf", "syscon": for rk3188 + - "rockchip,rk3228-grf", "syscon": for rk3228 + - "rockchip,rk3288-grf", "syscon": for rk3288 + - "rockchip,rk3368-grf", "syscon": for rk3368 + - "rockchip,rk3399-grf", "syscon": for rk3399 +- compatible: PMUGRF should be one of the followings + - "rockchip,rk3368-pmugrf", "syscon": for rk3368 + - "rockchip,rk3399-pmugrf", "syscon": for rk3399 +- reg: physical base address of the controller and length of memory mapped + region. + +Example: GRF and PMUGRF of RK3399 SoCs + + pmugrf: syscon@ff320000 { + compatible = "rockchip,rk3399-pmugrf", "syscon"; + reg = <0x0 0xff320000 0x0 0x1000>; + }; + + grf: syscon@ff770000 { + compatible = "rockchip,rk3399-grf", "syscon"; + reg = <0x0 0xff770000 0x0 0x10000>; + }; From 7796031eec9e41099af35bc531f04843358fa3f1 Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Mon, 15 Feb 2016 15:33:32 +0800 Subject: [PATCH 08/27] ARM: dts: rockchip: add the thermal main info found on rk3228 This patch adds the thermal needed main information for rk3228 SoCS. Basically has the following content: 1) TSADC controller: Add the needed attributes for rk3036 TSADC controller. Especially for the TSHUT, in some cases if we are unable to shut it down in orderly fashion (says: kernel is stuck holding a lock or similar), then hardware TSHUT will reset it. If the temperature is over 95C over a period of time the thermal shutdown of the tsadc is invoked with can either reset the entire chip via the CRU, or notify the PMIC via a GPIO. This should be set in the specific board. 2) Thermal zones: Add the needed device mode for thermal generic framework. Detail in Documentation/devicetree/bindings/thermal/thermal.txt. Signed-off-by: Caesar Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3228.dtsi | 69 +++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm/boot/dts/rk3228.dtsi b/arch/arm/boot/dts/rk3228.dtsi index 4dae42a01509..f9c34124ccc3 100644 --- a/arch/arm/boot/dts/rk3228.dtsi +++ b/arch/arm/boot/dts/rk3228.dtsi @@ -43,6 +43,7 @@ #include #include #include +#include #include "skeleton.dtsi" / { @@ -69,6 +70,7 @@ cpu0: cpu@f00 { /* KHz uV */ 816000 1000000 >; + #cooling-cells = <2>; /* min followed by max */ clock-latency = <40000>; clocks = <&cru ARMCLK>; }; @@ -247,6 +249,63 @@ cru: clock-controller@110e0000 { assigned-clock-rates = <594000000>; }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 0>; + + trips { + cpu_alert0: cpu_alert0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert1: cpu_alert1 { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT 6>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + tsadc: tsadc@11150000 { + compatible = "rockchip,rk3228-tsadc"; + reg = <0x11150000 0x100>; + interrupts = ; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + resets = <&cru SRST_TSADC>; + reset-names = "tsadc-apb"; + pinctrl-names = "init", "default", "sleep"; + pinctrl-0 = <&otp_gpio>; + pinctrl-1 = <&otp_out>; + pinctrl-2 = <&otp_gpio>; + #thermal-sensor-cells = <0>; + rockchip,hw-tshut-temp = <95000>; + status = "disabled"; + }; + emmc: dwmmc@30020000 { compatible = "rockchip,rk3288-dw-mshc"; reg = <0x30020000 0x4000>; @@ -394,6 +453,16 @@ pwm3_pin: pwm3-pin { }; }; + tsadc { + otp_gpio: otp-gpio { + rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otp_out: otp-out { + rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + uart0 { uart0_xfer: uart0-xfer { rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>, From 26f5e19dfb07de627112074721f254482f941dab Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Mon, 15 Feb 2016 15:33:33 +0800 Subject: [PATCH 09/27] ARM: dts: rockchip: enable the tsadc for rk3228 evb This patch enables the tsadc for rk3228 evb board. The rk3228 evb board uses the CRU to reset the chip since it hasn't the PMIC to connect it, and TSHUT is low active on evb board. Signed-off-by: Caesar Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3228-evb.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/rk3228-evb.dts b/arch/arm/boot/dts/rk3228-evb.dts index e3898b810150..c75cc41d8c1f 100644 --- a/arch/arm/boot/dts/rk3228-evb.dts +++ b/arch/arm/boot/dts/rk3228-evb.dts @@ -61,6 +61,13 @@ &emmc { status = "okay"; }; +&tsadc { + status = "okay"; + + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ +}; + &uart2 { status = "okay"; }; From 57375d88fa3f6bf9351051529464c708f72adb1d Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Tue, 26 Jan 2016 10:06:43 +0800 Subject: [PATCH 10/27] ARM: dts: rockchip: remove broken-cd from emmc and sdio Only one of "broken-cd" and "non-removable" should be supplied according to Documentation/devicetree/bindings/mmc/mmc.txt. Obviously emmc and sdio-wifi are non-removable devices, while broken-cd is for removable device whose card detect pin is broken. Signed-off-by: Shawn Lin Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036-kylin.dts | 1 - arch/arm/boot/dts/rk3036.dtsi | 1 - arch/arm/boot/dts/rk3066a-rayeager.dts | 2 -- arch/arm/boot/dts/rk3228-evb.dts | 1 - arch/arm/boot/dts/rk3288-evb.dtsi | 1 - arch/arm/boot/dts/rk3288-firefly.dtsi | 2 -- arch/arm/boot/dts/rk3288-popmetal.dts | 1 - arch/arm/boot/dts/rk3288-veyron.dtsi | 2 -- 8 files changed, 11 deletions(-) diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts index 01dd4a805c81..951f15d675c7 100644 --- a/arch/arm/boot/dts/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rk3036-kylin.dts @@ -345,7 +345,6 @@ &i2s { &sdio { status = "okay"; - broken-cd; bus-width = <4>; cap-sd-highspeed; cap-sdio-irq; diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index 8139fbf3de7f..fa6b5cf31aa7 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -272,7 +272,6 @@ emmc: dwmmc@1021c000 { compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x1021c000 0x4000>; interrupts = ; - broken-cd; bus-width = <8>; cap-mmc-highspeed; clock-frequency = <37500000>; diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts index 05533005a809..3a5989b1724a 100644 --- a/arch/arm/boot/dts/rk3066a-rayeager.dts +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts @@ -182,7 +182,6 @@ phy0: ethernet-phy@0 { }; &emmc { - broken-cd; bus-width = <8>; cap-mmc-highspeed; disable-wp; @@ -348,7 +347,6 @@ &mmc0 { }; &mmc1 { - broken-cd; bus-width = <4>; disable-wp; non-removable; diff --git a/arch/arm/boot/dts/rk3228-evb.dts b/arch/arm/boot/dts/rk3228-evb.dts index c75cc41d8c1f..5956e8246abe 100644 --- a/arch/arm/boot/dts/rk3228-evb.dts +++ b/arch/arm/boot/dts/rk3228-evb.dts @@ -53,7 +53,6 @@ memory { }; &emmc { - broken-cd; cap-mmc-highspeed; mmc-ddr-1_8v; disable-wp; diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi index 78d47f7d2938..3ccd8f35a841 100644 --- a/arch/arm/boot/dts/rk3288-evb.dtsi +++ b/arch/arm/boot/dts/rk3288-evb.dtsi @@ -172,7 +172,6 @@ &cpu0 { }; &emmc { - broken-cd; bus-width = <8>; cap-mmc-highspeed; disable-wp; diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi index 98c586a43c73..5f06d8c1b9f6 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly.dtsi @@ -208,7 +208,6 @@ &cpu0 { }; &emmc { - broken-cd; bus-width = <8>; cap-mmc-highspeed; disable-wp; @@ -509,7 +508,6 @@ &saradc { }; &sdio0 { - broken-cd; bus-width = <4>; disable-wp; non-removable; diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts index 2ff9689d2e1b..eb77276e1cc2 100644 --- a/arch/arm/boot/dts/rk3288-popmetal.dts +++ b/arch/arm/boot/dts/rk3288-popmetal.dts @@ -162,7 +162,6 @@ &cpu0 { }; &emmc { - broken-cd; bus-width = <8>; cap-mmc-highspeed; disable-wp; diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 412809c60d01..bfb20c878384 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -146,7 +146,6 @@ &cpu0 { &emmc { status = "okay"; - broken-cd; bus-width = <8>; cap-mmc-highspeed; rockchip,default-sample-phase = <158>; @@ -347,7 +346,6 @@ &pwm1 { &sdio0 { status = "okay"; - broken-cd; bus-width = <4>; cap-sd-highspeed; cap-sdio-irq; From 1ab0c304a029fe3f2338c505b81df02d4220dbc7 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 6 Aug 2015 22:57:08 +0200 Subject: [PATCH 11/27] ARM: dts: rockchip: update rk3288-veyron cpu operating points The generic operating points specified in rk3288.dtsi are specified by Rockchip as conservative and for all cases. In contrast the Veyron ChromeOS devices are supposed to use a special chip variant often called rk3288-c and use different operating points in their kernel also including a higher max frequency. So override the operating points for veyron devices. Signed-off-by: Heiko Stuebner Reviewed-by: Douglas Anderson --- arch/arm/boot/dts/rk3288-veyron.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index bfb20c878384..b2557bf5a58f 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -141,6 +141,22 @@ vcc50_hdmi: vcc50-hdmi { &cpu0 { cpu0-supply = <&vdd_cpu>; + operating-points = < + /* KHz uV */ + 1800000 1400000 + 1704000 1350000 + 1608000 1300000 + 1512000 1250000 + 1416000 1200000 + 1200000 1100000 + 1008000 1050000 + 816000 1000000 + 696000 950000 + 600000 900000 + 408000 900000 + 216000 900000 + 126000 900000 + >; }; &emmc { From 95cface95b6a6a8de6e95de2c8a25a64fd0f3558 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 31 Mar 2016 19:28:26 +0200 Subject: [PATCH 12/27] ARM: dts: rockchip: fix rk3288 power-domain unit names The power-domain sub-nodes do have reg properties, but so far are missing the expected unit names. So add the missing ones. Signed-off-by: Heiko Stuebner Acked-by: Rob Herring --- arch/arm/boot/dts/rk3288.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 74eae995c330..f445d190ed1a 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -659,7 +659,7 @@ power: power-controller { * *_HDMI HDMI * *_MIPI_* MIPI */ - pd_vio { + pd_vio@RK3288_PD_VIO { reg = ; clocks = <&cru ACLK_IEP>, <&cru ACLK_ISP>, @@ -692,7 +692,7 @@ pd_vio { * Note: The following 3 are HEVC(H.265) clocks, * and on the ACLK_HEVC_NIU (NOC). */ - pd_hevc { + pd_hevc@RK3288_PD_HEVC { reg = ; clocks = <&cru ACLK_HEVC>, <&cru SCLK_HEVC_CABAC>, @@ -704,7 +704,7 @@ pd_hevc { * (video endecoder & decoder) clocks that on the * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). */ - pd_video { + pd_video@RK3288_PD_VIDEO { reg = ; clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; @@ -714,7 +714,7 @@ pd_video { * Note: ACLK_GPU is the GPU clock, * and on the ACLK_GPU_NIU (NOC). */ - pd_gpu { + pd_gpu@RK3288_PD_GPU { reg = ; clocks = <&cru ACLK_GPU>; }; From a8f0fa2764626d2dd808cfbe1a160f2939a36c88 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 31 Mar 2016 20:12:14 +0200 Subject: [PATCH 13/27] ARM: dts: rockchip: fix missing usbphy unit-names The usbphy subnodes do have a reg property but no unitname, add them. Signed-off-by: Heiko Stuebner Acked-by: Rob Herring --- arch/arm/boot/dts/rk3066a.dtsi | 4 ++-- arch/arm/boot/dts/rk3188.dtsi | 4 ++-- arch/arm/boot/dts/rk3288.dtsi | 6 +++--- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index cb0a552e0b18..c84a306fd73f 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -207,7 +207,7 @@ usbphy: phy { #size-cells = <0>; status = "disabled"; - usbphy0: usb-phy0 { + usbphy0: usb-phy@17c { #phy-cells = <0>; reg = <0x17c>; clocks = <&cru SCLK_OTGPHY0>; @@ -215,7 +215,7 @@ usbphy0: usb-phy0 { #clock-cells = <0>; }; - usbphy1: usb-phy1 { + usbphy1: usb-phy@188 { #phy-cells = <0>; reg = <0x188>; clocks = <&cru SCLK_OTGPHY1>; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 9271833958f9..c44c31874bbd 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -166,7 +166,7 @@ usbphy: phy { #size-cells = <0>; status = "disabled"; - usbphy0: usb-phy0 { + usbphy0: usb-phy@10c { #phy-cells = <0>; reg = <0x10c>; clocks = <&cru SCLK_OTGPHY0>; @@ -174,7 +174,7 @@ usbphy0: usb-phy0 { #clock-cells = <0>; }; - usbphy1: usb-phy1 { + usbphy1: usb-phy@11c { #phy-cells = <0>; reg = <0x11c>; clocks = <&cru SCLK_OTGPHY1>; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index f445d190ed1a..ee4085dd7007 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -967,7 +967,7 @@ usbphy: phy { #size-cells = <0>; status = "disabled"; - usbphy0: usb-phy0 { + usbphy0: usb-phy@320 { #phy-cells = <0>; reg = <0x320>; clocks = <&cru SCLK_OTGPHY0>; @@ -975,7 +975,7 @@ usbphy0: usb-phy0 { #clock-cells = <0>; }; - usbphy1: usb-phy1 { + usbphy1: usb-phy@334 { #phy-cells = <0>; reg = <0x334>; clocks = <&cru SCLK_OTGPHY1>; @@ -983,7 +983,7 @@ usbphy1: usb-phy1 { #clock-cells = <0>; }; - usbphy2: usb-phy2 { + usbphy2: usb-phy@348 { #phy-cells = <0>; reg = <0x348>; clocks = <&cru SCLK_OTGPHY2>; From 8b30c899c7dd9eb92b957a3c112d3226a9ac1c3c Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 31 Mar 2016 20:24:29 +0200 Subject: [PATCH 14/27] ARM: dts: rockchip: clean up gpio-keys nodes Drop superfluous #address-cells and #size-cells, rename key-nodes to individual names and also use the key constants intead of numbers. Reported-by: Julien Chauveau Signed-off-by: Heiko Stuebner Acked-by: Rob Herring --- arch/arm/boot/dts/rk3066a-bqcurie2.dts | 11 +++++------ arch/arm/boot/dts/rk3066a-rayeager.dts | 7 +++---- arch/arm/boot/dts/rk3188-radxarock.dts | 7 +++---- arch/arm/boot/dts/rk3288-evb.dtsi | 7 +++---- arch/arm/boot/dts/rk3288-firefly.dtsi | 7 +++---- arch/arm/boot/dts/rk3288-popmetal.dts | 8 +++----- arch/arm/boot/dts/rk3288-r89.dts | 7 +++---- 7 files changed, 23 insertions(+), 31 deletions(-) diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index 6d2a5b3a84a8..bc674ee206ec 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts @@ -42,6 +42,7 @@ */ /dts-v1/; +#include #include "rk3066a.dtsi" / { @@ -77,21 +78,19 @@ vcc_sd0: fixed-regulator { gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@0 { + power { gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */ - linux,code = <116>; + linux,code = ; label = "GPIO Key Power"; linux,input-type = <1>; wakeup-source; debounce-interval = <100>; }; - button@1 { + volume-down { gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */ - linux,code = <104>; + linux,code = ; label = "GPIO Key Vol-"; linux,input-type = <1>; debounce-interval = <100>; diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts index 3a5989b1724a..6e7f2187a0e3 100644 --- a/arch/arm/boot/dts/rk3066a-rayeager.dts +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts @@ -41,6 +41,7 @@ */ /dts-v1/; +#include #include "rk3066a.dtsi" / { @@ -61,14 +62,12 @@ ir: ir-receiver { keys: gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - button@0 { + power { wakeup-source; gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; label = "GPIO Power"; - linux,code = <116>; + linux,code = ; pinctrl-names = "default"; pinctrl-0 = <&pwr_key>; }; diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index 0b6924c97b6b..1da46d138029 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -41,6 +41,7 @@ */ /dts-v1/; +#include #include "rk3188.dtsi" / { @@ -54,13 +55,11 @@ memory { gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@0 { + power { gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; - linux,code = <116>; + linux,code = ; label = "GPIO Key Power"; linux,input-type = <1>; wakeup-source; diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi index 3ccd8f35a841..963365d12208 100644 --- a/arch/arm/boot/dts/rk3288-evb.dtsi +++ b/arch/arm/boot/dts/rk3288-evb.dtsi @@ -38,6 +38,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include #include #include "rk3288.dtsi" @@ -98,16 +99,14 @@ ext_gmac: external-gmac-clock { gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; pinctrl-names = "default"; pinctrl-0 = <&pwrbtn>; - button@0 { + power { gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - linux,code = <116>; + linux,code = ; label = "GPIO Key Power"; linux,input-type = <1>; wakeup-source; diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi index 5f06d8c1b9f6..d6cf9ada13c9 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly.dtsi @@ -40,6 +40,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include #include "rk3288.dtsi" / { @@ -87,14 +88,12 @@ ir: ir-receiver { keys: gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - button@0 { + power { wakeup-source; gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; label = "GPIO Power"; - linux,code = <116>; + linux,code = ; pinctrl-names = "default"; pinctrl-0 = <&pwr_key>; }; diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts index eb77276e1cc2..720717bb3614 100644 --- a/arch/arm/boot/dts/rk3288-popmetal.dts +++ b/arch/arm/boot/dts/rk3288-popmetal.dts @@ -41,7 +41,7 @@ */ /dts-v1/; - +#include #include "rk3288.dtsi" / { @@ -62,16 +62,14 @@ ext_gmac: external-gmac-clock { gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; pinctrl-names = "default"; pinctrl-0 = <&pwrbtn>; - button@0 { + power { gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - linux,code = <116>; + linux,code = ; label = "GPIO Key Power"; linux,input-type = <1>; wakeup-source; diff --git a/arch/arm/boot/dts/rk3288-r89.dts b/arch/arm/boot/dts/rk3288-r89.dts index 510a1d0d7abb..4b8a8adb243c 100644 --- a/arch/arm/boot/dts/rk3288-r89.dts +++ b/arch/arm/boot/dts/rk3288-r89.dts @@ -41,6 +41,7 @@ */ /dts-v1/; +#include #include #include "rk3288.dtsi" @@ -61,16 +62,14 @@ ext_gmac: external-gmac-clock { gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; pinctrl-names = "default"; pinctrl-0 = <&pwrbtn>; - button@0 { + power { gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - linux,code = <116>; + linux,code = ; label = "GPIO Key Power"; linux,input-type = <1>; wakeup-source; From 6b241fcccb42ab96b3cdca7066cebd0f5cdd44e0 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 31 Mar 2016 20:37:40 +0200 Subject: [PATCH 15/27] ARM: dts: rockchip: drop unneeded properties from mipi node The mipi controller node does contain an unused reg property as well as unnecessary #address-cells and #size-cells properties for subnodes not using addresses, so remove those to also make dtc happy. Signed-off-by: Heiko Stuebner Acked-by: Rob Herring --- arch/arm/boot/dts/rk3288.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index ee4085dd7007..9114c7b8dff4 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -888,10 +888,6 @@ mipi_dsi: mipi@ff960000 { status = "disabled"; ports { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - mipi_in: port { #address-cells = <1>; #size-cells = <0>; From 6691409224de8f7badc3f5d072c2bf72b223395d Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 31 Mar 2016 22:15:43 +0200 Subject: [PATCH 16/27] ARM: dts: rockchip: add missing unitname to cpu_leakage efuse The cpu_leakage efuse on rk3288 did get it right including the unitname but on both rk3066a and rk3188 it was missing, fix that. Signed-off-by: Heiko Stuebner Acked-by: Rob Herring --- arch/arm/boot/dts/rk3066a.dtsi | 2 +- arch/arm/boot/dts/rk3188.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index c84a306fd73f..c0ba86c3a2ab 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -169,7 +169,7 @@ efuse: efuse@20010000 { clocks = <&cru PCLK_EFUSE>; clock-names = "pclk_efuse"; - cpu_leakage: cpu_leakage { + cpu_leakage: cpu_leakage@17 { reg = <0x17 0x1>; }; }; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index c44c31874bbd..31f81b265cef 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -154,7 +154,7 @@ efuse: efuse@20010000 { clocks = <&cru PCLK_EFUSE>; clock-names = "pclk_efuse"; - cpu_leakage: cpu_leakage { + cpu_leakage: cpu_leakage@17 { reg = <0x17 0x1>; }; }; From f5663969d8125a5c5b7835812e1e636ecedf030b Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 28 Oct 2015 10:54:22 +0100 Subject: [PATCH 17/27] ARM: dts: rockchip: add rk3288 edp-phy node Add the core device node of the edp-phy on rk3288 socs. Signed-off-by: Heiko Stuebner Tested-by: Douglas Anderson --- arch/arm/boot/dts/rk3288.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 9114c7b8dff4..437dd263a753 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -201,6 +201,15 @@ xin24m: oscillator { #clock-cells = <0>; }; + edp_phy: edp-phy { + compatible = "rockchip,rk3288-dp-phy"; + clocks = <&cru SCLK_EDP_24M>; + clock-names = "24m"; + rockchip,grf = <&grf>; + #phy-cells = <0>; + status = "disabled"; + }; + timer { compatible = "arm,armv7-timer"; arm,cpu-registers-not-fw-configured; From 6df7ec6186644a4ffb4f0c859327ef41a1145a5f Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 28 Oct 2015 10:55:19 +0100 Subject: [PATCH 18/27] ARM: dts: rockchip: add rk3288 displayport controller node Add the rk3288 edp node and its hooks into the display-subsystem. Signed-off-by: Heiko Stuebner Tested-by: Douglas Anderson --- arch/arm/boot/dts/rk3288.dtsi | 44 +++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 437dd263a753..688cb37b156e 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -830,6 +830,12 @@ vopb_out_hdmi: endpoint@0 { reg = <0>; remote-endpoint = <&hdmi_in_vopb>; }; + + vopb_out_edp: endpoint@1 { + reg = <1>; + remote-endpoint = <&edp_in_vopb>; + }; + vopb_out_mipi: endpoint@2 { reg = <2>; remote-endpoint = <&mipi_in_vopb>; @@ -867,6 +873,12 @@ vopl_out_hdmi: endpoint@0 { reg = <0>; remote-endpoint = <&hdmi_in_vopl>; }; + + vopl_out_edp: endpoint@1 { + reg = <1>; + remote-endpoint = <&edp_in_vopl>; + }; + vopl_out_mipi: endpoint@2 { reg = <2>; remote-endpoint = <&mipi_in_vopl>; @@ -912,6 +924,38 @@ mipi_in_vopl: endpoint@1 { }; }; + edp: dp@ff970000 { + compatible = "rockchip,rk3288-dp"; + reg = <0xff970000 0x4000>; + interrupts = ; + clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; + clock-names = "dp", "pclk"; + phys = <&edp_phy>; + phy-names = "dp"; + resets = <&cru SRST_EDP>; + reset-names = "dp"; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + edp_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + edp_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_edp>; + }; + edp_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_edp>; + }; + }; + }; + }; + hdmi: hdmi@ff980000 { compatible = "rockchip,rk3288-dw-hdmi"; reg = <0xff980000 0x20000>; From a4e00345b29dbc93fe7e6f4070458f325261b0ac Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 28 Oct 2015 00:19:37 +0100 Subject: [PATCH 19/27] ARM: dts: rockchip: move edp-hpd pin definition into common location The edp hotplug pin is fixed on the soc side, anybody wanting to use it will need the same definition anyway, so move it to a common location. Signed-off-by: Heiko Stuebner Tested-by: Douglas Anderson --- arch/arm/boot/dts/rk3288-veyron-jaq.dts | 6 ------ arch/arm/boot/dts/rk3288.dtsi | 6 ++++++ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rk3288-veyron-jaq.dts index c2f52cfb4d06..5c97e3153526 100644 --- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts +++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts @@ -142,12 +142,6 @@ drv_5v: drv-5v { }; }; - edp { - edp_hpd: edp_hpd { - rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>; - }; - }; - hdmi { vcc50_hdmi_en: vcc50-hdmi-en { rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 688cb37b156e..3071e94e86ed 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -1208,6 +1208,12 @@ ddr1_retention: ddr1-retention { }; }; + edp { + edp_hpd: edp-hpd { + rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>; + }; + }; + i2c0 { i2c0_xfer: i2c0-xfer { rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>, From 1f45e8c6d0161f044d679f242fe7514e2625af4a Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sun, 29 Nov 2015 19:46:09 +0100 Subject: [PATCH 20/27] ARM: dts: rockchip: add startup delay to rk3288-veyron panel-regulators The panels need a bit of time to actually turn on. If this isn't observed, this results in problems when trying talk to the panels and thus produces detection errors. 100ms seem to be a safe value for the time being. Signed-off-by: Heiko Stuebner Tested-by: Douglas Anderson --- arch/arm/boot/dts/rk3288-veyron-jaq.dts | 1 + arch/arm/boot/dts/rk3288-veyron-jerry.dts | 1 + arch/arm/boot/dts/rk3288-veyron-minnie.dts | 1 + arch/arm/boot/dts/rk3288-veyron-speedy.dts | 1 + 4 files changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rk3288-veyron-jaq.dts index 5c97e3153526..2123ac21491e 100644 --- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts +++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts @@ -61,6 +61,7 @@ panel_regulator: panel-regulator { pinctrl-names = "default"; pinctrl-0 = <&lcd_enable_h>; regulator-name = "panel_regulator"; + startup-delay-us = <100000>; vin-supply = <&vcc33_sys>; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-jerry.dts b/arch/arm/boot/dts/rk3288-veyron-jerry.dts index 60bd6e91e308..1a9bef1303d3 100644 --- a/arch/arm/boot/dts/rk3288-veyron-jerry.dts +++ b/arch/arm/boot/dts/rk3288-veyron-jerry.dts @@ -60,6 +60,7 @@ panel_regulator: panel-regulator { pinctrl-names = "default"; pinctrl-0 = <&lcd_enable_h>; regulator-name = "panel_regulator"; + startup-delay-us = <100000>; vin-supply = <&vcc33_sys>; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts index 699beb0a9481..8b16f378a847 100644 --- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts +++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts @@ -70,6 +70,7 @@ panel_regulator: panel-regulator { pinctrl-names = "default"; pinctrl-0 = <&lcd_enable_h>; regulator-name = "panel_regulator"; + startup-delay-us = <100000>; vin-supply = <&vcc33_sys>; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts index b34a7b5b3f62..e62cdee78302 100644 --- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts +++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts @@ -61,6 +61,7 @@ panel_regulator: panel-regulator { pinctrl-names = "default"; pinctrl-0 = <&lcd_enable_h>; regulator-name = "panel_regulator"; + startup-delay-us = <100000>; vin-supply = <&vcc33_sys>; }; From dfb2146efc6b07f1a6cc04938248c2ce948c9c98 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 14 Dec 2015 11:32:28 +0100 Subject: [PATCH 21/27] ARM: dts: rockchip: add core rk3288-veyron backlight and panel nodes Many Veyron chromebooks share the same panel type, so define the core settings for all of them and allow the few runaways to override it later. Signed-off-by: Heiko Stuebner Tested-by: Douglas Anderson --- .../boot/dts/rk3288-veyron-chromebook.dtsi | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi index 610769d99522..7563d3d156d7 100644 --- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi @@ -54,6 +54,50 @@ aliases { i2c20 = &i2c_tunnel; }; + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <128>; + enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; + backlight-boot-off; + pinctrl-names = "default"; + pinctrl-0 = <&bl_en>; + pwms = <&pwm0 0 1000000 0>; + pwm-delay-us = <10000>; + }; + gpio-charger { compatible = "gpio-charger"; charger-type = "mains"; @@ -62,6 +106,13 @@ gpio-charger { pinctrl-0 = <&ac_present_ap>; }; + panel: panel { + compatible ="innolux,n116bge", "simple-panel"; + status = "okay"; + power-supply = <&vcc33_lcd>; + backlight = <&backlight>; + }; + /* A non-regulated voltage from power supply or battery */ vccsys: vccsys { compatible = "regulator-fixed"; @@ -184,6 +235,12 @@ &global_pwroff &suspend_l_sleep >; + backlight { + bl_en: bl-en { + rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + buttons { ap_lid_int_l: ap-lid-int-l { rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_up>; From d8444fed59261f0342095e5a259386baf929f92e Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Mon, 7 Dec 2015 21:11:08 +0800 Subject: [PATCH 22/27] ARM: dts: rockchip: add rk3288-veyron-jaq backlight and panel overrides The panel which jaq uses requires the pwm duty cycle larger than 3%, when the backlight status from power off to power on, otherwise the backlight will flush, so we modify the second brightness-level to 8, and when the backlight from power off to power on the pwm duty cycle will larger than 3%. Signed-off-by: Caesar Wang Signed-off-by: Heiko Stuebner Tested-by: Douglas Anderson --- arch/arm/boot/dts/rk3288-veyron-jaq.dts | 42 +++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rk3288-veyron-jaq.dts index 2123ac21491e..3748abf562b1 100644 --- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts +++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts @@ -89,6 +89,48 @@ backlight_regulator: backlight-regulator { }; }; +&backlight { + /* Jaq panel PWM must be >= 3%, so start non-zero brightness at 8 */ + brightness-levels = < + 0 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + power-supply = <&backlight_regulator>; +}; + +&panel { + power-supply = <&panel_regulator>; +}; + &rk808 { pinctrl-names = "default"; pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; From 712e6051c440a41f5e797412afa7b246d27adc69 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 14 Dec 2015 11:39:58 +0100 Subject: [PATCH 23/27] ARM: dts: rockchip: add rk3288-veyron-minnie backlight and panel settings The pwm for Minnie's backlight needs to be above 1%, so adapt the start of non-zero brightness accordingly. Minnie is also using a different panel, so re-set the compatible property. Signed-off-by: Heiko Stuebner Tested-by: Douglas Anderson --- arch/arm/boot/dts/rk3288-veyron-minnie.dts | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts index 8b16f378a847..f72d616d1bf8 100644 --- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts +++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts @@ -87,6 +87,44 @@ vcc18_lcd: vcc18-lcd { }; }; +&backlight { + /* Minnie panel PWM must be >= 1%, so start non-zero brightness at 3 */ + brightness-levels = < + 0 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + power-supply = <&backlight_regulator>; +}; + &emmc { /delete-property/mmc-hs200-1_8v; }; @@ -136,6 +174,11 @@ touchscreen@10 { }; }; +&panel { + compatible = "auo,b101ean01", "simple-panel"; + power-supply= <&panel_regulator>; +}; + &rk808 { pinctrl-names = "default"; pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; From 2f171d4043cf574cc003b3cbe0325b2fd02c2a43 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 14 Dec 2015 17:12:47 +0100 Subject: [PATCH 24/27] ARM: dts: rockchip: override edp hpd handling on veyron-pinky and speedy Pinky boards don't have the hotplug pin connected. So remove the hotplug pinctrl setting and enable the force-hpd option, to allow them to find the display too. While on speedy boards, the hotplug pin is connected, judging by comments in a chromeos change it seems the "panels HPD voltage is too low to be detected", so it also needs the forced hotplug, as we of course also know that a display is connected. Signed-off-by: Heiko Stuebner Tested-by: Douglas Anderson --- arch/arm/boot/dts/rk3288-veyron-pinky.dts | 7 +++++++ arch/arm/boot/dts/rk3288-veyron-speedy.dts | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/rk3288-veyron-pinky.dts b/arch/arm/boot/dts/rk3288-veyron-pinky.dts index 94b56e33d947..d44351ec2333 100644 --- a/arch/arm/boot/dts/rk3288-veyron-pinky.dts +++ b/arch/arm/boot/dts/rk3288-veyron-pinky.dts @@ -65,6 +65,13 @@ &emmc { pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_reset>; }; +&edp { + /delete-property/pinctrl-names; + /delete-property/pinctrl-0; + + force-hpd; +}; + &gpio_keys { pinctrl-0 = <&pwr_key_h &ap_lid_int_l>; diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts index e62cdee78302..90aa145404b5 100644 --- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts +++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts @@ -97,6 +97,13 @@ &cpu_alert1 { temperature = <70000>; }; +&edp { + /delete-property/pinctrl-names; + /delete-property/pinctrl-0; + + force-hpd; +}; + &rk808 { pinctrl-names = "default"; pinctrl-0 = <&pmic_int_l>; From 03deaf4a814425ceb67c73c1b1b9ada1ee929ca5 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 14 Dec 2015 17:15:25 +0100 Subject: [PATCH 25/27] ARM: dts: rockchip: simple panel and backlight supplies on veyron boards Jerry and Speedy don't need any special handling wrt the backlight or panel, so only need their backlight and panel-regulators hooked up. Signed-off-by: Heiko Stuebner Tested-by: Douglas Anderson --- arch/arm/boot/dts/rk3288-veyron-jerry.dts | 8 ++++++++ arch/arm/boot/dts/rk3288-veyron-speedy.dts | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/rk3288-veyron-jerry.dts b/arch/arm/boot/dts/rk3288-veyron-jerry.dts index 1a9bef1303d3..f6b2eaaebb9a 100644 --- a/arch/arm/boot/dts/rk3288-veyron-jerry.dts +++ b/arch/arm/boot/dts/rk3288-veyron-jerry.dts @@ -88,6 +88,14 @@ backlight_regulator: backlight-regulator { }; }; +&backlight { + power-supply = <&backlight_regulator>; +}; + +&panel { + power-supply= <&panel_regulator>; +}; + &rk808 { pinctrl-names = "default"; pinctrl-0 = <&pmic_int_l>; diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts index 90aa145404b5..a0d033f6fe52 100644 --- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts +++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts @@ -89,6 +89,10 @@ backlight_regulator: backlight-regulator { }; }; +&backlight { + power-supply = <&backlight_regulator>; +}; + &cpu_alert0 { temperature = <65000>; }; @@ -104,6 +108,10 @@ &edp { force-hpd; }; +&panel { + power-supply= <&panel_regulator>; +}; + &rk808 { pinctrl-names = "default"; pinctrl-0 = <&pmic_int_l>; From 37aedb29b9f053215a5a0dfb15ecc49af67c1fbc Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 14 Dec 2015 17:18:42 +0100 Subject: [PATCH 26/27] ARM: dts: rockchip: enable the eDP on rk3288 veyron devices After hooking up panel and backlight informations, enable the edp on veyron chromebooks now. Signed-off-by: Heiko Stuebner Tested-by: Douglas Anderson --- .../boot/dts/rk3288-veyron-chromebook.dtsi | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi index 7563d3d156d7..2958c36d12a0 100644 --- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi @@ -111,6 +111,14 @@ panel: panel { status = "okay"; power-supply = <&vcc33_lcd>; backlight = <&backlight>; + + ports { + panel_in: port { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; }; /* A non-regulated voltage from power supply or battery */ @@ -154,6 +162,29 @@ vcc5v_otg: vcc5v-otg-regulator { }; }; +&edp { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&edp_hpd>; + + ports { + edp_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + edp_out_panel: endpoint { + reg = <0>; + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +&edp_phy { + status = "okay"; +}; + &gpio_keys { pinctrl-0 = <&pwr_key_l &ap_lid_int_l>; lid { @@ -166,6 +197,10 @@ lid { }; }; +&pwm0 { + status = "okay"; +}; + &rk808 { vcc11-supply = <&vcc_5v>; @@ -219,6 +254,14 @@ trackpad@15 { }; }; +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + &pinctrl { pinctrl-0 = < /* Common for sleep and wake, but no owners */ From fbf15046f12d6c8d5821c0dc5bf3ffc55a132243 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 30 Mar 2016 17:33:24 +0200 Subject: [PATCH 27/27] ARM: dts: rockchip: move rk3036 memory definition to board files The amount of available memory is clearly a board-specific value, so the core per-soc dtsi should not define a default of any sort. Therefore move the memory-nodes to the two board files. Also fix the amount of memory on Kylin (512MB instead of 1GB). While in most cases the bootloader will override this with the actual amount of memory, there is no need to keep known wrong values in the board-dts. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036-evb.dts | 5 +++++ arch/arm/boot/dts/rk3036-kylin.dts | 5 +++++ arch/arm/boot/dts/rk3036.dtsi | 5 ----- 3 files changed, 10 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/rk3036-evb.dts b/arch/arm/boot/dts/rk3036-evb.dts index b3d6ec87f615..8db9e9b197a2 100644 --- a/arch/arm/boot/dts/rk3036-evb.dts +++ b/arch/arm/boot/dts/rk3036-evb.dts @@ -45,6 +45,11 @@ / { model = "Rockchip RK3036 Evaluation board"; compatible = "rockchip,rk3036-evb", "rockchip,rk3036"; + + memory { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; }; &emac { diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts index 951f15d675c7..1df1557a46c3 100644 --- a/arch/arm/boot/dts/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rk3036-kylin.dts @@ -46,6 +46,11 @@ / { model = "Rockchip RK3036 KylinBoard"; compatible = "rockchip,rk3036-kylin", "rockchip,rk3036"; + memory { + device_type = "memory"; + reg = <0x60000000 0x20000000>; + }; + leds: gpio-leds { compatible = "gpio-leds"; diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index fa6b5cf31aa7..843d2be2e4e9 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -63,11 +63,6 @@ aliases { spi = &spi; }; - memory { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - cpus { #address-cells = <1>; #size-cells = <0>;