From 668d361c9d893be3cbd4f3650e1934a62b204def Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 22 Jun 2022 19:17:22 +0100 Subject: [PATCH 1/3] dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset Definitions Renesas RZ/Five SoC has almost the same clock structure compared to the Renesas RZ/G2UL SoC, re-use the r9a07g043-cpg.h header file and just amend the RZ/Five CPG clock and reset definitions. Signed-off-by: Lad Prabhakar Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220622181723.13033-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- include/dt-bindings/clock/r9a07g043-cpg.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h b/include/dt-bindings/clock/r9a07g043-cpg.h index 27e232733096..77cde8effdc7 100644 --- a/include/dt-bindings/clock/r9a07g043-cpg.h +++ b/include/dt-bindings/clock/r9a07g043-cpg.h @@ -108,6 +108,15 @@ #define R9A07G043_ADC_ADCLK 76 #define R9A07G043_ADC_PCLK 77 #define R9A07G043_TSU_PCLK 78 +#define R9A07G043_NCEPLDM_DM_CLK 79 /* RZ/Five Only */ +#define R9A07G043_NCEPLDM_ACLK 80 /* RZ/Five Only */ +#define R9A07G043_NCEPLDM_TCK 81 /* RZ/Five Only */ +#define R9A07G043_NCEPLMT_ACLK 82 /* RZ/Five Only */ +#define R9A07G043_NCEPLIC_ACLK 83 /* RZ/Five Only */ +#define R9A07G043_AX45MP_CORE0_CLK 84 /* RZ/Five Only */ +#define R9A07G043_AX45MP_ACLK 85 /* RZ/Five Only */ +#define R9A07G043_IAX45_CLK 86 /* RZ/Five Only */ +#define R9A07G043_IAX45_PCLK 87 /* RZ/Five Only */ /* R9A07G043 Resets */ #define R9A07G043_CA55_RST_1_0 0 /* RZ/G2UL Only */ @@ -180,5 +189,16 @@ #define R9A07G043_ADC_PRESETN 67 #define R9A07G043_ADC_ADRST_N 68 #define R9A07G043_TSU_PRESETN 69 +#define R9A07G043_NCEPLDM_DTM_PWR_RST_N 70 /* RZ/Five Only */ +#define R9A07G043_NCEPLDM_ARESETN 71 /* RZ/Five Only */ +#define R9A07G043_NCEPLMT_POR_RSTN 72 /* RZ/Five Only */ +#define R9A07G043_NCEPLMT_ARESETN 73 /* RZ/Five Only */ +#define R9A07G043_NCEPLIC_ARESETN 74 /* RZ/Five Only */ +#define R9A07G043_AX45MP_ARESETNM 75 /* RZ/Five Only */ +#define R9A07G043_AX45MP_ARESETNS 76 /* RZ/Five Only */ +#define R9A07G043_AX45MP_L2_RESETN 77 /* RZ/Five Only */ +#define R9A07G043_AX45MP_CORE0_RESETN 78 /* RZ/Five Only */ +#define R9A07G043_IAX45_RESETN 79 /* RZ/Five Only */ + #endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */ From 95d48d270305ad2ce4e6e8d84a9fb6ea49d6f8aa Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 22 Jun 2022 19:17:23 +0100 Subject: [PATCH 2/3] clk: renesas: r9a07g043: Add support for RZ/Five SoC Renesas RZ/Five SoC has almost the same clock structure compared to the Renesas RZ/G2UL SoC, re-use the r9a07g043-cpg.c file to add support for RZ/Five SoC. This patch splits up the clocks and reset arrays for RZ/G2UL and RZ/Five SoC using #ifdef CONFIG_ARM64 and #ifdef CONFIG_RISCV checks. Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220622181723.13033-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g043-cpg.c | 32 +++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index 33c2bd8df2e5..37475465100d 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -36,9 +36,11 @@ enum clk_ids { CLK_PLL3_DIV2_4_2, CLK_SEL_PLL3_3, CLK_DIV_PLL3_C, +#ifdef CONFIG_ARM64 CLK_PLL5, CLK_PLL5_500, CLK_PLL5_250, +#endif CLK_PLL6, CLK_PLL6_250, CLK_P1_DIV2, @@ -100,9 +102,11 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3), DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3), DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32), +#ifdef CONFIG_ARM64 DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1), DEF_FIXED(".pll5_500", CLK_PLL5_500, CLK_PLL5, 1, 6), DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_500, 1, 2), +#endif DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6), DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2), @@ -126,12 +130,20 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { }; static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { +#ifdef CONFIG_ARM64 DEF_MOD("gic", R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1, 0x514, 0), DEF_MOD("ia55_pclk", R9A07G043_IA55_PCLK, R9A07G043_CLK_P2, 0x518, 0), DEF_MOD("ia55_clk", R9A07G043_IA55_CLK, R9A07G043_CLK_P1, 0x518, 1), +#endif +#ifdef CONFIG_RISCV + DEF_MOD("iax45_pclk", R9A07G043_IAX45_PCLK, R9A07G043_CLK_P2, + 0x518, 0), + DEF_MOD("iax45_clk", R9A07G043_IAX45_CLK, R9A07G043_CLK_P1, + 0x518, 1), +#endif DEF_MOD("dmac_aclk", R9A07G043_DMAC_ACLK, R9A07G043_CLK_P1, 0x52c, 0), DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2, @@ -243,9 +255,14 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { }; static struct rzg2l_reset r9a07g043_resets[] = { +#ifdef CONFIG_ARM64 DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0), DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1), DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0), +#endif +#ifdef CONFIG_RISCV + DEF_RST(R9A07G043_IAX45_RESETN, 0x818, 0), +#endif DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0), DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1), DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0), @@ -291,8 +308,13 @@ static struct rzg2l_reset r9a07g043_resets[] = { }; static const unsigned int r9a07g043_crit_mod_clks[] __initconst = { +#ifdef CONFIG_ARM64 MOD_CLK_BASE + R9A07G043_GIC600_GICCLK, MOD_CLK_BASE + R9A07G043_IA55_CLK, +#endif +#ifdef CONFIG_RISCV + MOD_CLK_BASE + R9A07G043_IAX45_CLK, +#endif MOD_CLK_BASE + R9A07G043_DMAC_ACLK, }; @@ -310,11 +332,21 @@ const struct rzg2l_cpg_info r9a07g043_cpg_info = { /* Module Clocks */ .mod_clks = r9a07g043_mod_clks, .num_mod_clks = ARRAY_SIZE(r9a07g043_mod_clks), +#ifdef CONFIG_ARM64 .num_hw_mod_clks = R9A07G043_TSU_PCLK + 1, +#endif +#ifdef CONFIG_RISCV + .num_hw_mod_clks = R9A07G043_IAX45_PCLK + 1, +#endif /* Resets */ .resets = r9a07g043_resets, +#ifdef CONFIG_ARM64 .num_resets = R9A07G043_TSU_PRESETN + 1, /* Last reset ID + 1 */ +#endif +#ifdef CONFIG_RISCV + .num_resets = R9A07G043_IAX45_RESETN + 1, /* Last reset ID + 1 */ +#endif .has_clk_mon_regs = true, }; From 0e704f6c42dc64f081d0b1738d06b2dee9524f27 Mon Sep 17 00:00:00 2001 From: Andi Kleen Date: Thu, 23 Jun 2022 10:32:17 +0200 Subject: [PATCH 3/3] clk: renesas: rcar-gen4: Fix initconst confusion for cpg_pll_config A variable pointing to const isn't const itself. It'd have to contain "const" keyword after "*" too. Therefore, cpg_pll_config cannot be put to "rodata". Hence use __initdata instead of __initconst to fix this. Signed-off-by: Andi Kleen [js] more explanatory commit message. Signed-off-by: Jiri Slaby Acked-by: Stephen Boyd Link: https://lore.kernel.org/r/20220623083217.26433-2-jslaby@suse.cz Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/rcar-gen4-cpg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/renesas/rcar-gen4-cpg.c b/drivers/clk/renesas/rcar-gen4-cpg.c index c7ed43d6aa67..e27832e5114f 100644 --- a/drivers/clk/renesas/rcar-gen4-cpg.c +++ b/drivers/clk/renesas/rcar-gen4-cpg.c @@ -23,7 +23,7 @@ #include "rcar-gen4-cpg.h" #include "rcar-cpg-lib.h" -static const struct rcar_gen4_cpg_pll_config *cpg_pll_config __initconst; +static const struct rcar_gen4_cpg_pll_config *cpg_pll_config __initdata; static unsigned int cpg_clk_extalr __initdata; static u32 cpg_mode __initdata;