mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-05-07 10:24:01 -04:00
Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC-related driver updates from Olof Johansson:
"Various driver updates for platforms and a couple of the small driver
subsystems we merge through our tree:
- A driver for SCU (system control) on NXP i.MX8QXP
- Qualcomm Always-on Subsystem messaging driver (AOSS QMP)
- Qualcomm PM support for MSM8998
- Support for a newer version of DRAM PHY driver for Broadcom (DPFE)
- Reset controller support for Bitmain BM1880
- TI SCI (System Control Interface) support for CPU control on AM654
processors
- More TI sysc refactoring and rework"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (84 commits)
reset: remove redundant null check on pointer dev
soc: rockchip: work around clang warning
dt-bindings: reset: imx7: Fix the spelling of 'indices'
soc: imx: Add i.MX8MN SoC driver support
soc: aspeed: lpc-ctrl: Fix probe error handling
soc: qcom: geni: Add support for ACPI
firmware: ti_sci: Fix gcc unused-but-set-variable warning
firmware: ti_sci: Use the correct style for SPDX License Identifier
soc: imx8: Use existing of_root directly
soc: imx8: Fix potential kernel dump in error path
firmware/psci: psci_checker: Park kthreads before stopping them
memory: move jedec_ddr.h from include/memory to drivers/memory/
memory: move jedec_ddr_data.c from lib/ to drivers/memory/
MAINTAINERS: Remove myself as qcom maintainer
soc: aspeed: lpc-ctrl: make parameter optional
soc: qcom: apr: Don't use reg for domain id
soc: qcom: fix QCOM_AOSS_QMP dependency and build errors
memory: tegra: Fix -Wunused-const-variable
firmware: tegra: Early resume BPMP
soc/tegra: Select pinctrl for Tegra194
...
This commit is contained in:
Linus Torvalds
14
include/dt-bindings/power/qcom-aoss-qmp.h
Normal file
14
include/dt-bindings/power/qcom-aoss-qmp.h
Normal file
@@ -0,0 +1,14 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/* Copyright (c) 2018, Linaro Ltd. */
|
||||
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||||
#ifndef __DT_BINDINGS_POWER_QCOM_AOSS_QMP_H
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||||
#define __DT_BINDINGS_POWER_QCOM_AOSS_QMP_H
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||||
|
||||
#define AOSS_QMP_LS_CDSP 0
|
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#define AOSS_QMP_LS_LPASS 1
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||||
#define AOSS_QMP_LS_MODEM 2
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#define AOSS_QMP_LS_SLPI 3
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#define AOSS_QMP_LS_SPSS 4
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#define AOSS_QMP_LS_VENUS 5
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||||
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#endif
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@@ -36,4 +36,38 @@
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#define MSM8996_VDDSSCX 5
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#define MSM8996_VDDSSCX_VFC 6
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/* MSM8998 Power Domain Indexes */
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#define MSM8998_VDDCX 0
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#define MSM8998_VDDCX_AO 1
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#define MSM8998_VDDCX_VFL 2
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#define MSM8998_VDDMX 3
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#define MSM8998_VDDMX_AO 4
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#define MSM8998_VDDMX_VFL 5
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#define MSM8998_SSCCX 6
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#define MSM8998_SSCCX_VFL 7
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#define MSM8998_SSCMX 8
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#define MSM8998_SSCMX_VFL 9
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/* QCS404 Power Domains */
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#define QCS404_VDDMX 0
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#define QCS404_VDDMX_AO 1
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#define QCS404_VDDMX_VFL 2
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#define QCS404_LPICX 3
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#define QCS404_LPICX_VFL 4
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#define QCS404_LPIMX 5
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#define QCS404_LPIMX_VFL 6
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||||
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||||
/* RPM SMD Power Domain performance levels */
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#define RPM_SMD_LEVEL_RETENTION 16
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#define RPM_SMD_LEVEL_RETENTION_PLUS 32
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#define RPM_SMD_LEVEL_MIN_SVS 48
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#define RPM_SMD_LEVEL_LOW_SVS 64
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#define RPM_SMD_LEVEL_SVS 128
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#define RPM_SMD_LEVEL_SVS_PLUS 192
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#define RPM_SMD_LEVEL_NOM 256
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#define RPM_SMD_LEVEL_NOM_PLUS 320
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#define RPM_SMD_LEVEL_TURBO 384
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#define RPM_SMD_LEVEL_TURBO_NO_CPR 416
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#define RPM_SMD_LEVEL_BINNING 512
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#endif
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51
include/dt-bindings/reset/bitmain,bm1880-reset.h
Normal file
51
include/dt-bindings/reset/bitmain,bm1880-reset.h
Normal file
@@ -0,0 +1,51 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2018 Bitmain Ltd.
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* Copyright (c) 2019 Linaro Ltd.
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||||
*/
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||||
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#ifndef _DT_BINDINGS_BM1880_RESET_H
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#define _DT_BINDINGS_BM1880_RESET_H
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#define BM1880_RST_MAIN_AP 0
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#define BM1880_RST_SECOND_AP 1
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||||
#define BM1880_RST_DDR 2
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#define BM1880_RST_VIDEO 3
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#define BM1880_RST_JPEG 4
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#define BM1880_RST_VPP 5
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#define BM1880_RST_GDMA 6
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#define BM1880_RST_AXI_SRAM 7
|
||||
#define BM1880_RST_TPU 8
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#define BM1880_RST_USB 9
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#define BM1880_RST_ETH0 10
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#define BM1880_RST_ETH1 11
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#define BM1880_RST_NAND 12
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#define BM1880_RST_EMMC 13
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#define BM1880_RST_SD 14
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#define BM1880_RST_SDMA 15
|
||||
#define BM1880_RST_I2S0 16
|
||||
#define BM1880_RST_I2S1 17
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||||
#define BM1880_RST_UART0_1_CLK 18
|
||||
#define BM1880_RST_UART0_1_ACLK 19
|
||||
#define BM1880_RST_UART2_3_CLK 20
|
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#define BM1880_RST_UART2_3_ACLK 21
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#define BM1880_RST_MINER 22
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#define BM1880_RST_I2C0 23
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||||
#define BM1880_RST_I2C1 24
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||||
#define BM1880_RST_I2C2 25
|
||||
#define BM1880_RST_I2C3 26
|
||||
#define BM1880_RST_I2C4 27
|
||||
#define BM1880_RST_PWM0 28
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||||
#define BM1880_RST_PWM1 29
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#define BM1880_RST_PWM2 30
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||||
#define BM1880_RST_PWM3 31
|
||||
#define BM1880_RST_SPI 32
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||||
#define BM1880_RST_GPIO0 33
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#define BM1880_RST_GPIO1 34
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#define BM1880_RST_GPIO2 35
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#define BM1880_RST_EFUSE 36
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#define BM1880_RST_WDT 37
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#define BM1880_RST_AHB_ROM 38
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#define BM1880_RST_SPIC 39
|
||||
|
||||
#endif /* _DT_BINDINGS_BM1880_RESET_H */
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||||
@@ -19,6 +19,7 @@ enum ti_sysc_module_type {
|
||||
|
||||
struct ti_sysc_cookie {
|
||||
void *data;
|
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void *clkdm;
|
||||
};
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||||
|
||||
/**
|
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@@ -46,6 +47,10 @@ struct sysc_regbits {
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s8 emufree_shift;
|
||||
};
|
||||
|
||||
#define SYSC_MODULE_QUIRK_HDQ1W BIT(17)
|
||||
#define SYSC_MODULE_QUIRK_I2C BIT(16)
|
||||
#define SYSC_MODULE_QUIRK_WDT BIT(15)
|
||||
#define SYSS_QUIRK_RESETDONE_INVERTED BIT(14)
|
||||
#define SYSC_QUIRK_SWSUP_MSTANDBY BIT(13)
|
||||
#define SYSC_QUIRK_SWSUP_SIDLE_ACT BIT(12)
|
||||
#define SYSC_QUIRK_SWSUP_SIDLE BIT(11)
|
||||
@@ -125,9 +130,16 @@ struct ti_sysc_module_data {
|
||||
};
|
||||
|
||||
struct device;
|
||||
struct clk;
|
||||
|
||||
struct ti_sysc_platform_data {
|
||||
struct of_dev_auxdata *auxdata;
|
||||
int (*init_clockdomain)(struct device *dev, struct clk *fck,
|
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struct clk *ick, struct ti_sysc_cookie *cookie);
|
||||
void (*clkdm_deny_idle)(struct device *dev,
|
||||
const struct ti_sysc_cookie *cookie);
|
||||
void (*clkdm_allow_idle)(struct device *dev,
|
||||
const struct ti_sysc_cookie *cookie);
|
||||
int (*init_module)(struct device *dev,
|
||||
const struct ti_sysc_module_data *data,
|
||||
struct ti_sysc_cookie *cookie);
|
||||
|
||||
@@ -144,6 +144,7 @@ struct scmi_power_ops {
|
||||
struct scmi_sensor_info {
|
||||
u32 id;
|
||||
u8 type;
|
||||
s8 scale;
|
||||
char name[SCMI_MAX_STR_SIZE];
|
||||
};
|
||||
|
||||
|
||||
@@ -241,12 +241,254 @@ struct ti_sci_rm_irq_ops {
|
||||
u16 global_event, u8 vint_status_bit);
|
||||
};
|
||||
|
||||
/* RA config.addr_lo parameter is valid for RM ring configure TI_SCI message */
|
||||
#define TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID BIT(0)
|
||||
/* RA config.addr_hi parameter is valid for RM ring configure TI_SCI message */
|
||||
#define TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID BIT(1)
|
||||
/* RA config.count parameter is valid for RM ring configure TI_SCI message */
|
||||
#define TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID BIT(2)
|
||||
/* RA config.mode parameter is valid for RM ring configure TI_SCI message */
|
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#define TI_SCI_MSG_VALUE_RM_RING_MODE_VALID BIT(3)
|
||||
/* RA config.size parameter is valid for RM ring configure TI_SCI message */
|
||||
#define TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID BIT(4)
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||||
/* RA config.order_id parameter is valid for RM ring configure TISCI message */
|
||||
#define TI_SCI_MSG_VALUE_RM_RING_ORDER_ID_VALID BIT(5)
|
||||
|
||||
#define TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER \
|
||||
(TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID | \
|
||||
TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID | \
|
||||
TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID | \
|
||||
TI_SCI_MSG_VALUE_RM_RING_MODE_VALID | \
|
||||
TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID)
|
||||
|
||||
/**
|
||||
* struct ti_sci_rm_ringacc_ops - Ring Accelerator Management operations
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||||
* @config: configure the SoC Navigator Subsystem Ring Accelerator ring
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||||
* @get_config: get the SoC Navigator Subsystem Ring Accelerator ring
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||||
* configuration
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||||
*/
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||||
struct ti_sci_rm_ringacc_ops {
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int (*config)(const struct ti_sci_handle *handle,
|
||||
u32 valid_params, u16 nav_id, u16 index,
|
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u32 addr_lo, u32 addr_hi, u32 count, u8 mode,
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||||
u8 size, u8 order_id
|
||||
);
|
||||
int (*get_config)(const struct ti_sci_handle *handle,
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u32 nav_id, u32 index, u8 *mode,
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||||
u32 *addr_lo, u32 *addr_hi, u32 *count,
|
||||
u8 *size, u8 *order_id);
|
||||
};
|
||||
|
||||
/**
|
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* struct ti_sci_rm_psil_ops - PSI-L thread operations
|
||||
* @pair: pair PSI-L source thread to a destination thread.
|
||||
* If the src_thread is mapped to UDMA tchan, the corresponding channel's
|
||||
* TCHAN_THRD_ID register is updated.
|
||||
* If the dst_thread is mapped to UDMA rchan, the corresponding channel's
|
||||
* RCHAN_THRD_ID register is updated.
|
||||
* @unpair: unpair PSI-L source thread from a destination thread.
|
||||
* If the src_thread is mapped to UDMA tchan, the corresponding channel's
|
||||
* TCHAN_THRD_ID register is cleared.
|
||||
* If the dst_thread is mapped to UDMA rchan, the corresponding channel's
|
||||
* RCHAN_THRD_ID register is cleared.
|
||||
*/
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struct ti_sci_rm_psil_ops {
|
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int (*pair)(const struct ti_sci_handle *handle, u32 nav_id,
|
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u32 src_thread, u32 dst_thread);
|
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int (*unpair)(const struct ti_sci_handle *handle, u32 nav_id,
|
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u32 src_thread, u32 dst_thread);
|
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};
|
||||
|
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/* UDMAP channel types */
|
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#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR 2
|
||||
#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR_SB 3 /* RX only */
|
||||
#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBRR 10
|
||||
#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBVR 11
|
||||
#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR 12
|
||||
#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBVR 13
|
||||
|
||||
#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST 0
|
||||
#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_MONO 2
|
||||
|
||||
#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES 1
|
||||
#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES 2
|
||||
#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES 3
|
||||
|
||||
/* UDMAP TX/RX channel valid_params common declarations */
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID BIT(0)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID BIT(1)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID BIT(2)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID BIT(3)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID BIT(4)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_VALID BIT(5)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID BIT(6)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID BIT(7)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID BIT(8)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_VALID BIT(14)
|
||||
|
||||
/**
|
||||
* Configures a Navigator Subsystem UDMAP transmit channel
|
||||
*
|
||||
* Configures a Navigator Subsystem UDMAP transmit channel registers.
|
||||
* See @ti_sci_msg_rm_udmap_tx_ch_cfg_req
|
||||
*/
|
||||
struct ti_sci_msg_rm_udmap_tx_ch_cfg {
|
||||
u32 valid_params;
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID BIT(9)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID BIT(10)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID BIT(11)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID BIT(12)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID BIT(13)
|
||||
u16 nav_id;
|
||||
u16 index;
|
||||
u8 tx_pause_on_err;
|
||||
u8 tx_filt_einfo;
|
||||
u8 tx_filt_pswords;
|
||||
u8 tx_atype;
|
||||
u8 tx_chan_type;
|
||||
u8 tx_supr_tdpkt;
|
||||
u16 tx_fetch_size;
|
||||
u8 tx_credit_count;
|
||||
u16 txcq_qnum;
|
||||
u8 tx_priority;
|
||||
u8 tx_qos;
|
||||
u8 tx_orderid;
|
||||
u16 fdepth;
|
||||
u8 tx_sched_priority;
|
||||
u8 tx_burst_size;
|
||||
};
|
||||
|
||||
/**
|
||||
* Configures a Navigator Subsystem UDMAP receive channel
|
||||
*
|
||||
* Configures a Navigator Subsystem UDMAP receive channel registers.
|
||||
* See @ti_sci_msg_rm_udmap_rx_ch_cfg_req
|
||||
*/
|
||||
struct ti_sci_msg_rm_udmap_rx_ch_cfg {
|
||||
u32 valid_params;
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID BIT(9)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID BIT(10)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID BIT(11)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID BIT(12)
|
||||
u16 nav_id;
|
||||
u16 index;
|
||||
u16 rx_fetch_size;
|
||||
u16 rxcq_qnum;
|
||||
u8 rx_priority;
|
||||
u8 rx_qos;
|
||||
u8 rx_orderid;
|
||||
u8 rx_sched_priority;
|
||||
u16 flowid_start;
|
||||
u16 flowid_cnt;
|
||||
u8 rx_pause_on_err;
|
||||
u8 rx_atype;
|
||||
u8 rx_chan_type;
|
||||
u8 rx_ignore_short;
|
||||
u8 rx_ignore_long;
|
||||
u8 rx_burst_size;
|
||||
};
|
||||
|
||||
/**
|
||||
* Configures a Navigator Subsystem UDMAP receive flow
|
||||
*
|
||||
* Configures a Navigator Subsystem UDMAP receive flow's registers.
|
||||
* See @tis_ci_msg_rm_udmap_flow_cfg_req
|
||||
*/
|
||||
struct ti_sci_msg_rm_udmap_flow_cfg {
|
||||
u32 valid_params;
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID BIT(0)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID BIT(1)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID BIT(2)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID BIT(3)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SOP_OFFSET_VALID BIT(4)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID BIT(5)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_VALID BIT(6)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_VALID BIT(7)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_VALID BIT(8)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_VALID BIT(9)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID BIT(10)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID BIT(11)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID BIT(12)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID BIT(13)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID BIT(14)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID BIT(15)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID BIT(16)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID BIT(17)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID BIT(18)
|
||||
u16 nav_id;
|
||||
u16 flow_index;
|
||||
u8 rx_einfo_present;
|
||||
u8 rx_psinfo_present;
|
||||
u8 rx_error_handling;
|
||||
u8 rx_desc_type;
|
||||
u16 rx_sop_offset;
|
||||
u16 rx_dest_qnum;
|
||||
u8 rx_src_tag_hi;
|
||||
u8 rx_src_tag_lo;
|
||||
u8 rx_dest_tag_hi;
|
||||
u8 rx_dest_tag_lo;
|
||||
u8 rx_src_tag_hi_sel;
|
||||
u8 rx_src_tag_lo_sel;
|
||||
u8 rx_dest_tag_hi_sel;
|
||||
u8 rx_dest_tag_lo_sel;
|
||||
u16 rx_fdq0_sz0_qnum;
|
||||
u16 rx_fdq1_qnum;
|
||||
u16 rx_fdq2_qnum;
|
||||
u16 rx_fdq3_qnum;
|
||||
u8 rx_ps_location;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ti_sci_rm_udmap_ops - UDMA Management operations
|
||||
* @tx_ch_cfg: configure SoC Navigator Subsystem UDMA transmit channel.
|
||||
* @rx_ch_cfg: configure SoC Navigator Subsystem UDMA receive channel.
|
||||
* @rx_flow_cfg1: configure SoC Navigator Subsystem UDMA receive flow.
|
||||
*/
|
||||
struct ti_sci_rm_udmap_ops {
|
||||
int (*tx_ch_cfg)(const struct ti_sci_handle *handle,
|
||||
const struct ti_sci_msg_rm_udmap_tx_ch_cfg *params);
|
||||
int (*rx_ch_cfg)(const struct ti_sci_handle *handle,
|
||||
const struct ti_sci_msg_rm_udmap_rx_ch_cfg *params);
|
||||
int (*rx_flow_cfg)(const struct ti_sci_handle *handle,
|
||||
const struct ti_sci_msg_rm_udmap_flow_cfg *params);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ti_sci_proc_ops - Processor Control operations
|
||||
* @request: Request to control a physical processor. The requesting host
|
||||
* should be in the processor access list
|
||||
* @release: Relinquish a physical processor control
|
||||
* @handover: Handover a physical processor control to another host
|
||||
* in the permitted list
|
||||
* @set_config: Set base configuration of a processor
|
||||
* @set_control: Setup limited control flags in specific cases
|
||||
* @get_status: Get the state of physical processor
|
||||
*
|
||||
* NOTE: The following paramteres are generic in nature for all these ops,
|
||||
* -handle: Pointer to TI SCI handle as retrieved by *ti_sci_get_handle
|
||||
* -pid: Processor ID
|
||||
* -hid: Host ID
|
||||
*/
|
||||
struct ti_sci_proc_ops {
|
||||
int (*request)(const struct ti_sci_handle *handle, u8 pid);
|
||||
int (*release)(const struct ti_sci_handle *handle, u8 pid);
|
||||
int (*handover)(const struct ti_sci_handle *handle, u8 pid, u8 hid);
|
||||
int (*set_config)(const struct ti_sci_handle *handle, u8 pid,
|
||||
u64 boot_vector, u32 cfg_set, u32 cfg_clr);
|
||||
int (*set_control)(const struct ti_sci_handle *handle, u8 pid,
|
||||
u32 ctrl_set, u32 ctrl_clr);
|
||||
int (*get_status)(const struct ti_sci_handle *handle, u8 pid,
|
||||
u64 *boot_vector, u32 *cfg_flags, u32 *ctrl_flags,
|
||||
u32 *status_flags);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ti_sci_ops - Function support for TI SCI
|
||||
* @dev_ops: Device specific operations
|
||||
* @clk_ops: Clock specific operations
|
||||
* @rm_core_ops: Resource management core operations.
|
||||
* @rm_irq_ops: IRQ management specific operations
|
||||
* @proc_ops: Processor Control specific operations
|
||||
*/
|
||||
struct ti_sci_ops {
|
||||
struct ti_sci_core_ops core_ops;
|
||||
@@ -254,6 +496,10 @@ struct ti_sci_ops {
|
||||
struct ti_sci_clk_ops clk_ops;
|
||||
struct ti_sci_rm_core_ops rm_core_ops;
|
||||
struct ti_sci_rm_irq_ops rm_irq_ops;
|
||||
struct ti_sci_rm_ringacc_ops rm_ring_ops;
|
||||
struct ti_sci_rm_psil_ops rm_psil_ops;
|
||||
struct ti_sci_rm_udmap_ops rm_udmap_ops;
|
||||
struct ti_sci_proc_ops proc_ops;
|
||||
};
|
||||
|
||||
/**
|
||||
|
||||
@@ -1,172 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Definitions for DDR memories based on JEDEC specs
|
||||
*
|
||||
* Copyright (C) 2012 Texas Instruments, Inc.
|
||||
*
|
||||
* Aneesh V <aneesh@ti.com>
|
||||
*/
|
||||
#ifndef __LINUX_JEDEC_DDR_H
|
||||
#define __LINUX_JEDEC_DDR_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
/* DDR Densities */
|
||||
#define DDR_DENSITY_64Mb 1
|
||||
#define DDR_DENSITY_128Mb 2
|
||||
#define DDR_DENSITY_256Mb 3
|
||||
#define DDR_DENSITY_512Mb 4
|
||||
#define DDR_DENSITY_1Gb 5
|
||||
#define DDR_DENSITY_2Gb 6
|
||||
#define DDR_DENSITY_4Gb 7
|
||||
#define DDR_DENSITY_8Gb 8
|
||||
#define DDR_DENSITY_16Gb 9
|
||||
#define DDR_DENSITY_32Gb 10
|
||||
|
||||
/* DDR type */
|
||||
#define DDR_TYPE_DDR2 1
|
||||
#define DDR_TYPE_DDR3 2
|
||||
#define DDR_TYPE_LPDDR2_S4 3
|
||||
#define DDR_TYPE_LPDDR2_S2 4
|
||||
#define DDR_TYPE_LPDDR2_NVM 5
|
||||
|
||||
/* DDR IO width */
|
||||
#define DDR_IO_WIDTH_4 1
|
||||
#define DDR_IO_WIDTH_8 2
|
||||
#define DDR_IO_WIDTH_16 3
|
||||
#define DDR_IO_WIDTH_32 4
|
||||
|
||||
/* Number of Row bits */
|
||||
#define R9 9
|
||||
#define R10 10
|
||||
#define R11 11
|
||||
#define R12 12
|
||||
#define R13 13
|
||||
#define R14 14
|
||||
#define R15 15
|
||||
#define R16 16
|
||||
|
||||
/* Number of Column bits */
|
||||
#define C7 7
|
||||
#define C8 8
|
||||
#define C9 9
|
||||
#define C10 10
|
||||
#define C11 11
|
||||
#define C12 12
|
||||
|
||||
/* Number of Banks */
|
||||
#define B1 0
|
||||
#define B2 1
|
||||
#define B4 2
|
||||
#define B8 3
|
||||
|
||||
/* Refresh rate in nano-seconds */
|
||||
#define T_REFI_15_6 15600
|
||||
#define T_REFI_7_8 7800
|
||||
#define T_REFI_3_9 3900
|
||||
|
||||
/* tRFC values */
|
||||
#define T_RFC_90 90000
|
||||
#define T_RFC_110 110000
|
||||
#define T_RFC_130 130000
|
||||
#define T_RFC_160 160000
|
||||
#define T_RFC_210 210000
|
||||
#define T_RFC_300 300000
|
||||
#define T_RFC_350 350000
|
||||
|
||||
/* Mode register numbers */
|
||||
#define DDR_MR0 0
|
||||
#define DDR_MR1 1
|
||||
#define DDR_MR2 2
|
||||
#define DDR_MR3 3
|
||||
#define DDR_MR4 4
|
||||
#define DDR_MR5 5
|
||||
#define DDR_MR6 6
|
||||
#define DDR_MR7 7
|
||||
#define DDR_MR8 8
|
||||
#define DDR_MR9 9
|
||||
#define DDR_MR10 10
|
||||
#define DDR_MR11 11
|
||||
#define DDR_MR16 16
|
||||
#define DDR_MR17 17
|
||||
#define DDR_MR18 18
|
||||
|
||||
/*
|
||||
* LPDDR2 related defines
|
||||
*/
|
||||
|
||||
/* MR4 register fields */
|
||||
#define MR4_SDRAM_REF_RATE_SHIFT 0
|
||||
#define MR4_SDRAM_REF_RATE_MASK 7
|
||||
#define MR4_TUF_SHIFT 7
|
||||
#define MR4_TUF_MASK (1 << 7)
|
||||
|
||||
/* MR4 SDRAM Refresh Rate field values */
|
||||
#define SDRAM_TEMP_NOMINAL 0x3
|
||||
#define SDRAM_TEMP_RESERVED_4 0x4
|
||||
#define SDRAM_TEMP_HIGH_DERATE_REFRESH 0x5
|
||||
#define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS 0x6
|
||||
#define SDRAM_TEMP_VERY_HIGH_SHUTDOWN 0x7
|
||||
|
||||
#define NUM_DDR_ADDR_TABLE_ENTRIES 11
|
||||
#define NUM_DDR_TIMING_TABLE_ENTRIES 4
|
||||
|
||||
/* Structure for DDR addressing info from the JEDEC spec */
|
||||
struct lpddr2_addressing {
|
||||
u32 num_banks;
|
||||
u32 tREFI_ns;
|
||||
u32 tRFCab_ps;
|
||||
};
|
||||
|
||||
/*
|
||||
* Structure for timings from the LPDDR2 datasheet
|
||||
* All parameters are in pico seconds(ps) unless explicitly indicated
|
||||
* with a suffix like tRAS_max_ns below
|
||||
*/
|
||||
struct lpddr2_timings {
|
||||
u32 max_freq;
|
||||
u32 min_freq;
|
||||
u32 tRPab;
|
||||
u32 tRCD;
|
||||
u32 tWR;
|
||||
u32 tRAS_min;
|
||||
u32 tRRD;
|
||||
u32 tWTR;
|
||||
u32 tXP;
|
||||
u32 tRTP;
|
||||
u32 tCKESR;
|
||||
u32 tDQSCK_max;
|
||||
u32 tDQSCK_max_derated;
|
||||
u32 tFAW;
|
||||
u32 tZQCS;
|
||||
u32 tZQCL;
|
||||
u32 tZQinit;
|
||||
u32 tRAS_max_ns;
|
||||
};
|
||||
|
||||
/*
|
||||
* Min value for some parameters in terms of number of tCK cycles(nCK)
|
||||
* Please set to zero parameters that are not valid for a given memory
|
||||
* type
|
||||
*/
|
||||
struct lpddr2_min_tck {
|
||||
u32 tRPab;
|
||||
u32 tRCD;
|
||||
u32 tWR;
|
||||
u32 tRASmin;
|
||||
u32 tRRD;
|
||||
u32 tWTR;
|
||||
u32 tXP;
|
||||
u32 tRTP;
|
||||
u32 tCKE;
|
||||
u32 tCKESR;
|
||||
u32 tFAW;
|
||||
};
|
||||
|
||||
extern const struct lpddr2_addressing
|
||||
lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES];
|
||||
extern const struct lpddr2_timings
|
||||
lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES];
|
||||
extern const struct lpddr2_min_tck lpddr2_jedec_min_tck;
|
||||
|
||||
#endif /* __LINUX_JEDEC_DDR_H */
|
||||
@@ -133,5 +133,13 @@ int bman_acquire(struct bman_pool *pool, struct bm_buffer *bufs, u8 num);
|
||||
* failed to probe or 0 if the bman driver did not probed yet.
|
||||
*/
|
||||
int bman_is_probed(void);
|
||||
/**
|
||||
* bman_portals_probed - Check if all cpu bound bman portals are probed
|
||||
*
|
||||
* Returns 1 if all the required cpu bound bman portals successfully probed,
|
||||
* -1 if probe errors appeared or 0 if the bman portals did not yet finished
|
||||
* probing.
|
||||
*/
|
||||
int bman_portals_probed(void);
|
||||
|
||||
#endif /* __FSL_BMAN_H */
|
||||
|
||||
@@ -1194,6 +1194,15 @@ int qman_release_cgrid(u32 id);
|
||||
*/
|
||||
int qman_is_probed(void);
|
||||
|
||||
/**
|
||||
* qman_portals_probed - Check if all cpu bound qman portals are probed
|
||||
*
|
||||
* Returns 1 if all the required cpu bound qman portals successfully probed,
|
||||
* -1 if probe errors appeared or 0 if the qman portals did not yet finished
|
||||
* probing.
|
||||
*/
|
||||
int qman_portals_probed(void);
|
||||
|
||||
/**
|
||||
* qman_dqrr_get_ithresh - Get coalesce interrupt threshold
|
||||
* @portal: portal to get the value for
|
||||
|
||||
Reference in New Issue
Block a user