From ec9cd359248b2f8d7fb385f3f97f0c2e5cdbd381 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 1 Mar 2018 16:25:12 +0100 Subject: [PATCH 01/11] arm64: dts: rockchip: enable typec-phy for rk3399-sapphire Commit c301b327aea898af ("arm64: dts: rockchip: add usb3-phy otg-port support for rk3399") caused a regression regarding the USB3 type-A port. During boot, the following message appears a few times: dwc3: failed to initialize core The driver is deferred waiting for the typec-phy, but this never happens bceause is disabled. So, enable it. The offending commit was reverted in 4.16-rc but can be re-applied after enabling the typec phys. Reported-by: Vicente Bergas Signed-off-by: Enric Balletbo i Serra Tested-by: Vicente Bergas Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi index e5daed7d2026..96c097b56c85 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi @@ -560,6 +560,14 @@ &sdmmc { status = "okay"; }; +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + &tsadc { /* tshut mode 0:CRU 1:GPIO */ rockchip,hw-tshut-mode = <1>; From 1438c1d2fc7e7e735563c4746c7f9038603de349 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 1 Mar 2018 16:25:13 +0100 Subject: [PATCH 02/11] arm64: dts: rockchip: enable typec-phy for rk3399-firefly Commit c301b327aea898af ("arm64: dts: rockchip: add usb3-phy otg-port support for rk3399") caused a regression regarding the USB3. During boot, the following message appears a few times: dwc3: failed to initialize core The driver is deferred waiting for the typec-phy, but this never happens beause is disabled. So, enable it. The offending commit was reverted in 4.16-rc but can be re-applied after enabling the typec phys. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-firefly.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts index 4f28628aa091..2a352763c848 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts @@ -662,6 +662,14 @@ &sdhci { status = "okay"; }; +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + &tsadc { /* tshut mode 0:CRU 1:GPIO */ rockchip,hw-tshut-mode = <1>; From fd3e830387d688f37827d526049746f6df7b324a Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 1 Mar 2018 16:25:14 +0100 Subject: [PATCH 03/11] arm64: dts: rockchip: enable typec-phy1 for rk3399-puma Commit c301b327aea898af ("arm64: dts: rockchip: add usb3-phy otg-port support for rk3399") caused a regression regarding the USB3. During boot, the following message appears a few times: dwc3: failed to initialize core The driver is deferred waiting for the typec-phy, but this never happens beause is disabled. So, enable it. The offending commit was reverted in 4.16-rc but can be re-applied after enabling the typec phys. Signed-off-by: Enric Balletbo i Serra Tested-by: Klaus Goger Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi index 4a2d06abe9c1..14a0f1998639 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi @@ -527,6 +527,10 @@ norflash: flash@0 { }; }; +&tcphy1 { + status = "okay"; +}; + &tsadc { rockchip,hw-tshut-mode = <1>; rockchip,hw-tshut-polarity = <1>; From 7c573e3741e5b22112304bddb7534e8ad59cc146 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 1 Mar 2018 16:25:15 +0100 Subject: [PATCH 04/11] arm64: dts: rockchip: enable typec-phy0 for rk3399-puma-haikou Commit c301b327aea898af ("arm64: dts: rockchip: add usb3-phy otg-port support for rk3399") caused a regression regarding the USB3. During boot, the following message appears a few times: dwc3: failed to initialize core The driver is deferred waiting for the typec-phy, but this never happens beause is disabled. So, enable it. The offending commit was reverted in 4.16-rc but can be re-applied after enabling the typec phys. Signed-off-by: Enric Balletbo i Serra Tested-by: Klaus Goger Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts index 7d3e8bfd51dd..bb2b5a804408 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts @@ -246,6 +246,10 @@ &spi5 { status = "okay"; }; +&tcphy0 { + status = "okay"; +}; + &u2phy0 { status = "okay"; }; From e702e13f0b4ffbe3178a39bb878b37121cbd05e2 Mon Sep 17 00:00:00 2001 From: Lin Huang Date: Tue, 20 Mar 2018 10:06:29 +0800 Subject: [PATCH 05/11] arm64: dts: rockchip: assign clock rate for cpll child clocks on rk3399 These clocks do not assign default clock frequency, and use the default cru register value to get frequency, so if cpll increase frequency, these clocks also increase their frequency, that may exceed their signed off frequency. So assign default clock for them to avoid it. NOTE: on none of the boards currently in mainline do we expect CPLL to be anything other than 800 MHz, but some future boards might have it. It's still good to be explicit about the clock rates to make diffing against future boards easier and also to rely less on BIOS muxing. Signed-off-by: Lin Huang Reviewed-by: Douglas Anderson Reviewed-by: Shawn Lin Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 8 ++++++-- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 14 ++++++++++---- 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi index 18f546f2dfd1..f49bfab75dd0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -588,7 +588,9 @@ &cru { <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, - <&cru ACLK_VIO>; + <&cru ACLK_VIO>, <&cru ACLK_HDCP>, + <&cru ACLK_GIC_PRE>, + <&cru PCLK_DDR>; assigned-clock-rates = <600000000>, <800000000>, <1000000000>, @@ -597,7 +599,9 @@ &cru { <100000000>, <100000000>, <50000000>, <800000000>, <100000000>, <50000000>, - <400000000>; + <400000000>, <400000000>, + <200000000>, + <200000000>; }; &emmc_phy { diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 4550c0f82be9..384a0c2ce55a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -312,6 +312,8 @@ sdmmc: dwmmc@fe320000 { reg = <0x0 0xfe320000 0x0 0x4000>; interrupts = ; max-frequency = <150000000>; + assigned-clocks = <&cru HCLK_SD>; + assigned-clock-rates = <200000000>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; @@ -461,8 +463,8 @@ cdn_dp: dp@fec00000 { compatible = "rockchip,rk3399-cdn-dp"; reg = <0x0 0xfec00000 0x0 0x100000>; interrupts = ; - assigned-clocks = <&cru SCLK_DP_CORE>; - assigned-clock-rates = <100000000>; + assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>; + assigned-clock-rates = <100000000>, <200000000>; clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; clock-names = "core-clk", "pclk", "spdif", "grf"; @@ -1323,7 +1325,9 @@ cru: clock-controller@ff760000 { <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, - <&cru ACLK_VIO>; + <&cru ACLK_VIO>, <&cru ACLK_HDCP>, + <&cru ACLK_GIC_PRE>, + <&cru PCLK_DDR>; assigned-clock-rates = <594000000>, <800000000>, <1000000000>, @@ -1332,7 +1336,9 @@ cru: clock-controller@ff760000 { <100000000>, <100000000>, <50000000>, <600000000>, <100000000>, <50000000>, - <400000000>; + <400000000>, <400000000>, + <200000000>, + <200000000>; }; grf: syscon@ff770000 { From 2bbb0c0e6a7164c1fbfb5c0474ab7c208c02dab8 Mon Sep 17 00:00:00 2001 From: Vicente Bergas Date: Mon, 26 Feb 2018 19:57:21 +0100 Subject: [PATCH 06/11] arm64: dts: rockchip: move rk3399-sapphire PCIe to excavator baseboard The PCIe signals are routed through the connector to the baseboard. Signed-off-by: Vicente Bergas Reviewed-by: Shawn Lin Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3399-sapphire-excavator.dts | 15 +++++++++++++++ arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi | 15 --------------- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts index 56952d1a3fb8..2ce7ce7bb778 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts @@ -190,6 +190,21 @@ &i2s0 { status = "okay"; }; +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + assigned-clocks = <&cru SCLK_PCIEPHY_REF>; + assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; + assigned-clock-rates = <100000000>; + ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>; + status = "okay"; +}; + &pinctrl { sdio-pwrseq { wifi_enable_h: wifi-enable-h { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi index 96c097b56c85..941b627094d7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi @@ -471,21 +471,6 @@ &io_domains { gpio1830-supply = <&vcc_3v0>; }; -&pcie_phy { - status = "okay"; -}; - -&pcie0 { - assigned-clocks = <&cru SCLK_PCIEPHY_REF>; - assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; - assigned-clock-rates = <100000000>; - ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreqn_cpm>; - status = "okay"; -}; - &pmu_io_domains { pmu1830-supply = <&vcc_3v0>; status = "okay"; From 557cb8eb6218e328d708d8fa2b95ba599a8a37f1 Mon Sep 17 00:00:00 2001 From: Vicente Bergas Date: Tue, 27 Feb 2018 19:28:22 +0100 Subject: [PATCH 07/11] arm64: dts: rockchip: remove PCIe assigned-clocks in excavator baseboard Reference clock is needed for pcie_phy, not pcie controller. Actually pcie_phy doesn't need this since rk3399 clock driver already take care of this. Suggested-by: Shawn Lin Signed-off-by: Vicente Bergas Reviewed-by: Shawn Lin Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts index 2ce7ce7bb778..ad7548d3b93d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts @@ -195,9 +195,6 @@ &pcie_phy { }; &pcie0 { - assigned-clocks = <&cru SCLK_PCIEPHY_REF>; - assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; - assigned-clock-rates = <100000000>; ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; num-lanes = <4>; pinctrl-names = "default"; From bfdca1736ea76345071bbc5607d18928e54909ac Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Fri, 15 Dec 2017 12:00:03 +0100 Subject: [PATCH 08/11] arm64: dts: rockchip: add usb3-phy otg-port support for rk3399 Add the usb3 phyter for the USB3.0 OTG controller. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 384a0c2ce55a..e4a054a446d5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -413,8 +413,8 @@ usbdrd_dwc3_0: dwc3 { reg = <0x0 0xfe800000 0x0 0x100000>; interrupts = ; dr_mode = "otg"; - phys = <&u2phy0_otg>; - phy-names = "usb2-phy"; + phys = <&u2phy0_otg>, <&tcphy0_usb3>; + phy-names = "usb2-phy", "usb3-phy"; phy_type = "utmi_wide"; snps,dis_enblslpm_quirk; snps,dis-u2-freeclk-exists-quirk; @@ -446,8 +446,8 @@ usbdrd_dwc3_1: dwc3 { reg = <0x0 0xfe900000 0x0 0x100000>; interrupts = ; dr_mode = "otg"; - phys = <&u2phy1_otg>; - phy-names = "usb2-phy"; + phys = <&u2phy1_otg>, <&tcphy1_usb3>; + phy-names = "usb2-phy", "usb3-phy"; phy_type = "utmi_wide"; snps,dis_enblslpm_quirk; snps,dis-u2-freeclk-exists-quirk; From df3bcde704fb51645615635667944fc550c493e2 Mon Sep 17 00:00:00 2001 From: Jeffy Chen Date: Fri, 23 Mar 2018 15:38:07 +0800 Subject: [PATCH 09/11] arm64: dts: rockchip: add clocks in iommu nodes Add clocks in iommu nodes, since we are going to control clocks in rockchip iommu driver. Signed-off-by: Jeffy Chen Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 10 ++++++++++ arch/arm64/boot/dts/rockchip/rk3368.dtsi | 10 ++++++++++ arch/arm64/boot/dts/rockchip/rk3399.dtsi | 14 ++++++++++++-- 3 files changed, 32 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index be2bfbc6b483..b8e9da15e00c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -595,6 +595,8 @@ h265e_mmu: iommu@ff330200 { reg = <0x0 0xff330200 0 0x100>; interrupts = ; interrupt-names = "h265e_mmu"; + clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; + clock-names = "aclk", "iface"; #iommu-cells = <0>; status = "disabled"; }; @@ -604,6 +606,8 @@ vepu_mmu: iommu@ff340800 { reg = <0x0 0xff340800 0x0 0x40>; interrupts = ; interrupt-names = "vepu_mmu"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "iface"; #iommu-cells = <0>; status = "disabled"; }; @@ -613,6 +617,8 @@ vpu_mmu: iommu@ff350800 { reg = <0x0 0xff350800 0x0 0x40>; interrupts = ; interrupt-names = "vpu_mmu"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "iface"; #iommu-cells = <0>; status = "disabled"; }; @@ -622,6 +628,8 @@ rkvdec_mmu: iommu@ff360480 { reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; interrupts = ; interrupt-names = "rkvdec_mmu"; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; + clock-names = "aclk", "iface"; #iommu-cells = <0>; status = "disabled"; }; @@ -631,6 +639,8 @@ vop_mmu: iommu@ff373f00 { reg = <0x0 0xff373f00 0x0 0x100>; interrupts = ; interrupt-names = "vop_mmu"; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; #iommu-cells = <0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index 03458ac44201..ad91ced78649 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -742,6 +742,8 @@ iep_mmu: iommu@ff900800 { reg = <0x0 0xff900800 0x0 0x100>; interrupts = ; interrupt-names = "iep_mmu"; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk", "iface"; #iommu-cells = <0>; status = "disabled"; }; @@ -752,6 +754,8 @@ isp_mmu: iommu@ff914000 { <0x0 0xff915000 0x0 0x100>; interrupts = ; interrupt-names = "isp_mmu"; + clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; + clock-names = "aclk", "iface"; #iommu-cells = <0>; rockchip,disable-mmu-reset; status = "disabled"; @@ -762,6 +766,8 @@ vop_mmu: iommu@ff930300 { reg = <0x0 0xff930300 0x0 0x100>; interrupts = ; interrupt-names = "vop_mmu"; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; #iommu-cells = <0>; status = "disabled"; }; @@ -772,6 +778,8 @@ hevc_mmu: iommu@ff9a0440 { <0x0 0xff9a0480 0x0 0x40>; interrupts = ; interrupt-names = "hevc_mmu"; + clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>; + clock-names = "aclk", "iface"; #iommu-cells = <0>; status = "disabled"; }; @@ -782,6 +790,8 @@ vpu_mmu: iommu@ff9a0800 { interrupts = , ; interrupt-names = "vepu_mmu", "vdpu_mmu"; + clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>; + clock-names = "aclk", "iface"; #iommu-cells = <0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index e4a054a446d5..e0040b648f43 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1236,6 +1236,8 @@ vpu_mmu: iommu@ff650800 { reg = <0x0 0xff650800 0x0 0x40>; interrupts = ; interrupt-names = "vpu_mmu"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "iface"; #iommu-cells = <0>; status = "disabled"; }; @@ -1245,6 +1247,8 @@ vdec_mmu: iommu@ff660480 { reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; interrupts = ; interrupt-names = "vdec_mmu"; + clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; + clock-names = "aclk", "iface"; #iommu-cells = <0>; status = "disabled"; }; @@ -1254,6 +1258,8 @@ iep_mmu: iommu@ff670800 { reg = <0x0 0xff670800 0x0 0x40>; interrupts = ; interrupt-names = "iep_mmu"; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk", "iface"; #iommu-cells = <0>; status = "disabled"; }; @@ -1605,7 +1611,7 @@ vopl_mmu: iommu@ff8f3f00 { interrupts = ; interrupt-names = "vopl_mmu"; clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; - clock-names = "aclk", "hclk"; + clock-names = "aclk", "iface"; power-domains = <&power RK3399_PD_VOPL>; #iommu-cells = <0>; status = "disabled"; @@ -1662,7 +1668,7 @@ vopb_mmu: iommu@ff903f00 { interrupts = ; interrupt-names = "vopb_mmu"; clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; - clock-names = "aclk", "hclk"; + clock-names = "aclk", "iface"; power-domains = <&power RK3399_PD_VOPB>; #iommu-cells = <0>; status = "disabled"; @@ -1673,6 +1679,8 @@ isp0_mmu: iommu@ff914000 { reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; interrupts = ; interrupt-names = "isp0_mmu"; + clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>; + clock-names = "aclk", "iface"; #iommu-cells = <0>; rockchip,disable-mmu-reset; status = "disabled"; @@ -1683,6 +1691,8 @@ isp1_mmu: iommu@ff924000 { reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; interrupts = ; interrupt-names = "isp1_mmu"; + clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>; + clock-names = "aclk", "iface"; #iommu-cells = <0>; rockchip,disable-mmu-reset; status = "disabled"; From 5041bb82f83d281ec3302aadbbc3fbad73983872 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Tue, 1 May 2018 15:46:28 -0700 Subject: [PATCH 10/11] arm64: dts: rockchip: use canonical compatible for touchpad/touchscreen on gru-kevin "atmel,atmel_mxt_tp" and "atmel,atmel_mxt_ts" are ChromeOS inventions, let's replace them with canonical compatible string "atmel,maxtouch". Signed-off-by: Dmitry Torokhov Reviewed-by: Brian Norris Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts index 191a6bcb1704..82179125bfb7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts @@ -255,7 +255,7 @@ digitizer: digitizer@9 { &ap_i2c_tp { trackpad@4a { - compatible = "atmel,atmel_mxt_tp"; + compatible = "atmel,maxtouch"; reg = <0x4a>; pinctrl-names = "default"; pinctrl-0 = <&trackpad_int_l>; @@ -271,7 +271,7 @@ KEY_RESERVED &ap_i2c_ts { touchscreen@4b { - compatible = "atmel,atmel_mxt_ts"; + compatible = "atmel,maxtouch"; reg = <0x4b>; pinctrl-names = "default"; pinctrl-0 = <&touch_int_l>; From 17bd0737948aa841b76278a601217b914aa5f18e Mon Sep 17 00:00:00 2001 From: Jakob Unterwurzacher Date: Tue, 24 Apr 2018 16:24:59 +0200 Subject: [PATCH 11/11] arm64: dts: rockchip: enable hdmi on rk3399-puma-haikou The Puma-haikou combo supports hdmi output, so enable the hdmi controller and vop controllers on it. Signed-off-by: Jakob Unterwurzacher Cc: linux-rockchip@lists.infradead.org Cc: Heiko Stuebner Cc: Klaus Goger Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-puma-haikou.dts | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts index bb2b5a804408..e0afdd8b62bd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts @@ -143,6 +143,11 @@ vddd_codec: vddd-codec { }; }; +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + &i2c1 { status = "okay"; clock-frequency = <400000>; @@ -285,3 +290,19 @@ &usb_host0_ehci { &usb_host0_ohci { status = "okay"; }; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +};