From 81964f539601f3dcbf1ed64979aa9b5ae0e4adf4 Mon Sep 17 00:00:00 2001 From: Koichiro Den Date: Tue, 21 Jul 2026 15:28:13 +0900 Subject: [PATCH] dmaengine: dw-edma-pcie: Handle optional data blocks Skip data block BAR mapping and debug output when a channel has no data block size. This lets future providers describe channels that only need descriptor memory exposed. No functional change intended for existing Synopsys EDDA and AMD (Xilinx) MDB/CPM6 devices. Their static channel descriptions still provide data block sizes where data block windows are used. A zero-sized data block now means "not present" for future metadata providers. Reviewed-by: Frank Li Signed-off-by: Koichiro Den Link: https://patch.msgid.link/20260721062815.4117887-13-den@valinux.co.jp Signed-off-by: Vinod Koul --- drivers/dma/dw-edma/dw-edma-pcie.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c index 6da890a4ad28..37be455b7b6f 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -430,11 +430,13 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, mask = BIT(dma_data->rg.bar); for (i = 0; i < dma_data->wr_ch_cnt; i++) { mask |= BIT(dma_data->ll_wr[i].bar); - mask |= BIT(dma_data->dt_wr[i].bar); + if (dma_data->dt_wr[i].sz) + mask |= BIT(dma_data->dt_wr[i].bar); } for (i = 0; i < dma_data->rd_ch_cnt; i++) { mask |= BIT(dma_data->ll_rd[i].bar); - mask |= BIT(dma_data->dt_rd[i].bar); + if (dma_data->dt_rd[i].sz) + mask |= BIT(dma_data->dt_rd[i].bar); } err = pcim_iomap_regions(pdev, mask, pci_name(pdev)); if (err) { @@ -497,6 +499,9 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, ll_block); ll_region->sz = ll_block->sz; + if (!dt_block->sz) + continue; + dt_region->vaddr.io = pcim_iomap_table(pdev)[dt_block->bar]; if (!dt_region->vaddr.io) return -ENOMEM; @@ -522,6 +527,9 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, ll_block); ll_region->sz = ll_block->sz; + if (!dt_block->sz) + continue; + dt_region->vaddr.io = pcim_iomap_table(pdev)[dt_block->bar]; if (!dt_region->vaddr.io) return -ENOMEM; @@ -555,10 +563,14 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, dma_data->ll_wr[i].off, chip->ll_region_wr[i].sz, chip->ll_region_wr[i].vaddr.io, &chip->ll_region_wr[i].paddr); + if (!dma_data->dt_wr[i].sz) + continue; + pci_dbg(pdev, "Data:\tWRITE CH%.2u, BAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n", i, dma_data->dt_wr[i].bar, dma_data->dt_wr[i].off, chip->dt_region_wr[i].sz, - chip->dt_region_wr[i].vaddr.io, &chip->dt_region_wr[i].paddr); + chip->dt_region_wr[i].vaddr.io, + &chip->dt_region_wr[i].paddr); } for (i = 0; i < chip->ll_rd_cnt; i++) { @@ -567,10 +579,14 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, dma_data->ll_rd[i].off, chip->ll_region_rd[i].sz, chip->ll_region_rd[i].vaddr.io, &chip->ll_region_rd[i].paddr); + if (!dma_data->dt_rd[i].sz) + continue; + pci_dbg(pdev, "Data:\tREAD CH%.2u, BAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n", i, dma_data->dt_rd[i].bar, dma_data->dt_rd[i].off, chip->dt_region_rd[i].sz, - chip->dt_region_rd[i].vaddr.io, &chip->dt_region_rd[i].paddr); + chip->dt_region_rd[i].vaddr.io, + &chip->dt_region_rd[i].paddr); } pci_dbg(pdev, "Nr. IRQs:\t%u\n", chip->nr_irqs);