From e00d100a94a15531eec0caf2dddfeec439690097 Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Wed, 20 Mar 2024 22:33:49 +0100 Subject: [PATCH 1/2] ARM: dts: st: add thermal property on stih410.dtsi and stih418.dtsi "#thermal-sensor-cells" is required and missing in thermal nodes. Add it. Signed-off-by: Raphael Gallais-Pou Reviewed-by: Patrice Chotard Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/st/stih410.dtsi | 1 + arch/arm/boot/dts/st/stih418.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/st/stih410.dtsi b/arch/arm/boot/dts/st/stih410.dtsi index 29e95e9d3229..a69231854f78 100644 --- a/arch/arm/boot/dts/st/stih410.dtsi +++ b/arch/arm/boot/dts/st/stih410.dtsi @@ -270,6 +270,7 @@ thermal@91a0000 { clock-names = "thermal"; clocks = <&clk_sysin>; interrupts = ; + #thermal-sensor-cells = <0>; }; cec@94a087c { diff --git a/arch/arm/boot/dts/st/stih418.dtsi b/arch/arm/boot/dts/st/stih418.dtsi index b35b9b7a7ccc..0f0db988a907 100644 --- a/arch/arm/boot/dts/st/stih418.dtsi +++ b/arch/arm/boot/dts/st/stih418.dtsi @@ -113,6 +113,7 @@ thermal@91a0000 { clock-names = "thermal"; clocks = <&clk_sysin>; interrupts = ; + #thermal-sensor-cells = <0>; }; }; }; From b664f6f7a77a41b0e8da7e12534debc94c9d23db Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Tue, 25 Jun 2024 23:32:42 +0200 Subject: [PATCH 2/2] ARM: dts: sti: add thermal-zones support on stih418 Add a 'thermal-zones' node for stih418. A thermal-zone needs three components: - thermal sensors, described in an earlier commit[1] - cooling devices, specified for each CPU - a thermal zone, describing the overall behavior. The thermal zone needs references to both CPUs and thermal sensors, which phandle are also added. The thermal management will then be achieved on CPUs using the cpufreq framework. [1] https://lore.kernel.org/lkml/20240320-thermal-v3-2-700296694c4a@gmail.com/ Reviewed-by: Patrice Chotard Signed-off-by: Raphael Gallais-Pou Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/st/stih407-family.dtsi | 6 ++-- arch/arm/boot/dts/st/stih418.dtsi | 41 ++++++++++++++++++++++-- 2 files changed, 42 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/st/stih407-family.dtsi b/arch/arm/boot/dts/st/stih407-family.dtsi index 29302e74aa1d..35a55aef7f4b 100644 --- a/arch/arm/boot/dts/st/stih407-family.dtsi +++ b/arch/arm/boot/dts/st/stih407-family.dtsi @@ -33,7 +33,7 @@ delta_reserved: rproc@44000000 { cpus { #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; @@ -52,8 +52,9 @@ cpu@0 { clock-latency = <100000>; cpu0-supply = <&pwm_regulator>; st,syscfg = <&syscfg_core 0x8e0>; + #cooling-cells = <2>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; @@ -66,6 +67,7 @@ cpu@1 { 1200000 0 800000 0 500000 0>; + #cooling-cells = <2>; }; }; diff --git a/arch/arm/boot/dts/st/stih418.dtsi b/arch/arm/boot/dts/st/stih418.dtsi index 0f0db988a907..8fb8b3af5e49 100644 --- a/arch/arm/boot/dts/st/stih418.dtsi +++ b/arch/arm/boot/dts/st/stih418.dtsi @@ -6,23 +6,26 @@ #include "stih418-clock.dtsi" #include "stih407-family.dtsi" #include "stih410-pinctrl.dtsi" +#include / { cpus { #address-cells = <1>; #size-cells = <0>; - cpu@2 { + cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <2>; /* u-boot puts hpen in SBC dmem at 0xa4 offset */ cpu-release-addr = <0x94100A4>; + #cooling-cells = <2>; }; - cpu@3 { + cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <3>; /* u-boot puts hpen in SBC dmem at 0xa4 offset */ cpu-release-addr = <0x94100A4>; + #cooling-cells = <2>; }; }; @@ -44,6 +47,38 @@ usb2_picophy2: phy3 { reset-names = "global", "port"; }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <250>; /* 250ms */ + polling-delay = <1000>; /* 1000ms */ + + thermal-sensors = <&thermal>; + + trips { + cpu_crit: cpu-crit { + temperature = <95000>; /* 95C */ + hysteresis = <2000>; + type = "critical"; + }; + cpu_alert: cpu-alert { + temperature = <85000>; /* 85C */ + hysteresis = <2000>; + type = "passive"; + }; + }; + + cooling-maps { + map { + trip = <&cpu_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + soc { rng11: rng@8a8a000 { status = "disabled"; @@ -107,7 +142,7 @@ mmc0: sdhci@9060000 { assigned-clock-rates = <200000000>; }; - thermal@91a0000 { + thermal: thermal@91a0000 { compatible = "st,stih407-thermal"; reg = <0x91a0000 0x28>; clock-names = "thermal";