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arm64: dts: qcom: sc7280: Add cpufreq hw node

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Add cpufreq HW device node to scale 4-Silver/3-Gold/1-Gold+
cores on SC7280 SoCs.

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1618020280-5470-2-git-send-email-tdas@codeaurora.org
[bjorn: Dropped reg-names]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Taniya Das
2021-04-10 07:34:39 +05:30
committed by Bjorn Andersson
parent 822c8f2a2f
commit 7dbd121a2c
1 changed files with 18 additions and 0 deletions
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18
arch/arm64/boot/dts/qcom/sc7280.dtsi
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@@ -71,6 +71,7 @@ CPU0: cpu@0 {
&LITTLE_CPU_SLEEP_1 &LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>; &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>; #cooling-cells = <2>;
L2_0: l2-cache { L2_0: l2-cache {
compatible = "cache"; compatible = "cache";
@@ -90,6 +91,7 @@ CPU1: cpu@100 {
&LITTLE_CPU_SLEEP_1 &LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>; &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_100>; next-level-cache = <&L2_100>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>; #cooling-cells = <2>;
L2_100: l2-cache { L2_100: l2-cache {
compatible = "cache"; compatible = "cache";
@@ -106,6 +108,7 @@ CPU2: cpu@200 {
&LITTLE_CPU_SLEEP_1 &LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>; &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_200>; next-level-cache = <&L2_200>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>; #cooling-cells = <2>;
L2_200: l2-cache { L2_200: l2-cache {
compatible = "cache"; compatible = "cache";
@@ -122,6 +125,7 @@ CPU3: cpu@300 {
&LITTLE_CPU_SLEEP_1 &LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>; &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_300>; next-level-cache = <&L2_300>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>; #cooling-cells = <2>;
L2_300: l2-cache { L2_300: l2-cache {
compatible = "cache"; compatible = "cache";
@@ -138,6 +142,7 @@ CPU4: cpu@400 {
&BIG_CPU_SLEEP_1 &BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>; &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_400>; next-level-cache = <&L2_400>;
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>; #cooling-cells = <2>;
L2_400: l2-cache { L2_400: l2-cache {
compatible = "cache"; compatible = "cache";
@@ -154,6 +159,7 @@ CPU5: cpu@500 {
&BIG_CPU_SLEEP_1 &BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>; &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_500>; next-level-cache = <&L2_500>;
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>; #cooling-cells = <2>;
L2_500: l2-cache { L2_500: l2-cache {
compatible = "cache"; compatible = "cache";
@@ -170,6 +176,7 @@ CPU6: cpu@600 {
&BIG_CPU_SLEEP_1 &BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>; &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_600>; next-level-cache = <&L2_600>;
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>; #cooling-cells = <2>;
L2_600: l2-cache { L2_600: l2-cache {
compatible = "cache"; compatible = "cache";
@@ -186,6 +193,7 @@ CPU7: cpu@700 {
&BIG_CPU_SLEEP_1 &BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>; &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_700>; next-level-cache = <&L2_700>;
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>; #cooling-cells = <2>;
L2_700: l2-cache { L2_700: l2-cache {
compatible = "cache"; compatible = "cache";
@@ -1147,6 +1155,16 @@ rpmhcc: clock-controller {
#clock-cells = <1>; #clock-cells = <1>;
}; };
}; };
cpufreq_hw: cpufreq@18591000 {
compatible = "qcom,cpufreq-epss";
reg = <0 0x18591000 0 0x1000>,
<0 0x18592000 0 0x1000>,
<0 0x18593000 0 0x1000>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
#freq-domain-cells = <1>;
};
}; };
thermal_zones: thermal-zones { thermal_zones: thermal-zones {