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iommu/amd: Add support for hw_info for iommu capability query

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AMD IOMMU Extended Feature (EFR) and Extended Feature 2 (EFR2) registers
specify features supported by each IOMMU hardware instance.
The IOMMU driver checks each feature-specific bits before enabling
each feature at run time.

For IOMMUFD, the hypervisor passes the raw value of amd_iommu_efr and
amd_iommu_efr2 to VMM via iommufd IOMMU_DEVICE_GET_HW_INFO ioctl.

Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-by: Vasant Hegde <vasant.hegde@amd.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
This commit is contained in:
Suravee Suthikulpanit
2026-01-15 06:08:02 +00:00
committed by Joerg Roedel
parent 2e66659565
commit 7d8b06ecc4
6 changed files with 87 additions and 0 deletions
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28
include/uapi/linux/iommufd.h
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@@ -623,6 +623,32 @@ struct iommu_hw_info_tegra241_cmdqv {
__u8 __reserved;
};
/**
* struct iommu_hw_info_amd - AMD IOMMU device info
*
* @efr : Value of AMD IOMMU Extended Feature Register (EFR)
* @efr2: Value of AMD IOMMU Extended Feature 2 Register (EFR2)
*
* Please See description of these registers in the following sections of
* the AMD I/O Virtualization Technology (IOMMU) Specification.
* (https://docs.amd.com/v/u/en-US/48882_3.10_PUB)
*
* - MMIO Offset 0030h IOMMU Extended Feature Register
* - MMIO Offset 01A0h IOMMU Extended Feature 2 Register
*
* Note: The EFR and EFR2 are raw values reported by hardware.
* VMM is responsible to determine the appropriate flags to be exposed to
* the VM since cetertain features are not currently supported by the kernel
* for HW-vIOMMU.
*
* Current VMM-allowed list of feature flags are:
* - EFR[GTSup, GASup, GioSup, PPRSup, EPHSup, GATS, GLX, PASmax]
*/
struct iommu_hw_info_amd {
__aligned_u64 efr;
__aligned_u64 efr2;
};
/**
* enum iommu_hw_info_type - IOMMU Hardware Info Types
* @IOMMU_HW_INFO_TYPE_NONE: Output by the drivers that do not report hardware
@@ -632,6 +658,7 @@ struct iommu_hw_info_tegra241_cmdqv {
* @IOMMU_HW_INFO_TYPE_ARM_SMMUV3: ARM SMMUv3 iommu info type
* @IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV: NVIDIA Tegra241 CMDQV (extension for ARM
* SMMUv3) info type
* @IOMMU_HW_INFO_TYPE_AMD: AMD IOMMU info type
*/
enum iommu_hw_info_type {
IOMMU_HW_INFO_TYPE_NONE = 0,
@@ -639,6 +666,7 @@ enum iommu_hw_info_type {
IOMMU_HW_INFO_TYPE_INTEL_VTD = 1,
IOMMU_HW_INFO_TYPE_ARM_SMMUV3 = 2,
IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV = 3,
IOMMU_HW_INFO_TYPE_AMD = 4,
};
/**