From c8da1d15b8a4957f105ad77bb1404d72e304566f Mon Sep 17 00:00:00 2001 From: Alan Tull Date: Wed, 8 Aug 2018 10:42:41 -0500 Subject: [PATCH 1/6] arm64: dts: stratix10: i2c clock running out of spec DesignWare I2C controller was observed running at 105.93kHz rather than the specified 100kHz. Adjust device tree settings to bring it within spec (a slightly conservative 98 MHz). Signed-off-by: Alan Tull Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index 6edc4fa9fd42..53cf195c2ada 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -124,6 +124,8 @@ &watchdog0 { &i2c1 { status = "okay"; clock-frequency = <100000>; + i2c-sda-falling-time-ns = <890>; /* hcnt */ + i2c-sdl-falling-time-ns = <890>; /* lcnt */ adc@14 { compatible = "lltc,ltc2497"; From f20193f7c79e1a8433954342f0e30cad0f17c192 Mon Sep 17 00:00:00 2001 From: Simon Goldschmidt Date: Wed, 8 Aug 2018 11:09:44 +0200 Subject: [PATCH 2/6] ARM: dts: socfpga: use stdout-path for chosen node Use stdout-path dts property for kernel console. There were two socfpga boards left not using stdout-path: socrates and vining. Make sure they match the other boards. Signed-off-by: Simon Goldschmidt Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_cyclone5_socrates.dts | 3 ++- arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts index 53bf99eef66d..6f5255a7d192 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts @@ -22,7 +22,8 @@ / { compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga"; chosen { - bootargs = "console=ttyS0,115200"; + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory@0 { diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts index f50b19447de6..e61efe16e79c 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts @@ -54,7 +54,8 @@ / { compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga"; chosen { - bootargs = "console=ttyS0,115200"; + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory@0 { From 9a8e3cfd3469a7c083c013963ca5282aec63b1e8 Mon Sep 17 00:00:00 2001 From: Silvan Murer Date: Thu, 2 Aug 2018 13:41:14 +0200 Subject: [PATCH 3/6] ARM: dts: socfpga: set timer interrupt to edge sensitive Change timer interrupt to edge sensitive. Signed-off-by: Silvan Murer Reviewed-by: Thor Thayer Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index a4dcb68f4322..cebbf0b2808e 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -760,7 +760,7 @@ sysmgr: sysmgr@ffd06000 { timer@ffffc600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xffffc600 0x100>; - interrupts = <1 13 0xf04>; + interrupts = <1 13 0xf01>; clocks = <&mpu_periph_clk>; }; From 12b2982a1f72ce453d76da977e1dad422b2f34ad Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 9 Jul 2018 13:47:20 -0500 Subject: [PATCH 4/6] ARM: dts: arria10: update NAND clocking The NAND IP needs 3 clocks(nand_x_clk, nand_clk, and nand_ecc_clk). This patch adds a nand_clk, which is derived from the nand_x_clk, but has a fixed divider of 4, and the nand_ecc_clk, which is derived from the nand_x_clk. Update the NAND node to use the additional clocks. Signed-off-by: Dinh Nguyen --- v2: add nand_ecc_clk and update commit message --- arch/arm/boot/dts/socfpga_arria10.dtsi | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index cebbf0b2808e..266c67878a15 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -377,13 +377,28 @@ qspi_clk: qspi_clk { clk-gate = <0xC8 11>; }; - nand_clk: nand_clk { + nand_x_clk: nand_x_clk { #clock-cells = <0>; compatible = "altr,socfpga-a10-gate-clk"; clocks = <&l4_mp_clk>; clk-gate = <0xC8 10>; }; + nand_ecc_clk: nand_ecc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&nand_x_clk>; + clk-gate = <0xC8 10>; + }; + + nand_clk: nand_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&nand_x_clk>; + fixed-divider = <4>; + clk-gate = <0xC8 10>; + }; + spi_m_clk: spi_m_clk { #clock-cells = <0>; compatible = "altr,socfpga-a10-gate-clk"; @@ -650,7 +665,8 @@ nand: nand@ffb90000 { reg-names = "nand_data", "denali_reg"; interrupts = <0 99 4>; dma-mask = <0xffffffff>; - clocks = <&nand_clk>; + clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; + clock-names = "nand", "nand_x", "ecc"; status = "disabled"; }; From 0ffc5df823dd3495441c47ea3ffaa09d4a57a5f1 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 9 Jul 2018 17:16:00 -0500 Subject: [PATCH 5/6] ARM: dts: socfpga: update NAND clocking for c5/a5 The NAND IP needs 3 clocks(nand_x_clk, nand_clk, and nand_ecc_clk). The nand_x_clk and nand_ecc_clk are derived from the nand_clk. The nand_x_clk has a fixed divider of 4. Also, update the NAND dts property with the correct clocks property. Signed-off-by: Dinh Nguyen --- v2: add nand_ecc_clk and update commit message --- arch/arm/boot/dts/socfpga.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index b38f8c240558..daf249e57b08 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -483,10 +483,17 @@ nand_x_clk: nand_x_clk { clk-gate = <0xa0 9>; }; + nand_ecc_clk: nand_ecc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&nand_x_clk>; + clk-gate = <0xa0 9>; + }; + nand_clk: nand_clk { #clock-cells = <0>; compatible = "altr,socfpga-gate-clk"; - clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clocks = <&nand_x_clk>; clk-gate = <0xa0 10>; fixed-divider = <4>; }; @@ -754,7 +761,8 @@ nand0: nand@ff900000 { reg-names = "nand_data", "denali_reg"; interrupts = <0x0 0x90 0x4>; dma-mask = <0xffffffff>; - clocks = <&nand_x_clk>; + clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; + clock-names = "nand", "nand_x", "ecc"; status = "disabled"; }; From 202eb5481421040e115526b75317b5ca72584806 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 29 Aug 2018 17:15:04 +0200 Subject: [PATCH 6/6] ARM: dts: socfpga: Rename socfpga_cyclone5_de0_{sockit,nano_soc} Rename DT source for DE0 Nano SoC . The board name is really DE0-Nano-SoC or Atlas SoC, and it is not to be confused with SoCkit board, which is a different one. Rename the DT source file to match the board name and to avoid this possible mixup with another different board. Signed-off-by: Marek Vasut Cc: Dinh Nguyen Cc: Jan Kiszka Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/Makefile | 2 +- ...yclone5_de0_sockit.dts => socfpga_cyclone5_de0_nano_soc.dts} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename arch/arm/boot/dts/{socfpga_cyclone5_de0_sockit.dts => socfpga_cyclone5_de0_nano_soc.dts} (100%) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b5bd3de87c33..1036d396da83 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -892,7 +892,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria10_socdk_sdmmc.dtb \ socfpga_cyclone5_mcvevk.dtb \ socfpga_cyclone5_socdk.dtb \ - socfpga_cyclone5_de0_sockit.dtb \ + socfpga_cyclone5_de0_nano_soc.dtb \ socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb \ socfpga_cyclone5_sodia.dtb \ diff --git a/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts similarity index 100% rename from arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts rename to arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts