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drm/i915/cmtg: Add CMTG transcoder offset in struct _device_info

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As all cmtg registers offset from base cmtg register is similar to
normal transcoder register, so follow existing way of defining
transcoder register for cmtg as well. Add base CMTG offset in
struct _display_device_info which will be used to derive the actual
register address for platform supporting CMTG.

Bspec: 68989
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patch.msgid.link/20260615200339.885190-4-animesh.manna@intel.com
This commit is contained in:
Animesh Manna
2026-06-16 01:33:20 +05:30
parent b5cbe1aefe
commit 789dda6429
3 changed files with 17 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
drivers/gpu/drm/i915/display/intel_display_device.c
View File

@@ -101,6 +101,8 @@ static const struct intel_display_device_info no_display = {};
#define TRANSCODER_EDP_OFFSET 0x6f000
#define TRANSCODER_DSI0_OFFSET 0x6b000
#define TRANSCODER_DSI1_OFFSET 0x6b800
#define TRANSCODER_CMTG0_OFFSET 0x6F000
#define TRANSCODER_CMTG1_OFFSET 0x6F100
#define CURSOR_A_OFFSET 0x70080
#define CURSOR_B_OFFSET 0x700c0
@@ -1352,6 +1354,18 @@ static const struct intel_display_device_info xe2_lpd_display = {
BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) |
BIT(INTEL_FBC_C) | BIT(INTEL_FBC_D),
.__runtime_defaults.has_dbuf_overlap_detection = true,
.trans_offsets = {
[TRANSCODER_A] = TRANSCODER_A_OFFSET,
[TRANSCODER_B] = TRANSCODER_B_OFFSET,
[TRANSCODER_C] = TRANSCODER_C_OFFSET,
[TRANSCODER_D] = TRANSCODER_D_OFFSET,
[TRANSCODER_CMTG0] = TRANSCODER_CMTG0_OFFSET,
[TRANSCODER_CMTG1] = TRANSCODER_CMTG1_OFFSET,
},
.__runtime_defaults.cpu_transcoder_mask =
BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
BIT(TRANSCODER_CMTG0) | BIT(TRANSCODER_CMTG1),
};
static const struct intel_display_device_info wcl_display = {

2
drivers/gpu/drm/i915/display/intel_display_device.h
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@@ -292,7 +292,7 @@ struct intel_display_runtime_info {
u32 rawclk_freq;
u8 pipe_mask;
u8 cpu_transcoder_mask;
u16 cpu_transcoder_mask;
u16 port_mask;
u8 num_sprites[I915_MAX_PIPES];

2
drivers/gpu/drm/i915/display/intel_display_limits.h
View File

@@ -45,6 +45,8 @@ enum transcoder {
TRANSCODER_DSI_1,
TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */
TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */
TRANSCODER_CMTG0,
TRANSCODER_CMTG1,
I915_MAX_TRANSCODERS
};