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arm64: dts: qcom: sm8650: Flatten the USB nodes

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Transition the USB controllers found in the SM8650 SoC to the newly
introduced, flattened representation of the Qualcomm USB block.

The reg and interrupts properties from the usb child node are merged
with their counterpart in the outer node, remaining properties and child
nodes are simply moved.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250811-topic-sm8x50-usb-flatten-v2-2-0bbb3ac292e4@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Neil Armstrong
2025-08-11 14:25:18 +02:00
committed by Bjorn Andersson
parent 33450878ad
commit 77e1f16b93
4 changed files with 47 additions and 59 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm64/boot/dts/qcom/sm8650-hdk.dts
View File

@@ -1310,12 +1310,10 @@ &ufs_mem_phy {
*/
&usb_1 {
status = "okay";
};
&usb_1_dwc3 {
dr_mode = "otg";
usb-role-switch;
status = "okay";
};
&usb_1_dwc3_hs {

6
arch/arm64/boot/dts/qcom/sm8650-mtp.dts
View File

@@ -857,12 +857,10 @@ &ufs_mem_phy {
*/
&usb_1 {
status = "okay";
};
&usb_1_dwc3 {
dr_mode = "otg";
usb-role-switch;
status = "okay";
};
&usb_1_dwc3_hs {

6
arch/arm64/boot/dts/qcom/sm8650-qrd.dts
View File

@@ -1293,12 +1293,10 @@ &ufs_mem_phy {
*/
&usb_1 {
status = "okay";
};
&usb_1_dwc3 {
dr_mode = "otg";
usb-role-switch;
status = "okay";
};
&usb_1_dwc3_hs {

88
arch/arm64/boot/dts/qcom/sm8650.dtsi
View File

@@ -5651,16 +5651,18 @@ usb_dp_qmpphy_dp_in: endpoint {
};
};
usb_1: usb@a6f8800 {
compatible = "qcom,sm8650-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>;
usb_1: usb@a600000 {
compatible = "qcom,sm8650-dwc3", "qcom,snps-dwc3";
reg = <0 0x0a600000 0 0xfc100>;
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>,
interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>,
<&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>,
<&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>,
<&pdc 14 IRQ_TYPE_EDGE_RISING>,
<&pdc 15 IRQ_TYPE_EDGE_RISING>,
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
interrupt-names = "dwc_usb3",
"pwr_event",
"hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
@@ -5685,6 +5687,11 @@ usb_1: usb@a6f8800 {
resets = <&gcc GCC_USB30_PRIM_BCR>;
phys = <&usb_1_hsphy>,
<&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy",
"usb3-phy";
interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
@@ -5692,59 +5699,46 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
interconnect-names = "usb-ddr",
"apps-usb";
iommus = <&apps_smmu 0x40 0>;
power-domains = <&gcc USB30_PRIM_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,usb2-gadget-lpm-disable;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
snps,is-utmi-l1-suspend;
snps,usb3_lpm_capable;
snps,usb2-lpm-disable;
snps,has-lpm-erratum;
tx-fifo-resize;
dma-coherent;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
usb_1_dwc3: usb@a600000 {
compatible = "snps,dwc3";
reg = <0 0x0a600000 0 0xcd00>;
ports {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>;
port@0 {
reg = <0>;
iommus = <&apps_smmu 0x40 0>;
phys = <&usb_1_hsphy>,
<&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy",
"usb3-phy";
snps,hird-threshold = /bits/ 8 <0x0>;
snps,usb2-gadget-lpm-disable;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
snps,is-utmi-l1-suspend;
snps,usb3_lpm_capable;
snps,usb2-lpm-disable;
snps,has-lpm-erratum;
tx-fifo-resize;
dma-coherent;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_1_dwc3_hs: endpoint {
};
usb_1_dwc3_hs: endpoint {
};
};
port@1 {
reg = <1>;
port@1 {
reg = <1>;
usb_1_dwc3_ss: endpoint {
remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
};
usb_1_dwc3_ss: endpoint {
remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
};
};
};