From 7745c857ddc866acfd141ce44f2d8d3f6535047b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Tue, 12 May 2026 00:41:14 +0300 Subject: [PATCH] drm/xe: Do the initial FB size alignment earlier MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For some reason we've split the alignment of 'base' vs. 'size' to live on separate sides of the xe initial plane PTE readout. There's no reason for this split, so make things less confusing by aligning both at the same time. Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20260511214122.8468-7-ville.syrjala@linux.intel.com Signed-off-by: Maarten Lankhorst Acked-by: Matthew Brost #teams --- drivers/gpu/drm/xe/display/xe_initial_plane.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/xe/display/xe_initial_plane.c b/drivers/gpu/drm/xe/display/xe_initial_plane.c index da04ee66252a..feb979cca12a 100644 --- a/drivers/gpu/drm/xe/display/xe_initial_plane.c +++ b/drivers/gpu/drm/xe/display/xe_initial_plane.c @@ -37,6 +37,10 @@ initial_plane_bo(struct xe_device *xe, flags = XE_BO_FLAG_FORCE_WC | XE_BO_FLAG_GGTT; base = round_down(plane_config->base, page_size); + size = round_up(plane_config->base + plane_config->size, + page_size); + size -= base; + if (IS_DGFX(xe)) { u64 pte = xe_ggtt_read_pte(tile0->mem.ggtt, base); @@ -79,10 +83,6 @@ initial_plane_bo(struct xe_device *xe, } } - size = round_up(plane_config->base + plane_config->size, - page_size); - size -= base; - bo = xe_bo_create_pin_map_at_novm(xe, tile0, size, phys_base, ttm_bo_type_kernel, flags, 0, false); if (IS_ERR(bo)) {