From 9a181e1093af59f53eaa33bcd2281a0a2158a7be Mon Sep 17 00:00:00 2001 From: Bharat Kumar Gogada Date: Fri, 14 Apr 2017 20:34:32 +0530 Subject: [PATCH 1/2] PCI: xilinx-nwl: Modify IRQ chip for legacy interrupts - Add spinlock for protecting legacy mask register - Few wifi end points which only support legacy interrupts, performs hardware reset functionalities after disabling interrupts by invoking disable_irq() and then re-enable using enable_irq(), they enable hardware interrupts first and then virtual IRQ line later. - The legacy IRQ line goes low only after DEASSERT_INTx is received. As the legacy IRQ line is high immediately after hardware interrupts are enabled but virq of EP is still in disabled state and EP handler is never executed resulting no DEASSERT_INTx. If dummy IRQ chip is used, interrupts are not masked and system hangs with CPU stall. - Add IRQ chip functions instead of dummy IRQ chip for legacy interrupts. - Legacy interrupts are level sensitive, so using handle_level_irq() is more appropriate as it is masks interrupts until Endpoint handles interrupts and unmasks interrupts after Endpoint handler is executed. - Legacy interrupts are level triggered, virtual IRQ line of EndPoint shows as edge in /proc/interrupts. - Set IRQ flags of virtual IRQ line of EP to level triggered at the time of mapping. Signed-off-by: Bharat Kumar Gogada Signed-off-by: Bjorn Helgaas --- drivers/pci/host/pcie-xilinx-nwl.c | 45 +++++++++++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/host/pcie-xilinx-nwl.c index d1f7e4ca5a5a..eec641a34fc5 100644 --- a/drivers/pci/host/pcie-xilinx-nwl.c +++ b/drivers/pci/host/pcie-xilinx-nwl.c @@ -172,6 +172,7 @@ struct nwl_pcie { u8 root_busno; struct nwl_msi msi; struct irq_domain *legacy_irq_domain; + raw_spinlock_t leg_mask_lock; }; static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off) @@ -383,11 +384,52 @@ static void nwl_pcie_msi_handler_low(struct irq_desc *desc) chained_irq_exit(chip, desc); } +static void nwl_mask_leg_irq(struct irq_data *data) +{ + struct irq_desc *desc = irq_to_desc(data->irq); + struct nwl_pcie *pcie; + unsigned long flags; + u32 mask; + u32 val; + + pcie = irq_desc_get_chip_data(desc); + mask = 1 << (data->hwirq - 1); + raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); + val = nwl_bridge_readl(pcie, MSGF_LEG_MASK); + nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK); + raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); +} + +static void nwl_unmask_leg_irq(struct irq_data *data) +{ + struct irq_desc *desc = irq_to_desc(data->irq); + struct nwl_pcie *pcie; + unsigned long flags; + u32 mask; + u32 val; + + pcie = irq_desc_get_chip_data(desc); + mask = 1 << (data->hwirq - 1); + raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); + val = nwl_bridge_readl(pcie, MSGF_LEG_MASK); + nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK); + raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); +} + +static struct irq_chip nwl_leg_irq_chip = { + .name = "nwl_pcie:legacy", + .irq_enable = nwl_unmask_leg_irq, + .irq_disable = nwl_mask_leg_irq, + .irq_mask = nwl_mask_leg_irq, + .irq_unmask = nwl_unmask_leg_irq, +}; + static int nwl_legacy_map(struct irq_domain *domain, unsigned int irq, irq_hw_number_t hwirq) { - irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); + irq_set_chip_and_handler(irq, &nwl_leg_irq_chip, handle_level_irq); irq_set_chip_data(irq, domain->host_data); + irq_set_status_flags(irq, IRQ_LEVEL); return 0; } @@ -526,6 +568,7 @@ static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie) return -ENOMEM; } + raw_spin_lock_init(&pcie->leg_mask_lock); nwl_pcie_init_msi_irq_domain(pcie); return 0; } From fdc71ce97c13f64ffd0e2c74b6c50da64e1642f8 Mon Sep 17 00:00:00 2001 From: Arvind Yadav Date: Tue, 20 Jun 2017 11:17:48 +0530 Subject: [PATCH 2/2] PCI: xilinx: Make of_device_ids const of_device_ids are not supposed to change at runtime. All functions working with of_device_ids provided by work with const of_device_ids. So mark the non-const structs as const. File size before: text data bss dec hex filename 195 600 0 795 31b drivers/pci/host/pcie-xilinx.o File size after constify xilinx_pcie_of_match: text data bss dec hex filename 595 184 0 779 30b drivers/pci/host/pcie-xilinx.o Signed-off-by: Arvind Yadav Signed-off-by: Bjorn Helgaas --- drivers/pci/host/pcie-xilinx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c index d09b00579bde..f63fa5e0278c 100644 --- a/drivers/pci/host/pcie-xilinx.c +++ b/drivers/pci/host/pcie-xilinx.c @@ -704,7 +704,7 @@ static int xilinx_pcie_probe(struct platform_device *pdev) return err; } -static struct of_device_id xilinx_pcie_of_match[] = { +static const struct of_device_id xilinx_pcie_of_match[] = { { .compatible = "xlnx,axi-pcie-host-1.00.a", }, {} };