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Merge tag 'v6.0-rc6' into locking/core, to refresh the branch

Browse Source 
Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Ingo Molnar
2022-09-21 09:58:02 +02:00
parent 0d97db0265 521a547ced
commit 74656d03ac
13386 changed files with 1361646 additions and 268321 deletions
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12
include/acpi/acpi_bus.h
View File

@@ -344,8 +344,9 @@ struct acpi_device_physical_node {
struct acpi_device_properties {
const guid_t *guid;
const union acpi_object *properties;
union acpi_object *properties;
struct list_head list;
void **bufs;
};
/* ACPI Device Specific Data (_DSD) */
@@ -365,8 +366,6 @@ struct acpi_device {
acpi_handle handle; /* no handle for fixed hardware */
struct fwnode_handle fwnode;
struct acpi_device *parent;
struct list_head children;
struct list_head node;
struct list_head wakeup_list;
struct list_head del_list;
struct acpi_device_status status;
@@ -379,7 +378,6 @@ struct acpi_device {
struct acpi_device_data data;
struct acpi_scan_handler *handler;
struct acpi_hotplug_context *hp;
struct acpi_driver *driver;
const struct acpi_gpio_mapping *driver_gpios;
void *driver_data;
struct device dev;
@@ -483,6 +481,9 @@ extern struct bus_type acpi_bus_type;
int acpi_bus_for_each_dev(int (*fn)(struct device *, void *), void *data);
int acpi_dev_for_each_child(struct acpi_device *adev,
int (*fn)(struct acpi_device *, void *), void *data);
int acpi_dev_for_each_child_reverse(struct acpi_device *adev,
int (*fn)(struct acpi_device *, void *),
void *data);
/*
* Events
@@ -521,6 +522,7 @@ const char *acpi_power_state_string(int state);
int acpi_device_set_power(struct acpi_device *device, int state);
int acpi_bus_init_power(struct acpi_device *device);
int acpi_device_fix_up_power(struct acpi_device *device);
void acpi_device_fix_up_power_extended(struct acpi_device *adev);
int acpi_bus_update_power(acpi_handle handle, int *state_p);
int acpi_device_update_power(struct acpi_device *device, int *state_p);
bool acpi_bus_power_manageable(acpi_handle handle);
@@ -622,6 +624,8 @@ static inline int acpi_dma_configure(struct device *dev,
}
struct acpi_device *acpi_find_child_device(struct acpi_device *parent,
u64 address, bool check_children);
struct acpi_device *acpi_find_child_by_adr(struct acpi_device *adev,
acpi_bus_address adr);
int acpi_is_root_bridge(acpi_handle);
struct acpi_pci_root *acpi_pci_find_root(acpi_handle handle);

2
include/acpi/cppc_acpi.h
View File

@@ -17,7 +17,7 @@
#include <acpi/pcc.h>
#include <acpi/processor.h>
/* Support CPPCv2 and CPPCv3 */
/* CPPCv2 and CPPCv3 support */
#define CPPC_V2_REV 2
#define CPPC_V3_REV 3
#define CPPC_V2_NUM_ENT 21

9
include/acpi/processor.h
View File

@@ -441,9 +441,12 @@ static inline int acpi_processor_hotplug(struct acpi_processor *pr)
#endif /* CONFIG_ACPI_PROCESSOR_IDLE */
/* in processor_thermal.c */
int acpi_processor_get_limit_info(struct acpi_processor *pr);
int acpi_processor_thermal_init(struct acpi_processor *pr,
struct acpi_device *device);
void acpi_processor_thermal_exit(struct acpi_processor *pr,
struct acpi_device *device);
extern const struct thermal_cooling_device_ops processor_cooling_ops;
#if defined(CONFIG_ACPI_CPU_FREQ_PSS) & defined(CONFIG_CPU_FREQ)
#ifdef CONFIG_CPU_FREQ
void acpi_thermal_cpufreq_init(struct cpufreq_policy *policy);
void acpi_thermal_cpufreq_exit(struct cpufreq_policy *policy);
#else
@@ -455,6 +458,6 @@ static inline void acpi_thermal_cpufreq_exit(struct cpufreq_policy *policy)
{
return;
}
#endif /* CONFIG_ACPI_CPU_FREQ_PSS */
#endif /* CONFIG_CPU_FREQ */
#endif

2
include/asm-generic/Kbuild
View File

@@ -5,6 +5,7 @@
# asm headers from the host architecutre.)
mandatory-y += atomic.h
mandatory-y += archrandom.h
mandatory-y += barrier.h
mandatory-y += bitops.h
mandatory-y += bug.h
@@ -44,7 +45,6 @@ mandatory-y += msi.h
mandatory-y += pci.h
mandatory-y += percpu.h
mandatory-y += pgalloc.h
mandatory-y += platform-feature.h
mandatory-y += preempt.h
mandatory-y += rwonce.h
mandatory-y += sections.h

15
include/asm-generic/archrandom.h Normal file
View File

@@ -0,0 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_GENERIC_ARCHRANDOM_H__
#define __ASM_GENERIC_ARCHRANDOM_H__
static inline size_t __must_check arch_get_random_longs(unsigned long *v, size_t max_longs)
{
return 0;
}
static inline size_t __must_check arch_get_random_seed_longs(unsigned long *v, size_t max_longs)
{
return 0;
}
#endif

6
include/asm-generic/bitops/atomic.h
View File

@@ -39,9 +39,6 @@ arch_test_and_set_bit(unsigned int nr, volatile unsigned long *p)
unsigned long mask = BIT_MASK(nr);
p += BIT_WORD(nr);
if (READ_ONCE(*p) & mask)
return 1;
old = arch_atomic_long_fetch_or(mask, (atomic_long_t *)p);
return !!(old & mask);
}
@@ -53,9 +50,6 @@ arch_test_and_clear_bit(unsigned int nr, volatile unsigned long *p)
unsigned long mask = BIT_MASK(nr);
p += BIT_WORD(nr);
if (!(READ_ONCE(*p) & mask))
return 0;
old = arch_atomic_long_fetch_andnot(mask, (atomic_long_t *)p);
return !!(old & mask);
}

175
include/asm-generic/bitops/generic-non-atomic.h Normal file
View File

@@ -0,0 +1,175 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __ASM_GENERIC_BITOPS_GENERIC_NON_ATOMIC_H
#define __ASM_GENERIC_BITOPS_GENERIC_NON_ATOMIC_H
#include <linux/bits.h>
#include <asm/barrier.h>
#ifndef _LINUX_BITOPS_H
#error only <linux/bitops.h> can be included directly
#endif
/*
* Generic definitions for bit operations, should not be used in regular code
* directly.
*/
/**
* generic___set_bit - Set a bit in memory
* @nr: the bit to set
* @addr: the address to start counting from
*
* Unlike set_bit(), this function is non-atomic and may be reordered.
* If it's called on the same region of memory simultaneously, the effect
* may be that only one operation succeeds.
*/
static __always_inline void
generic___set_bit(unsigned long nr, volatile unsigned long *addr)
{
unsigned long mask = BIT_MASK(nr);
unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
*p |= mask;
}
static __always_inline void
generic___clear_bit(unsigned long nr, volatile unsigned long *addr)
{
unsigned long mask = BIT_MASK(nr);
unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
*p &= ~mask;
}
/**
* generic___change_bit - Toggle a bit in memory
* @nr: the bit to change
* @addr: the address to start counting from
*
* Unlike change_bit(), this function is non-atomic and may be reordered.
* If it's called on the same region of memory simultaneously, the effect
* may be that only one operation succeeds.
*/
static __always_inline void
generic___change_bit(unsigned long nr, volatile unsigned long *addr)
{
unsigned long mask = BIT_MASK(nr);
unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
*p ^= mask;
}
/**
* generic___test_and_set_bit - Set a bit and return its old value
* @nr: Bit to set
* @addr: Address to count from
*
* This operation is non-atomic and can be reordered.
* If two examples of this operation race, one can appear to succeed
* but actually fail. You must protect multiple accesses with a lock.
*/
static __always_inline bool
generic___test_and_set_bit(unsigned long nr, volatile unsigned long *addr)
{
unsigned long mask = BIT_MASK(nr);
unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
unsigned long old = *p;
*p = old | mask;
return (old & mask) != 0;
}
/**
* generic___test_and_clear_bit - Clear a bit and return its old value
* @nr: Bit to clear
* @addr: Address to count from
*
* This operation is non-atomic and can be reordered.
* If two examples of this operation race, one can appear to succeed
* but actually fail. You must protect multiple accesses with a lock.
*/
static __always_inline bool
generic___test_and_clear_bit(unsigned long nr, volatile unsigned long *addr)
{
unsigned long mask = BIT_MASK(nr);
unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
unsigned long old = *p;
*p = old & ~mask;
return (old & mask) != 0;
}
/* WARNING: non atomic and it can be reordered! */
static __always_inline bool
generic___test_and_change_bit(unsigned long nr, volatile unsigned long *addr)
{
unsigned long mask = BIT_MASK(nr);
unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
unsigned long old = *p;
*p = old ^ mask;
return (old & mask) != 0;
}
/**
* generic_test_bit - Determine whether a bit is set
* @nr: bit number to test
* @addr: Address to start counting from
*/
static __always_inline bool
generic_test_bit(unsigned long nr, const volatile unsigned long *addr)
{
/*
* Unlike the bitops with the '__' prefix above, this one *is* atomic,
* so `volatile` must always stay here with no cast-aways. See
* `Documentation/atomic_bitops.txt` for the details.
*/
return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1)));
}
/**
* generic_test_bit_acquire - Determine, with acquire semantics, whether a bit is set
* @nr: bit number to test
* @addr: Address to start counting from
*/
static __always_inline bool
generic_test_bit_acquire(unsigned long nr, const volatile unsigned long *addr)
{
unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
return 1UL & (smp_load_acquire(p) >> (nr & (BITS_PER_LONG-1)));
}
/*
* const_*() definitions provide good compile-time optimizations when
* the passed arguments can be resolved at compile time.
*/
#define const___set_bit generic___set_bit
#define const___clear_bit generic___clear_bit
#define const___change_bit generic___change_bit
#define const___test_and_set_bit generic___test_and_set_bit
#define const___test_and_clear_bit generic___test_and_clear_bit
#define const___test_and_change_bit generic___test_and_change_bit
#define const_test_bit_acquire generic_test_bit_acquire
/**
* const_test_bit - Determine whether a bit is set
* @nr: bit number to test
* @addr: Address to start counting from
*
* A version of generic_test_bit() which discards the `volatile` qualifier to
* allow a compiler to optimize code harder. Non-atomic and to be called only
* for testing compile-time constants, e.g. by the corresponding macros, not
* directly from "regular" code.
*/
static __always_inline bool
const_test_bit(unsigned long nr, const volatile unsigned long *addr)
{
const unsigned long *p = (const unsigned long *)addr + BIT_WORD(nr);
unsigned long mask = BIT_MASK(nr);
unsigned long val = *p;
return !!(val & mask);
}
#endif /* __ASM_GENERIC_BITOPS_GENERIC_NON_ATOMIC_H */

47
include/asm-generic/bitops/instrumented-non-atomic.h
View File

@@ -14,7 +14,7 @@
#include <linux/instrumented.h>
/**
* __set_bit - Set a bit in memory
* ___set_bit - Set a bit in memory
* @nr: the bit to set
* @addr: the address to start counting from
*
@@ -22,14 +22,15 @@
* region of memory concurrently, the effect may be that only one operation
* succeeds.
*/
static __always_inline void __set_bit(long nr, volatile unsigned long *addr)
static __always_inline void
___set_bit(unsigned long nr, volatile unsigned long *addr)
{
instrument_write(addr + BIT_WORD(nr), sizeof(long));
arch___set_bit(nr, addr);
}
/**
* __clear_bit - Clears a bit in memory
* ___clear_bit - Clears a bit in memory
* @nr: the bit to clear
* @addr: the address to start counting from
*
@@ -37,14 +38,15 @@ static __always_inline void __set_bit(long nr, volatile unsigned long *addr)
* region of memory concurrently, the effect may be that only one operation
* succeeds.
*/
static __always_inline void __clear_bit(long nr, volatile unsigned long *addr)
static __always_inline void
___clear_bit(unsigned long nr, volatile unsigned long *addr)
{
instrument_write(addr + BIT_WORD(nr), sizeof(long));
arch___clear_bit(nr, addr);
}
/**
* __change_bit - Toggle a bit in memory
* ___change_bit - Toggle a bit in memory
* @nr: the bit to change
* @addr: the address to start counting from
*
@@ -52,7 +54,8 @@ static __always_inline void __clear_bit(long nr, volatile unsigned long *addr)
* region of memory concurrently, the effect may be that only one operation
* succeeds.
*/
static __always_inline void __change_bit(long nr, volatile unsigned long *addr)
static __always_inline void
___change_bit(unsigned long nr, volatile unsigned long *addr)
{
instrument_write(addr + BIT_WORD(nr), sizeof(long));
arch___change_bit(nr, addr);
@@ -83,56 +86,72 @@ static __always_inline void __instrument_read_write_bitop(long nr, volatile unsi
}
/**
* __test_and_set_bit - Set a bit and return its old value
* ___test_and_set_bit - Set a bit and return its old value
* @nr: Bit to set
* @addr: Address to count from
*
* This operation is non-atomic. If two instances of this operation race, one
* can appear to succeed but actually fail.
*/
static __always_inline bool __test_and_set_bit(long nr, volatile unsigned long *addr)
static __always_inline bool
___test_and_set_bit(unsigned long nr, volatile unsigned long *addr)
{
__instrument_read_write_bitop(nr, addr);
return arch___test_and_set_bit(nr, addr);
}
/**
* __test_and_clear_bit - Clear a bit and return its old value
* ___test_and_clear_bit - Clear a bit and return its old value
* @nr: Bit to clear
* @addr: Address to count from
*
* This operation is non-atomic. If two instances of this operation race, one
* can appear to succeed but actually fail.
*/
static __always_inline bool __test_and_clear_bit(long nr, volatile unsigned long *addr)
static __always_inline bool
___test_and_clear_bit(unsigned long nr, volatile unsigned long *addr)
{
__instrument_read_write_bitop(nr, addr);
return arch___test_and_clear_bit(nr, addr);
}
/**
* __test_and_change_bit - Change a bit and return its old value
* ___test_and_change_bit - Change a bit and return its old value
* @nr: Bit to change
* @addr: Address to count from
*
* This operation is non-atomic. If two instances of this operation race, one
* can appear to succeed but actually fail.
*/
static __always_inline bool __test_and_change_bit(long nr, volatile unsigned long *addr)
static __always_inline bool
___test_and_change_bit(unsigned long nr, volatile unsigned long *addr)
{
__instrument_read_write_bitop(nr, addr);
return arch___test_and_change_bit(nr, addr);
}
/**
* test_bit - Determine whether a bit is set
* _test_bit - Determine whether a bit is set
* @nr: bit number to test
* @addr: Address to start counting from
*/
static __always_inline bool test_bit(long nr, const volatile unsigned long *addr)
static __always_inline bool
_test_bit(unsigned long nr, const volatile unsigned long *addr)
{
instrument_atomic_read(addr + BIT_WORD(nr), sizeof(long));
return arch_test_bit(nr, addr);
}
/**
* _test_bit_acquire - Determine, with acquire semantics, whether a bit is set
* @nr: bit number to test
* @addr: Address to start counting from
*/
static __always_inline bool
_test_bit_acquire(unsigned long nr, const volatile unsigned long *addr)
{
instrument_atomic_read(addr + BIT_WORD(nr), sizeof(long));
return arch_test_bit_acquire(nr, addr);
}
#endif /* _ASM_GENERIC_BITOPS_INSTRUMENTED_NON_ATOMIC_H */

122
include/asm-generic/bitops/non-atomic.h
View File

@@ -2,121 +2,19 @@
#ifndef _ASM_GENERIC_BITOPS_NON_ATOMIC_H_
#define _ASM_GENERIC_BITOPS_NON_ATOMIC_H_
#include <asm/types.h>
#include <asm-generic/bitops/generic-non-atomic.h>
/**
* arch___set_bit - Set a bit in memory
* @nr: the bit to set
* @addr: the address to start counting from
*
* Unlike set_bit(), this function is non-atomic and may be reordered.
* If it's called on the same region of memory simultaneously, the effect
* may be that only one operation succeeds.
*/
static __always_inline void
arch___set_bit(unsigned int nr, volatile unsigned long *addr)
{
unsigned long mask = BIT_MASK(nr);
unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
#define arch___set_bit generic___set_bit
#define arch___clear_bit generic___clear_bit
#define arch___change_bit generic___change_bit
*p |= mask;
}
#define __set_bit arch___set_bit
#define arch___test_and_set_bit generic___test_and_set_bit
#define arch___test_and_clear_bit generic___test_and_clear_bit
#define arch___test_and_change_bit generic___test_and_change_bit
static __always_inline void
arch___clear_bit(unsigned int nr, volatile unsigned long *addr)
{
unsigned long mask = BIT_MASK(nr);
unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
#define arch_test_bit generic_test_bit
#define arch_test_bit_acquire generic_test_bit_acquire
*p &= ~mask;
}
#define __clear_bit arch___clear_bit
/**
* arch___change_bit - Toggle a bit in memory
* @nr: the bit to change
* @addr: the address to start counting from
*
* Unlike change_bit(), this function is non-atomic and may be reordered.
* If it's called on the same region of memory simultaneously, the effect
* may be that only one operation succeeds.
*/
static __always_inline
void arch___change_bit(unsigned int nr, volatile unsigned long *addr)
{
unsigned long mask = BIT_MASK(nr);
unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
*p ^= mask;
}
#define __change_bit arch___change_bit
/**
* arch___test_and_set_bit - Set a bit and return its old value
* @nr: Bit to set
* @addr: Address to count from
*
* This operation is non-atomic and can be reordered.
* If two examples of this operation race, one can appear to succeed
* but actually fail. You must protect multiple accesses with a lock.
*/
static __always_inline int
arch___test_and_set_bit(unsigned int nr, volatile unsigned long *addr)
{
unsigned long mask = BIT_MASK(nr);
unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
unsigned long old = *p;
*p = old | mask;
return (old & mask) != 0;
}
#define __test_and_set_bit arch___test_and_set_bit
/**
* arch___test_and_clear_bit - Clear a bit and return its old value
* @nr: Bit to clear
* @addr: Address to count from
*
* This operation is non-atomic and can be reordered.
* If two examples of this operation race, one can appear to succeed
* but actually fail. You must protect multiple accesses with a lock.
*/
static __always_inline int
arch___test_and_clear_bit(unsigned int nr, volatile unsigned long *addr)
{
unsigned long mask = BIT_MASK(nr);
unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
unsigned long old = *p;
*p = old & ~mask;
return (old & mask) != 0;
}
#define __test_and_clear_bit arch___test_and_clear_bit
/* WARNING: non atomic and it can be reordered! */
static __always_inline int
arch___test_and_change_bit(unsigned int nr, volatile unsigned long *addr)
{
unsigned long mask = BIT_MASK(nr);
unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
unsigned long old = *p;
*p = old ^ mask;
return (old & mask) != 0;
}
#define __test_and_change_bit arch___test_and_change_bit
/**
* arch_test_bit - Determine whether a bit is set
* @nr: bit number to test
* @addr: Address to start counting from
*/
static __always_inline int
arch_test_bit(unsigned int nr, const volatile unsigned long *addr)
{
return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1)));
}
#define test_bit arch_test_bit
#include <asm-generic/bitops/non-instrumented-non-atomic.h>
#endif /* _ASM_GENERIC_BITOPS_NON_ATOMIC_H_ */

17
include/asm-generic/bitops/non-instrumented-non-atomic.h Normal file
View File

@@ -0,0 +1,17 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_GENERIC_BITOPS_NON_INSTRUMENTED_NON_ATOMIC_H
#define __ASM_GENERIC_BITOPS_NON_INSTRUMENTED_NON_ATOMIC_H
#define ___set_bit arch___set_bit
#define ___clear_bit arch___clear_bit
#define ___change_bit arch___change_bit
#define ___test_and_set_bit arch___test_and_set_bit
#define ___test_and_clear_bit arch___test_and_clear_bit
#define ___test_and_change_bit arch___test_and_change_bit
#define _test_bit arch_test_bit
#define _test_bit_acquire arch_test_bit_acquire
#endif /* __ASM_GENERIC_BITOPS_NON_INSTRUMENTED_NON_ATOMIC_H */

105
include/asm-generic/io.h
View File

@@ -10,6 +10,7 @@
#include <asm/page.h> /* I/O is all done through memory accesses */
#include <linux/string.h> /* for memset() and memcpy() */
#include <linux/types.h>
#include <linux/instruction_pointer.h>
#ifdef CONFIG_GENERIC_IOMAP
#include <asm-generic/iomap.h>
@@ -61,6 +62,44 @@
#define __io_par(v) __io_ar(v)
#endif
/*
* "__DISABLE_TRACE_MMIO__" flag can be used to disable MMIO tracing for
* specific kernel drivers in case of excessive/unwanted logging.
*
* Usage: Add a #define flag at the beginning of the driver file.
* Ex: #define __DISABLE_TRACE_MMIO__
* #include <...>
* ...
*/
#if IS_ENABLED(CONFIG_TRACE_MMIO_ACCESS) && !(defined(__DISABLE_TRACE_MMIO__))
#include <linux/tracepoint-defs.h>
DECLARE_TRACEPOINT(rwmmio_write);
DECLARE_TRACEPOINT(rwmmio_post_write);
DECLARE_TRACEPOINT(rwmmio_read);
DECLARE_TRACEPOINT(rwmmio_post_read);
void log_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
unsigned long caller_addr);
void log_post_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
unsigned long caller_addr);
void log_read_mmio(u8 width, const volatile void __iomem *addr,
unsigned long caller_addr);
void log_post_read_mmio(u64 val, u8 width, const volatile void __iomem *addr,
unsigned long caller_addr);
#else
static inline void log_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
unsigned long caller_addr) {}
static inline void log_post_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
unsigned long caller_addr) {}
static inline void log_read_mmio(u8 width, const volatile void __iomem *addr,
unsigned long caller_addr) {}
static inline void log_post_read_mmio(u64 val, u8 width, const volatile void __iomem *addr,
unsigned long caller_addr) {}
#endif /* CONFIG_TRACE_MMIO_ACCESS */
/*
* __raw_{read,write}{b,w,l,q}() access memory in native endianness.
@@ -149,9 +188,11 @@ static inline u8 readb(const volatile void __iomem *addr)
{
u8 val;
log_read_mmio(8, addr, _THIS_IP_);
__io_br();
val = __raw_readb(addr);
__io_ar(val);
log_post_read_mmio(val, 8, addr, _THIS_IP_);
return val;
}
#endif
@@ -162,9 +203,11 @@ static inline u16 readw(const volatile void __iomem *addr)
{
u16 val;
log_read_mmio(16, addr, _THIS_IP_);
__io_br();
val = __le16_to_cpu((__le16 __force)__raw_readw(addr));
__io_ar(val);
log_post_read_mmio(val, 16, addr, _THIS_IP_);
return val;
}
#endif
@@ -175,9 +218,11 @@ static inline u32 readl(const volatile void __iomem *addr)
{
u32 val;
log_read_mmio(32, addr, _THIS_IP_);
__io_br();
val = __le32_to_cpu((__le32 __force)__raw_readl(addr));
__io_ar(val);
log_post_read_mmio(val, 32, addr, _THIS_IP_);
return val;
}
#endif
@@ -189,9 +234,11 @@ static inline u64 readq(const volatile void __iomem *addr)
{
u64 val;
log_read_mmio(64, addr, _THIS_IP_);
__io_br();
val = __le64_to_cpu(__raw_readq(addr));
__io_ar(val);
log_post_read_mmio(val, 64, addr, _THIS_IP_);
return val;
}
#endif
@@ -201,9 +248,11 @@ static inline u64 readq(const volatile void __iomem *addr)
#define writeb writeb
static inline void writeb(u8 value, volatile void __iomem *addr)
{
log_write_mmio(value, 8, addr, _THIS_IP_);
__io_bw();
__raw_writeb(value, addr);
__io_aw();
log_post_write_mmio(value, 8, addr, _THIS_IP_);
}
#endif
@@ -211,9 +260,11 @@ static inline void writeb(u8 value, volatile void __iomem *addr)
#define writew writew
static inline void writew(u16 value, volatile void __iomem *addr)
{
log_write_mmio(value, 16, addr, _THIS_IP_);
__io_bw();
__raw_writew((u16 __force)cpu_to_le16(value), addr);
__io_aw();
log_post_write_mmio(value, 16, addr, _THIS_IP_);
}
#endif
@@ -221,9 +272,11 @@ static inline void writew(u16 value, volatile void __iomem *addr)
#define writel writel
static inline void writel(u32 value, volatile void __iomem *addr)
{
log_write_mmio(value, 32, addr, _THIS_IP_);
__io_bw();
__raw_writel((u32 __force)__cpu_to_le32(value), addr);
__io_aw();
log_post_write_mmio(value, 32, addr, _THIS_IP_);
}
#endif
@@ -232,9 +285,11 @@ static inline void writel(u32 value, volatile void __iomem *addr)
#define writeq writeq
static inline void writeq(u64 value, volatile void __iomem *addr)
{
log_write_mmio(value, 64, addr, _THIS_IP_);
__io_bw();
__raw_writeq(__cpu_to_le64(value), addr);
__io_aw();
log_post_write_mmio(value, 64, addr, _THIS_IP_);
}
#endif
#endif /* CONFIG_64BIT */
@@ -248,7 +303,12 @@ static inline void writeq(u64 value, volatile void __iomem *addr)
#define readb_relaxed readb_relaxed
static inline u8 readb_relaxed(const volatile void __iomem *addr)
{
return __raw_readb(addr);
u8 val;
log_read_mmio(8, addr, _THIS_IP_);
val = __raw_readb(addr);
log_post_read_mmio(val, 8, addr, _THIS_IP_);
return val;
}
#endif
@@ -256,7 +316,12 @@ static inline u8 readb_relaxed(const volatile void __iomem *addr)
#define readw_relaxed readw_relaxed
static inline u16 readw_relaxed(const volatile void __iomem *addr)
{
return __le16_to_cpu(__raw_readw(addr));
u16 val;
log_read_mmio(16, addr, _THIS_IP_);
val = __le16_to_cpu(__raw_readw(addr));
log_post_read_mmio(val, 16, addr, _THIS_IP_);
return val;
}
#endif
@@ -264,7 +329,12 @@ static inline u16 readw_relaxed(const volatile void __iomem *addr)
#define readl_relaxed readl_relaxed
static inline u32 readl_relaxed(const volatile void __iomem *addr)
{
return __le32_to_cpu(__raw_readl(addr));
u32 val;
log_read_mmio(32, addr, _THIS_IP_);
val = __le32_to_cpu(__raw_readl(addr));
log_post_read_mmio(val, 32, addr, _THIS_IP_);
return val;
}
#endif
@@ -272,7 +342,12 @@ static inline u32 readl_relaxed(const volatile void __iomem *addr)
#define readq_relaxed readq_relaxed
static inline u64 readq_relaxed(const volatile void __iomem *addr)
{
return __le64_to_cpu(__raw_readq(addr));
u64 val;
log_read_mmio(64, addr, _THIS_IP_);
val = __le64_to_cpu(__raw_readq(addr));
log_post_read_mmio(val, 64, addr, _THIS_IP_);
return val;
}
#endif
@@ -280,7 +355,9 @@ static inline u64 readq_relaxed(const volatile void __iomem *addr)
#define writeb_relaxed writeb_relaxed
static inline void writeb_relaxed(u8 value, volatile void __iomem *addr)
{
log_write_mmio(value, 8, addr, _THIS_IP_);
__raw_writeb(value, addr);
log_post_write_mmio(value, 8, addr, _THIS_IP_);
}
#endif
@@ -288,7 +365,9 @@ static inline void writeb_relaxed(u8 value, volatile void __iomem *addr)
#define writew_relaxed writew_relaxed
static inline void writew_relaxed(u16 value, volatile void __iomem *addr)
{
log_write_mmio(value, 16, addr, _THIS_IP_);
__raw_writew(cpu_to_le16(value), addr);
log_post_write_mmio(value, 16, addr, _THIS_IP_);
}
#endif
@@ -296,7 +375,9 @@ static inline void writew_relaxed(u16 value, volatile void __iomem *addr)
#define writel_relaxed writel_relaxed
static inline void writel_relaxed(u32 value, volatile void __iomem *addr)
{
log_write_mmio(value, 32, addr, _THIS_IP_);
__raw_writel(__cpu_to_le32(value), addr);
log_post_write_mmio(value, 32, addr, _THIS_IP_);
}
#endif
@@ -304,7 +385,9 @@ static inline void writel_relaxed(u32 value, volatile void __iomem *addr)
#define writeq_relaxed writeq_relaxed
static inline void writeq_relaxed(u64 value, volatile void __iomem *addr)
{
log_write_mmio(value, 64, addr, _THIS_IP_);
__raw_writeq(__cpu_to_le64(value), addr);
log_post_write_mmio(value, 64, addr, _THIS_IP_);
}
#endif
@@ -1086,20 +1169,6 @@ static inline void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr)
}
#endif
#ifdef CONFIG_VIRT_TO_BUS
#ifndef virt_to_bus
static inline unsigned long virt_to_bus(void *address)
{
return (unsigned long)address;
}
static inline void *bus_to_virt(unsigned long address)
{
return (void *)address;
}
#endif
#endif
#ifndef memset_io
#define memset_io memset_io
/**

39
include/asm-generic/pci.h
View File

@@ -1,17 +1,30 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* linux/include/asm-generic/pci.h
*
* Copyright (C) 2003 Russell King
*/
#ifndef _ASM_GENERIC_PCI_H
#define _ASM_GENERIC_PCI_H
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
#ifndef __ASM_GENERIC_PCI_H
#define __ASM_GENERIC_PCI_H
#ifndef PCIBIOS_MIN_IO
#define PCIBIOS_MIN_IO 0
#endif
#ifndef PCIBIOS_MIN_MEM
#define PCIBIOS_MIN_MEM 0
#endif
#ifndef pcibios_assign_all_busses
/* For bootloaders that do not initialize the PCI bus */
#define pcibios_assign_all_busses() 1
#endif
/* Enable generic resource mapping code in drivers/pci/ */
#define ARCH_GENERIC_PCI_MMAP_RESOURCE
#ifdef CONFIG_PCI_DOMAINS
static inline int pci_proc_domain(struct pci_bus *bus)
{
return channel ? 15 : 14;
/* always show the domain in /proc */
return 1;
}
#endif /* HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ */
#endif /* CONFIG_PCI_DOMAINS */
#endif /* _ASM_GENERIC_PCI_H */
#endif /* __ASM_GENERIC_PCI_H */

2
include/asm-generic/pci_iomap.h
View File

@@ -25,6 +25,8 @@ extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
#ifdef CONFIG_NO_GENERIC_PCI_IOPORT_MAP
extern void __iomem *__pci_ioport_map(struct pci_dev *dev, unsigned long port,
unsigned int nr);
#elif !defined(CONFIG_HAS_IOPORT_MAP)
#define __pci_ioport_map(dev, port, nr) NULL
#else
#define __pci_ioport_map(dev, port, nr) ioport_map((port), (nr))
#endif

8
include/asm-generic/platform-feature.h
View File

@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_GENERIC_PLATFORM_FEATURE_H
#define _ASM_GENERIC_PLATFORM_FEATURE_H
/* Number of arch specific feature flags. */
#define PLATFORM_ARCH_FEAT_N 0
#endif /* _ASM_GENERIC_PLATFORM_FEATURE_H */

7
include/asm-generic/sections.h
View File

@@ -97,7 +97,7 @@ static inline bool memory_contains(void *begin, void *end, void *virt,
/**
* memory_intersects - checks if the region occupied by an object intersects
* with another memory region
* @begin: virtual address of the beginning of the memory regien
* @begin: virtual address of the beginning of the memory region
* @end: virtual address of the end of the memory region
* @virt: virtual address of the memory object
* @size: size of the memory object
@@ -110,7 +110,10 @@ static inline bool memory_intersects(void *begin, void *end, void *virt,
{
void *vend = virt + size;
return (virt >= begin && virt < end) || (vend >= begin && vend < end);
if (virt < end && vend > begin)
return true;
return false;
}
/**

2
include/asm-generic/softirq_stack.h
View File

@@ -2,7 +2,7 @@
#ifndef __ASM_GENERIC_SOFTIRQ_STACK_H
#define __ASM_GENERIC_SOFTIRQ_STACK_H
#ifdef CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK
#ifdef CONFIG_SOFTIRQ_ON_OWN_STACK
void do_softirq_own_stack(void);
#else
static inline void do_softirq_own_stack(void)

461
include/crypto/aria.h Normal file
View File

@@ -0,0 +1,461 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Cryptographic API.
*
* ARIA Cipher Algorithm.
*
* Documentation of ARIA can be found in RFC 5794.
* Copyright (c) 2022 Taehee Yoo <ap420073@gmail.com>
* Copyright (c) 2022 Taehee Yoo <ap420073@gmail.com>
*
* Information for ARIA
* http://210.104.33.10/ARIA/index-e.html (English)
* http://seed.kisa.or.kr/ (Korean)
*
* Public domain version is distributed above.
*/
#ifndef _CRYPTO_ARIA_H
#define _CRYPTO_ARIA_H
#include <linux/module.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/crypto.h>
#include <asm/byteorder.h>
#define ARIA_MIN_KEY_SIZE 16
#define ARIA_MAX_KEY_SIZE 32
#define ARIA_BLOCK_SIZE 16
#define ARIA_MAX_RD_KEYS 17
#define ARIA_RD_KEY_WORDS (ARIA_BLOCK_SIZE / sizeof(u32))
struct aria_ctx {
int key_length;
int rounds;
u32 enc_key[ARIA_MAX_RD_KEYS][ARIA_RD_KEY_WORDS];
u32 dec_key[ARIA_MAX_RD_KEYS][ARIA_RD_KEY_WORDS];
};
static const u32 key_rc[5][4] = {
{ 0x517cc1b7, 0x27220a94, 0xfe13abe8, 0xfa9a6ee0 },
{ 0x6db14acc, 0x9e21c820, 0xff28b1d5, 0xef5de2b0 },
{ 0xdb92371d, 0x2126e970, 0x03249775, 0x04e8c90e },
{ 0x517cc1b7, 0x27220a94, 0xfe13abe8, 0xfa9a6ee0 },
{ 0x6db14acc, 0x9e21c820, 0xff28b1d5, 0xef5de2b0 }
};
static const u32 s1[256] = {
0x00636363, 0x007c7c7c, 0x00777777, 0x007b7b7b,
0x00f2f2f2, 0x006b6b6b, 0x006f6f6f, 0x00c5c5c5,
0x00303030, 0x00010101, 0x00676767, 0x002b2b2b,
0x00fefefe, 0x00d7d7d7, 0x00ababab, 0x00767676,
0x00cacaca, 0x00828282, 0x00c9c9c9, 0x007d7d7d,
0x00fafafa, 0x00595959, 0x00474747, 0x00f0f0f0,
0x00adadad, 0x00d4d4d4, 0x00a2a2a2, 0x00afafaf,
0x009c9c9c, 0x00a4a4a4, 0x00727272, 0x00c0c0c0,
0x00b7b7b7, 0x00fdfdfd, 0x00939393, 0x00262626,
0x00363636, 0x003f3f3f, 0x00f7f7f7, 0x00cccccc,
0x00343434, 0x00a5a5a5, 0x00e5e5e5, 0x00f1f1f1,
0x00717171, 0x00d8d8d8, 0x00313131, 0x00151515,
0x00040404, 0x00c7c7c7, 0x00232323, 0x00c3c3c3,
0x00181818, 0x00969696, 0x00050505, 0x009a9a9a,
0x00070707, 0x00121212, 0x00808080, 0x00e2e2e2,
0x00ebebeb, 0x00272727, 0x00b2b2b2, 0x00757575,
0x00090909, 0x00838383, 0x002c2c2c, 0x001a1a1a,
0x001b1b1b, 0x006e6e6e, 0x005a5a5a, 0x00a0a0a0,
0x00525252, 0x003b3b3b, 0x00d6d6d6, 0x00b3b3b3,
0x00292929, 0x00e3e3e3, 0x002f2f2f, 0x00848484,
0x00535353, 0x00d1d1d1, 0x00000000, 0x00ededed,
0x00202020, 0x00fcfcfc, 0x00b1b1b1, 0x005b5b5b,
0x006a6a6a, 0x00cbcbcb, 0x00bebebe, 0x00393939,
0x004a4a4a, 0x004c4c4c, 0x00585858, 0x00cfcfcf,
0x00d0d0d0, 0x00efefef, 0x00aaaaaa, 0x00fbfbfb,
0x00434343, 0x004d4d4d, 0x00333333, 0x00858585,
0x00454545, 0x00f9f9f9, 0x00020202, 0x007f7f7f,
0x00505050, 0x003c3c3c, 0x009f9f9f, 0x00a8a8a8,
0x00515151, 0x00a3a3a3, 0x00404040, 0x008f8f8f,
0x00929292, 0x009d9d9d, 0x00383838, 0x00f5f5f5,
0x00bcbcbc, 0x00b6b6b6, 0x00dadada, 0x00212121,
0x00101010, 0x00ffffff, 0x00f3f3f3, 0x00d2d2d2,
0x00cdcdcd, 0x000c0c0c, 0x00131313, 0x00ececec,
0x005f5f5f, 0x00979797, 0x00444444, 0x00171717,
0x00c4c4c4, 0x00a7a7a7, 0x007e7e7e, 0x003d3d3d,
0x00646464, 0x005d5d5d, 0x00191919, 0x00737373,
0x00606060, 0x00818181, 0x004f4f4f, 0x00dcdcdc,
0x00222222, 0x002a2a2a, 0x00909090, 0x00888888,
0x00464646, 0x00eeeeee, 0x00b8b8b8, 0x00141414,
0x00dedede, 0x005e5e5e, 0x000b0b0b, 0x00dbdbdb,
0x00e0e0e0, 0x00323232, 0x003a3a3a, 0x000a0a0a,
0x00494949, 0x00060606, 0x00242424, 0x005c5c5c,
0x00c2c2c2, 0x00d3d3d3, 0x00acacac, 0x00626262,
0x00919191, 0x00959595, 0x00e4e4e4, 0x00797979,
0x00e7e7e7, 0x00c8c8c8, 0x00373737, 0x006d6d6d,
0x008d8d8d, 0x00d5d5d5, 0x004e4e4e, 0x00a9a9a9,
0x006c6c6c, 0x00565656, 0x00f4f4f4, 0x00eaeaea,
0x00656565, 0x007a7a7a, 0x00aeaeae, 0x00080808,
0x00bababa, 0x00787878, 0x00252525, 0x002e2e2e,
0x001c1c1c, 0x00a6a6a6, 0x00b4b4b4, 0x00c6c6c6,
0x00e8e8e8, 0x00dddddd, 0x00747474, 0x001f1f1f,
0x004b4b4b, 0x00bdbdbd, 0x008b8b8b, 0x008a8a8a,
0x00707070, 0x003e3e3e, 0x00b5b5b5, 0x00666666,
0x00484848, 0x00030303, 0x00f6f6f6, 0x000e0e0e,
0x00616161, 0x00353535, 0x00575757, 0x00b9b9b9,
0x00868686, 0x00c1c1c1, 0x001d1d1d, 0x009e9e9e,
0x00e1e1e1, 0x00f8f8f8, 0x00989898, 0x00111111,
0x00696969, 0x00d9d9d9, 0x008e8e8e, 0x00949494,
0x009b9b9b, 0x001e1e1e, 0x00878787, 0x00e9e9e9,
0x00cecece, 0x00555555, 0x00282828, 0x00dfdfdf,
0x008c8c8c, 0x00a1a1a1, 0x00898989, 0x000d0d0d,
0x00bfbfbf, 0x00e6e6e6, 0x00424242, 0x00686868,
0x00414141, 0x00999999, 0x002d2d2d, 0x000f0f0f,
0x00b0b0b0, 0x00545454, 0x00bbbbbb, 0x00161616
};
static const u32 s2[256] = {
0xe200e2e2, 0x4e004e4e, 0x54005454, 0xfc00fcfc,
0x94009494, 0xc200c2c2, 0x4a004a4a, 0xcc00cccc,
0x62006262, 0x0d000d0d, 0x6a006a6a, 0x46004646,
0x3c003c3c, 0x4d004d4d, 0x8b008b8b, 0xd100d1d1,
0x5e005e5e, 0xfa00fafa, 0x64006464, 0xcb00cbcb,
0xb400b4b4, 0x97009797, 0xbe00bebe, 0x2b002b2b,
0xbc00bcbc, 0x77007777, 0x2e002e2e, 0x03000303,
0xd300d3d3, 0x19001919, 0x59005959, 0xc100c1c1,
0x1d001d1d, 0x06000606, 0x41004141, 0x6b006b6b,
0x55005555, 0xf000f0f0, 0x99009999, 0x69006969,
0xea00eaea, 0x9c009c9c, 0x18001818, 0xae00aeae,
0x63006363, 0xdf00dfdf, 0xe700e7e7, 0xbb00bbbb,
0x00000000, 0x73007373, 0x66006666, 0xfb00fbfb,
0x96009696, 0x4c004c4c, 0x85008585, 0xe400e4e4,
0x3a003a3a, 0x09000909, 0x45004545, 0xaa00aaaa,
0x0f000f0f, 0xee00eeee, 0x10001010, 0xeb00ebeb,
0x2d002d2d, 0x7f007f7f, 0xf400f4f4, 0x29002929,
0xac00acac, 0xcf00cfcf, 0xad00adad, 0x91009191,
0x8d008d8d, 0x78007878, 0xc800c8c8, 0x95009595,
0xf900f9f9, 0x2f002f2f, 0xce00cece, 0xcd00cdcd,
0x08000808, 0x7a007a7a, 0x88008888, 0x38003838,
0x5c005c5c, 0x83008383, 0x2a002a2a, 0x28002828,
0x47004747, 0xdb00dbdb, 0xb800b8b8, 0xc700c7c7,
0x93009393, 0xa400a4a4, 0x12001212, 0x53005353,
0xff00ffff, 0x87008787, 0x0e000e0e, 0x31003131,
0x36003636, 0x21002121, 0x58005858, 0x48004848,
0x01000101, 0x8e008e8e, 0x37003737, 0x74007474,
0x32003232, 0xca00caca, 0xe900e9e9, 0xb100b1b1,
0xb700b7b7, 0xab00abab, 0x0c000c0c, 0xd700d7d7,
0xc400c4c4, 0x56005656, 0x42004242, 0x26002626,
0x07000707, 0x98009898, 0x60006060, 0xd900d9d9,
0xb600b6b6, 0xb900b9b9, 0x11001111, 0x40004040,
0xec00ecec, 0x20002020, 0x8c008c8c, 0xbd00bdbd,
0xa000a0a0, 0xc900c9c9, 0x84008484, 0x04000404,
0x49004949, 0x23002323, 0xf100f1f1, 0x4f004f4f,
0x50005050, 0x1f001f1f, 0x13001313, 0xdc00dcdc,
0xd800d8d8, 0xc000c0c0, 0x9e009e9e, 0x57005757,
0xe300e3e3, 0xc300c3c3, 0x7b007b7b, 0x65006565,
0x3b003b3b, 0x02000202, 0x8f008f8f, 0x3e003e3e,
0xe800e8e8, 0x25002525, 0x92009292, 0xe500e5e5,
0x15001515, 0xdd00dddd, 0xfd00fdfd, 0x17001717,
0xa900a9a9, 0xbf00bfbf, 0xd400d4d4, 0x9a009a9a,
0x7e007e7e, 0xc500c5c5, 0x39003939, 0x67006767,
0xfe00fefe, 0x76007676, 0x9d009d9d, 0x43004343,
0xa700a7a7, 0xe100e1e1, 0xd000d0d0, 0xf500f5f5,
0x68006868, 0xf200f2f2, 0x1b001b1b, 0x34003434,
0x70007070, 0x05000505, 0xa300a3a3, 0x8a008a8a,
0xd500d5d5, 0x79007979, 0x86008686, 0xa800a8a8,
0x30003030, 0xc600c6c6, 0x51005151, 0x4b004b4b,
0x1e001e1e, 0xa600a6a6, 0x27002727, 0xf600f6f6,
0x35003535, 0xd200d2d2, 0x6e006e6e, 0x24002424,
0x16001616, 0x82008282, 0x5f005f5f, 0xda00dada,
0xe600e6e6, 0x75007575, 0xa200a2a2, 0xef00efef,
0x2c002c2c, 0xb200b2b2, 0x1c001c1c, 0x9f009f9f,
0x5d005d5d, 0x6f006f6f, 0x80008080, 0x0a000a0a,
0x72007272, 0x44004444, 0x9b009b9b, 0x6c006c6c,
0x90009090, 0x0b000b0b, 0x5b005b5b, 0x33003333,
0x7d007d7d, 0x5a005a5a, 0x52005252, 0xf300f3f3,
0x61006161, 0xa100a1a1, 0xf700f7f7, 0xb000b0b0,
0xd600d6d6, 0x3f003f3f, 0x7c007c7c, 0x6d006d6d,
0xed00eded, 0x14001414, 0xe000e0e0, 0xa500a5a5,
0x3d003d3d, 0x22002222, 0xb300b3b3, 0xf800f8f8,
0x89008989, 0xde00dede, 0x71007171, 0x1a001a1a,
0xaf00afaf, 0xba00baba, 0xb500b5b5, 0x81008181
};
static const u32 x1[256] = {
0x52520052, 0x09090009, 0x6a6a006a, 0xd5d500d5,
0x30300030, 0x36360036, 0xa5a500a5, 0x38380038,
0xbfbf00bf, 0x40400040, 0xa3a300a3, 0x9e9e009e,
0x81810081, 0xf3f300f3, 0xd7d700d7, 0xfbfb00fb,
0x7c7c007c, 0xe3e300e3, 0x39390039, 0x82820082,
0x9b9b009b, 0x2f2f002f, 0xffff00ff, 0x87870087,
0x34340034, 0x8e8e008e, 0x43430043, 0x44440044,
0xc4c400c4, 0xdede00de, 0xe9e900e9, 0xcbcb00cb,
0x54540054, 0x7b7b007b, 0x94940094, 0x32320032,
0xa6a600a6, 0xc2c200c2, 0x23230023, 0x3d3d003d,
0xeeee00ee, 0x4c4c004c, 0x95950095, 0x0b0b000b,
0x42420042, 0xfafa00fa, 0xc3c300c3, 0x4e4e004e,
0x08080008, 0x2e2e002e, 0xa1a100a1, 0x66660066,
0x28280028, 0xd9d900d9, 0x24240024, 0xb2b200b2,
0x76760076, 0x5b5b005b, 0xa2a200a2, 0x49490049,
0x6d6d006d, 0x8b8b008b, 0xd1d100d1, 0x25250025,
0x72720072, 0xf8f800f8, 0xf6f600f6, 0x64640064,
0x86860086, 0x68680068, 0x98980098, 0x16160016,
0xd4d400d4, 0xa4a400a4, 0x5c5c005c, 0xcccc00cc,
0x5d5d005d, 0x65650065, 0xb6b600b6, 0x92920092,
0x6c6c006c, 0x70700070, 0x48480048, 0x50500050,
0xfdfd00fd, 0xeded00ed, 0xb9b900b9, 0xdada00da,
0x5e5e005e, 0x15150015, 0x46460046, 0x57570057,
0xa7a700a7, 0x8d8d008d, 0x9d9d009d, 0x84840084,
0x90900090, 0xd8d800d8, 0xabab00ab, 0x00000000,
0x8c8c008c, 0xbcbc00bc, 0xd3d300d3, 0x0a0a000a,
0xf7f700f7, 0xe4e400e4, 0x58580058, 0x05050005,
0xb8b800b8, 0xb3b300b3, 0x45450045, 0x06060006,
0xd0d000d0, 0x2c2c002c, 0x1e1e001e, 0x8f8f008f,
0xcaca00ca, 0x3f3f003f, 0x0f0f000f, 0x02020002,
0xc1c100c1, 0xafaf00af, 0xbdbd00bd, 0x03030003,
0x01010001, 0x13130013, 0x8a8a008a, 0x6b6b006b,
0x3a3a003a, 0x91910091, 0x11110011, 0x41410041,
0x4f4f004f, 0x67670067, 0xdcdc00dc, 0xeaea00ea,
0x97970097, 0xf2f200f2, 0xcfcf00cf, 0xcece00ce,
0xf0f000f0, 0xb4b400b4, 0xe6e600e6, 0x73730073,
0x96960096, 0xacac00ac, 0x74740074, 0x22220022,
0xe7e700e7, 0xadad00ad, 0x35350035, 0x85850085,
0xe2e200e2, 0xf9f900f9, 0x37370037, 0xe8e800e8,
0x1c1c001c, 0x75750075, 0xdfdf00df, 0x6e6e006e,
0x47470047, 0xf1f100f1, 0x1a1a001a, 0x71710071,
0x1d1d001d, 0x29290029, 0xc5c500c5, 0x89890089,
0x6f6f006f, 0xb7b700b7, 0x62620062, 0x0e0e000e,
0xaaaa00aa, 0x18180018, 0xbebe00be, 0x1b1b001b,
0xfcfc00fc, 0x56560056, 0x3e3e003e, 0x4b4b004b,
0xc6c600c6, 0xd2d200d2, 0x79790079, 0x20200020,
0x9a9a009a, 0xdbdb00db, 0xc0c000c0, 0xfefe00fe,
0x78780078, 0xcdcd00cd, 0x5a5a005a, 0xf4f400f4,
0x1f1f001f, 0xdddd00dd, 0xa8a800a8, 0x33330033,
0x88880088, 0x07070007, 0xc7c700c7, 0x31310031,
0xb1b100b1, 0x12120012, 0x10100010, 0x59590059,
0x27270027, 0x80800080, 0xecec00ec, 0x5f5f005f,
0x60600060, 0x51510051, 0x7f7f007f, 0xa9a900a9,
0x19190019, 0xb5b500b5, 0x4a4a004a, 0x0d0d000d,
0x2d2d002d, 0xe5e500e5, 0x7a7a007a, 0x9f9f009f,
0x93930093, 0xc9c900c9, 0x9c9c009c, 0xefef00ef,
0xa0a000a0, 0xe0e000e0, 0x3b3b003b, 0x4d4d004d,
0xaeae00ae, 0x2a2a002a, 0xf5f500f5, 0xb0b000b0,
0xc8c800c8, 0xebeb00eb, 0xbbbb00bb, 0x3c3c003c,
0x83830083, 0x53530053, 0x99990099, 0x61610061,
0x17170017, 0x2b2b002b, 0x04040004, 0x7e7e007e,
0xbaba00ba, 0x77770077, 0xd6d600d6, 0x26260026,
0xe1e100e1, 0x69690069, 0x14140014, 0x63630063,
0x55550055, 0x21210021, 0x0c0c000c, 0x7d7d007d
};
static const u32 x2[256] = {
0x30303000, 0x68686800, 0x99999900, 0x1b1b1b00,
0x87878700, 0xb9b9b900, 0x21212100, 0x78787800,
0x50505000, 0x39393900, 0xdbdbdb00, 0xe1e1e100,
0x72727200, 0x09090900, 0x62626200, 0x3c3c3c00,
0x3e3e3e00, 0x7e7e7e00, 0x5e5e5e00, 0x8e8e8e00,
0xf1f1f100, 0xa0a0a000, 0xcccccc00, 0xa3a3a300,
0x2a2a2a00, 0x1d1d1d00, 0xfbfbfb00, 0xb6b6b600,
0xd6d6d600, 0x20202000, 0xc4c4c400, 0x8d8d8d00,
0x81818100, 0x65656500, 0xf5f5f500, 0x89898900,
0xcbcbcb00, 0x9d9d9d00, 0x77777700, 0xc6c6c600,
0x57575700, 0x43434300, 0x56565600, 0x17171700,
0xd4d4d400, 0x40404000, 0x1a1a1a00, 0x4d4d4d00,
0xc0c0c000, 0x63636300, 0x6c6c6c00, 0xe3e3e300,
0xb7b7b700, 0xc8c8c800, 0x64646400, 0x6a6a6a00,
0x53535300, 0xaaaaaa00, 0x38383800, 0x98989800,
0x0c0c0c00, 0xf4f4f400, 0x9b9b9b00, 0xededed00,
0x7f7f7f00, 0x22222200, 0x76767600, 0xafafaf00,
0xdddddd00, 0x3a3a3a00, 0x0b0b0b00, 0x58585800,
0x67676700, 0x88888800, 0x06060600, 0xc3c3c300,
0x35353500, 0x0d0d0d00, 0x01010100, 0x8b8b8b00,
0x8c8c8c00, 0xc2c2c200, 0xe6e6e600, 0x5f5f5f00,
0x02020200, 0x24242400, 0x75757500, 0x93939300,
0x66666600, 0x1e1e1e00, 0xe5e5e500, 0xe2e2e200,
0x54545400, 0xd8d8d800, 0x10101000, 0xcecece00,
0x7a7a7a00, 0xe8e8e800, 0x08080800, 0x2c2c2c00,
0x12121200, 0x97979700, 0x32323200, 0xababab00,
0xb4b4b400, 0x27272700, 0x0a0a0a00, 0x23232300,
0xdfdfdf00, 0xefefef00, 0xcacaca00, 0xd9d9d900,
0xb8b8b800, 0xfafafa00, 0xdcdcdc00, 0x31313100,
0x6b6b6b00, 0xd1d1d100, 0xadadad00, 0x19191900,
0x49494900, 0xbdbdbd00, 0x51515100, 0x96969600,
0xeeeeee00, 0xe4e4e400, 0xa8a8a800, 0x41414100,
0xdadada00, 0xffffff00, 0xcdcdcd00, 0x55555500,
0x86868600, 0x36363600, 0xbebebe00, 0x61616100,
0x52525200, 0xf8f8f800, 0xbbbbbb00, 0x0e0e0e00,
0x82828200, 0x48484800, 0x69696900, 0x9a9a9a00,
0xe0e0e000, 0x47474700, 0x9e9e9e00, 0x5c5c5c00,
0x04040400, 0x4b4b4b00, 0x34343400, 0x15151500,
0x79797900, 0x26262600, 0xa7a7a700, 0xdedede00,
0x29292900, 0xaeaeae00, 0x92929200, 0xd7d7d700,
0x84848400, 0xe9e9e900, 0xd2d2d200, 0xbababa00,
0x5d5d5d00, 0xf3f3f300, 0xc5c5c500, 0xb0b0b000,
0xbfbfbf00, 0xa4a4a400, 0x3b3b3b00, 0x71717100,
0x44444400, 0x46464600, 0x2b2b2b00, 0xfcfcfc00,
0xebebeb00, 0x6f6f6f00, 0xd5d5d500, 0xf6f6f600,
0x14141400, 0xfefefe00, 0x7c7c7c00, 0x70707000,
0x5a5a5a00, 0x7d7d7d00, 0xfdfdfd00, 0x2f2f2f00,
0x18181800, 0x83838300, 0x16161600, 0xa5a5a500,
0x91919100, 0x1f1f1f00, 0x05050500, 0x95959500,
0x74747400, 0xa9a9a900, 0xc1c1c100, 0x5b5b5b00,
0x4a4a4a00, 0x85858500, 0x6d6d6d00, 0x13131300,
0x07070700, 0x4f4f4f00, 0x4e4e4e00, 0x45454500,
0xb2b2b200, 0x0f0f0f00, 0xc9c9c900, 0x1c1c1c00,
0xa6a6a600, 0xbcbcbc00, 0xececec00, 0x73737300,
0x90909000, 0x7b7b7b00, 0xcfcfcf00, 0x59595900,
0x8f8f8f00, 0xa1a1a100, 0xf9f9f900, 0x2d2d2d00,
0xf2f2f200, 0xb1b1b100, 0x00000000, 0x94949400,
0x37373700, 0x9f9f9f00, 0xd0d0d000, 0x2e2e2e00,
0x9c9c9c00, 0x6e6e6e00, 0x28282800, 0x3f3f3f00,
0x80808000, 0xf0f0f000, 0x3d3d3d00, 0xd3d3d300,
0x25252500, 0x8a8a8a00, 0xb5b5b500, 0xe7e7e700,
0x42424200, 0xb3b3b300, 0xc7c7c700, 0xeaeaea00,
0xf7f7f700, 0x4c4c4c00, 0x11111100, 0x33333300,
0x03030300, 0xa2a2a200, 0xacacac00, 0x60606000
};
static inline u32 rotl32(u32 v, u32 r)
{
return ((v << r) | (v >> (32 - r)));
}
static inline u32 rotr32(u32 v, u32 r)
{
return ((v >> r) | (v << (32 - r)));
}
static inline u32 bswap32(u32 v)
{
return ((v << 24) ^
(v >> 24) ^
((v & 0x0000ff00) << 8) ^
((v & 0x00ff0000) >> 8));
}
static inline u8 get_u8(u32 x, u32 y)
{
return (x >> ((3 - y) * 8));
}
static inline u32 make_u32(u8 v0, u8 v1, u8 v2, u8 v3)
{
return ((u32)v0 << 24) | ((u32)v1 << 16) | ((u32)v2 << 8) | ((u32)v3);
}
static inline u32 aria_m(u32 t0)
{
return rotr32(t0, 8) ^ rotr32(t0 ^ rotr32(t0, 8), 16);
}
/* S-Box Layer 1 + M */
static inline void aria_sbox_layer1_with_pre_diff(u32 *t0, u32 *t1, u32 *t2,
u32 *t3)
{
*t0 = s1[get_u8(*t0, 0)] ^
s2[get_u8(*t0, 1)] ^
x1[get_u8(*t0, 2)] ^
x2[get_u8(*t0, 3)];
*t1 = s1[get_u8(*t1, 0)] ^
s2[get_u8(*t1, 1)] ^
x1[get_u8(*t1, 2)] ^
x2[get_u8(*t1, 3)];
*t2 = s1[get_u8(*t2, 0)] ^
s2[get_u8(*t2, 1)] ^
x1[get_u8(*t2, 2)] ^
x2[get_u8(*t2, 3)];
*t3 = s1[get_u8(*t3, 0)] ^
s2[get_u8(*t3, 1)] ^
x1[get_u8(*t3, 2)] ^
x2[get_u8(*t3, 3)];
}
/* S-Box Layer 2 + M */
static inline void aria_sbox_layer2_with_pre_diff(u32 *t0, u32 *t1, u32 *t2,
u32 *t3)
{
*t0 = x1[get_u8(*t0, 0)] ^
x2[get_u8(*t0, 1)] ^
s1[get_u8(*t0, 2)] ^
s2[get_u8(*t0, 3)];
*t1 = x1[get_u8(*t1, 0)] ^
x2[get_u8(*t1, 1)] ^
s1[get_u8(*t1, 2)] ^
s2[get_u8(*t1, 3)];
*t2 = x1[get_u8(*t2, 0)] ^
x2[get_u8(*t2, 1)] ^
s1[get_u8(*t2, 2)] ^
s2[get_u8(*t2, 3)];
*t3 = x1[get_u8(*t3, 0)] ^
x2[get_u8(*t3, 1)] ^
s1[get_u8(*t3, 2)] ^
s2[get_u8(*t3, 3)];
}
/* Word-level diffusion */
static inline void aria_diff_word(u32 *t0, u32 *t1, u32 *t2, u32 *t3)
{
*t1 ^= *t2;
*t2 ^= *t3;
*t0 ^= *t1;
*t3 ^= *t1;
*t2 ^= *t0;
*t1 ^= *t2;
}
/* Byte-level diffusion */
static inline void aria_diff_byte(u32 *t1, u32 *t2, u32 *t3)
{
*t1 = ((*t1 << 8) & 0xff00ff00) ^ ((*t1 >> 8) & 0x00ff00ff);
*t2 = rotr32(*t2, 16);
*t3 = bswap32(*t3);
}
/* Key XOR Layer */
static inline void aria_add_round_key(u32 *rk, u32 *t0, u32 *t1, u32 *t2,
u32 *t3)
{
*t0 ^= rk[0];
*t1 ^= rk[1];
*t2 ^= rk[2];
*t3 ^= rk[3];
}
/* Odd round Substitution & Diffusion */
static inline void aria_subst_diff_odd(u32 *t0, u32 *t1, u32 *t2, u32 *t3)
{
aria_sbox_layer1_with_pre_diff(t0, t1, t2, t3);
aria_diff_word(t0, t1, t2, t3);
aria_diff_byte(t1, t2, t3);
aria_diff_word(t0, t1, t2, t3);
}
/* Even round Substitution & Diffusion */
static inline void aria_subst_diff_even(u32 *t0, u32 *t1, u32 *t2, u32 *t3)
{
aria_sbox_layer2_with_pre_diff(t0, t1, t2, t3);
aria_diff_word(t0, t1, t2, t3);
aria_diff_byte(t3, t0, t1);
aria_diff_word(t0, t1, t2, t3);
}
/* Q, R Macro expanded ARIA GSRK */
static inline void aria_gsrk(u32 *rk, u32 *x, u32 *y, u32 n)
{
int q = 4 - (n / 32);
int r = n % 32;
rk[0] = (x[0]) ^
((y[q % 4]) >> r) ^
((y[(q + 3) % 4]) << (32 - r));
rk[1] = (x[1]) ^
((y[(q + 1) % 4]) >> r) ^
((y[q % 4]) << (32 - r));
rk[2] = (x[2]) ^
((y[(q + 2) % 4]) >> r) ^
((y[(q + 1) % 4]) << (32 - r));
rk[3] = (x[3]) ^
((y[(q + 3) % 4]) >> r) ^
((y[(q + 2) % 4]) << (32 - r));
}
#endif

2
include/crypto/hash.h
View File

@@ -718,6 +718,8 @@ static inline void ahash_request_set_crypt(struct ahash_request *req,
struct crypto_shash *crypto_alloc_shash(const char *alg_name, u32 type,
u32 mask);
int crypto_has_shash(const char *alg_name, u32 type, u32 mask);
static inline struct crypto_tfm *crypto_shash_tfm(struct crypto_shash *tfm)
{
return &tfm->base;

108
include/crypto/internal/blake2s.h
View File

@@ -8,7 +8,6 @@
#define _CRYPTO_INTERNAL_BLAKE2S_H
#include <crypto/blake2s.h>
#include <crypto/internal/hash.h>
#include <linux/string.h>
void blake2s_compress_generic(struct blake2s_state *state, const u8 *block,
@@ -19,111 +18,4 @@ void blake2s_compress(struct blake2s_state *state, const u8 *block,
bool blake2s_selftest(void);
static inline void blake2s_set_lastblock(struct blake2s_state *state)
{
state->f[0] = -1;
}
/* Helper functions for BLAKE2s shared by the library and shash APIs */
static __always_inline void
__blake2s_update(struct blake2s_state *state, const u8 *in, size_t inlen,
bool force_generic)
{
const size_t fill = BLAKE2S_BLOCK_SIZE - state->buflen;
if (unlikely(!inlen))
return;
if (inlen > fill) {
memcpy(state->buf + state->buflen, in, fill);
if (force_generic)
blake2s_compress_generic(state, state->buf, 1,
BLAKE2S_BLOCK_SIZE);
else
blake2s_compress(state, state->buf, 1,
BLAKE2S_BLOCK_SIZE);
state->buflen = 0;
in += fill;
inlen -= fill;
}
if (inlen > BLAKE2S_BLOCK_SIZE) {
const size_t nblocks = DIV_ROUND_UP(inlen, BLAKE2S_BLOCK_SIZE);
/* Hash one less (full) block than strictly possible */
if (force_generic)
blake2s_compress_generic(state, in, nblocks - 1,
BLAKE2S_BLOCK_SIZE);
else
blake2s_compress(state, in, nblocks - 1,
BLAKE2S_BLOCK_SIZE);
in += BLAKE2S_BLOCK_SIZE * (nblocks - 1);
inlen -= BLAKE2S_BLOCK_SIZE * (nblocks - 1);
}
memcpy(state->buf + state->buflen, in, inlen);
state->buflen += inlen;
}
static __always_inline void
__blake2s_final(struct blake2s_state *state, u8 *out, bool force_generic)
{
blake2s_set_lastblock(state);
memset(state->buf + state->buflen, 0,
BLAKE2S_BLOCK_SIZE - state->buflen); /* Padding */
if (force_generic)
blake2s_compress_generic(state, state->buf, 1, state->buflen);
else
blake2s_compress(state, state->buf, 1, state->buflen);
cpu_to_le32_array(state->h, ARRAY_SIZE(state->h));
memcpy(out, state->h, state->outlen);
}
/* Helper functions for shash implementations of BLAKE2s */
struct blake2s_tfm_ctx {
u8 key[BLAKE2S_KEY_SIZE];
unsigned int keylen;
};
static inline int crypto_blake2s_setkey(struct crypto_shash *tfm,
const u8 *key, unsigned int keylen)
{
struct blake2s_tfm_ctx *tctx = crypto_shash_ctx(tfm);
if (keylen == 0 || keylen > BLAKE2S_KEY_SIZE)
return -EINVAL;
memcpy(tctx->key, key, keylen);
tctx->keylen = keylen;
return 0;
}
static inline int crypto_blake2s_init(struct shash_desc *desc)
{
const struct blake2s_tfm_ctx *tctx = crypto_shash_ctx(desc->tfm);
struct blake2s_state *state = shash_desc_ctx(desc);
unsigned int outlen = crypto_shash_digestsize(desc->tfm);
__blake2s_init(state, outlen, tctx->key, tctx->keylen);
return 0;
}
static inline int crypto_blake2s_update(struct shash_desc *desc,
const u8 *in, unsigned int inlen,
bool force_generic)
{
struct blake2s_state *state = shash_desc_ctx(desc);
__blake2s_update(state, in, inlen, force_generic);
return 0;
}
static inline int crypto_blake2s_final(struct shash_desc *desc, u8 *out,
bool force_generic)
{
struct blake2s_state *state = shash_desc_ctx(desc);
__blake2s_final(state, out, force_generic);
return 0;
}
#endif /* _CRYPTO_INTERNAL_BLAKE2S_H */

2
include/crypto/kpp.h
View File

@@ -104,6 +104,8 @@ struct kpp_alg {
*/
struct crypto_kpp *crypto_alloc_kpp(const char *alg_name, u32 type, u32 mask);
int crypto_has_kpp(const char *alg_name, u32 type, u32 mask);
static inline struct crypto_tfm *crypto_kpp_tfm(struct crypto_kpp *tfm)
{
return &tfm->base;

22
include/crypto/polyval.h Normal file
View File

@@ -0,0 +1,22 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Common values for the Polyval hash algorithm
*
* Copyright 2021 Google LLC
*/
#ifndef _CRYPTO_POLYVAL_H
#define _CRYPTO_POLYVAL_H
#include <linux/types.h>
#include <linux/crypto.h>
#define POLYVAL_BLOCK_SIZE 16
#define POLYVAL_DIGEST_SIZE 16
void polyval_mul_non4k(u8 *op1, const u8 *op2);
void polyval_update_non4k(const u8 *key, const u8 *in,
size_t nblocks, u8 *accumulator);
#endif

34
include/drm/display/drm_dp_aux_bus.h
View File

@@ -44,9 +44,37 @@ static inline struct dp_aux_ep_driver *to_dp_aux_ep_drv(struct device_driver *dr
return container_of(drv, struct dp_aux_ep_driver, driver);
}
int of_dp_aux_populate_ep_devices(struct drm_dp_aux *aux);
void of_dp_aux_depopulate_ep_devices(struct drm_dp_aux *aux);
int devm_of_dp_aux_populate_ep_devices(struct drm_dp_aux *aux);
int of_dp_aux_populate_bus(struct drm_dp_aux *aux,
int (*done_probing)(struct drm_dp_aux *aux));
void of_dp_aux_depopulate_bus(struct drm_dp_aux *aux);
int devm_of_dp_aux_populate_bus(struct drm_dp_aux *aux,
int (*done_probing)(struct drm_dp_aux *aux));
/* Deprecated versions of the above functions. To be removed when no callers. */
static inline int of_dp_aux_populate_ep_devices(struct drm_dp_aux *aux)
{
int ret;
ret = of_dp_aux_populate_bus(aux, NULL);
/* New API returns -ENODEV for no child case; adapt to old assumption */
return (ret != -ENODEV) ? ret : 0;
}
static inline int devm_of_dp_aux_populate_ep_devices(struct drm_dp_aux *aux)
{
int ret;
ret = devm_of_dp_aux_populate_bus(aux, NULL);
/* New API returns -ENODEV for no child case; adapt to old assumption */
return (ret != -ENODEV) ? ret : 0;
}
static inline void of_dp_aux_depopulate_ep_devices(struct drm_dp_aux *aux)
{
of_dp_aux_depopulate_bus(aux);
}
#define dp_aux_dp_driver_register(aux_ep_drv) \
__dp_aux_dp_driver_register(aux_ep_drv, THIS_MODULE)

48
include/drm/display/drm_dp_helper.h
View File

@@ -370,13 +370,55 @@ struct drm_dp_aux {
* helpers assume this is the case.
*
* Also note that this callback can be called no matter the
* state @dev is in. Drivers that need that device to be powered
* to perform this operation will first need to make sure it's
* been properly enabled.
* state @dev is in and also no matter what state the panel is
* in. It's expected:
*
* - If the @dev providing the AUX bus is currently unpowered then
* it will power itself up for the transfer.
*
* - If we're on eDP (using a drm_panel) and the panel is not in a
* state where it can respond (it's not powered or it's in a
* low power state) then this function may return an error, but
* not crash. It's up to the caller of this code to make sure that
* the panel is powered on if getting an error back is not OK. If a
* drm_panel driver is initiating a DP AUX transfer it may power
* itself up however it wants. All other code should ensure that
* the pre_enable() bridge chain (which eventually calls the
* drm_panel prepare function) has powered the panel.
*/
ssize_t (*transfer)(struct drm_dp_aux *aux,
struct drm_dp_aux_msg *msg);
/**
* @wait_hpd_asserted: wait for HPD to be asserted
*
* This is mainly useful for eDP panels drivers to wait for an eDP
* panel to finish powering on. This is an optional function.
*
* This function will efficiently wait for the HPD signal to be
* asserted. The `wait_us` parameter that is passed in says that we
* know that the HPD signal is expected to be asserted within `wait_us`
* microseconds. This function could wait for longer than `wait_us` if
* the logic in the DP controller has a long debouncing time. The
* important thing is that if this function returns success that the
* DP controller is ready to send AUX transactions.
*
* This function returns 0 if HPD was asserted or -ETIMEDOUT if time
* expired and HPD wasn't asserted. This function should not print
* timeout errors to the log.
*
* The semantics of this function are designed to match the
* readx_poll_timeout() function. That means a `wait_us` of 0 means
* to wait forever. Like readx_poll_timeout(), this function may sleep.
*
* NOTE: this function specifically reports the state of the HPD pin
* that's associated with the DP AUX channel. This is different from
* the HPD concept in much of the rest of DRM which is more about
* physical presence of a display. For eDP, for instance, a display is
* assumed always present even if the HPD pin is deasserted.
*/
int (*wait_hpd_asserted)(struct drm_dp_aux *aux, unsigned long wait_us);
/**
* @i2c_nack_count: Counts I2C NACKs, used for DP validation.
*/

2
include/drm/drm_atomic_helper.h
View File

@@ -46,6 +46,8 @@ int drm_atomic_helper_check_plane_state(struct drm_plane_state *plane_state,
int max_scale,
bool can_position,
bool can_update_disabled);
int drm_atomic_helper_check_crtc_state(struct drm_crtc_state *crtc_state,
bool can_disable_primary_plane);
int drm_atomic_helper_check_planes(struct drm_device *dev,
struct drm_atomic_state *state);
int drm_atomic_helper_check(struct drm_device *dev,

15
include/drm/drm_bridge.h
View File

@@ -796,6 +796,7 @@ drm_priv_to_bridge(struct drm_private_obj *priv)
}
void drm_bridge_add(struct drm_bridge *bridge);
int devm_drm_bridge_add(struct device *dev, struct drm_bridge *bridge);
void drm_bridge_remove(struct drm_bridge *bridge);
int drm_bridge_attach(struct drm_encoder *encoder, struct drm_bridge *bridge,
struct drm_bridge *previous,
@@ -917,16 +918,30 @@ void drm_bridge_hpd_notify(struct drm_bridge *bridge,
enum drm_connector_status status);
#ifdef CONFIG_DRM_PANEL_BRIDGE
bool drm_bridge_is_panel(const struct drm_bridge *bridge);
struct drm_bridge *drm_panel_bridge_add(struct drm_panel *panel);
struct drm_bridge *drm_panel_bridge_add_typed(struct drm_panel *panel,
u32 connector_type);
void drm_panel_bridge_remove(struct drm_bridge *bridge);
int drm_panel_bridge_set_orientation(struct drm_connector *connector,
struct drm_bridge *bridge);
struct drm_bridge *devm_drm_panel_bridge_add(struct device *dev,
struct drm_panel *panel);
struct drm_bridge *devm_drm_panel_bridge_add_typed(struct device *dev,
struct drm_panel *panel,
u32 connector_type);
struct drm_connector *drm_panel_bridge_connector(struct drm_bridge *bridge);
#else
static inline bool drm_bridge_is_panel(const struct drm_bridge *bridge)
{
return false;
}
static inline int drm_panel_bridge_set_orientation(struct drm_connector *connector,
struct drm_bridge *bridge)
{
return -EINVAL;
}
#endif
#if defined(CONFIG_OF) && defined(CONFIG_DRM_PANEL_BRIDGE)

14
include/drm/drm_connector.h
View File

@@ -38,6 +38,7 @@ struct drm_modeset_acquire_ctx;
struct drm_device;
struct drm_crtc;
struct drm_encoder;
struct drm_panel;
struct drm_property;
struct drm_property_blob;
struct drm_printer;
@@ -318,8 +319,8 @@ enum drm_panel_orientation {
* EDID's detailed monitor range
*/
struct drm_monitor_range_info {
u8 min_vfreq;
u8 max_vfreq;
u16 min_vfreq;
u16 max_vfreq;
};
/**
@@ -1526,7 +1527,11 @@ struct drm_connector {
struct drm_cmdline_mode cmdline_mode;
/** @force: a DRM_FORCE_<foo> state for forced mode sets */
enum drm_connector_force force;
/** @override_edid: has the EDID been overwritten through debugfs for testing? */
/**
* @override_edid: has the EDID been overwritten through debugfs for
* testing? Do not modify outside of drm_edid_override_set() and
* drm_edid_override_reset().
*/
bool override_edid;
/** @epoch_counter: used to detect any other changes in connector, besides status */
u64 epoch_counter;
@@ -1802,6 +1807,9 @@ int drm_connector_set_panel_orientation_with_quirk(
struct drm_connector *connector,
enum drm_panel_orientation panel_orientation,
int width, int height);
int drm_connector_set_orientation_from_panel(
struct drm_connector *connector,
struct drm_panel *panel);
int drm_connector_attach_max_bpc_property(struct drm_connector *connector,
int min, int max);
void drm_connector_create_privacy_screen_properties(struct drm_connector *conn);

17
include/drm/drm_crtc.h
View File

@@ -25,37 +25,24 @@
#ifndef __DRM_CRTC_H__
#define __DRM_CRTC_H__
#include <linux/i2c.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <linux/fb.h>
#include <linux/hdmi.h>
#include <linux/media-bus-format.h>
#include <uapi/drm/drm_mode.h>
#include <uapi/drm/drm_fourcc.h>
#include <drm/drm_modeset_lock.h>
#include <drm/drm_rect.h>
#include <drm/drm_mode_object.h>
#include <drm/drm_framebuffer.h>
#include <drm/drm_modes.h>
#include <drm/drm_connector.h>
#include <drm/drm_device.h>
#include <drm/drm_property.h>
#include <drm/drm_edid.h>
#include <drm/drm_plane.h>
#include <drm/drm_blend.h>
#include <drm/drm_color_mgmt.h>
#include <drm/drm_debugfs_crc.h>
#include <drm/drm_mode_config.h>
struct drm_connector;
struct drm_device;
struct drm_framebuffer;
struct drm_mode_set;
struct drm_file;
struct drm_clip_rect;
struct drm_printer;
struct drm_self_refresh_data;
struct device_node;
struct dma_fence;
struct edid;
static inline int64_t U642I64(uint64_t val)

6
include/drm/drm_displayid.h
View File

@@ -25,7 +25,7 @@
#include <linux/types.h>
#include <linux/bits.h>
struct edid;
struct drm_edid;
#define VESA_IEEE_OUI 0x3a0292
@@ -141,7 +141,7 @@ struct displayid_vesa_vendor_specific_block {
/* DisplayID iteration */
struct displayid_iter {
const struct edid *edid;
const struct drm_edid *drm_edid;
const u8 *section;
int length;
@@ -149,7 +149,7 @@ struct displayid_iter {
int ext_index;
};
void displayid_iter_edid_begin(const struct edid *edid,
void displayid_iter_edid_begin(const struct drm_edid *drm_edid,
struct displayid_iter *iter);
const struct displayid_block *
__displayid_iter_next(struct displayid_iter *iter);

44
include/drm/drm_edid.h
View File

@@ -28,6 +28,7 @@
#include <drm/drm_mode.h>
struct drm_device;
struct drm_edid;
struct i2c_adapter;
#define EDID_LENGTH 128
@@ -91,6 +92,11 @@ struct detailed_data_string {
u8 str[13];
} __attribute__((packed));
#define DRM_EDID_RANGE_OFFSET_MIN_VFREQ (1 << 0) /* 1.4 */
#define DRM_EDID_RANGE_OFFSET_MAX_VFREQ (1 << 1) /* 1.4 */
#define DRM_EDID_RANGE_OFFSET_MIN_HFREQ (1 << 2) /* 1.4 */
#define DRM_EDID_RANGE_OFFSET_MAX_HFREQ (1 << 3) /* 1.4 */
#define DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG 0x00
#define DRM_EDID_RANGE_LIMITS_ONLY_FLAG 0x01
#define DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG 0x02
@@ -496,6 +502,22 @@ static inline u8 drm_eld_get_conn_type(const uint8_t *eld)
return eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_CONN_TYPE_MASK;
}
/**
* drm_edid_decode_mfg_id - Decode the manufacturer ID
* @mfg_id: The manufacturer ID
* @vend: A 4-byte buffer to store the 3-letter vendor string plus a '\0'
* termination
*/
static inline const char *drm_edid_decode_mfg_id(u16 mfg_id, char vend[4])
{
vend[0] = '@' + ((mfg_id >> 10) & 0x1f);
vend[1] = '@' + ((mfg_id >> 5) & 0x1f);
vend[2] = '@' + ((mfg_id >> 0) & 0x1f);
vend[3] = '\0';
return vend;
}
/**
* drm_edid_encode_panel_id - Encode an ID for matching against drm_edid_get_panel_id()
* @vend_chr_0: First character of the vendor string.
@@ -536,10 +558,7 @@ static inline u8 drm_eld_get_conn_type(const uint8_t *eld)
static inline void drm_edid_decode_panel_id(u32 panel_id, char vend[4], u16 *product_id)
{
*product_id = (u16)(panel_id & 0xffff);
vend[0] = '@' + ((panel_id >> 26) & 0x1f);
vend[1] = '@' + ((panel_id >> 21) & 0x1f);
vend[2] = '@' + ((panel_id >> 16) & 0x1f);
vend[3] = '\0';
drm_edid_decode_mfg_id(panel_id >> 16, vend);
}
bool drm_probe_ddc(struct i2c_adapter *adapter);
@@ -578,8 +597,21 @@ struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
struct drm_display_mode *
drm_display_mode_from_cea_vic(struct drm_device *dev,
u8 video_code);
const u8 *drm_find_edid_extension(const struct edid *edid,
/* Interface based on struct drm_edid */
const struct drm_edid *drm_edid_alloc(const void *edid, size_t size);
const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid);
void drm_edid_free(const struct drm_edid *drm_edid);
const struct edid *drm_edid_raw(const struct drm_edid *drm_edid);
const struct drm_edid *drm_edid_read(struct drm_connector *connector);
const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
struct i2c_adapter *adapter);
const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
int (*read_block)(void *context, u8 *buf, unsigned int block, size_t len),
void *context);
int drm_edid_connector_update(struct drm_connector *connector,
const struct drm_edid *edid);
const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid,
int ext_id, int *ext_index);
#endif /* __DRM_EDID_H__ */

2
include/drm/drm_encoder_slave.h
View File

@@ -27,6 +27,8 @@
#ifndef __DRM_ENCODER_SLAVE_H__
#define __DRM_ENCODER_SLAVE_H__
#include <linux/i2c.h>
#include <drm/drm_crtc.h>
#include <drm/drm_encoder.h>

1
include/drm/drm_fb_helper.h
View File

@@ -35,6 +35,7 @@ struct drm_fb_helper;
#include <drm/drm_client.h>
#include <drm/drm_crtc.h>
#include <drm/drm_device.h>
#include <linux/fb.h>
#include <linux/kgdb.h>
enum mode_set_atomic {

26
include/drm/drm_gem.h
View File

@@ -314,6 +314,23 @@ struct drm_gem_object {
const struct drm_gem_object_funcs *funcs;
};
/**
* DRM_GEM_FOPS - Default drm GEM file operations
*
* This macro provides a shorthand for setting the GEM file ops in the
* &file_operations structure. If all you need are the default ops, use
* DEFINE_DRM_GEM_FOPS instead.
*/
#define DRM_GEM_FOPS \
.open = drm_open,\
.release = drm_release,\
.unlocked_ioctl = drm_ioctl,\
.compat_ioctl = drm_compat_ioctl,\
.poll = drm_poll,\
.read = drm_read,\
.llseek = noop_llseek,\
.mmap = drm_gem_mmap
/**
* DEFINE_DRM_GEM_FOPS() - macro to generate file operations for GEM drivers
* @name: name for the generated structure
@@ -330,14 +347,7 @@ struct drm_gem_object {
#define DEFINE_DRM_GEM_FOPS(name) \
static const struct file_operations name = {\
.owner = THIS_MODULE,\
.open = drm_open,\
.release = drm_release,\
.unlocked_ioctl = drm_ioctl,\
.compat_ioctl = drm_compat_ioctl,\
.poll = drm_poll,\
.read = drm_read,\
.llseek = noop_llseek,\
.mmap = drm_gem_mmap,\
DRM_GEM_FOPS,\
}
void drm_gem_object_release(struct drm_gem_object *obj);

10
include/drm/drm_gem_framebuffer_helper.h
View File

@@ -4,8 +4,6 @@
#include <linux/dma-buf.h>
#include <linux/iosys-map.h>
#include <drm/drm_fourcc.h>
struct drm_afbc_framebuffer;
struct drm_device;
struct drm_fb_helper_surface_size;
@@ -39,11 +37,9 @@ struct drm_framebuffer *
drm_gem_fb_create_with_dirty(struct drm_device *dev, struct drm_file *file,
const struct drm_mode_fb_cmd2 *mode_cmd);
int drm_gem_fb_vmap(struct drm_framebuffer *fb,
struct iosys_map map[static DRM_FORMAT_MAX_PLANES],
struct iosys_map data[DRM_FORMAT_MAX_PLANES]);
void drm_gem_fb_vunmap(struct drm_framebuffer *fb,
struct iosys_map map[static DRM_FORMAT_MAX_PLANES]);
int drm_gem_fb_vmap(struct drm_framebuffer *fb, struct iosys_map *map,
struct iosys_map *data);
void drm_gem_fb_vunmap(struct drm_framebuffer *fb, struct iosys_map *map);
int drm_gem_fb_begin_cpu_access(struct drm_framebuffer *fb, enum dma_data_direction dir);
void drm_gem_fb_end_cpu_access(struct drm_framebuffer *fb, enum dma_data_direction dir);

17
include/drm/drm_mipi_dsi.h
View File

@@ -295,6 +295,23 @@ int mipi_dsi_dcs_set_display_brightness(struct mipi_dsi_device *dsi,
int mipi_dsi_dcs_get_display_brightness(struct mipi_dsi_device *dsi,
u16 *brightness);
/**
* mipi_dsi_dcs_write_seq - transmit a DCS command with payload
* @dsi: DSI peripheral device
* @cmd: Command
* @seq: buffer containing data to be transmitted
*/
#define mipi_dsi_dcs_write_seq(dsi, cmd, seq...) do { \
static const u8 d[] = { cmd, seq }; \
struct device *dev = &dsi->dev; \
int ret; \
ret = mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d)); \
if (ret < 0) { \
dev_err_ratelimited(dev, "sending command %#02x failed: %d\n", cmd, ret); \
return ret; \
} \
} while (0)
/**
* struct mipi_dsi_driver - DSI driver
* @driver: device driver model driver

22
include/drm/drm_of.h
View File

@@ -50,6 +50,12 @@ int drm_of_find_panel_or_bridge(const struct device_node *np,
int drm_of_lvds_get_dual_link_pixel_order(const struct device_node *port1,
const struct device_node *port2);
int drm_of_lvds_get_data_mapping(const struct device_node *port);
int drm_of_get_data_lanes_count(const struct device_node *endpoint,
const unsigned int min, const unsigned int max);
int drm_of_get_data_lanes_count_ep(const struct device_node *port,
int port_reg, int reg,
const unsigned int min,
const unsigned int max);
#else
static inline uint32_t drm_of_crtc_port_mask(struct drm_device *dev,
struct device_node *port)
@@ -105,6 +111,22 @@ drm_of_lvds_get_data_mapping(const struct device_node *port)
{
return -EINVAL;
}
static inline int
drm_of_get_data_lanes_count(const struct device_node *endpoint,
const unsigned int min, const unsigned int max)
{
return -EINVAL;
}
static inline int
drm_of_get_data_lanes_count_ep(const struct device_node *port,
int port_reg, int reg,
const unsigned int min,
const unsigned int max)
{
return -EINVAL;
}
#endif
/*

9
include/drm/drm_panel.h
View File

@@ -116,6 +116,15 @@ struct drm_panel_funcs {
int (*get_modes)(struct drm_panel *panel,
struct drm_connector *connector);
/**
* @get_orientation:
*
* Return the panel orientation set by device tree or EDID.
*
* This function is optional.
*/
enum drm_panel_orientation (*get_orientation)(struct drm_panel *panel);
/**
* @get_timings:
*

3
include/drm/drm_probe_helper.h
View File

@@ -26,4 +26,7 @@ void drm_kms_helper_poll_disable(struct drm_device *dev);
void drm_kms_helper_poll_enable(struct drm_device *dev);
bool drm_kms_helper_is_poll_worker(void);
int drm_connector_helper_get_modes_from_ddc(struct drm_connector *connector);
int drm_connector_helper_get_modes(struct drm_connector *connector);
#endif

16
include/drm/drm_rect.h
View File

@@ -47,6 +47,22 @@ struct drm_rect {
int x1, y1, x2, y2;
};
/**
* DRM_RECT_INIT - initialize a rectangle from x/y/w/h
* @x: x coordinate
* @y: y coordinate
* @w: width
* @h: height
*
* RETURNS:
* A new rectangle of the specified size.
*/
#define DRM_RECT_INIT(x, y, w, h) ((struct drm_rect){ \
.x1 = (x), \
.y1 = (y), \
.x2 = (x) + (w), \
.y2 = (y) + (h) })
/**
* DRM_RECT_FMT - printf string for &struct drm_rect
*/

39
include/drm/i915_pciids.h
View File

@@ -696,22 +696,55 @@
#define INTEL_DG2_G10_IDS(info) \
INTEL_VGA_DEVICE(0x5690, info), \
INTEL_VGA_DEVICE(0x5691, info), \
INTEL_VGA_DEVICE(0x5692, info)
INTEL_VGA_DEVICE(0x5692, info), \
INTEL_VGA_DEVICE(0x56A0, info), \
INTEL_VGA_DEVICE(0x56A1, info), \
INTEL_VGA_DEVICE(0x56A2, info)
#define INTEL_DG2_G11_IDS(info) \
INTEL_VGA_DEVICE(0x5693, info), \
INTEL_VGA_DEVICE(0x5694, info), \
INTEL_VGA_DEVICE(0x5695, info), \
INTEL_VGA_DEVICE(0x56B0, info)
INTEL_VGA_DEVICE(0x5698, info), \
INTEL_VGA_DEVICE(0x56A5, info), \
INTEL_VGA_DEVICE(0x56A6, info), \
INTEL_VGA_DEVICE(0x56B0, info), \
INTEL_VGA_DEVICE(0x56B1, info)
#define INTEL_DG2_G12_IDS(info) \
INTEL_VGA_DEVICE(0x5696, info), \
INTEL_VGA_DEVICE(0x5697, info), \
INTEL_VGA_DEVICE(0x56B2, info)
INTEL_VGA_DEVICE(0x56A3, info), \
INTEL_VGA_DEVICE(0x56A4, info), \
INTEL_VGA_DEVICE(0x56B2, info), \
INTEL_VGA_DEVICE(0x56B3, info)
#define INTEL_DG2_IDS(info) \
INTEL_DG2_G10_IDS(info), \
INTEL_DG2_G11_IDS(info), \
INTEL_DG2_G12_IDS(info)
#define INTEL_ATS_M150_IDS(info) \
INTEL_VGA_DEVICE(0x56C0, info)
#define INTEL_ATS_M75_IDS(info) \
INTEL_VGA_DEVICE(0x56C1, info)
#define INTEL_ATS_M_IDS(info) \
INTEL_ATS_M150_IDS(info), \
INTEL_ATS_M75_IDS(info)
/* MTL */
#define INTEL_MTL_M_IDS(info) \
INTEL_VGA_DEVICE(0x7D40, info), \
INTEL_VGA_DEVICE(0x7D60, info)
#define INTEL_MTL_P_IDS(info) \
INTEL_VGA_DEVICE(0x7D45, info), \
INTEL_VGA_DEVICE(0x7D55, info), \
INTEL_VGA_DEVICE(0x7DD5, info)
#define INTEL_MTL_IDS(info) \
INTEL_MTL_M_IDS(info), \
INTEL_MTL_P_IDS(info)
#endif /* _I915_PCIIDS_H */

24
include/drm/intel-gtt.h
View File

@@ -10,24 +10,24 @@ struct agp_bridge_data;
struct pci_dev;
struct sg_table;
void intel_gtt_get(u64 *gtt_total,
phys_addr_t *mappable_base,
resource_size_t *mappable_end);
void intel_gmch_gtt_get(u64 *gtt_total,
phys_addr_t *mappable_base,
resource_size_t *mappable_end);
int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
struct agp_bridge_data *bridge);
void intel_gmch_remove(void);
bool intel_enable_gtt(void);
bool intel_gmch_enable_gtt(void);
void intel_gtt_chipset_flush(void);
void intel_gtt_insert_page(dma_addr_t addr,
unsigned int pg,
unsigned int flags);
void intel_gtt_insert_sg_entries(struct sg_table *st,
unsigned int pg_start,
unsigned int flags);
void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries);
void intel_gmch_gtt_flush(void);
void intel_gmch_gtt_insert_page(dma_addr_t addr,
unsigned int pg,
unsigned int flags);
void intel_gmch_gtt_insert_sg_entries(struct sg_table *st,
unsigned int pg_start,
unsigned int flags);
void intel_gmch_gtt_clear_range(unsigned int first_entry, unsigned int num_entries);
/* Special gtt memory types */
#define AGP_DCACHE_MEMORY 1

10
include/dt-bindings/clock/bcm21664.h
View File

@@ -1,15 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2013 Broadcom Corporation
* Copyright 2013 Linaro Limited
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _CLOCK_BCM21664_H

10
include/dt-bindings/clock/bcm281xx.h
View File

@@ -1,15 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2013 Broadcom Corporation
* Copyright 2013 Linaro Limited
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _CLOCK_BCM281XX_H

43
include/dt-bindings/clock/efm32-cmu.h
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@@ -1,43 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __DT_BINDINGS_CLOCK_EFM32_CMU_H
#define __DT_BINDINGS_CLOCK_EFM32_CMU_H
#define clk_HFXO 0
#define clk_HFRCO 1
#define clk_LFXO 2
#define clk_LFRCO 3
#define clk_ULFRCO 4
#define clk_AUXHFRCO 5
#define clk_HFCLKNODIV 6
#define clk_HFCLK 7
#define clk_HFPERCLK 8
#define clk_HFCORECLK 9
#define clk_LFACLK 10
#define clk_LFBCLK 11
#define clk_WDOGCLK 12
#define clk_HFCORECLKDMA 13
#define clk_HFCORECLKAES 14
#define clk_HFCORECLKUSBC 15
#define clk_HFCORECLKUSB 16
#define clk_HFCORECLKLE 17
#define clk_HFCORECLKEBI 18
#define clk_HFPERCLKUSART0 19
#define clk_HFPERCLKUSART1 20
#define clk_HFPERCLKUSART2 21
#define clk_HFPERCLKUART0 22
#define clk_HFPERCLKUART1 23
#define clk_HFPERCLKTIMER0 24
#define clk_HFPERCLKTIMER1 25
#define clk_HFPERCLKTIMER2 26
#define clk_HFPERCLKTIMER3 27
#define clk_HFPERCLKACMP0 28
#define clk_HFPERCLKACMP1 29
#define clk_HFPERCLKI2C0 30
#define clk_HFPERCLKI2C1 31
#define clk_HFPERCLKGPIO 32
#define clk_HFPERCLKVCMP 33
#define clk_HFPERCLKPRS 34
#define clk_HFPERCLKADC0 35
#define clk_HFPERCLKDAC0 36
#endif /* __DT_BINDINGS_CLOCK_EFM32_CMU_H */

54
include/dt-bindings/clock/exynos7885.h
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@@ -54,17 +54,39 @@
#define CLK_GOUT_PERI_USI0 43
#define CLK_GOUT_PERI_USI1 44
#define CLK_GOUT_PERI_USI2 45
#define TOP_NR_CLK 46
#define CLK_MOUT_FSYS_BUS 46
#define CLK_MOUT_FSYS_MMC_CARD 47
#define CLK_MOUT_FSYS_MMC_EMBD 48
#define CLK_MOUT_FSYS_MMC_SDIO 49
#define CLK_MOUT_FSYS_USB30DRD 50
#define CLK_DOUT_FSYS_BUS 51
#define CLK_DOUT_FSYS_MMC_CARD 52
#define CLK_DOUT_FSYS_MMC_EMBD 53
#define CLK_DOUT_FSYS_MMC_SDIO 54
#define CLK_DOUT_FSYS_USB30DRD 55
#define CLK_GOUT_FSYS_BUS 56
#define CLK_GOUT_FSYS_MMC_CARD 57
#define CLK_GOUT_FSYS_MMC_EMBD 58
#define CLK_GOUT_FSYS_MMC_SDIO 59
#define CLK_GOUT_FSYS_USB30DRD 60
#define TOP_NR_CLK 61
/* CMU_CORE */
#define CLK_MOUT_CORE_BUS_USER 1
#define CLK_MOUT_CORE_CCI_USER 2
#define CLK_MOUT_CORE_G3D_USER 3
#define CLK_MOUT_CORE_GIC 4
#define CLK_DOUT_CORE_BUSP 5
#define CLK_GOUT_CCI_ACLK 6
#define CLK_GOUT_GIC400_CLK 7
#define CORE_NR_CLK 8
#define CLK_MOUT_CORE_BUS_USER 1
#define CLK_MOUT_CORE_CCI_USER 2
#define CLK_MOUT_CORE_G3D_USER 3
#define CLK_MOUT_CORE_GIC 4
#define CLK_DOUT_CORE_BUSP 5
#define CLK_GOUT_CCI_ACLK 6
#define CLK_GOUT_GIC400_CLK 7
#define CLK_GOUT_TREX_D_CORE_ACLK 8
#define CLK_GOUT_TREX_D_CORE_GCLK 9
#define CLK_GOUT_TREX_D_CORE_PCLK 10
#define CLK_GOUT_TREX_P_CORE_ACLK_P_CORE 11
#define CLK_GOUT_TREX_P_CORE_CCLK_P_CORE 12
#define CLK_GOUT_TREX_P_CORE_PCLK 13
#define CLK_GOUT_TREX_P_CORE_PCLK_P_CORE 14
#define CORE_NR_CLK 15
/* CMU_PERI */
#define CLK_MOUT_PERI_BUS_USER 1
@@ -112,4 +134,18 @@
#define CLK_GOUT_WDT1_PCLK 43
#define PERI_NR_CLK 44
/* CMU_FSYS */
#define CLK_MOUT_FSYS_BUS_USER 1
#define CLK_MOUT_FSYS_MMC_CARD_USER 2
#define CLK_MOUT_FSYS_MMC_EMBD_USER 3
#define CLK_MOUT_FSYS_MMC_SDIO_USER 4
#define CLK_MOUT_FSYS_USB30DRD_USER 4
#define CLK_GOUT_MMC_CARD_ACLK 5
#define CLK_GOUT_MMC_CARD_SDCLKIN 6
#define CLK_GOUT_MMC_EMBD_ACLK 7
#define CLK_GOUT_MMC_EMBD_SDCLKIN 8
#define CLK_GOUT_MMC_SDIO_ACLK 9
#define CLK_GOUT_MMC_SDIO_SDCLKIN 10
#define FSYS_NR_CLK 11
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */

49
include/dt-bindings/clock/nuvoton,npcm845-clk.h Normal file
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@@ -0,0 +1,49 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) 2021 Nuvoton Technologies.
* Author: Tomer Maimon <tomer.maimon@nuvoton.com>
*
* Device Tree binding constants for NPCM8XX clock controller.
*/
#ifndef __DT_BINDINGS_CLOCK_NPCM8XX_H
#define __DT_BINDINGS_CLOCK_NPCM8XX_H
#define NPCM8XX_CLK_CPU 0
#define NPCM8XX_CLK_GFX_PIXEL 1
#define NPCM8XX_CLK_MC 2
#define NPCM8XX_CLK_ADC 3
#define NPCM8XX_CLK_AHB 4
#define NPCM8XX_CLK_TIMER 5
#define NPCM8XX_CLK_UART 6
#define NPCM8XX_CLK_UART2 7
#define NPCM8XX_CLK_MMC 8
#define NPCM8XX_CLK_SPI3 9
#define NPCM8XX_CLK_PCI 10
#define NPCM8XX_CLK_AXI 11
#define NPCM8XX_CLK_APB4 12
#define NPCM8XX_CLK_APB3 13
#define NPCM8XX_CLK_APB2 14
#define NPCM8XX_CLK_APB1 15
#define NPCM8XX_CLK_APB5 16
#define NPCM8XX_CLK_CLKOUT 17
#define NPCM8XX_CLK_GFX 18
#define NPCM8XX_CLK_SU 19
#define NPCM8XX_CLK_SU48 20
#define NPCM8XX_CLK_SDHC 21
#define NPCM8XX_CLK_SPI0 22
#define NPCM8XX_CLK_SPI1 23
#define NPCM8XX_CLK_SPIX 24
#define NPCM8XX_CLK_RG 25
#define NPCM8XX_CLK_RCP 26
#define NPCM8XX_CLK_PRE_ADC 27
#define NPCM8XX_CLK_ATB 28
#define NPCM8XX_CLK_PRE_CLK 29
#define NPCM8XX_CLK_TH 30
#define NPCM8XX_CLK_REFCLK 31
#define NPCM8XX_CLK_SYSBYPCK 32
#define NPCM8XX_CLK_MCBYPCK 33
#define NPCM8XX_NUM_CLOCKS (NPCM8XX_CLK_MCBYPCK + 1)
#endif

1
include/dt-bindings/clock/qcom,dispcc-sm8350.h Symbolic link
View File

@@ -0,0 +1 @@
qcom,dispcc-sm8250.h

4
include/dt-bindings/clock/qcom,gcc-ipq8074.h
View File

@@ -233,6 +233,7 @@
#define GCC_PCIE0_AXI_S_BRIDGE_CLK 224
#define GCC_PCIE0_RCHNG_CLK_SRC 225
#define GCC_PCIE0_RCHNG_CLK 226
#define GCC_CRYPTO_PPE_CLK 227
#define GCC_BLSP1_BCR 0
#define GCC_BLSP1_QUP1_BCR 1
@@ -367,4 +368,7 @@
#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130
#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131
#define USB0_GDSC 0
#define USB1_GDSC 1
#endif

1
include/dt-bindings/clock/qcom,gcc-msm8939.h
View File

@@ -192,6 +192,7 @@
#define GCC_VENUS0_CORE0_VCODEC0_CLK 183
#define GCC_VENUS0_CORE1_VCODEC0_CLK 184
#define GCC_OXILI_TIMER_CLK 185
#define SYSTEM_MM_NOC_BFDCD_CLK_SRC 186
/* Indexes for GDSCs */
#define BIMC_GDSC 0

52
include/dt-bindings/clock/qcom,gpucc-sm8350.h Normal file
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@@ -0,0 +1,52 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2022, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H
/* GPU_CC clocks */
#define GPU_CC_AHB_CLK 0
#define GPU_CC_CB_CLK 1
#define GPU_CC_CRC_AHB_CLK 2
#define GPU_CC_CX_APB_CLK 3
#define GPU_CC_CX_GMU_CLK 4
#define GPU_CC_CX_QDSS_AT_CLK 5
#define GPU_CC_CX_QDSS_TRIG_CLK 6
#define GPU_CC_CX_QDSS_TSCTR_CLK 7
#define GPU_CC_CX_SNOC_DVM_CLK 8
#define GPU_CC_CXO_AON_CLK 9
#define GPU_CC_CXO_CLK 10
#define GPU_CC_FREQ_MEASURE_CLK 11
#define GPU_CC_GMU_CLK_SRC 12
#define GPU_CC_GX_GMU_CLK 13
#define GPU_CC_GX_QDSS_TSCTR_CLK 14
#define GPU_CC_GX_VSENSE_CLK 15
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16
#define GPU_CC_HUB_AHB_DIV_CLK_SRC 17
#define GPU_CC_HUB_AON_CLK 18
#define GPU_CC_HUB_CLK_SRC 19
#define GPU_CC_HUB_CX_INT_CLK 20
#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 21
#define GPU_CC_MND1X_0_GFX3D_CLK 22
#define GPU_CC_MND1X_1_GFX3D_CLK 23
#define GPU_CC_PLL0 24
#define GPU_CC_PLL1 25
#define GPU_CC_SLEEP_CLK 26
/* GPU_CC resets */
#define GPUCC_GPU_CC_ACD_BCR 0
#define GPUCC_GPU_CC_CB_BCR 1
#define GPUCC_GPU_CC_CX_BCR 2
#define GPUCC_GPU_CC_FAST_HUB_BCR 3
#define GPUCC_GPU_CC_GFX3D_AON_BCR 4
#define GPUCC_GPU_CC_GMU_BCR 5
#define GPUCC_GPU_CC_GX_BCR 6
#define GPUCC_GPU_CC_XO_BCR 7
/* GPU_CC GDSCRs */
#define GPU_CX_GDSC 0
#define GPU_GX_GDSC 1
#endif

159
include/dt-bindings/clock/qcom,sm8450-camcc.h Normal file
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@@ -0,0 +1,159 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8450_H
#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8450_H
/* CAM_CC clocks */
#define CAM_CC_BPS_AHB_CLK 0
#define CAM_CC_BPS_CLK 1
#define CAM_CC_BPS_CLK_SRC 2
#define CAM_CC_BPS_FAST_AHB_CLK 3
#define CAM_CC_CAMNOC_AXI_CLK 4
#define CAM_CC_CAMNOC_AXI_CLK_SRC 5
#define CAM_CC_CAMNOC_DCD_XO_CLK 6
#define CAM_CC_CCI_0_CLK 7
#define CAM_CC_CCI_0_CLK_SRC 8
#define CAM_CC_CCI_1_CLK 9
#define CAM_CC_CCI_1_CLK_SRC 10
#define CAM_CC_CORE_AHB_CLK 11
#define CAM_CC_CPAS_AHB_CLK 12
#define CAM_CC_CPAS_BPS_CLK 13
#define CAM_CC_CPAS_FAST_AHB_CLK 14
#define CAM_CC_CPAS_IFE_0_CLK 15
#define CAM_CC_CPAS_IFE_1_CLK 16
#define CAM_CC_CPAS_IFE_2_CLK 17
#define CAM_CC_CPAS_IFE_LITE_CLK 18
#define CAM_CC_CPAS_IPE_NPS_CLK 19
#define CAM_CC_CPAS_SBI_CLK 20
#define CAM_CC_CPAS_SFE_0_CLK 21
#define CAM_CC_CPAS_SFE_1_CLK 22
#define CAM_CC_CPHY_RX_CLK_SRC 23
#define CAM_CC_CSI0PHYTIMER_CLK 24
#define CAM_CC_CSI0PHYTIMER_CLK_SRC 25
#define CAM_CC_CSI1PHYTIMER_CLK 26
#define CAM_CC_CSI1PHYTIMER_CLK_SRC 27
#define CAM_CC_CSI2PHYTIMER_CLK 28
#define CAM_CC_CSI2PHYTIMER_CLK_SRC 29
#define CAM_CC_CSI3PHYTIMER_CLK 30
#define CAM_CC_CSI3PHYTIMER_CLK_SRC 31
#define CAM_CC_CSI4PHYTIMER_CLK 32
#define CAM_CC_CSI4PHYTIMER_CLK_SRC 33
#define CAM_CC_CSI5PHYTIMER_CLK 34
#define CAM_CC_CSI5PHYTIMER_CLK_SRC 35
#define CAM_CC_CSID_CLK 36
#define CAM_CC_CSID_CLK_SRC 37
#define CAM_CC_CSID_CSIPHY_RX_CLK 38
#define CAM_CC_CSIPHY0_CLK 39
#define CAM_CC_CSIPHY1_CLK 40
#define CAM_CC_CSIPHY2_CLK 41
#define CAM_CC_CSIPHY3_CLK 42
#define CAM_CC_CSIPHY4_CLK 43
#define CAM_CC_CSIPHY5_CLK 44
#define CAM_CC_FAST_AHB_CLK_SRC 45
#define CAM_CC_GDSC_CLK 46
#define CAM_CC_ICP_AHB_CLK 47
#define CAM_CC_ICP_CLK 48
#define CAM_CC_ICP_CLK_SRC 49
#define CAM_CC_IFE_0_CLK 50
#define CAM_CC_IFE_0_CLK_SRC 51
#define CAM_CC_IFE_0_DSP_CLK 52
#define CAM_CC_IFE_0_FAST_AHB_CLK 53
#define CAM_CC_IFE_1_CLK 54
#define CAM_CC_IFE_1_CLK_SRC 55
#define CAM_CC_IFE_1_DSP_CLK 56
#define CAM_CC_IFE_1_FAST_AHB_CLK 57
#define CAM_CC_IFE_2_CLK 58
#define CAM_CC_IFE_2_CLK_SRC 59
#define CAM_CC_IFE_2_DSP_CLK 60
#define CAM_CC_IFE_2_FAST_AHB_CLK 61
#define CAM_CC_IFE_LITE_AHB_CLK 62
#define CAM_CC_IFE_LITE_CLK 63
#define CAM_CC_IFE_LITE_CLK_SRC 64
#define CAM_CC_IFE_LITE_CPHY_RX_CLK 65
#define CAM_CC_IFE_LITE_CSID_CLK 66
#define CAM_CC_IFE_LITE_CSID_CLK_SRC 67
#define CAM_CC_IPE_NPS_AHB_CLK 68
#define CAM_CC_IPE_NPS_CLK 69
#define CAM_CC_IPE_NPS_CLK_SRC 70
#define CAM_CC_IPE_NPS_FAST_AHB_CLK 71
#define CAM_CC_IPE_PPS_CLK 72
#define CAM_CC_IPE_PPS_FAST_AHB_CLK 73
#define CAM_CC_JPEG_CLK 74
#define CAM_CC_JPEG_CLK_SRC 75
#define CAM_CC_MCLK0_CLK 76
#define CAM_CC_MCLK0_CLK_SRC 77
#define CAM_CC_MCLK1_CLK 78
#define CAM_CC_MCLK1_CLK_SRC 79
#define CAM_CC_MCLK2_CLK 80
#define CAM_CC_MCLK2_CLK_SRC 81
#define CAM_CC_MCLK3_CLK 82
#define CAM_CC_MCLK3_CLK_SRC 83
#define CAM_CC_MCLK4_CLK 84
#define CAM_CC_MCLK4_CLK_SRC 85
#define CAM_CC_MCLK5_CLK 86
#define CAM_CC_MCLK5_CLK_SRC 87
#define CAM_CC_MCLK6_CLK 88
#define CAM_CC_MCLK6_CLK_SRC 89
#define CAM_CC_MCLK7_CLK 90
#define CAM_CC_MCLK7_CLK_SRC 91
#define CAM_CC_PLL0 92
#define CAM_CC_PLL0_OUT_EVEN 93
#define CAM_CC_PLL0_OUT_ODD 94
#define CAM_CC_PLL1 95
#define CAM_CC_PLL1_OUT_EVEN 96
#define CAM_CC_PLL2 97
#define CAM_CC_PLL3 98
#define CAM_CC_PLL3_OUT_EVEN 99
#define CAM_CC_PLL4 100
#define CAM_CC_PLL4_OUT_EVEN 101
#define CAM_CC_PLL5 102
#define CAM_CC_PLL5_OUT_EVEN 103
#define CAM_CC_PLL6 104
#define CAM_CC_PLL6_OUT_EVEN 105
#define CAM_CC_PLL7 106
#define CAM_CC_PLL7_OUT_EVEN 107
#define CAM_CC_PLL8 108
#define CAM_CC_PLL8_OUT_EVEN 109
#define CAM_CC_QDSS_DEBUG_CLK 110
#define CAM_CC_QDSS_DEBUG_CLK_SRC 111
#define CAM_CC_QDSS_DEBUG_XO_CLK 112
#define CAM_CC_SBI_AHB_CLK 113
#define CAM_CC_SBI_CLK 114
#define CAM_CC_SFE_0_CLK 115
#define CAM_CC_SFE_0_CLK_SRC 116
#define CAM_CC_SFE_0_FAST_AHB_CLK 117
#define CAM_CC_SFE_1_CLK 118
#define CAM_CC_SFE_1_CLK_SRC 119
#define CAM_CC_SFE_1_FAST_AHB_CLK 120
#define CAM_CC_SLEEP_CLK 121
#define CAM_CC_SLEEP_CLK_SRC 122
#define CAM_CC_SLOW_AHB_CLK_SRC 123
#define CAM_CC_XO_CLK_SRC 124
/* CAM_CC resets */
#define CAM_CC_BPS_BCR 0
#define CAM_CC_ICP_BCR 1
#define CAM_CC_IFE_0_BCR 2
#define CAM_CC_IFE_1_BCR 3
#define CAM_CC_IFE_2_BCR 4
#define CAM_CC_IPE_0_BCR 5
#define CAM_CC_QDSS_DEBUG_BCR 6
#define CAM_CC_SBI_BCR 7
#define CAM_CC_SFE_0_BCR 8
#define CAM_CC_SFE_1_BCR 9
/* CAM_CC GDSCRs */
#define BPS_GDSC 0
#define IPE_0_GDSC 1
#define SBI_GDSC 2
#define IFE_0_GDSC 3
#define IFE_1_GDSC 4
#define IFE_2_GDSC 5
#define SFE_0_GDSC 6
#define SFE_1_GDSC 7
#define TITAN_TOP_GDSC 8
#endif

20
include/dt-bindings/clock/r9a07g043-cpg.h
View File

@@ -108,6 +108,15 @@
#define R9A07G043_ADC_ADCLK 76
#define R9A07G043_ADC_PCLK 77
#define R9A07G043_TSU_PCLK 78
#define R9A07G043_NCEPLDM_DM_CLK 79 /* RZ/Five Only */
#define R9A07G043_NCEPLDM_ACLK 80 /* RZ/Five Only */
#define R9A07G043_NCEPLDM_TCK 81 /* RZ/Five Only */
#define R9A07G043_NCEPLMT_ACLK 82 /* RZ/Five Only */
#define R9A07G043_NCEPLIC_ACLK 83 /* RZ/Five Only */
#define R9A07G043_AX45MP_CORE0_CLK 84 /* RZ/Five Only */
#define R9A07G043_AX45MP_ACLK 85 /* RZ/Five Only */
#define R9A07G043_IAX45_CLK 86 /* RZ/Five Only */
#define R9A07G043_IAX45_PCLK 87 /* RZ/Five Only */
/* R9A07G043 Resets */
#define R9A07G043_CA55_RST_1_0 0 /* RZ/G2UL Only */
@@ -180,5 +189,16 @@
#define R9A07G043_ADC_PRESETN 67
#define R9A07G043_ADC_ADRST_N 68
#define R9A07G043_TSU_PRESETN 69
#define R9A07G043_NCEPLDM_DTM_PWR_RST_N 70 /* RZ/Five Only */
#define R9A07G043_NCEPLDM_ARESETN 71 /* RZ/Five Only */
#define R9A07G043_NCEPLMT_POR_RSTN 72 /* RZ/Five Only */
#define R9A07G043_NCEPLMT_ARESETN 73 /* RZ/Five Only */
#define R9A07G043_NCEPLIC_ARESETN 74 /* RZ/Five Only */
#define R9A07G043_AX45MP_ARESETNM 75 /* RZ/Five Only */
#define R9A07G043_AX45MP_ARESETNS 76 /* RZ/Five Only */
#define R9A07G043_AX45MP_L2_RESETN 77 /* RZ/Five Only */
#define R9A07G043_AX45MP_CORE0_RESETN 78 /* RZ/Five Only */
#define R9A07G043_IAX45_RESETN 79 /* RZ/Five Only */
#endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */

397
include/dt-bindings/clock/sprd,ums512-clk.h Normal file
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@@ -0,0 +1,397 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Unisoc UMS512 SoC DTS file
*
* Copyright (C) 2022, Unisoc Inc.
*/
#ifndef _DT_BINDINGS_CLK_UMS512_H_
#define _DT_BINDINGS_CLK_UMS512_H_
#define CLK_26M_AUD 0
#define CLK_13M 1
#define CLK_6M5 2
#define CLK_4M3 3
#define CLK_2M 4
#define CLK_1M 5
#define CLK_250K 6
#define CLK_RCO_25M 7
#define CLK_RCO_4M 8
#define CLK_RCO_2M 9
#define CLK_ISPPLL_GATE 10
#define CLK_DPLL0_GATE 11
#define CLK_DPLL1_GATE 12
#define CLK_LPLL_GATE 13
#define CLK_TWPLL_GATE 14
#define CLK_GPLL_GATE 15
#define CLK_RPLL_GATE 16
#define CLK_CPPLL_GATE 17
#define CLK_MPLL0_GATE 18
#define CLK_MPLL1_GATE 19
#define CLK_MPLL2_GATE 20
#define CLK_PMU_GATE_NUM (CLK_MPLL2_GATE + 1)
#define CLK_DPLL0 0
#define CLK_DPLL0_58M31 1
#define CLK_ANLG_PHY_G0_NUM (CLK_DPLL0_58M31 + 1)
#define CLK_MPLL1 0
#define CLK_MPLL1_63M38 1
#define CLK_ANLG_PHY_G2_NUM (CLK_MPLL1_63M38 + 1)
#define CLK_RPLL 0
#define CLK_AUDIO_GATE 1
#define CLK_MPLL0 2
#define CLK_MPLL0_56M88 3
#define CLK_MPLL2 4
#define CLK_MPLL2_47M13 5
#define CLK_ANLG_PHY_G3_NUM (CLK_MPLL2_47M13 + 1)
#define CLK_TWPLL 0
#define CLK_TWPLL_768M 1
#define CLK_TWPLL_384M 2
#define CLK_TWPLL_192M 3
#define CLK_TWPLL_96M 4
#define CLK_TWPLL_48M 5
#define CLK_TWPLL_24M 6
#define CLK_TWPLL_12M 7
#define CLK_TWPLL_512M 8
#define CLK_TWPLL_256M 9
#define CLK_TWPLL_128M 10
#define CLK_TWPLL_64M 11
#define CLK_TWPLL_307M2 12
#define CLK_TWPLL_219M4 13
#define CLK_TWPLL_170M6 14
#define CLK_TWPLL_153M6 15
#define CLK_TWPLL_76M8 16
#define CLK_TWPLL_51M2 17
#define CLK_TWPLL_38M4 18
#define CLK_TWPLL_19M2 19
#define CLK_TWPLL_12M29 20
#define CLK_LPLL 21
#define CLK_LPLL_614M4 22
#define CLK_LPLL_409M6 23
#define CLK_LPLL_245M76 24
#define CLK_LPLL_30M72 25
#define CLK_ISPPLL 26
#define CLK_ISPPLL_468M 27
#define CLK_ISPPLL_78M 28
#define CLK_GPLL 29
#define CLK_GPLL_40M 30
#define CLK_CPPLL 31
#define CLK_CPPLL_39M32 32
#define CLK_ANLG_PHY_GC_NUM (CLK_CPPLL_39M32 + 1)
#define CLK_AP_APB 0
#define CLK_IPI 1
#define CLK_AP_UART0 2
#define CLK_AP_UART1 3
#define CLK_AP_UART2 4
#define CLK_AP_I2C0 5
#define CLK_AP_I2C1 6
#define CLK_AP_I2C2 7
#define CLK_AP_I2C3 8
#define CLK_AP_I2C4 9
#define CLK_AP_SPI0 10
#define CLK_AP_SPI1 11
#define CLK_AP_SPI2 12
#define CLK_AP_SPI3 13
#define CLK_AP_IIS0 14
#define CLK_AP_IIS1 15
#define CLK_AP_IIS2 16
#define CLK_AP_SIM 17
#define CLK_AP_CE 18
#define CLK_SDIO0_2X 19
#define CLK_SDIO1_2X 20
#define CLK_EMMC_2X 21
#define CLK_VSP 22
#define CLK_DISPC0 23
#define CLK_DISPC0_DPI 24
#define CLK_DSI_APB 25
#define CLK_DSI_RXESC 26
#define CLK_DSI_LANEBYTE 27
#define CLK_VDSP 28
#define CLK_VDSP_M 29
#define CLK_AP_CLK_NUM (CLK_VDSP_M + 1)
#define CLK_DSI_EB 0
#define CLK_DISPC_EB 1
#define CLK_VSP_EB 2
#define CLK_VDMA_EB 3
#define CLK_DMA_PUB_EB 4
#define CLK_DMA_SEC_EB 5
#define CLK_IPI_EB 6
#define CLK_AHB_CKG_EB 7
#define CLK_BM_CLK_EB 8
#define CLK_AP_AHB_GATE_NUM (CLK_BM_CLK_EB + 1)
#define CLK_AON_APB 0
#define CLK_ADI 1
#define CLK_AUX0 2
#define CLK_AUX1 3
#define CLK_AUX2 4
#define CLK_PROBE 5
#define CLK_PWM0 6
#define CLK_PWM1 7
#define CLK_PWM2 8
#define CLK_PWM3 9
#define CLK_EFUSE 10
#define CLK_UART0 11
#define CLK_UART1 12
#define CLK_THM0 13
#define CLK_THM1 14
#define CLK_THM2 15
#define CLK_THM3 16
#define CLK_AON_I2C 17
#define CLK_AON_IIS 18
#define CLK_SCC 19
#define CLK_APCPU_DAP 20
#define CLK_APCPU_DAP_MTCK 21
#define CLK_APCPU_TS 22
#define CLK_DEBUG_TS 23
#define CLK_DSI_TEST_S 24
#define CLK_DJTAG_TCK 25
#define CLK_DJTAG_TCK_HW 26
#define CLK_AON_TMR 27
#define CLK_AON_PMU 28
#define CLK_DEBOUNCE 29
#define CLK_APCPU_PMU 30
#define CLK_TOP_DVFS 31
#define CLK_OTG_UTMI 32
#define CLK_OTG_REF 33
#define CLK_CSSYS 34
#define CLK_CSSYS_PUB 35
#define CLK_CSSYS_APB 36
#define CLK_AP_AXI 37
#define CLK_AP_MM 38
#define CLK_SDIO2_2X 39
#define CLK_ANALOG_IO_APB 40
#define CLK_DMC_REF_CLK 41
#define CLK_EMC 42
#define CLK_USB 43
#define CLK_26M_PMU 44
#define CLK_AON_APB_NUM (CLK_26M_PMU + 1)
#define CLK_MM_AHB 0
#define CLK_MM_MTX 1
#define CLK_SENSOR0 2
#define CLK_SENSOR1 3
#define CLK_SENSOR2 4
#define CLK_CPP 5
#define CLK_JPG 6
#define CLK_FD 7
#define CLK_DCAM_IF 8
#define CLK_DCAM_AXI 9
#define CLK_ISP 10
#define CLK_MIPI_CSI0 11
#define CLK_MIPI_CSI1 12
#define CLK_MIPI_CSI2 13
#define CLK_MM_CLK_NUM (CLK_MIPI_CSI2 + 1)
#define CLK_RC100M_CAL_EB 0
#define CLK_DJTAG_TCK_EB 1
#define CLK_DJTAG_EB 2
#define CLK_AUX0_EB 3
#define CLK_AUX1_EB 4
#define CLK_AUX2_EB 5
#define CLK_PROBE_EB 6
#define CLK_MM_EB 7
#define CLK_GPU_EB 8
#define CLK_MSPI_EB 9
#define CLK_APCPU_DAP_EB 10
#define CLK_AON_CSSYS_EB 11
#define CLK_CSSYS_APB_EB 12
#define CLK_CSSYS_PUB_EB 13
#define CLK_SDPHY_CFG_EB 14
#define CLK_SDPHY_REF_EB 15
#define CLK_EFUSE_EB 16
#define CLK_GPIO_EB 17
#define CLK_MBOX_EB 18
#define CLK_KPD_EB 19
#define CLK_AON_SYST_EB 20
#define CLK_AP_SYST_EB 21
#define CLK_AON_TMR_EB 22
#define CLK_OTG_UTMI_EB 23
#define CLK_OTG_PHY_EB 24
#define CLK_SPLK_EB 25
#define CLK_PIN_EB 26
#define CLK_ANA_EB 27
#define CLK_APCPU_TS0_EB 28
#define CLK_APB_BUSMON_EB 29
#define CLK_AON_IIS_EB 30
#define CLK_SCC_EB 31
#define CLK_THM0_EB 32
#define CLK_THM1_EB 33
#define CLK_THM2_EB 34
#define CLK_ASIM_TOP_EB 35
#define CLK_I2C_EB 36
#define CLK_PMU_EB 37
#define CLK_ADI_EB 38
#define CLK_EIC_EB 39
#define CLK_AP_INTC0_EB 40
#define CLK_AP_INTC1_EB 41
#define CLK_AP_INTC2_EB 42
#define CLK_AP_INTC3_EB 43
#define CLK_AP_INTC4_EB 44
#define CLK_AP_INTC5_EB 45
#define CLK_AUDCP_INTC_EB 46
#define CLK_AP_TMR0_EB 47
#define CLK_AP_TMR1_EB 48
#define CLK_AP_TMR2_EB 49
#define CLK_PWM0_EB 50
#define CLK_PWM1_EB 51
#define CLK_PWM2_EB 52
#define CLK_PWM3_EB 53
#define CLK_AP_WDG_EB 54
#define CLK_APCPU_WDG_EB 55
#define CLK_SERDES_EB 56
#define CLK_ARCH_RTC_EB 57
#define CLK_KPD_RTC_EB 58
#define CLK_AON_SYST_RTC_EB 59
#define CLK_AP_SYST_RTC_EB 60
#define CLK_AON_TMR_RTC_EB 61
#define CLK_EIC_RTC_EB 62
#define CLK_EIC_RTCDV5_EB 63
#define CLK_AP_WDG_RTC_EB 64
#define CLK_AC_WDG_RTC_EB 65
#define CLK_AP_TMR0_RTC_EB 66
#define CLK_AP_TMR1_RTC_EB 67
#define CLK_AP_TMR2_RTC_EB 68
#define CLK_DCXO_LC_RTC_EB 69
#define CLK_BB_CAL_RTC_EB 70
#define CLK_AP_EMMC_RTC_EB 71
#define CLK_AP_SDIO0_RTC_EB 72
#define CLK_AP_SDIO1_RTC_EB 73
#define CLK_AP_SDIO2_RTC_EB 74
#define CLK_DSI_CSI_TEST_EB 75
#define CLK_DJTAG_TCK_EN 76
#define CLK_DPHY_REF_EB 77
#define CLK_DMC_REF_EB 78
#define CLK_OTG_REF_EB 79
#define CLK_TSEN_EB 80
#define CLK_TMR_EB 81
#define CLK_RC100M_REF_EB 82
#define CLK_RC100M_FDK_EB 83
#define CLK_DEBOUNCE_EB 84
#define CLK_DET_32K_EB 85
#define CLK_TOP_CSSYS_EB 86
#define CLK_AP_AXI_EN 87
#define CLK_SDIO0_2X_EN 88
#define CLK_SDIO0_1X_EN 89
#define CLK_SDIO1_2X_EN 90
#define CLK_SDIO1_1X_EN 91
#define CLK_SDIO2_2X_EN 92
#define CLK_SDIO2_1X_EN 93
#define CLK_EMMC_2X_EN 94
#define CLK_EMMC_1X_EN 95
#define CLK_PLL_TEST_EN 96
#define CLK_CPHY_CFG_EN 97
#define CLK_DEBUG_TS_EN 98
#define CLK_ACCESS_AUD_EN 99
#define CLK_AON_APB_GATE_NUM (CLK_ACCESS_AUD_EN + 1)
#define CLK_MM_CPP_EB 0
#define CLK_MM_JPG_EB 1
#define CLK_MM_DCAM_EB 2
#define CLK_MM_ISP_EB 3
#define CLK_MM_CSI2_EB 4
#define CLK_MM_CSI1_EB 5
#define CLK_MM_CSI0_EB 6
#define CLK_MM_CKG_EB 7
#define CLK_ISP_AHB_EB 8
#define CLK_MM_DVFS_EB 9
#define CLK_MM_FD_EB 10
#define CLK_MM_SENSOR2_EB 11
#define CLK_MM_SENSOR1_EB 12
#define CLK_MM_SENSOR0_EB 13
#define CLK_MM_MIPI_CSI2_EB 14
#define CLK_MM_MIPI_CSI1_EB 15
#define CLK_MM_MIPI_CSI0_EB 16
#define CLK_DCAM_AXI_EB 17
#define CLK_ISP_AXI_EB 18
#define CLK_MM_CPHY_EB 19
#define CLK_MM_GATE_CLK_NUM (CLK_MM_CPHY_EB + 1)
#define CLK_SIM0_EB 0
#define CLK_IIS0_EB 1
#define CLK_IIS1_EB 2
#define CLK_IIS2_EB 3
#define CLK_APB_REG_EB 4
#define CLK_SPI0_EB 5
#define CLK_SPI1_EB 6
#define CLK_SPI2_EB 7
#define CLK_SPI3_EB 8
#define CLK_I2C0_EB 9
#define CLK_I2C1_EB 10
#define CLK_I2C2_EB 11
#define CLK_I2C3_EB 12
#define CLK_I2C4_EB 13
#define CLK_UART0_EB 14
#define CLK_UART1_EB 15
#define CLK_UART2_EB 16
#define CLK_SIM0_32K_EB 17
#define CLK_SPI0_LFIN_EB 18
#define CLK_SPI1_LFIN_EB 19
#define CLK_SPI2_LFIN_EB 20
#define CLK_SPI3_LFIN_EB 21
#define CLK_SDIO0_EB 22
#define CLK_SDIO1_EB 23
#define CLK_SDIO2_EB 24
#define CLK_EMMC_EB 25
#define CLK_SDIO0_32K_EB 26
#define CLK_SDIO1_32K_EB 27
#define CLK_SDIO2_32K_EB 28
#define CLK_EMMC_32K_EB 29
#define CLK_AP_APB_GATE_NUM (CLK_EMMC_32K_EB + 1)
#define CLK_GPU_CORE_EB 0
#define CLK_GPU_CORE 1
#define CLK_GPU_MEM_EB 2
#define CLK_GPU_MEM 3
#define CLK_GPU_SYS_EB 4
#define CLK_GPU_SYS 5
#define CLK_GPU_CLK_NUM (CLK_GPU_SYS + 1)
#define CLK_AUDCP_IIS0_EB 0
#define CLK_AUDCP_IIS1_EB 1
#define CLK_AUDCP_IIS2_EB 2
#define CLK_AUDCP_UART_EB 3
#define CLK_AUDCP_DMA_CP_EB 4
#define CLK_AUDCP_DMA_AP_EB 5
#define CLK_AUDCP_SRC48K_EB 6
#define CLK_AUDCP_MCDT_EB 7
#define CLK_AUDCP_VBCIFD_EB 8
#define CLK_AUDCP_VBC_EB 9
#define CLK_AUDCP_SPLK_EB 10
#define CLK_AUDCP_ICU_EB 11
#define CLK_AUDCP_DMA_AP_ASHB_EB 12
#define CLK_AUDCP_DMA_CP_ASHB_EB 13
#define CLK_AUDCP_AUD_EB 14
#define CLK_AUDCP_VBC_24M_EB 15
#define CLK_AUDCP_TMR_26M_EB 16
#define CLK_AUDCP_DVFS_ASHB_EB 17
#define CLK_AUDCP_AHB_GATE_NUM (CLK_AUDCP_DVFS_ASHB_EB + 1)
#define CLK_AUDCP_WDG_EB 0
#define CLK_AUDCP_RTC_WDG_EB 1
#define CLK_AUDCP_TMR0_EB 2
#define CLK_AUDCP_TMR1_EB 3
#define CLK_AUDCP_APB_GATE_NUM (CLK_AUDCP_TMR1_EB + 1)
#define CLK_ACORE0 0
#define CLK_ACORE1 1
#define CLK_ACORE2 2
#define CLK_ACORE3 3
#define CLK_ACORE4 4
#define CLK_ACORE5 5
#define CLK_PCORE0 6
#define CLK_PCORE1 7
#define CLK_SCU 8
#define CLK_ACE 9
#define CLK_PERIPH 10
#define CLK_GIC 11
#define CLK_ATB 12
#define CLK_DEBUG_APB 13
#define CLK_APCPU_SEC_NUM (CLK_DEBUG_APB + 1)
#endif /* _DT_BINDINGS_CLK_UMS512_H_ */

88
include/dt-bindings/clock/sunplus,sp7021-clkc.h Normal file
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@@ -0,0 +1,88 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) Sunplus Technology Co., Ltd.
* All rights reserved.
*/
#ifndef _DT_BINDINGS_CLOCK_SUNPLUS_SP7021_H
#define _DT_BINDINGS_CLOCK_SUNPLUS_SP7021_H
/* gates */
#define CLK_RTC 0
#define CLK_OTPRX 1
#define CLK_NOC 2
#define CLK_BR 3
#define CLK_SPIFL 4
#define CLK_PERI0 5
#define CLK_PERI1 6
#define CLK_STC0 7
#define CLK_STC_AV0 8
#define CLK_STC_AV1 9
#define CLK_STC_AV2 10
#define CLK_UA0 11
#define CLK_UA1 12
#define CLK_UA2 13
#define CLK_UA3 14
#define CLK_UA4 15
#define CLK_HWUA 16
#define CLK_DDC0 17
#define CLK_UADMA 18
#define CLK_CBDMA0 19
#define CLK_CBDMA1 20
#define CLK_SPI_COMBO_0 21
#define CLK_SPI_COMBO_1 22
#define CLK_SPI_COMBO_2 23
#define CLK_SPI_COMBO_3 24
#define CLK_AUD 25
#define CLK_USBC0 26
#define CLK_USBC1 27
#define CLK_UPHY0 28
#define CLK_UPHY1 29
#define CLK_I2CM0 30
#define CLK_I2CM1 31
#define CLK_I2CM2 32
#define CLK_I2CM3 33
#define CLK_PMC 34
#define CLK_CARD_CTL0 35
#define CLK_CARD_CTL1 36
#define CLK_CARD_CTL4 37
#define CLK_BCH 38
#define CLK_DDFCH 39
#define CLK_CSIIW0 40
#define CLK_CSIIW1 41
#define CLK_MIPICSI0 42
#define CLK_MIPICSI1 43
#define CLK_HDMI_TX 44
#define CLK_VPOST 45
#define CLK_TGEN 46
#define CLK_DMIX 47
#define CLK_TCON 48
#define CLK_GPIO 49
#define CLK_MAILBOX 50
#define CLK_SPIND 51
#define CLK_I2C2CBUS 52
#define CLK_SEC 53
#define CLK_DVE 54
#define CLK_GPOST0 55
#define CLK_OSD0 56
#define CLK_DISP_PWM 57
#define CLK_UADBG 58
#define CLK_FIO_CTL 59
#define CLK_FPGA 60
#define CLK_L2SW 61
#define CLK_ICM 62
#define CLK_AXI_GLOBAL 63
/* plls */
#define PLL_A 64
#define PLL_E 65
#define PLL_E_2P5 66
#define PLL_E_25 67
#define PLL_E_112P5 68
#define PLL_F 69
#define PLL_TV 70
#define PLL_TV_A 71
#define PLL_SYS 72
#define CLK_MAX 73
#endif

105
include/dt-bindings/clock/tegra234-clock.h
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@@ -38,6 +38,8 @@
* throughput and memory controller power.
*/
#define TEGRA234_CLK_EMC 31U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */
#define TEGRA234_CLK_HOST1X 46U
/** @brief output of gate CLK_ENB_FUSE */
#define TEGRA234_CLK_FUSE 40U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */
@@ -132,6 +134,8 @@
#define TEGRA234_CLK_UARTA 155U
/** @brief output of gate CLK_ENB_PEX1_CORE_6 */
#define TEGRA234_CLK_PEX1_C6_CORE 161U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */
#define TEGRA234_CLK_VIC 167U
/** @brief output of gate CLK_ENB_PEX2_CORE_7 */
#define TEGRA234_CLK_PEX2_C7_CORE 171U
/** @brief output of gate CLK_ENB_PEX2_CORE_8 */
@@ -164,10 +168,111 @@
#define TEGRA234_CLK_PEX1_C5_CORE 225U
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
#define TEGRA234_CLK_PLLC4 237U
/** @brief RX clock recovered from MGBE0 lane input */
#define TEGRA234_CLK_MGBE0_RX_INPUT 248U
/** @brief RX clock recovered from MGBE1 lane input */
#define TEGRA234_CLK_MGBE1_RX_INPUT 249U
/** @brief RX clock recovered from MGBE2 lane input */
#define TEGRA234_CLK_MGBE2_RX_INPUT 250U
/** @brief RX clock recovered from MGBE3 lane input */
#define TEGRA234_CLK_MGBE3_RX_INPUT 251U
/** @brief 32K input clock provided by PMIC */
#define TEGRA234_CLK_CLK_32K 289U
/** @brief Monitored branch of MBGE0 RX input clock */
#define TEGRA234_CLK_MGBE0_RX_INPUT_M 357U
/** @brief Monitored branch of MBGE1 RX input clock */
#define TEGRA234_CLK_MGBE1_RX_INPUT_M 358U
/** @brief Monitored branch of MBGE2 RX input clock */
#define TEGRA234_CLK_MGBE2_RX_INPUT_M 359U
/** @brief Monitored branch of MBGE3 RX input clock */
#define TEGRA234_CLK_MGBE3_RX_INPUT_M 360U
/** @brief Monitored branch of MGBE0 RX PCS mux output */
#define TEGRA234_CLK_MGBE0_RX_PCS_M 361U
/** @brief Monitored branch of MGBE1 RX PCS mux output */
#define TEGRA234_CLK_MGBE1_RX_PCS_M 362U
/** @brief Monitored branch of MGBE2 RX PCS mux output */
#define TEGRA234_CLK_MGBE2_RX_PCS_M 363U
/** @brief Monitored branch of MGBE3 RX PCS mux output */
#define TEGRA234_CLK_MGBE3_RX_PCS_M 364U
/** @brief RX PCS clock recovered from MGBE0 lane input */
#define TEGRA234_CLK_MGBE0_RX_PCS_INPUT 369U
/** @brief RX PCS clock recovered from MGBE1 lane input */
#define TEGRA234_CLK_MGBE1_RX_PCS_INPUT 370U
/** @brief RX PCS clock recovered from MGBE2 lane input */
#define TEGRA234_CLK_MGBE2_RX_PCS_INPUT 371U
/** @brief RX PCS clock recovered from MGBE3 lane input */
#define TEGRA234_CLK_MGBE3_RX_PCS_INPUT 372U
/** @brief output of mux controlled by GBE_UPHY_MGBE0_RX_PCS_CLK_SRC_SEL */
#define TEGRA234_CLK_MGBE0_RX_PCS 373U
/** @brief GBE_UPHY_MGBE0_TX_CLK divider gated output */
#define TEGRA234_CLK_MGBE0_TX 374U
/** @brief GBE_UPHY_MGBE0_TX_PCS_CLK divider gated output */
#define TEGRA234_CLK_MGBE0_TX_PCS 375U
/** @brief GBE_UPHY_MGBE0_MAC_CLK divider output */
#define TEGRA234_CLK_MGBE0_MAC_DIVIDER 376U
/** @brief GBE_UPHY_MGBE0_MAC_CLK gate output */
#define TEGRA234_CLK_MGBE0_MAC 377U
/** @brief GBE_UPHY_MGBE0_MACSEC_CLK gate output */
#define TEGRA234_CLK_MGBE0_MACSEC 378U
/** @brief GBE_UPHY_MGBE0_EEE_PCS_CLK gate output */
#define TEGRA234_CLK_MGBE0_EEE_PCS 379U
/** @brief GBE_UPHY_MGBE0_APP_CLK gate output */
#define TEGRA234_CLK_MGBE0_APP 380U
/** @brief GBE_UPHY_MGBE0_PTP_REF_CLK divider gated output */
#define TEGRA234_CLK_MGBE0_PTP_REF 381U
/** @brief output of mux controlled by GBE_UPHY_MGBE1_RX_PCS_CLK_SRC_SEL */
#define TEGRA234_CLK_MGBE1_RX_PCS 382U
/** @brief GBE_UPHY_MGBE1_TX_CLK divider gated output */
#define TEGRA234_CLK_MGBE1_TX 383U
/** @brief GBE_UPHY_MGBE1_TX_PCS_CLK divider gated output */
#define TEGRA234_CLK_MGBE1_TX_PCS 384U
/** @brief GBE_UPHY_MGBE1_MAC_CLK divider output */
#define TEGRA234_CLK_MGBE1_MAC_DIVIDER 385U
/** @brief GBE_UPHY_MGBE1_MAC_CLK gate output */
#define TEGRA234_CLK_MGBE1_MAC 386U
/** @brief GBE_UPHY_MGBE1_EEE_PCS_CLK gate output */
#define TEGRA234_CLK_MGBE1_EEE_PCS 388U
/** @brief GBE_UPHY_MGBE1_APP_CLK gate output */
#define TEGRA234_CLK_MGBE1_APP 389U
/** @brief GBE_UPHY_MGBE1_PTP_REF_CLK divider gated output */
#define TEGRA234_CLK_MGBE1_PTP_REF 390U
/** @brief output of mux controlled by GBE_UPHY_MGBE2_RX_PCS_CLK_SRC_SEL */
#define TEGRA234_CLK_MGBE2_RX_PCS 391U
/** @brief GBE_UPHY_MGBE2_TX_CLK divider gated output */
#define TEGRA234_CLK_MGBE2_TX 392U
/** @brief GBE_UPHY_MGBE2_TX_PCS_CLK divider gated output */
#define TEGRA234_CLK_MGBE2_TX_PCS 393U
/** @brief GBE_UPHY_MGBE2_MAC_CLK divider output */
#define TEGRA234_CLK_MGBE2_MAC_DIVIDER 394U
/** @brief GBE_UPHY_MGBE2_MAC_CLK gate output */
#define TEGRA234_CLK_MGBE2_MAC 395U
/** @brief GBE_UPHY_MGBE2_EEE_PCS_CLK gate output */
#define TEGRA234_CLK_MGBE2_EEE_PCS 397U
/** @brief GBE_UPHY_MGBE2_APP_CLK gate output */
#define TEGRA234_CLK_MGBE2_APP 398U
/** @brief GBE_UPHY_MGBE2_PTP_REF_CLK divider gated output */
#define TEGRA234_CLK_MGBE2_PTP_REF 399U
/** @brief output of mux controlled by GBE_UPHY_MGBE3_RX_PCS_CLK_SRC_SEL */
#define TEGRA234_CLK_MGBE3_RX_PCS 400U
/** @brief GBE_UPHY_MGBE3_TX_CLK divider gated output */
#define TEGRA234_CLK_MGBE3_TX 401U
/** @brief GBE_UPHY_MGBE3_TX_PCS_CLK divider gated output */
#define TEGRA234_CLK_MGBE3_TX_PCS 402U
/** @brief GBE_UPHY_MGBE3_MAC_CLK divider output */
#define TEGRA234_CLK_MGBE3_MAC_DIVIDER 403U
/** @brief GBE_UPHY_MGBE3_MAC_CLK gate output */
#define TEGRA234_CLK_MGBE3_MAC 404U
/** @brief GBE_UPHY_MGBE3_MACSEC_CLK gate output */
#define TEGRA234_CLK_MGBE3_MACSEC 405U
/** @brief GBE_UPHY_MGBE3_EEE_PCS_CLK gate output */
#define TEGRA234_CLK_MGBE3_EEE_PCS 406U
/** @brief GBE_UPHY_MGBE3_APP_CLK gate output */
#define TEGRA234_CLK_MGBE3_APP 407U
/** @brief GBE_UPHY_MGBE3_PTP_REF_CLK divider gated output */
#define TEGRA234_CLK_MGBE3_PTP_REF 408U
/** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */
#define TEGRA234_CLK_AZA_2XBIT 457U
/** @brief aza_2xbitclk / 2 (aza_bitclk) */
#define TEGRA234_CLK_AZA_BIT 458U
#endif

10
include/dt-bindings/clock/ti-dra7-atl.h
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@@ -1,3 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* This header provides constants for DRA7 ATL (Audio Tracking Logic)
*
@@ -6,15 +7,6 @@
* Copyright (C) 2013 Texas Instruments, Inc.
*
* Peter Ujfalusi <peter.ujfalusi@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_CLK_DRA7_ATL_H

3
include/dt-bindings/gpio/gpio.h
View File

@@ -39,4 +39,7 @@
/* Bit 5 express pull down */
#define GPIO_PULL_DOWN 32
/* Bit 6 express pull disable */
#define GPIO_PULL_DISABLE 64
#endif

59
include/dt-bindings/interconnect/fsl,imx8mp.h Normal file
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@@ -0,0 +1,59 @@
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
* Interconnect framework driver for i.MX SoC
*
* Copyright 2022 NXP
* Peng Fan <peng.fan@nxp.com>
*/
#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MP_H
#define __DT_BINDINGS_INTERCONNECT_IMX8MP_H
#define IMX8MP_ICN_NOC 0
#define IMX8MP_ICN_MAIN 1
#define IMX8MP_ICS_DRAM 2
#define IMX8MP_ICS_OCRAM 3
#define IMX8MP_ICM_A53 4
#define IMX8MP_ICM_SUPERMIX 5
#define IMX8MP_ICM_GIC 6
#define IMX8MP_ICM_MLMIX 7
#define IMX8MP_ICN_AUDIO 8
#define IMX8MP_ICM_DSP 9
#define IMX8MP_ICM_SDMA2PER 10
#define IMX8MP_ICM_SDMA2BURST 11
#define IMX8MP_ICM_SDMA3PER 12
#define IMX8MP_ICM_SDMA3BURST 13
#define IMX8MP_ICM_EDMA 14
#define IMX8MP_ICN_GPU 15
#define IMX8MP_ICM_GPU2D 16
#define IMX8MP_ICM_GPU3D 17
#define IMX8MP_ICN_HDMI 18
#define IMX8MP_ICM_HRV 19
#define IMX8MP_ICM_LCDIF_HDMI 20
#define IMX8MP_ICM_HDCP 21
#define IMX8MP_ICN_HSIO 22
#define IMX8MP_ICM_NOC_PCIE 23
#define IMX8MP_ICM_USB1 24
#define IMX8MP_ICM_USB2 25
#define IMX8MP_ICM_PCIE 26
#define IMX8MP_ICN_MEDIA 27
#define IMX8MP_ICM_LCDIF_RD 28
#define IMX8MP_ICM_LCDIF_WR 29
#define IMX8MP_ICM_ISI0 30
#define IMX8MP_ICM_ISI1 31
#define IMX8MP_ICM_ISI2 32
#define IMX8MP_ICM_ISP0 33
#define IMX8MP_ICM_ISP1 34
#define IMX8MP_ICM_DWE 35
#define IMX8MP_ICN_VIDEO 36
#define IMX8MP_ICM_VPU_G1 37
#define IMX8MP_ICM_VPU_G2 38
#define IMX8MP_ICM_VPU_H1 39
#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MP_H */

148
include/dt-bindings/interconnect/qcom,sm6350.h Normal file
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@@ -0,0 +1,148 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
/*
* Qualcomm SM6350 interconnect IDs
*
* Copyright (C) 2022 Luca Weiss <luca.weiss@fairphone.com>
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM6350_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_SM6350_H
#define MASTER_A1NOC_CFG 0
#define MASTER_QUP_0 1
#define MASTER_EMMC 2
#define MASTER_UFS_MEM 3
#define A1NOC_SNOC_SLV 4
#define SLAVE_SERVICE_A1NOC 5
#define MASTER_A2NOC_CFG 0
#define MASTER_QDSS_BAM 1
#define MASTER_QUP_1 2
#define MASTER_CRYPTO_CORE_0 3
#define MASTER_IPA 4
#define MASTER_QDSS_ETR 5
#define MASTER_SDCC_2 6
#define MASTER_USB3 7
#define A2NOC_SNOC_SLV 8
#define SLAVE_SERVICE_A2NOC 9
#define MASTER_CAMNOC_HF0_UNCOMP 0
#define MASTER_CAMNOC_ICP_UNCOMP 1
#define MASTER_CAMNOC_SF_UNCOMP 2
#define MASTER_QUP_CORE_0 3
#define MASTER_QUP_CORE_1 4
#define MASTER_LLCC 5
#define SLAVE_CAMNOC_UNCOMP 6
#define SLAVE_QUP_CORE_0 7
#define SLAVE_QUP_CORE_1 8
#define SLAVE_EBI_CH0 9
#define MASTER_NPU 0
#define MASTER_NPU_PROC 1
#define SLAVE_CDSP_GEM_NOC 2
#define SNOC_CNOC_MAS 0
#define MASTER_QDSS_DAP 1
#define SLAVE_A1NOC_CFG 2
#define SLAVE_A2NOC_CFG 3
#define SLAVE_AHB2PHY 4
#define SLAVE_AHB2PHY_2 5
#define SLAVE_AOSS 6
#define SLAVE_BOOT_ROM 7
#define SLAVE_CAMERA_CFG 8
#define SLAVE_CAMERA_NRT_THROTTLE_CFG 9
#define SLAVE_CAMERA_RT_THROTTLE_CFG 10
#define SLAVE_CLK_CTL 11
#define SLAVE_RBCPR_CX_CFG 12
#define SLAVE_RBCPR_MX_CFG 13
#define SLAVE_CRYPTO_0_CFG 14
#define SLAVE_DCC_CFG 15
#define SLAVE_CNOC_DDRSS 16
#define SLAVE_DISPLAY_CFG 17
#define SLAVE_DISPLAY_THROTTLE_CFG 18
#define SLAVE_EMMC_CFG 19
#define SLAVE_GLM 20
#define SLAVE_GRAPHICS_3D_CFG 21
#define SLAVE_IMEM_CFG 22
#define SLAVE_IPA_CFG 23
#define SLAVE_CNOC_MNOC_CFG 24
#define SLAVE_CNOC_MSS 25
#define SLAVE_NPU_CFG 26
#define SLAVE_PDM 27
#define SLAVE_PIMEM_CFG 28
#define SLAVE_PRNG 29
#define SLAVE_QDSS_CFG 30
#define SLAVE_QM_CFG 31
#define SLAVE_QM_MPU_CFG 32
#define SLAVE_QUP_0 33
#define SLAVE_QUP_1 34
#define SLAVE_SDCC_2 35
#define SLAVE_SECURITY 36
#define SLAVE_SNOC_CFG 37
#define SLAVE_TCSR 38
#define SLAVE_UFS_MEM_CFG 39
#define SLAVE_USB3 40
#define SLAVE_VENUS_CFG 41
#define SLAVE_VENUS_THROTTLE_CFG 42
#define SLAVE_VSENSE_CTRL_CFG 43
#define SLAVE_SERVICE_CNOC 44
#define MASTER_CNOC_DC_NOC 0
#define SLAVE_GEM_NOC_CFG 1
#define SLAVE_LLCC_CFG 2
#define MASTER_AMPSS_M0 0
#define MASTER_SYS_TCU 1
#define MASTER_GEM_NOC_CFG 2
#define MASTER_COMPUTE_NOC 3
#define MASTER_MNOC_HF_MEM_NOC 4
#define MASTER_MNOC_SF_MEM_NOC 5
#define MASTER_SNOC_GC_MEM_NOC 6
#define MASTER_SNOC_SF_MEM_NOC 7
#define MASTER_GRAPHICS_3D 8
#define SLAVE_MCDMA_MS_MPU_CFG 9
#define SLAVE_MSS_PROC_MS_MPU_CFG 10
#define SLAVE_GEM_NOC_SNOC 11
#define SLAVE_LLCC 12
#define SLAVE_SERVICE_GEM_NOC 13
#define MASTER_CNOC_MNOC_CFG 0
#define MASTER_VIDEO_P0 1
#define MASTER_VIDEO_PROC 2
#define MASTER_CAMNOC_HF 3
#define MASTER_CAMNOC_ICP 4
#define MASTER_CAMNOC_SF 5
#define MASTER_MDP_PORT0 6
#define SLAVE_MNOC_HF_MEM_NOC 7
#define SLAVE_MNOC_SF_MEM_NOC 8
#define SLAVE_SERVICE_MNOC 9
#define MASTER_NPU_SYS 0
#define MASTER_NPU_NOC_CFG 1
#define SLAVE_NPU_CAL_DP0 2
#define SLAVE_NPU_CP 3
#define SLAVE_NPU_INT_DMA_BWMON_CFG 4
#define SLAVE_NPU_DPM 5
#define SLAVE_ISENSE_CFG 6
#define SLAVE_NPU_LLM_CFG 7
#define SLAVE_NPU_TCM 8
#define SLAVE_NPU_COMPUTE_NOC 9
#define SLAVE_SERVICE_NPU_NOC 10
#define MASTER_SNOC_CFG 0
#define A1NOC_SNOC_MAS 1
#define A2NOC_SNOC_MAS 2
#define MASTER_GEM_NOC_SNOC 3
#define MASTER_PIMEM 4
#define MASTER_GIC 5
#define SLAVE_APPSS 6
#define SNOC_CNOC_SLV 7
#define SLAVE_SNOC_GEM_NOC_GC 8
#define SLAVE_SNOC_GEM_NOC_SF 9
#define SLAVE_OCIMEM 10
#define SLAVE_PIMEM 11
#define SLAVE_SERVICE_SNOC 12
#define SLAVE_QDSS_STM 13
#define SLAVE_TCU 14
#endif

1
include/dt-bindings/mailbox/qcom-ipcc.h
View File

@@ -30,6 +30,7 @@
#define IPCC_CLIENT_PCIE1 14
#define IPCC_CLIENT_PCIE2 15
#define IPCC_CLIENT_SPSS 16
#define IPCC_CLIENT_NSP1 18
#define IPCC_CLIENT_TME 23
#define IPCC_CLIENT_WPSS 24

26
include/dt-bindings/memory/tegra234-mc.h
View File

@@ -11,11 +11,16 @@
/* NISO0 stream IDs */
#define TEGRA234_SID_APE 0x02
#define TEGRA234_SID_HDA 0x03
#define TEGRA234_SID_GPCDMA 0x04
#define TEGRA234_SID_MGBE 0x06
#define TEGRA234_SID_PCIE0 0x12
#define TEGRA234_SID_PCIE4 0x13
#define TEGRA234_SID_PCIE5 0x14
#define TEGRA234_SID_PCIE6 0x15
#define TEGRA234_SID_PCIE9 0x1f
#define TEGRA234_SID_MGBE_VF1 0x49
#define TEGRA234_SID_MGBE_VF2 0x4a
#define TEGRA234_SID_MGBE_VF3 0x4b
/* NISO1 stream IDs */
#define TEGRA234_SID_SDMMC4 0x02
@@ -26,6 +31,8 @@
#define TEGRA234_SID_PCIE8 0x09
#define TEGRA234_SID_PCIE10 0x0b
#define TEGRA234_SID_BPMP 0x10
#define TEGRA234_SID_HOST1X 0x27
#define TEGRA234_SID_VIC 0x34
/*
* memory client IDs
@@ -33,6 +40,7 @@
/* High-definition audio (HDA) read clients */
#define TEGRA234_MEMORY_CLIENT_HDAR 0x15
#define TEGRA234_MEMORY_CLIENT_HOST1XDMAR 0x16
/* PCIE6 read clients */
#define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28
/* PCIE6 write clients */
@@ -61,10 +69,28 @@
#define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48
/* PCIE7r1 read clients */
#define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49
/* MGBE0 read client */
#define TEGRA234_MEMORY_CLIENT_MGBEARD 0x58
/* MGBEB read client */
#define TEGRA234_MEMORY_CLIENT_MGBEBRD 0x59
/* MGBEC read client */
#define TEGRA234_MEMORY_CLIENT_MGBECRD 0x5a
/* MGBED read client */
#define TEGRA234_MEMORY_CLIENT_MGBEDRD 0x5b
/* MGBE0 write client */
#define TEGRA234_MEMORY_CLIENT_MGBEAWR 0x5c
/* MGBEB write client */
#define TEGRA234_MEMORY_CLIENT_MGBEBWR 0x5f
/* MGBEC write client */
#define TEGRA234_MEMORY_CLIENT_MGBECWR 0x61
/* sdmmcd memory read client */
#define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63
/* MGBED write client */
#define TEGRA234_MEMORY_CLIENT_MGBEDWR 0x65
/* sdmmcd memory write client */
#define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67
#define TEGRA234_MEMORY_CLIENT_VICSRD 0x6c
#define TEGRA234_MEMORY_CLIENT_VICSWR 0x6d
/* BPMP read client */
#define TEGRA234_MEMORY_CLIENT_BPMPR 0x93
/* BPMP write client */

33
include/dt-bindings/net/pcs-rzn1-miic.h Normal file
View File

@@ -0,0 +1,33 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) 2022 Schneider-Electric
*
* Clément Léger <clement.leger@bootlin.com>
*/
#ifndef _DT_BINDINGS_PCS_RZN1_MIIC
#define _DT_BINDINGS_PCS_RZN1_MIIC
/*
* Reefer to the datasheet [1] section 8.2.1, Internal Connection of Ethernet
* Ports to check the available combination
*
* [1] REN_r01uh0750ej0140-rzn1-introduction_MAT_20210228.pdf
*/
#define MIIC_GMAC1_PORT 0
#define MIIC_GMAC2_PORT 1
#define MIIC_RTOS_PORT 2
#define MIIC_SERCOS_PORTA 3
#define MIIC_SERCOS_PORTB 4
#define MIIC_ETHERCAT_PORTA 5
#define MIIC_ETHERCAT_PORTB 6
#define MIIC_ETHERCAT_PORTC 7
#define MIIC_SWITCH_PORTA 8
#define MIIC_SWITCH_PORTB 9
#define MIIC_SWITCH_PORTC 10
#define MIIC_SWITCH_PORTD 11
#define MIIC_HSR_PORTA 12
#define MIIC_HSR_PORTB 13
#endif

12
include/dt-bindings/nvmem/microchip,sama7g5-otpc.h Normal file
View File

@@ -0,0 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
#ifndef _DT_BINDINGS_NVMEM_MICROCHIP_OTPC_H
#define _DT_BINDINGS_NVMEM_MICROCHIP_OTPC_H
/*
* Need to have it as a multiple of 4 as NVMEM memory is registered with
* stride = 4.
*/
#define OTP_PKT(id) ((id) * 4)
#endif

10
include/dt-bindings/pinctrl/hisi.h
View File

@@ -1,17 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* This header provides constants for hisilicon pinctrl bindings.
*
* Copyright (c) 2015 HiSilicon Limited.
* Copyright (c) 2015 Linaro Limited.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_PINCTRL_HISI_H

10
include/dt-bindings/pinctrl/keystone.h
View File

@@ -1,16 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* This header provides constants for Keystone pinctrl bindings.
*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_PINCTRL_KEYSTONE_H

2
include/dt-bindings/pinctrl/r7s9210-pinctrl.h
View File

@@ -42,6 +42,6 @@
/*
* Convert a port and pin label to its global pin index
*/
#define RZA2_PIN(port, pin) ((port) * RZA2_PINS_PER_PORT + (pin))
#define RZA2_PIN(port, pin) ((port) * RZA2_PINS_PER_PORT + (pin))
#endif /* __DT_BINDINGS_PINCTRL_RENESAS_RZA2_H */

2
include/dt-bindings/pinctrl/rzg2l-pinctrl.h
View File

@@ -18,6 +18,6 @@
#define RZG2L_PORT_PINMUX(b, p, f) ((b) * RZG2L_PINS_PER_PORT + (p) | ((f) << 16))
/* Convert a port and pin label to its global pin index */
#define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin))
#define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin))
#endif /* __DT_BINDINGS_RZG2L_PINCTRL_H */

23
include/dt-bindings/pinctrl/rzv2m-pinctrl.h Normal file
View File

@@ -0,0 +1,23 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* This header provides constants for Renesas RZ/V2M pinctrl bindings.
*
* Copyright (C) 2022 Renesas Electronics Corp.
*
*/
#ifndef __DT_BINDINGS_RZV2M_PINCTRL_H
#define __DT_BINDINGS_RZV2M_PINCTRL_H
#define RZV2M_PINS_PER_PORT 16
/*
* Create the pin index from its bank and position numbers and store in
* the upper 16 bits the alternate function identifier
*/
#define RZV2M_PORT_PINMUX(b, p, f) ((b) * RZV2M_PINS_PER_PORT + (p) | ((f) << 16))
/* Convert a port and pin label to its global pin index */
#define RZV2M_GPIO(port, pin) ((port) * RZV2M_PINS_PER_PORT + (pin))
#endif /* __DT_BINDINGS_RZV2M_PINCTRL_H */

16
include/dt-bindings/power/mt6795-power.h Normal file
View File

@@ -0,0 +1,16 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
#ifndef _DT_BINDINGS_POWER_MT6795_POWER_H
#define _DT_BINDINGS_POWER_MT6795_POWER_H
#define MT6795_POWER_DOMAIN_MM 0
#define MT6795_POWER_DOMAIN_VDEC 1
#define MT6795_POWER_DOMAIN_VENC 2
#define MT6795_POWER_DOMAIN_ISP 3
#define MT6795_POWER_DOMAIN_MJC 4
#define MT6795_POWER_DOMAIN_AUDIO 5
#define MT6795_POWER_DOMAIN_MFG_ASYNC 6
#define MT6795_POWER_DOMAIN_MFG_2D 7
#define MT6795_POWER_DOMAIN_MFG 8
#define MT6795_POWER_DOMAIN_MODEM 9
#endif /* _DT_BINDINGS_POWER_MT6795_POWER_H */

9
include/dt-bindings/power/mt6797-power.h
View File

@@ -1,14 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2017 MediaTek Inc.
* Author: Mars.C <mars.cheng@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_POWER_MT6797_POWER_H

7
include/dt-bindings/power/qcom-rpmpd.h
View File

@@ -187,6 +187,13 @@
#define MSM8916_VDDMX 3
#define MSM8916_VDDMX_AO 4
/* MSM8909 Power Domain Indexes */
#define MSM8909_VDDCX MSM8916_VDDCX
#define MSM8909_VDDCX_AO MSM8916_VDDCX_AO
#define MSM8909_VDDCX_VFC MSM8916_VDDCX_VFC
#define MSM8909_VDDMX MSM8916_VDDMX
#define MSM8909_VDDMX_AO MSM8916_VDDMX_AO
/* MSM8953 Power Domain Indexes */
#define MSM8953_VDDMD 0
#define MSM8953_VDDMD_AO 1

2
include/dt-bindings/power/tegra234-powergate.h
View File

@@ -18,5 +18,7 @@
#define TEGRA234_POWER_DOMAIN_MGBEA 17U
#define TEGRA234_POWER_DOMAIN_MGBEB 18U
#define TEGRA234_POWER_DOMAIN_MGBEC 19U
#define TEGRA234_POWER_DOMAIN_MGBED 20U
#define TEGRA234_POWER_DOMAIN_VIC 29U
#endif

5
include/dt-bindings/reset/mt8186-resets.h
View File

@@ -7,6 +7,7 @@
#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8186
#define _DT_BINDINGS_RESET_CONTROLLER_MT8186
/* TOPRGU resets */
#define MT8186_TOPRGU_INFRA_SW_RST 0
#define MT8186_TOPRGU_MM_SW_RST 1
#define MT8186_TOPRGU_MFG_SW_RST 2
@@ -33,4 +34,8 @@
/* MMSYS resets */
#define MT8186_MMSYS_SW0_RST_B_DISP_DSI0 19
/* INFRA resets */
#define MT8186_INFRA_THERMAL_CTRL_RST 0
#define MT8186_INFRA_PTP_CTRL_RST 1
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8186 */

8
include/dt-bindings/reset/mt8192-resets.h
View File

@@ -7,6 +7,7 @@
#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192
#define _DT_BINDINGS_RESET_CONTROLLER_MT8192
/* TOPRGU resets */
#define MT8192_TOPRGU_MM_SW_RST 1
#define MT8192_TOPRGU_MFG_SW_RST 2
#define MT8192_TOPRGU_VENC_SW_RST 3
@@ -30,4 +31,11 @@
/* MMSYS resets */
#define MT8192_MMSYS_SW0_RST_B_DISP_DSI0 15
/* INFRA resets */
#define MT8192_INFRA_RST0_THERM_CTRL_SWRST 0
#define MT8192_INFRA_RST2_PEXTP_PHY_SWRST 1
#define MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST 2
#define MT8192_INFRA_RST4_PCIE_TOP_SWRST 3
#define MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST 4
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */

6
include/dt-bindings/reset/mt8195-resets.h
View File

@@ -7,6 +7,7 @@
#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195
#define _DT_BINDINGS_RESET_CONTROLLER_MT8195
/* TOPRGU resets */
#define MT8195_TOPRGU_CONN_MCU_SW_RST 0
#define MT8195_TOPRGU_INFRA_GRST_SW_RST 1
#define MT8195_TOPRGU_APU_SW_RST 2
@@ -26,4 +27,9 @@
#define MT8195_TOPRGU_SW_RST_NUM 16
/* INFRA resets */
#define MT8195_INFRA_RST0_THERM_CTRL_SWRST 0
#define MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST 1
#define MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST 2
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */

10
include/dt-bindings/reset/sama7g5-reset.h Normal file
View File

@@ -0,0 +1,10 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
#ifndef __DT_BINDINGS_RESET_SAMA7G5_H
#define __DT_BINDINGS_RESET_SAMA7G5_H
#define SAMA7G5_RESET_USB_PHY1 4
#define SAMA7G5_RESET_USB_PHY2 5
#define SAMA7G5_RESET_USB_PHY3 6
#endif /* __DT_BINDINGS_RESET_SAMA7G5_H */

87
include/dt-bindings/reset/sunplus,sp7021-reset.h Normal file
View File

@@ -0,0 +1,87 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) Sunplus Technology Co., Ltd.
* All rights reserved.
*/
#ifndef _DT_BINDINGS_RST_SUNPLUS_SP7021_H
#define _DT_BINDINGS_RST_SUNPLUS_SP7021_H
#define RST_SYSTEM 0
#define RST_RTC 1
#define RST_IOCTL 2
#define RST_IOP 3
#define RST_OTPRX 4
#define RST_NOC 5
#define RST_BR 6
#define RST_RBUS_L00 7
#define RST_SPIFL 8
#define RST_SDCTRL0 9
#define RST_PERI0 10
#define RST_A926 11
#define RST_UMCTL2 12
#define RST_PERI1 13
#define RST_DDR_PHY0 14
#define RST_ACHIP 15
#define RST_STC0 16
#define RST_STC_AV0 17
#define RST_STC_AV1 18
#define RST_STC_AV2 19
#define RST_UA0 20
#define RST_UA1 21
#define RST_UA2 22
#define RST_UA3 23
#define RST_UA4 24
#define RST_HWUA 25
#define RST_DDC0 26
#define RST_UADMA 27
#define RST_CBDMA0 28
#define RST_CBDMA1 29
#define RST_SPI_COMBO_0 30
#define RST_SPI_COMBO_1 31
#define RST_SPI_COMBO_2 32
#define RST_SPI_COMBO_3 33
#define RST_AUD 34
#define RST_USBC0 35
#define RST_USBC1 36
#define RST_UPHY0 37
#define RST_UPHY1 38
#define RST_I2CM0 39
#define RST_I2CM1 40
#define RST_I2CM2 41
#define RST_I2CM3 42
#define RST_PMC 43
#define RST_CARD_CTL0 44
#define RST_CARD_CTL1 45
#define RST_CARD_CTL4 46
#define RST_BCH 47
#define RST_DDFCH 48
#define RST_CSIIW0 49
#define RST_CSIIW1 50
#define RST_MIPICSI0 51
#define RST_MIPICSI1 52
#define RST_HDMI_TX 53
#define RST_VPOST 54
#define RST_TGEN 55
#define RST_DMIX 56
#define RST_TCON 57
#define RST_INTERRUPT 58
#define RST_RGST 59
#define RST_GPIO 60
#define RST_RBUS_TOP 61
#define RST_MAILBOX 62
#define RST_SPIND 63
#define RST_I2C2CBUS 64
#define RST_SEC 65
#define RST_DVE 66
#define RST_GPOST0 67
#define RST_OSD0 68
#define RST_DISP_PWM 69
#define RST_UADBG 70
#define RST_DUMMY_MASTER 71
#define RST_FIO_CTL 72
#define RST_FPGA 73
#define RST_L2SW 74
#define RST_ICM 75
#define RST_AXI_GLOBAL 76
#endif

10
include/dt-bindings/reset/tegra234-reset.h
View File

@@ -15,6 +15,7 @@
#define TEGRA234_RESET_PEX1_COMMON_APB 13U
#define TEGRA234_RESET_PEX2_CORE_7 14U
#define TEGRA234_RESET_PEX2_CORE_7_APB 15U
#define TEGRA234_RESET_GPCDMA 18U
#define TEGRA234_RESET_HDA 20U
#define TEGRA234_RESET_HDACODEC 21U
#define TEGRA234_RESET_I2C1 24U
@@ -29,6 +30,12 @@
#define TEGRA234_RESET_I2C7 33U
#define TEGRA234_RESET_I2C8 34U
#define TEGRA234_RESET_I2C9 35U
#define TEGRA234_RESET_MGBE0_PCS 45U
#define TEGRA234_RESET_MGBE0_MAC 46U
#define TEGRA234_RESET_MGBE1_PCS 49U
#define TEGRA234_RESET_MGBE1_MAC 50U
#define TEGRA234_RESET_MGBE2_PCS 53U
#define TEGRA234_RESET_MGBE2_MAC 54U
#define TEGRA234_RESET_PEX2_CORE_10 56U
#define TEGRA234_RESET_PEX2_CORE_10_APB 57U
#define TEGRA234_RESET_PEX2_COMMON_APB 58U
@@ -43,7 +50,10 @@
#define TEGRA234_RESET_QSPI0 76U
#define TEGRA234_RESET_QSPI1 77U
#define TEGRA234_RESET_SDMMC4 85U
#define TEGRA234_RESET_MGBE3_PCS 87U
#define TEGRA234_RESET_MGBE3_MAC 88U
#define TEGRA234_RESET_UARTA 100U
#define TEGRA234_RESET_VIC 113U
#define TEGRA234_RESET_PEX0_CORE_0 116U
#define TEGRA234_RESET_PEX0_CORE_1 117U
#define TEGRA234_RESET_PEX0_CORE_2 118U

18
include/dt-bindings/soc/samsung,boot-mode.h Normal file
View File

@@ -0,0 +1,18 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2022 Samsung Electronics Co., Ltd.
* Author: Chanho Park <chanho61.park@samsung.com>
*
* Device Tree bindings for Samsung Boot Mode.
*/
#ifndef __DT_BINDINGS_SAMSUNG_BOOT_MODE_H
#define __DT_BINDINGS_SAMSUNG_BOOT_MODE_H
/* Boot mode definitions for Exynos Auto v9 SoC */
#define EXYNOSAUTOV9_BOOT_FASTBOOT 0xfa
#define EXYNOSAUTOV9_BOOT_BOOTLOADER 0xfc
#define EXYNOSAUTOV9_BOOT_RECOVERY 0xff
#endif /* __DT_BINDINGS_SAMSUNG_BOOT_MODE_H */

15
include/dt-bindings/sound/qcom,wcd9335.h Normal file
View File

@@ -0,0 +1,15 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
#ifndef __DT_SOUND_QCOM_WCD9335_H
#define __DT_SOUND_QCOM_WCD9335_H
#define AIF1_PB 0
#define AIF1_CAP 1
#define AIF2_PB 2
#define AIF2_CAP 3
#define AIF3_PB 4
#define AIF3_CAP 5
#define AIF4_PB 6
#define NUM_CODEC_DAIS 7
#endif

69
include/kunit/test.h
View File

@@ -237,9 +237,9 @@ size_t kunit_suite_num_test_cases(struct kunit_suite *suite);
unsigned int kunit_test_case_num(struct kunit_suite *suite,
struct kunit_case *test_case);
int __kunit_test_suites_init(struct kunit_suite * const * const suites);
int __kunit_test_suites_init(struct kunit_suite * const * const suites, int num_suites);
void __kunit_test_suites_exit(struct kunit_suite **suites);
void __kunit_test_suites_exit(struct kunit_suite **suites, int num_suites);
#if IS_BUILTIN(CONFIG_KUNIT)
int kunit_run_all_tests(void);
@@ -250,43 +250,11 @@ static inline int kunit_run_all_tests(void)
}
#endif /* IS_BUILTIN(CONFIG_KUNIT) */
#ifdef MODULE
/**
* kunit_test_suites_for_module() - used to register one or more
* &struct kunit_suite with KUnit.
*
* @__suites: a statically allocated list of &struct kunit_suite.
*
* Registers @__suites with the test framework. See &struct kunit_suite for
* more information.
*
* If a test suite is built-in, module_init() gets translated into
* an initcall which we don't want as the idea is that for builtins
* the executor will manage execution. So ensure we do not define
* module_{init|exit} functions for the builtin case when registering
* suites via kunit_test_suites() below.
*/
#define kunit_test_suites_for_module(__suites) \
static int __init kunit_test_suites_init(void) \
{ \
return __kunit_test_suites_init(__suites); \
} \
module_init(kunit_test_suites_init); \
\
static void __exit kunit_test_suites_exit(void) \
{ \
return __kunit_test_suites_exit(__suites); \
} \
module_exit(kunit_test_suites_exit)
#else
#define kunit_test_suites_for_module(__suites)
#endif /* MODULE */
#define __kunit_test_suites(unique_array, unique_suites, ...) \
static struct kunit_suite *unique_array[] = { __VA_ARGS__, NULL }; \
kunit_test_suites_for_module(unique_array); \
static struct kunit_suite **unique_suites \
__used __section(".kunit_test_suites") = unique_array
#define __kunit_test_suites(unique_array, ...) \
MODULE_INFO(test, "Y"); \
static struct kunit_suite *unique_array[] \
__aligned(sizeof(struct kunit_suite *)) \
__used __section(".kunit_test_suites") = { __VA_ARGS__ }
/**
* kunit_test_suites() - used to register one or more &struct kunit_suite
@@ -294,21 +262,16 @@ static inline int kunit_run_all_tests(void)
*
* @__suites: a statically allocated list of &struct kunit_suite.
*
* Registers @suites with the test framework. See &struct kunit_suite for
* more information.
* Registers @suites with the test framework.
* This is done by placing the array of struct kunit_suite * in the
* .kunit_test_suites ELF section.
*
* When builtin, KUnit tests are all run via executor; this is done
* by placing the array of struct kunit_suite * in the .kunit_test_suites
* ELF section.
*
* An alternative is to build the tests as a module. Because modules do not
* support multiple initcall()s, we need to initialize an array of suites for a
* module.
* When builtin, KUnit tests are all run via the executor at boot, and when
* built as a module, they run on module load.
*
*/
#define kunit_test_suites(__suites...) \
__kunit_test_suites(__UNIQUE_ID(array), \
__UNIQUE_ID(suites), \
##__suites)
#define kunit_test_suite(suite) kunit_test_suites(&suite)
@@ -320,7 +283,7 @@ static inline int kunit_run_all_tests(void)
*
* @__suites: a statically allocated list of &struct kunit_suite.
*
* This functions identically as &kunit_test_suites() except that it suppresses
* This functions identically as kunit_test_suites() except that it suppresses
* modpost warnings for referencing functions marked __init or data marked
* __initdata; this is OK because currently KUnit only runs tests upon boot
* during the init phase or upon loading a module during the init phase.
@@ -863,7 +826,7 @@ do { \
#define KUNIT_EXPECT_LE_MSG(test, left, right, fmt, ...) \
KUNIT_BINARY_INT_ASSERTION(test, \
KUNIT_ASSERTION, \
KUNIT_EXPECTATION, \
left, <=, right, \
fmt, \
##__VA_ARGS__)
@@ -1153,7 +1116,7 @@ do { \
#define KUNIT_ASSERT_LT_MSG(test, left, right, fmt, ...) \
KUNIT_BINARY_INT_ASSERTION(test, \
KUNIT_EXPECTATION, \
KUNIT_ASSERTION, \
left, <, right, \
fmt, \
##__VA_ARGS__)
@@ -1194,7 +1157,7 @@ do { \
#define KUNIT_ASSERT_GT_MSG(test, left, right, fmt, ...) \
KUNIT_BINARY_INT_ASSERTION(test, \
KUNIT_EXPECTATION, \
KUNIT_ASSERTION, \
left, >, right, \
fmt, \
##__VA_ARGS__)

2
include/kvm/arm_vgic.h
View File

@@ -364,7 +364,7 @@ struct vgic_cpu {
extern struct static_key_false vgic_v2_cpuif_trap;
extern struct static_key_false vgic_v3_cpuif_trap;
int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
int kvm_set_legacy_vgic_v2_addr(struct kvm *kvm, struct kvm_arm_device_addr *dev_addr);
void kvm_vgic_early_init(struct kvm *kvm);
int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
int kvm_vgic_create(struct kvm *kvm, u32 type);

13
include/linux/acpi.h
View File

@@ -764,6 +764,7 @@ static inline u64 acpi_arch_get_root_pointer(void)
#endif
int acpi_get_local_address(acpi_handle handle, u32 *addr);
const char *acpi_get_subsystem_id(acpi_handle handle);
#else /* !CONFIG_ACPI */
@@ -1025,6 +1026,11 @@ static inline int acpi_get_local_address(acpi_handle handle, u32 *addr)
return -ENODEV;
}
static inline const char *acpi_get_subsystem_id(acpi_handle handle)
{
return ERR_PTR(-ENODEV);
}
static inline int acpi_register_wakeup_handler(int wake_irq,
bool (*wakeup)(void *context), void *context)
{
@@ -1245,7 +1251,7 @@ static inline bool acpi_dev_has_props(const struct acpi_device *adev)
struct acpi_device_properties *
acpi_data_add_props(struct acpi_device_data *data, const guid_t *guid,
const union acpi_object *properties);
union acpi_object *properties);
int acpi_node_prop_get(const struct fwnode_handle *fwnode, const char *propname,
void **valptr);
@@ -1431,7 +1437,6 @@ int find_acpi_cpu_topology(unsigned int cpu, int level);
int find_acpi_cpu_topology_cluster(unsigned int cpu);
int find_acpi_cpu_topology_package(unsigned int cpu);
int find_acpi_cpu_topology_hetero_id(unsigned int cpu);
int find_acpi_cpu_cache_topology(unsigned int cpu, int level);
#else
static inline int acpi_pptt_cpu_is_thread(unsigned int cpu)
{
@@ -1453,10 +1458,6 @@ static inline int find_acpi_cpu_topology_hetero_id(unsigned int cpu)
{
return -EINVAL;
}
static inline int find_acpi_cpu_cache_topology(unsigned int cpu, int level)
{
return -EINVAL;
}
#endif
#ifdef CONFIG_ACPI_PCC

14
include/linux/acpi_iort.h
View File

@@ -33,10 +33,14 @@ struct irq_domain *iort_get_device_domain(struct device *dev, u32 id,
enum irq_domain_bus_token bus_token);
void acpi_configure_pmsi_domain(struct device *dev);
int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id);
void iort_get_rmr_sids(struct fwnode_handle *iommu_fwnode,
struct list_head *head);
void iort_put_rmr_sids(struct fwnode_handle *iommu_fwnode,
struct list_head *head);
/* IOMMU interface */
int iort_dma_get_ranges(struct device *dev, u64 *size);
int iort_iommu_configure_id(struct device *dev, const u32 *id_in);
int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head);
void iort_iommu_get_resv_regions(struct device *dev, struct list_head *head);
phys_addr_t acpi_iort_dma_get_max_cpu_address(void);
#else
static inline void acpi_iort_init(void) { }
@@ -46,14 +50,18 @@ static inline struct irq_domain *iort_get_device_domain(
struct device *dev, u32 id, enum irq_domain_bus_token bus_token)
{ return NULL; }
static inline void acpi_configure_pmsi_domain(struct device *dev) { }
static inline
void iort_get_rmr_sids(struct fwnode_handle *iommu_fwnode, struct list_head *head) { }
static inline
void iort_put_rmr_sids(struct fwnode_handle *iommu_fwnode, struct list_head *head) { }
/* IOMMU interface */
static inline int iort_dma_get_ranges(struct device *dev, u64 *size)
{ return -ENODEV; }
static inline int iort_iommu_configure_id(struct device *dev, const u32 *id_in)
{ return -ENODEV; }
static inline
int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head)
{ return 0; }
void iort_iommu_get_resv_regions(struct device *dev, struct list_head *head)
{ }
static inline phys_addr_t acpi_iort_dma_get_max_cpu_address(void)
{ return PHYS_ADDR_MAX; }

2
include/linux/acpi_viot.h
View File

@@ -6,9 +6,11 @@
#include <linux/acpi.h>
#ifdef CONFIG_ACPI_VIOT
void __init acpi_viot_early_init(void);
void __init acpi_viot_init(void);
int viot_iommu_configure(struct device *dev);
#else
static inline void acpi_viot_early_init(void) {}
static inline void acpi_viot_init(void) {}
static inline int viot_iommu_configure(struct device *dev)
{

1
include/linux/amba/bus.h
View File

@@ -67,6 +67,7 @@ struct amba_device {
struct clk *pclk;
struct device_dma_parameters dma_parms;
unsigned int periphid;
struct mutex periphid_lock;
unsigned int cid;
struct amba_cs_uci_id uci;
unsigned int irq[AMBA_NR_IRQS];

4
include/linux/amd-iommu.h
View File

@@ -206,4 +206,8 @@ int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn,
u64 *value);
struct amd_iommu *get_amd_iommu(unsigned int idx);
#ifdef CONFIG_AMD_MEM_ENCRYPT
int amd_iommu_snp_enable(void);
#endif
#endif /* _ASM_X86_AMD_IOMMU_H */

56
include/linux/aperture.h Normal file
View File

@@ -0,0 +1,56 @@
/* SPDX-License-Identifier: MIT */
#ifndef _LINUX_APERTURE_H_
#define _LINUX_APERTURE_H_
#include <linux/types.h>
struct pci_dev;
struct platform_device;
#if defined(CONFIG_APERTURE_HELPERS)
int devm_aperture_acquire_for_platform_device(struct platform_device *pdev,
resource_size_t base,
resource_size_t size);
int aperture_remove_conflicting_devices(resource_size_t base, resource_size_t size,
bool primary, const char *name);
int aperture_remove_conflicting_pci_devices(struct pci_dev *pdev, const char *name);
#else
static inline int devm_aperture_acquire_for_platform_device(struct platform_device *pdev,
resource_size_t base,
resource_size_t size)
{
return 0;
}
static inline int aperture_remove_conflicting_devices(resource_size_t base, resource_size_t size,
bool primary, const char *name)
{
return 0;
}
static inline int aperture_remove_conflicting_pci_devices(struct pci_dev *pdev, const char *name)
{
return 0;
}
#endif
/**
* aperture_remove_all_conflicting_devices - remove all existing framebuffers
* @primary: also kick vga16fb if present; only relevant for VGA devices
* @name: a descriptive name of the requesting driver
*
* This function removes all graphics device drivers. Use this function on systems
* that can have their framebuffer located anywhere in memory.
*
* Returns:
* 0 on success, or a negative errno code otherwise
*/
static inline int aperture_remove_all_conflicting_devices(bool primary, const char *name)
{
return aperture_remove_conflicting_devices(0, (resource_size_t)-1, primary, name);
}
#endif

1
include/linux/arch_topology.h
View File

@@ -68,7 +68,6 @@ struct cpu_topology {
int core_id;
int cluster_id;
int package_id;
int llc_id;
cpumask_t thread_sibling;
cpumask_t core_sibling;
cpumask_t cluster_sibling;

2
include/linux/atm_tcp.h
View File

@@ -9,6 +9,8 @@
#include <uapi/linux/atm_tcp.h>
struct atm_vcc;
struct module;
struct atm_tcp_ops {
int (*attach)(struct atm_vcc *vcc,int itf);

7
include/linux/audit.h
View File

@@ -119,8 +119,6 @@ enum audit_nfcfgop {
AUDIT_NFT_OP_INVALID,
};
extern int is_audit_feature_set(int which);
extern int __init audit_register_class(int class, unsigned *list);
extern int audit_classify_syscall(int abi, unsigned syscall);
extern int audit_classify_arch(int arch);
@@ -287,7 +285,6 @@ static inline int audit_signal_info(int sig, struct task_struct *t)
/* These are defined in auditsc.c */
/* Public API */
extern int audit_alloc(struct task_struct *task);
extern int audit_alloc_kernel(struct task_struct *task);
extern void __audit_free(struct task_struct *task);
extern void __audit_uring_entry(u8 op);
extern void __audit_uring_exit(int success, long code);
@@ -580,10 +577,6 @@ static inline int audit_alloc(struct task_struct *task)
{
return 0;
}
static inline int audit_alloc_kernel(struct task_struct *task)
{
return 0;
}
static inline void audit_free(struct task_struct *task)
{ }
static inline void audit_uring_entry(u8 op)

7
include/linux/backing-dev-defs.h
View File

@@ -28,11 +28,6 @@ enum wb_state {
WB_start_all, /* nr_pages == 0 (all) work pending */
};
enum wb_congested_state {
WB_async_congested, /* The async (write) queue is getting full */
WB_sync_congested, /* The sync queue is getting full */
};
enum wb_stat_item {
WB_RECLAIMABLE,
WB_WRITEBACK,
@@ -122,8 +117,6 @@ struct bdi_writeback {
atomic_t writeback_inodes; /* number of inodes under writeback */
struct percpu_counter stat[NR_WB_STAT_ITEMS];
unsigned long congested; /* WB_[a]sync_congested flags */
unsigned long bw_time_stamp; /* last time write bw is updated */
unsigned long dirtied_stamp;
unsigned long written_stamp; /* pages written at bw_time_stamp */

23
include/linux/backing-dev.h
View File

@@ -140,12 +140,6 @@ static inline bool mapping_can_writeback(struct address_space *mapping)
return inode_to_bdi(mapping->host)->capabilities & BDI_CAP_WRITEBACK;
}
static inline int bdi_sched_wait(void *word)
{
schedule();
return 0;
}
#ifdef CONFIG_CGROUP_WRITEBACK
struct bdi_writeback *wb_get_lookup(struct backing_dev_info *bdi,
@@ -235,18 +229,6 @@ wb_get_create_current(struct backing_dev_info *bdi, gfp_t gfp)
return wb;
}
/**
* inode_to_wb_is_valid - test whether an inode has a wb associated
* @inode: inode of interest
*
* Returns %true if @inode has a wb associated. May be called without any
* locking.
*/
static inline bool inode_to_wb_is_valid(struct inode *inode)
{
return inode->i_wb;
}
/**
* inode_to_wb - determine the wb of an inode
* @inode: inode of interest
@@ -345,11 +327,6 @@ wb_get_create_current(struct backing_dev_info *bdi, gfp_t gfp)
return &bdi->wb;
}
static inline bool inode_to_wb_is_valid(struct inode *inode)
{
return true;
}
static inline struct bdi_writeback *inode_to_wb(struct inode *inode)
{
return &inode_to_bdi(inode)->wb;

6
include/linux/balloon_compaction.h
View File

@@ -57,7 +57,6 @@ struct balloon_dev_info {
struct list_head pages; /* Pages enqueued & handled to Host */
int (*migratepage)(struct balloon_dev_info *, struct page *newpage,
struct page *page, enum migrate_mode mode);
struct inode *inode;
};
extern struct page *balloon_page_alloc(void);
@@ -75,11 +74,10 @@ static inline void balloon_devinfo_init(struct balloon_dev_info *balloon)
spin_lock_init(&balloon->pages_lock);
INIT_LIST_HEAD(&balloon->pages);
balloon->migratepage = NULL;
balloon->inode = NULL;
}
#ifdef CONFIG_BALLOON_COMPACTION
extern const struct address_space_operations balloon_aops;
extern const struct movable_operations balloon_mops;
/*
* balloon_page_insert - insert a page into the balloon's page list and make
@@ -94,7 +92,7 @@ static inline void balloon_page_insert(struct balloon_dev_info *balloon,
struct page *page)
{
__SetPageOffline(page);
__SetPageMovable(page, balloon->inode->i_mapping);
__SetPageMovable(page, &balloon_mops);
set_page_private(page, (unsigned long)balloon);
list_add(&page->lru, &balloon->pages);
}

16
include/linux/base64.h Normal file
View File

@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0
/*
* base64 encoding, lifted from fs/crypto/fname.c.
*/
#ifndef _LINUX_BASE64_H
#define _LINUX_BASE64_H
#include <linux/types.h>
#define BASE64_CHARS(nbytes) DIV_ROUND_UP((nbytes) * 4, 3)
int base64_encode(const u8 *src, int len, char *dst);
int base64_decode(const char *src, int len, u8 *dst);
#endif /* _LINUX_BASE64_H */

10
include/linux/bio.h
View File

@@ -405,7 +405,7 @@ extern void bioset_exit(struct bio_set *);
extern int biovec_init_pool(mempool_t *pool, int pool_entries);
struct bio *bio_alloc_bioset(struct block_device *bdev, unsigned short nr_vecs,
unsigned int opf, gfp_t gfp_mask,
blk_opf_t opf, gfp_t gfp_mask,
struct bio_set *bs);
struct bio *bio_kmalloc(unsigned short nr_vecs, gfp_t gfp_mask);
extern void bio_put(struct bio *);
@@ -418,7 +418,7 @@ int bio_init_clone(struct block_device *bdev, struct bio *bio,
extern struct bio_set fs_bio_set;
static inline struct bio *bio_alloc(struct block_device *bdev,
unsigned short nr_vecs, unsigned int opf, gfp_t gfp_mask)
unsigned short nr_vecs, blk_opf_t opf, gfp_t gfp_mask)
{
return bio_alloc_bioset(bdev, nr_vecs, opf, gfp_mask, &fs_bio_set);
}
@@ -456,9 +456,9 @@ struct request_queue;
extern int submit_bio_wait(struct bio *bio);
void bio_init(struct bio *bio, struct block_device *bdev, struct bio_vec *table,
unsigned short max_vecs, unsigned int opf);
unsigned short max_vecs, blk_opf_t opf);
extern void bio_uninit(struct bio *);
void bio_reset(struct bio *bio, struct block_device *bdev, unsigned int opf);
void bio_reset(struct bio *bio, struct block_device *bdev, blk_opf_t opf);
void bio_chain(struct bio *, struct bio *);
int bio_add_page(struct bio *, struct page *, unsigned len, unsigned off);
@@ -789,6 +789,6 @@ static inline void bio_clear_polled(struct bio *bio)
}
struct bio *blk_next_bio(struct bio *bio, struct block_device *bdev,
unsigned int nr_pages, unsigned int opf, gfp_t gfp);
unsigned int nr_pages, blk_opf_t opf, gfp_t gfp);
#endif /* __LINUX_BIO_H */

37
include/linux/bitmap.h
View File

@@ -71,9 +71,9 @@ struct device;
* bitmap_release_region(bitmap, pos, order) Free specified bit region
* bitmap_allocate_region(bitmap, pos, order) Allocate specified bit region
* bitmap_from_arr32(dst, buf, nbits) Copy nbits from u32[] buf to dst
* bitmap_from_arr64(dst, buf, nbits) Copy nbits from u64[] buf to dst
* bitmap_to_arr32(buf, src, nbits) Copy nbits from buf to u32[] dst
* bitmap_to_arr64(buf, src, nbits) Copy nbits from buf to u64[] dst
* bitmap_to_arr64(buf, src, nbits) Copy nbits from buf to u64[] dst
* bitmap_get_value8(map, start) Get 8bit value from map at start
* bitmap_set_value8(map, value, start) Set 8bit value to map at start
*
@@ -148,13 +148,13 @@ void __bitmap_shift_left(unsigned long *dst, const unsigned long *src,
unsigned int shift, unsigned int nbits);
void bitmap_cut(unsigned long *dst, const unsigned long *src,
unsigned int first, unsigned int cut, unsigned int nbits);
int __bitmap_and(unsigned long *dst, const unsigned long *bitmap1,
bool __bitmap_and(unsigned long *dst, const unsigned long *bitmap1,
const unsigned long *bitmap2, unsigned int nbits);
void __bitmap_or(unsigned long *dst, const unsigned long *bitmap1,
const unsigned long *bitmap2, unsigned int nbits);
void __bitmap_xor(unsigned long *dst, const unsigned long *bitmap1,
const unsigned long *bitmap2, unsigned int nbits);
int __bitmap_andnot(unsigned long *dst, const unsigned long *bitmap1,
bool __bitmap_andnot(unsigned long *dst, const unsigned long *bitmap1,
const unsigned long *bitmap2, unsigned int nbits);
void __bitmap_replace(unsigned long *dst,
const unsigned long *old, const unsigned long *new,
@@ -163,7 +163,7 @@ bool __bitmap_intersects(const unsigned long *bitmap1,
const unsigned long *bitmap2, unsigned int nbits);
bool __bitmap_subset(const unsigned long *bitmap1,
const unsigned long *bitmap2, unsigned int nbits);
int __bitmap_weight(const unsigned long *bitmap, unsigned int nbits);
unsigned int __bitmap_weight(const unsigned long *bitmap, unsigned int nbits);
void __bitmap_set(unsigned long *map, unsigned int start, int len);
void __bitmap_clear(unsigned long *map, unsigned int start, int len);
@@ -238,20 +238,32 @@ extern int bitmap_print_list_to_buf(char *buf, const unsigned long *maskp,
static inline void bitmap_zero(unsigned long *dst, unsigned int nbits)
{
unsigned int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long);
memset(dst, 0, len);
if (small_const_nbits(nbits))
*dst = 0;
else
memset(dst, 0, len);
}
static inline void bitmap_fill(unsigned long *dst, unsigned int nbits)
{
unsigned int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long);
memset(dst, 0xff, len);
if (small_const_nbits(nbits))
*dst = ~0UL;
else
memset(dst, 0xff, len);
}
static inline void bitmap_copy(unsigned long *dst, const unsigned long *src,
unsigned int nbits)
{
unsigned int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long);
memcpy(dst, src, len);
if (small_const_nbits(nbits))
*dst = *src;
else
memcpy(dst, src, len);
}
/*
@@ -303,7 +315,7 @@ void bitmap_to_arr64(u64 *buf, const unsigned long *bitmap, unsigned int nbits);
bitmap_copy_clear_tail((unsigned long *)(buf), (const unsigned long *)(bitmap), (nbits))
#endif
static inline int bitmap_and(unsigned long *dst, const unsigned long *src1,
static inline bool bitmap_and(unsigned long *dst, const unsigned long *src1,
const unsigned long *src2, unsigned int nbits)
{
if (small_const_nbits(nbits))
@@ -329,7 +341,7 @@ static inline void bitmap_xor(unsigned long *dst, const unsigned long *src1,
__bitmap_xor(dst, src1, src2, nbits);
}
static inline int bitmap_andnot(unsigned long *dst, const unsigned long *src1,
static inline bool bitmap_andnot(unsigned long *dst, const unsigned long *src1,
const unsigned long *src2, unsigned int nbits)
{
if (small_const_nbits(nbits))
@@ -419,7 +431,8 @@ static inline bool bitmap_full(const unsigned long *src, unsigned int nbits)
return find_first_zero_bit(src, nbits) == nbits;
}
static __always_inline int bitmap_weight(const unsigned long *src, unsigned int nbits)
static __always_inline
unsigned int bitmap_weight(const unsigned long *src, unsigned int nbits)
{
if (small_const_nbits(nbits))
return hweight_long(*src & BITMAP_LAST_WORD_MASK(nbits));
@@ -431,6 +444,8 @@ static __always_inline void bitmap_set(unsigned long *map, unsigned int start,
{
if (__builtin_constant_p(nbits) && nbits == 1)
__set_bit(start, map);
else if (small_const_nbits(start + nbits))
*map |= GENMASK(start + nbits - 1, start);
else if (__builtin_constant_p(start & BITMAP_MEM_MASK) &&
IS_ALIGNED(start, BITMAP_MEM_ALIGNMENT) &&
__builtin_constant_p(nbits & BITMAP_MEM_MASK) &&
@@ -445,6 +460,8 @@ static __always_inline void bitmap_clear(unsigned long *map, unsigned int start,
{
if (__builtin_constant_p(nbits) && nbits == 1)
__clear_bit(start, map);
else if (small_const_nbits(start + nbits))
*map &= ~GENMASK(start + nbits - 1, start);
else if (__builtin_constant_p(start & BITMAP_MEM_MASK) &&
IS_ALIGNED(start, BITMAP_MEM_ALIGNMENT) &&
__builtin_constant_p(nbits & BITMAP_MEM_MASK) &&

51
include/linux/bitops.h
View File

@@ -26,12 +26,63 @@ extern unsigned int __sw_hweight16(unsigned int w);
extern unsigned int __sw_hweight32(unsigned int w);
extern unsigned long __sw_hweight64(__u64 w);
/*
* Defined here because those may be needed by architecture-specific static
* inlines.
*/
#include <asm-generic/bitops/generic-non-atomic.h>
/*
* Many architecture-specific non-atomic bitops contain inline asm code and due
* to that the compiler can't optimize them to compile-time expressions or
* constants. In contrary, generic_*() helpers are defined in pure C and
* compilers optimize them just well.
* Therefore, to make `unsigned long foo = 0; __set_bit(BAR, &foo)` effectively
* equal to `unsigned long foo = BIT(BAR)`, pick the generic C alternative when
* the arguments can be resolved at compile time. That expression itself is a
* constant and doesn't bring any functional changes to the rest of cases.
* The casts to `uintptr_t` are needed to mitigate `-Waddress` warnings when
* passing a bitmap from .bss or .data (-> `!!addr` is always true).
*/
#define bitop(op, nr, addr) \
((__builtin_constant_p(nr) && \
__builtin_constant_p((uintptr_t)(addr) != (uintptr_t)NULL) && \
(uintptr_t)(addr) != (uintptr_t)NULL && \
__builtin_constant_p(*(const unsigned long *)(addr))) ? \
const##op(nr, addr) : op(nr, addr))
#define __set_bit(nr, addr) bitop(___set_bit, nr, addr)
#define __clear_bit(nr, addr) bitop(___clear_bit, nr, addr)
#define __change_bit(nr, addr) bitop(___change_bit, nr, addr)
#define __test_and_set_bit(nr, addr) bitop(___test_and_set_bit, nr, addr)
#define __test_and_clear_bit(nr, addr) bitop(___test_and_clear_bit, nr, addr)
#define __test_and_change_bit(nr, addr) bitop(___test_and_change_bit, nr, addr)
#define test_bit(nr, addr) bitop(_test_bit, nr, addr)
#define test_bit_acquire(nr, addr) bitop(_test_bit_acquire, nr, addr)
/*
* Include this here because some architectures need generic_ffs/fls in
* scope
*/
#include <asm/bitops.h>
/* Check that the bitops prototypes are sane */
#define __check_bitop_pr(name) \
static_assert(__same_type(arch_##name, generic_##name) && \
__same_type(const_##name, generic_##name) && \
__same_type(_##name, generic_##name))
__check_bitop_pr(__set_bit);
__check_bitop_pr(__clear_bit);
__check_bitop_pr(__change_bit);
__check_bitop_pr(__test_and_set_bit);
__check_bitop_pr(__test_and_clear_bit);
__check_bitop_pr(__test_and_change_bit);
__check_bitop_pr(test_bit);
#undef __check_bitop_pr
static inline int get_bitmask_order(unsigned int count)
{
int order;

35
include/linux/blk-mq.h
View File

@@ -57,6 +57,7 @@ typedef __u32 __bitwise req_flags_t;
#define RQF_TIMED_OUT ((__force req_flags_t)(1 << 21))
/* queue has elevator attached */
#define RQF_ELV ((__force req_flags_t)(1 << 22))
#define RQF_RESV ((__force req_flags_t)(1 << 23))
/* flags that prevent us from merging requests: */
#define RQF_NOMERGE_FLAGS \
@@ -79,7 +80,7 @@ struct request {
struct blk_mq_ctx *mq_ctx;
struct blk_mq_hw_ctx *mq_hctx;
unsigned int cmd_flags; /* op and common flags */
blk_opf_t cmd_flags; /* op and common flags */
req_flags_t rq_flags;
int tag;
@@ -197,8 +198,10 @@ struct request {
void *end_io_data;
};
#define req_op(req) \
((req)->cmd_flags & REQ_OP_MASK)
static inline enum req_op req_op(const struct request *req)
{
return req->cmd_flags & REQ_OP_MASK;
}
static inline bool blk_rq_is_passthrough(struct request *rq)
{
@@ -519,7 +522,7 @@ struct blk_mq_queue_data {
bool last;
};
typedef bool (busy_tag_iter_fn)(struct request *, void *, bool);
typedef bool (busy_tag_iter_fn)(struct request *, void *);
/**
* struct blk_mq_ops - Callback functions that implements block driver
@@ -574,7 +577,7 @@ struct blk_mq_ops {
/**
* @timeout: Called on request timeout.
*/
enum blk_eh_timer_return (*timeout)(struct request *, bool);
enum blk_eh_timer_return (*timeout)(struct request *);
/**
* @poll: Called to poll for completion of a specific tag.
@@ -686,10 +689,12 @@ struct gendisk *__blk_mq_alloc_disk(struct blk_mq_tag_set *set, void *queuedata,
\
__blk_mq_alloc_disk(set, queuedata, &__key); \
})
struct gendisk *blk_mq_alloc_disk_for_queue(struct request_queue *q,
struct lock_class_key *lkclass);
struct request_queue *blk_mq_init_queue(struct blk_mq_tag_set *);
int blk_mq_init_allocated_queue(struct blk_mq_tag_set *set,
struct request_queue *q);
void blk_mq_unregister_dev(struct device *, struct request_queue *);
void blk_mq_destroy_queue(struct request_queue *);
int blk_mq_alloc_tag_set(struct blk_mq_tag_set *set);
int blk_mq_alloc_sq_tag_set(struct blk_mq_tag_set *set,
@@ -710,10 +715,10 @@ enum {
BLK_MQ_REQ_PM = (__force blk_mq_req_flags_t)(1 << 2),
};
struct request *blk_mq_alloc_request(struct request_queue *q, unsigned int op,
struct request *blk_mq_alloc_request(struct request_queue *q, blk_opf_t opf,
blk_mq_req_flags_t flags);
struct request *blk_mq_alloc_request_hctx(struct request_queue *q,
unsigned int op, blk_mq_req_flags_t flags,
blk_opf_t opf, blk_mq_req_flags_t flags,
unsigned int hctx_idx);
/*
@@ -823,6 +828,11 @@ static inline bool blk_mq_need_time_stamp(struct request *rq)
return (rq->rq_flags & (RQF_IO_STAT | RQF_STATS | RQF_ELV));
}
static inline bool blk_mq_is_reserved_rq(struct request *rq)
{
return rq->rq_flags & RQF_RESV;
}
/*
* Batched completions only work when there is no I/O error and no special
* ->end_io handler.
@@ -847,7 +857,6 @@ void blk_mq_kick_requeue_list(struct request_queue *q);
void blk_mq_delay_kick_requeue_list(struct request_queue *q, unsigned long msecs);
void blk_mq_complete_request(struct request *rq);
bool blk_mq_complete_request_remote(struct request *rq);
bool blk_mq_queue_stopped(struct request_queue *q);
void blk_mq_stop_hw_queue(struct blk_mq_hw_ctx *hctx);
void blk_mq_start_hw_queue(struct blk_mq_hw_ctx *hctx);
void blk_mq_stop_hw_queues(struct request_queue *q);
@@ -1121,12 +1130,12 @@ void blk_dump_rq_flags(struct request *, char *);
#ifdef CONFIG_BLK_DEV_ZONED
static inline unsigned int blk_rq_zone_no(struct request *rq)
{
return blk_queue_zone_no(rq->q, blk_rq_pos(rq));
return disk_zone_no(rq->q->disk, blk_rq_pos(rq));
}
static inline unsigned int blk_rq_zone_is_seq(struct request *rq)
{
return blk_queue_zone_is_seq(rq->q, blk_rq_pos(rq));
return disk_zone_is_seq(rq->q->disk, blk_rq_pos(rq));
}
bool blk_req_needs_zone_write_lock(struct request *rq);
@@ -1148,8 +1157,8 @@ static inline void blk_req_zone_write_unlock(struct request *rq)
static inline bool blk_req_zone_is_write_locked(struct request *rq)
{
return rq->q->seq_zones_wlock &&
test_bit(blk_rq_zone_no(rq), rq->q->seq_zones_wlock);
return rq->q->disk->seq_zones_wlock &&
test_bit(blk_rq_zone_no(rq), rq->q->disk->seq_zones_wlock);
}
static inline bool blk_req_can_dispatch_to_zone(struct request *rq)

115
include/linux/blk_types.h
View File

@@ -240,6 +240,8 @@ static inline void bio_issue_init(struct bio_issue *issue,
((u64)size << BIO_ISSUE_SIZE_SHIFT));
}
typedef __u32 __bitwise blk_opf_t;
typedef unsigned int blk_qc_t;
#define BLK_QC_T_NONE -1U
@@ -250,7 +252,7 @@ typedef unsigned int blk_qc_t;
struct bio {
struct bio *bi_next; /* request queue link */
struct block_device *bi_bdev;
unsigned int bi_opf; /* bottom bits REQ_OP, top bits
blk_opf_t bi_opf; /* bottom bits REQ_OP, top bits
* req_flags.
*/
unsigned short bi_flags; /* BIO_* below */
@@ -337,8 +339,12 @@ enum {
typedef __u32 __bitwise blk_mq_req_flags_t;
/*
* Operations and flags common to the bio and request structures.
#define REQ_OP_BITS 8
#define REQ_OP_MASK (__force blk_opf_t)((1 << REQ_OP_BITS) - 1)
#define REQ_FLAG_BITS 24
/**
* enum req_op - Operations common to the bio and request structures.
* We use 8 bits for encoding the operation, and the remaining 24 for flags.
*
* The least significant bit of the operation number indicates the data
@@ -350,41 +356,37 @@ typedef __u32 __bitwise blk_mq_req_flags_t;
* If a operation does not transfer data the least significant bit has no
* meaning.
*/
#define REQ_OP_BITS 8
#define REQ_OP_MASK ((1 << REQ_OP_BITS) - 1)
#define REQ_FLAG_BITS 24
enum req_opf {
enum req_op {
/* read sectors from the device */
REQ_OP_READ = 0,
REQ_OP_READ = (__force blk_opf_t)0,
/* write sectors to the device */
REQ_OP_WRITE = 1,
REQ_OP_WRITE = (__force blk_opf_t)1,
/* flush the volatile write cache */
REQ_OP_FLUSH = 2,
REQ_OP_FLUSH = (__force blk_opf_t)2,
/* discard sectors */
REQ_OP_DISCARD = 3,
REQ_OP_DISCARD = (__force blk_opf_t)3,
/* securely erase sectors */
REQ_OP_SECURE_ERASE = 5,
REQ_OP_SECURE_ERASE = (__force blk_opf_t)5,
/* write the zero filled sector many times */
REQ_OP_WRITE_ZEROES = 9,
REQ_OP_WRITE_ZEROES = (__force blk_opf_t)9,
/* Open a zone */
REQ_OP_ZONE_OPEN = 10,
REQ_OP_ZONE_OPEN = (__force blk_opf_t)10,
/* Close a zone */
REQ_OP_ZONE_CLOSE = 11,
REQ_OP_ZONE_CLOSE = (__force blk_opf_t)11,
/* Transition a zone to full */
REQ_OP_ZONE_FINISH = 12,
REQ_OP_ZONE_FINISH = (__force blk_opf_t)12,
/* write data at the current zone write pointer */
REQ_OP_ZONE_APPEND = 13,
REQ_OP_ZONE_APPEND = (__force blk_opf_t)13,
/* reset a zone write pointer */
REQ_OP_ZONE_RESET = 15,
REQ_OP_ZONE_RESET = (__force blk_opf_t)15,
/* reset all the zone present on the device */
REQ_OP_ZONE_RESET_ALL = 17,
REQ_OP_ZONE_RESET_ALL = (__force blk_opf_t)17,
/* Driver private requests */
REQ_OP_DRV_IN = 34,
REQ_OP_DRV_OUT = 35,
REQ_OP_DRV_IN = (__force blk_opf_t)34,
REQ_OP_DRV_OUT = (__force blk_opf_t)35,
REQ_OP_LAST,
REQ_OP_LAST = (__force blk_opf_t)36,
};
enum req_flag_bits {
@@ -425,28 +427,31 @@ enum req_flag_bits {
__REQ_NR_BITS, /* stops here */
};
#define REQ_FAILFAST_DEV (1ULL << __REQ_FAILFAST_DEV)
#define REQ_FAILFAST_TRANSPORT (1ULL << __REQ_FAILFAST_TRANSPORT)
#define REQ_FAILFAST_DRIVER (1ULL << __REQ_FAILFAST_DRIVER)
#define REQ_SYNC (1ULL << __REQ_SYNC)
#define REQ_META (1ULL << __REQ_META)
#define REQ_PRIO (1ULL << __REQ_PRIO)
#define REQ_NOMERGE (1ULL << __REQ_NOMERGE)
#define REQ_IDLE (1ULL << __REQ_IDLE)
#define REQ_INTEGRITY (1ULL << __REQ_INTEGRITY)
#define REQ_FUA (1ULL << __REQ_FUA)
#define REQ_PREFLUSH (1ULL << __REQ_PREFLUSH)
#define REQ_RAHEAD (1ULL << __REQ_RAHEAD)
#define REQ_BACKGROUND (1ULL << __REQ_BACKGROUND)
#define REQ_NOWAIT (1ULL << __REQ_NOWAIT)
#define REQ_CGROUP_PUNT (1ULL << __REQ_CGROUP_PUNT)
#define REQ_FAILFAST_DEV \
(__force blk_opf_t)(1ULL << __REQ_FAILFAST_DEV)
#define REQ_FAILFAST_TRANSPORT \
(__force blk_opf_t)(1ULL << __REQ_FAILFAST_TRANSPORT)
#define REQ_FAILFAST_DRIVER \
(__force blk_opf_t)(1ULL << __REQ_FAILFAST_DRIVER)
#define REQ_SYNC (__force blk_opf_t)(1ULL << __REQ_SYNC)
#define REQ_META (__force blk_opf_t)(1ULL << __REQ_META)
#define REQ_PRIO (__force blk_opf_t)(1ULL << __REQ_PRIO)
#define REQ_NOMERGE (__force blk_opf_t)(1ULL << __REQ_NOMERGE)
#define REQ_IDLE (__force blk_opf_t)(1ULL << __REQ_IDLE)
#define REQ_INTEGRITY (__force blk_opf_t)(1ULL << __REQ_INTEGRITY)
#define REQ_FUA (__force blk_opf_t)(1ULL << __REQ_FUA)
#define REQ_PREFLUSH (__force blk_opf_t)(1ULL << __REQ_PREFLUSH)
#define REQ_RAHEAD (__force blk_opf_t)(1ULL << __REQ_RAHEAD)
#define REQ_BACKGROUND (__force blk_opf_t)(1ULL << __REQ_BACKGROUND)
#define REQ_NOWAIT (__force blk_opf_t)(1ULL << __REQ_NOWAIT)
#define REQ_CGROUP_PUNT (__force blk_opf_t)(1ULL << __REQ_CGROUP_PUNT)
#define REQ_NOUNMAP (1ULL << __REQ_NOUNMAP)
#define REQ_POLLED (1ULL << __REQ_POLLED)
#define REQ_ALLOC_CACHE (1ULL << __REQ_ALLOC_CACHE)
#define REQ_NOUNMAP (__force blk_opf_t)(1ULL << __REQ_NOUNMAP)
#define REQ_POLLED (__force blk_opf_t)(1ULL << __REQ_POLLED)
#define REQ_ALLOC_CACHE (__force blk_opf_t)(1ULL << __REQ_ALLOC_CACHE)
#define REQ_DRV (1ULL << __REQ_DRV)
#define REQ_SWAP (1ULL << __REQ_SWAP)
#define REQ_DRV (__force blk_opf_t)(1ULL << __REQ_DRV)
#define REQ_SWAP (__force blk_opf_t)(1ULL << __REQ_SWAP)
#define REQ_FAILFAST_MASK \
(REQ_FAILFAST_DEV | REQ_FAILFAST_TRANSPORT | REQ_FAILFAST_DRIVER)
@@ -463,26 +468,28 @@ enum stat_group {
NR_STAT_GROUPS
};
#define bio_op(bio) \
((bio)->bi_opf & REQ_OP_MASK)
static inline enum req_op bio_op(const struct bio *bio)
{
return bio->bi_opf & REQ_OP_MASK;
}
/* obsolete, don't use in new code */
static inline void bio_set_op_attrs(struct bio *bio, unsigned op,
unsigned op_flags)
static inline void bio_set_op_attrs(struct bio *bio, enum req_op op,
blk_opf_t op_flags)
{
bio->bi_opf = op | op_flags;
}
static inline bool op_is_write(unsigned int op)
static inline bool op_is_write(blk_opf_t op)
{
return (op & 1);
return !!(op & (__force blk_opf_t)1);
}
/*
* Check if the bio or request is one that needs special treatment in the
* flush state machine.
*/
static inline bool op_is_flush(unsigned int op)
static inline bool op_is_flush(blk_opf_t op)
{
return op & (REQ_FUA | REQ_PREFLUSH);
}
@@ -492,13 +499,13 @@ static inline bool op_is_flush(unsigned int op)
* PREFLUSH flag. Other operations may be marked as synchronous using the
* REQ_SYNC flag.
*/
static inline bool op_is_sync(unsigned int op)
static inline bool op_is_sync(blk_opf_t op)
{
return (op & REQ_OP_MASK) == REQ_OP_READ ||
(op & (REQ_SYNC | REQ_FUA | REQ_PREFLUSH));
}
static inline bool op_is_discard(unsigned int op)
static inline bool op_is_discard(blk_opf_t op)
{
return (op & REQ_OP_MASK) == REQ_OP_DISCARD;
}
@@ -509,7 +516,7 @@ static inline bool op_is_discard(unsigned int op)
* due to its different handling in the block layer and device response in
* case of command failure.
*/
static inline bool op_is_zone_mgmt(enum req_opf op)
static inline bool op_is_zone_mgmt(enum req_op op)
{
switch (op & REQ_OP_MASK) {
case REQ_OP_ZONE_RESET:
@@ -522,7 +529,7 @@ static inline bool op_is_zone_mgmt(enum req_opf op)
}
}
static inline int op_stat_group(unsigned int op)
static inline int op_stat_group(enum req_op op)
{
if (op_is_discard(op))
return STAT_DISCARD;

244
include/linux/blkdev.h
View File

@@ -140,6 +140,8 @@ struct gendisk {
struct request_queue *queue;
void *private_data;
struct bio_set bio_split;
int flags;
unsigned long state;
#define GD_NEED_PART_SCAN 0
@@ -148,6 +150,7 @@ struct gendisk {
#define GD_NATIVE_CAPACITY 3
#define GD_ADDED 4
#define GD_SUPPRESS_PART_SCAN 5
#define GD_OWNS_QUEUE 6
struct mutex open_mutex; /* open/close mutex */
unsigned open_partitions; /* number of open partitions */
@@ -163,6 +166,29 @@ struct gendisk {
#ifdef CONFIG_BLK_DEV_INTEGRITY
struct kobject integrity_kobj;
#endif /* CONFIG_BLK_DEV_INTEGRITY */
#ifdef CONFIG_BLK_DEV_ZONED
/*
* Zoned block device information for request dispatch control.
* nr_zones is the total number of zones of the device. This is always
* 0 for regular block devices. conv_zones_bitmap is a bitmap of nr_zones
* bits which indicates if a zone is conventional (bit set) or
* sequential (bit clear). seq_zones_wlock is a bitmap of nr_zones
* bits which indicates if a zone is write locked, that is, if a write
* request targeting the zone was dispatched.
*
* Reads of this information must be protected with blk_queue_enter() /
* blk_queue_exit(). Modifying this information is only allowed while
* no requests are being processed. See also blk_mq_freeze_queue() and
* blk_mq_unfreeze_queue().
*/
unsigned int nr_zones;
unsigned int max_open_zones;
unsigned int max_active_zones;
unsigned long *conv_zones_bitmap;
unsigned long *seq_zones_wlock;
#endif /* CONFIG_BLK_DEV_ZONED */
#if IS_ENABLED(CONFIG_CDROM)
struct cdrom_device_info *cdi;
#endif
@@ -170,6 +196,12 @@ struct gendisk {
struct badblocks *bb;
struct lockdep_map lockdep_map;
u64 diskseq;
/*
* Independent sector access ranges. This is always NULL for
* devices that do not have multiple independent access ranges.
*/
struct blk_independent_access_ranges *ia_ranges;
};
static inline bool disk_live(struct gendisk *disk)
@@ -220,7 +252,7 @@ static inline int blk_validate_block_size(unsigned long bsize)
return 0;
}
static inline bool blk_op_is_passthrough(unsigned int op)
static inline bool blk_op_is_passthrough(blk_opf_t op)
{
op &= REQ_OP_MASK;
return op == REQ_OP_DRV_IN || op == REQ_OP_DRV_OUT;
@@ -284,15 +316,15 @@ struct queue_limits {
typedef int (*report_zones_cb)(struct blk_zone *zone, unsigned int idx,
void *data);
void blk_queue_set_zoned(struct gendisk *disk, enum blk_zoned_model model);
void disk_set_zoned(struct gendisk *disk, enum blk_zoned_model model);
#ifdef CONFIG_BLK_DEV_ZONED
#define BLK_ALL_ZONES ((unsigned int)-1)
int blkdev_report_zones(struct block_device *bdev, sector_t sector,
unsigned int nr_zones, report_zones_cb cb, void *data);
unsigned int blkdev_nr_zones(struct gendisk *disk);
extern int blkdev_zone_mgmt(struct block_device *bdev, enum req_opf op,
unsigned int bdev_nr_zones(struct block_device *bdev);
extern int blkdev_zone_mgmt(struct block_device *bdev, enum req_op op,
sector_t sectors, sector_t nr_sectors,
gfp_t gfp_mask);
int blk_revalidate_disk_zones(struct gendisk *disk,
@@ -305,7 +337,7 @@ extern int blkdev_zone_mgmt_ioctl(struct block_device *bdev, fmode_t mode,
#else /* CONFIG_BLK_DEV_ZONED */
static inline unsigned int blkdev_nr_zones(struct gendisk *disk)
static inline unsigned int bdev_nr_zones(struct block_device *bdev)
{
return 0;
}
@@ -424,6 +456,11 @@ struct request_queue {
unsigned long nr_requests; /* Max # of requests */
unsigned int dma_pad_mask;
/*
* Drivers that set dma_alignment to less than 511 must be prepared to
* handle individual bvec's that are not a multiple of a SECTOR_SIZE
* due to possible offsets.
*/
unsigned int dma_alignment;
#ifdef CONFIG_BLK_INLINE_ENCRYPTION
@@ -455,31 +492,6 @@ struct request_queue {
unsigned int required_elevator_features;
#ifdef CONFIG_BLK_DEV_ZONED
/*
* Zoned block device information for request dispatch control.
* nr_zones is the total number of zones of the device. This is always
* 0 for regular block devices. conv_zones_bitmap is a bitmap of nr_zones
* bits which indicates if a zone is conventional (bit set) or
* sequential (bit clear). seq_zones_wlock is a bitmap of nr_zones
* bits which indicates if a zone is write locked, that is, if a write
* request targeting the zone was dispatched. All three fields are
* initialized by the low level device driver (e.g. scsi/sd.c).
* Stacking drivers (device mappers) may or may not initialize
* these fields.
*
* Reads of this information must be protected with blk_queue_enter() /
* blk_queue_exit(). Modifying this information is only allowed while
* no requests are being processed. See also blk_mq_freeze_queue() and
* blk_mq_unfreeze_queue().
*/
unsigned int nr_zones;
unsigned long *conv_zones_bitmap;
unsigned long *seq_zones_wlock;
unsigned int max_open_zones;
unsigned int max_active_zones;
#endif /* CONFIG_BLK_DEV_ZONED */
int node;
#ifdef CONFIG_BLK_DEV_IO_TRACE
struct blk_trace __rcu *blk_trace;
@@ -521,7 +533,6 @@ struct request_queue {
struct blk_mq_tag_set *tag_set;
struct list_head tag_set_list;
struct bio_set bio_split;
struct dentry *debugfs_dir;
struct dentry *sched_debugfs_dir;
@@ -533,12 +544,6 @@ struct request_queue {
bool mq_sysfs_init_done;
/*
* Independent sector access ranges. This is always NULL for
* devices that do not have multiple independent access ranges.
*/
struct blk_independent_access_ranges *ia_ranges;
/**
* @srcu: Sleepable RCU. Use as lock when type of the request queue
* is blocking (BLK_MQ_F_BLOCKING). Must be the last member
@@ -559,7 +564,6 @@ struct request_queue {
#define QUEUE_FLAG_NOXMERGES 9 /* No extended merges */
#define QUEUE_FLAG_ADD_RANDOM 10 /* Contributes to random pool */
#define QUEUE_FLAG_SAME_FORCE 12 /* force complete on same CPU */
#define QUEUE_FLAG_DEAD 13 /* queue tear-down finished */
#define QUEUE_FLAG_INIT_DONE 14 /* queue is initialized */
#define QUEUE_FLAG_STABLE_WRITES 15 /* don't modify blks until WB is done */
#define QUEUE_FLAG_POLL 16 /* IO polling enabled if set */
@@ -587,7 +591,6 @@ bool blk_queue_flag_test_and_set(unsigned int flag, struct request_queue *q);
#define blk_queue_stopped(q) test_bit(QUEUE_FLAG_STOPPED, &(q)->queue_flags)
#define blk_queue_dying(q) test_bit(QUEUE_FLAG_DYING, &(q)->queue_flags)
#define blk_queue_has_srcu(q) test_bit(QUEUE_FLAG_HAS_SRCU, &(q)->queue_flags)
#define blk_queue_dead(q) test_bit(QUEUE_FLAG_DEAD, &(q)->queue_flags)
#define blk_queue_init_done(q) test_bit(QUEUE_FLAG_INIT_DONE, &(q)->queue_flags)
#define blk_queue_nomerges(q) test_bit(QUEUE_FLAG_NOMERGES, &(q)->queue_flags)
#define blk_queue_noxmerges(q) \
@@ -663,76 +666,69 @@ static inline bool blk_queue_is_zoned(struct request_queue *q)
}
}
static inline sector_t blk_queue_zone_sectors(struct request_queue *q)
{
return blk_queue_is_zoned(q) ? q->limits.chunk_sectors : 0;
}
#ifdef CONFIG_BLK_DEV_ZONED
static inline unsigned int blk_queue_nr_zones(struct request_queue *q)
static inline unsigned int disk_nr_zones(struct gendisk *disk)
{
return blk_queue_is_zoned(q) ? q->nr_zones : 0;
return blk_queue_is_zoned(disk->queue) ? disk->nr_zones : 0;
}
static inline unsigned int blk_queue_zone_no(struct request_queue *q,
sector_t sector)
static inline unsigned int disk_zone_no(struct gendisk *disk, sector_t sector)
{
if (!blk_queue_is_zoned(q))
if (!blk_queue_is_zoned(disk->queue))
return 0;
return sector >> ilog2(q->limits.chunk_sectors);
return sector >> ilog2(disk->queue->limits.chunk_sectors);
}
static inline bool blk_queue_zone_is_seq(struct request_queue *q,
sector_t sector)
static inline bool disk_zone_is_seq(struct gendisk *disk, sector_t sector)
{
if (!blk_queue_is_zoned(q))
if (!blk_queue_is_zoned(disk->queue))
return false;
if (!q->conv_zones_bitmap)
if (!disk->conv_zones_bitmap)
return true;
return !test_bit(blk_queue_zone_no(q, sector), q->conv_zones_bitmap);
return !test_bit(disk_zone_no(disk, sector), disk->conv_zones_bitmap);
}
static inline void blk_queue_max_open_zones(struct request_queue *q,
static inline void disk_set_max_open_zones(struct gendisk *disk,
unsigned int max_open_zones)
{
q->max_open_zones = max_open_zones;
disk->max_open_zones = max_open_zones;
}
static inline unsigned int queue_max_open_zones(const struct request_queue *q)
{
return q->max_open_zones;
}
static inline void blk_queue_max_active_zones(struct request_queue *q,
static inline void disk_set_max_active_zones(struct gendisk *disk,
unsigned int max_active_zones)
{
q->max_active_zones = max_active_zones;
disk->max_active_zones = max_active_zones;
}
static inline unsigned int queue_max_active_zones(const struct request_queue *q)
static inline unsigned int bdev_max_open_zones(struct block_device *bdev)
{
return q->max_active_zones;
return bdev->bd_disk->max_open_zones;
}
static inline unsigned int bdev_max_active_zones(struct block_device *bdev)
{
return bdev->bd_disk->max_active_zones;
}
#else /* CONFIG_BLK_DEV_ZONED */
static inline unsigned int blk_queue_nr_zones(struct request_queue *q)
static inline unsigned int disk_nr_zones(struct gendisk *disk)
{
return 0;
}
static inline bool blk_queue_zone_is_seq(struct request_queue *q,
sector_t sector)
static inline bool disk_zone_is_seq(struct gendisk *disk, sector_t sector)
{
return false;
}
static inline unsigned int blk_queue_zone_no(struct request_queue *q,
sector_t sector)
static inline unsigned int disk_zone_no(struct gendisk *disk, sector_t sector)
{
return 0;
}
static inline unsigned int queue_max_open_zones(const struct request_queue *q)
static inline unsigned int bdev_max_open_zones(struct block_device *bdev)
{
return 0;
}
static inline unsigned int queue_max_active_zones(const struct request_queue *q)
static inline unsigned int bdev_max_active_zones(struct block_device *bdev)
{
return 0;
}
@@ -812,8 +808,6 @@ static inline u64 sb_bdev_nr_blocks(struct super_block *sb)
int bdev_disk_changed(struct gendisk *disk, bool invalidate);
struct gendisk *__alloc_disk_node(struct request_queue *q, int node_id,
struct lock_class_key *lkclass);
void put_disk(struct gendisk *disk);
struct gendisk *__blk_alloc_disk(int node, struct lock_class_key *lkclass);
@@ -832,7 +826,6 @@ struct gendisk *__blk_alloc_disk(int node, struct lock_class_key *lkclass);
\
__blk_alloc_disk(node_id, &__key); \
})
void blk_cleanup_disk(struct gendisk *disk);
int __register_blkdev(unsigned int major, const char *name,
void (*probe)(dev_t devt));
@@ -872,15 +865,15 @@ void blk_request_module(dev_t devt);
extern int blk_register_queue(struct gendisk *disk);
extern void blk_unregister_queue(struct gendisk *disk);
void submit_bio_noacct(struct bio *bio);
struct bio *bio_split_to_limits(struct bio *bio);
extern int blk_lld_busy(struct request_queue *q);
extern void blk_queue_split(struct bio **);
extern int blk_queue_enter(struct request_queue *q, blk_mq_req_flags_t flags);
extern void blk_queue_exit(struct request_queue *q);
extern void blk_sync_queue(struct request_queue *q);
/* Helper to convert REQ_OP_XXX to its string format XXX */
extern const char *blk_op_str(unsigned int op);
extern const char *blk_op_str(enum req_op op);
int blk_status_to_errno(blk_status_t status);
blk_status_t errno_to_blk_status(int errno);
@@ -898,64 +891,33 @@ static inline struct request_queue *bdev_get_queue(struct block_device *bdev)
return bdev->bd_queue; /* this is never NULL */
}
#ifdef CONFIG_BLK_DEV_ZONED
/* Helper to convert BLK_ZONE_ZONE_XXX to its string format XXX */
const char *blk_zone_cond_str(enum blk_zone_cond zone_cond);
static inline unsigned int bio_zone_no(struct bio *bio)
{
return blk_queue_zone_no(bdev_get_queue(bio->bi_bdev),
bio->bi_iter.bi_sector);
return disk_zone_no(bio->bi_bdev->bd_disk, bio->bi_iter.bi_sector);
}
static inline unsigned int bio_zone_is_seq(struct bio *bio)
{
return blk_queue_zone_is_seq(bdev_get_queue(bio->bi_bdev),
bio->bi_iter.bi_sector);
}
#endif /* CONFIG_BLK_DEV_ZONED */
static inline unsigned int blk_queue_get_max_sectors(struct request_queue *q,
int op)
{
if (unlikely(op == REQ_OP_DISCARD || op == REQ_OP_SECURE_ERASE))
return min(q->limits.max_discard_sectors,
UINT_MAX >> SECTOR_SHIFT);
if (unlikely(op == REQ_OP_WRITE_ZEROES))
return q->limits.max_write_zeroes_sectors;
return q->limits.max_sectors;
return disk_zone_is_seq(bio->bi_bdev->bd_disk, bio->bi_iter.bi_sector);
}
/*
* Return maximum size of a request at given offset. Only valid for
* file system requests.
* Return how much of the chunk is left to be used for I/O at a given offset.
*/
static inline unsigned int blk_max_size_offset(struct request_queue *q,
sector_t offset,
unsigned int chunk_sectors)
static inline unsigned int blk_chunk_sectors_left(sector_t offset,
unsigned int chunk_sectors)
{
if (!chunk_sectors) {
if (q->limits.chunk_sectors)
chunk_sectors = q->limits.chunk_sectors;
else
return q->limits.max_sectors;
}
if (likely(is_power_of_2(chunk_sectors)))
chunk_sectors -= offset & (chunk_sectors - 1);
else
chunk_sectors -= sector_div(offset, chunk_sectors);
return min(q->limits.max_sectors, chunk_sectors);
if (unlikely(!is_power_of_2(chunk_sectors)))
return chunk_sectors - sector_div(offset, chunk_sectors);
return chunk_sectors - (offset & (chunk_sectors - 1));
}
/*
* Access functions for manipulating queue properties
*/
extern void blk_cleanup_queue(struct request_queue *);
void blk_queue_bounce_limit(struct request_queue *q, enum blk_bounce limit);
extern void blk_queue_max_hw_sectors(struct request_queue *, unsigned int);
extern void blk_queue_chunk_sectors(struct request_queue *, unsigned int);
@@ -1206,6 +1168,11 @@ bdev_max_zone_append_sectors(struct block_device *bdev)
return queue_max_zone_append_sectors(bdev_get_queue(bdev));
}
static inline unsigned int bdev_max_segments(struct block_device *bdev)
{
return queue_max_segments(bdev_get_queue(bdev));
}
static inline unsigned queue_logical_block_size(const struct request_queue *q)
{
int retval = 512;
@@ -1337,27 +1304,9 @@ static inline sector_t bdev_zone_sectors(struct block_device *bdev)
{
struct request_queue *q = bdev_get_queue(bdev);
if (q)
return blk_queue_zone_sectors(q);
return 0;
}
static inline unsigned int bdev_max_open_zones(struct block_device *bdev)
{
struct request_queue *q = bdev_get_queue(bdev);
if (q)
return queue_max_open_zones(q);
return 0;
}
static inline unsigned int bdev_max_active_zones(struct block_device *bdev)
{
struct request_queue *q = bdev_get_queue(bdev);
if (q)
return queue_max_active_zones(q);
return 0;
if (!blk_queue_is_zoned(q))
return 0;
return q->limits.chunk_sectors;
}
static inline int queue_dma_alignment(const struct request_queue *q)
@@ -1365,6 +1314,18 @@ static inline int queue_dma_alignment(const struct request_queue *q)
return q ? q->dma_alignment : 511;
}
static inline unsigned int bdev_dma_alignment(struct block_device *bdev)
{
return queue_dma_alignment(bdev_get_queue(bdev));
}
static inline bool bdev_iter_is_aligned(struct block_device *bdev,
struct iov_iter *iter)
{
return iov_iter_is_aligned(iter, bdev_dma_alignment(bdev),
bdev_logical_block_size(bdev) - 1);
}
static inline int blk_rq_aligned(struct request_queue *q, unsigned long addr,
unsigned int len)
{
@@ -1426,7 +1387,7 @@ struct block_device_operations {
unsigned int flags);
int (*open) (struct block_device *, fmode_t);
void (*release) (struct gendisk *, fmode_t);
int (*rw_page)(struct block_device *, sector_t, struct page *, unsigned int);
int (*rw_page)(struct block_device *, sector_t, struct page *, enum req_op);
int (*ioctl) (struct block_device *, fmode_t, unsigned, unsigned long);
int (*compat_ioctl) (struct block_device *, fmode_t, unsigned, unsigned long);
unsigned int (*check_events) (struct gendisk *disk,
@@ -1479,9 +1440,9 @@ static inline void blk_wake_io_task(struct task_struct *waiter)
}
unsigned long bdev_start_io_acct(struct block_device *bdev,
unsigned int sectors, unsigned int op,
unsigned int sectors, enum req_op op,
unsigned long start_time);
void bdev_end_io_acct(struct block_device *bdev, unsigned int op,
void bdev_end_io_acct(struct block_device *bdev, enum req_op op,
unsigned long start_time);
void bio_start_io_acct_time(struct bio *bio, unsigned long start_time);
@@ -1502,7 +1463,6 @@ static inline void bio_end_io_acct(struct bio *bio, unsigned long start_time)
int bdev_read_only(struct block_device *bdev);
int set_blocksize(struct block_device *bdev, int size);
const char *bdevname(struct block_device *bdev, char *buffer);
int lookup_bdev(const char *pathname, dev_t *dev);
void blkdev_show(struct seq_file *seqf, off_t offset);

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