From e04a61c04a4ac242682820be7c89da5dbb183851 Mon Sep 17 00:00:00 2001 From: Adam Sampson Date: Fri, 23 Oct 2015 23:36:27 +0100 Subject: [PATCH 01/40] ARM: sun7i: dt: Enable audio codec on pcDuino V3 Nano The pcDuino V3 Nano has a 3.5mm TRRS jack socket for audio, using the CTIA standard pinout, connected to HPOUTL, HPOUTR, HPCOM/HPCOMFB and MICIN1/VMIC (via appropriate RC networks) on the A20. The PH00 GPIO is wired for headphone plug detection: it reads 0 when nothing's plugged in, and 1 when a plug is inserted. LINEINL/R and FMINL/R are not connected. Signed-off-by: Adam Sampson Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts index 1757a6ad74e9..ddac7328b852 100644 --- a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts @@ -82,6 +82,10 @@ &ahci { status = "okay"; }; +&codec { + status = "okay"; +}; + &cpu0 { cpu-supply = <®_dcdc2>; }; From 329f25b343c5fdd74da7a4c0520b24a732993ba8 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 23 Oct 2015 12:56:12 +0200 Subject: [PATCH 02/40] arm: sun7i: Add sun7i-a20-icnova-swac.dts This baseboard from SWAC is equipped with the ICnova-A20 SoM from Incircuit. This board is equipped with the following interfaces / devices: - 512 MiB SDRAM - 4 GiB MLC NAND (Micron MT29F32G08CBACAWP or Hynix H27UBG8T2BTR) - USB host - LCD 800x480 - HDMI - CAN Note that the NAND support is still missing. As its currently not supported in mainline for sunxi and especially for these MLC devices. The original plan was to also provide a dtsi for the ICnova SoM, to put all the SoM internal nodes / properties there. But as I don't have a clear overview of the SoM specific and baseboard specific differences, I'm putting all in one dts for now. Once somebody pushed support for some other baseboard using the A20 SoM from Incircuit (e.g. the ADB4006 reference design), this should be separated. Signed-off-by: Stefan Roese Cc: Marcus Heuer [maxime: Fixed CPU regulator upper voltage boundary] Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun7i-a20-icnova-swac.dts | 169 ++++++++++++++++++++ 2 files changed, 170 insertions(+) create mode 100644 arch/arm/boot/dts/sun7i-a20-icnova-swac.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 30bbc3746130..e8f44c705089 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -638,6 +638,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-cubietruck.dtb \ sun7i-a20-hummingbird.dtb \ sun7i-a20-i12-tvbox.dtb \ + sun7i-a20-icnova-swac.dtb \ sun7i-a20-m3.dtb \ sun7i-a20-mk808c.dtb \ sun7i-a20-olimex-som-evb.dtb \ diff --git a/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts b/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts new file mode 100644 index 000000000000..f5b5325a70e2 --- /dev/null +++ b/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts @@ -0,0 +1,169 @@ +/* + * Copyright 2015 Stefan Roese + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include +#include + +/ { + model = "ICnova-A20 SWAC"; + compatible = "swac,icnova-a20-swac", "incircuit,icnova-a20", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_mii_a>; + phy = <&phy1>; + phy-mode = "mii"; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 8 5 GPIO_ACTIVE_HIGH>; /* PI5 */ + cd-inverted; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +#include "axp209.dtsi" + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; From 5058ec4a95d1822156cc6ec5d93f4cc0c999c641 Mon Sep 17 00:00:00 2001 From: Lawrence Yu Date: Sun, 25 Oct 2015 13:49:32 -0700 Subject: [PATCH 03/40] dts: sun6i: yones toptech bs1078 v2: Add AXP221 support to dts Enable the axp221 PMIC chip in the dts file. Allows board to power off correctly from the poweroff command This board requires dc1sw to be enabled in order to provide a power source for the 5V DCDC converter that powers USB2. This board uses dldo1 for 3.3V wifi power This board requires dldo3 to be enabled at 2.8V in order to provide voltage to the pullup resistors for the i2c0 bus. Signed-off-by: Lawrence Yu Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- .../sun6i-a31s-yones-toptech-bs1078-v2.dts | 85 +++++++++++++++++-- 1 file changed, 78 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts b/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts index b199020733d3..360adfb1e9ca 100644 --- a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts +++ b/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts @@ -113,18 +113,83 @@ &mmc0_pins_a { allwinner,pull = ; }; -®_usb1_vbus { - gpio = <&pio 7 27 GPIO_ACTIVE_HIGH>; +&p2wi { status = "okay"; + + axp22x: pmic@68 { + compatible = "x-powers,axp221"; + reg = <0x68>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; }; -&usb1_vbus_pin_a { - allwinner,pins = "PH27"; +#include "axp22x.dtsi" + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; }; -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; +®_dc1sw { + regulator-name = "vcc-lcd-usb2"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; +}; + +®_dc5ldo { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpus"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v0"; +}; + +®_dcdc2 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc4 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-sys-dll"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +/* Voltage source for I2C pullup resistors for I2C Bus 0 */ +®_dldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vddio-csi"; }; &uart0 { @@ -132,3 +197,9 @@ &uart0 { pinctrl-0 = <&uart0_pins_a>; status = "okay"; }; + +&usbphy { + usb1_vbus-supply = <®_dldo1>; + usb2_vbus-supply = <®_dc1sw>; + status = "okay"; +}; From 18f17cb7d79c6cb6d6ed87c5956a0ebf084db44d Mon Sep 17 00:00:00 2001 From: Marcus Weseloh Date: Sat, 31 Oct 2015 13:55:42 +0100 Subject: [PATCH 04/40] ARM: dts: sun4i: Enable audio codec on Olimex A20-SOM-EVB Enable the on-chip audio codec on the Olimex A20-SOM-EVB Signed-off-by: Marcus Weseloh Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts index b7fe102475e7..a91879ed07f8 100644 --- a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts +++ b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts @@ -86,6 +86,10 @@ &ehci1 { status = "okay"; }; +&codec { + status = "okay"; +}; + &gmac { pinctrl-names = "default"; pinctrl-0 = <&gmac_pins_rgmii_a>; From 581de703ef3293fb71925a250fce08218924e7dc Mon Sep 17 00:00:00 2001 From: Aleksei Mamlin Date: Sun, 1 Nov 2015 16:53:52 +0300 Subject: [PATCH 05/40] ARM: dts: sun7i: Enable audio codec on Wexler TAB7200 tablet. Enable on-chip audio codec on the Wexler TAB7200 tablet. Signed-off-by: Aleksei Mamlin Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts index 78239ad988e7..239b5d2915a4 100644 --- a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts +++ b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts @@ -62,6 +62,10 @@ chosen { }; }; +&codec { + status = "okay"; +}; + &cpu0 { cpu-supply = <®_dcdc2>; }; From 111af755658e2417b48df978f7a231c3c616fe3e Mon Sep 17 00:00:00 2001 From: Jelle van der Waa Date: Tue, 3 Nov 2015 16:47:20 +0100 Subject: [PATCH 06/40] ARM: dts: sun7i: Enable audio codec on pcDuino Enable the on-chip audio codec Signed-off-by: Jelle van der Waa Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-pcduino3.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts index 861a4a66fb19..1a8b39be1d61 100644 --- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts @@ -111,6 +111,10 @@ &ahci_pwr_pin_a { allwinner,pins = "PH2"; }; +&codec { + status = "okay"; +}; + &cpu0 { cpu-supply = <®_dcdc2>; }; From e6c9b75453f48c455c8e2831cb265329a307cb29 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Tue, 3 Nov 2015 16:51:48 +0100 Subject: [PATCH 07/40] ARM: dts: sun4i: inet9f-rev03: Add support for game buttons / joysticks The inet9f-rev03 tablet has multiple fire-buttons / direction controls, add support for these using the same axis mapping as ps2 compatible game controllers with the same stick / button layout use. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts | 164 +++++++++++++++++++ 1 file changed, 164 insertions(+) diff --git a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts index 2fffc0434075..ca49b0d0ce1e 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts @@ -59,6 +59,159 @@ aliases { chosen { stdout-path = "serial0:115200n8"; }; + + gpio_keys { + compatible = "gpio-keys-polled"; + pinctrl-names = "default"; + pinctrl-0 = <&key_pins_inet9f>; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + + button@0 { + label = "Left Joystick Left"; + linux,code = ; + linux,input-type = ; + linux,input-value = <0xffffffff>; /* -1 */ + gpios = <&pio 0 6 GPIO_ACTIVE_LOW>; /* PA6 */ + }; + + button@1 { + label = "Left Joystick Right"; + linux,code = ; + linux,input-type = ; + linux,input-value = <1>; + gpios = <&pio 0 5 GPIO_ACTIVE_LOW>; /* PA5 */ + }; + + button@2 { + label = "Left Joystick Up"; + linux,code = ; + linux,input-type = ; + linux,input-value = <0xffffffff>; /* -1 */ + gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ + }; + + button@3 { + label = "Left Joystick Down"; + linux,code = ; + linux,input-type = ; + linux,input-value = <1>; + gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */ + }; + + button@4 { + label = "Right Joystick Left"; + linux,code = ; + linux,input-type = ; + linux,input-value = <0xffffffff>; /* -1 */ + gpios = <&pio 0 1 GPIO_ACTIVE_LOW>; /* PA1 */ + }; + + button@5 { + label = "Right Joystick Right"; + linux,code = ; + linux,input-type = ; + linux,input-value = <1>; + gpios = <&pio 0 0 GPIO_ACTIVE_LOW>; /* PA0 */ + }; + + button@6 { + label = "Right Joystick Up"; + linux,code = ; + linux,input-type = ; + linux,input-value = <0xffffffff>; /* -1 */ + gpios = <&pio 0 3 GPIO_ACTIVE_LOW>; /* PA3 */ + }; + + button@7 { + label = "Right Joystick Down"; + linux,code = ; + linux,input-type = ; + linux,input-value = <1>; + gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */ + }; + + button@8 { + label = "DPad Left"; + linux,code = ; + linux,input-type = ; + linux,input-value = <0xffffffff>; /* -1 */ + gpios = <&pio 7 23 GPIO_ACTIVE_LOW>; /* PH23 */ + }; + + button@9 { + label = "DPad Right"; + linux,code = ; + linux,input-type = ; + linux,input-value = <1>; + gpios = <&pio 7 24 GPIO_ACTIVE_LOW>; /* PH24 */ + }; + + button@10 { + label = "DPad Up"; + linux,code = ; + linux,input-type = ; + linux,input-value = <0xffffffff>; /* -1 */ + gpios = <&pio 7 25 GPIO_ACTIVE_LOW>; /* PH25 */ + }; + + button@11 { + label = "DPad Down"; + linux,code = ; + linux,input-type = ; + linux,input-value = <1>; + gpios = <&pio 7 26 GPIO_ACTIVE_LOW>; /* PH26 */ + }; + + button@12 { + label = "Button X"; + linux,code = ; + gpios = <&pio 0 16 GPIO_ACTIVE_LOW>; /* PA16 */ + }; + + button@13 { + label = "Button Y"; + linux,code = ; + gpios = <&pio 0 14 GPIO_ACTIVE_LOW>; /* PA14 */ + }; + + button@14 { + label = "Button A"; + linux,code = ; + gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */ + }; + + button@15 { + label = "Button B"; + linux,code = ; + gpios = <&pio 0 15 GPIO_ACTIVE_LOW>; /* PA15 */ + }; + + button@16 { + label = "Select Button"; + linux,code = ; + gpios = <&pio 0 11 GPIO_ACTIVE_LOW>; /* PA11 */ + }; + + button@17 { + label = "Start Button"; + linux,code = ; + gpios = <&pio 0 12 GPIO_ACTIVE_LOW>; /* PA12 */ + }; + + button@18 { + label = "Top Left Button"; + linux,code = ; + gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ + }; + + button@19 { + label = "Top Right Button"; + linux,code = ; + gpios = <&pio 0 13 GPIO_ACTIVE_LOW>; /* PA13 */ + }; + }; }; &cpu0 { @@ -157,6 +310,17 @@ &otg_sram { }; &pio { + key_pins_inet9f: key_pins@0 { + allwinner,pins = "PA0", "PA1", "PA3", "PA4", + "PA5", "PA6", "PA8", "PA9", + "PA11", "PA12", "PA13", + "PA14", "PA15", "PA16", "PA17", + "PH22", "PH23", "PH24", "PH25", "PH26"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; + usb0_id_detect_pin: usb0_id_detect_pin@0 { allwinner,pins = "PH4"; allwinner,function = "gpio_in"; From bc1e2718696e1488392cb1bacc5379300520cebd Mon Sep 17 00:00:00 2001 From: Priit Laes Date: Fri, 6 Nov 2015 19:54:44 +0200 Subject: [PATCH 08/40] ARM: dts: sun4i: gemei-g9: Convert to use axp209 regulator nodes Add regulator nodes for axp209 using the axp209.dtsi include. Signed-off-by: Priit Laes Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10-gemei-g9.dts | 35 +++++++++++++++++++++--- 1 file changed, 31 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts b/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts index 3f0aeb8288cd..6b4c29db3387 100644 --- a/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts +++ b/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts @@ -72,6 +72,10 @@ chosen { * Touchscreen - gt801_2plus1 @ i2c adapter 2 @ 0x48 */ +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + &ehci0 { status = "okay"; }; @@ -86,15 +90,13 @@ &i2c0 { status = "okay"; axp209: pmic@34 { - compatible = "x-powers,axp209"; reg = <0x34>; interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; }; }; +#include "axp209.dtsi" + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins_a>; @@ -146,6 +148,31 @@ &mmc0 { status = "okay"; }; +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + ®_usb1_vbus { status = "okay"; }; From 108f780a704f66f1b9d80a1b8b42d467ecca3981 Mon Sep 17 00:00:00 2001 From: Priit Laes Date: Fri, 6 Nov 2015 19:54:45 +0200 Subject: [PATCH 09/40] ARM: dts: sun4i: gemei-g9: Use reg_ldo2 instead of reg_vcc3v0 ADC seems to be using ldo2 for reference voltage. Signed-off-by: Priit Laes Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10-gemei-g9.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts b/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts index 6b4c29db3387..16c1a6783090 100644 --- a/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts +++ b/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts @@ -112,7 +112,7 @@ bma250@18 { }; &lradc { - vref-supply = <®_vcc3v0>; + vref-supply = <®_ldo2>; status = "okay"; From fef5218430dc52e3d7494986dfff2ff93a6e409a Mon Sep 17 00:00:00 2001 From: Priit Laes Date: Fri, 6 Nov 2015 19:54:46 +0200 Subject: [PATCH 10/40] ARM: dts: sun4i: gemei-g9: Enable sun4i audio codec support Gemei G9 has internal speakers and headphone jack. Audio switching from internal speakers to headphones is automatically handled by extra FT2012Q audio amplifier chip that works out of the box. Signed-off-by: Priit Laes Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10-gemei-g9.dts | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts b/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts index 16c1a6783090..1d73a9897b71 100644 --- a/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts +++ b/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts @@ -65,12 +65,15 @@ chosen { /* * TODO: * 2x cameras via CSI - * audio + * audio input * AXP battery management * NAND * OTG * Touchscreen - gt801_2plus1 @ i2c adapter 2 @ 0x48 */ +&codec { + status = "okay"; +}; &cpu0 { cpu-supply = <®_dcdc2>; From aea4c39526132e01a6cb18462ad2c15e7f15da1b Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 17 Nov 2015 00:38:25 +0800 Subject: [PATCH 11/40] ARM: dts: sun8i: Add simplefb node labels to reference at board level Some boards, such as tablets, have regulators providing power to parts of the display pipeline, like signal converters and LCD panels. Add labels to the simplefb device nodes so that we can reference them in the board dts files to add regulator supply properties. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 0c0964d4fa1f..6f88fb0ddbc7 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -56,7 +56,7 @@ chosen { #size-cells = <1>; ranges; - framebuffer@0 { + simplefb_lcd: framebuffer@0 { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0"; From a292e576f533070b39547077a5662d33f6c3ed07 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 20 Nov 2015 14:47:11 +0100 Subject: [PATCH 12/40] ARM: dts: sun4i: Enable onboard codec used on the iNet1 tablet The iNet1 tablet uses the A10's integrated audio codec, enable it. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10-inet1.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/sun4i-a10-inet1.dts b/arch/arm/boot/dts/sun4i-a10-inet1.dts index 487ce63519dc..0711fa26ca67 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet1.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet1.dts @@ -61,6 +61,10 @@ chosen { }; }; +&codec { + status = "okay"; +}; + &cpu0 { cpu-supply = <®_dcdc2>; }; From 8a7b89d1f674c5202908935267fcade13c83f76e Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 20 Nov 2015 14:59:07 +0100 Subject: [PATCH 13/40] ARM: dts: sun4i: Add backlight node to iNet1 tablet Add a node describing the lcd panel backlight on the iNet1 tablet. Signed-off-by: Hans de Goede Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10-inet1.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/sun4i-a10-inet1.dts b/arch/arm/boot/dts/sun4i-a10-inet1.dts index 0711fa26ca67..d46a141bb847 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet1.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet1.dts @@ -47,6 +47,7 @@ #include #include #include +#include / { model = "iNet-1"; @@ -56,6 +57,16 @@ aliases { serial0 = &uart0; }; + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&bl_en_pin_inet>; + pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <8>; + enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -155,6 +166,13 @@ &otg_sram { }; &pio { + bl_en_pin_inet: bl_en_pin@0 { + allwinner,pins = "PH7"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + usb0_id_detect_pin: usb0_id_detect_pin@0 { allwinner,pins = "PH4"; allwinner,function = "gpio_in"; @@ -170,6 +188,12 @@ usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { }; }; +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins_a>; + status = "okay"; +}; + ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; From 45f0cf84ac7096e76a6fffa17c43d25b50d86d05 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 20 Nov 2015 14:59:08 +0100 Subject: [PATCH 14/40] ARM: dts: sun5i: Add backlight node to UTOO P66 tablet Add a node describing the lcd panel backlight on the UTOO P66 tablet. Signed-off-by: Hans de Goede Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-a13-utoo-p66.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts index eb793d5a2bd6..5236c1e3a1b5 100644 --- a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts +++ b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts @@ -47,11 +47,21 @@ #include #include #include +#include / { model = "Utoo P66"; compatible = "utoo,p66", "allwinner,sun5i-a13"; + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; + /* Note levels of 10 / 20% result in backlight off */ + brightness-levels = <0 30 40 50 60 70 80 90 100>; + default-brightness-level = <6>; + /* TODO: backlight uses axp gpio1 as enable pin */ + }; + i2c_lcd: i2c@0 { /* The lcd panel i2c interface is hooked up via gpios */ compatible = "i2c-gpio"; @@ -201,6 +211,12 @@ usb0_vbus_pin_a: usb0_vbus_pin@0 { }; }; +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins>; + status = "okay"; +}; + ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; From 0f95851bbc9997bc7ee94180b4058bf376b4473a Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 20 Nov 2015 14:59:09 +0100 Subject: [PATCH 15/40] ARM: dts: sun4i: Add backlight node to pov protab2 ips9 tablet Add a node describing the lcd panel backlight on the pov protab2 ips9 tablet. Signed-off-by: Hans de Goede Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- .../boot/dts/sun4i-a10-pov-protab2-ips9.dts | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts index 82e69c3820a2..d1ea36cd216b 100644 --- a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts +++ b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts @@ -47,6 +47,7 @@ #include #include #include +#include / { model = "Point of View Protab2-IPS9"; @@ -56,6 +57,16 @@ aliases { serial0 = &uart0; }; + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&bl_en_pin_protab>; + pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <8>; + enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -129,6 +140,13 @@ &otg_sram { }; &pio { + bl_en_pin_protab: bl_en_pin@0 { + allwinner,pins = "PH7"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + usb0_id_detect_pin: usb0_id_detect_pin@0 { allwinner,pins = "PH4"; allwinner,function = "gpio_in"; @@ -144,6 +162,12 @@ usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { }; }; +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins_a>; + status = "okay"; +}; + ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; From c9bb9aedb04986e55f269484556330f5b74d76ff Mon Sep 17 00:00:00 2001 From: Michael van Slingerland Date: Fri, 20 Nov 2015 14:59:10 +0100 Subject: [PATCH 16/40] ARM: dts: sun5i: Add i2c axp152 pmic support for Auxtek T004 boards Add a node describing the AXP152 pmic used on Auxtek T004 boards. Acked-by: Chen-Yu Tsai Signed-off-by: Michael van Slingerland Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts index 2b3511ea2e5d..a790ec8adb75 100644 --- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts +++ b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts @@ -86,6 +86,20 @@ &ehci0 { status = "okay"; }; +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp152: pmic@30 { + compatible = "x-powers,axp152"; + reg = <0x30>; + interrupts = <0>; + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_t004>; From 71101fdf05a141c65363ecfb3f085d9e847138b7 Mon Sep 17 00:00:00 2001 From: Stefan Monnier Date: Mon, 23 Nov 2015 13:50:16 -0500 Subject: [PATCH 17/40] ARM: dts: sun7i: Enable audio codec on OrangePi Mini Enable the on-chip audio codec Signed-off-by: Stefan Monnier Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts b/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts index 4f65664e5dfe..2be04c438b1e 100644 --- a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts +++ b/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts @@ -95,6 +95,10 @@ &ahci { status = "okay"; }; +&codec { + status = "okay"; +}; + &ehci0 { status = "okay"; }; From 38e633f3f3756b5630c5eb66042e776d86764296 Mon Sep 17 00:00:00 2001 From: Stefan Monnier Date: Mon, 23 Nov 2015 13:50:17 -0500 Subject: [PATCH 18/40] ARM: dts: sun7i: Enable audio codec on BananaPi Enable the on-chip audio codec Signed-off-by: Stefan Monnier Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-bananapi.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/sun7i-a20-bananapi.dts index fd7594ff90d5..67c8a7644b99 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapi.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapi.dts @@ -92,6 +92,10 @@ &ahci { status = "okay"; }; +&codec { + status = "okay"; +}; + &cpu0 { cpu-supply = <®_dcdc2>; operating-points = < From 6ffd6fa0134a7dd6b65633bb0b8c587517ac94e9 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 20 Nov 2015 14:24:51 +0100 Subject: [PATCH 19/40] ARM: dts: sun4i: Add touchscreen node to iNet1 tablet Add a node describing the touchscreen controller used on the iNet1 tablet. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10-inet1.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/sun4i-a10-inet1.dts b/arch/arm/boot/dts/sun4i-a10-inet1.dts index d46a141bb847..e09053bf5e1f 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet1.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet1.dts @@ -119,6 +119,19 @@ &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins_a>; status = "okay"; + + ft5x: touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + interrupt-parent = <&pio>; + interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_wake_pin>; + wake-gpios = <&pio 1 13 GPIO_ACTIVE_HIGH>; /* PB13 */ + touchscreen-size-x = <600>; + touchscreen-size-y = <1024>; + touchscreen-swapped-x-y; + }; }; &lradc { @@ -173,6 +186,13 @@ bl_en_pin_inet: bl_en_pin@0 { allwinner,pull = ; }; + touchscreen_wake_pin: touchscreen_wake_pin@0 { + allwinner,pins = "PB13"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + usb0_id_detect_pin: usb0_id_detect_pin@0 { allwinner,pins = "PH4"; allwinner,function = "gpio_in"; From c1751e32727c5356c4e33c8da33edb782dde6210 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 20 Nov 2015 14:24:52 +0100 Subject: [PATCH 20/40] ARM: dts: sun4i: Add touchscreen node to pov protab2-ips9 tablet Add a node describing the touchscreen found on the pov protab2-ips9 tablet. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- .../boot/dts/sun4i-a10-pov-protab2-ips9.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts index d1ea36cd216b..1f92ec7c82e8 100644 --- a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts +++ b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts @@ -104,6 +104,22 @@ &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins_a>; status = "okay"; + + pixcir_ts@5c { + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + compatible = "pixcir,pixcir_tangoc"; + reg = <0x5c>; + interrupt-parent = <&pio>; + interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; /* EINT21 (PH21) */ + attb-gpio = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* PH21 */ + enable-gpios = <&pio 0 5 GPIO_ACTIVE_LOW>; + wake-gpios = <&pio 1 13 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <1024>; + touchscreen-size-y = <768>; + touchscreen-inverted-x; + touchscreen-inverted-y; + }; }; &lradc { @@ -147,6 +163,13 @@ bl_en_pin_protab: bl_en_pin@0 { allwinner,pull = ; }; + touchscreen_pins: touchscreen_pins@0 { + allwinner,pins = "PA5", "PB13"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + usb0_id_detect_pin: usb0_id_detect_pin@0 { allwinner,pins = "PH4"; allwinner,function = "gpio_in"; From afd7d66c240ba734740b1b4daccd8b1cc735b788 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sun, 29 Nov 2015 11:03:09 +0800 Subject: [PATCH 21/40] ARM: dts: sun9i: Add A80 PRCM clocks and reset control nodes This adds the supported PRCM clocks and reset controls to the A80 dtsi. The DAUDIO module clocks are not supported yet. Also update clock and reset phandles for r_uart. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80.dtsi | 79 +++++++++++++++++++++++++++++++- 1 file changed, 78 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index 1118bf5cc4fb..a4ce348c0831 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -164,6 +164,14 @@ usb_phy_clk: clk@00a08004 { "usb_phy2", "usb_hsic_12M"; }; + pll3: clk@06000008 { + /* placeholder until implemented */ + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-rate = <0>; + clock-output-names = "pll3"; + }; + pll4: clk@0600000c { #clock-cells = <0>; compatible = "allwinner,sun9i-a80-pll4-clk"; @@ -350,6 +358,68 @@ apb1_gates: clk@06000594 { "apb1_uart2", "apb1_uart3", "apb1_uart4", "apb1_uart5"; }; + + cpus_clk: clk@08001410 { + compatible = "allwinner,sun9i-a80-cpus-clk"; + reg = <0x08001410 0x4>; + #clock-cells = <0>; + clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>; + clock-output-names = "cpus"; + }; + + ahbs: ahbs_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&cpus_clk>; + clock-output-names = "ahbs"; + }; + + apbs: clk@0800141c { + compatible = "allwinner,sun8i-a23-apb0-clk"; + reg = <0x0800141c 0x4>; + #clock-cells = <0>; + clocks = <&ahbs>; + clock-output-names = "apbs"; + }; + + apbs_gates: clk@08001428 { + compatible = "allwinner,sun9i-a80-apbs-gates-clk"; + reg = <0x08001428 0x4>; + #clock-cells = <1>; + clocks = <&apbs>; + clock-indices = <0>, <1>, + <2>, <3>, + <4>, <5>, + <6>, <7>, + <12>, <13>, + <16>, <17>, + <18>, <20>; + clock-output-names = "apbs_pio", "apbs_ir", + "apbs_timer", "apbs_rsb", + "apbs_uart", "apbs_1wire", + "apbs_i2c0", "apbs_i2c1", + "apbs_ps2_0", "apbs_ps2_1", + "apbs_dma", "apbs_i2s0", + "apbs_i2s1", "apbs_twd"; + }; + + r_1wire_clk: clk@08001450 { + reg = <0x08001450 0x4>; + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + clocks = <&osc32k>, <&osc24M>; + clock-output-names = "r_1wire"; + }; + + r_ir_clk: clk@08001454 { + reg = <0x08001454 0x4>; + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + clocks = <&osc32k>, <&osc24M>; + clock-output-names = "r_ir"; + }; }; soc { @@ -764,13 +834,20 @@ r_wdt: watchdog@08001000 { interrupts = ; }; + apbs_rst: reset@080014b0 { + reg = <0x080014b0 0x4>; + compatible = "allwinner,sun6i-a31-clock-reset"; + #reset-cells = <1>; + }; + r_uart: serial@08002800 { compatible = "snps,dw-apb-uart"; reg = <0x08002800 0x400>; interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc24M>; + clocks = <&apbs_gates 4>; + resets = <&apbs_rst 4>; status = "disabled"; }; }; From d255abd60e9c0c91e0146fdcbe534b3b9f5352a6 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sun, 29 Nov 2015 11:03:10 +0800 Subject: [PATCH 22/40] ARM: dts: sun9i: Add TODO comments for the main and low power clocks The main (24MHz) clock on the A80 is configurable via the PRCM address space. The low power/speed (32kHz) clock is from an external chip, the AC100. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index a4ce348c0831..eb69a62f6bc4 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -128,6 +128,17 @@ clocks { */ ranges = <0 0 0 0x20000000>; + /* + * This clock is actually configurable from the PRCM address + * space. The external 24M oscillator can be turned off, and + * the clock switched to an internal 16M RC oscillator. Under + * normal operation there's no reason to do this, and the + * default is to use the external good one, so just model this + * as a fixed clock. Also it is not entirely clear if the + * osc24M mux in the PRCM affects the entire clock tree, which + * would also throw all the PLL clock rates off, or just the + * downstream clocks in the PRCM. + */ osc24M: osc24M_clk { #clock-cells = <0>; compatible = "fixed-clock"; @@ -135,6 +146,13 @@ osc24M: osc24M_clk { clock-output-names = "osc24M"; }; + /* + * The 32k clock is from an external source, normally the + * AC100 codec/RTC chip. This clock is by default enabled + * and clocked at 32768 Hz, from the oscillator connected + * to the AC100. It is configurable, but no such driver or + * bindings exist yet. + */ osc32k: osc32k_clk { #clock-cells = <0>; compatible = "fixed-clock"; From 1ac56a6da9e11fe35470f804376a67b5bb9d13fe Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 1 Dec 2015 13:47:20 +0800 Subject: [PATCH 23/40] ARM: dts: sun9i: Add A80 R_PIO pin controller device node The A80 has a secondary pin controller. Add a device node for it. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index eb69a62f6bc4..d02ee5d520e2 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -868,5 +868,19 @@ r_uart: serial@08002800 { resets = <&apbs_rst 4>; status = "disabled"; }; + + r_pio: pinctrl@08002c00 { + compatible = "allwinner,sun9i-a80-r-pinctrl"; + reg = <0x08002c00 0x400>; + interrupts = , + ; + clocks = <&apbs_gates 0>; + resets = <&apbs_rst 0>; + gpio-controller; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #gpio-cells = <3>; + }; }; }; From d2118f06d10886513ca0f462afc8e5263d01692e Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 1 Dec 2015 13:47:21 +0800 Subject: [PATCH 24/40] ARM: dts: sun9i: optimus: Enable LED3 LED3 is connected to pin PM15 on R_PIO. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80-optimus.dts | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts index 6ce4b5e8b615..ae7db9fcb2a7 100644 --- a/arch/arm/boot/dts/sun9i-a80-optimus.dts +++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts @@ -65,7 +65,7 @@ chosen { leds { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&led_pins_optimus>; + pinctrl-0 = <&led_pins_optimus>, <&led_r_pins_optimus>; /* The LED names match those found on the board */ @@ -74,7 +74,10 @@ led2 { gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; }; - /* led3 is on PM15, in R_PIO */ + led3 { + label = "optimus:led3:usr"; + gpios = <&r_pio 1 15 GPIO_ACTIVE_HIGH>; /* PM15 */ + }; led4 { label = "optimus:led4:usr"; @@ -180,6 +183,15 @@ ®_usb1_vbus { status = "okay"; }; +&r_pio { + led_r_pins_optimus: led-pins@1 { + allwinner,pins = "PM15"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; From 1595b37cb212242791dd4ac9334242d32c8ad2c5 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 1 Dec 2015 13:47:22 +0800 Subject: [PATCH 25/40] ARM: dts: sun9i: Add consumer IR receiver device node and pinmux settings The Allwinner A80 SoC has a consumer IR receiver, which is the same as older SoCs. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index d02ee5d520e2..80777a33ee78 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -858,6 +858,18 @@ apbs_rst: reset@080014b0 { #reset-cells = <1>; }; + r_ir: ir@08002000 { + compatible = "allwinner,sun5i-a13-ir"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&r_ir_pins>; + clocks = <&apbs_gates 1>, <&r_ir_clk>; + clock-names = "apb", "ir"; + resets = <&apbs_rst 1>; + reg = <0x08002000 0x40>; + status = "disabled"; + }; + r_uart: serial@08002800 { compatible = "snps,dw-apb-uart"; reg = <0x08002800 0x400>; @@ -881,6 +893,13 @@ r_pio: pinctrl@08002c00 { #address-cells = <1>; #size-cells = <0>; #gpio-cells = <3>; + + r_ir_pins: r_ir { + allwinner,pins = "PL6"; + allwinner,function = "s_cir_rx"; + allwinner,drive = ; + allwinner,pull = ; + }; }; }; }; From 969c9687414335701244a98c9d259d2e918d7e34 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 1 Dec 2015 13:47:23 +0800 Subject: [PATCH 26/40] ARM: dts: sun9i: optimus: Enable consumer IR receiver The A80 Optimus board has a consumer IR receiver. Enable it in the DT. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80-optimus.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts index ae7db9fcb2a7..79766e5867cd 100644 --- a/arch/arm/boot/dts/sun9i-a80-optimus.dts +++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts @@ -183,6 +183,10 @@ ®_usb1_vbus { status = "okay"; }; +&r_ir { + status = "okay"; +}; + &r_pio { led_r_pins_optimus: led-pins@1 { allwinner,pins = "PM15"; From ed473ebd9c15481669bfcc1058c6b9bba64ecd12 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 1 Dec 2015 13:47:24 +0800 Subject: [PATCH 27/40] ARM: dts: sun9i: Add Reduced Serial Bus controller device node to A80 dtsi This patch adds a device node for the Reduced Serial Bus (RSB) controller and the defacto pinmux setting to the A80 dtsi. Since there is only one possible pinmux setting for RSB, just set it in the dtsi. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index 80777a33ee78..dc666c69f6ab 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -900,6 +900,27 @@ r_ir_pins: r_ir { allwinner,drive = ; allwinner,pull = ; }; + + r_rsb_pins: r_rsb { + allwinner,pins = "PN0", "PN1"; + allwinner,function = "s_rsb"; + allwinner,drive = ; + allwinner,pull = ; + }; + }; + + r_rsb: i2c@08003400 { + compatible = "allwinner,sun8i-a23-rsb"; + reg = <0x08003400 0x400>; + interrupts = ; + clocks = <&apbs_gates 3>; + clock-frequency = <3000000>; + resets = <&apbs_rst 3>; + pinctrl-names = "default"; + pinctrl-0 = <&r_rsb_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; }; }; From a87b5ba9dc2d356cf8e121aeef84f5741a662038 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 1 Dec 2015 13:47:25 +0800 Subject: [PATCH 28/40] ARM: dts: sun9i: optimus: Enable Reduced Serial Bus controller Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80-optimus.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts index 79766e5867cd..c0060e4f7379 100644 --- a/arch/arm/boot/dts/sun9i-a80-optimus.dts +++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts @@ -196,6 +196,10 @@ led_r_pins_optimus: led-pins@1 { }; }; +&r_rsb { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; From 67e1cbfbc14ab07d0aeffa8d2c92141da32b56e9 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 3 Dec 2015 16:20:13 +0800 Subject: [PATCH 29/40] ARM: dts: sun9i: Add NMI controller device node The Allwinner A80 SoC has an NMI controller. NMI is an external interrupt pin exclusely used with PMICs and other system critical peripherals (such as RTC) in Allwinner's reference designs. Signed-off-by: Chen-Yu Tsai Reviewed-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index dc666c69f6ab..e838f206f2a0 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -858,6 +858,14 @@ apbs_rst: reset@080014b0 { #reset-cells = <1>; }; + nmi_intc: interrupt-controller@080015a0 { + compatible = "allwinner,sun9i-a80-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x080015a0 0xc>; + interrupts = ; + }; + r_ir: ir@08002000 { compatible = "allwinner,sun5i-a13-ir"; interrupts = ; From 82f8582feef4c048ee7ef0155a71c23614a7856d Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sat, 5 Dec 2015 21:16:44 +0800 Subject: [PATCH 30/40] ARM: dts: sun4i: Add DRAM gates The DRAM gates controls direct memory access for some peripherals. These peripherals include the display pipeline, so add the required gates to the simplefb nodes as well. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 36 ++++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index aa90f319309b..849d0242ece8 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -66,7 +66,7 @@ framebuffer@0 { "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, - <&ahb_gates 44>; + <&ahb_gates 44>, <&dram_gates 26>; status = "disabled"; }; @@ -75,7 +75,8 @@ framebuffer@1 { "simple-framebuffer"; allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, - <&ahb_gates 44>, <&ahb_gates 46>; + <&ahb_gates 44>, <&ahb_gates 46>, + <&dram_gates 25>, <&dram_gates 26>; status = "disabled"; }; @@ -84,7 +85,8 @@ framebuffer@2 { "simple-framebuffer"; allwinner,pipeline = "de_fe0-de_be0-lcd0"; clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>, - <&ahb_gates 46>; + <&ahb_gates 46>, <&dram_gates 25>, + <&dram_gates 26>; status = "disabled"; }; @@ -93,7 +95,8 @@ framebuffer@3 { "simple-framebuffer"; allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, - <&ahb_gates 44>, <&ahb_gates 46>; + <&ahb_gates 44>, <&ahb_gates 46>, + <&dram_gates 25>, <&dram_gates 26>; status = "disabled"; }; }; @@ -492,6 +495,31 @@ spi3_clk: clk@01c200d4 { clock-output-names = "spi3"; }; + dram_gates: clk@01c20100 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-dram-gates-clk"; + reg = <0x01c20100 0x4>; + clocks = <&pll5 0>; + clock-indices = <0>, + <1>, <2>, + <3>, + <4>, + <5>, <6>, + <15>, + <24>, <25>, + <26>, <27>, + <28>, <29>; + clock-output-names = "dram_ve", + "dram_csi0", "dram_csi1", + "dram_ts", + "dram_tvd", + "dram_tve0", "dram_tve1", + "dram_output", + "dram_de_fe1", "dram_de_fe0", + "dram_de_be0", "dram_de_be1", + "dram_de_mp", "dram_ace"; + }; + codec_clk: clk@01c20140 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-codec-clk"; From 0b4bf5a5200b9ac5ddf545665f171feb5594677d Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sat, 5 Dec 2015 21:16:46 +0800 Subject: [PATCH 31/40] ARM: dts: sun7i: Add DRAM gates The DRAM gates controls direct memory access for some peripherals. These peripherals include the display pipeline, so add the required gates to the simplefb nodes as well. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 32 +++++++++++++++++++++++++++++--- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index e02eb720c4fc..21169c0a6627 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -68,7 +68,7 @@ framebuffer@0 { "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, - <&ahb_gates 44>; + <&ahb_gates 44>, <&dram_gates 26>; status = "disabled"; }; @@ -76,7 +76,8 @@ framebuffer@1 { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0"; - clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>; + clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>, + <&dram_gates 26>; status = "disabled"; }; @@ -85,7 +86,7 @@ framebuffer@2 { "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-tve0"; clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, - <&ahb_gates 44>; + <&ahb_gates 44>, <&dram_gates 26>; status = "disabled"; }; }; @@ -501,6 +502,31 @@ spi3_clk: clk@01c200d4 { clock-output-names = "spi3"; }; + dram_gates: clk@01c20100 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-dram-gates-clk"; + reg = <0x01c20100 0x4>; + clocks = <&pll5 0>; + clock-indices = <0>, + <1>, <2>, + <3>, + <4>, + <5>, <6>, + <15>, + <24>, <25>, + <26>, <27>, + <28>, <29>; + clock-output-names = "dram_ve", + "dram_csi0", "dram_csi1", + "dram_ts", + "dram_tvd", + "dram_tve0", "dram_tve1", + "dram_output", + "dram_de_fe1", "dram_de_fe0", + "dram_de_be0", "dram_de_be1", + "dram_de_mp", "dram_ace"; + }; + codec_clk: clk@01c20140 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-codec-clk"; From 318d93bc41823e86967c8251eef0444a72e4d687 Mon Sep 17 00:00:00 2001 From: Jens Kuske Date: Fri, 4 Dec 2015 22:24:42 +0100 Subject: [PATCH 32/40] ARM: dts: sunxi: Add Allwinner H3 DTSI The Allwinner H3 is a home entertainment system oriented SoC with four Cortex-A7 cores and a Mali-400MP2 GPU. Signed-off-by: Jens Kuske Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3.dtsi | 497 ++++++++++++++++++++++++++++++++ 1 file changed, 497 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-h3.dtsi diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi new file mode 100644 index 000000000000..1524130e43c9 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -0,0 +1,497 @@ +/* + * Copyright (C) 2015 Jens Kuske + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "skeleton.dtsi" + +#include +#include + +/ { + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <3>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: osc24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: osc32k_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + + pll1: clk@01c20000 { + #clock-cells = <0>; + compatible = "allwinner,sun8i-a23-pll1-clk"; + reg = <0x01c20000 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll1"; + }; + + /* dummy clock until actually implemented */ + pll5: pll5_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "pll5"; + }; + + pll6: clk@01c20028 { + #clock-cells = <1>; + compatible = "allwinner,sun6i-a31-pll6-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6", "pll6x2"; + }; + + pll6d2: pll6d2_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <2>; + clock-mult = <1>; + clocks = <&pll6 0>; + clock-output-names = "pll6d2"; + }; + + /* dummy clock until pll6 can be reused */ + pll8: pll8_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <1>; + clock-output-names = "pll8"; + }; + + cpu: cpu_clk@01c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-cpu-clk"; + reg = <0x01c20050 0x4>; + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; + clock-output-names = "cpu"; + }; + + axi: axi_clk@01c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-axi-clk"; + reg = <0x01c20050 0x4>; + clocks = <&cpu>; + clock-output-names = "axi"; + }; + + ahb1: ahb1_clk@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun6i-a31-ahb1-clk"; + reg = <0x01c20054 0x4>; + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; + clock-output-names = "ahb1"; + }; + + ahb2: ahb2_clk@01c2005c { + #clock-cells = <0>; + compatible = "allwinner,sun8i-h3-ahb2-clk"; + reg = <0x01c2005c 0x4>; + clocks = <&ahb1>, <&pll6d2>; + clock-output-names = "ahb2"; + }; + + apb1: apb1_clk@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb0-clk"; + reg = <0x01c20054 0x4>; + clocks = <&ahb1>; + clock-output-names = "apb1"; + }; + + apb2: apb2_clk@01c20058 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb1-clk"; + reg = <0x01c20058 0x4>; + clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; + clock-output-names = "apb2"; + }; + + bus_gates: clk@01c20060 { + #clock-cells = <1>; + compatible = "allwinner,sun8i-h3-bus-gates-clk"; + reg = <0x01c20060 0x14>; + clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>; + clock-names = "ahb1", "ahb2", "apb1", "apb2"; + clock-indices = <5>, <6>, <8>, + <9>, <10>, <13>, + <14>, <17>, <18>, + <19>, <20>, + <21>, <23>, + <24>, <25>, + <26>, <27>, + <28>, <29>, + <30>, <31>, <32>, + <35>, <36>, <37>, + <40>, <41>, <43>, + <44>, <52>, <53>, + <54>, <64>, + <65>, <69>, <72>, + <76>, <77>, <78>, + <96>, <97>, <98>, + <112>, <113>, + <114>, <115>, + <116>, <128>, <135>; + clock-output-names = "bus_ce", "bus_dma", "bus_mmc0", + "bus_mmc1", "bus_mmc2", "bus_nand", + "bus_sdram", "bus_gmac", "bus_ts", + "bus_hstimer", "bus_spi0", + "bus_spi1", "bus_otg", + "bus_otg_ehci0", "bus_ehci1", + "bus_ehci2", "bus_ehci3", + "bus_otg_ohci0", "bus_ohci1", + "bus_ohci2", "bus_ohci3", "bus_ve", + "bus_lcd0", "bus_lcd1", "bus_deint", + "bus_csi", "bus_tve", "bus_hdmi", + "bus_de", "bus_gpu", "bus_msgbox", + "bus_spinlock", "bus_codec", + "bus_spdif", "bus_pio", "bus_ths", + "bus_i2s0", "bus_i2s1", "bus_i2s2", + "bus_i2c0", "bus_i2c1", "bus_i2c2", + "bus_uart0", "bus_uart1", + "bus_uart2", "bus_uart3", + "bus_scr", "bus_ephy", "bus_dbg"; + }; + + mmc0_clk: clk@01c20088 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6 0>, <&pll8>; + clock-output-names = "mmc0", + "mmc0_output", + "mmc0_sample"; + }; + + mmc1_clk: clk@01c2008c { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c2008c 0x4>; + clocks = <&osc24M>, <&pll6 0>, <&pll8>; + clock-output-names = "mmc1", + "mmc1_output", + "mmc1_sample"; + }; + + mmc2_clk: clk@01c20090 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c20090 0x4>; + clocks = <&osc24M>, <&pll6 0>, <&pll8>; + clock-output-names = "mmc2", + "mmc2_output", + "mmc2_sample"; + }; + + mbus_clk: clk@01c2015c { + #clock-cells = <0>; + compatible = "allwinner,sun8i-a23-mbus-clk"; + reg = <0x01c2015c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5>; + clock-output-names = "mbus"; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dma: dma-controller@01c02000 { + compatible = "allwinner,sun8i-h3-dma"; + reg = <0x01c02000 0x1000>; + interrupts = ; + clocks = <&bus_gates 6>; + resets = <&ahb_rst 6>; + #dma-cells = <1>; + }; + + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&bus_gates 8>, + <&mmc0_clk 0>, + <&mmc0_clk 1>, + <&mmc0_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ahb_rst 8>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@01c10000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&bus_gates 9>, + <&mmc1_clk 0>, + <&mmc1_clk 1>, + <&mmc1_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ahb_rst 9>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&bus_gates 10>, + <&mmc2_clk 0>, + <&mmc2_clk 1>, + <&mmc2_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ahb_rst 10>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + pio: pinctrl@01c20800 { + compatible = "allwinner,sun8i-h3-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = , + ; + clocks = <&bus_gates 69>; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <2>; + + uart0_pins_a: uart0@0 { + allwinner,pins = "PA4", "PA5"; + allwinner,function = "uart0"; + allwinner,drive = ; + allwinner,pull = ; + }; + + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0", "PF1", "PF2", "PF3", + "PF4", "PF5"; + allwinner,function = "mmc0"; + allwinner,drive = ; + allwinner,pull = ; + }; + + mmc0_cd_pin: mmc0_cd_pin@0 { + allwinner,pins = "PF6"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; + + mmc1_pins_a: mmc1@0 { + allwinner,pins = "PG0", "PG1", "PG2", "PG3", + "PG4", "PG5"; + allwinner,function = "mmc1"; + allwinner,drive = ; + allwinner,pull = ; + }; + }; + + ahb_rst: reset@01c202c0 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-ahb1-reset"; + reg = <0x01c202c0 0xc>; + }; + + apb1_rst: reset@01c202d0 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-clock-reset"; + reg = <0x01c202d0 0x4>; + }; + + apb2_rst: reset@01c202d8 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-clock-reset"; + reg = <0x01c202d8 0x4>; + }; + + timer@01c20c00 { + compatible = "allwinner,sun4i-a10-timer"; + reg = <0x01c20c00 0xa0>; + interrupts = , + ; + clocks = <&osc24M>; + }; + + wdt0: watchdog@01c20ca0 { + compatible = "allwinner,sun6i-a31-wdt"; + reg = <0x01c20ca0 0x20>; + interrupts = ; + }; + + uart0: serial@01c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&bus_gates 112>; + resets = <&apb2_rst 16>; + dmas = <&dma 6>, <&dma 6>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart1: serial@01c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&bus_gates 113>; + resets = <&apb2_rst 17>; + dmas = <&dma 7>, <&dma 7>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart2: serial@01c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&bus_gates 114>; + resets = <&apb2_rst 18>; + dmas = <&dma 8>, <&dma 8>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart3: serial@01c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&bus_gates 115>; + resets = <&apb2_rst 19>; + dmas = <&dma 9>, <&dma 9>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + gic: interrupt-controller@01c81000 { + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x1000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + }; + + rtc: rtc@01f00000 { + compatible = "allwinner,sun6i-a31-rtc"; + reg = <0x01f00000 0x54>; + interrupts = , + ; + }; + }; +}; From dfcf8196de7411a5e7fd49795938b1bc8c56859c Mon Sep 17 00:00:00 2001 From: Jens Kuske Date: Fri, 4 Dec 2015 22:24:43 +0100 Subject: [PATCH 33/40] ARM: dts: sun8i: Add Orange Pi Plus support The Orange Pi Plus is a SBC based on the Allwinner H3 SoC with 8GB eMMC, multiple USB ports through a USB hub chip, SATA through a USB-SATA bridge, one uSD slot, a 10/100/1000M ethernet port, WiFi, HDMI, headphone jack, IR receiver, a microphone, a CSI connector and a 40-pin GPIO header. Signed-off-by: Jens Kuske Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 77 ++++++++++++++++++++ 2 files changed, 79 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e8f44c705089..cc7309be499f 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -661,7 +661,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a33-ga10h-v1.1.dtb \ sun8i-a33-ippo-q8h-v1.2.dtb \ sun8i-a33-q8-tablet.dtb \ - sun8i-a33-sinlinx-sina33.dtb + sun8i-a33-sinlinx-sina33.dtb \ + sun8i-h3-orangepi-plus.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts new file mode 100644 index 000000000000..e67df590535f --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2015 Jens Kuske + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Xunlong Orange Pi Plus"; + compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + cd-inverted; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; From 1ccc4939220cf815c309feddcf82dba260499194 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sat, 5 Dec 2015 21:16:45 +0800 Subject: [PATCH 34/40] ARM: dts: sun4i: Add VE (Video Engine) module clock node The video engine has its own module clock, which also includes a reset control for it. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 849d0242ece8..2c8f5e6ad905 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -520,6 +520,15 @@ dram_gates: clk@01c20100 { "dram_de_mp", "dram_ace"; }; + ve_clk: clk@01c2013c { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-ve-clk"; + reg = <0x01c2013c 0x4>; + clocks = <&pll4>; + clock-output-names = "ve"; + }; + codec_clk: clk@01c20140 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-codec-clk"; From f0571ab140723f9a898d4a404118580534dcc468 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sat, 5 Dec 2015 21:16:47 +0800 Subject: [PATCH 35/40] ARM: dts: sun7i: Add VE (Video Engine) module clock node The video engine has its own module clock, which also includes a reset control for it. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 21169c0a6627..0940a788f824 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -527,6 +527,15 @@ dram_gates: clk@01c20100 { "dram_de_mp", "dram_ace"; }; + ve_clk: clk@01c2013c { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-ve-clk"; + reg = <0x01c2013c 0x4>; + clocks = <&pll4>; + clock-output-names = "ve"; + }; + codec_clk: clk@01c20140 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-codec-clk"; From c807d6e2046347d679e992fe4fe4b1133638a464 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 10 Dec 2015 21:36:29 +0800 Subject: [PATCH 36/40] ARM: dts: sun9i: cubieboard4: Enable LEDs The Cubieboard4 has 2 controllable LEDs, 1 red and 1 green. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 22 +++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts index 6484dcf69873..8791d49bed2d 100644 --- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts +++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts @@ -62,9 +62,31 @@ chosen { stdout-path = "serial0:115200n8"; }; + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_cubieboard4>; + + green { + label = "cubieboard4:green:usr"; + gpios = <&pio 7 17 GPIO_ACTIVE_HIGH>; /* PH17 */ + }; + + red { + label = "cubieboard4:red:usr"; + gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ + }; + }; }; &pio { + led_pins_cubieboard4: led-pins@0 { + allwinner,pins = "PH6", "PH17"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + mmc0_cd_pin_cubieboard4: mmc0_cd_pin@0 { allwinner,pins = "PH18"; allwinner,function = "gpio_in"; From 62b4b20cd2bca593c89896711cac7c913be67e80 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 10 Dec 2015 21:36:30 +0800 Subject: [PATCH 37/40] ARM: dts: sun9i: cubieboard4: Enable consumer IR receiver The Cubieboard4 has a consumer IR receiver. Enable it in the DT. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts index 8791d49bed2d..8c26b556e82a 100644 --- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts +++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts @@ -114,6 +114,10 @@ &mmc2 { status = "okay"; }; +&r_ir { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; From 6f353f61e29a8fc919b5afa1277a98277782f5b1 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 10 Dec 2015 21:36:31 +0800 Subject: [PATCH 38/40] ARM: dts: sun9i: cubieboard4: Enable Reduced Serial Bus controller The Reduced Serial Bus (RSB) controller is used to talk to the 3 companion ICs (2 PMICs, 1 RTC/codec IC) on the board. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts index 8c26b556e82a..382bd9fc5647 100644 --- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts +++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts @@ -118,6 +118,10 @@ &r_ir { status = "okay"; }; +&r_rsb { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; From 15228f04de82c2f6d893926423b71c9ce8c4200e Mon Sep 17 00:00:00 2001 From: Karsten Merker Date: Thu, 10 Dec 2015 21:31:59 +0100 Subject: [PATCH 39/40] ARM: dts: sun7i: Olimex A20-SOM-EVB: Add LRADC keys The Olimex A20-SOM-EVB is an evaluation board for the Olimex A20-SOM system-on-module. It provides a set of android-style buttons (labeled "VOL+", "VOL-", "MENU", "SEARCH", "HOME", "ESC" and "ENTER") which are connected to a low-resolution ADC via a resistor network. This patch adds appropriate button definitions to the board dts. The voltages assigned to the keys are specified in the board schematics published by the manufacturer. Signed-off-by: Karsten Merker Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- .../arm/boot/dts/sun7i-a20-olimex-som-evb.dts | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts index a91879ed07f8..beccb25e88bf 100644 --- a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts +++ b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts @@ -1,5 +1,6 @@ /* * Copyright 2015 - Marcus Cooper + * Copyright 2015 - Karsten Merker * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -45,6 +46,7 @@ #include "sunxi-common-regulators.dtsi" #include +#include #include #include @@ -114,6 +116,60 @@ axp209: pmic@34 { }; }; +&lradc { + vref-supply = <®_vcc3v0>; + status = "okay"; + + button@190 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <190000>; + }; + + button@390 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <390000>; + }; + + button@600 { + label = "Menu"; + linux,code = ; + channel = <0>; + voltage = <600000>; + }; + + button@800 { + label = "Search"; + linux,code = ; + channel = <0>; + voltage = <800000>; + }; + + button@980 { + label = "Home"; + linux,code = ; + channel = <0>; + voltage = <980000>; + }; + + button@1180 { + label = "Esc"; + linux,code = ; + channel = <0>; + voltage = <1180000>; + }; + + button@1400 { + label = "Enter"; + linux,code = ; + channel = <0>; + voltage = <1400000>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; From 2367cee5fda1e9ebc605b13175492b31030acd9d Mon Sep 17 00:00:00 2001 From: Karsten Merker Date: Thu, 10 Dec 2015 21:32:00 +0100 Subject: [PATCH 40/40] ARM: dts: sun7i: Olimex A20-SOM-EVB: Enable mmc3 (baseboard SD socket) The Olimex A20-SOM-EVB is an evaluation board for the Olimex A20-SOM system-on-module. The baseboard provides a full-size SD socket (connected to mmc3) in addition to the micro-SD socket on the SOM itself (which is connected to mmc0). Enable the mmc3 controller in the dts. Signed-off-by: Karsten Merker Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts index beccb25e88bf..c3c626b2cfa2 100644 --- a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts +++ b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts @@ -180,6 +180,16 @@ &mmc0 { status = "okay"; }; +&mmc3 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olimex_som_evb>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 0 GPIO_ACTIVE_HIGH>; /* PH0 */ + cd-inverted; + status = "okay"; +}; + &ohci0 { status = "okay"; }; @@ -202,6 +212,13 @@ led_pins_olimex_som_evb: led_pins@0 { allwinner,drive = ; allwinner,pull = ; }; + + mmc3_cd_pin_olimex_som_evb: mmc3_cd_pin@0 { + allwinner,pins = "PH0"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; }; ®_ahci_5v {