From 72b2d2a6f178b99354eaccfac2c5e9bf5e2fcb53 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Thu, 21 Sep 2023 22:51:49 +0300 Subject: [PATCH] drm/i915/dp: Factor out helpers to compute the link limits MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Factor out helpers that DP / DP_MST encoders can use to compute the link rate/lane count and bpp limits. A follow-up patch will call these to recalculate the limits if DSC compression is required. Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20230921195159.2646027-2-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 71 +++++++++++++-------- drivers/gpu/drm/i915/display/intel_dp_mst.c | 52 ++++++++------- 2 files changed, 73 insertions(+), 50 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index f16d9fa88fe1..04034a4c7a1f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2188,6 +2188,47 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, return 0; } +static void +intel_dp_compute_config_limits(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state, + bool respect_downstream_limits, + struct link_config_limits *limits) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + + limits->min_rate = intel_dp_common_rate(intel_dp, 0); + limits->max_rate = intel_dp_max_link_rate(intel_dp); + + limits->min_lane_count = 1; + limits->max_lane_count = intel_dp_max_lane_count(intel_dp); + + limits->min_bpp = intel_dp_min_bpp(crtc_state->output_format); + limits->max_bpp = intel_dp_max_bpp(intel_dp, crtc_state, + respect_downstream_limits); + + if (intel_dp->use_max_params) { + /* + * Use the maximum clock and number of lanes the eDP panel + * advertizes being capable of in case the initial fast + * optimal params failed us. The panels are generally + * designed to support only a single clock and lane + * configuration, and typically on older panels these + * values correspond to the native resolution of the panel. + */ + limits->min_lane_count = limits->max_lane_count; + limits->min_rate = limits->max_rate; + } + + intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits); + + drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i " + "max rate %d max bpp %d pixel clock %iKHz\n", + limits->max_lane_count, limits->max_rate, + limits->max_bpp, adjusted_mode->crtc_clock); +} + static int intel_dp_compute_link_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, @@ -2203,34 +2244,8 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, bool joiner_needs_dsc = false; int ret; - limits.min_rate = intel_dp_common_rate(intel_dp, 0); - limits.max_rate = intel_dp_max_link_rate(intel_dp); - - limits.min_lane_count = 1; - limits.max_lane_count = intel_dp_max_lane_count(intel_dp); - - limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format); - limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config, respect_downstream_limits); - - if (intel_dp->use_max_params) { - /* - * Use the maximum clock and number of lanes the eDP panel - * advertizes being capable of in case the initial fast - * optimal params failed us. The panels are generally - * designed to support only a single clock and lane - * configuration, and typically on older panels these - * values correspond to the native resolution of the panel. - */ - limits.min_lane_count = limits.max_lane_count; - limits.min_rate = limits.max_rate; - } - - intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits); - - drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i " - "max rate %d max bpp %d pixel clock %iKHz\n", - limits.max_lane_count, limits.max_rate, - limits.max_bpp, adjusted_mode->crtc_clock); + intel_dp_compute_config_limits(intel_dp, pipe_config, + respect_downstream_limits, &limits); if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_clock)) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 0b33190e2d7a..38f31c135506 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -293,6 +293,35 @@ static int intel_dp_mst_update_slots(struct intel_encoder *encoder, return 0; } +static void +intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state, + struct link_config_limits *limits) +{ + /* + * for MST we always configure max link bw - the spec doesn't + * seem to suggest we should do otherwise. + */ + limits->min_rate = limits->max_rate = + intel_dp_max_link_rate(intel_dp); + + limits->min_lane_count = limits->max_lane_count = + intel_dp_max_lane_count(intel_dp); + + limits->min_bpp = intel_dp_min_bpp(crtc_state->output_format); + /* + * FIXME: If all the streams can't fit into the link with + * their current pipe_bpp we should reduce pipe_bpp across + * the board until things start to fit. Until then we + * limit to <= 8bpc since that's what was hardcoded for all + * MST streams previously. This hack should be removed once + * we have the proper retry logic in place. + */ + limits->max_bpp = min(crtc_state->pipe_bpp, 24); + + intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits); +} + static int intel_dp_mst_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state) @@ -312,28 +341,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; pipe_config->has_pch_encoder = false; - /* - * for MST we always configure max link bw - the spec doesn't - * seem to suggest we should do otherwise. - */ - limits.min_rate = - limits.max_rate = intel_dp_max_link_rate(intel_dp); - - limits.min_lane_count = - limits.max_lane_count = intel_dp_max_lane_count(intel_dp); - - limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format); - /* - * FIXME: If all the streams can't fit into the link with - * their current pipe_bpp we should reduce pipe_bpp across - * the board until things start to fit. Until then we - * limit to <= 8bpc since that's what was hardcoded for all - * MST streams previously. This hack should be removed once - * we have the proper retry logic in place. - */ - limits.max_bpp = min(pipe_config->pipe_bpp, 24); - - intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits); + intel_dp_mst_compute_config_limits(intel_dp, pipe_config, &limits); ret = intel_dp_mst_compute_link_config(encoder, pipe_config, conn_state, &limits);