From 2cd517ed4eaf728631eafce645ebf63d0749c679 Mon Sep 17 00:00:00 2001 From: Kaustabh Chakraborty Date: Sat, 16 May 2026 03:08:35 +0530 Subject: [PATCH 01/47] dt-bindings: mfd: Add documentation for S2MU005 PMIC Samsung's S2MU005 PMIC includes subdevices for a charger, an MUIC (Micro USB Interface Controller), and flash and RGB LED controllers. Add the compatible and documentation for the S2MU005 PMIC. Also, add an example for nodes for supported sub-devices, i.e. MUIC, flash LEDs, and RGB LEDs. Charger sub-device uses the node of the parent. Signed-off-by: Kaustabh Chakraborty Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260516-s2mu005-pmic-v7-3-73f9702fb461@disroot.org Signed-off-by: Lee Jones --- .../bindings/mfd/samsung,s2mu005-pmic.yaml | 120 ++++++++++++++++++ 1 file changed, 120 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/samsung,s2mu005-pmic.yaml diff --git a/Documentation/devicetree/bindings/mfd/samsung,s2mu005-pmic.yaml b/Documentation/devicetree/bindings/mfd/samsung,s2mu005-pmic.yaml new file mode 100644 index 000000000000..aff68c035b38 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/samsung,s2mu005-pmic.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/samsung,s2mu005-pmic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S2MU005 Power Management IC + +maintainers: + - Kaustabh Chakraborty + +description: | + The S2MU005 is a companion power management IC which includes subdevices for + a charger controller, an MUIC (Micro USB Interface Controller), and flash and + RGB LED controllers. + +allOf: + - $ref: /schemas/power/supply/power-supply.yaml# + +properties: + compatible: + const: samsung,s2mu005-pmic + + flash: + $ref: /schemas/leds/samsung,s2mu005-flash.yaml# + description: + Child node describing flash LEDs. + + interrupts: + maxItems: 1 + + muic: + $ref: /schemas/extcon/samsung,s2mu005-muic.yaml# + description: + Child node describing MUIC device. + + multi-led: + type: object + + allOf: + - $ref: /schemas/leds/leds-class-multicolor.yaml# + + properties: + compatible: + const: samsung,s2mu005-rgb + + required: + - compatible + + unevaluatedProperties: false + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@3d { + compatible = "samsung,s2mu005-pmic"; + reg = <0x3d>; + interrupt-parent = <&gpa2>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + monitored-battery = <&battery>; + + flash { + compatible = "samsung,s2mu005-flash"; + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_FLASH; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_FLASH; + function-enumerator = <1>; + }; + }; + + muic { + compatible = "samsung,s2mu005-muic"; + + connector { + compatible = "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + }; + + port { + muic_to_usb: endpoint { + remote-endpoint = <&usb_to_muic>; + }; + }; + }; + + multi-led { + compatible = "samsung,s2mu005-rgb"; + color = ; + function = LED_FUNCTION_INDICATOR; + linux,default-trigger = "pattern"; + }; + }; + }; From e491ebea157ff3ba18483ea0f82a9536dc393dec Mon Sep 17 00:00:00 2001 From: Kaustabh Chakraborty Date: Sat, 16 May 2026 03:08:36 +0530 Subject: [PATCH 02/47] mfd: sec: Add support for S2MU005 PMIC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Samsung's S2MU005 PMIC includes subdevices for a charger, an MUIC (Micro USB Interface Controller), and flash and RGB LED controllers. S2MU005's interrupt registers divided into three domains, each for the charger, flash LEDs, and the MUIC, packed into a single regmap IRQ chip construct. In devices other than S2MPG1X, the revision can be retrieved from the first register of the PMIC regmap. In S2MU005 however, the location is in offset 0x73. Introduce a switch-case block to allow selecting the REG_ID register. S2MU005 also has a field mask for the revision. Apply it using FIELD_GET() and get the extracted value. Add initial support for S2MU005 in the PMIC driver, along with its three interrupt chips, and support for allowing to fetch revision based on the device variant. Co-developed-by: Łukasz Lebiedziński Signed-off-by: Łukasz Lebiedziński Signed-off-by: Kaustabh Chakraborty Link: https://patch.msgid.link/20260516-s2mu005-pmic-v7-4-73f9702fb461@disroot.org Signed-off-by: Lee Jones --- drivers/mfd/sec-common.c | 34 ++- drivers/mfd/sec-i2c.c | 29 +++ drivers/mfd/sec-irq.c | 73 ++++++ include/linux/mfd/samsung/core.h | 1 + include/linux/mfd/samsung/irq.h | 66 ++++++ include/linux/mfd/samsung/s2mu005.h | 332 ++++++++++++++++++++++++++++ 6 files changed, 529 insertions(+), 6 deletions(-) create mode 100644 include/linux/mfd/samsung/s2mu005.h diff --git a/drivers/mfd/sec-common.c b/drivers/mfd/sec-common.c index bd8b5f968689..22f6c74eb6c0 100644 --- a/drivers/mfd/sec-common.c +++ b/drivers/mfd/sec-common.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -105,22 +106,39 @@ static const struct mfd_cell s2mpu05_devs[] = { MFD_CELL_RES("s2mps15-rtc", s2mpu05_rtc_resources), }; +static const struct resource s2mu005_muic_resources[] = { + DEFINE_RES_IRQ_NAMED(S2MU005_IRQ_MUIC_ATTACH, "attach"), + DEFINE_RES_IRQ_NAMED(S2MU005_IRQ_MUIC_DETACH, "detach"), +}; + +static const struct mfd_cell s2mu005_devs[] = { + MFD_CELL_NAME("s2mu005-charger"), + MFD_CELL_OF("s2mu005-flash", NULL, NULL, 0, 0, "samsung,s2mu005-flash"), + MFD_CELL_OF("s2mu005-muic", s2mu005_muic_resources, NULL, 0, 0, "samsung,s2mu005-muic"), + MFD_CELL_OF("s2mu005-rgb", NULL, NULL, 0, 0, "samsung,s2mu005-rgb"), +}; + static void sec_pmic_dump_rev(struct sec_pmic_dev *sec_pmic) { - unsigned int val; + unsigned int reg, mask, val; - /* For s2mpg1x, the revision is in a different regmap */ switch (sec_pmic->device_type) { case S2MPG10: case S2MPG11: + /* For s2mpg1x, the revision is in a different regmap */ return; - default: + case S2MU005: + reg = S2MU005_REG_ID; + mask = S2MU005_ID_MASK; break; + default: + /* For other device types, REG_ID is always the first register. */ + reg = S2MPS11_REG_ID; + mask = ~0; } - /* For each device type, the REG_ID is always the first register */ - if (!regmap_read(sec_pmic->regmap_pmic, S2MPS11_REG_ID, &val)) - dev_dbg(sec_pmic->dev, "Revision: 0x%x\n", val); + if (!regmap_read(sec_pmic->regmap_pmic, reg, &val)) + dev_dbg(sec_pmic->dev, "Revision: 0x%x\n", field_get(mask, val)); } static void sec_pmic_configure(struct sec_pmic_dev *sec_pmic) @@ -250,6 +268,10 @@ int sec_pmic_probe(struct device *dev, int device_type, unsigned int irq, sec_devs = s2mpu05_devs; num_sec_devs = ARRAY_SIZE(s2mpu05_devs); break; + case S2MU005: + sec_devs = s2mu005_devs; + num_sec_devs = ARRAY_SIZE(s2mu005_devs); + break; default: return dev_err_probe(sec_pmic->dev, -EINVAL, "Unsupported device type %d\n", diff --git a/drivers/mfd/sec-i2c.c b/drivers/mfd/sec-i2c.c index 3132b849b4bc..d8609886fcc8 100644 --- a/drivers/mfd/sec-i2c.c +++ b/drivers/mfd/sec-i2c.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -66,6 +67,19 @@ static bool s2mpu02_volatile(struct device *dev, unsigned int reg) } } +static bool s2mu005_volatile(struct device *dev, unsigned int reg) +{ + switch (reg) { + case S2MU005_REG_CHGR_INT1M: + case S2MU005_REG_FLED_INT1M: + case S2MU005_REG_MUIC_INT1M: + case S2MU005_REG_MUIC_INT2M: + return false; + default: + return true; + } +} + static const struct regmap_config s2dos05_regmap_config = { .reg_bits = 8, .val_bits = 8, @@ -130,6 +144,15 @@ static const struct regmap_config s2mpu05_regmap_config = { .val_bits = 8, }; +static const struct regmap_config s2mu005_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + + .max_register = S2MU005_REG_MUIC_LDOADC_H, + .volatile_reg = s2mu005_volatile, + .cache_type = REGCACHE_FLAT_S, +}; + static const struct regmap_config s5m8767_regmap_config = { .reg_bits = 8, .val_bits = 8, @@ -203,6 +226,11 @@ static const struct sec_pmic_i2c_platform_data s2mpu05_data = { .device_type = S2MPU05, }; +static const struct sec_pmic_i2c_platform_data s2mu005_data = { + .regmap_cfg = &s2mu005_regmap_config, + .device_type = S2MU005, +}; + static const struct sec_pmic_i2c_platform_data s5m8767_data = { .regmap_cfg = &s5m8767_regmap_config, .device_type = S5M8767X, @@ -217,6 +245,7 @@ static const struct of_device_id sec_pmic_i2c_of_match[] = { { .compatible = "samsung,s2mps15-pmic", .data = &s2mps15_data, }, { .compatible = "samsung,s2mpu02-pmic", .data = &s2mpu02_data, }, { .compatible = "samsung,s2mpu05-pmic", .data = &s2mpu05_data, }, + { .compatible = "samsung,s2mu005-pmic", .data = &s2mu005_data, }, { .compatible = "samsung,s5m8767-pmic", .data = &s5m8767_data, }, { }, }; diff --git a/drivers/mfd/sec-irq.c b/drivers/mfd/sec-irq.c index 133188391f7c..42862807be1a 100644 --- a/drivers/mfd/sec-irq.c +++ b/drivers/mfd/sec-irq.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include "sec-core.h" @@ -223,6 +224,65 @@ static const struct regmap_irq s2mpu05_irqs[] = { REGMAP_IRQ_REG(S2MPU05_IRQ_TSD, 2, S2MPU05_IRQ_TSD_MASK), }; +static const struct regmap_irq s2mu005_irqs[] = { + REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_DETBAT, 0, S2MU005_IRQ_CHGR_DETBAT_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_BAT, 0, S2MU005_IRQ_CHGR_BAT_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_IVR, 0, S2MU005_IRQ_CHGR_IVR_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_EVENT, 0, S2MU005_IRQ_CHGR_EVENT_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_CHG, 0, S2MU005_IRQ_CHGR_CHG_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_VMID, 0, S2MU005_IRQ_CHGR_VMID_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_WCIN, 0, S2MU005_IRQ_CHGR_WCIN_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_VBUS, 0, S2MU005_IRQ_CHGR_VBUS_MASK), + + REGMAP_IRQ_REG(S2MU005_IRQ_FLED_LBPROT, 1, S2MU005_IRQ_FLED_LBPROT_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_FLED_OPENCH2, 1, S2MU005_IRQ_FLED_OPENCH2_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_FLED_OPENCH1, 1, S2MU005_IRQ_FLED_OPENCH1_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_FLED_SHORTCH2, 1, S2MU005_IRQ_FLED_SHORTCH2_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_FLED_SHORTCH1, 1, S2MU005_IRQ_FLED_SHORTCH1_MASK), + + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_ATTACH, 2, S2MU005_IRQ_MUIC_ATTACH_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_DETACH, 2, S2MU005_IRQ_MUIC_DETACH_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_KP, 2, S2MU005_IRQ_MUIC_KP_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_LKP, 2, S2MU005_IRQ_MUIC_LKP_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_LKR, 2, S2MU005_IRQ_MUIC_LKR_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_RIDCHG, 2, S2MU005_IRQ_MUIC_RIDCHG_MASK), + + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_VBUSON, 3, S2MU005_IRQ_MUIC_VBUSON_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_RSVD, 3, S2MU005_IRQ_MUIC_RSVD_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_ADC, 3, S2MU005_IRQ_MUIC_ADC_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_STUCK, 3, S2MU005_IRQ_MUIC_STUCK_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_STUCKRCV, 3, S2MU005_IRQ_MUIC_STUCKRCV_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_MHDL, 3, S2MU005_IRQ_MUIC_MHDL_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_AVCHG, 3, S2MU005_IRQ_MUIC_AVCHG_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_VBUSOFF, 3, S2MU005_IRQ_MUIC_VBUSOFF_MASK), +}; + +static unsigned int s2mu005_irq_get_reg(struct regmap_irq_chip_data *data, + unsigned int base, int index) +{ + const unsigned int irqf_regs[] = { + S2MU005_REG_CHGR_INT1, + S2MU005_REG_FLED_INT1, + S2MU005_REG_MUIC_INT1, + S2MU005_REG_MUIC_INT2, + }; + const unsigned int mask_regs[] = { + S2MU005_REG_CHGR_INT1M, + S2MU005_REG_FLED_INT1M, + S2MU005_REG_MUIC_INT1M, + S2MU005_REG_MUIC_INT2M, + }; + + switch (base) { + case S2MU005_REG_CHGR_INT1: + return irqf_regs[index]; + case S2MU005_REG_CHGR_INT1M: + return mask_regs[index]; + } + + return base; +} + static const struct regmap_irq s5m8767_irqs[] = { REGMAP_IRQ_REG(S5M8767_IRQ_PWRR, 0, S5M8767_IRQ_PWRR_MASK), REGMAP_IRQ_REG(S5M8767_IRQ_PWRF, 0, S5M8767_IRQ_PWRF_MASK), @@ -337,6 +397,16 @@ static const struct regmap_irq_chip s2mpu05_irq_chip = { .ack_base = S2MPU05_REG_INT1, }; +static const struct regmap_irq_chip s2mu005_irq_chip = { + .name = "s2mu005", + .irqs = s2mu005_irqs, + .num_irqs = ARRAY_SIZE(s2mu005_irqs), + .num_regs = 4, + .status_base = S2MU005_REG_CHGR_INT1, + .mask_base = S2MU005_REG_CHGR_INT1M, + .get_irq_reg = s2mu005_irq_get_reg, +}; + static const struct regmap_irq_chip s5m8767_irq_chip = { .name = "s5m8767", .irqs = s5m8767_irqs, @@ -442,6 +512,9 @@ struct regmap_irq_chip_data *sec_irq_init(struct sec_pmic_dev *sec_pmic) case S2MPU05: sec_irq_chip = &s2mpu05_irq_chip; break; + case S2MU005: + sec_irq_chip = &s2mu005_irq_chip; + break; default: return dev_err_ptr_probe(sec_pmic->dev, -EINVAL, "Unsupported device type %d\n", sec_pmic->device_type); diff --git a/include/linux/mfd/samsung/core.h b/include/linux/mfd/samsung/core.h index 4480c631110a..6191f409de94 100644 --- a/include/linux/mfd/samsung/core.h +++ b/include/linux/mfd/samsung/core.h @@ -47,6 +47,7 @@ enum sec_device_type { S2MPS15X, S2MPU02, S2MPU05, + S2MU005, }; /** diff --git a/include/linux/mfd/samsung/irq.h b/include/linux/mfd/samsung/irq.h index 6eab95de6fa8..19d0f0e12944 100644 --- a/include/linux/mfd/samsung/irq.h +++ b/include/linux/mfd/samsung/irq.h @@ -408,6 +408,72 @@ enum s2mpu05_irq { #define S2MPU05_IRQ_INT140C_MASK BIT(1) #define S2MPU05_IRQ_TSD_MASK BIT(2) +enum s2mu005_irq { + S2MU005_IRQ_CHGR_DETBAT, + S2MU005_IRQ_CHGR_BAT, + S2MU005_IRQ_CHGR_IVR, + S2MU005_IRQ_CHGR_EVENT, + S2MU005_IRQ_CHGR_CHG, + S2MU005_IRQ_CHGR_VMID, + S2MU005_IRQ_CHGR_WCIN, + S2MU005_IRQ_CHGR_VBUS, + + S2MU005_IRQ_FLED_LBPROT, + S2MU005_IRQ_FLED_OPENCH2, + S2MU005_IRQ_FLED_OPENCH1, + S2MU005_IRQ_FLED_SHORTCH2, + S2MU005_IRQ_FLED_SHORTCH1, + + S2MU005_IRQ_MUIC_ATTACH, + S2MU005_IRQ_MUIC_DETACH, + S2MU005_IRQ_MUIC_KP, + S2MU005_IRQ_MUIC_LKP, + S2MU005_IRQ_MUIC_LKR, + S2MU005_IRQ_MUIC_RIDCHG, + + S2MU005_IRQ_MUIC_VBUSON, + S2MU005_IRQ_MUIC_RSVD, + S2MU005_IRQ_MUIC_ADC, + S2MU005_IRQ_MUIC_STUCK, + S2MU005_IRQ_MUIC_STUCKRCV, + S2MU005_IRQ_MUIC_MHDL, + S2MU005_IRQ_MUIC_AVCHG, + S2MU005_IRQ_MUIC_VBUSOFF, + + S2MU005_IRQ_NR, +}; + +#define S2MU005_IRQ_CHGR_DETBAT_MASK BIT(0) +#define S2MU005_IRQ_CHGR_BAT_MASK BIT(1) +#define S2MU005_IRQ_CHGR_IVR_MASK BIT(2) +#define S2MU005_IRQ_CHGR_EVENT_MASK BIT(3) +#define S2MU005_IRQ_CHGR_CHG_MASK BIT(4) +#define S2MU005_IRQ_CHGR_VMID_MASK BIT(5) +#define S2MU005_IRQ_CHGR_WCIN_MASK BIT(6) +#define S2MU005_IRQ_CHGR_VBUS_MASK BIT(7) + +#define S2MU005_IRQ_FLED_LBPROT_MASK BIT(2) +#define S2MU005_IRQ_FLED_OPENCH2_MASK BIT(4) +#define S2MU005_IRQ_FLED_OPENCH1_MASK BIT(5) +#define S2MU005_IRQ_FLED_SHORTCH2_MASK BIT(6) +#define S2MU005_IRQ_FLED_SHORTCH1_MASK BIT(7) + +#define S2MU005_IRQ_MUIC_ATTACH_MASK BIT(0) +#define S2MU005_IRQ_MUIC_DETACH_MASK BIT(1) +#define S2MU005_IRQ_MUIC_KP_MASK BIT(2) +#define S2MU005_IRQ_MUIC_LKP_MASK BIT(3) +#define S2MU005_IRQ_MUIC_LKR_MASK BIT(4) +#define S2MU005_IRQ_MUIC_RIDCHG_MASK BIT(5) + +#define S2MU005_IRQ_MUIC_VBUSON_MASK BIT(0) +#define S2MU005_IRQ_MUIC_RSVD_MASK BIT(1) +#define S2MU005_IRQ_MUIC_ADC_MASK BIT(2) +#define S2MU005_IRQ_MUIC_STUCK_MASK BIT(3) +#define S2MU005_IRQ_MUIC_STUCKRCV_MASK BIT(4) +#define S2MU005_IRQ_MUIC_MHDL_MASK BIT(5) +#define S2MU005_IRQ_MUIC_AVCHG_MASK BIT(6) +#define S2MU005_IRQ_MUIC_VBUSOFF_MASK BIT(7) + enum s5m8767_irq { S5M8767_IRQ_PWRR, S5M8767_IRQ_PWRF, diff --git a/include/linux/mfd/samsung/s2mu005.h b/include/linux/mfd/samsung/s2mu005.h new file mode 100644 index 000000000000..46e7759545af --- /dev/null +++ b/include/linux/mfd/samsung/s2mu005.h @@ -0,0 +1,332 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2015 Samsung Electronics Co., Ltd + * Copyright (c) 2026 Kaustabh Chakraborty + * Copyright (c) 2026 Łukasz Lebiedziński + */ + +#ifndef __LINUX_MFD_S2MU005_H +#define __LINUX_MFD_S2MU005_H + +#include +#include + +/* S2MU005 registers */ +enum s2mu005_reg { + S2MU005_REG_CHGR_INT1, + S2MU005_REG_CHGR_INT1M, + + S2MU005_REG_FLED_INT1, + S2MU005_REG_FLED_INT1M, + + S2MU005_REG_MUIC_INT1, + S2MU005_REG_MUIC_INT2, + S2MU005_REG_MUIC_INT1M, + S2MU005_REG_MUIC_INT2M, + + S2MU005_REG_CHGR_STATUS0, + S2MU005_REG_CHGR_STATUS1, + S2MU005_REG_CHGR_STATUS2, + S2MU005_REG_CHGR_STATUS3, + S2MU005_REG_CHGR_STATUS4, + S2MU005_REG_CHGR_STATUS5, + S2MU005_REG_CHGR_CTRL0, + S2MU005_REG_CHGR_CTRL1, + S2MU005_REG_CHGR_CTRL2, + S2MU005_REG_CHGR_CTRL3, + S2MU005_REG_CHGR_CTRL4, + S2MU005_REG_CHGR_CTRL5, + S2MU005_REG_CHGR_CTRL6, + S2MU005_REG_CHGR_CTRL7, + S2MU005_REG_CHGR_CTRL8, + S2MU005_REG_CHGR_CTRL9, + S2MU005_REG_CHGR_CTRL10, + S2MU005_REG_CHGR_CTRL11, + S2MU005_REG_CHGR_CTRL12, + S2MU005_REG_CHGR_CTRL13, + S2MU005_REG_CHGR_CTRL14, + S2MU005_REG_CHGR_CTRL15, + S2MU005_REG_CHGR_CTRL16, + S2MU005_REG_CHGR_CTRL17, + S2MU005_REG_CHGR_CTRL18, + S2MU005_REG_CHGR_CTRL19, + S2MU005_REG_CHGR_TEST0, + S2MU005_REG_CHGR_TEST1, + S2MU005_REG_CHGR_TEST2, + S2MU005_REG_CHGR_TEST3, + S2MU005_REG_CHGR_TEST4, + S2MU005_REG_CHGR_TEST5, + S2MU005_REG_CHGR_TEST6, + S2MU005_REG_CHGR_TEST7, + S2MU005_REG_CHGR_TEST8, + S2MU005_REG_CHGR_TEST9, + S2MU005_REG_CHGR_TEST10, + + S2MU005_REG_FLED_STATUS, + S2MU005_REG_FLED_CH0_CTRL0, + S2MU005_REG_FLED_CH0_CTRL1, + S2MU005_REG_FLED_CH0_CTRL2, + S2MU005_REG_FLED_CH0_CTRL3, + S2MU005_REG_FLED_CH1_CTRL0, + S2MU005_REG_FLED_CH1_CTRL1, + S2MU005_REG_FLED_CH1_CTRL2, + S2MU005_REG_FLED_CH1_CTRL3, + S2MU005_REG_FLED_CTRL0, + S2MU005_REG_FLED_CTRL1, + S2MU005_REG_FLED_CTRL2, + S2MU005_REG_FLED_CTRL3, + S2MU005_REG_FLED_CTRL4, + S2MU005_REG_FLED_CTRL5, + S2MU005_REG_FLED_CTRL6, + + S2MU005_REG_RGB_EN, + S2MU005_REG_RGB_CH0_CTRL, + S2MU005_REG_RGB_CH1_CTRL, + S2MU005_REG_RGB_CH2_CTRL, + S2MU005_REG_RGB_CH0_RAMP, + S2MU005_REG_RGB_CH0_STAY, + S2MU005_REG_RGB_CH1_RAMP, + S2MU005_REG_RGB_CH1_STAY, + S2MU005_REG_RGB_CH2_RAMP, + S2MU005_REG_RGB_CH2_STAY, + S2MU005_REG_RGB_TEST0, + S2MU005_REG_RGB_CTRL0, + + S2MU005_REG_MUIC_ADC, + S2MU005_REG_MUIC_DEV1, + S2MU005_REG_MUIC_DEV2, + S2MU005_REG_MUIC_DEV3, + S2MU005_REG_MUIC_BUTTON1, + S2MU005_REG_MUIC_BUTTON2, + S2MU005_REG_MUIC_RESET, + S2MU005_REG_MUIC_CHGTYPE, + S2MU005_REG_MUIC_DEVAPPLE, + S2MU005_REG_MUIC_BCDRESCAN, + S2MU005_REG_MUIC_TEST1, + S2MU005_REG_MUIC_TEST2, + S2MU005_REG_MUIC_TEST3, + + S2MU005_REG_ID = 0x73, + + S2MU005_REG_MUIC_CTRL1 = 0xb2, + S2MU005_REG_MUIC_TIMERSET1, + S2MU005_REG_MUIC_TIMERSET2, + S2MU005_REG_MUIC_SWCTRL, + S2MU005_REG_MUIC_TIMERSET3, + S2MU005_REG_MUIC_CTRL2, + S2MU005_REG_MUIC_CTRL3, + + S2MU005_REG_MUIC_LDOADC_L = 0xbf, + S2MU005_REG_MUIC_LDOADC_H, +}; + +#define S2MU005_REG_FLED_CH_CTRL0(x) (S2MU005_REG_FLED_CH0_CTRL0 + 4 * (x)) +#define S2MU005_REG_FLED_CH_CTRL1(x) (S2MU005_REG_FLED_CH0_CTRL1 + 4 * (x)) +#define S2MU005_REG_FLED_CH_CTRL2(x) (S2MU005_REG_FLED_CH0_CTRL2 + 4 * (x)) +#define S2MU005_REG_FLED_CH_CTRL3(x) (S2MU005_REG_FLED_CH0_CTRL3 + 4 * (x)) + +#define S2MU005_REG_RGB_CH_CTRL(x) (S2MU005_REG_RGB_CH0_CTRL + 1 * (x)) +#define S2MU005_REG_RGB_CH_RAMP(x) (S2MU005_REG_RGB_CH0_RAMP + 2 * (x)) +#define S2MU005_REG_RGB_CH_STAY(x) (S2MU005_REG_RGB_CH0_STAY + 2 * (x)) + +/* S2MU005_REG_CHGR_STATUS0 */ +#define S2MU005_CHGR_VBUS BIT(7) +#define S2MU005_CHGR_WCIN BIT(6) +#define S2MU005_CHGR_VMID BIT(5) +#define S2MU005_CHGR_CHG BIT(4) +#define S2MU005_CHGR_STAT GENMASK(3, 0) + +#define S2MU005_CHGR_STAT_DONE 8 +#define S2MU005_CHGR_STAT_TOPOFF 7 +#define S2MU005_CHGR_STAT_DONE_FLAG 6 +#define S2MU005_CHGR_STAT_CV 5 +#define S2MU005_CHGR_STAT_CC 4 +#define S2MU005_CHGR_STAT_COOL_CHG 3 +#define S2MU005_CHGR_STAT_PRE_CHG 2 + +/* S2MU005_REG_CHGR_STATUS1 */ +#define S2MU005_CHGR_DETBAT BIT(7) +#define S2MU005_CHGR_VBUS_OVP GENMASK(6, 4) + +#define S2MU005_CHGR_VBUS_OVP_OVERVOLT 2 + +/* S2MU005_REG_CHGR_STATUS2 */ +#define S2MU005_CHGR_BAT GENMASK(6, 4) + +#define S2MU005_CHGR_BAT_VOLT_DET 7 +#define S2MU005_CHGR_BAT_FAST_CHG_DET 6 +#define S2MU005_CHGR_BAT_COOL_CHG_DET 5 +#define S2MU005_CHGR_BAT_LOW_CHG 2 +#define S2MU005_CHGR_BAT_SELF_DISCHG 1 +#define S2MU005_CHGR_BAT_OVP_DET 0 + +/* S2MU005_REG_CHGR_STATUS3 */ +#define S2MU005_CHGR_EVT GENMASK(3, 0) + +#define S2MU005_CHGR_EVT_WDT_RST 6 +#define S2MU005_CHGR_EVT_WDT_SUSP 5 +#define S2MU005_CHGR_EVT_VSYS_VUVLO 4 +#define S2MU005_CHGR_EVT_VSYS_VOVP 3 +#define S2MU005_CHGR_EVT_THERM_FOLDBACK 2 +#define S2MU005_CHGR_EVT_THERM_SHUTDOWN 1 + +/* S2MU005_REG_CHGR_CTRL0 */ +#define S2MU005_CHGR_CHG_EN BIT(4) +#define S2MU005_CHGR_OP_MODE GENMASK(2, 0) + +#define S2MU005_CHGR_OP_MODE_OTG BIT(2) +#define S2MU005_CHGR_OP_MODE_CHG BIT(1) + +/* S2MU005_REG_CHGR_CTRL1 */ +#define S2MU005_CHGR_VIN_DROP GENMASK(6, 4) + +/* S2MU005_REG_CHGR_CTRL2 */ +#define S2MU005_CHGR_IN_CURR_LIM GENMASK(5, 0) + +/* S2MU005_REG_CHGR_CTRL4 */ +#define S2MU005_CHGR_OTG_OCP_ON BIT(5) +#define S2MU005_CHGR_OTG_OCP_OFF BIT(4) +#define S2MU005_CHGR_OTG_OCP GENMASK(3, 2) +#define S2MU005_CHGR_OTG_OCP_1P5A 0x3 + +/* S2MU005_REG_CHGR_CTRL5 */ +#define S2MU005_CHGR_VMID_BOOST GENMASK(4, 0) +#define S2MU005_CHGR_VMID_BOOST_5P1V 0x16 + +/* S2MU005_REG_CHGR_CTRL6 */ +#define S2MU005_CHGR_COOL_CHG_CURR GENMASK(5, 0) + +/* S2MU005_REG_CHGR_CTRL7 */ +#define S2MU005_CHGR_FAST_CHG_CURR GENMASK(5, 0) + +/* S2MU005_REG_CHGR_CTRL8 */ +#define S2MU005_CHGR_VF_VBAT GENMASK(6, 1) + +/* S2MU005_REG_CHGR_CTRL10 */ +#define S2MU005_CHGR_TOPOFF_CURR(x) (GENMASK(3, 0) << 4 * (x)) + +/* S2MU005_REG_CHGR_CTRL11 */ +#define S2MU005_CHGR_OSC_BOOST GENMASK(6, 5) +#define S2MU005_CHGR_OSC_BUCK GENMASK(4, 3) +#define S2MU005_CHGR_OSC_BOOST_2MHZ 0x3 + +/* S2MU005_REG_CHGR_CTRL12 */ +#define S2MU005_CHGR_WDT GENMASK(2, 0) + +#define S2MU005_CHGR_WDT_ON BIT(2) +#define S2MU005_CHGR_WDT_OFF BIT(1) + +/* S2MU005_REG_CHGR_CTRL15 */ +#define S2MU005_CHGR_OTG_EN GENMASK(3, 2) +#define S2MU005_CHGR_OTG_EN_ON 0x3 + +/* S2MU005_REG_FLED_STATUS */ +#define S2MU005_FLED_FLASH_STATUS(x) (BIT(7) >> 2 * (x)) +#define S2MU005_FLED_TORCH_STATUS(x) (BIT(6) >> 2 * (x)) + +/* S2MU005_REG_FLED_CHx_CTRL0 */ +#define S2MU005_FLED_FLASH_IOUT GENMASK(3, 0) + +/* S2MU005_REG_FLED_CHx_CTRL1 */ +#define S2MU005_FLED_TORCH_IOUT GENMASK(3, 0) + +/* S2MU005_REG_FLED_CHx_CTRL2 */ +#define S2MU005_FLED_TORCH_TIMEOUT GENMASK(3, 0) + +/* S2MU005_REG_FLED_CHx_CTRL3 */ +#define S2MU005_FLED_FLASH_TIMEOUT GENMASK(3, 0) + +/* S2MU005_REG_FLED_CTRL1 */ +#define S2MU005_FLED_CH_EN BIT(7) + +/* + * S2MU005_REG_FLED_CTRL4 - Rev. EVT0 + * S2MU005_REG_FLED_CTRL6 - Rev. EVT1 and later + */ +#define S2MU005_FLED_FLASH_EN(x) (GENMASK(7, 6) >> 4 * (x)) +#define S2MU005_FLED_TORCH_EN(x) (GENMASK(5, 4) >> 4 * (x)) + +/* S2MU005_REG_RGB_EN */ +#define S2MU005_RGB_RESET BIT(6) +#define S2MU005_RGB_SLOPE GENMASK(5, 0) + +#define S2MU005_RGB_SLOPE_CONST (BIT(4) | BIT(2) | BIT(0)) +#define S2MU005_RGB_SLOPE_SMOOTH (BIT(5) | BIT(3) | BIT(1)) + +/* S2MU005_REG_RGB_CHx_RAMP */ +#define S2MU005_RGB_CH_RAMP_UP GENMASK(7, 4) +#define S2MU005_RGB_CH_RAMP_DN GENMASK(3, 0) + +/* S2MU005_REG_RGB_CHx_STAY */ +#define S2MU005_RGB_CH_STAY_HI GENMASK(7, 4) +#define S2MU005_RGB_CH_STAY_LO GENMASK(3, 0) + +/* S2MU005_REG_MUIC_DEV1 */ +#define S2MU005_MUIC_OTG BIT(7) +#define S2MU005_MUIC_DCP BIT(6) +#define S2MU005_MUIC_CDP BIT(5) +#define S2MU005_MUIC_T1_T2_CHG BIT(4) +#define S2MU005_MUIC_UART BIT(3) +#define S2MU005_MUIC_SDP BIT(2) +#define S2MU005_MUIC_LANHUB BIT(1) +#define S2MU005_MUIC_AUDIO BIT(0) + +/* S2MU005_REG_MUIC_DEV2 */ +#define S2MU005_MUIC_SDP_1P8S BIT(7) +#define S2MU005_MUIC_AV BIT(6) +#define S2MU005_MUIC_TTY BIT(5) +#define S2MU005_MUIC_PPD BIT(4) +#define S2MU005_MUIC_JIG_UART_OFF BIT(3) +#define S2MU005_MUIC_JIG_UART_ON BIT(2) +#define S2MU005_MUIC_JIG_USB_OFF BIT(1) +#define S2MU005_MUIC_JIG_USB_ON BIT(0) + +/* S2MU005_REG_MUIC_DEV3 */ +#define S2MU005_MUIC_U200_CHG BIT(7) +#define S2MU005_MUIC_VBUS_AV BIT(4) +#define S2MU005_MUIC_VBUS_R255 BIT(1) +#define S2MU005_MUIC_MHL BIT(0) + +/* S2MU005_REG_MUIC_DEVAPPLE */ +#define S2MU005_MUIC_APPLE_CHG_0P5A BIT(7) +#define S2MU005_MUIC_APPLE_CHG_1P0A BIT(6) +#define S2MU005_MUIC_APPLE_CHG_2P0A BIT(5) +#define S2MU005_MUIC_APPLE_CHG_2P4A BIT(4) +#define S2MU005_MUIC_SDP_DCD_OUT BIT(3) +#define S2MU005_MUIC_RID_WAKEUP BIT(2) +#define S2MU005_MUIC_VBUS_WAKEUP BIT(1) +#define S2MU005_MUIC_BCV1P2_OR_OPEN BIT(0) + +/* S2MU005_REG_ID */ +#define S2MU005_ID_MASK GENMASK(3, 0) + +/* S2MU005_REG_MUIC_SWCTRL */ +#define S2MU005_MUIC_DM_DP GENMASK(7, 2) +#define S2MU005_MUIC_JIG BIT(0) + +#define S2MU005_MUIC_DM_DP_UART 0x12 +#define S2MU005_MUIC_DM_DP_USB 0x09 + +/* S2MU005_REG_MUIC_CTRL1 */ +#define S2MU005_MUIC_OPEN BIT(4) +#define S2MU005_MUIC_RAW_DATA BIT(3) +#define S2MU005_MUIC_MAN_SW BIT(2) +#define S2MU005_MUIC_WAIT BIT(1) +#define S2MU005_MUIC_IRQ BIT(0) + +/* S2MU005_REG_MUIC_CTRL3 */ +#define S2MU005_MUIC_ONESHOT_ADC BIT(2) + +/* S2MU005_REG_MUIC_LDOADC_L and S2MU005_REG_MUIC_LDOADC_H */ +#define S2MU005_MUIC_VSET GENMASK(4, 0) + +#define S2MU005_MUIC_VSET_3P0V 0x1f +#define S2MU005_MUIC_VSET_2P6V 0x0e +#define S2MU005_MUIC_VSET_2P4V 0x0c +#define S2MU005_MUIC_VSET_2P2V 0x0a +#define S2MU005_MUIC_VSET_2P0V 0x08 +#define S2MU005_MUIC_VSET_1P5V 0x03 +#define S2MU005_MUIC_VSET_1P4V 0x02 +#define S2MU005_MUIC_VSET_1P2V 0x00 + +#endif /* __LINUX_MFD_S2MU005_H */ From 9e667b8ebd5d8229cf523372bf62660f1090c8a0 Mon Sep 17 00:00:00 2001 From: Kaustabh Chakraborty Date: Sat, 16 May 2026 03:08:37 +0530 Subject: [PATCH 03/47] mfd: sec: Set DMA coherent mask Kernel logs are filled with "DMA mask not set" messages for every sub-device. The device does not use DMA for communication, so these messages are useless. Disable the coherent DMA mask for the PMIC device, which is also propagated to sub-devices. Signed-off-by: Kaustabh Chakraborty Link: https://patch.msgid.link/20260516-s2mu005-pmic-v7-5-73f9702fb461@disroot.org Signed-off-by: Lee Jones --- drivers/mfd/sec-common.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mfd/sec-common.c b/drivers/mfd/sec-common.c index 22f6c74eb6c0..fe92bc4a3dd2 100644 --- a/drivers/mfd/sec-common.c +++ b/drivers/mfd/sec-common.c @@ -221,6 +221,9 @@ int sec_pmic_probe(struct device *dev, int device_type, unsigned int irq, if (IS_ERR(irq_data)) return PTR_ERR(irq_data); + dev->coherent_dma_mask = 0; + dev->dma_mask = &dev->coherent_dma_mask; + pm_runtime_set_active(sec_pmic->dev); switch (sec_pmic->device_type) { From f5f40b828179361862cac6c9d3c0e975e573dc3e Mon Sep 17 00:00:00 2001 From: Wenyuan Li <2063309626@qq.com> Date: Wed, 1 Apr 2026 13:09:31 +0800 Subject: [PATCH 04/47] mfd: tps65910: Add error handling for dummy I2C transfer in probe In tps65910_i2c_probe(), a dummy I2C transfer is performed to work around silicon erratum SWCZ010. However, the return value of i2c_master_send() is not checked. If this dummy transfer fails, the driver continues execution without detecting the error. This may lead to subsequent I2C operations also failing, but the driver would incorrectly report success. Add proper return value checking for the dummy I2C transfer. If the transfer fails, log the error and return an appropriate error code to the caller. Signed-off-by: Wenyuan Li <2063309626@qq.com> Link: https://patch.msgid.link/tencent_01102156392EC89EDF2CA22A7C8B4ABB2509@qq.com Signed-off-by: Lee Jones --- drivers/mfd/tps65910.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/mfd/tps65910.c b/drivers/mfd/tps65910.c index 6a7b7a697fb7..6243b66b1b6f 100644 --- a/drivers/mfd/tps65910.c +++ b/drivers/mfd/tps65910.c @@ -21,6 +21,9 @@ #include #include +/* Dummy I2C transfer length for SWCZ010 workaround */ +#define TPS65910_DUMMY_XFER_LEN 1 + static const struct resource rtc_resources[] = { { .start = TPS65910_IRQ_RTC_ALARM, @@ -472,7 +475,18 @@ static int tps65910_i2c_probe(struct i2c_client *i2c) * first I2C transfer. So issue a dummy transfer before the first * real transfer. */ - i2c_master_send(i2c, "", 1); + ret = i2c_master_send(i2c, "", TPS65910_DUMMY_XFER_LEN); + if (ret != TPS65910_DUMMY_XFER_LEN) { + int err; + + if (ret < 0) + err = ret; + else + err = -EIO; + + return dev_err_probe(&i2c->dev, err, "dummy transfer failed\n"); + } + tps65910->regmap = devm_regmap_init_i2c(i2c, &tps65910_regmap_config); if (IS_ERR(tps65910->regmap)) { ret = PTR_ERR(tps65910->regmap); From 104cd764a031bfe2ffe253adce9581384a78c16e Mon Sep 17 00:00:00 2001 From: Akashdeep Kaur Date: Wed, 1 Apr 2026 16:52:57 +0530 Subject: [PATCH 05/47] mfd: tps65219: Make poweroff handler conditional on system-power-controller Currently, the TPS65219 driver unconditionally registers a poweroff handler. This causes issues on systems where a different component (such as TF-A firmware) should handle system poweroff instead. Make the poweroff handler registration conditional based on the "system-power-controller" device tree property. This follows the standard kernel pattern where only the designated power controller registers for system poweroff operations. On systems where the property is absent, the PMIC will not register a poweroff handler, allowing other poweroff mechanisms to function. Signed-off-by: Akashdeep Kaur Link: https://patch.msgid.link/20260401112257.1248437-3-a-kaur@ti.com Signed-off-by: Lee Jones --- drivers/mfd/tps65219.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/mfd/tps65219.c b/drivers/mfd/tps65219.c index 7275dcdb7c44..e52fbf1481fe 100644 --- a/drivers/mfd/tps65219.c +++ b/drivers/mfd/tps65219.c @@ -541,13 +541,15 @@ static int tps65219_probe(struct i2c_client *client) return ret; } - ret = devm_register_power_off_handler(tps->dev, - tps65219_power_off_handler, - tps); - if (ret) { - dev_err(tps->dev, "failed to register power-off handler: %d\n", ret); - return ret; + if (of_device_is_system_power_controller(tps->dev->of_node)) { + ret = devm_register_power_off_handler(tps->dev, + tps65219_power_off_handler, + tps); + if (ret) + return dev_err_probe(tps->dev, ret, + "Failed to register power-off handler\n"); } + return 0; } From 3c8658d6b55564167b11c6dd5ecffe368ef9c2ec Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Otto=20Pfl=C3=BCger?= Date: Sun, 29 Mar 2026 09:27:47 +0200 Subject: [PATCH 06/47] mfd: sprd-sc27xx: Switch to devm_mfd_add_devices() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To allow instantiating subdevices such as the regulator and poweroff devices that do not have corresponding device tree nodes with a "compatible" property, use devm_mfd_add_devices() with MFD cells instead of devm_of_platform_populate(). Since different PMICs in the SC27xx series contain different components, use separate MFD cell tables for each PMIC model. Define cells for all components that have upstream drivers at this point. Signed-off-by: Otto Pflüger Link: https://patch.msgid.link/20260329-sc27xx-mfd-cells-v3-3-9158dee41f74@abscue.de Signed-off-by: Lee Jones --- drivers/mfd/sprd-sc27xx-spi.c | 62 ++++++++++++++++++++++++++++++----- 1 file changed, 53 insertions(+), 9 deletions(-) diff --git a/drivers/mfd/sprd-sc27xx-spi.c b/drivers/mfd/sprd-sc27xx-spi.c index d6b4350779e6..aa052f646623 100644 --- a/drivers/mfd/sprd-sc27xx-spi.c +++ b/drivers/mfd/sprd-sc27xx-spi.c @@ -14,6 +14,11 @@ #include #include +enum sprd_pmic_type { + PMIC_TYPE_SC2730 = 1, + PMIC_TYPE_SC2731, +}; + #define SPRD_PMIC_INT_MASK_STATUS 0x0 #define SPRD_PMIC_INT_RAW_STATUS 0x4 #define SPRD_PMIC_INT_EN 0x8 @@ -50,6 +55,29 @@ struct sprd_pmic_data { u32 charger_det; }; +static const struct mfd_cell sc2730_devices[] = { + MFD_CELL_OF("sc2730-adc", NULL, NULL, 0, 0, "sprd,sc2730-adc"), + MFD_CELL_OF("sc2730-bltc", NULL, NULL, 0, 0, "sprd,sc2730-bltc"), + MFD_CELL_OF("sc2730-efuse", NULL, NULL, 0, 0, "sprd,sc2730-efuse"), + MFD_CELL_OF("sc2730-eic", NULL, NULL, 0, 0, "sprd,sc2730-eic"), + MFD_CELL_OF("sc2730-fgu", NULL, NULL, 0, 0, "sprd,sc2730-fgu"), + MFD_CELL_OF("sc2730-rtc", NULL, NULL, 0, 0, "sprd,sc2730-rtc"), + MFD_CELL_OF("sc2730-vibrator", NULL, NULL, 0, 0, "sprd,sc2730-vibrator"), +}; + +static const struct mfd_cell sc2731_devices[] = { + MFD_CELL_OF("sc2731-adc", NULL, NULL, 0, 0, "sprd,sc2731-adc"), + MFD_CELL_OF("sc2731-bltc", NULL, NULL, 0, 0, "sprd,sc2731-bltc"), + MFD_CELL_OF("sc2731-charger", NULL, NULL, 0, 0, "sprd,sc2731-charger"), + MFD_CELL_OF("sc2731-efuse", NULL, NULL, 0, 0, "sprd,sc2731-efuse"), + MFD_CELL_OF("sc2731-eic", NULL, NULL, 0, 0, "sprd,sc2731-eic"), + MFD_CELL_OF("sc2731-fgu", NULL, NULL, 0, 0, "sprd,sc2731-fgu"), + MFD_CELL_NAME("sc2731-poweroff"), + MFD_CELL_NAME("sc2731-regulator"), + MFD_CELL_OF("sc2731-rtc", NULL, NULL, 0, 0, "sprd,sc2731-rtc"), + MFD_CELL_OF("sc2731-vibrator", NULL, NULL, 0, 0, "sprd,sc2731-vibrator"), +}; + /* * Since different PMICs of SC27xx series can have different interrupt * base address and irq number, we should save irq number and irq base @@ -152,12 +180,26 @@ static const struct regmap_config sprd_pmic_config = { static int sprd_pmic_probe(struct spi_device *spi) { struct sprd_pmic *ddata; + enum sprd_pmic_type pmic_type; const struct sprd_pmic_data *pdata; - int ret, i; + const struct mfd_cell *cells; + int ret, i, num_cells; - pdata = of_device_get_match_data(&spi->dev); - if (!pdata) { - dev_err(&spi->dev, "No matching driver data found\n"); + pmic_type = (uintptr_t)of_device_get_match_data(&spi->dev); + + switch (pmic_type) { + case PMIC_TYPE_SC2730: + pdata = &sc2730_data; + cells = sc2730_devices; + num_cells = ARRAY_SIZE(sc2730_devices); + break; + case PMIC_TYPE_SC2731: + pdata = &sc2731_data; + cells = sc2731_devices; + num_cells = ARRAY_SIZE(sc2731_devices); + break; + default: + dev_err(&spi->dev, "Invalid device ID\n"); return -EINVAL; } @@ -204,7 +246,9 @@ static int sprd_pmic_probe(struct spi_device *spi) return ret; } - ret = devm_of_platform_populate(&spi->dev); + ret = devm_mfd_add_devices(&spi->dev, PLATFORM_DEVID_AUTO, + cells, num_cells, NULL, 0, + regmap_irq_get_domain(ddata->irq_data)); if (ret) { dev_err(&spi->dev, "Failed to populate sub-devices %d\n", ret); return ret; @@ -241,15 +285,15 @@ static DEFINE_SIMPLE_DEV_PM_OPS(sprd_pmic_pm_ops, sprd_pmic_suspend, sprd_pmic_resume); static const struct of_device_id sprd_pmic_match[] = { - { .compatible = "sprd,sc2730", .data = &sc2730_data }, - { .compatible = "sprd,sc2731", .data = &sc2731_data }, + { .compatible = "sprd,sc2730", .data = (void *)PMIC_TYPE_SC2730 }, + { .compatible = "sprd,sc2731", .data = (void *)PMIC_TYPE_SC2731 }, {}, }; MODULE_DEVICE_TABLE(of, sprd_pmic_match); static const struct spi_device_id sprd_pmic_spi_ids[] = { - { .name = "sc2730", .driver_data = (unsigned long)&sc2730_data }, - { .name = "sc2731", .driver_data = (unsigned long)&sc2731_data }, + { .name = "sc2730", .driver_data = PMIC_TYPE_SC2730 }, + { .name = "sc2731", .driver_data = PMIC_TYPE_SC2731 }, {}, }; MODULE_DEVICE_TABLE(spi, sprd_pmic_spi_ids); From 6a2cb13761d90ef3fa960db189a2cc1bdf965ae1 Mon Sep 17 00:00:00 2001 From: Matti Vaittinen Date: Tue, 7 Apr 2026 16:26:48 +0300 Subject: [PATCH 07/47] mfd: bd72720: Drop BUCK11 ID The BD72720 header reserves an ID for BUCK11. While this does not (at the moment) cause problems I can see, it is misleading as the BD72720 contains only 10 BUCKs. Make the code clearer and drop the BUCK11 ID. Fixes: af25277b1ddc ("mfd: rohm-bd71828: Support ROHM BD72720") Signed-off-by: Matti Vaittinen Link: https://patch.msgid.link/812c3749a18d609d6f4698506bc516ec7183dfdd.1775565298.git.mazziesaccount@gmail.com Signed-off-by: Lee Jones --- include/linux/mfd/rohm-bd72720.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/linux/mfd/rohm-bd72720.h b/include/linux/mfd/rohm-bd72720.h index ae7343bcab06..d8ddbf232bb3 100644 --- a/include/linux/mfd/rohm-bd72720.h +++ b/include/linux/mfd/rohm-bd72720.h @@ -21,7 +21,6 @@ enum { BD72720_BUCK8, BD72720_BUCK9, BD72720_BUCK10, - BD72720_BUCK11, BD72720_LDO1, BD72720_LDO2, BD72720_LDO3, From 25c80f08e54ef5298eb68866f755f35b59a26d2b Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Mon, 3 Nov 2025 00:02:00 +0100 Subject: [PATCH 08/47] mfd: simple-mfd-i2c: Add a reboot cell for the SpacemiT P1 chip Add a "spacemit-p1-reboot" cell for the SpacemiT P1 chip. Signed-off-by: Aurelien Jarno Reviewed-by: Troy Mitchell Tested-by: Vincent Legoll # OrangePi-RV2 Link: https://patch.msgid.link/20251102230352.914421-3-aurelien@aurel32.net Signed-off-by: Lee Jones --- drivers/mfd/simple-mfd-i2c.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mfd/simple-mfd-i2c.c b/drivers/mfd/simple-mfd-i2c.c index 7315fad618e4..52c81b18750e 100644 --- a/drivers/mfd/simple-mfd-i2c.c +++ b/drivers/mfd/simple-mfd-i2c.c @@ -105,6 +105,7 @@ static const struct regmap_config spacemit_p1_regmap_config = { }; static const struct mfd_cell spacemit_p1_cells[] = { + { .name = "spacemit-p1-reboot", }, { .name = "spacemit-p1-regulator", }, { .name = "spacemit-p1-rtc", }, }; From 583003fe5e6e9ffc4a4edc6a1527890965d2c95c Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Tue, 31 Mar 2026 19:43:38 +0400 Subject: [PATCH 09/47] dt-bindings: mfd: ti,bq25703a: Expand to include BQ25792 TI BQ25792 is similar in operation to BQ25703A, but has a different register layout and different current/voltage capabilities. Expand the existing BQ25703A binding to include BQ25792, and move the voltage and current limits into per-variant conditional statements. Signed-off-by: Alexey Charkov Reviewed-by: Krzysztof Kozlowski Tested-by: Chris Morgan Link: https://patch.msgid.link/20260331-bq25792-v6-1-0278fba33eb9@flipper.net Signed-off-by: Lee Jones --- .../devicetree/bindings/mfd/ti,bq25703a.yaml | 73 ++++++++++++++++--- 1 file changed, 63 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/ti,bq25703a.yaml b/Documentation/devicetree/bindings/mfd/ti,bq25703a.yaml index ba14663c9266..cdce83f05804 100644 --- a/Documentation/devicetree/bindings/mfd/ti,bq25703a.yaml +++ b/Documentation/devicetree/bindings/mfd/ti,bq25703a.yaml @@ -4,17 +4,16 @@ $id: http://devicetree.org/schemas/mfd/ti,bq25703a.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: BQ25703A Charger Manager/Buck/Boost Converter +title: BQ257xx Charger Manager/Buck/Boost Converter maintainers: - Chris Morgan -allOf: - - $ref: /schemas/power/supply/power-supply.yaml# - properties: compatible: - const: ti,bq25703a + enum: + - ti,bq25703a + - ti,bq25792 reg: const: 0x6b @@ -25,7 +24,6 @@ properties: powering the device. minimum: 50000 maximum: 6400000 - default: 3250000 interrupts: maxItems: 1 @@ -57,11 +55,11 @@ properties: minimum: 0 maximum: 6350000 regulator-min-microvolt: - minimum: 4480000 - maximum: 20800000 + minimum: 2800000 + maximum: 22000000 regulator-max-microvolt: - minimum: 4480000 - maximum: 20800000 + minimum: 2800000 + maximum: 22000000 enable-gpios: description: The BQ25703 may require both a register write and a GPIO @@ -74,6 +72,61 @@ properties: - regulator-min-microvolt - regulator-max-microvolt +allOf: + - $ref: /schemas/power/supply/power-supply.yaml# + - if: + properties: + compatible: + const: ti,bq25703a + then: + properties: + input-current-limit-microamp: + minimum: 50000 + maximum: 6400000 + default: 3250000 + regulators: + properties: + vbus: + properties: + regulator-min-microamp: + minimum: 0 + maximum: 6350000 + regulator-max-microamp: + minimum: 0 + maximum: 6350000 + regulator-min-microvolt: + minimum: 4480000 + maximum: 20800000 + regulator-max-microvolt: + minimum: 4480000 + maximum: 20800000 + - if: + properties: + compatible: + const: ti,bq25792 + then: + properties: + input-current-limit-microamp: + minimum: 100000 + maximum: 3300000 + default: 3000000 + regulators: + properties: + vbus: + properties: + regulator-min-microamp: + minimum: 0 + maximum: 3320000 + regulator-max-microamp: + minimum: 0 + maximum: 3320000 + regulator-min-microvolt: + minimum: 2800000 + maximum: 22000000 + regulator-max-microvolt: + minimum: 2800000 + maximum: 22000000 + unevaluatedProperties: false required: From 9adbe53e32cdf3785cf71e27962282c628e97f5c Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Tue, 31 Mar 2026 19:43:46 +0400 Subject: [PATCH 10/47] mfd: bq257xx: Add BQ25792 support Add register definitions and a new 'type' enum to be passed via MFD private data to support the BQ25792, which is a newer variant of the BQ257xx family. BQ25792 shares similar logic of operation with the already supported BQ25703A but has a completely different register map and different electrical constraints. Signed-off-by: Alexey Charkov Tested-by: Chris Morgan Link: https://patch.msgid.link/20260331-bq25792-v6-9-0278fba33eb9@flipper.net Signed-off-by: Lee Jones --- drivers/mfd/bq257xx.c | 54 ++++- include/linux/mfd/bq257xx.h | 412 ++++++++++++++++++++++++++++++++++++ 2 files changed, 463 insertions(+), 3 deletions(-) diff --git a/drivers/mfd/bq257xx.c b/drivers/mfd/bq257xx.c index e9d49dac0a16..054342c60b73 100644 --- a/drivers/mfd/bq257xx.c +++ b/drivers/mfd/bq257xx.c @@ -39,6 +39,39 @@ static const struct regmap_config bq25703_regmap_config = { .val_format_endian = REGMAP_ENDIAN_LITTLE, }; +static const struct regmap_range bq25792_writeable_reg_ranges[] = { + regmap_reg_range(BQ25792_REG00_MIN_SYS_VOLTAGE, + BQ25792_REG18_NTC_CONTROL_1), + regmap_reg_range(BQ25792_REG28_CHARGER_MASK_0, + BQ25792_REG30_ADC_FUNCTION_DISABLE_1), +}; + +static const struct regmap_access_table bq25792_writeable_regs = { + .yes_ranges = bq25792_writeable_reg_ranges, + .n_yes_ranges = ARRAY_SIZE(bq25792_writeable_reg_ranges), +}; + +static const struct regmap_range bq25792_volatile_reg_ranges[] = { + regmap_reg_range(BQ25792_REG19_ICO_CURRENT_LIMIT, + BQ25792_REG27_FAULT_FLAG_1), + regmap_reg_range(BQ25792_REG31_IBUS_ADC, + BQ25792_REG47_DPDM_DRIVER), +}; + +static const struct regmap_access_table bq25792_volatile_regs = { + .yes_ranges = bq25792_volatile_reg_ranges, + .n_yes_ranges = ARRAY_SIZE(bq25792_volatile_reg_ranges), +}; + +static const struct regmap_config bq25792_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = BQ25792_REG48_PART_INFORMATION, + .cache_type = REGCACHE_MAPLE, + .wr_table = &bq25792_writeable_regs, + .volatile_table = &bq25792_volatile_regs, +}; + static const struct mfd_cell cells[] = { MFD_CELL_NAME("bq257xx-regulator"), MFD_CELL_NAME("bq257xx-charger"), @@ -46,6 +79,7 @@ static const struct mfd_cell cells[] = { static int bq257xx_probe(struct i2c_client *client) { + const struct regmap_config *rcfg; struct bq257xx_device *ddata; int ret; @@ -53,9 +87,21 @@ static int bq257xx_probe(struct i2c_client *client) if (!ddata) return -ENOMEM; + ddata->type = (uintptr_t)i2c_get_match_data(client); ddata->client = client; - ddata->regmap = devm_regmap_init_i2c(client, &bq25703_regmap_config); + switch (ddata->type) { + case BQ25703A: + rcfg = &bq25703_regmap_config; + break; + case BQ25792: + rcfg = &bq25792_regmap_config; + break; + default: + return dev_err_probe(&client->dev, -ENODEV, "Unsupported device type\n"); + } + + ddata->regmap = devm_regmap_init_i2c(client, rcfg); if (IS_ERR(ddata->regmap)) { return dev_err_probe(&client->dev, PTR_ERR(ddata->regmap), "Failed to allocate register map\n"); @@ -73,13 +119,15 @@ static int bq257xx_probe(struct i2c_client *client) } static const struct i2c_device_id bq257xx_i2c_ids[] = { - { "bq25703a" }, + { "bq25703a", BQ25703A }, + { "bq25792", BQ25792 }, {} }; MODULE_DEVICE_TABLE(i2c, bq257xx_i2c_ids); static const struct of_device_id bq257xx_of_match[] = { - { .compatible = "ti,bq25703a" }, + { .compatible = "ti,bq25703a", .data = (void *)BQ25703A }, + { .compatible = "ti,bq25792", .data = (void *)BQ25792 }, {} }; MODULE_DEVICE_TABLE(of, bq257xx_of_match); diff --git a/include/linux/mfd/bq257xx.h b/include/linux/mfd/bq257xx.h index 1d6ddc7fb09f..4ec72eb920f2 100644 --- a/include/linux/mfd/bq257xx.h +++ b/include/linux/mfd/bq257xx.h @@ -98,7 +98,419 @@ #define BQ25703_EN_OTG_MASK BIT(12) +#define BQ25792_REG00_MIN_SYS_VOLTAGE 0x00 +#define BQ25792_REG01_CHARGE_VOLTAGE_LIMIT 0x01 +#define BQ25792_REG03_CHARGE_CURRENT_LIMIT 0x03 +#define BQ25792_REG05_INPUT_VOLTAGE_LIMIT 0x05 +#define BQ25792_REG06_INPUT_CURRENT_LIMIT 0x06 +#define BQ25792_REG08_PRECHARGE_CONTROL 0x08 +#define BQ25792_REG09_TERMINATION_CONTROL 0x09 +#define BQ25792_REG0A_RECHARGE_CONTROL 0x0a +#define BQ25792_REG0B_VOTG_REGULATION 0x0b +#define BQ25792_REG0D_IOTG_REGULATION 0x0d +#define BQ25792_REG0E_TIMER_CONTROL 0x0e +#define BQ25792_REG0F_CHARGER_CONTROL_0 0x0f +#define BQ25792_REG10_CHARGER_CONTROL_1 0x10 +#define BQ25792_REG11_CHARGER_CONTROL_2 0x11 +#define BQ25792_REG12_CHARGER_CONTROL_3 0x12 +#define BQ25792_REG13_CHARGER_CONTROL_4 0x13 +#define BQ25792_REG14_CHARGER_CONTROL_5 0x14 +/* REG15 reserved */ +#define BQ25792_REG16_TEMPERATURE_CONTROL 0x16 +#define BQ25792_REG17_NTC_CONTROL_0 0x17 +#define BQ25792_REG18_NTC_CONTROL_1 0x18 +#define BQ25792_REG19_ICO_CURRENT_LIMIT 0x19 +#define BQ25792_REG1B_CHARGER_STATUS_0 0x1b +#define BQ25792_REG1C_CHARGER_STATUS_1 0x1c +#define BQ25792_REG1D_CHARGER_STATUS_2 0x1d +#define BQ25792_REG1E_CHARGER_STATUS_3 0x1e +#define BQ25792_REG1F_CHARGER_STATUS_4 0x1f +#define BQ25792_REG20_FAULT_STATUS_0 0x20 +#define BQ25792_REG21_FAULT_STATUS_1 0x21 +#define BQ25792_REG22_CHARGER_FLAG_0 0x22 +#define BQ25792_REG23_CHARGER_FLAG_1 0x23 +#define BQ25792_REG24_CHARGER_FLAG_2 0x24 +#define BQ25792_REG25_CHARGER_FLAG_3 0x25 +#define BQ25792_REG26_FAULT_FLAG_0 0x26 +#define BQ25792_REG27_FAULT_FLAG_1 0x27 +#define BQ25792_REG28_CHARGER_MASK_0 0x28 +#define BQ25792_REG29_CHARGER_MASK_1 0x29 +#define BQ25792_REG2A_CHARGER_MASK_2 0x2a +#define BQ25792_REG2B_CHARGER_MASK_3 0x2b +#define BQ25792_REG2C_FAULT_MASK_0 0x2c +#define BQ25792_REG2D_FAULT_MASK_1 0x2d +#define BQ25792_REG2E_ADC_CONTROL 0x2e +#define BQ25792_REG2F_ADC_FUNCTION_DISABLE_0 0x2f +#define BQ25792_REG30_ADC_FUNCTION_DISABLE_1 0x30 +#define BQ25792_REG31_IBUS_ADC 0x31 +#define BQ25792_REG33_IBAT_ADC 0x33 +#define BQ25792_REG35_VBUS_ADC 0x35 +#define BQ25792_REG37_VAC1_ADC 0x37 +#define BQ25792_REG39_VAC2_ADC 0x39 +#define BQ25792_REG3B_VBAT_ADC 0x3b +#define BQ25792_REG3D_VSYS_ADC 0x3d +#define BQ25792_REG3F_TS_ADC 0x3f +#define BQ25792_REG41_TDIE_ADC 0x41 +#define BQ25792_REG43_DP_ADC 0x43 +#define BQ25792_REG45_DM_ADC 0x45 +#define BQ25792_REG47_DPDM_DRIVER 0x47 +#define BQ25792_REG48_PART_INFORMATION 0x48 + +/* Minimal System Voltage */ +#define BQ25792_REG00_VSYSMIN_MASK GENMASK(5, 0) + +#define BQ25792_MINVSYS_MIN_UV 2500000 +#define BQ25792_MINVSYS_STEP_UV 250000 +#define BQ25792_MINVSYS_MAX_UV 16000000 + +/* Charge Voltage Limit */ +#define BQ25792_REG01_VREG_MASK GENMASK(10, 0) + +#define BQ25792_VBATREG_MIN_UV 3000000 +#define BQ25792_VBATREG_STEP_UV 10000 +#define BQ25792_VBATREG_MAX_UV 18800000 + +/* Charge Current Limit */ +#define BQ25792_REG03_ICHG_MASK GENMASK(8, 0) + +#define BQ25792_ICHG_MIN_UA 50000 +#define BQ25792_ICHG_STEP_UA 10000 +#define BQ25792_ICHG_MAX_UA 5000000 + +/* Input Voltage Limit */ +#define BQ25792_REG05_VINDPM_MASK GENMASK(7, 0) + +/* Input Current Limit */ +#define BQ25792_REG06_IINDPM_MASK GENMASK(8, 0) +#define BQ25792_IINDPM_DEFAULT_UA 3000000 +#define BQ25792_IINDPM_STEP_UA 10000 +#define BQ25792_IINDPM_MIN_UA 100000 +#define BQ25792_IINDPM_MAX_UA 3300000 + +/* Precharge Control */ +#define BQ25792_REG08_VBAT_LOWV_MASK GENMASK(7, 6) +#define BQ25792_REG08_IPRECHG_MASK GENMASK(5, 0) + +/* Termination Control */ +#define BQ25792_REG09_REG_RST BIT(6) +#define BQ25792_REG09_ITERM_MASK GENMASK(4, 0) + +/* Re-charge Control */ +#define BQ25792_REG0A_CELL_MASK GENMASK(7, 6) +#define BQ25792_REG0A_TRECHG_MASK GENMASK(5, 4) +#define BQ25792_REG0A_VRECHG_MASK GENMASK(3, 0) + +/* VOTG regulation */ +#define BQ25792_REG0B_VOTG_MASK GENMASK(10, 0) + +#define BQ25792_OTG_VOLT_MIN_UV 2800000 +#define BQ25792_OTG_VOLT_STEP_UV 10000 +#define BQ25792_OTG_VOLT_MAX_UV 22000000 +#define BQ25792_OTG_VOLT_NUM_VOLT ((BQ25792_OTG_VOLT_MAX_UV \ + - BQ25792_OTG_VOLT_MIN_UV) \ + / BQ25792_OTG_VOLT_STEP_UV + 1) + +/* IOTG regulation */ +#define BQ25792_REG0D_PRECHG_TMR BIT(7) +#define BQ25792_REG0D_IOTG_MASK GENMASK(6, 0) + +#define BQ25792_OTG_CUR_MIN_UA 120000 +#define BQ25792_OTG_CUR_STEP_UA 40000 +#define BQ25792_OTG_CUR_MAX_UA 3320000 + +/* Timer Control */ +#define BQ25792_REG0E_TOPOFF_TMR_MASK GENMASK(7, 6) +#define BQ25792_REG0E_EN_TRICHG_TMR BIT(5) +#define BQ25792_REG0E_EN_PRECHG_TMR BIT(4) +#define BQ25792_REG0E_EN_CHG_TMR BIT(3) +#define BQ25792_REG0E_CHG_TMR_MASK GENMASK(2, 1) +#define BQ25792_REG0E_TMR2X_EN BIT(0) + +/* Charger Control 0 */ +#define BQ25792_REG0F_EN_AUTO_IBATDIS BIT(7) +#define BQ25792_REG0F_FORCE_IBATDIS BIT(6) +#define BQ25792_REG0F_EN_CHG BIT(5) +#define BQ25792_REG0F_EN_ICO BIT(4) +#define BQ25792_REG0F_FORCE_ICO BIT(3) +#define BQ25792_REG0F_EN_HIZ BIT(2) +#define BQ25792_REG0F_EN_TERM BIT(1) +/* bit0 reserved */ + +/* Charger Control 1 */ +#define BQ25792_REG10_VAC_OVP_MASK GENMASK(5, 4) +#define BQ25792_REG10_WD_RST BIT(3) +#define BQ25792_REG10_WATCHDOG_MASK GENMASK(2, 0) + +/* Charger Control 2 */ +#define BQ25792_REG11_FORCE_INDET BIT(7) +#define BQ25792_REG11_AUTO_INDET_EN BIT(6) +#define BQ25792_REG11_EN_12V BIT(5) +#define BQ25792_REG11_EN_9V BIT(4) +#define BQ25792_REG11_HVDCP_EN BIT(3) +#define BQ25792_REG11_SDRV_CTRL_MASK GENMASK(2, 1) +#define BQ25792_REG11_SDRV_DLY BIT(0) + +/* Charger Control 3 */ +#define BQ25792_REG12_DIS_ACDRV BIT(7) +#define BQ25792_REG12_EN_OTG BIT(6) +#define BQ25792_REG12_PFM_OTG_DIS BIT(5) +#define BQ25792_REG12_PFM_FWD_DIS BIT(4) +#define BQ25792_REG12_WKUP_DLY BIT(3) +#define BQ25792_REG12_DIS_LDO BIT(2) +#define BQ25792_REG12_DIS_OTG_OOA BIT(1) +#define BQ25792_REG12_DIS_FWD_OOA BIT(0) + +/* Charger Control 4 */ +#define BQ25792_REG13_EN_ACDRV2 BIT(7) +#define BQ25792_REG13_EN_ACDRV1 BIT(6) +#define BQ25792_REG13_PWM_FREQ BIT(5) +#define BQ25792_REG13_DIS_STAT BIT(4) +#define BQ25792_REG13_DIS_VSYS_SHORT BIT(3) +#define BQ25792_REG13_DIS_VOTG_UVP BIT(2) +#define BQ25792_REG13_FORCE_VINDPM_DET BIT(1) +#define BQ25792_REG13_EN_IBUS_OCP BIT(0) + +/* Charger Control 5 */ +#define BQ25792_REG14_SFET_PRESENT BIT(7) +/* bit6 reserved */ +#define BQ25792_REG14_EN_IBAT BIT(5) +#define BQ25792_REG14_IBAT_REG_MASK GENMASK(4, 3) +#define BQ25792_REG14_EN_IINDPM BIT(2) +#define BQ25792_REG14_EN_EXTILIM BIT(1) +#define BQ25792_REG14_EN_BATOC BIT(0) + +#define BQ25792_IBAT_3A FIELD_PREP(BQ25792_REG14_IBAT_REG_MASK, 0) +#define BQ25792_IBAT_4A FIELD_PREP(BQ25792_REG14_IBAT_REG_MASK, 1) +#define BQ25792_IBAT_5A FIELD_PREP(BQ25792_REG14_IBAT_REG_MASK, 2) +#define BQ25792_IBAT_UNLIM FIELD_PREP(BQ25792_REG14_IBAT_REG_MASK, 3) + +/* Temperature Control */ +#define BQ25792_REG16_TREG_MASK GENMASK(7, 6) +#define BQ25792_REG16_TSHUT_MASK GENMASK(5, 4) +#define BQ25792_REG16_VBUS_PD_EN BIT(3) +#define BQ25792_REG16_VAC1_PD_EN BIT(2) +#define BQ25792_REG16_VAC2_PD_EN BIT(1) + +/* NTC Control 0 */ +#define BQ25792_REG17_JEITA_VSET_MASK GENMASK(7, 5) +#define BQ25792_REG17_JEITA_ISETH_MASK GENMASK(4, 3) +#define BQ25792_REG17_JEITA_ISETC_MASK GENMASK(2, 1) + +/* NTC Control 1 */ +#define BQ25792_REG18_TS_COOL_MASK GENMASK(7, 6) +#define BQ25792_REG18_TS_WARM_MASK GENMASK(5, 4) +#define BQ25792_REG18_BHOT_MASK GENMASK(3, 2) +#define BQ25792_REG18_BCOLD BIT(1) +#define BQ25792_REG18_TS_IGNORE BIT(0) + +/* ICO Current Limit */ +#define BQ25792_REG19_ICO_ILIM_MASK GENMASK(8, 0) + +/* Charger Status 0 */ +#define BQ25792_REG1B_IINDPM_STAT BIT(7) +#define BQ25792_REG1B_VINDPM_STAT BIT(6) +#define BQ25792_REG1B_WD_STAT BIT(5) +#define BQ25792_REG1B_POORSRC_STAT BIT(4) +#define BQ25792_REG1B_PG_STAT BIT(3) +#define BQ25792_REG1B_AC2_PRESENT_STAT BIT(2) +#define BQ25792_REG1B_AC1_PRESENT_STAT BIT(1) +#define BQ25792_REG1B_VBUS_PRESENT_STAT BIT(0) + +/* Charger Status 1 */ +#define BQ25792_REG1C_CHG_STAT_MASK GENMASK(7, 5) +#define BQ25792_REG1C_VBUS_STAT_MASK GENMASK(4, 1) +#define BQ25792_REG1C_BC12_DONE_STAT BIT(0) + +/* Charger Status 2 */ +#define BQ25792_REG1D_ICO_STAT_MASK GENMASK(7, 6) +#define BQ25792_REG1D_TREG_STAT BIT(2) +#define BQ25792_REG1D_DPDM_STAT BIT(1) +#define BQ25792_REG1D_VBAT_PRESENT_STAT BIT(0) + +/* Charger Status 3 */ +#define BQ25792_REG1E_ACRB2_STAT BIT(7) +#define BQ25792_REG1E_ACRB1_STAT BIT(6) +#define BQ25792_REG1E_ADC_DONE_STAT BIT(5) +#define BQ25792_REG1E_VSYS_STAT BIT(4) +#define BQ25792_REG1E_CHG_TMR_STAT BIT(3) +#define BQ25792_REG1E_TRICHG_TMR_STAT BIT(2) +#define BQ25792_REG1E_PRECHG_TMR_STAT BIT(1) + +/* Charger Status 4 */ +#define BQ25792_REG1F_VBATOTG_LOW_STAT BIT(4) +#define BQ25792_REG1F_TS_COLD_STAT BIT(3) +#define BQ25792_REG1F_TS_COOL_STAT BIT(2) +#define BQ25792_REG1F_TS_WARM_STAT BIT(1) +#define BQ25792_REG1F_TS_HOT_STAT BIT(0) + +/* FAULT Status 0 */ +#define BQ25792_REG20_IBAT_REG_STAT BIT(7) +#define BQ25792_REG20_VBUS_OVP_STAT BIT(6) +#define BQ25792_REG20_VBAT_OVP_STAT BIT(5) +#define BQ25792_REG20_IBUS_OCP_STAT BIT(4) +#define BQ25792_REG20_IBAT_OCP_STAT BIT(3) +#define BQ25792_REG20_CONV_OCP_STAT BIT(2) +#define BQ25792_REG20_VAC2_OVP_STAT BIT(1) +#define BQ25792_REG20_VAC1_OVP_STAT BIT(0) + +#define BQ25792_REG20_OVERVOLTAGE_MASK (BQ25792_REG20_VBAT_OVP_STAT | \ + BQ25792_REG20_VAC2_OVP_STAT | \ + BQ25792_REG20_VAC1_OVP_STAT) +#define BQ25792_REG20_OVERCURRENT_MASK (BQ25792_REG20_IBAT_OCP_STAT | \ + BQ25792_REG20_CONV_OCP_STAT) + +/* FAULT Status 1 */ +#define BQ25792_REG21_VSYS_SHORT_STAT BIT(7) +#define BQ25792_REG21_VSYS_OVP_STAT BIT(6) +#define BQ25792_REG21_OTG_OVP_STAT BIT(5) +#define BQ25792_REG21_OTG_UVP_STAT BIT(4) +#define BQ25792_REG21_TSHUT_STAT BIT(2) + + +/* Charger Flag 0 */ +#define BQ25792_REG22_IINDPM_FLAG BIT(7) +#define BQ25792_REG22_VINDPM_FLAG BIT(6) +#define BQ25792_REG22_WD_FLAG BIT(5) +#define BQ25792_REG22_POORSRC_FLAG BIT(4) +#define BQ25792_REG22_PG_FLAG BIT(3) +#define BQ25792_REG22_AC2_PRESENT_FLAG BIT(2) +#define BQ25792_REG22_AC1_PRESENT_FLAG BIT(1) +#define BQ25792_REG22_VBUS_PRESENT_FLAG BIT(0) + +/* Charger Flag 1 */ +#define BQ25792_REG23_CHG_FLAG BIT(7) +#define BQ25792_REG23_ICO_FLAG BIT(6) +#define BQ25792_REG23_VBUS_FLAG BIT(4) +#define BQ25792_REG23_TREG_FLAG BIT(2) +#define BQ25792_REG23_VBAT_PRESENT_FLAG BIT(1) +#define BQ25792_REG23_BC12_DONE_FLAG BIT(0) + +/* Charger Flag 2 */ +#define BQ25792_REG24_DPDM_DONE_FLAG BIT(6) +#define BQ25792_REG24_ADC_DONE_FLAG BIT(5) +#define BQ25792_REG24_VSYS_FLAG BIT(4) +#define BQ25792_REG24_CHG_TMR_FLAG BIT(3) +#define BQ25792_REG24_TRICHG_TMR_FLAG BIT(2) +#define BQ25792_REG24_PRECHG_TMR_FLAG BIT(1) +#define BQ25792_REG24_TOPOFF_TMR_FLAG BIT(0) + +/* Charger Flag 3 */ +#define BQ25792_REG25_VBATOTG_LOW_FLAG BIT(4) +#define BQ25792_REG25_TS_COLD_FLAG BIT(3) +#define BQ25792_REG25_TS_COOL_FLAG BIT(2) +#define BQ25792_REG25_TS_WARM_FLAG BIT(1) +#define BQ25792_REG25_TS_HOT_FLAG BIT(0) + +/* FAULT Flag 0 */ +#define BQ25792_REG26_IBAT_REG_FLAG BIT(7) +#define BQ25792_REG26_VBUS_OVP_FLAG BIT(6) +#define BQ25792_REG26_VBAT_OVP_FLAG BIT(5) +#define BQ25792_REG26_IBUS_OCP_FLAG BIT(4) +#define BQ25792_REG26_IBAT_OCP_FLAG BIT(3) +#define BQ25792_REG26_CONV_OCP_FLAG BIT(2) +#define BQ25792_REG26_VAC2_OVP_FLAG BIT(1) +#define BQ25792_REG26_VAC1_OVP_FLAG BIT(0) + +/* FAULT Flag 1 */ +#define BQ25792_REG27_VSYS_SHORT_FLAG BIT(7) +#define BQ25792_REG27_VSYS_OVP_FLAG BIT(6) +#define BQ25792_REG27_OTG_OVP_FLAG BIT(5) +#define BQ25792_REG27_OTG_UVP_FLAG BIT(4) +#define BQ25792_REG27_TSHUT_FLAG BIT(2) + +/* Charger Mask 0 */ +#define BQ25792_REG28_IINDPM_MASK BIT(7) +#define BQ25792_REG28_VINDPM_MASK BIT(6) +#define BQ25792_REG28_WD_MASK BIT(5) +#define BQ25792_REG28_POORSRC_MASK BIT(4) +#define BQ25792_REG28_PG_MASK BIT(3) +#define BQ25792_REG28_AC2_PRESENT_MASK BIT(2) +#define BQ25792_REG28_AC1_PRESENT_MASK BIT(1) +#define BQ25792_REG28_VBUS_PRESENT_MASK BIT(0) + +/* Charger Mask 1 */ +#define BQ25792_REG29_CHG_MASK BIT(7) +#define BQ25792_REG29_ICO_MASK BIT(6) +#define BQ25792_REG29_VBUS_MASK BIT(4) +#define BQ25792_REG29_TREG_MASK BIT(2) +#define BQ25792_REG29_VBAT_PRESENT_MASK BIT(1) +#define BQ25792_REG29_BC12_DONE_MASK BIT(0) + +/* Charger Mask 2 */ +#define BQ25792_REG2A_DPDM_DONE_MASK BIT(6) +#define BQ25792_REG2A_ADC_DONE_MASK BIT(5) +#define BQ25792_REG2A_VSYS_MASK BIT(4) +#define BQ25792_REG2A_CHG_TMR_MASK BIT(3) +#define BQ25792_REG2A_TRICHG_TMR_MASK BIT(2) +#define BQ25792_REG2A_PRECHG_TMR_MASK BIT(1) +#define BQ25792_REG2A_TOPOFF_TMR_MASK BIT(0) + +/* Charger Mask 3 */ +#define BQ25792_REG2B_VBATOTG_LOW_MASK BIT(4) +#define BQ25792_REG2B_TS_COLD_MASK BIT(3) +#define BQ25792_REG2B_TS_COOL_MASK BIT(2) +#define BQ25792_REG2B_TS_WARM_MASK BIT(1) +#define BQ25792_REG2B_TS_HOT_MASK BIT(0) + +/* FAULT Mask 0 */ +#define BQ25792_REG2C_IBAT_REG_MASK BIT(7) +#define BQ25792_REG2C_VBUS_OVP_MASK BIT(6) +#define BQ25792_REG2C_VBAT_OVP_MASK BIT(5) +#define BQ25792_REG2C_IBUS_OCP_MASK BIT(4) +#define BQ25792_REG2C_IBAT_OCP_MASK BIT(3) +#define BQ25792_REG2C_CONV_OCP_MASK BIT(2) +#define BQ25792_REG2C_VAC2_OVP_MASK BIT(1) +#define BQ25792_REG2C_VAC1_OVP_MASK BIT(0) + +/* FAULT Mask 1 */ +#define BQ25792_REG2D_VSYS_SHORT_MASK BIT(7) +#define BQ25792_REG2D_VSYS_OVP_MASK BIT(6) +#define BQ25792_REG2D_OTG_OVP_MASK BIT(5) +#define BQ25792_REG2D_OTG_UVP_MASK BIT(4) +#define BQ25792_REG2D_TSHUT_MASK BIT(2) + +/* ADC Control */ +#define BQ25792_REG2E_ADC_EN BIT(7) +#define BQ25792_REG2E_ADC_RATE BIT(6) +#define BQ25792_REG2E_ADC_SAMPLE_MASK GENMASK(5, 4) +#define BQ25792_REG2E_ADC_AVG BIT(3) +#define BQ25792_REG2E_ADC_AVG_INIT BIT(2) + +/* ADC Function Disable 0 */ +#define BQ25792_REG2F_IBUS_ADC_DIS BIT(7) +#define BQ25792_REG2F_IBAT_ADC_DIS BIT(6) +#define BQ25792_REG2F_VBUS_ADC_DIS BIT(5) +#define BQ25792_REG2F_VBAT_ADC_DIS BIT(4) +#define BQ25792_REG2F_VSYS_ADC_DIS BIT(3) +#define BQ25792_REG2F_TS_ADC_DIS BIT(2) +#define BQ25792_REG2F_TDIE_ADC_DIS BIT(1) + +/* ADC Function Disable 1 */ +#define BQ25792_REG30_DP_ADC_DIS BIT(7) +#define BQ25792_REG30_DM_ADC_DIS BIT(6) +#define BQ25792_REG30_VAC2_ADC_DIS BIT(5) +#define BQ25792_REG30_VAC1_ADC_DIS BIT(4) + +/* 0x31-0x45: ADC result registers (16-bit, RO): single full-width field */ + +#define BQ25792_ADCVSYSVBAT_STEP_UV 1000 +#define BQ25792_ADCIBAT_STEP_UA 1000 + +/* DPDM Driver */ +#define BQ25792_REG47_DPLUS_DAC_MASK GENMASK(7, 5) +#define BQ25792_REG47_DMINUS_DAC_MASK GENMASK(4, 2) + +/* Part Information */ +#define BQ25792_REG48_PN_MASK GENMASK(5, 3) +#define BQ25792_REG48_DEV_REV_MASK GENMASK(2, 0) + +enum bq257xx_type { + BQ25703A = 1, + BQ25792, +}; + struct bq257xx_device { struct i2c_client *client; struct regmap *regmap; + enum bq257xx_type type; }; From 8c2f0b42fc252e1bf1c7746447091a468e784ca1 Mon Sep 17 00:00:00 2001 From: Guangshuo Li Date: Thu, 16 Apr 2026 00:26:27 +0800 Subject: [PATCH 11/47] mfd: sm501: Fix reference leak on failed device registration When platform_device_register() fails in sm501_register_device(), the embedded struct device in pdev has already been initialized by device_initialize(), but the failure path only reports the error and returns without dropping the device reference for the current platform device: sm501_register_device() -> platform_device_register(pdev) -> device_initialize(&pdev->dev) -> setup_pdev_dma_masks(pdev) -> platform_device_add(pdev) This leads to a reference leak when platform_device_register() fails. Fix this by calling platform_device_put() before returning the error. The issue was identified by a static analysis tool I developed and confirmed by manual review. Fixes: b6d6454fdb66f ("[PATCH] mfd: SM501 core driver") Cc: stable@vger.kernel.org Signed-off-by: Guangshuo Li Link: https://patch.msgid.link/20260415162627.3558789-1-lgs201920130244@gmail.com Signed-off-by: Lee Jones --- drivers/mfd/sm501.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mfd/sm501.c b/drivers/mfd/sm501.c index 0ee6d8940e69..8276456b142f 100644 --- a/drivers/mfd/sm501.c +++ b/drivers/mfd/sm501.c @@ -704,9 +704,11 @@ static int sm501_register_device(struct sm501_devdata *sm, if (ret >= 0) { dev_dbg(sm->dev, "registered %s\n", pdev->name); list_add_tail(&smdev->list, &sm->devices); - } else + } else { dev_err(sm->dev, "error registering %s (%d)\n", pdev->name, ret); + platform_device_put(pdev); + } return ret; } From 17f95281839db78be227a6924750dda699f74706 Mon Sep 17 00:00:00 2001 From: Jameson Thies Date: Fri, 3 Apr 2026 22:22:53 +0000 Subject: [PATCH 12/47] mfd: cros_ec: Don't add cros_ec_ucsi if it is defined in OF or ACPI On devices with a UCSI PPM in the EC, check for cros_ec_ucsi to be defined in the OF device tree or an ACPI node. If it is defined by either OF or ACPI, it does not need to be added as a subdevice of cros_ec_dev mfd. cros_ec_ucsi will load from the OF or ACPI node. Signed-off-by: Jameson Thies Reviewed-by: Benson Leung Reviewed-by: Abhishek Pandit-Subedi Link: https://patch.msgid.link/20260403222253.1888991-2-jthies@google.com Signed-off-by: Lee Jones --- drivers/mfd/cros_ec_dev.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/mfd/cros_ec_dev.c b/drivers/mfd/cros_ec_dev.c index 39430dd44e30..70d64b7c6243 100644 --- a/drivers/mfd/cros_ec_dev.c +++ b/drivers/mfd/cros_ec_dev.c @@ -5,6 +5,7 @@ * Copyright (C) 2014 Google, Inc. */ +#include #include #include #include @@ -131,11 +132,6 @@ static const struct cros_feature_to_cells cros_subdevices[] = { .mfd_cells = cros_ec_rtc_cells, .num_cells = ARRAY_SIZE(cros_ec_rtc_cells), }, - { - .id = EC_FEATURE_UCSI_PPM, - .mfd_cells = cros_ec_ucsi_cells, - .num_cells = ARRAY_SIZE(cros_ec_ucsi_cells), - }, { .id = EC_FEATURE_HANG_DETECT, .mfd_cells = cros_ec_wdt_cells, @@ -264,6 +260,23 @@ static int ec_device_probe(struct platform_device *pdev) } } + /* + * FW nodes can load cros_ec_ucsi, but early PDC devices did not define + * the required nodes. On PDC systems without FW nodes for cros_ec_ucsi, + * the driver should be added as an mfd subdevice. + */ + if (cros_ec_check_features(ec, EC_FEATURE_USB_PD) && + cros_ec_check_features(ec, EC_FEATURE_UCSI_PPM) && + !acpi_dev_found("GOOG0021") && + !of_find_compatible_node(NULL, NULL, "google,cros-ec-ucsi")) { + retval = mfd_add_hotplug_devices(ec->dev, + cros_ec_ucsi_cells, + ARRAY_SIZE(cros_ec_ucsi_cells)); + + if (retval) + dev_warn(ec->dev, "failed to add cros_ec_ucsi: %d\n", retval); + } + /* * UCSI provides power supply information so we don't need to separately * load the cros_usbpd_charger driver. From 68d574451d20927b38db08369af6bacecf55205a Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 21 Apr 2026 18:29:03 +0100 Subject: [PATCH 13/47] dt-bindings: mfd: syscon: Document the LVDS_CMN syscon for the RZ/G3L The RZ/G3{E,L} SoCs have an LVDS Common (LVDS_CMN) region which is common to all LVDS channels. The RZ/G3L has single-link, but the RZ/G3E has both single and dual-link. Use the syscon interface to access these registers for scalability. Signed-off-by: Tommaso Merciai Signed-off-by: Biju Das Acked-by: Conor Dooley Link: https://patch.msgid.link/20260421172910.218497-2-biju.das.jz@bp.renesas.com Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index e22867088063..9c81010d5a74 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -221,6 +221,7 @@ properties: - nxp,s32g3-gpr - qcom,apq8064-mmss-sfpb - qcom,apq8064-sps-sic + - renesas,r9a08g046-lvds-cmn - rockchip,px30-qos - rockchip,rk3036-qos - rockchip,rk3066-qos From 39dd85d9246ecf880aeea165f594c81c50afaabf Mon Sep 17 00:00:00 2001 From: Ronald Claveau Date: Tue, 21 Apr 2026 13:49:18 +0200 Subject: [PATCH 14/47] dt-bindings: mfd: khadas: Add new compatible for Khadas VIM4 MCU The Khadas VIM4 MCU register is slightly different from previous boards' MCU. This board also features a switchable power source for its fan. Signed-off-by: Ronald Claveau Acked-by: Conor Dooley Link: https://patch.msgid.link/20260421-add-mcu-fan-khadas-vim4-v4-1-447114a28f2d@aliel.fr Signed-off-by: Lee Jones --- .../devicetree/bindings/mfd/khadas,mcu.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml b/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml index 084960fd5a1f..1f135618e3b6 100644 --- a/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml +++ b/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml @@ -18,6 +18,7 @@ properties: compatible: enum: - khadas,mcu # MCU revision is discoverable + - khadas,vim4-mcu # Different MCU variant, not discoverable "#cooling-cells": # Only needed for boards having FAN control feature const: 2 @@ -25,10 +26,27 @@ properties: reg: maxItems: 1 + fan-supply: + description: Phandle to the regulator that powers the fan. + $ref: /schemas/types.yaml#/definitions/phandle + required: - compatible - reg +allOf: + - if: + properties: + compatible: + contains: + const: khadas,vim4-mcu + then: + required: + - fan-supply + else: + properties: + fan-supply: false + additionalProperties: false examples: From 82f09182307f9a721b9bb87869cb6cf03ba36fb4 Mon Sep 17 00:00:00 2001 From: Shaunak Datar Date: Thu, 23 Apr 2026 17:02:37 +0530 Subject: [PATCH 15/47] dt-bindings: mfd: hisilicon,hi655x-pmic: Convert to DT schema Convert the Hisilicon Hi655x PMIC binding from the text format to DT schema to enable dtbs_check validation. The 'regulators' child node is added based on existing usage in arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts, which defines child regulator nodes not documented in the original .txt binding. The uppercase LDO names are retained to match existing DTS usage. Signed-off-by: Shaunak Datar Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260423113237.260652-1-shaunakkdatar@gmail.com Signed-off-by: Lee Jones --- .../bindings/mfd/hisilicon,hi655x-pmic.yaml | 80 +++++++++++++++++++ .../bindings/mfd/hisilicon,hi655x.txt | 33 -------- 2 files changed, 80 insertions(+), 33 deletions(-) create mode 100644 Documentation/devicetree/bindings/mfd/hisilicon,hi655x-pmic.yaml delete mode 100644 Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt diff --git a/Documentation/devicetree/bindings/mfd/hisilicon,hi655x-pmic.yaml b/Documentation/devicetree/bindings/mfd/hisilicon,hi655x-pmic.yaml new file mode 100644 index 000000000000..6f28f472e0f5 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/hisilicon,hi655x-pmic.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/hisilicon,hi655x-pmic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Hi655x Power Management Integrated Circuit + +maintainers: + - Chen Feng + - Daniel Lezcano + +description: + The hardware layout for access PMIC Hi655x from AP SoC Hi6220. + Between PMIC Hi655x and Hi6220, the physical signal channel is SSI. + We can use memory-mapped I/O to communicate. + +properties: + compatible: + const: hisilicon,hi655x-pmic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + pmic-gpios: + maxItems: 1 + description: The GPIO used by PMIC IRQ + + '#clock-cells': + const: 0 + + clock-output-names: + maxItems: 1 + + regulators: + type: object + additionalProperties: false + + patternProperties: + '^LDO(2|7|10|13|14|15|17|19|21|22)$': + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - pmic-gpios + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + + pmic: pmic@f8000000 { + compatible = "hisilicon,hi655x-pmic"; + reg = <0xf8000000 0x1000>; + #clock-cells = <0>; + interrupt-controller; + #interrupt-cells = <2>; + pmic-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + + regulators { + ldo2: LDO2 { + regulator-name = "LDO2_2V8"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3200000>; + regulator-enable-ramp-delay = <120>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt b/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt deleted file mode 100644 index 9630ac0e4b56..000000000000 --- a/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt +++ /dev/null @@ -1,33 +0,0 @@ -Hisilicon Hi655x Power Management Integrated Circuit (PMIC) - -The hardware layout for access PMIC Hi655x from AP SoC Hi6220. -Between PMIC Hi655x and Hi6220, the physical signal channel is SSI. -We can use memory-mapped I/O to communicate. - -+----------------+ +-------------+ -| | | | -| Hi6220 | SSI bus | Hi655x | -| |-------------| | -| |(REGMAP_MMIO)| | -+----------------+ +-------------+ - -Required properties: -- compatible: Should be "hisilicon,hi655x-pmic". -- reg: Base address of PMIC on Hi6220 SoC. -- interrupt-controller: Hi655x has internal IRQs (has own IRQ domain). -- pmic-gpios: The GPIO used by PMIC IRQ. -- #clock-cells: From common clock binding; shall be set to 0 - -Optional properties: -- clock-output-names: From common clock binding to override the - default output clock name - -Example: - pmic: pmic@f8000000 { - compatible = "hisilicon,hi655x-pmic"; - reg = <0x0 0xf8000000 0x0 0x1000>; - interrupt-controller; - #interrupt-cells = <2>; - pmic-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - #clock-cells = <0>; - } From 4dd72d0044aaf5febe731e811bcaa1bc73400b48 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 28 Apr 2026 15:52:16 +0200 Subject: [PATCH 16/47] mfd: MAINTAINERS: Remove Krzysztof from Samsung PMIC drivers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Due to lack of time I did not perform reviews of patches for Samsung PMIC drivers last year, at least not in timely manner. I still can perform limited testing of the code on hardware, but that does not warrant having "M" here. Maintainer should be responsive, so drop my name and shift these drivers maintenance to André Draszik (from previous reviewer role). Signed-off-by: Krzysztof Kozlowski Acked-by: André Draszik Link: https://patch.msgid.link/20260428135216.100135-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Lee Jones --- CREDITS | 1 + MAINTAINERS | 3 +-- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/CREDITS b/CREDITS index 17962bdd6dbd..1537f2f70582 100644 --- a/CREDITS +++ b/CREDITS @@ -2241,6 +2241,7 @@ S: Canada N: Krzysztof Kozlowski E: krzk@kernel.org D: NFC network subsystem and drivers maintainer +D: Samsung S2M/S5M Multifunction PMIC device drivers for Exynos platforms N: Christian Krafft D: PowerPC Cell support diff --git a/MAINTAINERS b/MAINTAINERS index 2fb1c75afd16..3c40021ad2db 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23712,8 +23712,7 @@ S: Maintained F: drivers/platform/x86/samsung-laptop.c SAMSUNG MULTIFUNCTION PMIC DEVICE DRIVERS -M: Krzysztof Kozlowski -R: André Draszik +M: André Draszik L: linux-kernel@vger.kernel.org L: linux-samsung-soc@vger.kernel.org S: Maintained From 6bc38f26ed07197b11a2b588edf1f43bfbc81d76 Mon Sep 17 00:00:00 2001 From: Matthew Bystrin Date: Wed, 29 Apr 2026 10:20:46 +0300 Subject: [PATCH 17/47] mfd: rsmu: Fix page register setup Fix writes to page register in 8A3400x family (Clock Matrix). All calls to rsmu_write_page_register() (both in i2c and spi) have resulted in early return, because all addresses in include/linux/mfd/idt8a340_reg.h are less than RSMU_CM_SCSR_BASE. There were 2 separate patch series which have to be merged in one time: mfd and ptp. The latter have been merged, the former[1] have not. Link: https://lore.kernel.org/netdev/LV3P220MB1202F8E2FCCFBA2519B4966EA0192@LV3P220MB1202.NAMP220.PROD.OUTLOOK.COM/ Fixes: 67d6c76fc815 ("mfd: rsmu: Support 32-bit address space") Signed-off-by: Matthew Bystrin Link: https://patch.msgid.link/20260429072047.1111427-2-dev.mbstr@gmail.com Signed-off-by: Lee Jones --- drivers/mfd/rsmu_i2c.c | 6 +----- drivers/mfd/rsmu_spi.c | 5 +---- 2 files changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/mfd/rsmu_i2c.c b/drivers/mfd/rsmu_i2c.c index cba64f107a2f..9e5fc8259eec 100644 --- a/drivers/mfd/rsmu_i2c.c +++ b/drivers/mfd/rsmu_i2c.c @@ -134,14 +134,10 @@ static int rsmu_i2c_write_device(struct rsmu_ddata *rsmu, u8 reg, u8 *buf, u8 by static int rsmu_write_page_register(struct rsmu_ddata *rsmu, u32 reg, rsmu_rw_device rsmu_write_device) { - u32 page = reg & RSMU_CM_PAGE_MASK; + u32 page = (reg | RSMU_CM_SCSR_BASE) & RSMU_CM_PAGE_MASK; u8 buf[4]; int err; - /* Do not modify offset register for none-scsr registers */ - if (reg < RSMU_CM_SCSR_BASE) - return 0; - /* Simply return if we are on the same page */ if (rsmu->page == page) return 0; diff --git a/drivers/mfd/rsmu_spi.c b/drivers/mfd/rsmu_spi.c index 39d9be1e141f..c931d8cea0a1 100644 --- a/drivers/mfd/rsmu_spi.c +++ b/drivers/mfd/rsmu_spi.c @@ -101,11 +101,8 @@ static int rsmu_write_page_register(struct rsmu_ddata *rsmu, u32 reg) switch (rsmu->type) { case RSMU_CM: - /* Do not modify page register for none-scsr registers */ - if (reg < RSMU_CM_SCSR_BASE) - return 0; page_reg = RSMU_CM_PAGE_ADDR; - page = reg & RSMU_PAGE_MASK; + page = (reg | RSMU_CM_SCSR_BASE) & RSMU_PAGE_MASK; buf[0] = (u8)(page & 0xFF); buf[1] = (u8)((page >> 8) & 0xFF); buf[2] = (u8)((page >> 16) & 0xFF); From d18fd55c780c2bae3d353024cab7f8746d3d9e91 Mon Sep 17 00:00:00 2001 From: Matthew Bystrin Date: Wed, 29 Apr 2026 10:20:47 +0300 Subject: [PATCH 18/47] mfd: rsmu: Add 8a34002 support Add compatible string, i2c_devcie_id and spi_devcie_id to support 8a34002. Signed-off-by: Matthew Bystrin Link: https://patch.msgid.link/20260429072047.1111427-3-dev.mbstr@gmail.com Signed-off-by: Lee Jones --- drivers/mfd/rsmu_i2c.c | 2 ++ drivers/mfd/rsmu_spi.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/mfd/rsmu_i2c.c b/drivers/mfd/rsmu_i2c.c index 9e5fc8259eec..c57795ed20f4 100644 --- a/drivers/mfd/rsmu_i2c.c +++ b/drivers/mfd/rsmu_i2c.c @@ -330,6 +330,7 @@ static void rsmu_i2c_remove(struct i2c_client *client) static const struct i2c_device_id rsmu_i2c_id[] = { { "8a34000", RSMU_CM }, { "8a34001", RSMU_CM }, + { "8a34002", RSMU_CM }, { "82p33810", RSMU_SABRE }, { "82p33811", RSMU_SABRE }, { "8v19n850", RSMU_SL }, @@ -341,6 +342,7 @@ MODULE_DEVICE_TABLE(i2c, rsmu_i2c_id); static const struct of_device_id rsmu_i2c_of_match[] = { { .compatible = "idt,8a34000", .data = (void *)RSMU_CM }, { .compatible = "idt,8a34001", .data = (void *)RSMU_CM }, + { .compatible = "idt,8a34002", .data = (void *)RSMU_CM }, { .compatible = "idt,82p33810", .data = (void *)RSMU_SABRE }, { .compatible = "idt,82p33811", .data = (void *)RSMU_SABRE }, { .compatible = "idt,8v19n850", .data = (void *)RSMU_SL }, diff --git a/drivers/mfd/rsmu_spi.c b/drivers/mfd/rsmu_spi.c index c931d8cea0a1..e07f21482439 100644 --- a/drivers/mfd/rsmu_spi.c +++ b/drivers/mfd/rsmu_spi.c @@ -241,6 +241,7 @@ static void rsmu_spi_remove(struct spi_device *client) static const struct spi_device_id rsmu_spi_id[] = { { "8a34000", RSMU_CM }, { "8a34001", RSMU_CM }, + { "8a34002", RSMU_CM }, { "82p33810", RSMU_SABRE }, { "82p33811", RSMU_SABRE }, {} @@ -250,6 +251,7 @@ MODULE_DEVICE_TABLE(spi, rsmu_spi_id); static const struct of_device_id rsmu_spi_of_match[] = { { .compatible = "idt,8a34000", .data = (void *)RSMU_CM }, { .compatible = "idt,8a34001", .data = (void *)RSMU_CM }, + { .compatible = "idt,8a34002", .data = (void *)RSMU_CM }, { .compatible = "idt,82p33810", .data = (void *)RSMU_SABRE }, { .compatible = "idt,82p33811", .data = (void *)RSMU_SABRE }, {} From ade13e2b7bbb1dcdfb98091236b5abf63f259d03 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= Date: Wed, 29 Apr 2026 19:06:51 +0200 Subject: [PATCH 19/47] mfd: Consistently define pci_device_ids using named initializers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The various struct pci_device_id arrays were initialized mostly by one of the PCI_DEVICE macros and then list expressions. The latter isn't easily readable if you're not into PCI. Using named initializers is more explicit and thus easier to parse. The secret plan is to make struct pci_device_id::driver_data an anonymous union (similar to https://lore.kernel.org/all/cover.1776579304.git.u.kleine-koenig@baylibre.com/) and that requires named initializers. But it's also a nice cleanup on its own. This change doesn't introduce changes to the compiled pci_device_id arrays. Tested on x86 and arm64. Signed-off-by: Uwe Kleine-König (The Capable Hub) Link: https://patch.msgid.link/20260429170652.4178050-2-u.kleine-koenig@baylibre.com Signed-off-by: Lee Jones --- drivers/mfd/intel-lpss-pci.c | 786 +++++++++++++++++------------------ drivers/mfd/lpc_ich.c | 476 ++++++++++----------- drivers/mfd/lpc_sch.c | 10 +- drivers/mfd/sm501.c | 4 +- 4 files changed, 638 insertions(+), 638 deletions(-) diff --git a/drivers/mfd/intel-lpss-pci.c b/drivers/mfd/intel-lpss-pci.c index a9452ac92fb2..f7c592dd7e87 100644 --- a/drivers/mfd/intel-lpss-pci.c +++ b/drivers/mfd/intel-lpss-pci.c @@ -247,431 +247,431 @@ static const struct intel_lpss_platform_info tgl_spi_info = { static const struct pci_device_id intel_lpss_pci_ids[] = { /* CML-LP */ - { PCI_VDEVICE(INTEL, 0x02a8), (kernel_ulong_t)&spt_uart_info }, - { PCI_VDEVICE(INTEL, 0x02a9), (kernel_ulong_t)&spt_uart_info }, - { PCI_VDEVICE(INTEL, 0x02aa), (kernel_ulong_t)&cnl_spi_info }, - { PCI_VDEVICE(INTEL, 0x02ab), (kernel_ulong_t)&cnl_spi_info }, - { PCI_VDEVICE(INTEL, 0x02c5), (kernel_ulong_t)&cnl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x02c6), (kernel_ulong_t)&cnl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x02c7), (kernel_ulong_t)&spt_uart_info }, - { PCI_VDEVICE(INTEL, 0x02e8), (kernel_ulong_t)&cnl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x02e9), (kernel_ulong_t)&cnl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x02ea), (kernel_ulong_t)&cnl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x02eb), (kernel_ulong_t)&cnl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x02fb), (kernel_ulong_t)&cnl_spi_info }, + { PCI_VDEVICE(INTEL, 0x02a8), .driver_data = (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0x02a9), .driver_data = (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0x02aa), .driver_data = (kernel_ulong_t)&cnl_spi_info }, + { PCI_VDEVICE(INTEL, 0x02ab), .driver_data = (kernel_ulong_t)&cnl_spi_info }, + { PCI_VDEVICE(INTEL, 0x02c5), .driver_data = (kernel_ulong_t)&cnl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x02c6), .driver_data = (kernel_ulong_t)&cnl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x02c7), .driver_data = (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0x02e8), .driver_data = (kernel_ulong_t)&cnl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x02e9), .driver_data = (kernel_ulong_t)&cnl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x02ea), .driver_data = (kernel_ulong_t)&cnl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x02eb), .driver_data = (kernel_ulong_t)&cnl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x02fb), .driver_data = (kernel_ulong_t)&cnl_spi_info }, /* CML-H */ - { PCI_VDEVICE(INTEL, 0x06a8), (kernel_ulong_t)&spt_uart_info }, - { PCI_VDEVICE(INTEL, 0x06a9), (kernel_ulong_t)&spt_uart_info }, - { PCI_VDEVICE(INTEL, 0x06aa), (kernel_ulong_t)&cnl_spi_info }, - { PCI_VDEVICE(INTEL, 0x06ab), (kernel_ulong_t)&cnl_spi_info }, - { PCI_VDEVICE(INTEL, 0x06c7), (kernel_ulong_t)&spt_uart_info }, - { PCI_VDEVICE(INTEL, 0x06e8), (kernel_ulong_t)&cnl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x06e9), (kernel_ulong_t)&cnl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x06ea), (kernel_ulong_t)&cnl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x06eb), (kernel_ulong_t)&cnl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x06fb), (kernel_ulong_t)&cnl_spi_info }, + { PCI_VDEVICE(INTEL, 0x06a8), .driver_data = (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0x06a9), .driver_data = (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0x06aa), .driver_data = (kernel_ulong_t)&cnl_spi_info }, + { PCI_VDEVICE(INTEL, 0x06ab), .driver_data = (kernel_ulong_t)&cnl_spi_info }, + { PCI_VDEVICE(INTEL, 0x06c7), .driver_data = (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0x06e8), .driver_data = (kernel_ulong_t)&cnl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x06e9), .driver_data = (kernel_ulong_t)&cnl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x06ea), .driver_data = (kernel_ulong_t)&cnl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x06eb), .driver_data = (kernel_ulong_t)&cnl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x06fb), .driver_data = (kernel_ulong_t)&cnl_spi_info }, /* BXT A-Step */ - { PCI_VDEVICE(INTEL, 0x0aac), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x0aae), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x0ab0), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x0ab2), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x0ab4), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x0ab6), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x0ab8), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x0aba), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x0abc), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x0abe), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x0ac0), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x0ac2), (kernel_ulong_t)&bxt_spi_info }, - { PCI_VDEVICE(INTEL, 0x0ac4), (kernel_ulong_t)&bxt_spi_info }, - { PCI_VDEVICE(INTEL, 0x0ac6), (kernel_ulong_t)&bxt_spi_info }, - { PCI_VDEVICE(INTEL, 0x0aee), (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x0aac), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x0aae), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x0ab0), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x0ab2), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x0ab4), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x0ab6), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x0ab8), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x0aba), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x0abc), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x0abe), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x0ac0), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x0ac2), .driver_data = (kernel_ulong_t)&bxt_spi_info }, + { PCI_VDEVICE(INTEL, 0x0ac4), .driver_data = (kernel_ulong_t)&bxt_spi_info }, + { PCI_VDEVICE(INTEL, 0x0ac6), .driver_data = (kernel_ulong_t)&bxt_spi_info }, + { PCI_VDEVICE(INTEL, 0x0aee), .driver_data = (kernel_ulong_t)&bxt_uart_info }, /* BXT B-Step */ - { PCI_VDEVICE(INTEL, 0x1aac), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x1aae), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x1ab0), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x1ab2), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x1ab4), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x1ab6), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x1ab8), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x1aba), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x1abc), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x1abe), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x1ac0), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x1ac2), (kernel_ulong_t)&bxt_spi_info }, - { PCI_VDEVICE(INTEL, 0x1ac4), (kernel_ulong_t)&bxt_spi_info }, - { PCI_VDEVICE(INTEL, 0x1ac6), (kernel_ulong_t)&bxt_spi_info }, - { PCI_VDEVICE(INTEL, 0x1aee), (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x1aac), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x1aae), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x1ab0), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x1ab2), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x1ab4), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x1ab6), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x1ab8), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x1aba), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x1abc), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x1abe), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x1ac0), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x1ac2), .driver_data = (kernel_ulong_t)&bxt_spi_info }, + { PCI_VDEVICE(INTEL, 0x1ac4), .driver_data = (kernel_ulong_t)&bxt_spi_info }, + { PCI_VDEVICE(INTEL, 0x1ac6), .driver_data = (kernel_ulong_t)&bxt_spi_info }, + { PCI_VDEVICE(INTEL, 0x1aee), .driver_data = (kernel_ulong_t)&bxt_uart_info }, /* EBG */ - { PCI_VDEVICE(INTEL, 0x1bad), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x1bae), (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x1bad), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x1bae), .driver_data = (kernel_ulong_t)&bxt_uart_info }, /* GLK */ - { PCI_VDEVICE(INTEL, 0x31ac), (kernel_ulong_t)&glk_i2c_info }, - { PCI_VDEVICE(INTEL, 0x31ae), (kernel_ulong_t)&glk_i2c_info }, - { PCI_VDEVICE(INTEL, 0x31b0), (kernel_ulong_t)&glk_i2c_info }, - { PCI_VDEVICE(INTEL, 0x31b2), (kernel_ulong_t)&glk_i2c_info }, - { PCI_VDEVICE(INTEL, 0x31b4), (kernel_ulong_t)&glk_i2c_info }, - { PCI_VDEVICE(INTEL, 0x31b6), (kernel_ulong_t)&glk_i2c_info }, - { PCI_VDEVICE(INTEL, 0x31b8), (kernel_ulong_t)&glk_i2c_info }, - { PCI_VDEVICE(INTEL, 0x31ba), (kernel_ulong_t)&glk_i2c_info }, - { PCI_VDEVICE(INTEL, 0x31bc), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x31be), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x31c0), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x31c2), (kernel_ulong_t)&bxt_spi_info }, - { PCI_VDEVICE(INTEL, 0x31c4), (kernel_ulong_t)&bxt_spi_info }, - { PCI_VDEVICE(INTEL, 0x31c6), (kernel_ulong_t)&bxt_spi_info }, - { PCI_VDEVICE(INTEL, 0x31ee), (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x31ac), .driver_data = (kernel_ulong_t)&glk_i2c_info }, + { PCI_VDEVICE(INTEL, 0x31ae), .driver_data = (kernel_ulong_t)&glk_i2c_info }, + { PCI_VDEVICE(INTEL, 0x31b0), .driver_data = (kernel_ulong_t)&glk_i2c_info }, + { PCI_VDEVICE(INTEL, 0x31b2), .driver_data = (kernel_ulong_t)&glk_i2c_info }, + { PCI_VDEVICE(INTEL, 0x31b4), .driver_data = (kernel_ulong_t)&glk_i2c_info }, + { PCI_VDEVICE(INTEL, 0x31b6), .driver_data = (kernel_ulong_t)&glk_i2c_info }, + { PCI_VDEVICE(INTEL, 0x31b8), .driver_data = (kernel_ulong_t)&glk_i2c_info }, + { PCI_VDEVICE(INTEL, 0x31ba), .driver_data = (kernel_ulong_t)&glk_i2c_info }, + { PCI_VDEVICE(INTEL, 0x31bc), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x31be), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x31c0), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x31c2), .driver_data = (kernel_ulong_t)&bxt_spi_info }, + { PCI_VDEVICE(INTEL, 0x31c4), .driver_data = (kernel_ulong_t)&bxt_spi_info }, + { PCI_VDEVICE(INTEL, 0x31c6), .driver_data = (kernel_ulong_t)&bxt_spi_info }, + { PCI_VDEVICE(INTEL, 0x31ee), .driver_data = (kernel_ulong_t)&bxt_uart_info }, /* ICL-LP */ - { PCI_VDEVICE(INTEL, 0x34a8), (kernel_ulong_t)&spt_uart_info }, - { PCI_VDEVICE(INTEL, 0x34a9), (kernel_ulong_t)&spt_uart_info }, - { PCI_VDEVICE(INTEL, 0x34aa), (kernel_ulong_t)&cnl_spi_info }, - { PCI_VDEVICE(INTEL, 0x34ab), (kernel_ulong_t)&cnl_spi_info }, - { PCI_VDEVICE(INTEL, 0x34c5), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x34c6), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x34c7), (kernel_ulong_t)&spt_uart_info }, - { PCI_VDEVICE(INTEL, 0x34e8), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x34e9), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x34ea), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x34eb), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x34fb), (kernel_ulong_t)&cnl_spi_info }, + { PCI_VDEVICE(INTEL, 0x34a8), .driver_data = (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0x34a9), .driver_data = (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0x34aa), .driver_data = (kernel_ulong_t)&cnl_spi_info }, + { PCI_VDEVICE(INTEL, 0x34ab), .driver_data = (kernel_ulong_t)&cnl_spi_info }, + { PCI_VDEVICE(INTEL, 0x34c5), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x34c6), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x34c7), .driver_data = (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0x34e8), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x34e9), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x34ea), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x34eb), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x34fb), .driver_data = (kernel_ulong_t)&cnl_spi_info }, /* ICL-N */ - { PCI_VDEVICE(INTEL, 0x38a8), (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0x38a8), .driver_data = (kernel_ulong_t)&spt_uart_info }, /* TGL-H */ - { PCI_VDEVICE(INTEL, 0x43a7), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x43a8), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x43a9), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x43aa), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0x43ab), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0x43ad), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x43ae), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x43d8), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x43da), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x43e8), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x43e9), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x43ea), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x43eb), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x43fb), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0x43fd), (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x43a7), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x43a8), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x43a9), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x43aa), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x43ab), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x43ad), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x43ae), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x43d8), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x43da), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x43e8), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x43e9), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x43ea), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x43eb), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x43fb), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x43fd), .driver_data = (kernel_ulong_t)&tgl_spi_info }, /* EHL */ - { PCI_VDEVICE(INTEL, 0x4b28), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x4b29), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x4b2a), (kernel_ulong_t)&bxt_spi_info }, - { PCI_VDEVICE(INTEL, 0x4b2b), (kernel_ulong_t)&bxt_spi_info }, - { PCI_VDEVICE(INTEL, 0x4b37), (kernel_ulong_t)&bxt_spi_info }, - { PCI_VDEVICE(INTEL, 0x4b44), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x4b45), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x4b4b), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x4b4c), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x4b4d), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x4b78), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x4b79), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x4b7a), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x4b7b), (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x4b28), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x4b29), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x4b2a), .driver_data = (kernel_ulong_t)&bxt_spi_info }, + { PCI_VDEVICE(INTEL, 0x4b2b), .driver_data = (kernel_ulong_t)&bxt_spi_info }, + { PCI_VDEVICE(INTEL, 0x4b37), .driver_data = (kernel_ulong_t)&bxt_spi_info }, + { PCI_VDEVICE(INTEL, 0x4b44), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x4b45), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x4b4b), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x4b4c), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x4b4d), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x4b78), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x4b79), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x4b7a), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x4b7b), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, /* WCL */ - { PCI_VDEVICE(INTEL, 0x4d25), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x4d26), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x4d27), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0x4d30), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0x4d46), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0x4d50), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x4d51), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x4d52), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x4d78), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x4d79), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x4d7a), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x4d7b), (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x4d25), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x4d26), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x4d27), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x4d30), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x4d46), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x4d50), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x4d51), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x4d52), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x4d78), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x4d79), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x4d7a), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x4d7b), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, /* JSL */ - { PCI_VDEVICE(INTEL, 0x4da8), (kernel_ulong_t)&spt_uart_info }, - { PCI_VDEVICE(INTEL, 0x4da9), (kernel_ulong_t)&spt_uart_info }, - { PCI_VDEVICE(INTEL, 0x4daa), (kernel_ulong_t)&cnl_spi_info }, - { PCI_VDEVICE(INTEL, 0x4dab), (kernel_ulong_t)&cnl_spi_info }, - { PCI_VDEVICE(INTEL, 0x4dc5), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x4dc6), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x4dc7), (kernel_ulong_t)&spt_uart_info }, - { PCI_VDEVICE(INTEL, 0x4de8), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x4de9), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x4dea), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x4deb), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x4dfb), (kernel_ulong_t)&cnl_spi_info }, + { PCI_VDEVICE(INTEL, 0x4da8), .driver_data = (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0x4da9), .driver_data = (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0x4daa), .driver_data = (kernel_ulong_t)&cnl_spi_info }, + { PCI_VDEVICE(INTEL, 0x4dab), .driver_data = (kernel_ulong_t)&cnl_spi_info }, + { PCI_VDEVICE(INTEL, 0x4dc5), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x4dc6), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x4dc7), .driver_data = (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0x4de8), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x4de9), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x4dea), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x4deb), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x4dfb), .driver_data = (kernel_ulong_t)&cnl_spi_info }, /* ADL-P */ - { PCI_VDEVICE(INTEL, 0x51a8), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x51a9), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x51aa), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0x51ab), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0x51c5), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x51c6), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x51c7), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x51d8), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x51d9), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x51e8), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x51e9), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x51ea), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x51eb), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x51fb), (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x51a8), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x51a9), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x51aa), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x51ab), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x51c5), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x51c6), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x51c7), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x51d8), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x51d9), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x51e8), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x51e9), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x51ea), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x51eb), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x51fb), .driver_data = (kernel_ulong_t)&tgl_spi_info }, /* ADL-M */ - { PCI_VDEVICE(INTEL, 0x54a8), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x54a9), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x54aa), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0x54ab), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0x54c5), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x54c6), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x54c7), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x54e8), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x54e9), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x54ea), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x54eb), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x54fb), (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x54a8), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x54a9), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x54aa), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x54ab), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x54c5), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x54c6), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x54c7), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x54e8), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x54e9), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x54ea), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x54eb), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x54fb), .driver_data = (kernel_ulong_t)&tgl_spi_info }, /* APL */ - { PCI_VDEVICE(INTEL, 0x5aac), (kernel_ulong_t)&apl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x5aae), (kernel_ulong_t)&apl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x5ab0), (kernel_ulong_t)&apl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x5ab2), (kernel_ulong_t)&apl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x5ab4), (kernel_ulong_t)&apl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x5ab6), (kernel_ulong_t)&apl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x5ab8), (kernel_ulong_t)&apl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x5aba), (kernel_ulong_t)&apl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x5abc), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x5abe), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x5ac0), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x5ac2), (kernel_ulong_t)&bxt_spi_info }, - { PCI_VDEVICE(INTEL, 0x5ac4), (kernel_ulong_t)&bxt_spi_info }, - { PCI_VDEVICE(INTEL, 0x5ac6), (kernel_ulong_t)&bxt_spi_info }, - { PCI_VDEVICE(INTEL, 0x5aee), (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x5aac), .driver_data = (kernel_ulong_t)&apl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x5aae), .driver_data = (kernel_ulong_t)&apl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x5ab0), .driver_data = (kernel_ulong_t)&apl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x5ab2), .driver_data = (kernel_ulong_t)&apl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x5ab4), .driver_data = (kernel_ulong_t)&apl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x5ab6), .driver_data = (kernel_ulong_t)&apl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x5ab8), .driver_data = (kernel_ulong_t)&apl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x5aba), .driver_data = (kernel_ulong_t)&apl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x5abc), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x5abe), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x5ac0), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x5ac2), .driver_data = (kernel_ulong_t)&bxt_spi_info }, + { PCI_VDEVICE(INTEL, 0x5ac4), .driver_data = (kernel_ulong_t)&bxt_spi_info }, + { PCI_VDEVICE(INTEL, 0x5ac6), .driver_data = (kernel_ulong_t)&bxt_spi_info }, + { PCI_VDEVICE(INTEL, 0x5aee), .driver_data = (kernel_ulong_t)&bxt_uart_info }, /* NVL-S */ - { PCI_VDEVICE(INTEL, 0x6e28), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x6e29), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x6e2a), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0x6e2b), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0x6e4c), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x6e4d), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x6e4e), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x6e4f), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x6e5c), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x6e5e), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0x6e7a), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x6e7b), (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x6e28), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x6e29), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x6e2a), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x6e2b), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x6e4c), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x6e4d), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x6e4e), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x6e4f), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x6e5c), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x6e5e), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x6e7a), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x6e7b), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, /* ARL-H */ - { PCI_VDEVICE(INTEL, 0x7725), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x7726), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x7727), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0x7730), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0x7746), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0x7750), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x7751), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x7752), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x7778), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x7779), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x777a), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x777b), (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x7725), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x7726), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x7727), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x7730), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x7746), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x7750), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x7751), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x7752), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x7778), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x7779), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x777a), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x777b), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, /* RPL-S */ - { PCI_VDEVICE(INTEL, 0x7a28), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x7a29), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x7a2a), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0x7a2b), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0x7a4c), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x7a4d), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x7a4e), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x7a4f), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x7a5c), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x7a79), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0x7a7b), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0x7a7c), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x7a7d), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x7a7e), (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x7a28), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x7a29), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x7a2a), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x7a2b), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x7a4c), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x7a4d), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x7a4e), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x7a4f), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x7a5c), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x7a79), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x7a7b), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x7a7c), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x7a7d), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x7a7e), .driver_data = (kernel_ulong_t)&bxt_uart_info }, /* ADL-S */ - { PCI_VDEVICE(INTEL, 0x7aa8), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x7aa9), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x7aaa), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0x7aab), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0x7acc), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x7acd), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x7ace), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x7acf), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x7adc), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x7af9), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0x7afb), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0x7afc), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x7afd), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x7afe), (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x7aa8), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x7aa9), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x7aaa), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x7aab), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x7acc), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x7acd), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x7ace), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x7acf), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x7adc), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x7af9), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x7afb), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x7afc), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x7afd), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x7afe), .driver_data = (kernel_ulong_t)&bxt_uart_info }, /* MTL-P */ - { PCI_VDEVICE(INTEL, 0x7e25), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x7e26), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x7e27), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0x7e30), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0x7e46), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0x7e50), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x7e51), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x7e52), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x7e78), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x7e79), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x7e7a), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x7e7b), (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x7e25), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x7e26), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x7e27), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x7e30), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x7e46), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x7e50), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x7e51), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x7e52), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x7e78), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x7e79), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x7e7a), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x7e7b), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, /* MTP-S */ - { PCI_VDEVICE(INTEL, 0x7f28), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x7f29), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x7f2a), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0x7f2b), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0x7f4c), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x7f4d), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x7f4e), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x7f4f), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x7f5c), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x7f5d), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x7f5e), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0x7f5f), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0x7f7a), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x7f7b), (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x7f28), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x7f29), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x7f2a), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x7f2b), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x7f4c), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x7f4d), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x7f4e), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x7f4f), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x7f5c), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x7f5d), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x7f5e), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x7f5f), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0x7f7a), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x7f7b), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, /* LKF */ - { PCI_VDEVICE(INTEL, 0x98a8), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x98a9), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x98aa), (kernel_ulong_t)&bxt_spi_info }, - { PCI_VDEVICE(INTEL, 0x98c5), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x98c6), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x98c7), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0x98e8), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x98e9), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x98ea), (kernel_ulong_t)&bxt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x98eb), (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x98a8), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x98a9), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x98aa), .driver_data = (kernel_ulong_t)&bxt_spi_info }, + { PCI_VDEVICE(INTEL, 0x98c5), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x98c6), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x98c7), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x98e8), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x98e9), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x98ea), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x98eb), .driver_data = (kernel_ulong_t)&bxt_i2c_info }, /* SPT-LP */ - { PCI_VDEVICE(INTEL, 0x9d27), (kernel_ulong_t)&spt_uart_info }, - { PCI_VDEVICE(INTEL, 0x9d28), (kernel_ulong_t)&spt_uart_info }, - { PCI_VDEVICE(INTEL, 0x9d29), (kernel_ulong_t)&spt_spi_info }, - { PCI_VDEVICE(INTEL, 0x9d2a), (kernel_ulong_t)&spt_spi_info }, - { PCI_VDEVICE(INTEL, 0x9d60), (kernel_ulong_t)&spt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x9d61), (kernel_ulong_t)&spt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x9d62), (kernel_ulong_t)&spt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x9d63), (kernel_ulong_t)&spt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x9d64), (kernel_ulong_t)&spt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x9d65), (kernel_ulong_t)&spt_i2c_info }, - { PCI_VDEVICE(INTEL, 0x9d66), (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0x9d27), .driver_data = (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0x9d28), .driver_data = (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0x9d29), .driver_data = (kernel_ulong_t)&spt_spi_info }, + { PCI_VDEVICE(INTEL, 0x9d2a), .driver_data = (kernel_ulong_t)&spt_spi_info }, + { PCI_VDEVICE(INTEL, 0x9d60), .driver_data = (kernel_ulong_t)&spt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x9d61), .driver_data = (kernel_ulong_t)&spt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x9d62), .driver_data = (kernel_ulong_t)&spt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x9d63), .driver_data = (kernel_ulong_t)&spt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x9d64), .driver_data = (kernel_ulong_t)&spt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x9d65), .driver_data = (kernel_ulong_t)&spt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x9d66), .driver_data = (kernel_ulong_t)&spt_uart_info }, /* CNL-LP */ - { PCI_VDEVICE(INTEL, 0x9da8), (kernel_ulong_t)&spt_uart_info }, - { PCI_VDEVICE(INTEL, 0x9da9), (kernel_ulong_t)&spt_uart_info }, - { PCI_VDEVICE(INTEL, 0x9daa), (kernel_ulong_t)&cnl_spi_info }, - { PCI_VDEVICE(INTEL, 0x9dab), (kernel_ulong_t)&cnl_spi_info }, - { PCI_VDEVICE(INTEL, 0x9dc5), (kernel_ulong_t)&cnl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x9dc6), (kernel_ulong_t)&cnl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x9dc7), (kernel_ulong_t)&spt_uart_info }, - { PCI_VDEVICE(INTEL, 0x9de8), (kernel_ulong_t)&cnl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x9de9), (kernel_ulong_t)&cnl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x9dea), (kernel_ulong_t)&cnl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x9deb), (kernel_ulong_t)&cnl_i2c_info }, - { PCI_VDEVICE(INTEL, 0x9dfb), (kernel_ulong_t)&cnl_spi_info }, + { PCI_VDEVICE(INTEL, 0x9da8), .driver_data = (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0x9da9), .driver_data = (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0x9daa), .driver_data = (kernel_ulong_t)&cnl_spi_info }, + { PCI_VDEVICE(INTEL, 0x9dab), .driver_data = (kernel_ulong_t)&cnl_spi_info }, + { PCI_VDEVICE(INTEL, 0x9dc5), .driver_data = (kernel_ulong_t)&cnl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x9dc6), .driver_data = (kernel_ulong_t)&cnl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x9dc7), .driver_data = (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0x9de8), .driver_data = (kernel_ulong_t)&cnl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x9de9), .driver_data = (kernel_ulong_t)&cnl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x9dea), .driver_data = (kernel_ulong_t)&cnl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x9deb), .driver_data = (kernel_ulong_t)&cnl_i2c_info }, + { PCI_VDEVICE(INTEL, 0x9dfb), .driver_data = (kernel_ulong_t)&cnl_spi_info }, /* TGL-LP */ - { PCI_VDEVICE(INTEL, 0xa0a8), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0xa0a9), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0xa0aa), (kernel_ulong_t)&cnl_spi_info }, - { PCI_VDEVICE(INTEL, 0xa0ab), (kernel_ulong_t)&cnl_spi_info }, - { PCI_VDEVICE(INTEL, 0xa0c5), (kernel_ulong_t)&spt_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa0c6), (kernel_ulong_t)&spt_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa0c7), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0xa0d8), (kernel_ulong_t)&spt_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa0d9), (kernel_ulong_t)&spt_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa0da), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0xa0db), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0xa0dc), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0xa0dd), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0xa0de), (kernel_ulong_t)&cnl_spi_info }, - { PCI_VDEVICE(INTEL, 0xa0df), (kernel_ulong_t)&cnl_spi_info }, - { PCI_VDEVICE(INTEL, 0xa0e8), (kernel_ulong_t)&spt_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa0e9), (kernel_ulong_t)&spt_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa0ea), (kernel_ulong_t)&spt_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa0eb), (kernel_ulong_t)&spt_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa0fb), (kernel_ulong_t)&cnl_spi_info }, - { PCI_VDEVICE(INTEL, 0xa0fd), (kernel_ulong_t)&cnl_spi_info }, - { PCI_VDEVICE(INTEL, 0xa0fe), (kernel_ulong_t)&cnl_spi_info }, + { PCI_VDEVICE(INTEL, 0xa0a8), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0xa0a9), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0xa0aa), .driver_data = (kernel_ulong_t)&cnl_spi_info }, + { PCI_VDEVICE(INTEL, 0xa0ab), .driver_data = (kernel_ulong_t)&cnl_spi_info }, + { PCI_VDEVICE(INTEL, 0xa0c5), .driver_data = (kernel_ulong_t)&spt_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa0c6), .driver_data = (kernel_ulong_t)&spt_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa0c7), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0xa0d8), .driver_data = (kernel_ulong_t)&spt_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa0d9), .driver_data = (kernel_ulong_t)&spt_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa0da), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0xa0db), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0xa0dc), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0xa0dd), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0xa0de), .driver_data = (kernel_ulong_t)&cnl_spi_info }, + { PCI_VDEVICE(INTEL, 0xa0df), .driver_data = (kernel_ulong_t)&cnl_spi_info }, + { PCI_VDEVICE(INTEL, 0xa0e8), .driver_data = (kernel_ulong_t)&spt_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa0e9), .driver_data = (kernel_ulong_t)&spt_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa0ea), .driver_data = (kernel_ulong_t)&spt_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa0eb), .driver_data = (kernel_ulong_t)&spt_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa0fb), .driver_data = (kernel_ulong_t)&cnl_spi_info }, + { PCI_VDEVICE(INTEL, 0xa0fd), .driver_data = (kernel_ulong_t)&cnl_spi_info }, + { PCI_VDEVICE(INTEL, 0xa0fe), .driver_data = (kernel_ulong_t)&cnl_spi_info }, /* SPT-H */ - { PCI_VDEVICE(INTEL, 0xa127), (kernel_ulong_t)&spt_uart_info }, - { PCI_VDEVICE(INTEL, 0xa128), (kernel_ulong_t)&spt_uart_info }, - { PCI_VDEVICE(INTEL, 0xa129), (kernel_ulong_t)&spt_spi_info }, - { PCI_VDEVICE(INTEL, 0xa12a), (kernel_ulong_t)&spt_spi_info }, - { PCI_VDEVICE(INTEL, 0xa160), (kernel_ulong_t)&spt_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa161), (kernel_ulong_t)&spt_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa162), (kernel_ulong_t)&spt_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa166), (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0xa127), .driver_data = (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0xa128), .driver_data = (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0xa129), .driver_data = (kernel_ulong_t)&spt_spi_info }, + { PCI_VDEVICE(INTEL, 0xa12a), .driver_data = (kernel_ulong_t)&spt_spi_info }, + { PCI_VDEVICE(INTEL, 0xa160), .driver_data = (kernel_ulong_t)&spt_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa161), .driver_data = (kernel_ulong_t)&spt_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa162), .driver_data = (kernel_ulong_t)&spt_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa166), .driver_data = (kernel_ulong_t)&spt_uart_info }, /* KBL-H */ - { PCI_VDEVICE(INTEL, 0xa2a7), (kernel_ulong_t)&spt_uart_info }, - { PCI_VDEVICE(INTEL, 0xa2a8), (kernel_ulong_t)&spt_uart_info }, - { PCI_VDEVICE(INTEL, 0xa2a9), (kernel_ulong_t)&spt_spi_info }, - { PCI_VDEVICE(INTEL, 0xa2aa), (kernel_ulong_t)&spt_spi_info }, - { PCI_VDEVICE(INTEL, 0xa2e0), (kernel_ulong_t)&spt_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa2e1), (kernel_ulong_t)&spt_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa2e2), (kernel_ulong_t)&spt_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa2e3), (kernel_ulong_t)&spt_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa2e6), (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0xa2a7), .driver_data = (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0xa2a8), .driver_data = (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0xa2a9), .driver_data = (kernel_ulong_t)&spt_spi_info }, + { PCI_VDEVICE(INTEL, 0xa2aa), .driver_data = (kernel_ulong_t)&spt_spi_info }, + { PCI_VDEVICE(INTEL, 0xa2e0), .driver_data = (kernel_ulong_t)&spt_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa2e1), .driver_data = (kernel_ulong_t)&spt_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa2e2), .driver_data = (kernel_ulong_t)&spt_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa2e3), .driver_data = (kernel_ulong_t)&spt_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa2e6), .driver_data = (kernel_ulong_t)&spt_uart_info }, /* CNL-H */ - { PCI_VDEVICE(INTEL, 0xa328), (kernel_ulong_t)&spt_uart_info }, - { PCI_VDEVICE(INTEL, 0xa329), (kernel_ulong_t)&spt_uart_info }, - { PCI_VDEVICE(INTEL, 0xa32a), (kernel_ulong_t)&cnl_spi_info }, - { PCI_VDEVICE(INTEL, 0xa32b), (kernel_ulong_t)&cnl_spi_info }, - { PCI_VDEVICE(INTEL, 0xa347), (kernel_ulong_t)&spt_uart_info }, - { PCI_VDEVICE(INTEL, 0xa368), (kernel_ulong_t)&cnl_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa369), (kernel_ulong_t)&cnl_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa36a), (kernel_ulong_t)&cnl_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa36b), (kernel_ulong_t)&cnl_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa37b), (kernel_ulong_t)&cnl_spi_info }, + { PCI_VDEVICE(INTEL, 0xa328), .driver_data = (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0xa329), .driver_data = (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0xa32a), .driver_data = (kernel_ulong_t)&cnl_spi_info }, + { PCI_VDEVICE(INTEL, 0xa32b), .driver_data = (kernel_ulong_t)&cnl_spi_info }, + { PCI_VDEVICE(INTEL, 0xa347), .driver_data = (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0xa368), .driver_data = (kernel_ulong_t)&cnl_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa369), .driver_data = (kernel_ulong_t)&cnl_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa36a), .driver_data = (kernel_ulong_t)&cnl_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa36b), .driver_data = (kernel_ulong_t)&cnl_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa37b), .driver_data = (kernel_ulong_t)&cnl_spi_info }, /* CML-V */ - { PCI_VDEVICE(INTEL, 0xa3a7), (kernel_ulong_t)&spt_uart_info }, - { PCI_VDEVICE(INTEL, 0xa3a8), (kernel_ulong_t)&spt_uart_info }, - { PCI_VDEVICE(INTEL, 0xa3a9), (kernel_ulong_t)&spt_spi_info }, - { PCI_VDEVICE(INTEL, 0xa3aa), (kernel_ulong_t)&spt_spi_info }, - { PCI_VDEVICE(INTEL, 0xa3e0), (kernel_ulong_t)&spt_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa3e1), (kernel_ulong_t)&spt_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa3e2), (kernel_ulong_t)&spt_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa3e3), (kernel_ulong_t)&spt_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa3e6), (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0xa3a7), .driver_data = (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0xa3a8), .driver_data = (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0xa3a9), .driver_data = (kernel_ulong_t)&spt_spi_info }, + { PCI_VDEVICE(INTEL, 0xa3aa), .driver_data = (kernel_ulong_t)&spt_spi_info }, + { PCI_VDEVICE(INTEL, 0xa3e0), .driver_data = (kernel_ulong_t)&spt_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa3e1), .driver_data = (kernel_ulong_t)&spt_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa3e2), .driver_data = (kernel_ulong_t)&spt_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa3e3), .driver_data = (kernel_ulong_t)&spt_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa3e6), .driver_data = (kernel_ulong_t)&spt_uart_info }, /* LNL-M */ - { PCI_VDEVICE(INTEL, 0xa825), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0xa826), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0xa827), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0xa830), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0xa846), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0xa850), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa851), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa852), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0xa878), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa879), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa87a), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa87b), (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa825), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0xa826), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0xa827), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0xa830), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0xa846), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0xa850), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa851), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa852), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0xa878), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa879), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa87a), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa87b), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, /* NVL-H */ - { PCI_VDEVICE(INTEL, 0xd325), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0xd326), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0xd327), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0xd330), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0xd347), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0xd350), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0xd351), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0xd352), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0xd378), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0xd379), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0xd37a), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0xd37b), (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0xd325), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0xd326), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0xd327), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0xd330), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0xd347), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0xd350), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0xd351), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0xd352), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0xd378), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0xd379), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0xd37a), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0xd37b), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, /* PTL-H */ - { PCI_VDEVICE(INTEL, 0xe325), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0xe326), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0xe327), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0xe330), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0xe346), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0xe350), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0xe351), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0xe352), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0xe378), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0xe379), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0xe37a), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0xe37b), (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0xe325), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0xe326), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0xe327), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0xe330), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0xe346), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0xe350), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0xe351), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0xe352), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0xe378), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0xe379), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0xe37a), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0xe37b), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, /* PTL-P */ - { PCI_VDEVICE(INTEL, 0xe425), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0xe426), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0xe427), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0xe430), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0xe446), (kernel_ulong_t)&tgl_spi_info }, - { PCI_VDEVICE(INTEL, 0xe450), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0xe451), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0xe452), (kernel_ulong_t)&bxt_uart_info }, - { PCI_VDEVICE(INTEL, 0xe478), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0xe479), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0xe47a), (kernel_ulong_t)&ehl_i2c_info }, - { PCI_VDEVICE(INTEL, 0xe47b), (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0xe425), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0xe426), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0xe427), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0xe430), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0xe446), .driver_data = (kernel_ulong_t)&tgl_spi_info }, + { PCI_VDEVICE(INTEL, 0xe450), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0xe451), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0xe452), .driver_data = (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0xe478), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0xe479), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0xe47a), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, + { PCI_VDEVICE(INTEL, 0xe47b), .driver_data = (kernel_ulong_t)&ehl_i2c_info }, { } }; MODULE_DEVICE_TABLE(pci, intel_lpss_pci_ids); diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c index 5a3d79f339dd..d2efcc92bb59 100644 --- a/drivers/mfd/lpc_ich.c +++ b/drivers/mfd/lpc_ich.c @@ -721,244 +721,244 @@ static struct lpc_ich_info lpc_chipset_info[] = { * functions that probably will be registered by other drivers. */ static const struct pci_device_id lpc_ich_ids[] = { - { PCI_VDEVICE(INTEL, 0x0f1c), LPC_BAYTRAIL}, - { PCI_VDEVICE(INTEL, 0x19dc), LPC_DNV}, - { PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT}, - { PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD}, - { PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM}, - { PCI_VDEVICE(INTEL, 0x1c44), LPC_CPT}, - { PCI_VDEVICE(INTEL, 0x1c45), LPC_CPT}, - { PCI_VDEVICE(INTEL, 0x1c46), LPC_CPT}, - { PCI_VDEVICE(INTEL, 0x1c47), LPC_CPT}, - { PCI_VDEVICE(INTEL, 0x1c48), LPC_CPT}, - { PCI_VDEVICE(INTEL, 0x1c49), LPC_CPT}, - { PCI_VDEVICE(INTEL, 0x1c4a), LPC_CPT}, - { PCI_VDEVICE(INTEL, 0x1c4b), LPC_CPT}, - { PCI_VDEVICE(INTEL, 0x1c4c), LPC_CPT}, - { PCI_VDEVICE(INTEL, 0x1c4d), LPC_CPT}, - { PCI_VDEVICE(INTEL, 0x1c4e), LPC_CPT}, - { PCI_VDEVICE(INTEL, 0x1c4f), LPC_CPT}, - { PCI_VDEVICE(INTEL, 0x1c50), LPC_CPT}, - { PCI_VDEVICE(INTEL, 0x1c51), LPC_CPT}, - { PCI_VDEVICE(INTEL, 0x1c52), LPC_CPT}, - { PCI_VDEVICE(INTEL, 0x1c53), LPC_CPT}, - { PCI_VDEVICE(INTEL, 0x1c54), LPC_CPT}, - { PCI_VDEVICE(INTEL, 0x1c55), LPC_CPT}, - { PCI_VDEVICE(INTEL, 0x1c56), LPC_CPT}, - { PCI_VDEVICE(INTEL, 0x1c57), LPC_CPT}, - { PCI_VDEVICE(INTEL, 0x1c58), LPC_CPT}, - { PCI_VDEVICE(INTEL, 0x1c59), LPC_CPT}, - { PCI_VDEVICE(INTEL, 0x1c5a), LPC_CPT}, - { PCI_VDEVICE(INTEL, 0x1c5b), LPC_CPT}, - { PCI_VDEVICE(INTEL, 0x1c5c), LPC_CPT}, - { PCI_VDEVICE(INTEL, 0x1c5d), LPC_CPT}, - { PCI_VDEVICE(INTEL, 0x1c5e), LPC_CPT}, - { PCI_VDEVICE(INTEL, 0x1c5f), LPC_CPT}, - { PCI_VDEVICE(INTEL, 0x1d40), LPC_PBG}, - { PCI_VDEVICE(INTEL, 0x1d41), LPC_PBG}, - { PCI_VDEVICE(INTEL, 0x1e40), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1e41), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1e42), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1e43), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1e44), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1e45), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1e46), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1e47), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1e48), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1e49), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1e4a), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1e4b), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1e4c), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1e4d), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1e4e), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1e4f), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1e50), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1e51), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1e52), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1e53), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1e54), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1e55), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1e56), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1e57), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1e58), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1e59), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1e5a), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1e5b), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1e5c), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1e5d), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1e5e), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1e5f), LPC_PPT}, - { PCI_VDEVICE(INTEL, 0x1f38), LPC_AVN}, - { PCI_VDEVICE(INTEL, 0x1f39), LPC_AVN}, - { PCI_VDEVICE(INTEL, 0x1f3a), LPC_AVN}, - { PCI_VDEVICE(INTEL, 0x1f3b), LPC_AVN}, - { PCI_VDEVICE(INTEL, 0x229c), LPC_BRASWELL}, - { PCI_VDEVICE(INTEL, 0x2310), LPC_DH89XXCC}, - { PCI_VDEVICE(INTEL, 0x2390), LPC_COLETO}, - { PCI_VDEVICE(INTEL, 0x2410), LPC_ICH}, - { PCI_VDEVICE(INTEL, 0x2420), LPC_ICH0}, - { PCI_VDEVICE(INTEL, 0x2440), LPC_ICH2}, - { PCI_VDEVICE(INTEL, 0x244c), LPC_ICH2M}, - { PCI_VDEVICE(INTEL, 0x2450), LPC_CICH}, - { PCI_VDEVICE(INTEL, 0x2480), LPC_ICH3}, - { PCI_VDEVICE(INTEL, 0x248c), LPC_ICH3M}, - { PCI_VDEVICE(INTEL, 0x24c0), LPC_ICH4}, - { PCI_VDEVICE(INTEL, 0x24cc), LPC_ICH4M}, - { PCI_VDEVICE(INTEL, 0x24d0), LPC_ICH5}, - { PCI_VDEVICE(INTEL, 0x25a1), LPC_6300ESB}, - { PCI_VDEVICE(INTEL, 0x2640), LPC_ICH6}, - { PCI_VDEVICE(INTEL, 0x2641), LPC_ICH6M}, - { PCI_VDEVICE(INTEL, 0x2642), LPC_ICH6W}, - { PCI_VDEVICE(INTEL, 0x2670), LPC_631XESB}, - { PCI_VDEVICE(INTEL, 0x2671), LPC_631XESB}, - { PCI_VDEVICE(INTEL, 0x2672), LPC_631XESB}, - { PCI_VDEVICE(INTEL, 0x2673), LPC_631XESB}, - { PCI_VDEVICE(INTEL, 0x2674), LPC_631XESB}, - { PCI_VDEVICE(INTEL, 0x2675), LPC_631XESB}, - { PCI_VDEVICE(INTEL, 0x2676), LPC_631XESB}, - { PCI_VDEVICE(INTEL, 0x2677), LPC_631XESB}, - { PCI_VDEVICE(INTEL, 0x2678), LPC_631XESB}, - { PCI_VDEVICE(INTEL, 0x2679), LPC_631XESB}, - { PCI_VDEVICE(INTEL, 0x267a), LPC_631XESB}, - { PCI_VDEVICE(INTEL, 0x267b), LPC_631XESB}, - { PCI_VDEVICE(INTEL, 0x267c), LPC_631XESB}, - { PCI_VDEVICE(INTEL, 0x267d), LPC_631XESB}, - { PCI_VDEVICE(INTEL, 0x267e), LPC_631XESB}, - { PCI_VDEVICE(INTEL, 0x267f), LPC_631XESB}, - { PCI_VDEVICE(INTEL, 0x27b0), LPC_ICH7DH}, - { PCI_VDEVICE(INTEL, 0x27b8), LPC_ICH7}, - { PCI_VDEVICE(INTEL, 0x27b9), LPC_ICH7M}, - { PCI_VDEVICE(INTEL, 0x27bc), LPC_NM10}, - { PCI_VDEVICE(INTEL, 0x27bd), LPC_ICH7MDH}, - { PCI_VDEVICE(INTEL, 0x2810), LPC_ICH8}, - { PCI_VDEVICE(INTEL, 0x2811), LPC_ICH8ME}, - { PCI_VDEVICE(INTEL, 0x2812), LPC_ICH8DH}, - { PCI_VDEVICE(INTEL, 0x2814), LPC_ICH8DO}, - { PCI_VDEVICE(INTEL, 0x2815), LPC_ICH8M}, - { PCI_VDEVICE(INTEL, 0x2912), LPC_ICH9DH}, - { PCI_VDEVICE(INTEL, 0x2914), LPC_ICH9DO}, - { PCI_VDEVICE(INTEL, 0x2916), LPC_ICH9R}, - { PCI_VDEVICE(INTEL, 0x2917), LPC_ICH9ME}, - { PCI_VDEVICE(INTEL, 0x2918), LPC_ICH9}, - { PCI_VDEVICE(INTEL, 0x2919), LPC_ICH9M}, - { PCI_VDEVICE(INTEL, 0x2b9c), LPC_COUGARMOUNTAIN}, - { PCI_VDEVICE(INTEL, 0x3197), LPC_GLK}, - { PCI_VDEVICE(INTEL, 0x31e8), LPC_GLK}, - { PCI_VDEVICE(INTEL, 0x3a14), LPC_ICH10DO}, - { PCI_VDEVICE(INTEL, 0x3a16), LPC_ICH10R}, - { PCI_VDEVICE(INTEL, 0x3a18), LPC_ICH10}, - { PCI_VDEVICE(INTEL, 0x3a1a), LPC_ICH10D}, - { PCI_VDEVICE(INTEL, 0x3b00), LPC_PCH}, - { PCI_VDEVICE(INTEL, 0x3b01), LPC_PCHM}, - { PCI_VDEVICE(INTEL, 0x3b02), LPC_P55}, - { PCI_VDEVICE(INTEL, 0x3b03), LPC_PM55}, - { PCI_VDEVICE(INTEL, 0x3b06), LPC_H55}, - { PCI_VDEVICE(INTEL, 0x3b07), LPC_QM57}, - { PCI_VDEVICE(INTEL, 0x3b08), LPC_H57}, - { PCI_VDEVICE(INTEL, 0x3b09), LPC_HM55}, - { PCI_VDEVICE(INTEL, 0x3b0a), LPC_Q57}, - { PCI_VDEVICE(INTEL, 0x3b0b), LPC_HM57}, - { PCI_VDEVICE(INTEL, 0x3b0d), LPC_PCHMSFF}, - { PCI_VDEVICE(INTEL, 0x3b0f), LPC_QS57}, - { PCI_VDEVICE(INTEL, 0x3b12), LPC_3400}, - { PCI_VDEVICE(INTEL, 0x3b14), LPC_3420}, - { PCI_VDEVICE(INTEL, 0x3b16), LPC_3450}, - { PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579}, - { PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL}, - { PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8c43), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8c44), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8c45), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8c46), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8c47), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8c48), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8c49), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8c4a), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8c4b), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8c4c), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8c4d), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8c4e), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8c4f), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8c50), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8c51), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8c52), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8c53), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8c54), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8c55), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8c56), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8c57), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8c58), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8c59), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8c5a), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8c5b), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8c5c), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8c5d), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8c5e), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8c5f), LPC_LPT}, - { PCI_VDEVICE(INTEL, 0x8cc1), LPC_9S}, - { PCI_VDEVICE(INTEL, 0x8cc2), LPC_9S}, - { PCI_VDEVICE(INTEL, 0x8cc3), LPC_9S}, - { PCI_VDEVICE(INTEL, 0x8cc4), LPC_9S}, - { PCI_VDEVICE(INTEL, 0x8cc6), LPC_9S}, - { PCI_VDEVICE(INTEL, 0x8d40), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x8d41), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x8d42), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x8d43), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x8d44), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x8d45), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x8d46), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x8d47), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x8d48), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x8d49), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x8d4a), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x8d4b), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x8d4c), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x8d4d), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x8d4e), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x8d4f), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x8d50), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x8d51), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x8d52), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x8d53), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x8d54), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x8d55), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x8d56), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x8d57), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x8d58), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x8d59), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x8d5a), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x8d5b), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x8d5c), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x8d5d), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x8d5e), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x8d5f), LPC_WBG}, - { PCI_VDEVICE(INTEL, 0x9c40), LPC_LPT_LP}, - { PCI_VDEVICE(INTEL, 0x9c41), LPC_LPT_LP}, - { PCI_VDEVICE(INTEL, 0x9c42), LPC_LPT_LP}, - { PCI_VDEVICE(INTEL, 0x9c43), LPC_LPT_LP}, - { PCI_VDEVICE(INTEL, 0x9c44), LPC_LPT_LP}, - { PCI_VDEVICE(INTEL, 0x9c45), LPC_LPT_LP}, - { PCI_VDEVICE(INTEL, 0x9c46), LPC_LPT_LP}, - { PCI_VDEVICE(INTEL, 0x9c47), LPC_LPT_LP}, - { PCI_VDEVICE(INTEL, 0x9cc1), LPC_WPT_LP}, - { PCI_VDEVICE(INTEL, 0x9cc2), LPC_WPT_LP}, - { PCI_VDEVICE(INTEL, 0x9cc3), LPC_WPT_LP}, - { PCI_VDEVICE(INTEL, 0x9cc5), LPC_WPT_LP}, - { PCI_VDEVICE(INTEL, 0x9cc6), LPC_WPT_LP}, - { PCI_VDEVICE(INTEL, 0x9cc7), LPC_WPT_LP}, - { PCI_VDEVICE(INTEL, 0x9cc9), LPC_WPT_LP}, - { PCI_VDEVICE(INTEL, 0xa1c1), LPC_LEWISBURG}, - { PCI_VDEVICE(INTEL, 0xa1c2), LPC_LEWISBURG}, - { PCI_VDEVICE(INTEL, 0xa1c3), LPC_LEWISBURG}, - { PCI_VDEVICE(INTEL, 0xa1c4), LPC_LEWISBURG}, - { PCI_VDEVICE(INTEL, 0xa1c5), LPC_LEWISBURG}, - { PCI_VDEVICE(INTEL, 0xa1c6), LPC_LEWISBURG}, - { PCI_VDEVICE(INTEL, 0xa1c7), LPC_LEWISBURG}, - { PCI_VDEVICE(INTEL, 0xa242), LPC_LEWISBURG}, - { PCI_VDEVICE(INTEL, 0xa243), LPC_LEWISBURG}, - { 0, }, /* End of list */ + { PCI_VDEVICE(INTEL, 0x0f1c), .driver_data = LPC_BAYTRAIL }, + { PCI_VDEVICE(INTEL, 0x19dc), .driver_data = LPC_DNV }, + { PCI_VDEVICE(INTEL, 0x1c41), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c42), .driver_data = LPC_CPTD }, + { PCI_VDEVICE(INTEL, 0x1c43), .driver_data = LPC_CPTM }, + { PCI_VDEVICE(INTEL, 0x1c44), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c45), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c46), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c47), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c48), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c49), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c4a), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c4b), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c4c), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c4d), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c4e), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c4f), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c50), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c51), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c52), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c53), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c54), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c55), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c56), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c57), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c58), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c59), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c5a), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c5b), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c5c), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c5d), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c5e), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c5f), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1d40), .driver_data = LPC_PBG }, + { PCI_VDEVICE(INTEL, 0x1d41), .driver_data = LPC_PBG }, + { PCI_VDEVICE(INTEL, 0x1e40), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e41), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e42), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e43), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e44), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e45), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e46), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e47), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e48), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e49), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e4a), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e4b), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e4c), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e4d), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e4e), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e4f), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e50), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e51), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e52), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e53), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e54), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e55), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e56), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e57), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e58), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e59), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e5a), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e5b), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e5c), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e5d), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e5e), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e5f), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1f38), .driver_data = LPC_AVN }, + { PCI_VDEVICE(INTEL, 0x1f39), .driver_data = LPC_AVN }, + { PCI_VDEVICE(INTEL, 0x1f3a), .driver_data = LPC_AVN }, + { PCI_VDEVICE(INTEL, 0x1f3b), .driver_data = LPC_AVN }, + { PCI_VDEVICE(INTEL, 0x229c), .driver_data = LPC_BRASWELL }, + { PCI_VDEVICE(INTEL, 0x2310), .driver_data = LPC_DH89XXCC }, + { PCI_VDEVICE(INTEL, 0x2390), .driver_data = LPC_COLETO }, + { PCI_VDEVICE(INTEL, 0x2410), .driver_data = LPC_ICH }, + { PCI_VDEVICE(INTEL, 0x2420), .driver_data = LPC_ICH0 }, + { PCI_VDEVICE(INTEL, 0x2440), .driver_data = LPC_ICH2 }, + { PCI_VDEVICE(INTEL, 0x244c), .driver_data = LPC_ICH2M }, + { PCI_VDEVICE(INTEL, 0x2450), .driver_data = LPC_CICH }, + { PCI_VDEVICE(INTEL, 0x2480), .driver_data = LPC_ICH3 }, + { PCI_VDEVICE(INTEL, 0x248c), .driver_data = LPC_ICH3M }, + { PCI_VDEVICE(INTEL, 0x24c0), .driver_data = LPC_ICH4 }, + { PCI_VDEVICE(INTEL, 0x24cc), .driver_data = LPC_ICH4M }, + { PCI_VDEVICE(INTEL, 0x24d0), .driver_data = LPC_ICH5 }, + { PCI_VDEVICE(INTEL, 0x25a1), .driver_data = LPC_6300ESB }, + { PCI_VDEVICE(INTEL, 0x2640), .driver_data = LPC_ICH6 }, + { PCI_VDEVICE(INTEL, 0x2641), .driver_data = LPC_ICH6M }, + { PCI_VDEVICE(INTEL, 0x2642), .driver_data = LPC_ICH6W }, + { PCI_VDEVICE(INTEL, 0x2670), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x2671), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x2672), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x2673), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x2674), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x2675), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x2676), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x2677), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x2678), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x2679), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x267a), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x267b), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x267c), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x267d), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x267e), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x267f), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x27b0), .driver_data = LPC_ICH7DH }, + { PCI_VDEVICE(INTEL, 0x27b8), .driver_data = LPC_ICH7 }, + { PCI_VDEVICE(INTEL, 0x27b9), .driver_data = LPC_ICH7M }, + { PCI_VDEVICE(INTEL, 0x27bc), .driver_data = LPC_NM10 }, + { PCI_VDEVICE(INTEL, 0x27bd), .driver_data = LPC_ICH7MDH }, + { PCI_VDEVICE(INTEL, 0x2810), .driver_data = LPC_ICH8 }, + { PCI_VDEVICE(INTEL, 0x2811), .driver_data = LPC_ICH8ME }, + { PCI_VDEVICE(INTEL, 0x2812), .driver_data = LPC_ICH8DH }, + { PCI_VDEVICE(INTEL, 0x2814), .driver_data = LPC_ICH8DO }, + { PCI_VDEVICE(INTEL, 0x2815), .driver_data = LPC_ICH8M }, + { PCI_VDEVICE(INTEL, 0x2912), .driver_data = LPC_ICH9DH }, + { PCI_VDEVICE(INTEL, 0x2914), .driver_data = LPC_ICH9DO }, + { PCI_VDEVICE(INTEL, 0x2916), .driver_data = LPC_ICH9R }, + { PCI_VDEVICE(INTEL, 0x2917), .driver_data = LPC_ICH9ME }, + { PCI_VDEVICE(INTEL, 0x2918), .driver_data = LPC_ICH9 }, + { PCI_VDEVICE(INTEL, 0x2919), .driver_data = LPC_ICH9M }, + { PCI_VDEVICE(INTEL, 0x2b9c), .driver_data = LPC_COUGARMOUNTAIN }, + { PCI_VDEVICE(INTEL, 0x3197), .driver_data = LPC_GLK }, + { PCI_VDEVICE(INTEL, 0x31e8), .driver_data = LPC_GLK }, + { PCI_VDEVICE(INTEL, 0x3a14), .driver_data = LPC_ICH10DO }, + { PCI_VDEVICE(INTEL, 0x3a16), .driver_data = LPC_ICH10R }, + { PCI_VDEVICE(INTEL, 0x3a18), .driver_data = LPC_ICH10 }, + { PCI_VDEVICE(INTEL, 0x3a1a), .driver_data = LPC_ICH10D }, + { PCI_VDEVICE(INTEL, 0x3b00), .driver_data = LPC_PCH }, + { PCI_VDEVICE(INTEL, 0x3b01), .driver_data = LPC_PCHM }, + { PCI_VDEVICE(INTEL, 0x3b02), .driver_data = LPC_P55 }, + { PCI_VDEVICE(INTEL, 0x3b03), .driver_data = LPC_PM55 }, + { PCI_VDEVICE(INTEL, 0x3b06), .driver_data = LPC_H55 }, + { PCI_VDEVICE(INTEL, 0x3b07), .driver_data = LPC_QM57 }, + { PCI_VDEVICE(INTEL, 0x3b08), .driver_data = LPC_H57 }, + { PCI_VDEVICE(INTEL, 0x3b09), .driver_data = LPC_HM55 }, + { PCI_VDEVICE(INTEL, 0x3b0a), .driver_data = LPC_Q57 }, + { PCI_VDEVICE(INTEL, 0x3b0b), .driver_data = LPC_HM57 }, + { PCI_VDEVICE(INTEL, 0x3b0d), .driver_data = LPC_PCHMSFF }, + { PCI_VDEVICE(INTEL, 0x3b0f), .driver_data = LPC_QS57 }, + { PCI_VDEVICE(INTEL, 0x3b12), .driver_data = LPC_3400 }, + { PCI_VDEVICE(INTEL, 0x3b14), .driver_data = LPC_3420 }, + { PCI_VDEVICE(INTEL, 0x3b16), .driver_data = LPC_3450 }, + { PCI_VDEVICE(INTEL, 0x5031), .driver_data = LPC_EP80579 }, + { PCI_VDEVICE(INTEL, 0x5ae8), .driver_data = LPC_APL }, + { PCI_VDEVICE(INTEL, 0x8c40), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c41), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c42), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c43), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c44), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c45), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c46), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c47), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c48), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c49), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c4a), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c4b), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c4c), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c4d), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c4e), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c4f), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c50), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c51), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c52), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c53), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c54), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c55), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c56), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c57), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c58), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c59), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c5a), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c5b), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c5c), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c5d), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c5e), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c5f), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8cc1), .driver_data = LPC_9S }, + { PCI_VDEVICE(INTEL, 0x8cc2), .driver_data = LPC_9S }, + { PCI_VDEVICE(INTEL, 0x8cc3), .driver_data = LPC_9S }, + { PCI_VDEVICE(INTEL, 0x8cc4), .driver_data = LPC_9S }, + { PCI_VDEVICE(INTEL, 0x8cc6), .driver_data = LPC_9S }, + { PCI_VDEVICE(INTEL, 0x8d40), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d41), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d42), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d43), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d44), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d45), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d46), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d47), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d48), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d49), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d4a), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d4b), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d4c), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d4d), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d4e), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d4f), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d50), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d51), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d52), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d53), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d54), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d55), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d56), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d57), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d58), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d59), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d5a), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d5b), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d5c), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d5d), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d5e), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d5f), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x9c40), .driver_data = LPC_LPT_LP }, + { PCI_VDEVICE(INTEL, 0x9c41), .driver_data = LPC_LPT_LP }, + { PCI_VDEVICE(INTEL, 0x9c42), .driver_data = LPC_LPT_LP }, + { PCI_VDEVICE(INTEL, 0x9c43), .driver_data = LPC_LPT_LP }, + { PCI_VDEVICE(INTEL, 0x9c44), .driver_data = LPC_LPT_LP }, + { PCI_VDEVICE(INTEL, 0x9c45), .driver_data = LPC_LPT_LP }, + { PCI_VDEVICE(INTEL, 0x9c46), .driver_data = LPC_LPT_LP }, + { PCI_VDEVICE(INTEL, 0x9c47), .driver_data = LPC_LPT_LP }, + { PCI_VDEVICE(INTEL, 0x9cc1), .driver_data = LPC_WPT_LP }, + { PCI_VDEVICE(INTEL, 0x9cc2), .driver_data = LPC_WPT_LP }, + { PCI_VDEVICE(INTEL, 0x9cc3), .driver_data = LPC_WPT_LP }, + { PCI_VDEVICE(INTEL, 0x9cc5), .driver_data = LPC_WPT_LP }, + { PCI_VDEVICE(INTEL, 0x9cc6), .driver_data = LPC_WPT_LP }, + { PCI_VDEVICE(INTEL, 0x9cc7), .driver_data = LPC_WPT_LP }, + { PCI_VDEVICE(INTEL, 0x9cc9), .driver_data = LPC_WPT_LP }, + { PCI_VDEVICE(INTEL, 0xa1c1), .driver_data = LPC_LEWISBURG }, + { PCI_VDEVICE(INTEL, 0xa1c2), .driver_data = LPC_LEWISBURG }, + { PCI_VDEVICE(INTEL, 0xa1c3), .driver_data = LPC_LEWISBURG }, + { PCI_VDEVICE(INTEL, 0xa1c4), .driver_data = LPC_LEWISBURG }, + { PCI_VDEVICE(INTEL, 0xa1c5), .driver_data = LPC_LEWISBURG }, + { PCI_VDEVICE(INTEL, 0xa1c6), .driver_data = LPC_LEWISBURG }, + { PCI_VDEVICE(INTEL, 0xa1c7), .driver_data = LPC_LEWISBURG }, + { PCI_VDEVICE(INTEL, 0xa242), .driver_data = LPC_LEWISBURG }, + { PCI_VDEVICE(INTEL, 0xa243), .driver_data = LPC_LEWISBURG }, + { }, /* End of list */ }; MODULE_DEVICE_TABLE(pci, lpc_ich_ids); diff --git a/drivers/mfd/lpc_sch.c b/drivers/mfd/lpc_sch.c index 9ab9adce06fd..d069165f9b86 100644 --- a/drivers/mfd/lpc_sch.c +++ b/drivers/mfd/lpc_sch.c @@ -64,11 +64,11 @@ static struct lpc_sch_info sch_chipset_info[] = { }; static const struct pci_device_id lpc_sch_ids[] = { - { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SCH_LPC), LPC_SCH }, - { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ITC_LPC), LPC_ITC }, - { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CENTERTON_ILB), LPC_CENTERTON }, - { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB), LPC_QUARK_X1000 }, - { 0, } + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SCH_LPC), .driver_data = LPC_SCH }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ITC_LPC), .driver_data = LPC_ITC }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CENTERTON_ILB), .driver_data = LPC_CENTERTON }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB), .driver_data = LPC_QUARK_X1000 }, + { } }; MODULE_DEVICE_TABLE(pci, lpc_sch_ids); diff --git a/drivers/mfd/sm501.c b/drivers/mfd/sm501.c index 8276456b142f..b5bda477ebfc 100644 --- a/drivers/mfd/sm501.c +++ b/drivers/mfd/sm501.c @@ -1640,8 +1640,8 @@ static void sm501_plat_remove(struct platform_device *dev) } static const struct pci_device_id sm501_pci_tbl[] = { - { 0x126f, 0x0501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { 0, }, + { PCI_DEVICE(0x126f, 0x0501) }, + { }, }; MODULE_DEVICE_TABLE(pci, sm501_pci_tbl); From 4b51f0da731adb1d3468518dc2deb5dae83978b7 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Wed, 29 Apr 2026 14:23:30 +0200 Subject: [PATCH 20/47] mfd: cs5535: Add, assign and expose the software node for the GPIO cell There are board files in-tree that want to request GPIOs from this chip. They currently rely on the GPIO core's mechanism of matching software nodes' labels against GPIO controller names. We want to remove this behavior from the kernel and to this end, we need to associate the referenced GPIO controller with its target software node. Create a dedicated GPIO software node for cs5535, assign it to the GPIO cell and expose its address in a new header. We only expose a single software node instance but that's alright: all existing hardware only contains a single cs5535 companion and the geode board file for which we expose this is legacy anyway. Signed-off-by: Bartosz Golaszewski Link: https://patch.msgid.link/20260429-cs5535-swnode-v1-1-2bc5e17ddcf9@oss.qualcomm.com Signed-off-by: Lee Jones --- drivers/mfd/cs5535-mfd.c | 9 +++++++++ include/linux/mfd/cs5535.h | 8 ++++++++ 2 files changed, 17 insertions(+) create mode 100644 include/linux/mfd/cs5535.h diff --git a/drivers/mfd/cs5535-mfd.c b/drivers/mfd/cs5535-mfd.c index d0fb2e52ee76..f3becbef19f5 100644 --- a/drivers/mfd/cs5535-mfd.c +++ b/drivers/mfd/cs5535-mfd.c @@ -12,8 +12,11 @@ #include #include +#include #include #include +#include + #include #define DRV_NAME "cs5535-mfd" @@ -29,6 +32,11 @@ enum cs5535_mfd_bars { static struct resource cs5535_mfd_resources[NR_BARS]; +const struct software_node cs5535_gpio_swnode = { + .name = "cs5535-gpio", +}; +EXPORT_SYMBOL_NS(cs5535_gpio_swnode, "CS5535"); + static struct mfd_cell cs5535_mfd_cells[] = { { .name = "cs5535-smb", @@ -39,6 +47,7 @@ static struct mfd_cell cs5535_mfd_cells[] = { .name = "cs5535-gpio", .num_resources = 1, .resources = &cs5535_mfd_resources[GPIO_BAR], + .swnode = &cs5535_gpio_swnode, }, { .name = "cs5535-mfgpt", diff --git a/include/linux/mfd/cs5535.h b/include/linux/mfd/cs5535.h new file mode 100644 index 000000000000..2e4ebf5d06af --- /dev/null +++ b/include/linux/mfd/cs5535.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MFD_CS5535_H__ +#define __MFD_CS5535_H__ + +extern const struct software_node cs5535_gpio_swnode; + +#endif /* __MFD_CS5535_H__ */ From 5618127fed7e8f974b3615d429ffdea670b203be Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Mon, 27 Apr 2026 16:34:27 +0200 Subject: [PATCH 21/47] mfd: wm8994: Remove dead legacy-gpio code The old-style gpio handling in wm8994 came from a commit 7c8844481a1c ("mfd: wm8994: Emulate level triggered interrupts if required") in linux-3.11, but nothing in the kernel ever set the 'irq_gpio' member in the wm8994_pdata structure, so this was always dead code. Remove it now to reduce the dependency on the legacy gpio interfaces. Signed-off-by: Arnd Bergmann Reviewed-by: Bartosz Golaszewski Reviewed-by: Charles Keepax Reviewed-by: Linus Walleij Link: https://patch.msgid.link/20260427143437.3059210-1-arnd@kernel.org Signed-off-by: Lee Jones --- drivers/mfd/wm8994-irq.c | 94 ++------------------------------ include/linux/mfd/wm8994/pdata.h | 5 -- 2 files changed, 4 insertions(+), 95 deletions(-) diff --git a/drivers/mfd/wm8994-irq.c b/drivers/mfd/wm8994-irq.c index 1475b1ac6983..a46cea948763 100644 --- a/drivers/mfd/wm8994-irq.c +++ b/drivers/mfd/wm8994-irq.c @@ -135,53 +135,9 @@ static const struct regmap_irq_chip wm8994_irq_chip = { .runtime_pm = true, }; -static void wm8994_edge_irq_enable(struct irq_data *data) -{ -} - -static void wm8994_edge_irq_disable(struct irq_data *data) -{ -} - -static struct irq_chip wm8994_edge_irq_chip = { - .name = "wm8994_edge", - .irq_disable = wm8994_edge_irq_disable, - .irq_enable = wm8994_edge_irq_enable, -}; - -static irqreturn_t wm8994_edge_irq(int irq, void *data) -{ - struct wm8994 *wm8994 = data; - - while (gpio_get_value_cansleep(wm8994->pdata.irq_gpio)) - handle_nested_irq(irq_find_mapping(wm8994->edge_irq, 0)); - - return IRQ_HANDLED; -} - -static int wm8994_edge_irq_map(struct irq_domain *h, unsigned int virq, - irq_hw_number_t hw) -{ - struct wm8994 *wm8994 = h->host_data; - - irq_set_chip_data(virq, wm8994); - irq_set_chip_and_handler(virq, &wm8994_edge_irq_chip, handle_edge_irq); - irq_set_nested_thread(virq, 1); - irq_set_noprobe(virq); - - return 0; -} - -static const struct irq_domain_ops wm8994_edge_irq_ops = { - .map = wm8994_edge_irq_map, - .xlate = irq_domain_xlate_twocell, -}; - int wm8994_irq_init(struct wm8994 *wm8994) { int ret; - unsigned long irqflags; - struct wm8994_pdata *pdata = &wm8994->pdata; if (!wm8994->irq) { dev_warn(wm8994->dev, @@ -190,53 +146,11 @@ int wm8994_irq_init(struct wm8994 *wm8994) return 0; } - /* select user or default irq flags */ - irqflags = IRQF_TRIGGER_HIGH | IRQF_ONESHOT; - if (pdata->irq_flags) - irqflags = pdata->irq_flags; - /* use a GPIO for edge triggered controllers */ - if (irqflags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { - if (gpio_to_irq(pdata->irq_gpio) != wm8994->irq) { - dev_warn(wm8994->dev, "IRQ %d is not GPIO %d (%d)\n", - wm8994->irq, pdata->irq_gpio, - gpio_to_irq(pdata->irq_gpio)); - wm8994->irq = gpio_to_irq(pdata->irq_gpio); - } - - ret = devm_gpio_request_one(wm8994->dev, pdata->irq_gpio, - GPIOF_IN, "WM8994 IRQ"); - - if (ret != 0) { - dev_err(wm8994->dev, "Failed to get IRQ GPIO: %d\n", - ret); - return ret; - } - - wm8994->edge_irq = irq_domain_create_linear(NULL, 1, &wm8994_edge_irq_ops, wm8994); - - ret = regmap_add_irq_chip(wm8994->regmap, - irq_create_mapping(wm8994->edge_irq, - 0), - IRQF_ONESHOT, - wm8994->irq_base, &wm8994_irq_chip, - &wm8994->irq_data); - if (ret != 0) { - dev_err(wm8994->dev, "Failed to get IRQ: %d\n", - ret); - return ret; - } - - ret = request_threaded_irq(wm8994->irq, - NULL, wm8994_edge_irq, - irqflags, - "WM8994 edge", wm8994); - } else { - ret = regmap_add_irq_chip(wm8994->regmap, wm8994->irq, - irqflags, - wm8994->irq_base, &wm8994_irq_chip, - &wm8994->irq_data); - } + ret = regmap_add_irq_chip(wm8994->regmap, wm8994->irq, + IRQF_TRIGGER_HIGH | IRQF_ONESHOT, + wm8994->irq_base, &wm8994_irq_chip, + &wm8994->irq_data); if (ret != 0) { dev_err(wm8994->dev, "Failed to register IRQ chip: %d\n", ret); diff --git a/include/linux/mfd/wm8994/pdata.h b/include/linux/mfd/wm8994/pdata.h index 6e2962ef5b81..b95a56a338c3 100644 --- a/include/linux/mfd/wm8994/pdata.h +++ b/include/linux/mfd/wm8994/pdata.h @@ -226,11 +226,6 @@ struct wm8994_pdata { * lines is mastered. */ int max_channels_clocked[WM8994_NUM_AIF]; - - /** - * GPIO for the IRQ pin if host only supports edge triggering - */ - int irq_gpio; }; #endif From 7b7b7fa42d08087a9d5f3d49453dbe721cbbd2d4 Mon Sep 17 00:00:00 2001 From: Amit Sunil Dhamne Date: Mon, 4 May 2026 22:49:54 +0000 Subject: [PATCH 22/47] mfd: max77759: Improve static struct formatting and commentary Improve code style. This includes the following: - Formatting the max77759_chgr_irqs entries to fit in a single line instead of breaking them into multiple lines to improve readability. - Refactoring comments such that they're full sentences and have punctuation marks for a couple of macro definitions to adhere to the documentation style. - Explicitly initializing `MAX77759_CHGR_MODE_OFF`. Signed-off-by: Amit Sunil Dhamne Link: https://patch.msgid.link/20260504-fix-mfd-max77759-driver-v1-1-4d4a31a1d214@google.com Signed-off-by: Lee Jones --- drivers/mfd/max77759.c | 48 ++++++++++++------------------------ include/linux/mfd/max77759.h | 6 ++--- 2 files changed, 19 insertions(+), 35 deletions(-) diff --git a/drivers/mfd/max77759.c b/drivers/mfd/max77759.c index 9fa6027a92c4..b50433e7b3d3 100644 --- a/drivers/mfd/max77759.c +++ b/drivers/mfd/max77759.c @@ -286,38 +286,22 @@ static const struct regmap_irq max77759_topsys_irqs[] = { }; static const struct regmap_irq max77759_chgr_irqs[] = { - REGMAP_IRQ_REG(MAX77759_CHGR_INT1_AICL, 0, - MAX77759_CHGR_REG_CHG_INT_AICL), - REGMAP_IRQ_REG(MAX77759_CHGR_INT1_CHGIN, 0, - MAX77759_CHGR_REG_CHG_INT_CHGIN), - REGMAP_IRQ_REG(MAX77759_CHGR_INT1_WCIN, 0, - MAX77759_CHGR_REG_CHG_INT_WCIN), - REGMAP_IRQ_REG(MAX77759_CHGR_INT1_CHG, 0, - MAX77759_CHGR_REG_CHG_INT_CHG), - REGMAP_IRQ_REG(MAX77759_CHGR_INT1_BAT, 0, - MAX77759_CHGR_REG_CHG_INT_BAT), - REGMAP_IRQ_REG(MAX77759_CHGR_INT1_INLIM, 0, - MAX77759_CHGR_REG_CHG_INT_INLIM), - REGMAP_IRQ_REG(MAX77759_CHGR_INT1_THM2, 0, - MAX77759_CHGR_REG_CHG_INT_THM2), - REGMAP_IRQ_REG(MAX77759_CHGR_INT1_BYP, 0, - MAX77759_CHGR_REG_CHG_INT_BYP), - REGMAP_IRQ_REG(MAX77759_CHGR_INT2_INSEL, 1, - MAX77759_CHGR_REG_CHG_INT2_INSEL), - REGMAP_IRQ_REG(MAX77759_CHGR_INT2_SYS_UVLO1, 1, - MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO1), - REGMAP_IRQ_REG(MAX77759_CHGR_INT2_SYS_UVLO2, 1, - MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO2), - REGMAP_IRQ_REG(MAX77759_CHGR_INT2_BAT_OILO, 1, - MAX77759_CHGR_REG_CHG_INT2_BAT_OILO), - REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_CC, 1, - MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CC), - REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_CV, 1, - MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CV), - REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_TO, 1, - MAX77759_CHGR_REG_CHG_INT2_CHG_STA_TO), - REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_DONE, 1, - MAX77759_CHGR_REG_CHG_INT2_CHG_STA_DONE), + REGMAP_IRQ_REG(MAX77759_CHGR_INT1_AICL, 0, MAX77759_CHGR_REG_CHG_INT_AICL), + REGMAP_IRQ_REG(MAX77759_CHGR_INT1_CHGIN, 0, MAX77759_CHGR_REG_CHG_INT_CHGIN), + REGMAP_IRQ_REG(MAX77759_CHGR_INT1_WCIN, 0, MAX77759_CHGR_REG_CHG_INT_WCIN), + REGMAP_IRQ_REG(MAX77759_CHGR_INT1_CHG, 0, MAX77759_CHGR_REG_CHG_INT_CHG), + REGMAP_IRQ_REG(MAX77759_CHGR_INT1_BAT, 0, MAX77759_CHGR_REG_CHG_INT_BAT), + REGMAP_IRQ_REG(MAX77759_CHGR_INT1_INLIM, 0, MAX77759_CHGR_REG_CHG_INT_INLIM), + REGMAP_IRQ_REG(MAX77759_CHGR_INT1_THM2, 0, MAX77759_CHGR_REG_CHG_INT_THM2), + REGMAP_IRQ_REG(MAX77759_CHGR_INT1_BYP, 0, MAX77759_CHGR_REG_CHG_INT_BYP), + REGMAP_IRQ_REG(MAX77759_CHGR_INT2_INSEL, 1, MAX77759_CHGR_REG_CHG_INT2_INSEL), + REGMAP_IRQ_REG(MAX77759_CHGR_INT2_SYS_UVLO1, 1, MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO1), + REGMAP_IRQ_REG(MAX77759_CHGR_INT2_SYS_UVLO2, 1, MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO2), + REGMAP_IRQ_REG(MAX77759_CHGR_INT2_BAT_OILO, 1, MAX77759_CHGR_REG_CHG_INT2_BAT_OILO), + REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_CC, 1, MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CC), + REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_CV, 1, MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CV), + REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_TO, 1, MAX77759_CHGR_REG_CHG_INT2_CHG_STA_TO), + REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_DONE, 1, MAX77759_CHGR_REG_CHG_INT2_CHG_STA_DONE), }; static const struct regmap_irq_chip max77759_pmic_irq_chip = { diff --git a/include/linux/mfd/max77759.h b/include/linux/mfd/max77759.h index ec19be952877..7c0b13219d51 100644 --- a/include/linux/mfd/max77759.h +++ b/include/linux/mfd/max77759.h @@ -106,9 +106,9 @@ #define MAX77759_CHGR_REG_CHG_CNFG_10 0xc3 #define MAX77759_CHGR_REG_CHG_CNFG_11 0xc4 #define MAX77759_CHGR_REG_CHG_CNFG_12 0xc5 -/* Wireless Charging input channel select */ +/* Setting this enables the Wireless Charging input channel. */ #define MAX77759_CHGR_REG_CHG_CNFG_12_WCINSEL BIT(6) -/* CHGIN/USB input channel select */ +/* Setting this enables the CHGIN/USB input channel. */ #define MAX77759_CHGR_REG_CHG_CNFG_12_CHGINSEL BIT(5) #define MAX77759_CHGR_REG_CHG_CNFG_13 0xc6 #define MAX77759_CHGR_REG_CHG_CNFG_14 0xc7 @@ -204,7 +204,7 @@ enum max77759_chgr_chg_dtls_states { }; enum max77759_chgr_mode { - MAX77759_CHGR_MODE_OFF, + MAX77759_CHGR_MODE_OFF = 0x0, MAX77759_CHGR_MODE_CHG_BUCK_ON = 0x5, MAX77759_CHGR_MODE_OTG_BOOST_ON = 0xA, }; From 484c67469d15d80bc466fdec7fc85caaadd4b08e Mon Sep 17 00:00:00 2001 From: Deepti Jaggi Date: Mon, 4 May 2026 16:11:22 +0800 Subject: [PATCH 23/47] dt-bindings: mfd: qcom,tcsr: Add compatible for Nord Document Top Control and Status Register (TCSR) controller on Qualcomm Nord SoC. Signed-off-by: Deepti Jaggi Signed-off-by: Shawn Guo Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260504081122.825635-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml index 14ae3f00ef7e..23317d1b381c 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml @@ -19,6 +19,7 @@ properties: - enum: - qcom,msm8976-tcsr - qcom,msm8998-tcsr + - qcom,nord-tcsr - qcom,qcm2290-tcsr - qcom,qcs404-tcsr - qcom,qcs615-tcsr From d11880e32e7b3c702ac5cd7c415543a743c3db85 Mon Sep 17 00:00:00 2001 From: Thorsten Blum Date: Tue, 28 Apr 2026 18:58:01 +0200 Subject: [PATCH 24/47] mfd: menf21bmc: Inline i2c_check_functionality check Inline the i2c_check_functionality() check, since the function returns a boolean status rather than an error code. Signed-off-by: Thorsten Blum Link: https://patch.msgid.link/20260428165800.590496-3-thorsten.blum@linux.dev Signed-off-by: Lee Jones --- drivers/mfd/menf21bmc.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/mfd/menf21bmc.c b/drivers/mfd/menf21bmc.c index 1d36095155e0..0f24de516d72 100644 --- a/drivers/mfd/menf21bmc.c +++ b/drivers/mfd/menf21bmc.c @@ -54,11 +54,9 @@ menf21bmc_probe(struct i2c_client *client) int rev_major, rev_minor, rev_main; int ret; - ret = i2c_check_functionality(client->adapter, - I2C_FUNC_SMBUS_BYTE_DATA | - I2C_FUNC_SMBUS_WORD_DATA | - I2C_FUNC_SMBUS_BYTE); - if (!ret) + if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA | + I2C_FUNC_SMBUS_WORD_DATA | + I2C_FUNC_SMBUS_BYTE)) return -ENODEV; rev_major = i2c_smbus_read_word_data(client, BMC_CMD_REV_MAJOR); From 7ee4fa2674e51a0d100b9240cd8a50355141362f Mon Sep 17 00:00:00 2001 From: Thorsten Blum Date: Tue, 5 May 2026 13:45:43 +0200 Subject: [PATCH 25/47] mfd: twl-core: Use i2c_check_functionality as boolean value i2c_check_functionality() returns a boolean status rather than an error code - directly use it as a boolean value. Signed-off-by: Thorsten Blum Link: https://patch.msgid.link/20260505114543.159381-2-thorsten.blum@linux.dev Signed-off-by: Lee Jones --- drivers/mfd/twl-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c index f89eda4a17fe..c024a28b057e 100644 --- a/drivers/mfd/twl-core.c +++ b/drivers/mfd/twl-core.c @@ -754,7 +754,7 @@ twl_probe(struct i2c_client *client) return status; } - if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C) == 0) { + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { dev_dbg(&client->dev, "can't talk I2C?\n"); status = -EIO; goto free; From e6f0018fbf1f4eabd3fb8ac71f06cb31efce3c86 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 30 Apr 2026 18:28:05 +0200 Subject: [PATCH 26/47] mfd: ezx-pcap: Remove unused driver Support for the Motorola EZX phones based on Intel PXA processors was removed in 2022, but this driver remained present in the tree. As far as I can tell, the support was never quite functional upstream because the board files did not actually instantiate the SPI device for the PCAP. There are still also drivers for the various mfd cells: keys, touchscreen, regulator and rtc, all of which are obviously orphaned as well but can be removed separately as the Kconfig dependency now prevents them from being enabled. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202604301209.f1YXTsIr-lkp@intel.com/ Signed-off-by: Arnd Bergmann Reviewed-by: Linus Walleij Acked-by: Harald Welte Reviewed-by: Bartosz Golaszewski Link: https://patch.msgid.link/20260430162855.2029285-1-arnd@kernel.org Signed-off-by: Lee Jones --- drivers/mfd/Kconfig | 7 - drivers/mfd/Makefile | 1 - drivers/mfd/ezx-pcap.c | 491 ----------------------------------- include/linux/mfd/ezx-pcap.h | 253 ------------------ 4 files changed, 752 deletions(-) delete mode 100644 drivers/mfd/ezx-pcap.c delete mode 100644 include/linux/mfd/ezx-pcap.h diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 7192c9d1d268..d08d70d41bce 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1199,13 +1199,6 @@ config MFD_OCELOT If unsure, say N. -config EZX_PCAP - bool "Motorola EZXPCAP Support" - depends on SPI_MASTER - help - This enables the PCAP ASIC present on EZX Phones. This is - needed for MMC, TouchScreen, Sound, USB, etc.. - config MFD_CPCAP tristate "Support for Motorola CPCAP" depends on SPI diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index e75e8045c28a..dd4bb7e77c33 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -131,7 +131,6 @@ obj-$(CONFIG_MFD_CORE) += mfd-core.o ocelot-soc-objs := ocelot-core.o ocelot-spi.o obj-$(CONFIG_MFD_OCELOT) += ocelot-soc.o -obj-$(CONFIG_EZX_PCAP) += ezx-pcap.o obj-$(CONFIG_MFD_CPCAP) += motorola-cpcap.o obj-$(CONFIG_MCP) += mcp-core.o diff --git a/drivers/mfd/ezx-pcap.c b/drivers/mfd/ezx-pcap.c deleted file mode 100644 index 9a685ff8cd15..000000000000 --- a/drivers/mfd/ezx-pcap.c +++ /dev/null @@ -1,491 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Driver for Motorola PCAP2 as present in EZX phones - * - * Copyright (C) 2006 Harald Welte - * Copyright (C) 2009 Daniel Ribeiro - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define PCAP_ADC_MAXQ 8 -struct pcap_adc_request { - u8 bank; - u8 ch[2]; - u32 flags; - void (*callback)(void *, u16[]); - void *data; -}; - -struct pcap_chip { - struct spi_device *spi; - - /* IO */ - u32 buf; - spinlock_t io_lock; - - /* IRQ */ - unsigned int irq_base; - u32 msr; - struct work_struct isr_work; - struct work_struct msr_work; - struct workqueue_struct *workqueue; - - /* ADC */ - struct pcap_adc_request *adc_queue[PCAP_ADC_MAXQ]; - u8 adc_head; - u8 adc_tail; - spinlock_t adc_lock; -}; - -/* IO */ -static int ezx_pcap_putget(struct pcap_chip *pcap, u32 *data) -{ - struct spi_transfer t; - struct spi_message m; - int status; - - memset(&t, 0, sizeof(t)); - spi_message_init(&m); - t.len = sizeof(u32); - spi_message_add_tail(&t, &m); - - pcap->buf = *data; - t.tx_buf = (u8 *) &pcap->buf; - t.rx_buf = (u8 *) &pcap->buf; - status = spi_sync(pcap->spi, &m); - - if (status == 0) - *data = pcap->buf; - - return status; -} - -int ezx_pcap_write(struct pcap_chip *pcap, u8 reg_num, u32 value) -{ - unsigned long flags; - int ret; - - spin_lock_irqsave(&pcap->io_lock, flags); - value &= PCAP_REGISTER_VALUE_MASK; - value |= PCAP_REGISTER_WRITE_OP_BIT - | (reg_num << PCAP_REGISTER_ADDRESS_SHIFT); - ret = ezx_pcap_putget(pcap, &value); - spin_unlock_irqrestore(&pcap->io_lock, flags); - - return ret; -} -EXPORT_SYMBOL_GPL(ezx_pcap_write); - -int ezx_pcap_read(struct pcap_chip *pcap, u8 reg_num, u32 *value) -{ - unsigned long flags; - int ret; - - spin_lock_irqsave(&pcap->io_lock, flags); - *value = PCAP_REGISTER_READ_OP_BIT - | (reg_num << PCAP_REGISTER_ADDRESS_SHIFT); - - ret = ezx_pcap_putget(pcap, value); - spin_unlock_irqrestore(&pcap->io_lock, flags); - - return ret; -} -EXPORT_SYMBOL_GPL(ezx_pcap_read); - -int ezx_pcap_set_bits(struct pcap_chip *pcap, u8 reg_num, u32 mask, u32 val) -{ - unsigned long flags; - int ret; - u32 tmp = PCAP_REGISTER_READ_OP_BIT | - (reg_num << PCAP_REGISTER_ADDRESS_SHIFT); - - spin_lock_irqsave(&pcap->io_lock, flags); - ret = ezx_pcap_putget(pcap, &tmp); - if (ret) - goto out_unlock; - - tmp &= (PCAP_REGISTER_VALUE_MASK & ~mask); - tmp |= (val & mask) | PCAP_REGISTER_WRITE_OP_BIT | - (reg_num << PCAP_REGISTER_ADDRESS_SHIFT); - - ret = ezx_pcap_putget(pcap, &tmp); -out_unlock: - spin_unlock_irqrestore(&pcap->io_lock, flags); - - return ret; -} -EXPORT_SYMBOL_GPL(ezx_pcap_set_bits); - -/* IRQ */ -int irq_to_pcap(struct pcap_chip *pcap, int irq) -{ - return irq - pcap->irq_base; -} -EXPORT_SYMBOL_GPL(irq_to_pcap); - -int pcap_to_irq(struct pcap_chip *pcap, int irq) -{ - return pcap->irq_base + irq; -} -EXPORT_SYMBOL_GPL(pcap_to_irq); - -static void pcap_mask_irq(struct irq_data *d) -{ - struct pcap_chip *pcap = irq_data_get_irq_chip_data(d); - - pcap->msr |= 1 << irq_to_pcap(pcap, d->irq); - queue_work(pcap->workqueue, &pcap->msr_work); -} - -static void pcap_unmask_irq(struct irq_data *d) -{ - struct pcap_chip *pcap = irq_data_get_irq_chip_data(d); - - pcap->msr &= ~(1 << irq_to_pcap(pcap, d->irq)); - queue_work(pcap->workqueue, &pcap->msr_work); -} - -static struct irq_chip pcap_irq_chip = { - .name = "pcap", - .irq_disable = pcap_mask_irq, - .irq_mask = pcap_mask_irq, - .irq_unmask = pcap_unmask_irq, -}; - -static void pcap_msr_work(struct work_struct *work) -{ - struct pcap_chip *pcap = container_of(work, struct pcap_chip, msr_work); - - ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr); -} - -static void pcap_isr_work(struct work_struct *work) -{ - struct pcap_chip *pcap = container_of(work, struct pcap_chip, isr_work); - struct pcap_platform_data *pdata = dev_get_platdata(&pcap->spi->dev); - u32 msr, isr, int_sel, service; - int irq; - - do { - ezx_pcap_read(pcap, PCAP_REG_MSR, &msr); - ezx_pcap_read(pcap, PCAP_REG_ISR, &isr); - - /* We can't service/ack irqs that are assigned to port 2 */ - if (!(pdata->config & PCAP_SECOND_PORT)) { - ezx_pcap_read(pcap, PCAP_REG_INT_SEL, &int_sel); - isr &= ~int_sel; - } - - ezx_pcap_write(pcap, PCAP_REG_MSR, isr | msr); - ezx_pcap_write(pcap, PCAP_REG_ISR, isr); - - service = isr & ~msr; - for (irq = pcap->irq_base; service; service >>= 1, irq++) { - if (service & 1) - generic_handle_irq_safe(irq); - } - ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr); - } while (gpio_get_value(pdata->gpio)); -} - -static void pcap_irq_handler(struct irq_desc *desc) -{ - struct pcap_chip *pcap = irq_desc_get_handler_data(desc); - - desc->irq_data.chip->irq_ack(&desc->irq_data); - queue_work(pcap->workqueue, &pcap->isr_work); -} - -/* ADC */ -void pcap_set_ts_bits(struct pcap_chip *pcap, u32 bits) -{ - unsigned long flags; - u32 tmp; - - spin_lock_irqsave(&pcap->adc_lock, flags); - ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp); - tmp &= ~(PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR); - tmp |= bits & (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR); - ezx_pcap_write(pcap, PCAP_REG_ADC, tmp); - spin_unlock_irqrestore(&pcap->adc_lock, flags); -} -EXPORT_SYMBOL_GPL(pcap_set_ts_bits); - -static void pcap_disable_adc(struct pcap_chip *pcap) -{ - u32 tmp; - - ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp); - tmp &= ~(PCAP_ADC_ADEN|PCAP_ADC_BATT_I_ADC|PCAP_ADC_BATT_I_POLARITY); - ezx_pcap_write(pcap, PCAP_REG_ADC, tmp); -} - -static void pcap_adc_trigger(struct pcap_chip *pcap) -{ - unsigned long flags; - u32 tmp; - u8 head; - - spin_lock_irqsave(&pcap->adc_lock, flags); - head = pcap->adc_head; - if (!pcap->adc_queue[head]) { - /* queue is empty, save power */ - pcap_disable_adc(pcap); - spin_unlock_irqrestore(&pcap->adc_lock, flags); - return; - } - /* start conversion on requested bank, save TS_M bits */ - ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp); - tmp &= (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR); - tmp |= pcap->adc_queue[head]->flags | PCAP_ADC_ADEN; - - if (pcap->adc_queue[head]->bank == PCAP_ADC_BANK_1) - tmp |= PCAP_ADC_AD_SEL1; - - ezx_pcap_write(pcap, PCAP_REG_ADC, tmp); - spin_unlock_irqrestore(&pcap->adc_lock, flags); - ezx_pcap_write(pcap, PCAP_REG_ADR, PCAP_ADR_ASC); -} - -static irqreturn_t pcap_adc_irq(int irq, void *_pcap) -{ - struct pcap_chip *pcap = _pcap; - struct pcap_adc_request *req; - u16 res[2]; - u32 tmp; - - spin_lock(&pcap->adc_lock); - req = pcap->adc_queue[pcap->adc_head]; - - if (WARN(!req, "adc irq without pending request\n")) { - spin_unlock(&pcap->adc_lock); - return IRQ_HANDLED; - } - - /* read requested channels results */ - ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp); - tmp &= ~(PCAP_ADC_ADA1_MASK | PCAP_ADC_ADA2_MASK); - tmp |= (req->ch[0] << PCAP_ADC_ADA1_SHIFT); - tmp |= (req->ch[1] << PCAP_ADC_ADA2_SHIFT); - ezx_pcap_write(pcap, PCAP_REG_ADC, tmp); - ezx_pcap_read(pcap, PCAP_REG_ADR, &tmp); - res[0] = (tmp & PCAP_ADR_ADD1_MASK) >> PCAP_ADR_ADD1_SHIFT; - res[1] = (tmp & PCAP_ADR_ADD2_MASK) >> PCAP_ADR_ADD2_SHIFT; - - pcap->adc_queue[pcap->adc_head] = NULL; - pcap->adc_head = (pcap->adc_head + 1) & (PCAP_ADC_MAXQ - 1); - spin_unlock(&pcap->adc_lock); - - /* pass the results and release memory */ - req->callback(req->data, res); - kfree(req); - - /* trigger next conversion (if any) on queue */ - pcap_adc_trigger(pcap); - - return IRQ_HANDLED; -} - -int pcap_adc_async(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[], - void *callback, void *data) -{ - struct pcap_adc_request *req; - unsigned long irq_flags; - - /* This will be freed after we have a result */ - req = kmalloc_obj(struct pcap_adc_request); - if (!req) - return -ENOMEM; - - req->bank = bank; - req->flags = flags; - req->ch[0] = ch[0]; - req->ch[1] = ch[1]; - req->callback = callback; - req->data = data; - - spin_lock_irqsave(&pcap->adc_lock, irq_flags); - if (pcap->adc_queue[pcap->adc_tail]) { - spin_unlock_irqrestore(&pcap->adc_lock, irq_flags); - kfree(req); - return -EBUSY; - } - pcap->adc_queue[pcap->adc_tail] = req; - pcap->adc_tail = (pcap->adc_tail + 1) & (PCAP_ADC_MAXQ - 1); - spin_unlock_irqrestore(&pcap->adc_lock, irq_flags); - - /* start conversion */ - pcap_adc_trigger(pcap); - - return 0; -} -EXPORT_SYMBOL_GPL(pcap_adc_async); - -/* subdevs */ -static int pcap_remove_subdev(struct device *dev, void *unused) -{ - platform_device_unregister(to_platform_device(dev)); - return 0; -} - -static int pcap_add_subdev(struct pcap_chip *pcap, - struct pcap_subdev *subdev) -{ - struct platform_device *pdev; - int ret; - - pdev = platform_device_alloc(subdev->name, subdev->id); - if (!pdev) - return -ENOMEM; - - pdev->dev.parent = &pcap->spi->dev; - pdev->dev.platform_data = subdev->platform_data; - - ret = platform_device_add(pdev); - if (ret) - platform_device_put(pdev); - - return ret; -} - -static void ezx_pcap_remove(struct spi_device *spi) -{ - struct pcap_chip *pcap = spi_get_drvdata(spi); - unsigned long flags; - int i; - - /* remove all registered subdevs */ - device_for_each_child(&spi->dev, NULL, pcap_remove_subdev); - - /* cleanup ADC */ - spin_lock_irqsave(&pcap->adc_lock, flags); - for (i = 0; i < PCAP_ADC_MAXQ; i++) - kfree(pcap->adc_queue[i]); - spin_unlock_irqrestore(&pcap->adc_lock, flags); - - /* cleanup irqchip */ - for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++) - irq_set_chip_and_handler(i, NULL, NULL); -} - -static int ezx_pcap_probe(struct spi_device *spi) -{ - struct pcap_platform_data *pdata = dev_get_platdata(&spi->dev); - struct pcap_chip *pcap; - int i, adc_irq; - int ret; - - /* platform data is required */ - if (!pdata) - return -ENODEV; - - pcap = devm_kzalloc(&spi->dev, sizeof(*pcap), GFP_KERNEL); - if (!pcap) - return -ENOMEM; - - spin_lock_init(&pcap->io_lock); - spin_lock_init(&pcap->adc_lock); - INIT_WORK(&pcap->isr_work, pcap_isr_work); - INIT_WORK(&pcap->msr_work, pcap_msr_work); - spi_set_drvdata(spi, pcap); - - /* setup spi */ - spi->bits_per_word = 32; - spi->mode = SPI_MODE_0 | (pdata->config & PCAP_CS_AH ? SPI_CS_HIGH : 0); - ret = spi_setup(spi); - if (ret) - return ret; - - pcap->spi = spi; - - /* setup irq */ - pcap->irq_base = pdata->irq_base; - pcap->workqueue = devm_alloc_ordered_workqueue(&spi->dev, "pcapd", 0); - if (!pcap->workqueue) - return -ENOMEM; - - /* redirect interrupts to AP, except adcdone2 */ - if (!(pdata->config & PCAP_SECOND_PORT)) - ezx_pcap_write(pcap, PCAP_REG_INT_SEL, - (1 << PCAP_IRQ_ADCDONE2)); - - /* setup irq chip */ - for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++) { - irq_set_chip_and_handler(i, &pcap_irq_chip, handle_simple_irq); - irq_set_chip_data(i, pcap); - irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE); - } - - /* mask/ack all PCAP interrupts */ - ezx_pcap_write(pcap, PCAP_REG_MSR, PCAP_MASK_ALL_INTERRUPT); - ezx_pcap_write(pcap, PCAP_REG_ISR, PCAP_CLEAR_INTERRUPT_REGISTER); - pcap->msr = PCAP_MASK_ALL_INTERRUPT; - - irq_set_irq_type(spi->irq, IRQ_TYPE_EDGE_RISING); - irq_set_chained_handler_and_data(spi->irq, pcap_irq_handler, pcap); - irq_set_irq_wake(spi->irq, 1); - - /* ADC */ - adc_irq = pcap_to_irq(pcap, (pdata->config & PCAP_SECOND_PORT) ? - PCAP_IRQ_ADCDONE2 : PCAP_IRQ_ADCDONE); - - ret = devm_request_irq(&spi->dev, adc_irq, pcap_adc_irq, 0, "ADC", - pcap); - if (ret) - goto free_irqchip; - - /* setup subdevs */ - for (i = 0; i < pdata->num_subdevs; i++) { - ret = pcap_add_subdev(pcap, &pdata->subdevs[i]); - if (ret) - goto remove_subdevs; - } - - /* board specific quirks */ - if (pdata->init) - pdata->init(pcap); - - return 0; - -remove_subdevs: - device_for_each_child(&spi->dev, NULL, pcap_remove_subdev); -free_irqchip: - for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++) - irq_set_chip_and_handler(i, NULL, NULL); - - return ret; -} - -static struct spi_driver ezxpcap_driver = { - .probe = ezx_pcap_probe, - .remove = ezx_pcap_remove, - .driver = { - .name = "ezx-pcap", - }, -}; - -static int __init ezx_pcap_init(void) -{ - return spi_register_driver(&ezxpcap_driver); -} - -static void __exit ezx_pcap_exit(void) -{ - spi_unregister_driver(&ezxpcap_driver); -} - -subsys_initcall(ezx_pcap_init); -module_exit(ezx_pcap_exit); - -MODULE_AUTHOR("Daniel Ribeiro / Harald Welte"); -MODULE_DESCRIPTION("Motorola PCAP2 ASIC Driver"); -MODULE_ALIAS("spi:ezx-pcap"); diff --git a/include/linux/mfd/ezx-pcap.h b/include/linux/mfd/ezx-pcap.h deleted file mode 100644 index ea51b1cdca5a..000000000000 --- a/include/linux/mfd/ezx-pcap.h +++ /dev/null @@ -1,253 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2009 Daniel Ribeiro - * - * For further information, please see http://wiki.openezx.org/PCAP2 - */ - -#ifndef EZX_PCAP_H -#define EZX_PCAP_H - -struct pcap_subdev { - int id; - const char *name; - void *platform_data; -}; - -struct pcap_platform_data { - unsigned int irq_base; - unsigned int config; - int gpio; - void (*init) (void *); /* board specific init */ - int num_subdevs; - struct pcap_subdev *subdevs; -}; - -struct pcap_chip; - -int ezx_pcap_write(struct pcap_chip *, u8, u32); -int ezx_pcap_read(struct pcap_chip *, u8, u32 *); -int ezx_pcap_set_bits(struct pcap_chip *, u8, u32, u32); -int pcap_to_irq(struct pcap_chip *, int); -int irq_to_pcap(struct pcap_chip *, int); -int pcap_adc_async(struct pcap_chip *, u8, u32, u8[], void *, void *); -void pcap_set_ts_bits(struct pcap_chip *, u32); - -#define PCAP_SECOND_PORT 1 -#define PCAP_CS_AH 2 - -#define PCAP_REGISTER_WRITE_OP_BIT 0x80000000 -#define PCAP_REGISTER_READ_OP_BIT 0x00000000 - -#define PCAP_REGISTER_VALUE_MASK 0x01ffffff -#define PCAP_REGISTER_ADDRESS_MASK 0x7c000000 -#define PCAP_REGISTER_ADDRESS_SHIFT 26 -#define PCAP_REGISTER_NUMBER 32 -#define PCAP_CLEAR_INTERRUPT_REGISTER 0x01ffffff -#define PCAP_MASK_ALL_INTERRUPT 0x01ffffff - -/* registers accessible by both pcap ports */ -#define PCAP_REG_ISR 0x0 /* Interrupt Status */ -#define PCAP_REG_MSR 0x1 /* Interrupt Mask */ -#define PCAP_REG_PSTAT 0x2 /* Processor Status */ -#define PCAP_REG_VREG2 0x6 /* Regulator Bank 2 Control */ -#define PCAP_REG_AUXVREG 0x7 /* Auxiliary Regulator Control */ -#define PCAP_REG_BATT 0x8 /* Battery Control */ -#define PCAP_REG_ADC 0x9 /* AD Control */ -#define PCAP_REG_ADR 0xa /* AD Result */ -#define PCAP_REG_CODEC 0xb /* Audio Codec Control */ -#define PCAP_REG_RX_AMPS 0xc /* RX Audio Amplifiers Control */ -#define PCAP_REG_ST_DAC 0xd /* Stereo DAC Control */ -#define PCAP_REG_BUSCTRL 0x14 /* Connectivity Control */ -#define PCAP_REG_PERIPH 0x15 /* Peripheral Control */ -#define PCAP_REG_LOWPWR 0x18 /* Regulator Low Power Control */ -#define PCAP_REG_TX_AMPS 0x1a /* TX Audio Amplifiers Control */ -#define PCAP_REG_GP 0x1b /* General Purpose */ -#define PCAP_REG_TEST1 0x1c -#define PCAP_REG_TEST2 0x1d -#define PCAP_REG_VENDOR_TEST1 0x1e -#define PCAP_REG_VENDOR_TEST2 0x1f - -/* registers accessible by pcap port 1 only (a1200, e2 & e6) */ -#define PCAP_REG_INT_SEL 0x3 /* Interrupt Select */ -#define PCAP_REG_SWCTRL 0x4 /* Switching Regulator Control */ -#define PCAP_REG_VREG1 0x5 /* Regulator Bank 1 Control */ -#define PCAP_REG_RTC_TOD 0xe /* RTC Time of Day */ -#define PCAP_REG_RTC_TODA 0xf /* RTC Time of Day Alarm */ -#define PCAP_REG_RTC_DAY 0x10 /* RTC Day */ -#define PCAP_REG_RTC_DAYA 0x11 /* RTC Day Alarm */ -#define PCAP_REG_MTRTMR 0x12 /* AD Monitor Timer */ -#define PCAP_REG_PWR 0x13 /* Power Control */ -#define PCAP_REG_AUXVREG_MASK 0x16 /* Auxiliary Regulator Mask */ -#define PCAP_REG_VENDOR_REV 0x17 -#define PCAP_REG_PERIPH_MASK 0x19 /* Peripheral Mask */ - -/* PCAP2 Interrupts */ -#define PCAP_NIRQS 23 -#define PCAP_IRQ_ADCDONE 0 /* ADC done port 1 */ -#define PCAP_IRQ_TS 1 /* Touch Screen */ -#define PCAP_IRQ_1HZ 2 /* 1HZ timer */ -#define PCAP_IRQ_WH 3 /* ADC above high limit */ -#define PCAP_IRQ_WL 4 /* ADC below low limit */ -#define PCAP_IRQ_TODA 5 /* Time of day alarm */ -#define PCAP_IRQ_USB4V 6 /* USB above 4V */ -#define PCAP_IRQ_ONOFF 7 /* On/Off button */ -#define PCAP_IRQ_ONOFF2 8 /* On/Off button 2 */ -#define PCAP_IRQ_USB1V 9 /* USB above 1V */ -#define PCAP_IRQ_MOBPORT 10 -#define PCAP_IRQ_MIC 11 /* Mic attach/HS button */ -#define PCAP_IRQ_HS 12 /* Headset attach */ -#define PCAP_IRQ_ST 13 -#define PCAP_IRQ_PC 14 /* Power Cut */ -#define PCAP_IRQ_WARM 15 -#define PCAP_IRQ_EOL 16 /* Battery End Of Life */ -#define PCAP_IRQ_CLK 17 -#define PCAP_IRQ_SYSRST 18 /* System Reset */ -#define PCAP_IRQ_DUMMY 19 -#define PCAP_IRQ_ADCDONE2 20 /* ADC done port 2 */ -#define PCAP_IRQ_SOFTRESET 21 -#define PCAP_IRQ_MNEXB 22 - -/* voltage regulators */ -#define V1 0 -#define V2 1 -#define V3 2 -#define V4 3 -#define V5 4 -#define V6 5 -#define V7 6 -#define V8 7 -#define V9 8 -#define V10 9 -#define VAUX1 10 -#define VAUX2 11 -#define VAUX3 12 -#define VAUX4 13 -#define VSIM 14 -#define VSIM2 15 -#define VVIB 16 -#define SW1 17 -#define SW2 18 -#define SW3 19 -#define SW1S 20 -#define SW2S 21 - -#define PCAP_BATT_DAC_MASK 0x000000ff -#define PCAP_BATT_DAC_SHIFT 0 -#define PCAP_BATT_B_FDBK (1 << 8) -#define PCAP_BATT_EXT_ISENSE (1 << 9) -#define PCAP_BATT_V_COIN_MASK 0x00003c00 -#define PCAP_BATT_V_COIN_SHIFT 10 -#define PCAP_BATT_I_COIN (1 << 14) -#define PCAP_BATT_COIN_CH_EN (1 << 15) -#define PCAP_BATT_EOL_SEL_MASK 0x000e0000 -#define PCAP_BATT_EOL_SEL_SHIFT 17 -#define PCAP_BATT_EOL_CMP_EN (1 << 20) -#define PCAP_BATT_BATT_DET_EN (1 << 21) -#define PCAP_BATT_THERMBIAS_CTRL (1 << 22) - -#define PCAP_ADC_ADEN (1 << 0) -#define PCAP_ADC_RAND (1 << 1) -#define PCAP_ADC_AD_SEL1 (1 << 2) -#define PCAP_ADC_AD_SEL2 (1 << 3) -#define PCAP_ADC_ADA1_MASK 0x00000070 -#define PCAP_ADC_ADA1_SHIFT 4 -#define PCAP_ADC_ADA2_MASK 0x00000380 -#define PCAP_ADC_ADA2_SHIFT 7 -#define PCAP_ADC_ATO_MASK 0x00003c00 -#define PCAP_ADC_ATO_SHIFT 10 -#define PCAP_ADC_ATOX (1 << 14) -#define PCAP_ADC_MTR1 (1 << 15) -#define PCAP_ADC_MTR2 (1 << 16) -#define PCAP_ADC_TS_M_MASK 0x000e0000 -#define PCAP_ADC_TS_M_SHIFT 17 -#define PCAP_ADC_TS_REF_LOWPWR (1 << 20) -#define PCAP_ADC_TS_REFENB (1 << 21) -#define PCAP_ADC_BATT_I_POLARITY (1 << 22) -#define PCAP_ADC_BATT_I_ADC (1 << 23) - -#define PCAP_ADC_BANK_0 0 -#define PCAP_ADC_BANK_1 1 -/* ADC bank 0 */ -#define PCAP_ADC_CH_COIN 0 -#define PCAP_ADC_CH_BATT 1 -#define PCAP_ADC_CH_BPLUS 2 -#define PCAP_ADC_CH_MOBPORTB 3 -#define PCAP_ADC_CH_TEMPERATURE 4 -#define PCAP_ADC_CH_CHARGER_ID 5 -#define PCAP_ADC_CH_AD6 6 -/* ADC bank 1 */ -#define PCAP_ADC_CH_AD7 0 -#define PCAP_ADC_CH_AD8 1 -#define PCAP_ADC_CH_AD9 2 -#define PCAP_ADC_CH_TS_X1 3 -#define PCAP_ADC_CH_TS_X2 4 -#define PCAP_ADC_CH_TS_Y1 5 -#define PCAP_ADC_CH_TS_Y2 6 - -#define PCAP_ADC_T_NOW 0 -#define PCAP_ADC_T_IN_BURST 1 -#define PCAP_ADC_T_OUT_BURST 2 - -#define PCAP_ADC_ATO_IN_BURST 6 -#define PCAP_ADC_ATO_OUT_BURST 0 - -#define PCAP_ADC_TS_M_XY 1 -#define PCAP_ADC_TS_M_PRESSURE 2 -#define PCAP_ADC_TS_M_PLATE_X 3 -#define PCAP_ADC_TS_M_PLATE_Y 4 -#define PCAP_ADC_TS_M_STANDBY 5 -#define PCAP_ADC_TS_M_NONTS 6 - -#define PCAP_ADR_ADD1_MASK 0x000003ff -#define PCAP_ADR_ADD1_SHIFT 0 -#define PCAP_ADR_ADD2_MASK 0x000ffc00 -#define PCAP_ADR_ADD2_SHIFT 10 -#define PCAP_ADR_ADINC1 (1 << 20) -#define PCAP_ADR_ADINC2 (1 << 21) -#define PCAP_ADR_ASC (1 << 22) -#define PCAP_ADR_ONESHOT (1 << 23) - -#define PCAP_BUSCTRL_FSENB (1 << 0) -#define PCAP_BUSCTRL_USB_SUSPEND (1 << 1) -#define PCAP_BUSCTRL_USB_PU (1 << 2) -#define PCAP_BUSCTRL_USB_PD (1 << 3) -#define PCAP_BUSCTRL_VUSB_EN (1 << 4) -#define PCAP_BUSCTRL_USB_PS (1 << 5) -#define PCAP_BUSCTRL_VUSB_MSTR_EN (1 << 6) -#define PCAP_BUSCTRL_VBUS_PD_ENB (1 << 7) -#define PCAP_BUSCTRL_CURRLIM (1 << 8) -#define PCAP_BUSCTRL_RS232ENB (1 << 9) -#define PCAP_BUSCTRL_RS232_DIR (1 << 10) -#define PCAP_BUSCTRL_SE0_CONN (1 << 11) -#define PCAP_BUSCTRL_USB_PDM (1 << 12) -#define PCAP_BUSCTRL_BUS_PRI_ADJ (1 << 24) - -/* leds */ -#define PCAP_LED0 0 -#define PCAP_LED1 1 -#define PCAP_BL0 2 -#define PCAP_BL1 3 -#define PCAP_LED_3MA 0 -#define PCAP_LED_4MA 1 -#define PCAP_LED_5MA 2 -#define PCAP_LED_9MA 3 -#define PCAP_LED_T_MASK 0xf -#define PCAP_LED_C_MASK 0x3 -#define PCAP_BL_MASK 0x1f -#define PCAP_BL0_SHIFT 0 -#define PCAP_LED0_EN (1 << 5) -#define PCAP_LED1_EN (1 << 6) -#define PCAP_LED0_T_SHIFT 7 -#define PCAP_LED1_T_SHIFT 11 -#define PCAP_LED0_C_SHIFT 15 -#define PCAP_LED1_C_SHIFT 17 -#define PCAP_BL1_SHIFT 20 - -/* RTC */ -#define PCAP_RTC_DAY_MASK 0x3fff -#define PCAP_RTC_TOD_MASK 0xffff -#define PCAP_RTC_PC_MASK 0x7 -#define SEC_PER_DAY 86400 - -#endif From 2611c4d623ba867e196a4146f1927c3c468ac2bc Mon Sep 17 00:00:00 2001 From: Billy Tsai Date: Tue, 28 Apr 2026 17:49:46 +0800 Subject: [PATCH 27/47] dt-bindings: mfd: aspeed,ast2x00-scu: Describe AST2700 SCU0 AST2700 consists of two interconnected SoC instances, each with its own System Control Unit (SCU). The SCU0 provides pin control, interrupt controllers, clocks, resets, and address-space mappings for the Secondary and Tertiary Service Processors (SSP and TSP). Describe the SSP/TSP address mappings using the standard memory-region and memory-region-names properties. Disallow legacy child nodes that are not present on AST2700, including p2a-control and smp-memram. The latter is unnecessary as software can access the scratch registers via the SCU syscon. Also allow the AST2700 SoC0 pin controller to be described as a child node of the SCU0, and add an example illustrating the SCU0 layout, including reserved-memory, interrupt controllers, and pinctrl. Signed-off-by: Billy Tsai Reviewed-by: Rob Herring (Arm) Acked-by: Linus Walleij Link: https://patch.msgid.link/20260428-upstream_pinctrl-v8-2-eb8ef9ab0498@aspeedtech.com Signed-off-by: Lee Jones --- .../bindings/mfd/aspeed,ast2x00-scu.yaml | 114 ++++++++++++++++++ 1 file changed, 114 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml index a87f31fce019..0d5e168b0309 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml +++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml @@ -46,6 +46,18 @@ properties: '#reset-cells': const: 1 + memory-region: + items: + - description: Region mapped through the first SSP address window. + - description: Region mapped through the second SSP address window. + - description: Region mapped through the TSP address window. + + memory-region-names: + items: + - const: ssp-0 + - const: ssp-1 + - const: tsp + patternProperties: '^p2a-control@[0-9a-f]+$': description: > @@ -87,6 +99,7 @@ patternProperties: - aspeed,ast2400-pinctrl - aspeed,ast2500-pinctrl - aspeed,ast2600-pinctrl + - aspeed,ast2700-soc0-pinctrl required: - compatible @@ -156,6 +169,30 @@ required: - '#clock-cells' - '#reset-cells' +allOf: + - if: + properties: + compatible: + contains: + enum: + - aspeed,ast2700-scu0 + - aspeed,ast2700-scu1 + then: + patternProperties: + '^p2a-control@[0-9a-f]+$': false + '^smp-memram@[0-9a-f]+$': false + + - if: + not: + properties: + compatible: + contains: + const: aspeed,ast2700-scu0 + then: + properties: + memory-region: false + memory-region-names: false + additionalProperties: false examples: @@ -180,4 +217,81 @@ examples: reg = <0x7c 0x4>, <0x150 0x8>; }; }; + + - | + / { + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ssp_region_0: memory@400000000 { + reg = <0x4 0x00000000 0x0 0x01000000>; + no-map; + }; + + ssp_region_1: memory@401000000 { + reg = <0x4 0x01000000 0x0 0x01000000>; + no-map; + }; + + tsp_region: memory@402000000 { + reg = <0x4 0x02000000 0x0 0x01000000>; + no-map; + }; + }; + + bus { + #address-cells = <2>; + #size-cells = <2>; + + syscon@12c02000 { + compatible = "aspeed,ast2700-scu0", "syscon", "simple-mfd"; + reg = <0 0x12c02000 0 0x1000>; + ranges = <0x0 0x0 0x12c02000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + #clock-cells = <1>; + #reset-cells = <1>; + + memory-region = <&ssp_region_0>, <&ssp_region_1>, + <&tsp_region>; + memory-region-names = "ssp-0", "ssp-1", "tsp"; + + silicon-id@0 { + compatible = "aspeed,ast2700-silicon-id", "aspeed,silicon-id"; + reg = <0x0 0x4>; + }; + + interrupt-controller@1b0 { + compatible = "aspeed,ast2700-scu-ic0"; + reg = <0x1b0 0x4>; + #interrupt-cells = <1>; + interrupts-extended = <&intc0 97>; + interrupt-controller; + }; + + interrupt-controller@1e0 { + compatible = "aspeed,ast2700-scu-ic1"; + reg = <0x1e0 0x4>; + #interrupt-cells = <1>; + interrupts-extended = <&intc0 98>; + interrupt-controller; + }; + + pinctrl@400 { + compatible = "aspeed,ast2700-soc0-pinctrl"; + reg = <0x400 0x318>; + emmc-state { + function = "EMMC"; + groups = "EMMCG1"; + }; + }; + }; + }; + }; + ... From 8b2c1d41bc36c100b38ce5ee6def246c527eaf8a Mon Sep 17 00:00:00 2001 From: Andrei Kuchynski Date: Mon, 27 Apr 2026 13:17:21 +0000 Subject: [PATCH 28/47] mfd: cros_ec: Delay dev_set_drvdata() until probe success If ec_device_probe() fails, cros_ec_class_release releases memory for the cros_ec_dev structure. However, because the drvdata was already set, sub-drivers like cros_ec_typec can still retrieve the stale pointer via the platform device. This leads to a use-after-free when cros_ec_typec attempts to access &typec->ec->ec->dev on a device that has already been released. Move dev_set_drvdata() to ensure that the pointer is only made available once all initialization steps have succeeded. sysfs: cannot create duplicate filename '/class/chromeos/cros_ec' Call trace: sysfs_do_create_link_sd+0x94/0xdc sysfs_create_link+0x30/0x44 device_add_class_symlinks+0x90/0x13c device_add+0xf0/0x50c ec_device_probe+0x150/0x4f0 platform_probe+0xa0/0xe0 ... BUG: KASAN: invalid-access in __memcpy+0x44/0x230 Write at addr f5ffff809e2d33ac by task kworker/u32:5/125 Pointer tag: [f5], memory tag: [fe] Tainted : [W]=WARN, [O]=OOT_MODULE Hardware name: Google Navi unprovisioned 0x7FFFFFFF/sku0 board/sku3 Workqueue: events_unbound deferred_probe_work_func Call trace: __memcpy+0x44/0x230 cros_ec_check_features+0x60/0xcc [cros_ec_proto] cros_typec_probe+0xe8/0x6e0 [cros_ec_typec] platform_probe+0xa0/0xe0 Cc: stable@vger.kernel.org Fixes: 1c1d152cc5ac ("platform/chrome: cros_ec_dev - utilize new cdev_device_add helper function") Co-developed-by: Sergey Senozhatsky Signed-off-by: Sergey Senozhatsky Signed-off-by: Andrei Kuchynski Reviewed-by: Benson Leung Link: https://patch.msgid.link/20260427131721.1165078-1-akuchynski@chromium.org Signed-off-by: Lee Jones --- drivers/mfd/cros_ec_dev.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mfd/cros_ec_dev.c b/drivers/mfd/cros_ec_dev.c index 70d64b7c6243..11ee1146cf71 100644 --- a/drivers/mfd/cros_ec_dev.c +++ b/drivers/mfd/cros_ec_dev.c @@ -191,7 +191,6 @@ static int ec_device_probe(struct platform_device *pdev) if (!ec) return retval; - dev_set_drvdata(dev, ec); ec->ec_dev = dev_get_drvdata(dev->parent); ec->dev = dev; ec->cmd_offset = ec_platform->cmd_offset; @@ -233,6 +232,8 @@ static int ec_device_probe(struct platform_device *pdev) if (retval) goto failed; + dev_set_drvdata(dev, ec); + /* check whether this EC is a sensor hub. */ if (cros_ec_get_sensor_count(ec) > 0) { retval = mfd_add_hotplug_devices(ec->dev, From 1cd125db9343dde0c521562a02190088dde2bd29 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Apr 2026 09:01:10 +0200 Subject: [PATCH 29/47] mfd: qcom: Unify user-visible "Qualcomm" name Various names for Qualcomm as a company are used in user-visible config options: QCOM, Qualcomm and Qualcomm Technologies. Switch to unified "Qualcomm" so it will be easier for users to identify the options when for example running menuconfig. Signed-off-by: Krzysztof Kozlowski Acked-by: Guru Das Srinagesh Link: https://patch.msgid.link/20260427070109.18271-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Lee Jones --- drivers/mfd/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index d08d70d41bce..763ce6a34782 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -2381,7 +2381,7 @@ config MFD_ACER_A500_EC customized for the specific needs of the Acer A500 hardware. config MFD_QCOM_PM8008 - tristate "QCOM PM8008 Power Management IC" + tristate "Qualcomm PM8008 Power Management IC" depends on I2C && OF select MFD_CORE select REGMAP_I2C From b6ef1a74b3ec254f87a6a3c554fe8f8083ebd37c Mon Sep 17 00:00:00 2001 From: Charles Keepax Date: Fri, 8 May 2026 14:48:04 +0100 Subject: [PATCH 30/47] mfd: cs42l43: Sanity check firmware size Currently the code checks if a firmware was received, however it does not verify that the firmware size is larger than the firmware header. As the firmware pointer is dereferenced as a pointer to the header structure this could lead to an out of bounds memory access. Add the missing check. Fixes: ace6d1448138 ("mfd: cs42l43: Add support for cs42l43 core driver") Signed-off-by: Charles Keepax Link: https://patch.msgid.link/20260508134804.1787461-1-ckeepax@opensource.cirrus.com Signed-off-by: Lee Jones --- drivers/mfd/cs42l43.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mfd/cs42l43.c b/drivers/mfd/cs42l43.c index 166881751e69..ed6d93893de0 100644 --- a/drivers/mfd/cs42l43.c +++ b/drivers/mfd/cs42l43.c @@ -722,7 +722,7 @@ static void cs42l43_mcu_load_firmware(const struct firmware *firmware, void *con unsigned int loadaddr, val; int ret; - if (!firmware) { + if (!firmware || firmware->size < sizeof(*hdr)) { dev_err(cs42l43->dev, "Failed to load firmware\n"); cs42l43->firmware_error = -ENODEV; goto err; From 616207451dedfc064c2735966d42811259cf0a82 Mon Sep 17 00:00:00 2001 From: Louis-Alexis Eyraud Date: Wed, 29 Apr 2026 11:44:14 +0200 Subject: [PATCH 31/47] dt-bindings: mfd: mediatek: mt6397: Add rtc for MT6359 The rtc block of MT6359 PMIC is compatible with the one found in MT6358 but this compatibility was never expressed in the dt-bindings, so add the missing compatible string for the rtc subnode. Signed-off-by: Louis-Alexis Eyraud Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260429-mediatek-genio-mt6365-cleanup-v1-1-6f43838be92f@collabora.com Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml index 05c121b0cb3d..dc2b38cf285d 100644 --- a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml @@ -70,6 +70,7 @@ properties: - mediatek,mt6397-rtc - items: - enum: + - mediatek,mt6359-rtc - mediatek,mt6366-rtc - const: mediatek,mt6358-rtc From 078ca283be013d9179981221b2242d049e4b2aa5 Mon Sep 17 00:00:00 2001 From: Louis-Alexis Eyraud Date: Wed, 29 Apr 2026 11:44:15 +0200 Subject: [PATCH 32/47] dt-bindings: mfd: mediatek: mt6397: Add MT6365 PMIC support MT6365 PMIC is compatible with MT6359, so add the compatible strings for the main and sub devices (regulator, rtc, audio codec). Signed-off-by: Louis-Alexis Eyraud Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260429-mediatek-genio-mt6365-cleanup-v1-2-6f43838be92f@collabora.com Signed-off-by: Lee Jones --- .../devicetree/bindings/mfd/mediatek,mt6397.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml index dc2b38cf285d..122aba7a54f8 100644 --- a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml @@ -44,6 +44,10 @@ properties: - enum: - mediatek,mt6366 - const: mediatek,mt6358 + - items: + - enum: + - mediatek,mt6365 + - const: mediatek,mt6359 interrupts: maxItems: 1 @@ -71,6 +75,7 @@ properties: - items: - enum: - mediatek,mt6359-rtc + - mediatek,mt6365-rtc - mediatek,mt6366-rtc - const: mediatek,mt6358-rtc @@ -99,6 +104,10 @@ properties: - enum: - mediatek,mt6366-regulator - const: mediatek,mt6358-regulator + - items: + - enum: + - mediatek,mt6365-regulator + - const: mediatek,mt6359-regulator required: - compatible @@ -125,6 +134,10 @@ properties: - enum: - mediatek,mt6366-sound - const: mediatek,mt6358-sound + - items: + - enum: + - mediatek,mt6365-codec + - const: mediatek,mt6359-codec required: - compatible From 7502c035b884b73f51669cada3f4022cd11e8f5c Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 14 May 2026 17:15:14 +0800 Subject: [PATCH 33/47] mfd: dt-bindings: mt6397: Add regulator supplies On the MT6397 family each buck regulator has a separate supply. LDOs are split into various groups with independent supplies. There is also a supply for the regulator control logic. Add descriptions for all of the supplies for the MT6359. Signed-off-by: Chen-Yu Tsai Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260514091520.2718987-2-wenst@chromium.org Signed-off-by: Lee Jones --- .../bindings/mfd/mediatek,mt6397.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml index 122aba7a54f8..3cbc0dc12c31 100644 --- a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml @@ -239,12 +239,62 @@ properties: description: Pin controller + vsys-smps-supply: + description: Supply for regulator control logic + +patternProperties: + "^vsys-v[a-z]+[0-9]*-supply$": + description: Supplies for PMIC buck regulators + "^vs(ys|[12])-ldo[1-9]-supply$": + description: Supplies for PMIC LDO regulators + required: - compatible - regulators additionalProperties: false +allOf: + - if: + properties: + "compatible": + contains: + const: mediatek,mt6359 + then: + properties: + vsys-ldo1-supply: + description: Supply for LDOs vcn33_[12], vio28, vfe28, vibr + vsys-ldo2-supply: + description: Supply for LDOs vaux18, vbif28, vxo22, vrfck, vrfck_1, + vemc, vsim1, vsim2, vusb + vsys-vcore-supply: + description: Supply for buck regulator vcore + vsys-vgpu11-supply: + description: Supply for buck regulator vgpu11 + vsys-vmodem-supply: + description: Supply for buck regulator vmodem + vsys-vpa-supply: + description: Supply for buck regulator vpa + vsys-vproc1-supply: + description: Supply for buck regulator vproc1 + vsys-vproc2-supply: + description: Supply for buck regulator vproc2 + vsys-vpu-supply: + description: Supply for buck regulator vpu + vsys-vs1-supply: + description: Supply for buck regulator vs1 + vsys-vs2-supply: + description: Supply for buck regulator vs2 + vs1-ldo1-supply: + description: Supply for LDOs vaud18, vcamio, vm18, vufs + vs1-ldo2-supply: + description: Supply for LDOs vcn18, vefuse, vio18, vrf18 + vs2-ldo1-supply: + description: + Supply for LDOs vsram_proc1, vsram_proc2, vsram_others, vsram_md + vs2-ldo2-supply: + description: Supply for LDOs va09, va12, vcn13, vrf12 + examples: - | #include From f01e402bebf8a2f3843990b209b3f50cf536dbf8 Mon Sep 17 00:00:00 2001 From: Diogo Ivo Date: Thu, 14 May 2026 16:47:20 +0200 Subject: [PATCH 34/47] mfd: max77620: Convert poweroff support to sys-off API Convert max77620_pm_power_off() to the sys-off callback prototype and register it with the sys-off API when the device tree marks the PMIC as a system power controller. This also removes the global max77620_scratch pointer by passing the chip instance through the callback data. This modernizes the driver's poweroff handling and aligns it with the kernel sys-off infrastructure. Signed-off-by: Diogo Ivo Link: https://patch.msgid.link/20260514-smaug-poweroff-v1-2-30f9a4688966@tecnico.ulisboa.pt Signed-off-by: Lee Jones --- drivers/mfd/max77620.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/drivers/mfd/max77620.c b/drivers/mfd/max77620.c index 3af2974b3023..c4f89a9681f3 100644 --- a/drivers/mfd/max77620.c +++ b/drivers/mfd/max77620.c @@ -31,11 +31,10 @@ #include #include #include +#include #include #include -static struct max77620_chip *max77620_scratch; - static const struct resource gpio_resources[] = { DEFINE_RES_IRQ(MAX77620_IRQ_TOP_GPIO), }; @@ -484,13 +483,15 @@ static int max77620_read_es_version(struct max77620_chip *chip) return ret; } -static void max77620_pm_power_off(void) +static int max77620_pm_power_off(struct sys_off_data *data) { - struct max77620_chip *chip = max77620_scratch; + struct max77620_chip *chip = data->cb_data; regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1, MAX77620_ONOFFCNFG1_SFT_RST, MAX77620_ONOFFCNFG1_SFT_RST); + + return NOTIFY_DONE; } static int max77620_probe(struct i2c_client *client) @@ -501,7 +502,6 @@ static int max77620_probe(struct i2c_client *client) struct regmap_irq_chip *chip_desc; const struct mfd_cell *mfd_cells; int n_mfd_cells; - bool pm_off; int ret; chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); @@ -573,10 +573,14 @@ static int max77620_probe(struct i2c_client *client) return ret; } - pm_off = of_device_is_system_power_controller(client->dev.of_node); - if (pm_off && !pm_power_off) { - max77620_scratch = chip; - pm_power_off = max77620_pm_power_off; + if (of_device_is_system_power_controller(client->dev.of_node)) { + ret = devm_register_sys_off_handler(&client->dev, + SYS_OFF_MODE_POWER_OFF, + SYS_OFF_PRIO_DEFAULT, + max77620_pm_power_off, chip); + if (ret) + return dev_err_probe(&client->dev, ret, + "failed to register power-off handler\n"); } return 0; From a44ec8fd3839434c0c85ae68106a94081a31341f Mon Sep 17 00:00:00 2001 From: Md Shofiqul Islam Date: Thu, 14 May 2026 21:19:54 +0300 Subject: [PATCH 35/47] mfd: si476x-i2c: Fix spelling mistakes in comments Fix spelling mistake in comments: - succes -> success (4 times) Signed-off-by: Md Shofiqul Islam Link: https://patch.msgid.link/20260514181954.1442-1-shofiqtest@gmail.com Signed-off-by: Lee Jones --- drivers/mfd/si476x-i2c.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/mfd/si476x-i2c.c b/drivers/mfd/si476x-i2c.c index 899c0b5ea3aa..7ddc97dfc940 100644 --- a/drivers/mfd/si476x-i2c.c +++ b/drivers/mfd/si476x-i2c.c @@ -30,7 +30,7 @@ * * Configure the functions of the pins of the radio chip. * - * The function returns zero in case of succes or negative error code + * The function returns zero in case of success or negative error code * otherwise. */ static int si476x_core_config_pinmux(struct si476x_core *core) @@ -121,7 +121,7 @@ static inline void si476x_core_schedule_polling_work(struct si476x_core *core) * 4. Configures, pin multiplexor, disables digital audio and * configures interrupt sources. * - * The function returns zero in case of succes or negative error code + * The function returns zero in case of success or negative error code * otherwise. */ int si476x_core_start(struct si476x_core *core, bool soft) @@ -215,7 +215,7 @@ EXPORT_SYMBOL_GPL(si476x_core_start); * 2. Send the POWER_DOWN command if the power down is soft or bring * reset line low if not. * - * The function returns zero in case of succes or negative error code + * The function returns zero in case of success or negative error code * otherwise. */ int si476x_core_stop(struct si476x_core *core, bool soft) @@ -428,7 +428,7 @@ static void si476x_core_pronounce_dead(struct si476x_core *core) * of I/O errors. If the error counter rises above the threshold * pronounce device dead. * - * The function returns zero on succes or negative error code on + * The function returns zero on success or negative error code on * failure. */ int si476x_core_i2c_xfer(struct si476x_core *core, From 6b6e7e965a11f761a3b614f5ff3fa8d1d9c86b1e Mon Sep 17 00:00:00 2001 From: Antony Kurniawan Soemardi Date: Thu, 14 May 2026 21:08:32 +0700 Subject: [PATCH 36/47] mfd: qcom_rpm: Add msm8960 QDSS clock resource The msm8960 RPM resource table is missing the QDSS clock entry (resource ID 209) that is present in the android-msm-mako-3.4 downstream kernel. Add it so that RPM clock initialization succeeds. Tested-by: Rudraksha Gupta Signed-off-by: Antony Kurniawan Soemardi Link: https://patch.msgid.link/20260514-msm8960-wifi-v2-3-7cbae45dab5e@smankusors.com Signed-off-by: Lee Jones --- drivers/mfd/qcom_rpm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mfd/qcom_rpm.c b/drivers/mfd/qcom_rpm.c index 27446f43e3f3..0defb3279af1 100644 --- a/drivers/mfd/qcom_rpm.c +++ b/drivers/mfd/qcom_rpm.c @@ -324,6 +324,7 @@ static const struct qcom_rpm_resource msm8960_rpm_resource_table[] = { [QCOM_RPM_USB_OTG_SWITCH] = { 205, 119, 82, 1 }, [QCOM_RPM_HDMI_SWITCH] = { 206, 120, 83, 1 }, [QCOM_RPM_DDR_DMM] = { 207, 121, 84, 2 }, + [QCOM_RPM_QDSS_CLK] = { 209, ~0, 7, 1 }, }; static const struct qcom_rpm_data msm8960_template = { From 45a1d5f19684ab928b8375c30895b4cc8de937d3 Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Mon, 11 May 2026 16:28:21 +0530 Subject: [PATCH 37/47] dt-bindings: mfd: qcom,tcsr: Document the IPQ5210 TCSR block Document the TCSR block found on the Qualcomm's IPQ5210 SoC. Signed-off-by: Kathiravan Thirumoorthy Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260511-ipq5210_tcsr_binding-v1-1-c8d20fed014f@oss.qualcomm.com Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml index 23317d1b381c..7dd2fe035e6d 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml @@ -43,6 +43,7 @@ properties: - qcom,tcsr-apq8064 - qcom,tcsr-apq8084 - qcom,tcsr-ipq5018 + - qcom,tcsr-ipq5210 - qcom,tcsr-ipq5332 - qcom,tcsr-ipq5424 - qcom,tcsr-ipq6018 From 7aa3d8aba56ef337a2450385a29e074848ab0fa0 Mon Sep 17 00:00:00 2001 From: Ethan Nelson-Moore Date: Sat, 16 May 2026 19:37:21 -0700 Subject: [PATCH 38/47] mfd: twl4030-power: Update checks for specific boards to use the DT The twl4030-power driver contains two checks for ARM machine IDs via machine_is_*() macros. The two boards concerned now support only FDT booting, which does not use machine IDs, and therefore the code should be updated to check the DT compatible property instead. The legacy board files for these machines were removed in commit 1b383f44aabc ("ARM: OMAP2+: Drop board file for 3430sdp") and commit e92fc4f04a34 ("ARM: OMAP2+: Drop legacy board file for LDP"). The presence of these machine ID checks prevents the removal of machine IDs no longer used by the kernel from arch/arm/tools/mach-types, because the machine_is_*() macros are generated from mach-types. To resolve this issue, use of_machine_is_compatible() instead. Signed-off-by: Ethan Nelson-Moore Link: https://patch.msgid.link/20260517023723.92731-2-enelsonmoore@gmail.com Signed-off-by: Lee Jones --- drivers/mfd/twl4030-power.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/mfd/twl4030-power.c b/drivers/mfd/twl4030-power.c index 0bca948ab6ba..fc1cf316c236 100644 --- a/drivers/mfd/twl4030-power.c +++ b/drivers/mfd/twl4030-power.c @@ -30,8 +30,6 @@ #include #include -#include - static u8 twl4030_start_script_address = 0x2b; /* Register bits for P1, P2 and P3_SW_EVENTS */ @@ -294,8 +292,8 @@ twl4030_config_wakeup12_sequence(const struct twl4030_power_data *pdata, if (err) goto out; - if (pdata->ac_charger_quirk || machine_is_omap_3430sdp() || - machine_is_omap_ldp()) { + if (pdata->ac_charger_quirk || of_machine_is_compatible("ti,omap3430-sdp") || + of_machine_is_compatible("ti,omap3-ldp")) { /* Disabling AC charger effect on sleep-active transitions */ err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data, R_CFG_P1_TRANSITION); From 28ad23ef7f58abc8715e6f6c4255921da98e6acc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Otto=20Pfl=C3=BCger?= Date: Tue, 19 May 2026 14:06:12 +0200 Subject: [PATCH 39/47] dt-bindings: mfd: sprd,sc2731: Include SC2730 regulator bindings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SC2730 PMIC provides a different set of regulators than SC2731 and thus requires separate regulator bindings. Allow using them for the "regulators" node. Signed-off-by: Otto Pflüger Acked-by: Conor Dooley Link: https://patch.msgid.link/20260519-sc2730-regulators-v3-2-5bf0e02507e3@abscue.de Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/sprd,sc2731.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/sprd,sc2731.yaml b/Documentation/devicetree/bindings/mfd/sprd,sc2731.yaml index b023e1ef8d3c..e74ec4970994 100644 --- a/Documentation/devicetree/bindings/mfd/sprd,sc2731.yaml +++ b/Documentation/devicetree/bindings/mfd/sprd,sc2731.yaml @@ -54,7 +54,9 @@ properties: regulators: type: object - $ref: /schemas/regulator/sprd,sc2731-regulator.yaml# + oneOf: + - $ref: /schemas/regulator/sprd,sc2730-regulator.yaml# + - $ref: /schemas/regulator/sprd,sc2731-regulator.yaml# patternProperties: "^adc@[0-9a-f]+$": From 3001ed2b4e06da2276c42ace6551617065a5b1f9 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 21 May 2026 10:36:24 +0200 Subject: [PATCH 40/47] mfd: tps6586x: Fix OF node refcount Platform devices created with platform_device_alloc() call platform_device_release() when the last reference to the device's kobject is dropped. This function calls of_node_put() unconditionally. This works fine for devices created with platform_device_register_full() but users of the split approach (platform_device_alloc() + platform_device_add()) must bump the reference of the of_node they assign manually. Add the missing call to of_node_get(). Cc: stable@vger.kernel.org Fixes: 62f6b0879304 ("tps6586x: Add device tree support") Signed-off-by: Bartosz Golaszewski Link: https://patch.msgid.link/20260521-pdev-fwnode-ref-v1-1-88c324a1b8d2@oss.qualcomm.com Signed-off-by: Lee Jones --- drivers/mfd/tps6586x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mfd/tps6586x.c b/drivers/mfd/tps6586x.c index 8d5fe2b60bfa..f5f805446603 100644 --- a/drivers/mfd/tps6586x.c +++ b/drivers/mfd/tps6586x.c @@ -397,7 +397,7 @@ static int tps6586x_add_subdevs(struct tps6586x *tps6586x, pdev->dev.parent = tps6586x->dev; pdev->dev.platform_data = subdev->platform_data; - pdev->dev.of_node = subdev->of_node; + pdev->dev.of_node = of_node_get(subdev->of_node); ret = platform_device_add(pdev); if (ret) { From 960b38750b17ed24d8f8de06e3c066c20d2167f9 Mon Sep 17 00:00:00 2001 From: Billy Tsai Date: Thu, 21 May 2026 17:17:44 +0800 Subject: [PATCH 41/47] dt-bindings: mfd: aspeed,ast2x00-scu: Support AST2700 SoC1 pinctrl The AST2700 SoC integrates two interconnected SoC instances, each managed by its own System Control Unit (SCU). Allow the AST2700 SoC1 pin controller to be described as a child node of the SCU by extending the compatible strings accepted by the SCU binding. There is no functional change to the SCU binding beyond permitting the aspeed,ast2700-soc1-pinctrl compatible string. Signed-off-by: Billy Tsai Acked-by: Conor Dooley Reviewed-by: Linus Walleij Link: https://patch.msgid.link/20260521-pinctrl-single-bit-v5-1-308be2c160fc@aspeedtech.com Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml index 0d5e168b0309..948ba92ef49b 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml +++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml @@ -100,6 +100,7 @@ patternProperties: - aspeed,ast2500-pinctrl - aspeed,ast2600-pinctrl - aspeed,ast2700-soc0-pinctrl + - aspeed,ast2700-soc1-pinctrl required: - compatible From ed1a370da26369a26b25901685e620c12040a471 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Wed, 27 May 2026 17:56:03 +0300 Subject: [PATCH 42/47] mfd: rz-mtu3: Use device-managed APIs Replace devm_reset_control_get_exclusive() and the manual reset_control_deassert()/reset_control_assert() with handling by devm_reset_control_get_exclusive_deasserted(). Replace mfd_add_devices()/mfd_remove_devices() with devm_mfd_add_devices(). Remove the custom cleanup action. Signed-off-by: Cosmin Tanislav Link: https://patch.msgid.link/20260527145606.136536-2-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Lee Jones --- drivers/mfd/rz-mtu3.c | 26 +++----------------------- 1 file changed, 3 insertions(+), 23 deletions(-) diff --git a/drivers/mfd/rz-mtu3.c b/drivers/mfd/rz-mtu3.c index 9cdfef610398..6f6ed32e7592 100644 --- a/drivers/mfd/rz-mtu3.c +++ b/drivers/mfd/rz-mtu3.c @@ -301,15 +301,6 @@ void rz_mtu3_disable(struct rz_mtu3_channel *ch) } EXPORT_SYMBOL_GPL(rz_mtu3_disable); -static void rz_mtu3_reset_assert(void *data) -{ - struct rz_mtu3 *mtu = dev_get_drvdata(data); - struct rz_mtu3_priv *priv = mtu->priv_data; - - mfd_remove_devices(data); - reset_control_assert(priv->rstc); -} - static const struct mfd_cell rz_mtu3_devs[] = { { .name = "rz-mtu3-counter", @@ -324,7 +315,6 @@ static int rz_mtu3_probe(struct platform_device *pdev) struct rz_mtu3_priv *priv; struct rz_mtu3 *ddata; unsigned int i; - int ret; ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); if (!ddata) @@ -340,7 +330,7 @@ static int rz_mtu3_probe(struct platform_device *pdev) if (IS_ERR(priv->mmio)) return PTR_ERR(priv->mmio); - priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); + priv->rstc = devm_reset_control_get_exclusive_deasserted(&pdev->dev, NULL); if (IS_ERR(priv->rstc)) return PTR_ERR(priv->rstc); @@ -348,7 +338,6 @@ static int rz_mtu3_probe(struct platform_device *pdev) if (IS_ERR(ddata->clk)) return PTR_ERR(ddata->clk); - reset_control_deassert(priv->rstc); spin_lock_init(&priv->lock); platform_set_drvdata(pdev, ddata); @@ -358,17 +347,8 @@ static int rz_mtu3_probe(struct platform_device *pdev) mutex_init(&ddata->channels[i].lock); } - ret = mfd_add_devices(&pdev->dev, 0, rz_mtu3_devs, - ARRAY_SIZE(rz_mtu3_devs), NULL, 0, NULL); - if (ret < 0) - goto err_assert; - - return devm_add_action_or_reset(&pdev->dev, rz_mtu3_reset_assert, - &pdev->dev); - -err_assert: - reset_control_assert(priv->rstc); - return ret; + return devm_mfd_add_devices(&pdev->dev, 0, rz_mtu3_devs, + ARRAY_SIZE(rz_mtu3_devs), NULL, 0, NULL); } static const struct of_device_id rz_mtu3_of_match[] = { From 4bf15cafe9588d0c303143b4c64c7bfc7b1a3a5d Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Wed, 27 May 2026 17:56:04 +0300 Subject: [PATCH 43/47] mfd: rz-mtu3: Use local variable for reset Remove struct rz_mtu3_priv::rstc and use a local variable for it as it is not needed outside of rz_mtu3_probe() anymore. Signed-off-by: Cosmin Tanislav Link: https://patch.msgid.link/20260527145606.136536-3-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Lee Jones --- drivers/mfd/rz-mtu3.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/mfd/rz-mtu3.c b/drivers/mfd/rz-mtu3.c index 6f6ed32e7592..8122355e0e29 100644 --- a/drivers/mfd/rz-mtu3.c +++ b/drivers/mfd/rz-mtu3.c @@ -21,7 +21,6 @@ struct rz_mtu3_priv { void __iomem *mmio; - struct reset_control *rstc; spinlock_t lock; }; @@ -314,6 +313,7 @@ static int rz_mtu3_probe(struct platform_device *pdev) { struct rz_mtu3_priv *priv; struct rz_mtu3 *ddata; + struct reset_control *rstc; unsigned int i; ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); @@ -330,9 +330,9 @@ static int rz_mtu3_probe(struct platform_device *pdev) if (IS_ERR(priv->mmio)) return PTR_ERR(priv->mmio); - priv->rstc = devm_reset_control_get_exclusive_deasserted(&pdev->dev, NULL); - if (IS_ERR(priv->rstc)) - return PTR_ERR(priv->rstc); + rstc = devm_reset_control_get_exclusive_deasserted(&pdev->dev, NULL); + if (IS_ERR(rstc)) + return PTR_ERR(rstc); ddata->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(ddata->clk)) From a3bd9f3dd5c88c621e4bc4ecd5f2ae9c277f558a Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Wed, 27 May 2026 17:56:05 +0300 Subject: [PATCH 44/47] mfd: rz-mtu3: Store &pdev->dev in local variable &pdev->dev is accessed multiple times during probe. Store it in a local variable and use that to simplify the code. Signed-off-by: Cosmin Tanislav Link: https://patch.msgid.link/20260527145606.136536-4-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Lee Jones --- drivers/mfd/rz-mtu3.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/mfd/rz-mtu3.c b/drivers/mfd/rz-mtu3.c index 8122355e0e29..f64c748d6ce4 100644 --- a/drivers/mfd/rz-mtu3.c +++ b/drivers/mfd/rz-mtu3.c @@ -311,16 +311,17 @@ static const struct mfd_cell rz_mtu3_devs[] = { static int rz_mtu3_probe(struct platform_device *pdev) { + struct device *dev = &pdev->dev; struct rz_mtu3_priv *priv; struct rz_mtu3 *ddata; struct reset_control *rstc; unsigned int i; - ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); + ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL); if (!ddata) return -ENOMEM; - ddata->priv_data = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + ddata->priv_data = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!ddata->priv_data) return -ENOMEM; @@ -330,11 +331,11 @@ static int rz_mtu3_probe(struct platform_device *pdev) if (IS_ERR(priv->mmio)) return PTR_ERR(priv->mmio); - rstc = devm_reset_control_get_exclusive_deasserted(&pdev->dev, NULL); + rstc = devm_reset_control_get_exclusive_deasserted(dev, NULL); if (IS_ERR(rstc)) return PTR_ERR(rstc); - ddata->clk = devm_clk_get(&pdev->dev, NULL); + ddata->clk = devm_clk_get(dev, NULL); if (IS_ERR(ddata->clk)) return PTR_ERR(ddata->clk); @@ -347,7 +348,7 @@ static int rz_mtu3_probe(struct platform_device *pdev) mutex_init(&ddata->channels[i].lock); } - return devm_mfd_add_devices(&pdev->dev, 0, rz_mtu3_devs, + return devm_mfd_add_devices(dev, 0, rz_mtu3_devs, ARRAY_SIZE(rz_mtu3_devs), NULL, 0, NULL); } From f6b692d1f466ba3837ae9478e0d5ce6ef77697b4 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Wed, 27 May 2026 17:56:06 +0300 Subject: [PATCH 45/47] mfd: rz-mtu3: Make reset optional The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs do not have a reset line for the MTU3 block. Prepare for them by making it optional. Signed-off-by: Cosmin Tanislav Link: https://patch.msgid.link/20260527145606.136536-5-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Lee Jones --- drivers/mfd/rz-mtu3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mfd/rz-mtu3.c b/drivers/mfd/rz-mtu3.c index f64c748d6ce4..3fa7dfe71386 100644 --- a/drivers/mfd/rz-mtu3.c +++ b/drivers/mfd/rz-mtu3.c @@ -331,7 +331,7 @@ static int rz_mtu3_probe(struct platform_device *pdev) if (IS_ERR(priv->mmio)) return PTR_ERR(priv->mmio); - rstc = devm_reset_control_get_exclusive_deasserted(dev, NULL); + rstc = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL); if (IS_ERR(rstc)) return PTR_ERR(rstc); From f167dc91aeed1928292e65a03d6472d3d01711fb Mon Sep 17 00:00:00 2001 From: Manish Baing Date: Sat, 23 May 2026 17:32:50 +0000 Subject: [PATCH 46/47] dt-bindings: mfd: st,stmpe: Add missing properties for PWM subnode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The st,stmpe-pwm binding is already covered by the MFD schema in Documentation/devicetree/bindings/mfd/st,stmpe.yaml. However, the PWM subnode was missing a 'required' properties block. This allowed Device Tree nodes to pass validation even if the 'compatible' string was omitted. This omission could lead to probe failures at runtime. Fix the schema by adding the missing 'required' block. Signed-off-by: Manish Baing Acked-by: Conor Dooley Acked-by: Uwe Kleine-König Reviewed-by: Linus Walleij Link: https://patch.msgid.link/20260523173251.72540-2-manishbaing2789@gmail.com Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/st,stmpe.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/st,stmpe.yaml b/Documentation/devicetree/bindings/mfd/st,stmpe.yaml index df43878fbe18..4bb05d544901 100644 --- a/Documentation/devicetree/bindings/mfd/st,stmpe.yaml +++ b/Documentation/devicetree/bindings/mfd/st,stmpe.yaml @@ -127,6 +127,10 @@ properties: "#pwm-cells": const: 2 + required: + - compatible + - "#pwm-cells" + touchscreen: type: object $ref: /schemas/input/touchscreen/touchscreen.yaml# From c454531af72e0df811600601413bb8d3d039ed08 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 8 Jun 2026 13:55:08 +0200 Subject: [PATCH 47/47] dt-bindings: mfd: syscon: Revert renesas,r9a08g046-lvds-cmn Revert commit 51284d8b1dbc ("dt-bindings: mfd: syscon: Document the LVDS_CMN syscon for the RZ/G3L") because it is completely not matching reality and clearly incorrect in respect of renesas,r9a08g046-lvds-cmn. It wasn't ever build-tested by author on their DTS, either. The documented renesas,r9a08g046-lvds-cmn compatible clearly disallows any children and simple-mfd fallback, however its only use in original patchset is with simple-mfd and children, so this could have never worked. Fixes: 51284d8b1dbc ("dt-bindings: mfd: syscon: Document the LVDS_CMN syscon for the RZ/G3L") Signed-off-by: Krzysztof Kozlowski Acked-by: Biju Das Link: https://patch.msgid.link/20260608115507.134969-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 9c81010d5a74..e22867088063 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -221,7 +221,6 @@ properties: - nxp,s32g3-gpr - qcom,apq8064-mmss-sfpb - qcom,apq8064-sps-sic - - renesas,r9a08g046-lvds-cmn - rockchip,px30-qos - rockchip,rk3036-qos - rockchip,rk3066-qos