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synced 2026-05-17 01:23:58 -04:00
drm/xe: Include running dword offset in default_lrc dumps
Printing a running dword offset in the default_lrc_* debugfs entries makes it easier for developers to find the right offsets to use in regs/xe_lrc_layout.h and/or compare the default LRC contents against the bspec-documented LRC layout. Reviewed-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Link: https://patch.msgid.link/20260311-default_lrc_offsets-v1-1-58d8ed3aa081@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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@@ -1902,6 +1902,7 @@ static int instr_dw(u32 cmd_header)
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static int dump_mi_command(struct drm_printer *p,
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struct xe_gt *gt,
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u32 *start,
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u32 *dw,
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int remaining_dw)
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{
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@@ -1917,15 +1918,18 @@ static int dump_mi_command(struct drm_printer *p,
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while (num_noop < remaining_dw &&
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(*(++dw) & REG_GENMASK(31, 23)) == MI_NOOP)
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num_noop++;
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drm_printf(p, "[%#010x] MI_NOOP (%d dwords)\n", inst_header, num_noop);
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drm_printf(p, "LRC[%#5lx] = [%#010x] MI_NOOP (%d dwords)\n",
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dw - num_noop - start, inst_header, num_noop);
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return num_noop;
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case MI_TOPOLOGY_FILTER:
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drm_printf(p, "[%#010x] MI_TOPOLOGY_FILTER\n", inst_header);
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drm_printf(p, "LRC[%#5lx] = [%#010x] MI_TOPOLOGY_FILTER\n",
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dw - start, inst_header);
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return 1;
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case MI_BATCH_BUFFER_END:
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drm_printf(p, "[%#010x] MI_BATCH_BUFFER_END\n", inst_header);
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drm_printf(p, "LRC[%#5lx] = [%#010x] MI_BATCH_BUFFER_END\n",
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dw - start, inst_header);
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/* Return 'remaining_dw' to consume the rest of the LRC */
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return remaining_dw;
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}
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@@ -1939,39 +1943,43 @@ static int dump_mi_command(struct drm_printer *p,
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switch (inst_header & MI_OPCODE) {
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case MI_LOAD_REGISTER_IMM:
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drm_printf(p, "[%#010x] MI_LOAD_REGISTER_IMM: %d regs\n",
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inst_header, (numdw - 1) / 2);
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drm_printf(p, "LRC[%#5lx] = [%#010x] MI_LOAD_REGISTER_IMM: %d regs\n",
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dw - start, inst_header, (numdw - 1) / 2);
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for (int i = 1; i < numdw; i += 2)
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drm_printf(p, " - %#6x = %#010x\n", dw[i], dw[i + 1]);
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drm_printf(p, "LRC[%#5lx] = - %#6x = %#010x\n",
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&dw[i] - start, dw[i], dw[i + 1]);
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return numdw;
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case MI_LOAD_REGISTER_MEM & MI_OPCODE:
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drm_printf(p, "[%#010x] MI_LOAD_REGISTER_MEM: %s%s\n",
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inst_header,
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drm_printf(p, "LRC[%#5lx] = [%#010x] MI_LOAD_REGISTER_MEM: %s%s\n",
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dw - start, inst_header,
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dw[0] & MI_LRI_LRM_CS_MMIO ? "CS_MMIO " : "",
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dw[0] & MI_LRM_USE_GGTT ? "USE_GGTT " : "");
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if (numdw == 4)
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drm_printf(p, " - %#6x = %#010llx\n",
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drm_printf(p, "LRC[%#5lx] = - %#6x = %#010llx\n",
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dw - start,
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dw[1], ((u64)(dw[3]) << 32 | (u64)(dw[2])));
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else
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drm_printf(p, " - %*ph (%s)\n",
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(int)sizeof(u32) * (numdw - 1), dw + 1,
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numdw < 4 ? "truncated" : "malformed");
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drm_printf(p, "LRC[%#5lx] = - %*ph (%s)\n",
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dw - start, (int)sizeof(u32) * (numdw - 1),
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dw + 1, numdw < 4 ? "truncated" : "malformed");
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return numdw;
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case MI_FORCE_WAKEUP:
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drm_printf(p, "[%#010x] MI_FORCE_WAKEUP\n", inst_header);
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drm_printf(p, "LRC[%#5lx] = [%#010x] MI_FORCE_WAKEUP\n",
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dw - start, inst_header);
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return numdw;
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default:
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drm_printf(p, "[%#010x] unknown MI opcode %#x, likely %d dwords\n",
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inst_header, opcode, numdw);
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drm_printf(p, "LRC[%#5lx] = [%#010x] unknown MI opcode %#x, likely %d dwords\n",
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dw - start, inst_header, opcode, numdw);
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return numdw;
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}
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}
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static int dump_gfxpipe_command(struct drm_printer *p,
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struct xe_gt *gt,
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u32 *start,
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u32 *dw,
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int remaining_dw)
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{
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@@ -1990,11 +1998,13 @@ static int dump_gfxpipe_command(struct drm_printer *p,
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switch (*dw & GFXPIPE_MATCH_MASK) {
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#define MATCH(cmd) \
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case cmd: \
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drm_printf(p, "[%#010x] " #cmd " (%d dwords)\n", *dw, numdw); \
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drm_printf(p, "LRC[%#5lx] = [%#010x] " #cmd " (%d dwords)\n", \
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dw - start, *dw, numdw); \
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return numdw
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#define MATCH3D(cmd) \
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case CMD_##cmd: \
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drm_printf(p, "[%#010x] " #cmd " (%d dwords)\n", *dw, numdw); \
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drm_printf(p, "LRC[%#5lx] = [%#010x] " #cmd " (%d dwords)\n", \
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dw - start, *dw, numdw); \
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return numdw
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MATCH(STATE_BASE_ADDRESS);
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@@ -2126,14 +2136,15 @@ static int dump_gfxpipe_command(struct drm_printer *p,
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MATCH3D(3DSTATE_SLICE_TABLE_STATE_POINTER_2);
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default:
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drm_printf(p, "[%#010x] unknown GFXPIPE command (pipeline=%#x, opcode=%#x, subopcode=%#x), likely %d dwords\n",
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*dw, pipeline, opcode, subopcode, numdw);
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drm_printf(p, "LRC[%#5lx] = [%#010x] unknown GFXPIPE command (pipeline=%#x, opcode=%#x, subopcode=%#x), likely %d dwords\n",
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dw - start, *dw, pipeline, opcode, subopcode, numdw);
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return numdw;
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}
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}
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static int dump_gfx_state_command(struct drm_printer *p,
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struct xe_gt *gt,
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u32 *start,
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u32 *dw,
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int remaining_dw)
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{
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@@ -2151,8 +2162,8 @@ static int dump_gfx_state_command(struct drm_printer *p,
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MATCH(STATE_WRITE_INLINE);
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default:
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drm_printf(p, "[%#010x] unknown GFX_STATE command (opcode=%#x), likely %d dwords\n",
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*dw, opcode, numdw);
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drm_printf(p, "LRC[%#5lx] = [%#010x] unknown GFX_STATE command (opcode=%#x), likely %d dwords\n",
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dw - start, *dw, opcode, numdw);
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return numdw;
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}
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}
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@@ -2161,7 +2172,7 @@ void xe_lrc_dump_default(struct drm_printer *p,
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struct xe_gt *gt,
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enum xe_engine_class hwe_class)
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{
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u32 *dw;
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u32 *dw, *start;
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int remaining_dw, num_dw;
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if (!gt->default_lrc[hwe_class]) {
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@@ -2174,18 +2185,20 @@ void xe_lrc_dump_default(struct drm_printer *p,
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* hardware status page.
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*/
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dw = gt->default_lrc[hwe_class] + LRC_PPHWSP_SIZE;
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start = dw;
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remaining_dw = (xe_gt_lrc_size(gt, hwe_class) - LRC_PPHWSP_SIZE) / 4;
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while (remaining_dw > 0) {
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if ((*dw & XE_INSTR_CMD_TYPE) == XE_INSTR_MI) {
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num_dw = dump_mi_command(p, gt, dw, remaining_dw);
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num_dw = dump_mi_command(p, gt, start, dw, remaining_dw);
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} else if ((*dw & XE_INSTR_CMD_TYPE) == XE_INSTR_GFXPIPE) {
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num_dw = dump_gfxpipe_command(p, gt, dw, remaining_dw);
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num_dw = dump_gfxpipe_command(p, gt, start, dw, remaining_dw);
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} else if ((*dw & XE_INSTR_CMD_TYPE) == XE_INSTR_GFX_STATE) {
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num_dw = dump_gfx_state_command(p, gt, dw, remaining_dw);
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num_dw = dump_gfx_state_command(p, gt, start, dw, remaining_dw);
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} else {
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num_dw = min(instr_dw(*dw), remaining_dw);
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drm_printf(p, "[%#10x] Unknown instruction of type %#x, likely %d dwords\n",
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drm_printf(p, "LRC[%#5lx] = [%#10x] Unknown instruction of type %#x, likely %d dwords\n",
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dw - start,
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*dw, REG_FIELD_GET(XE_INSTR_CMD_TYPE, *dw),
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num_dw);
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}
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