From 2f81137f034765078399354ef6e9659259a77ae2 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Sun, 16 Oct 2016 23:59:16 +0900 Subject: [PATCH 1/5] arm64: dts: uniphier: switch over to PSCI enable method At the first system bring-up, I chose to use spin-table because ARM Trusted Firmware was not ready for this platform at that moment. Actually, these SoCs are equipped with EL3 and able to provide PSCI. Now I finished porting the ATF BL31 for the UniPhier platform, so it is ready to migrate to PSCI enable method. Signed-off-by: Masahiro Yamada --- .../boot/dts/socionext/uniphier-ld11.dtsi | 13 ++++++++----- .../boot/dts/socionext/uniphier-ld20.dtsi | 19 ++++++++++--------- 2 files changed, 18 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi index 3eb4c42ce7b9..17bc4b359912 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi @@ -43,7 +43,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */ +/memreserve/ 0x80000000 0x00080000; / { compatible = "socionext,uniphier-ld11"; @@ -70,19 +70,22 @@ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x000>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x80000000>; + enable-method = "psci"; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x001>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x80000000>; + enable-method = "psci"; }; }; + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + clocks { refclk: ref { compatible = "fixed-clock"; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index 56a1b2e92cf3..c8ebe7e52809 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -43,7 +43,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */ +/memreserve/ 0x80000000 0x00080000; / { compatible = "socionext,uniphier-ld20"; @@ -79,35 +79,36 @@ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0 0x000>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x80000000>; + enable-method = "psci"; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0 0x001>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x80000000>; + enable-method = "psci"; }; cpu2: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x80000000>; + enable-method = "psci"; }; cpu3: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x80000000>; + enable-method = "psci"; }; }; + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + clocks { refclk: ref { compatible = "fixed-clock"; From 1ef64af81716c8191c11792a297371277ab86ef2 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 17 Oct 2016 00:42:42 +0900 Subject: [PATCH 2/5] arm64: dts: uniphier: increase register region size of sysctrl node The System Control node has 0x10000 byte of registers. The current reg size must be expanded to use the cpufreq driver because the registers controlling CPU frequency are located at offset 0x8000. Signed-off-by: Masahiro Yamada --- arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 2 +- arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi index 17bc4b359912..73e0acfd4f98 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi @@ -323,7 +323,7 @@ gic: interrupt-controller@5fe00000 { sysctrl@61840000 { compatible = "socionext,uniphier-ld11-sysctrl", "simple-mfd", "syscon"; - reg = <0x61840000 0x4000>; + reg = <0x61840000 0x10000>; sys_clk: clock { compatible = "socionext,uniphier-ld11-clock"; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index c8ebe7e52809..eaf260823084 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -312,7 +312,7 @@ gic: interrupt-controller@5fe00000 { sysctrl@61840000 { compatible = "socionext,uniphier-sysctrl", "simple-mfd", "syscon"; - reg = <0x61840000 0x4000>; + reg = <0x61840000 0x10000>; sys_clk: clock { compatible = "socionext,uniphier-ld20-clock"; From bdb8183681810672dd7344ad14d070a3c8cf7d14 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 20 Oct 2016 13:44:06 +0900 Subject: [PATCH 3/5] arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC Add a CPU clock to every CPU node and a CPU OPP table to use the generic cpufreq driver. Note: clock-latency-ns (300ns) was calculated based on the CPU-gear switch sequencer spec; it takes 12 clock cycles on the sequencer running at 50 MHz, plus a bit additional latency. Signed-off-by: Masahiro Yamada Acked-by: Viresh Kumar --- .../boot/dts/socionext/uniphier-ld11.dtsi | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi index 73e0acfd4f98..0e5c58f7624d 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi @@ -70,14 +70,52 @@ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x000>; + clocks = <&sys_clk 33>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x001>; + clocks = <&sys_clk 33>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp>; + }; + }; + + cluster0_opp: opp_table { + compatible = "operating-points-v2"; + opp-shared; + + opp@245000000 { + opp-hz = /bits/ 64 <245000000>; + clock-latency-ns = <300>; + }; + opp@250000000 { + opp-hz = /bits/ 64 <250000000>; + clock-latency-ns = <300>; + }; + opp@490000000 { + opp-hz = /bits/ 64 <490000000>; + clock-latency-ns = <300>; + }; + opp@500000000 { + opp-hz = /bits/ 64 <500000000>; + clock-latency-ns = <300>; + }; + opp@653334000 { + opp-hz = /bits/ 64 <653334000>; + clock-latency-ns = <300>; + }; + opp@666667000 { + opp-hz = /bits/ 64 <666667000>; + clock-latency-ns = <300>; + }; + opp@980000000 { + opp-hz = /bits/ 64 <980000000>; + clock-latency-ns = <300>; }; }; From 183ad3669f28e96e820c0fdf495927955b559662 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 20 Oct 2016 13:44:07 +0900 Subject: [PATCH 4/5] arm64: dts: uniphier: add CPU clocks and OPP tables for LD20 SoC Add a CPU clock to every CPU node and CPU OPP tables to use the generic cpufreq driver. All the CPUs in each cluster share the same OPP table. Note: clock-latency-ns (300ns) was calculated based on the CPU-gear switch sequencer spec; it takes 12 clock cycles on the sequencer running at 50 MHz, plus a bit additional latency. Signed-off-by: Masahiro Yamada Acked-by: Viresh Kumar --- .../boot/dts/socionext/uniphier-ld20.dtsi | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index eaf260823084..c6462563ad88 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -79,28 +79,112 @@ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0 0x000>; + clocks = <&sys_clk 32>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0 0x001>; + clocks = <&sys_clk 32>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x100>; + clocks = <&sys_clk 33>; enable-method = "psci"; + operating-points-v2 = <&cluster1_opp>; }; cpu3: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x101>; + clocks = <&sys_clk 33>; enable-method = "psci"; + operating-points-v2 = <&cluster1_opp>; + }; + }; + + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp@250000000 { + opp-hz = /bits/ 64 <250000000>; + clock-latency-ns = <300>; + }; + opp@275000000 { + opp-hz = /bits/ 64 <275000000>; + clock-latency-ns = <300>; + }; + opp@500000000 { + opp-hz = /bits/ 64 <500000000>; + clock-latency-ns = <300>; + }; + opp@550000000 { + opp-hz = /bits/ 64 <550000000>; + clock-latency-ns = <300>; + }; + opp@666667000 { + opp-hz = /bits/ 64 <666667000>; + clock-latency-ns = <300>; + }; + opp@733334000 { + opp-hz = /bits/ 64 <733334000>; + clock-latency-ns = <300>; + }; + opp@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + clock-latency-ns = <300>; + }; + opp@1100000000 { + opp-hz = /bits/ 64 <1100000000>; + clock-latency-ns = <300>; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp@250000000 { + opp-hz = /bits/ 64 <250000000>; + clock-latency-ns = <300>; + }; + opp@275000000 { + opp-hz = /bits/ 64 <275000000>; + clock-latency-ns = <300>; + }; + opp@500000000 { + opp-hz = /bits/ 64 <500000000>; + clock-latency-ns = <300>; + }; + opp@550000000 { + opp-hz = /bits/ 64 <550000000>; + clock-latency-ns = <300>; + }; + opp@666667000 { + opp-hz = /bits/ 64 <666667000>; + clock-latency-ns = <300>; + }; + opp@733334000 { + opp-hz = /bits/ 64 <733334000>; + clock-latency-ns = <300>; + }; + opp@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + clock-latency-ns = <300>; + }; + opp@1100000000 { + opp-hz = /bits/ 64 <1100000000>; + clock-latency-ns = <300>; }; }; From fb28cef06a9065748fbc6949dd7fca3c320c8e0d Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Sat, 5 Nov 2016 23:30:11 +0900 Subject: [PATCH 5/5] arm64: dts: uniphier: make compatible of syscon nodes SoC-specific These hardware blocks are SoC-specific, so their compatible strings should be SoC-specific as well. This change has no impact on the actual behavior since it is controlled by the generic "simple-mfd", "syscon" compatible strings. Signed-off-by: Masahiro Yamada --- arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 6 +++--- arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi index 0e5c58f7624d..7c7511b9d231 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi @@ -274,7 +274,7 @@ smpctrl@59800000 { }; perictrl@59820000 { - compatible = "socionext,uniphier-perictrl", + compatible = "socionext,uniphier-ld11-perictrl", "simple-mfd", "syscon"; reg = <0x59820000 0x200>; @@ -323,7 +323,7 @@ usb2: usb@5a820100 { }; mioctrl@5b3e0000 { - compatible = "socionext,uniphier-mioctrl", + compatible = "socionext,uniphier-ld11-mioctrl", "simple-mfd", "syscon"; reg = <0x5b3e0000 0x800>; @@ -340,7 +340,7 @@ mio_rst: reset { }; soc-glue@5f800000 { - compatible = "socionext,uniphier-soc-glue", + compatible = "socionext,uniphier-ld11-soc-glue", "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index c6462563ad88..fcaecc6bdeac 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -359,7 +359,7 @@ sd_rst: reset { }; perictrl@59820000 { - compatible = "socionext,uniphier-perictrl", + compatible = "socionext,uniphier-ld20-perictrl", "simple-mfd", "syscon"; reg = <0x59820000 0x200>; @@ -375,7 +375,7 @@ peri_rst: reset { }; soc-glue@5f800000 { - compatible = "socionext,uniphier-soc-glue", + compatible = "socionext,uniphier-ld20-soc-glue", "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; @@ -394,7 +394,7 @@ gic: interrupt-controller@5fe00000 { }; sysctrl@61840000 { - compatible = "socionext,uniphier-sysctrl", + compatible = "socionext,uniphier-ld20-sysctrl", "simple-mfd", "syscon"; reg = <0x61840000 0x10000>;