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arm64: dts: imx8dxl: add flexspi0 support

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Add flexspi0 node at common lsio subsystem.
Change flexspi0 irq number for imx8dxl.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Frank Li
2022-11-11 10:47:39 -05:00
committed by Shawn Guo
parent 7772c29d61
commit 6276d66984
2 changed files with 21 additions and 1 deletions
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17
arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
View File

@@ -11,7 +11,8 @@ lsio_subsys: bus@5d000000 {
compatible = "simple-bus"; compatible = "simple-bus";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; ranges = <0x5d000000 0x0 0x5d000000 0x1000000>,
<0x08000000 0x0 0x08000000 0x10000000>;
lsio_mem_clk: clock-lsio-mem { lsio_mem_clk: clock-lsio-mem {
compatible = "fixed-clock"; compatible = "fixed-clock";
@@ -107,6 +108,20 @@ lsio_gpio7: gpio@5d0f0000 {
power-domains = <&pd IMX_SC_R_GPIO_7>; power-domains = <&pd IMX_SC_R_GPIO_7>;
}; };
flexspi0: spi@5d120000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nxp,imx8qxp-fspi";
reg = <0x5d120000 0x10000>, <0x08000000 0x10000000>;
reg-names = "fspi_base", "fspi_mmap";
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>;
clock-names = "fspi", "fspi_en";
power-domains = <&pd IMX_SC_R_FSPI_0>;
status = "disabled";
};
lsio_mu0: mailbox@5d1b0000 { lsio_mu0: mailbox@5d1b0000 {
reg = <0x5d1b0000 0x10000>; reg = <0x5d1b0000 0x10000>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;

5
arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
View File

@@ -3,6 +3,11 @@
* Copyright 2019~2020, 2022 NXP * Copyright 2019~2020, 2022 NXP
*/ */
&flexspi0 {
compatible = "nxp,imx8dxl-fspi";
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
};
&lsio_gpio0 { &lsio_gpio0 {
compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;