From 5547ba1c0af0eeb0a37c0a51fe1bd0dcc4d0451c Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Wed, 10 Jun 2026 16:30:53 +0530 Subject: [PATCH 1/7] dt-bindings: PCI: qcom,pcie-ipq9574: Add IPQ9650 compatible Add the IPQ9650 PCIe compatible to the IPQ9574 binding, as the IPQ9650 controller is compatible with IPQ9574 and uses it as the fallback. While at it, make the global interrupt as required for IPQ9650. Signed-off-by: Kathiravan Thirumoorthy Signed-off-by: Manivannan Sadhasivam Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260610-ipq9650_pcie_binding-v2-1-69e27a1fbf1c@oss.qualcomm.com --- .../devicetree/bindings/pci/qcom,pcie-ipq9574.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ipq9574.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ipq9574.yaml index 4be342cc04e1..e92acddb969e 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ipq9574.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ipq9574.yaml @@ -19,6 +19,7 @@ properties: - enum: - qcom,pcie-ipq5332 - qcom,pcie-ipq5424 + - qcom,pcie-ipq9650 - const: qcom,pcie-ipq9574 reg: @@ -82,6 +83,18 @@ required: allOf: - $ref: qcom,pcie-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-ipq9650 + then: + properties: + interrupts: + minItems: 9 + interrupt-names: + minItems: 9 unevaluatedProperties: false From df045ed256f9b3a933466a1ff6903c75d4e5b629 Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Wed, 10 Jun 2026 16:30:54 +0530 Subject: [PATCH 2/7] dt-bindings: PCI: qcom,pcie-ipq9574: Add IPQ5210 compatible Add the IPQ5210 compatible using IPQ9574 as fallback. Signed-off-by: Varadarajan Narayanan Signed-off-by: Kathiravan Thirumoorthy [mani: commit log] Signed-off-by: Manivannan Sadhasivam Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260610-ipq9650_pcie_binding-v2-2-69e27a1fbf1c@oss.qualcomm.com --- Documentation/devicetree/bindings/pci/qcom,pcie-ipq9574.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ipq9574.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ipq9574.yaml index e92acddb969e..533079811881 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ipq9574.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ipq9574.yaml @@ -17,6 +17,7 @@ properties: - qcom,pcie-ipq9574 - items: - enum: + - qcom,pcie-ipq5210 - qcom,pcie-ipq5332 - qcom,pcie-ipq5424 - qcom,pcie-ipq9650 @@ -88,6 +89,7 @@ allOf: compatible: contains: enum: + - qcom,pcie-ipq5210 - qcom,pcie-ipq9650 then: properties: From d71376622c459f57e5dd86c7d5bb505b664faa37 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Thu, 18 Jun 2026 17:20:58 +0800 Subject: [PATCH 3/7] dt-bindings: PCI: imx6q-pcie: Add i.MX95 optional intr/aer/pme interrupts The i.MX95 PCIe controller introduces three additional dedicated hardware interrupt lines for specific events: - intr: general controller events - aer: Advanced Error Reporting events - pme: Power Management Events These interrupts are optional on i.MX95. PCIe basic functionality (enumeration, configuration, and data transfer) works correctly without them, as the controller can operate using only the existing MSI interrupt. Earlier i.MX PCIe variants (imx6q, imx6sx, imx6qp, imx7d, imx8mm, imx8mp, imx8mq, imx8q) do not have these three dedicated interrupt lines. Update the binding to allow up to 5 interrupts for i.MX95, while restricting earlier variants to a maximum of 2 interrupts using conditional constraints (if/then schema). This ensures the schema accurately reflects the hardware capabilities of each SoC variant. Signed-off-by: Richard Zhu Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Helgaas Reviewed-by: Frank Li Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260618092100.3669556-2-hongxing.zhu@oss.nxp.com --- .../bindings/pci/fsl,imx6q-pcie.yaml | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index e8b8131f5f23..4f56e8e4f100 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -58,12 +58,18 @@ properties: items: - description: builtin MSI controller. - description: builtin DMA controller. + - description: PCIe event interrupt. + - description: builtin AER SPI standalone interrupt line. + - description: builtin PME SPI standalone interrupt line. interrupt-names: minItems: 1 items: - const: msi - const: dma + - const: intr + - const: aer + - const: pme reset-gpio: deprecated: true @@ -249,6 +255,25 @@ allOf: - const: ref - const: extref # Optional + - if: + properties: + compatible: + enum: + - fsl,imx6q-pcie + - fsl,imx6sx-pcie + - fsl,imx6qp-pcie + - fsl,imx7d-pcie + - fsl,imx8mm-pcie + - fsl,imx8mp-pcie + - fsl,imx8mq-pcie + - fsl,imx8q-pcie + then: + properties: + interrupts: + maxItems: 2 + interrupt-names: + maxItems: 2 + unevaluatedProperties: false examples: From 068601b547da091d9f56131cbb25e40ad40f4825 Mon Sep 17 00:00:00 2001 From: Louis-Alexis Eyraud Date: Wed, 1 Jul 2026 17:27:36 +0200 Subject: [PATCH 4/7] dt-bindings: PCI: mediatek-gen3: Add support for MT8189 SoC Add compatible for MT8189 PCIe Gen3 controller, that is compatible with the PCIe controller found in MT8192. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: Manivannan Sadhasivam Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260701-mt8189-dt-bindings-pcie-v1-1-7c7a65087654@collabora.com --- Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml index 4db700fc36ba..fbc0378392d4 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -51,6 +51,7 @@ properties: - mediatek,mt7981-pcie - mediatek,mt7986-pcie - mediatek,mt8188-pcie + - mediatek,mt8189-pcie - mediatek,mt8195-pcie - const: mediatek,mt8192-pcie - items: @@ -193,6 +194,7 @@ allOf: contains: enum: - mediatek,mt8188-pcie + - mediatek,mt8189-pcie - mediatek,mt8195-pcie then: properties: From 7e38b7b0e0e582024e97289a3b63c201f226124d Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 20 Jul 2026 17:21:15 +0800 Subject: [PATCH 5/7] dt-bindings: PCI: mediatek-gen3: Allow memory-region for restricted DMA buffer On some SoCs without an IOMMU behind the PCIe controller, the PCIe controller memory access could be limited to a small region by the firmware configuring a memory protection unit. This memory region must be assigned to the PCIe controller so that the OS knows to use that region. Otherwise PCIe devices would not work properly. Allow the memory-region property with one item pointing to a restricted DMA buffer. Signed-off-by: Chen-Yu Tsai Signed-off-by: Manivannan Sadhasivam Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260720092116.1823562-1-wenst@chromium.org --- Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml index fbc0378392d4..b88717dec1fa 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -116,6 +116,10 @@ properties: power-domains: maxItems: 1 + memory-region: + maxItems: 1 + description: phandle to restricted DMA buffer + mediatek,pbus-csr: $ref: /schemas/types.yaml#/definitions/phandle-array items: From 8ba87bf6edbd601d0bf5ee515d0fff77b5585a2e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 20 Jul 2026 03:54:41 +0200 Subject: [PATCH 6/7] dt-bindings: PCI: rcar-gen4-pci-host: Document optional msi-parent The R-Car Gen4 PCIe controller can optionally use GIC ITS as an MSI controller. This configuration is described in DT by setting msi-parent DT property in the PCIe controller node. Document this configuration. Signed-off-by: Marek Vasut Signed-off-by: Manivannan Sadhasivam Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260720015505.314957-1-marek.vasut+renesas@mailbox.org --- Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml index bb3f843c59d9..64f456c6a75a 100644 --- a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml @@ -66,6 +66,9 @@ properties: max-link-speed: maximum: 4 + msi-parent: + maxItems: 1 + num-lanes: maximum: 4 From f7b2ceb411479b4c95aee1c0dd720af53367ff8b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 1 Aug 2026 21:55:18 +0200 Subject: [PATCH 7/7] dt-bindings: PCI: Correct white-space style Correct a few white-space issues, like double space after '=' or before bracket '{' characters, which will be flagged by dt-check-style. No functional changes. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam Reviewed-by: Marek Vasut Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260801195517.235161-2-krzysztof.kozlowski@oss.qualcomm.com --- .../devicetree/bindings/pci/brcm,stb-pcie.yaml | 2 +- .../bindings/pci/renesas,pci-rcar-gen2.yaml | 2 +- .../devicetree/bindings/pci/ti,am65-pci-ep.yaml | 8 ++++---- .../devicetree/bindings/pci/ti,am65-pci-host.yaml | 12 ++++++------ 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index 812ef5957cfc..328b8156cd94 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -214,7 +214,7 @@ examples: dma-ranges = <0x42000000 0x1 0x00000000 0x0 0x40000000 0x0 0x80000000>, <0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>; brcm,enable-ssc; - brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>; + brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>; /* PCIe bridge, Root Port */ pci@0,0 { diff --git a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml index 065b7508d288..1f0ab9ccd1dd 100644 --- a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml +++ b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml @@ -155,7 +155,7 @@ examples: #include #include - pci@ee090000 { + pci@ee090000 { compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2"; device_type = "pci"; reg = <0xee090000 0xc00>, diff --git a/Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml index 74195c1f5292..afde18c5a4fa 100644 --- a/Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml @@ -63,10 +63,10 @@ examples: pcie0_ep: pcie-ep@5500000 { compatible = "ti,am654-pcie-ep"; - reg = <0x5500000 0x1000>, - <0x5501000 0x1000>, - <0x10000000 0x8000000>, - <0x5506000 0x1000>; + reg = <0x5500000 0x1000>, + <0x5501000 0x1000>, + <0x10000000 0x8000000>, + <0x5506000 0x1000>; reg-names = "app", "dbics", "addr_space", "atu"; power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; ti,syscon-pcie-mode = <&scm_conf 0x4060>; diff --git a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml index 98f6c7f1b1a6..db92125a2f2d 100644 --- a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml @@ -121,12 +121,12 @@ examples: pcie0_rc: pcie@5500000 { compatible = "ti,am654-pcie-rc"; - reg = <0x5500000 0x1000>, - <0x5501000 0x1000>, - <0x10000000 0x2000>, - <0x5506000 0x1000>, - <0x2900000 0x1000>, - <0x2908000 0x1000>; + reg = <0x5500000 0x1000>, + <0x5501000 0x1000>, + <0x10000000 0x2000>, + <0x5506000 0x1000>, + <0x2900000 0x1000>, + <0x2908000 0x1000>; reg-names = "app", "dbics", "config", "atu", "vmap_lp", "vmap_hp"; power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; #address-cells = <3>;